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1/*
2 * Copyright © 2008-2015 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 *
26 */
27
28#include <linux/dma-fence-array.h>
29#include <linux/kthread.h>
30#include <linux/dma-resv.h>
31#include <linux/shmem_fs.h>
32#include <linux/slab.h>
33#include <linux/stop_machine.h>
34#include <linux/swap.h>
35#include <linux/pci.h>
36#include <linux/dma-buf.h>
37#include <linux/mman.h>
38
39#include <drm/drm_cache.h>
40#include <drm/drm_vma_manager.h>
41
42#include "gem/i915_gem_clflush.h"
43#include "gem/i915_gem_context.h"
44#include "gem/i915_gem_ioctls.h"
45#include "gem/i915_gem_mman.h"
46#include "gem/i915_gem_object_frontbuffer.h"
47#include "gem/i915_gem_pm.h"
48#include "gem/i915_gem_region.h"
49#include "gt/intel_engine_user.h"
50#include "gt/intel_gt.h"
51#include "gt/intel_gt_pm.h"
52#include "gt/intel_workarounds.h"
53
54#include "i915_drv.h"
55#include "i915_file_private.h"
56#include "i915_trace.h"
57#include "i915_vgpu.h"
58#include "intel_clock_gating.h"
59
60static int
61insert_mappable_node(struct i915_ggtt *ggtt, struct drm_mm_node *node, u32 size)
62{
63 int err;
64
65 err = mutex_lock_interruptible(&ggtt->vm.mutex);
66 if (err)
67 return err;
68
69 memset(node, 0, sizeof(*node));
70 err = drm_mm_insert_node_in_range(&ggtt->vm.mm, node,
71 size, 0, I915_COLOR_UNEVICTABLE,
72 0, ggtt->mappable_end,
73 DRM_MM_INSERT_LOW);
74
75 mutex_unlock(&ggtt->vm.mutex);
76
77 return err;
78}
79
80static void
81remove_mappable_node(struct i915_ggtt *ggtt, struct drm_mm_node *node)
82{
83 mutex_lock(&ggtt->vm.mutex);
84 drm_mm_remove_node(node);
85 mutex_unlock(&ggtt->vm.mutex);
86}
87
88int
89i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
90 struct drm_file *file)
91{
92 struct drm_i915_private *i915 = to_i915(dev);
93 struct i915_ggtt *ggtt = to_gt(i915)->ggtt;
94 struct drm_i915_gem_get_aperture *args = data;
95 struct i915_vma *vma;
96 u64 pinned;
97
98 if (mutex_lock_interruptible(&ggtt->vm.mutex))
99 return -EINTR;
100
101 pinned = ggtt->vm.reserved;
102 list_for_each_entry(vma, &ggtt->vm.bound_list, vm_link)
103 if (i915_vma_is_pinned(vma))
104 pinned += vma->node.size;
105
106 mutex_unlock(&ggtt->vm.mutex);
107
108 args->aper_size = ggtt->vm.total;
109 args->aper_available_size = args->aper_size - pinned;
110
111 return 0;
112}
113
114int i915_gem_object_unbind(struct drm_i915_gem_object *obj,
115 unsigned long flags)
116{
117 struct intel_runtime_pm *rpm = &to_i915(obj->base.dev)->runtime_pm;
118 bool vm_trylock = !!(flags & I915_GEM_OBJECT_UNBIND_VM_TRYLOCK);
119 LIST_HEAD(still_in_list);
120 intel_wakeref_t wakeref;
121 struct i915_vma *vma;
122 int ret;
123
124 assert_object_held(obj);
125
126 if (list_empty(&obj->vma.list))
127 return 0;
128
129 /*
130 * As some machines use ACPI to handle runtime-resume callbacks, and
131 * ACPI is quite kmalloc happy, we cannot resume beneath the vm->mutex
132 * as they are required by the shrinker. Ergo, we wake the device up
133 * first just in case.
134 */
135 wakeref = intel_runtime_pm_get(rpm);
136
137try_again:
138 ret = 0;
139 spin_lock(&obj->vma.lock);
140 while (!ret && (vma = list_first_entry_or_null(&obj->vma.list,
141 struct i915_vma,
142 obj_link))) {
143 list_move_tail(&vma->obj_link, &still_in_list);
144 if (!i915_vma_is_bound(vma, I915_VMA_BIND_MASK))
145 continue;
146
147 if (flags & I915_GEM_OBJECT_UNBIND_TEST) {
148 ret = -EBUSY;
149 break;
150 }
151
152 /*
153 * Requiring the vm destructor to take the object lock
154 * before destroying a vma would help us eliminate the
155 * i915_vm_tryget() here, AND thus also the barrier stuff
156 * at the end. That's an easy fix, but sleeping locks in
157 * a kthread should generally be avoided.
158 */
159 ret = -EAGAIN;
160 if (!i915_vm_tryget(vma->vm))
161 break;
162
163 spin_unlock(&obj->vma.lock);
164
165 /*
166 * Since i915_vma_parked() takes the object lock
167 * before vma destruction, it won't race us here,
168 * and destroy the vma from under us.
169 */
170
171 ret = -EBUSY;
172 if (flags & I915_GEM_OBJECT_UNBIND_ASYNC) {
173 assert_object_held(vma->obj);
174 ret = i915_vma_unbind_async(vma, vm_trylock);
175 }
176
177 if (ret == -EBUSY && (flags & I915_GEM_OBJECT_UNBIND_ACTIVE ||
178 !i915_vma_is_active(vma))) {
179 if (vm_trylock) {
180 if (mutex_trylock(&vma->vm->mutex)) {
181 ret = __i915_vma_unbind(vma);
182 mutex_unlock(&vma->vm->mutex);
183 }
184 } else {
185 ret = i915_vma_unbind(vma);
186 }
187 }
188
189 i915_vm_put(vma->vm);
190 spin_lock(&obj->vma.lock);
191 }
192 list_splice_init(&still_in_list, &obj->vma.list);
193 spin_unlock(&obj->vma.lock);
194
195 if (ret == -EAGAIN && flags & I915_GEM_OBJECT_UNBIND_BARRIER) {
196 rcu_barrier(); /* flush the i915_vm_release() */
197 goto try_again;
198 }
199
200 intel_runtime_pm_put(rpm, wakeref);
201
202 return ret;
203}
204
205static int
206shmem_pread(struct page *page, int offset, int len, char __user *user_data,
207 bool needs_clflush)
208{
209 char *vaddr;
210 int ret;
211
212 vaddr = kmap(page);
213
214 if (needs_clflush)
215 drm_clflush_virt_range(vaddr + offset, len);
216
217 ret = __copy_to_user(user_data, vaddr + offset, len);
218
219 kunmap(page);
220
221 return ret ? -EFAULT : 0;
222}
223
224static int
225i915_gem_shmem_pread(struct drm_i915_gem_object *obj,
226 struct drm_i915_gem_pread *args)
227{
228 unsigned int needs_clflush;
229 char __user *user_data;
230 unsigned long offset;
231 pgoff_t idx;
232 u64 remain;
233 int ret;
234
235 ret = i915_gem_object_lock_interruptible(obj, NULL);
236 if (ret)
237 return ret;
238
239 ret = i915_gem_object_pin_pages(obj);
240 if (ret)
241 goto err_unlock;
242
243 ret = i915_gem_object_prepare_read(obj, &needs_clflush);
244 if (ret)
245 goto err_unpin;
246
247 i915_gem_object_finish_access(obj);
248 i915_gem_object_unlock(obj);
249
250 remain = args->size;
251 user_data = u64_to_user_ptr(args->data_ptr);
252 offset = offset_in_page(args->offset);
253 for (idx = args->offset >> PAGE_SHIFT; remain; idx++) {
254 struct page *page = i915_gem_object_get_page(obj, idx);
255 unsigned int length = min_t(u64, remain, PAGE_SIZE - offset);
256
257 ret = shmem_pread(page, offset, length, user_data,
258 needs_clflush);
259 if (ret)
260 break;
261
262 remain -= length;
263 user_data += length;
264 offset = 0;
265 }
266
267 i915_gem_object_unpin_pages(obj);
268 return ret;
269
270err_unpin:
271 i915_gem_object_unpin_pages(obj);
272err_unlock:
273 i915_gem_object_unlock(obj);
274 return ret;
275}
276
277static inline bool
278gtt_user_read(struct io_mapping *mapping,
279 loff_t base, int offset,
280 char __user *user_data, int length)
281{
282 void __iomem *vaddr;
283 unsigned long unwritten;
284
285 /* We can use the cpu mem copy function because this is X86. */
286 vaddr = io_mapping_map_atomic_wc(mapping, base);
287 unwritten = __copy_to_user_inatomic(user_data,
288 (void __force *)vaddr + offset,
289 length);
290 io_mapping_unmap_atomic(vaddr);
291 if (unwritten) {
292 vaddr = io_mapping_map_wc(mapping, base, PAGE_SIZE);
293 unwritten = copy_to_user(user_data,
294 (void __force *)vaddr + offset,
295 length);
296 io_mapping_unmap(vaddr);
297 }
298 return unwritten;
299}
300
301static struct i915_vma *i915_gem_gtt_prepare(struct drm_i915_gem_object *obj,
302 struct drm_mm_node *node,
303 bool write)
304{
305 struct drm_i915_private *i915 = to_i915(obj->base.dev);
306 struct i915_ggtt *ggtt = to_gt(i915)->ggtt;
307 struct i915_vma *vma;
308 struct i915_gem_ww_ctx ww;
309 int ret;
310
311 i915_gem_ww_ctx_init(&ww, true);
312retry:
313 vma = ERR_PTR(-ENODEV);
314 ret = i915_gem_object_lock(obj, &ww);
315 if (ret)
316 goto err_ww;
317
318 ret = i915_gem_object_set_to_gtt_domain(obj, write);
319 if (ret)
320 goto err_ww;
321
322 if (!i915_gem_object_is_tiled(obj))
323 vma = i915_gem_object_ggtt_pin_ww(obj, &ww, NULL, 0, 0,
324 PIN_MAPPABLE |
325 PIN_NONBLOCK /* NOWARN */ |
326 PIN_NOEVICT);
327 if (vma == ERR_PTR(-EDEADLK)) {
328 ret = -EDEADLK;
329 goto err_ww;
330 } else if (!IS_ERR(vma)) {
331 node->start = i915_ggtt_offset(vma);
332 node->flags = 0;
333 } else {
334 ret = insert_mappable_node(ggtt, node, PAGE_SIZE);
335 if (ret)
336 goto err_ww;
337 GEM_BUG_ON(!drm_mm_node_allocated(node));
338 vma = NULL;
339 }
340
341 ret = i915_gem_object_pin_pages(obj);
342 if (ret) {
343 if (drm_mm_node_allocated(node)) {
344 ggtt->vm.clear_range(&ggtt->vm, node->start, node->size);
345 remove_mappable_node(ggtt, node);
346 } else {
347 i915_vma_unpin(vma);
348 }
349 }
350
351err_ww:
352 if (ret == -EDEADLK) {
353 ret = i915_gem_ww_ctx_backoff(&ww);
354 if (!ret)
355 goto retry;
356 }
357 i915_gem_ww_ctx_fini(&ww);
358
359 return ret ? ERR_PTR(ret) : vma;
360}
361
362static void i915_gem_gtt_cleanup(struct drm_i915_gem_object *obj,
363 struct drm_mm_node *node,
364 struct i915_vma *vma)
365{
366 struct drm_i915_private *i915 = to_i915(obj->base.dev);
367 struct i915_ggtt *ggtt = to_gt(i915)->ggtt;
368
369 i915_gem_object_unpin_pages(obj);
370 if (drm_mm_node_allocated(node)) {
371 ggtt->vm.clear_range(&ggtt->vm, node->start, node->size);
372 remove_mappable_node(ggtt, node);
373 } else {
374 i915_vma_unpin(vma);
375 }
376}
377
378static int
379i915_gem_gtt_pread(struct drm_i915_gem_object *obj,
380 const struct drm_i915_gem_pread *args)
381{
382 struct drm_i915_private *i915 = to_i915(obj->base.dev);
383 struct i915_ggtt *ggtt = to_gt(i915)->ggtt;
384 unsigned long remain, offset;
385 intel_wakeref_t wakeref;
386 struct drm_mm_node node;
387 void __user *user_data;
388 struct i915_vma *vma;
389 int ret = 0;
390
391 if (overflows_type(args->size, remain) ||
392 overflows_type(args->offset, offset))
393 return -EINVAL;
394
395 wakeref = intel_runtime_pm_get(&i915->runtime_pm);
396
397 vma = i915_gem_gtt_prepare(obj, &node, false);
398 if (IS_ERR(vma)) {
399 ret = PTR_ERR(vma);
400 goto out_rpm;
401 }
402
403 user_data = u64_to_user_ptr(args->data_ptr);
404 remain = args->size;
405 offset = args->offset;
406
407 while (remain > 0) {
408 /* Operation in this page
409 *
410 * page_base = page offset within aperture
411 * page_offset = offset within page
412 * page_length = bytes to copy for this page
413 */
414 u32 page_base = node.start;
415 unsigned page_offset = offset_in_page(offset);
416 unsigned page_length = PAGE_SIZE - page_offset;
417 page_length = remain < page_length ? remain : page_length;
418 if (drm_mm_node_allocated(&node)) {
419 ggtt->vm.insert_page(&ggtt->vm,
420 i915_gem_object_get_dma_address(obj,
421 offset >> PAGE_SHIFT),
422 node.start,
423 i915_gem_get_pat_index(i915,
424 I915_CACHE_NONE), 0);
425 } else {
426 page_base += offset & PAGE_MASK;
427 }
428
429 if (gtt_user_read(&ggtt->iomap, page_base, page_offset,
430 user_data, page_length)) {
431 ret = -EFAULT;
432 break;
433 }
434
435 remain -= page_length;
436 user_data += page_length;
437 offset += page_length;
438 }
439
440 i915_gem_gtt_cleanup(obj, &node, vma);
441out_rpm:
442 intel_runtime_pm_put(&i915->runtime_pm, wakeref);
443 return ret;
444}
445
446/**
447 * i915_gem_pread_ioctl - Reads data from the object referenced by handle.
448 * @dev: drm device pointer
449 * @data: ioctl data blob
450 * @file: drm file pointer
451 *
452 * On error, the contents of *data are undefined.
453 */
454int
455i915_gem_pread_ioctl(struct drm_device *dev, void *data,
456 struct drm_file *file)
457{
458 struct drm_i915_private *i915 = to_i915(dev);
459 struct drm_i915_gem_pread *args = data;
460 struct drm_i915_gem_object *obj;
461 int ret;
462
463 /* PREAD is disallowed for all platforms after TGL-LP. This also
464 * covers all platforms with local memory.
465 */
466 if (GRAPHICS_VER(i915) >= 12 && !IS_TIGERLAKE(i915))
467 return -EOPNOTSUPP;
468
469 if (args->size == 0)
470 return 0;
471
472 if (!access_ok(u64_to_user_ptr(args->data_ptr),
473 args->size))
474 return -EFAULT;
475
476 obj = i915_gem_object_lookup(file, args->handle);
477 if (!obj)
478 return -ENOENT;
479
480 /* Bounds check source. */
481 if (range_overflows_t(u64, args->offset, args->size, obj->base.size)) {
482 ret = -EINVAL;
483 goto out;
484 }
485
486 trace_i915_gem_object_pread(obj, args->offset, args->size);
487 ret = -ENODEV;
488 if (obj->ops->pread)
489 ret = obj->ops->pread(obj, args);
490 if (ret != -ENODEV)
491 goto out;
492
493 ret = i915_gem_object_wait(obj,
494 I915_WAIT_INTERRUPTIBLE,
495 MAX_SCHEDULE_TIMEOUT);
496 if (ret)
497 goto out;
498
499 ret = i915_gem_shmem_pread(obj, args);
500 if (ret == -EFAULT || ret == -ENODEV)
501 ret = i915_gem_gtt_pread(obj, args);
502
503out:
504 i915_gem_object_put(obj);
505 return ret;
506}
507
508/* This is the fast write path which cannot handle
509 * page faults in the source data
510 */
511
512static inline bool
513ggtt_write(struct io_mapping *mapping,
514 loff_t base, int offset,
515 char __user *user_data, int length)
516{
517 void __iomem *vaddr;
518 unsigned long unwritten;
519
520 /* We can use the cpu mem copy function because this is X86. */
521 vaddr = io_mapping_map_atomic_wc(mapping, base);
522 unwritten = __copy_from_user_inatomic_nocache((void __force *)vaddr + offset,
523 user_data, length);
524 io_mapping_unmap_atomic(vaddr);
525 if (unwritten) {
526 vaddr = io_mapping_map_wc(mapping, base, PAGE_SIZE);
527 unwritten = copy_from_user((void __force *)vaddr + offset,
528 user_data, length);
529 io_mapping_unmap(vaddr);
530 }
531
532 return unwritten;
533}
534
535/**
536 * i915_gem_gtt_pwrite_fast - This is the fast pwrite path, where we copy the data directly from the
537 * user into the GTT, uncached.
538 * @obj: i915 GEM object
539 * @args: pwrite arguments structure
540 */
541static int
542i915_gem_gtt_pwrite_fast(struct drm_i915_gem_object *obj,
543 const struct drm_i915_gem_pwrite *args)
544{
545 struct drm_i915_private *i915 = to_i915(obj->base.dev);
546 struct i915_ggtt *ggtt = to_gt(i915)->ggtt;
547 struct intel_runtime_pm *rpm = &i915->runtime_pm;
548 unsigned long remain, offset;
549 intel_wakeref_t wakeref;
550 struct drm_mm_node node;
551 struct i915_vma *vma;
552 void __user *user_data;
553 int ret = 0;
554
555 if (overflows_type(args->size, remain) ||
556 overflows_type(args->offset, offset))
557 return -EINVAL;
558
559 if (i915_gem_object_has_struct_page(obj)) {
560 /*
561 * Avoid waking the device up if we can fallback, as
562 * waking/resuming is very slow (worst-case 10-100 ms
563 * depending on PCI sleeps and our own resume time).
564 * This easily dwarfs any performance advantage from
565 * using the cache bypass of indirect GGTT access.
566 */
567 wakeref = intel_runtime_pm_get_if_in_use(rpm);
568 if (!wakeref)
569 return -EFAULT;
570 } else {
571 /* No backing pages, no fallback, we must force GGTT access */
572 wakeref = intel_runtime_pm_get(rpm);
573 }
574
575 vma = i915_gem_gtt_prepare(obj, &node, true);
576 if (IS_ERR(vma)) {
577 ret = PTR_ERR(vma);
578 goto out_rpm;
579 }
580
581 i915_gem_object_invalidate_frontbuffer(obj, ORIGIN_CPU);
582
583 user_data = u64_to_user_ptr(args->data_ptr);
584 offset = args->offset;
585 remain = args->size;
586 while (remain) {
587 /* Operation in this page
588 *
589 * page_base = page offset within aperture
590 * page_offset = offset within page
591 * page_length = bytes to copy for this page
592 */
593 u32 page_base = node.start;
594 unsigned int page_offset = offset_in_page(offset);
595 unsigned int page_length = PAGE_SIZE - page_offset;
596 page_length = remain < page_length ? remain : page_length;
597 if (drm_mm_node_allocated(&node)) {
598 /* flush the write before we modify the GGTT */
599 intel_gt_flush_ggtt_writes(ggtt->vm.gt);
600 ggtt->vm.insert_page(&ggtt->vm,
601 i915_gem_object_get_dma_address(obj,
602 offset >> PAGE_SHIFT),
603 node.start,
604 i915_gem_get_pat_index(i915,
605 I915_CACHE_NONE), 0);
606 wmb(); /* flush modifications to the GGTT (insert_page) */
607 } else {
608 page_base += offset & PAGE_MASK;
609 }
610 /* If we get a fault while copying data, then (presumably) our
611 * source page isn't available. Return the error and we'll
612 * retry in the slow path.
613 * If the object is non-shmem backed, we retry again with the
614 * path that handles page fault.
615 */
616 if (ggtt_write(&ggtt->iomap, page_base, page_offset,
617 user_data, page_length)) {
618 ret = -EFAULT;
619 break;
620 }
621
622 remain -= page_length;
623 user_data += page_length;
624 offset += page_length;
625 }
626
627 intel_gt_flush_ggtt_writes(ggtt->vm.gt);
628 i915_gem_object_flush_frontbuffer(obj, ORIGIN_CPU);
629
630 i915_gem_gtt_cleanup(obj, &node, vma);
631out_rpm:
632 intel_runtime_pm_put(rpm, wakeref);
633 return ret;
634}
635
636/* Per-page copy function for the shmem pwrite fastpath.
637 * Flushes invalid cachelines before writing to the target if
638 * needs_clflush_before is set and flushes out any written cachelines after
639 * writing if needs_clflush is set.
640 */
641static int
642shmem_pwrite(struct page *page, int offset, int len, char __user *user_data,
643 bool needs_clflush_before,
644 bool needs_clflush_after)
645{
646 char *vaddr;
647 int ret;
648
649 vaddr = kmap(page);
650
651 if (needs_clflush_before)
652 drm_clflush_virt_range(vaddr + offset, len);
653
654 ret = __copy_from_user(vaddr + offset, user_data, len);
655 if (!ret && needs_clflush_after)
656 drm_clflush_virt_range(vaddr + offset, len);
657
658 kunmap(page);
659
660 return ret ? -EFAULT : 0;
661}
662
663static int
664i915_gem_shmem_pwrite(struct drm_i915_gem_object *obj,
665 const struct drm_i915_gem_pwrite *args)
666{
667 unsigned int partial_cacheline_write;
668 unsigned int needs_clflush;
669 void __user *user_data;
670 unsigned long offset;
671 pgoff_t idx;
672 u64 remain;
673 int ret;
674
675 ret = i915_gem_object_lock_interruptible(obj, NULL);
676 if (ret)
677 return ret;
678
679 ret = i915_gem_object_pin_pages(obj);
680 if (ret)
681 goto err_unlock;
682
683 ret = i915_gem_object_prepare_write(obj, &needs_clflush);
684 if (ret)
685 goto err_unpin;
686
687 i915_gem_object_finish_access(obj);
688 i915_gem_object_unlock(obj);
689
690 /* If we don't overwrite a cacheline completely we need to be
691 * careful to have up-to-date data by first clflushing. Don't
692 * overcomplicate things and flush the entire patch.
693 */
694 partial_cacheline_write = 0;
695 if (needs_clflush & CLFLUSH_BEFORE)
696 partial_cacheline_write = boot_cpu_data.x86_clflush_size - 1;
697
698 user_data = u64_to_user_ptr(args->data_ptr);
699 remain = args->size;
700 offset = offset_in_page(args->offset);
701 for (idx = args->offset >> PAGE_SHIFT; remain; idx++) {
702 struct page *page = i915_gem_object_get_page(obj, idx);
703 unsigned int length = min_t(u64, remain, PAGE_SIZE - offset);
704
705 ret = shmem_pwrite(page, offset, length, user_data,
706 (offset | length) & partial_cacheline_write,
707 needs_clflush & CLFLUSH_AFTER);
708 if (ret)
709 break;
710
711 remain -= length;
712 user_data += length;
713 offset = 0;
714 }
715
716 i915_gem_object_flush_frontbuffer(obj, ORIGIN_CPU);
717
718 i915_gem_object_unpin_pages(obj);
719 return ret;
720
721err_unpin:
722 i915_gem_object_unpin_pages(obj);
723err_unlock:
724 i915_gem_object_unlock(obj);
725 return ret;
726}
727
728/**
729 * i915_gem_pwrite_ioctl - Writes data to the object referenced by handle.
730 * @dev: drm device
731 * @data: ioctl data blob
732 * @file: drm file
733 *
734 * On error, the contents of the buffer that were to be modified are undefined.
735 */
736int
737i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
738 struct drm_file *file)
739{
740 struct drm_i915_private *i915 = to_i915(dev);
741 struct drm_i915_gem_pwrite *args = data;
742 struct drm_i915_gem_object *obj;
743 int ret;
744
745 /* PWRITE is disallowed for all platforms after TGL-LP. This also
746 * covers all platforms with local memory.
747 */
748 if (GRAPHICS_VER(i915) >= 12 && !IS_TIGERLAKE(i915))
749 return -EOPNOTSUPP;
750
751 if (args->size == 0)
752 return 0;
753
754 if (!access_ok(u64_to_user_ptr(args->data_ptr), args->size))
755 return -EFAULT;
756
757 obj = i915_gem_object_lookup(file, args->handle);
758 if (!obj)
759 return -ENOENT;
760
761 /* Bounds check destination. */
762 if (range_overflows_t(u64, args->offset, args->size, obj->base.size)) {
763 ret = -EINVAL;
764 goto err;
765 }
766
767 /* Writes not allowed into this read-only object */
768 if (i915_gem_object_is_readonly(obj)) {
769 ret = -EINVAL;
770 goto err;
771 }
772
773 trace_i915_gem_object_pwrite(obj, args->offset, args->size);
774
775 ret = -ENODEV;
776 if (obj->ops->pwrite)
777 ret = obj->ops->pwrite(obj, args);
778 if (ret != -ENODEV)
779 goto err;
780
781 ret = i915_gem_object_wait(obj,
782 I915_WAIT_INTERRUPTIBLE |
783 I915_WAIT_ALL,
784 MAX_SCHEDULE_TIMEOUT);
785 if (ret)
786 goto err;
787
788 ret = -EFAULT;
789 /* We can only do the GTT pwrite on untiled buffers, as otherwise
790 * it would end up going through the fenced access, and we'll get
791 * different detiling behavior between reading and writing.
792 * pread/pwrite currently are reading and writing from the CPU
793 * perspective, requiring manual detiling by the client.
794 */
795 if (!i915_gem_object_has_struct_page(obj) ||
796 i915_gem_cpu_write_needs_clflush(obj))
797 /* Note that the gtt paths might fail with non-page-backed user
798 * pointers (e.g. gtt mappings when moving data between
799 * textures). Fallback to the shmem path in that case.
800 */
801 ret = i915_gem_gtt_pwrite_fast(obj, args);
802
803 if (ret == -EFAULT || ret == -ENOSPC) {
804 if (i915_gem_object_has_struct_page(obj))
805 ret = i915_gem_shmem_pwrite(obj, args);
806 }
807
808err:
809 i915_gem_object_put(obj);
810 return ret;
811}
812
813/**
814 * i915_gem_sw_finish_ioctl - Called when user space has done writes to this buffer
815 * @dev: drm device
816 * @data: ioctl data blob
817 * @file: drm file
818 */
819int
820i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
821 struct drm_file *file)
822{
823 struct drm_i915_gem_sw_finish *args = data;
824 struct drm_i915_gem_object *obj;
825
826 obj = i915_gem_object_lookup(file, args->handle);
827 if (!obj)
828 return -ENOENT;
829
830 /*
831 * Proxy objects are barred from CPU access, so there is no
832 * need to ban sw_finish as it is a nop.
833 */
834
835 /* Pinned buffers may be scanout, so flush the cache */
836 i915_gem_object_flush_if_display(obj);
837 i915_gem_object_put(obj);
838
839 return 0;
840}
841
842void i915_gem_runtime_suspend(struct drm_i915_private *i915)
843{
844 struct drm_i915_gem_object *obj, *on;
845 int i;
846
847 /*
848 * Only called during RPM suspend. All users of the userfault_list
849 * must be holding an RPM wakeref to ensure that this can not
850 * run concurrently with themselves (and use the struct_mutex for
851 * protection between themselves).
852 */
853
854 list_for_each_entry_safe(obj, on,
855 &to_gt(i915)->ggtt->userfault_list, userfault_link)
856 __i915_gem_object_release_mmap_gtt(obj);
857
858 list_for_each_entry_safe(obj, on,
859 &i915->runtime_pm.lmem_userfault_list, userfault_link)
860 i915_gem_object_runtime_pm_release_mmap_offset(obj);
861
862 /*
863 * The fence will be lost when the device powers down. If any were
864 * in use by hardware (i.e. they are pinned), we should not be powering
865 * down! All other fences will be reacquired by the user upon waking.
866 */
867 for (i = 0; i < to_gt(i915)->ggtt->num_fences; i++) {
868 struct i915_fence_reg *reg = &to_gt(i915)->ggtt->fence_regs[i];
869
870 /*
871 * Ideally we want to assert that the fence register is not
872 * live at this point (i.e. that no piece of code will be
873 * trying to write through fence + GTT, as that both violates
874 * our tracking of activity and associated locking/barriers,
875 * but also is illegal given that the hw is powered down).
876 *
877 * Previously we used reg->pin_count as a "liveness" indicator.
878 * That is not sufficient, and we need a more fine-grained
879 * tool if we want to have a sanity check here.
880 */
881
882 if (!reg->vma)
883 continue;
884
885 GEM_BUG_ON(i915_vma_has_userfault(reg->vma));
886 reg->dirty = true;
887 }
888}
889
890static void discard_ggtt_vma(struct i915_vma *vma)
891{
892 struct drm_i915_gem_object *obj = vma->obj;
893
894 spin_lock(&obj->vma.lock);
895 if (!RB_EMPTY_NODE(&vma->obj_node)) {
896 rb_erase(&vma->obj_node, &obj->vma.tree);
897 RB_CLEAR_NODE(&vma->obj_node);
898 }
899 spin_unlock(&obj->vma.lock);
900}
901
902struct i915_vma *
903i915_gem_object_ggtt_pin_ww(struct drm_i915_gem_object *obj,
904 struct i915_gem_ww_ctx *ww,
905 const struct i915_gtt_view *view,
906 u64 size, u64 alignment, u64 flags)
907{
908 struct drm_i915_private *i915 = to_i915(obj->base.dev);
909 struct i915_ggtt *ggtt = to_gt(i915)->ggtt;
910 struct i915_vma *vma;
911 int ret;
912
913 GEM_WARN_ON(!ww);
914
915 if (flags & PIN_MAPPABLE &&
916 (!view || view->type == I915_GTT_VIEW_NORMAL)) {
917 /*
918 * If the required space is larger than the available
919 * aperture, we will not able to find a slot for the
920 * object and unbinding the object now will be in
921 * vain. Worse, doing so may cause us to ping-pong
922 * the object in and out of the Global GTT and
923 * waste a lot of cycles under the mutex.
924 */
925 if (obj->base.size > ggtt->mappable_end)
926 return ERR_PTR(-E2BIG);
927
928 /*
929 * If NONBLOCK is set the caller is optimistically
930 * trying to cache the full object within the mappable
931 * aperture, and *must* have a fallback in place for
932 * situations where we cannot bind the object. We
933 * can be a little more lax here and use the fallback
934 * more often to avoid costly migrations of ourselves
935 * and other objects within the aperture.
936 *
937 * Half-the-aperture is used as a simple heuristic.
938 * More interesting would to do search for a free
939 * block prior to making the commitment to unbind.
940 * That caters for the self-harm case, and with a
941 * little more heuristics (e.g. NOFAULT, NOEVICT)
942 * we could try to minimise harm to others.
943 */
944 if (flags & PIN_NONBLOCK &&
945 obj->base.size > ggtt->mappable_end / 2)
946 return ERR_PTR(-ENOSPC);
947 }
948
949new_vma:
950 vma = i915_vma_instance(obj, &ggtt->vm, view);
951 if (IS_ERR(vma))
952 return vma;
953
954 if (i915_vma_misplaced(vma, size, alignment, flags)) {
955 if (flags & PIN_NONBLOCK) {
956 if (i915_vma_is_pinned(vma) || i915_vma_is_active(vma))
957 return ERR_PTR(-ENOSPC);
958
959 /*
960 * If this misplaced vma is too big (i.e, at-least
961 * half the size of aperture) or hasn't been pinned
962 * mappable before, we ignore the misplacement when
963 * PIN_NONBLOCK is set in order to avoid the ping-pong
964 * issue described above. In other words, we try to
965 * avoid the costly operation of unbinding this vma
966 * from the GGTT and rebinding it back because there
967 * may not be enough space for this vma in the aperture.
968 */
969 if (flags & PIN_MAPPABLE &&
970 (vma->fence_size > ggtt->mappable_end / 2 ||
971 !i915_vma_is_map_and_fenceable(vma)))
972 return ERR_PTR(-ENOSPC);
973 }
974
975 if (i915_vma_is_pinned(vma) || i915_vma_is_active(vma)) {
976 discard_ggtt_vma(vma);
977 goto new_vma;
978 }
979
980 ret = i915_vma_unbind(vma);
981 if (ret)
982 return ERR_PTR(ret);
983 }
984
985 ret = i915_vma_pin_ww(vma, ww, size, alignment, flags | PIN_GLOBAL);
986
987 if (ret)
988 return ERR_PTR(ret);
989
990 if (vma->fence && !i915_gem_object_is_tiled(obj)) {
991 mutex_lock(&ggtt->vm.mutex);
992 i915_vma_revoke_fence(vma);
993 mutex_unlock(&ggtt->vm.mutex);
994 }
995
996 ret = i915_vma_wait_for_bind(vma);
997 if (ret) {
998 i915_vma_unpin(vma);
999 return ERR_PTR(ret);
1000 }
1001
1002 return vma;
1003}
1004
1005struct i915_vma * __must_check
1006i915_gem_object_ggtt_pin(struct drm_i915_gem_object *obj,
1007 const struct i915_gtt_view *view,
1008 u64 size, u64 alignment, u64 flags)
1009{
1010 struct i915_gem_ww_ctx ww;
1011 struct i915_vma *ret;
1012 int err;
1013
1014 for_i915_gem_ww(&ww, err, true) {
1015 err = i915_gem_object_lock(obj, &ww);
1016 if (err)
1017 continue;
1018
1019 ret = i915_gem_object_ggtt_pin_ww(obj, &ww, view, size,
1020 alignment, flags);
1021 if (IS_ERR(ret))
1022 err = PTR_ERR(ret);
1023 }
1024
1025 return err ? ERR_PTR(err) : ret;
1026}
1027
1028int
1029i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
1030 struct drm_file *file_priv)
1031{
1032 struct drm_i915_private *i915 = to_i915(dev);
1033 struct drm_i915_gem_madvise *args = data;
1034 struct drm_i915_gem_object *obj;
1035 int err;
1036
1037 switch (args->madv) {
1038 case I915_MADV_DONTNEED:
1039 case I915_MADV_WILLNEED:
1040 break;
1041 default:
1042 return -EINVAL;
1043 }
1044
1045 obj = i915_gem_object_lookup(file_priv, args->handle);
1046 if (!obj)
1047 return -ENOENT;
1048
1049 err = i915_gem_object_lock_interruptible(obj, NULL);
1050 if (err)
1051 goto out;
1052
1053 if (i915_gem_object_has_pages(obj) &&
1054 i915_gem_object_is_tiled(obj) &&
1055 i915->gem_quirks & GEM_QUIRK_PIN_SWIZZLED_PAGES) {
1056 if (obj->mm.madv == I915_MADV_WILLNEED) {
1057 GEM_BUG_ON(!i915_gem_object_has_tiling_quirk(obj));
1058 i915_gem_object_clear_tiling_quirk(obj);
1059 i915_gem_object_make_shrinkable(obj);
1060 }
1061 if (args->madv == I915_MADV_WILLNEED) {
1062 GEM_BUG_ON(i915_gem_object_has_tiling_quirk(obj));
1063 i915_gem_object_make_unshrinkable(obj);
1064 i915_gem_object_set_tiling_quirk(obj);
1065 }
1066 }
1067
1068 if (obj->mm.madv != __I915_MADV_PURGED) {
1069 obj->mm.madv = args->madv;
1070 if (obj->ops->adjust_lru)
1071 obj->ops->adjust_lru(obj);
1072 }
1073
1074 if (i915_gem_object_has_pages(obj) ||
1075 i915_gem_object_has_self_managed_shrink_list(obj)) {
1076 unsigned long flags;
1077
1078 spin_lock_irqsave(&i915->mm.obj_lock, flags);
1079 if (!list_empty(&obj->mm.link)) {
1080 struct list_head *list;
1081
1082 if (obj->mm.madv != I915_MADV_WILLNEED)
1083 list = &i915->mm.purge_list;
1084 else
1085 list = &i915->mm.shrink_list;
1086 list_move_tail(&obj->mm.link, list);
1087
1088 }
1089 spin_unlock_irqrestore(&i915->mm.obj_lock, flags);
1090 }
1091
1092 /* if the object is no longer attached, discard its backing storage */
1093 if (obj->mm.madv == I915_MADV_DONTNEED &&
1094 !i915_gem_object_has_pages(obj))
1095 i915_gem_object_truncate(obj);
1096
1097 args->retained = obj->mm.madv != __I915_MADV_PURGED;
1098
1099 i915_gem_object_unlock(obj);
1100out:
1101 i915_gem_object_put(obj);
1102 return err;
1103}
1104
1105/*
1106 * A single pass should suffice to release all the freed objects (along most
1107 * call paths), but be a little more paranoid in that freeing the objects does
1108 * take a little amount of time, during which the rcu callbacks could have added
1109 * new objects into the freed list, and armed the work again.
1110 */
1111void i915_gem_drain_freed_objects(struct drm_i915_private *i915)
1112{
1113 while (atomic_read(&i915->mm.free_count)) {
1114 flush_work(&i915->mm.free_work);
1115 drain_workqueue(i915->bdev.wq);
1116 rcu_barrier();
1117 }
1118}
1119
1120/*
1121 * Similar to objects above (see i915_gem_drain_freed-objects), in general we
1122 * have workers that are armed by RCU and then rearm themselves in their
1123 * callbacks. To be paranoid, we need to drain the workqueue a second time after
1124 * waiting for the RCU grace period so that we catch work queued via RCU from
1125 * the first pass. As neither drain_workqueue() nor flush_workqueue() report a
1126 * result, we make an assumption that we only don't require more than 3 passes
1127 * to catch all _recursive_ RCU delayed work.
1128 */
1129void i915_gem_drain_workqueue(struct drm_i915_private *i915)
1130{
1131 int i;
1132
1133 for (i = 0; i < 3; i++) {
1134 flush_workqueue(i915->wq);
1135 rcu_barrier();
1136 i915_gem_drain_freed_objects(i915);
1137 }
1138
1139 drain_workqueue(i915->wq);
1140}
1141
1142int i915_gem_init(struct drm_i915_private *dev_priv)
1143{
1144 struct intel_gt *gt;
1145 unsigned int i;
1146 int ret;
1147
1148 /*
1149 * In the proccess of replacing cache_level with pat_index a tricky
1150 * dependency is created on the definition of the enum i915_cache_level.
1151 * in case this enum is changed, PTE encode would be broken.
1152 * Add a WARNING here. And remove when we completely quit using this
1153 * enum
1154 */
1155 BUILD_BUG_ON(I915_CACHE_NONE != 0 ||
1156 I915_CACHE_LLC != 1 ||
1157 I915_CACHE_L3_LLC != 2 ||
1158 I915_CACHE_WT != 3 ||
1159 I915_MAX_CACHE_LEVEL != 4);
1160
1161 /* We need to fallback to 4K pages if host doesn't support huge gtt. */
1162 if (intel_vgpu_active(dev_priv) && !intel_vgpu_has_huge_gtt(dev_priv))
1163 RUNTIME_INFO(dev_priv)->page_sizes = I915_GTT_PAGE_SIZE_4K;
1164
1165 for_each_gt(gt, dev_priv, i) {
1166 intel_uc_fetch_firmwares(>->uc);
1167 intel_wopcm_init(>->wopcm);
1168 if (GRAPHICS_VER(dev_priv) >= 8)
1169 setup_private_pat(gt);
1170 }
1171
1172 ret = i915_init_ggtt(dev_priv);
1173 if (ret) {
1174 GEM_BUG_ON(ret == -EIO);
1175 goto err_unlock;
1176 }
1177
1178 /*
1179 * Despite its name intel_clock_gating_init applies both display
1180 * clock gating workarounds; GT mmio workarounds and the occasional
1181 * GT power context workaround. Worse, sometimes it includes a context
1182 * register workaround which we need to apply before we record the
1183 * default HW state for all contexts.
1184 *
1185 * FIXME: break up the workarounds and apply them at the right time!
1186 */
1187 intel_clock_gating_init(dev_priv);
1188
1189 for_each_gt(gt, dev_priv, i) {
1190 ret = intel_gt_init(gt);
1191 if (ret)
1192 goto err_unlock;
1193 }
1194
1195 /*
1196 * Register engines early to ensure the engine list is in its final
1197 * rb-tree form, lowering the amount of code that has to deal with
1198 * the intermediate llist state.
1199 */
1200 intel_engines_driver_register(dev_priv);
1201
1202 return 0;
1203
1204 /*
1205 * Unwinding is complicated by that we want to handle -EIO to mean
1206 * disable GPU submission but keep KMS alive. We want to mark the
1207 * HW as irrevisibly wedged, but keep enough state around that the
1208 * driver doesn't explode during runtime.
1209 */
1210err_unlock:
1211 i915_gem_drain_workqueue(dev_priv);
1212
1213 if (ret != -EIO) {
1214 for_each_gt(gt, dev_priv, i) {
1215 intel_gt_driver_remove(gt);
1216 intel_gt_driver_release(gt);
1217 intel_uc_cleanup_firmwares(>->uc);
1218 }
1219 }
1220
1221 if (ret == -EIO) {
1222 /*
1223 * Allow engines or uC initialisation to fail by marking the GPU
1224 * as wedged. But we only want to do this when the GPU is angry,
1225 * for all other failure, such as an allocation failure, bail.
1226 */
1227 for_each_gt(gt, dev_priv, i) {
1228 if (!intel_gt_is_wedged(gt)) {
1229 i915_probe_error(dev_priv,
1230 "Failed to initialize GPU, declaring it wedged!\n");
1231 intel_gt_set_wedged(gt);
1232 }
1233 }
1234
1235 /* Minimal basic recovery for KMS */
1236 ret = i915_ggtt_enable_hw(dev_priv);
1237 i915_ggtt_resume(to_gt(dev_priv)->ggtt);
1238 intel_clock_gating_init(dev_priv);
1239 }
1240
1241 i915_gem_drain_freed_objects(dev_priv);
1242
1243 return ret;
1244}
1245
1246void i915_gem_driver_register(struct drm_i915_private *i915)
1247{
1248 i915_gem_driver_register__shrinker(i915);
1249}
1250
1251void i915_gem_driver_unregister(struct drm_i915_private *i915)
1252{
1253 i915_gem_driver_unregister__shrinker(i915);
1254}
1255
1256void i915_gem_driver_remove(struct drm_i915_private *dev_priv)
1257{
1258 struct intel_gt *gt;
1259 unsigned int i;
1260
1261 i915_gem_suspend_late(dev_priv);
1262 for_each_gt(gt, dev_priv, i)
1263 intel_gt_driver_remove(gt);
1264 dev_priv->uabi_engines = RB_ROOT;
1265
1266 /* Flush any outstanding unpin_work. */
1267 i915_gem_drain_workqueue(dev_priv);
1268}
1269
1270void i915_gem_driver_release(struct drm_i915_private *dev_priv)
1271{
1272 struct intel_gt *gt;
1273 unsigned int i;
1274
1275 for_each_gt(gt, dev_priv, i) {
1276 intel_gt_driver_release(gt);
1277 intel_uc_cleanup_firmwares(>->uc);
1278 }
1279
1280 /* Flush any outstanding work, including i915_gem_context.release_work. */
1281 i915_gem_drain_workqueue(dev_priv);
1282
1283 drm_WARN_ON(&dev_priv->drm, !list_empty(&dev_priv->gem.contexts.list));
1284}
1285
1286static void i915_gem_init__mm(struct drm_i915_private *i915)
1287{
1288 spin_lock_init(&i915->mm.obj_lock);
1289
1290 init_llist_head(&i915->mm.free_list);
1291
1292 INIT_LIST_HEAD(&i915->mm.purge_list);
1293 INIT_LIST_HEAD(&i915->mm.shrink_list);
1294
1295 i915_gem_init__objects(i915);
1296}
1297
1298void i915_gem_init_early(struct drm_i915_private *dev_priv)
1299{
1300 i915_gem_init__mm(dev_priv);
1301 i915_gem_init__contexts(dev_priv);
1302}
1303
1304void i915_gem_cleanup_early(struct drm_i915_private *dev_priv)
1305{
1306 i915_gem_drain_workqueue(dev_priv);
1307 GEM_BUG_ON(!llist_empty(&dev_priv->mm.free_list));
1308 GEM_BUG_ON(atomic_read(&dev_priv->mm.free_count));
1309 drm_WARN_ON(&dev_priv->drm, dev_priv->mm.shrink_count);
1310}
1311
1312int i915_gem_open(struct drm_i915_private *i915, struct drm_file *file)
1313{
1314 struct drm_i915_file_private *file_priv;
1315 struct i915_drm_client *client;
1316 int ret = -ENOMEM;
1317
1318 drm_dbg(&i915->drm, "\n");
1319
1320 file_priv = kzalloc(sizeof(*file_priv), GFP_KERNEL);
1321 if (!file_priv)
1322 goto err_alloc;
1323
1324 client = i915_drm_client_alloc();
1325 if (!client)
1326 goto err_client;
1327
1328 file->driver_priv = file_priv;
1329 file_priv->i915 = i915;
1330 file_priv->file = file;
1331 file_priv->client = client;
1332
1333 file_priv->bsd_engine = -1;
1334 file_priv->hang_timestamp = jiffies;
1335
1336 ret = i915_gem_context_open(i915, file);
1337 if (ret)
1338 goto err_context;
1339
1340 return 0;
1341
1342err_context:
1343 i915_drm_client_put(client);
1344err_client:
1345 kfree(file_priv);
1346err_alloc:
1347 return ret;
1348}
1349
1350#if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
1351#include "selftests/mock_gem_device.c"
1352#include "selftests/i915_gem.c"
1353#endif
1/*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 *
26 */
27
28#include "drmP.h"
29#include "drm.h"
30#include "i915_drm.h"
31#include "i915_drv.h"
32#include "i915_trace.h"
33#include "intel_drv.h"
34#include <linux/shmem_fs.h>
35#include <linux/slab.h>
36#include <linux/swap.h>
37#include <linux/pci.h>
38#include <linux/dma-buf.h>
39
40static __must_check int i915_gem_object_flush_gpu_write_domain(struct drm_i915_gem_object *obj);
41static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj);
42static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj);
43static __must_check int i915_gem_object_bind_to_gtt(struct drm_i915_gem_object *obj,
44 unsigned alignment,
45 bool map_and_fenceable);
46static int i915_gem_phys_pwrite(struct drm_device *dev,
47 struct drm_i915_gem_object *obj,
48 struct drm_i915_gem_pwrite *args,
49 struct drm_file *file);
50
51static void i915_gem_write_fence(struct drm_device *dev, int reg,
52 struct drm_i915_gem_object *obj);
53static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj,
54 struct drm_i915_fence_reg *fence,
55 bool enable);
56
57static int i915_gem_inactive_shrink(struct shrinker *shrinker,
58 struct shrink_control *sc);
59static void i915_gem_object_truncate(struct drm_i915_gem_object *obj);
60
61static inline void i915_gem_object_fence_lost(struct drm_i915_gem_object *obj)
62{
63 if (obj->tiling_mode)
64 i915_gem_release_mmap(obj);
65
66 /* As we do not have an associated fence register, we will force
67 * a tiling change if we ever need to acquire one.
68 */
69 obj->fence_dirty = false;
70 obj->fence_reg = I915_FENCE_REG_NONE;
71}
72
73/* some bookkeeping */
74static void i915_gem_info_add_obj(struct drm_i915_private *dev_priv,
75 size_t size)
76{
77 dev_priv->mm.object_count++;
78 dev_priv->mm.object_memory += size;
79}
80
81static void i915_gem_info_remove_obj(struct drm_i915_private *dev_priv,
82 size_t size)
83{
84 dev_priv->mm.object_count--;
85 dev_priv->mm.object_memory -= size;
86}
87
88static int
89i915_gem_wait_for_error(struct drm_device *dev)
90{
91 struct drm_i915_private *dev_priv = dev->dev_private;
92 struct completion *x = &dev_priv->error_completion;
93 unsigned long flags;
94 int ret;
95
96 if (!atomic_read(&dev_priv->mm.wedged))
97 return 0;
98
99 ret = wait_for_completion_interruptible(x);
100 if (ret)
101 return ret;
102
103 if (atomic_read(&dev_priv->mm.wedged)) {
104 /* GPU is hung, bump the completion count to account for
105 * the token we just consumed so that we never hit zero and
106 * end up waiting upon a subsequent completion event that
107 * will never happen.
108 */
109 spin_lock_irqsave(&x->wait.lock, flags);
110 x->done++;
111 spin_unlock_irqrestore(&x->wait.lock, flags);
112 }
113 return 0;
114}
115
116int i915_mutex_lock_interruptible(struct drm_device *dev)
117{
118 int ret;
119
120 ret = i915_gem_wait_for_error(dev);
121 if (ret)
122 return ret;
123
124 ret = mutex_lock_interruptible(&dev->struct_mutex);
125 if (ret)
126 return ret;
127
128 WARN_ON(i915_verify_lists(dev));
129 return 0;
130}
131
132static inline bool
133i915_gem_object_is_inactive(struct drm_i915_gem_object *obj)
134{
135 return !obj->active;
136}
137
138int
139i915_gem_init_ioctl(struct drm_device *dev, void *data,
140 struct drm_file *file)
141{
142 struct drm_i915_gem_init *args = data;
143
144 if (drm_core_check_feature(dev, DRIVER_MODESET))
145 return -ENODEV;
146
147 if (args->gtt_start >= args->gtt_end ||
148 (args->gtt_end | args->gtt_start) & (PAGE_SIZE - 1))
149 return -EINVAL;
150
151 /* GEM with user mode setting was never supported on ilk and later. */
152 if (INTEL_INFO(dev)->gen >= 5)
153 return -ENODEV;
154
155 mutex_lock(&dev->struct_mutex);
156 i915_gem_init_global_gtt(dev, args->gtt_start,
157 args->gtt_end, args->gtt_end);
158 mutex_unlock(&dev->struct_mutex);
159
160 return 0;
161}
162
163int
164i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
165 struct drm_file *file)
166{
167 struct drm_i915_private *dev_priv = dev->dev_private;
168 struct drm_i915_gem_get_aperture *args = data;
169 struct drm_i915_gem_object *obj;
170 size_t pinned;
171
172 pinned = 0;
173 mutex_lock(&dev->struct_mutex);
174 list_for_each_entry(obj, &dev_priv->mm.gtt_list, gtt_list)
175 if (obj->pin_count)
176 pinned += obj->gtt_space->size;
177 mutex_unlock(&dev->struct_mutex);
178
179 args->aper_size = dev_priv->mm.gtt_total;
180 args->aper_available_size = args->aper_size - pinned;
181
182 return 0;
183}
184
185static int
186i915_gem_create(struct drm_file *file,
187 struct drm_device *dev,
188 uint64_t size,
189 uint32_t *handle_p)
190{
191 struct drm_i915_gem_object *obj;
192 int ret;
193 u32 handle;
194
195 size = roundup(size, PAGE_SIZE);
196 if (size == 0)
197 return -EINVAL;
198
199 /* Allocate the new object */
200 obj = i915_gem_alloc_object(dev, size);
201 if (obj == NULL)
202 return -ENOMEM;
203
204 ret = drm_gem_handle_create(file, &obj->base, &handle);
205 if (ret) {
206 drm_gem_object_release(&obj->base);
207 i915_gem_info_remove_obj(dev->dev_private, obj->base.size);
208 kfree(obj);
209 return ret;
210 }
211
212 /* drop reference from allocate - handle holds it now */
213 drm_gem_object_unreference(&obj->base);
214 trace_i915_gem_object_create(obj);
215
216 *handle_p = handle;
217 return 0;
218}
219
220int
221i915_gem_dumb_create(struct drm_file *file,
222 struct drm_device *dev,
223 struct drm_mode_create_dumb *args)
224{
225 /* have to work out size/pitch and return them */
226 args->pitch = ALIGN(args->width * ((args->bpp + 7) / 8), 64);
227 args->size = args->pitch * args->height;
228 return i915_gem_create(file, dev,
229 args->size, &args->handle);
230}
231
232int i915_gem_dumb_destroy(struct drm_file *file,
233 struct drm_device *dev,
234 uint32_t handle)
235{
236 return drm_gem_handle_delete(file, handle);
237}
238
239/**
240 * Creates a new mm object and returns a handle to it.
241 */
242int
243i915_gem_create_ioctl(struct drm_device *dev, void *data,
244 struct drm_file *file)
245{
246 struct drm_i915_gem_create *args = data;
247
248 return i915_gem_create(file, dev,
249 args->size, &args->handle);
250}
251
252static int i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj)
253{
254 drm_i915_private_t *dev_priv = obj->base.dev->dev_private;
255
256 return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
257 obj->tiling_mode != I915_TILING_NONE;
258}
259
260static inline int
261__copy_to_user_swizzled(char __user *cpu_vaddr,
262 const char *gpu_vaddr, int gpu_offset,
263 int length)
264{
265 int ret, cpu_offset = 0;
266
267 while (length > 0) {
268 int cacheline_end = ALIGN(gpu_offset + 1, 64);
269 int this_length = min(cacheline_end - gpu_offset, length);
270 int swizzled_gpu_offset = gpu_offset ^ 64;
271
272 ret = __copy_to_user(cpu_vaddr + cpu_offset,
273 gpu_vaddr + swizzled_gpu_offset,
274 this_length);
275 if (ret)
276 return ret + length;
277
278 cpu_offset += this_length;
279 gpu_offset += this_length;
280 length -= this_length;
281 }
282
283 return 0;
284}
285
286static inline int
287__copy_from_user_swizzled(char *gpu_vaddr, int gpu_offset,
288 const char __user *cpu_vaddr,
289 int length)
290{
291 int ret, cpu_offset = 0;
292
293 while (length > 0) {
294 int cacheline_end = ALIGN(gpu_offset + 1, 64);
295 int this_length = min(cacheline_end - gpu_offset, length);
296 int swizzled_gpu_offset = gpu_offset ^ 64;
297
298 ret = __copy_from_user(gpu_vaddr + swizzled_gpu_offset,
299 cpu_vaddr + cpu_offset,
300 this_length);
301 if (ret)
302 return ret + length;
303
304 cpu_offset += this_length;
305 gpu_offset += this_length;
306 length -= this_length;
307 }
308
309 return 0;
310}
311
312/* Per-page copy function for the shmem pread fastpath.
313 * Flushes invalid cachelines before reading the target if
314 * needs_clflush is set. */
315static int
316shmem_pread_fast(struct page *page, int shmem_page_offset, int page_length,
317 char __user *user_data,
318 bool page_do_bit17_swizzling, bool needs_clflush)
319{
320 char *vaddr;
321 int ret;
322
323 if (unlikely(page_do_bit17_swizzling))
324 return -EINVAL;
325
326 vaddr = kmap_atomic(page);
327 if (needs_clflush)
328 drm_clflush_virt_range(vaddr + shmem_page_offset,
329 page_length);
330 ret = __copy_to_user_inatomic(user_data,
331 vaddr + shmem_page_offset,
332 page_length);
333 kunmap_atomic(vaddr);
334
335 return ret;
336}
337
338static void
339shmem_clflush_swizzled_range(char *addr, unsigned long length,
340 bool swizzled)
341{
342 if (unlikely(swizzled)) {
343 unsigned long start = (unsigned long) addr;
344 unsigned long end = (unsigned long) addr + length;
345
346 /* For swizzling simply ensure that we always flush both
347 * channels. Lame, but simple and it works. Swizzled
348 * pwrite/pread is far from a hotpath - current userspace
349 * doesn't use it at all. */
350 start = round_down(start, 128);
351 end = round_up(end, 128);
352
353 drm_clflush_virt_range((void *)start, end - start);
354 } else {
355 drm_clflush_virt_range(addr, length);
356 }
357
358}
359
360/* Only difference to the fast-path function is that this can handle bit17
361 * and uses non-atomic copy and kmap functions. */
362static int
363shmem_pread_slow(struct page *page, int shmem_page_offset, int page_length,
364 char __user *user_data,
365 bool page_do_bit17_swizzling, bool needs_clflush)
366{
367 char *vaddr;
368 int ret;
369
370 vaddr = kmap(page);
371 if (needs_clflush)
372 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
373 page_length,
374 page_do_bit17_swizzling);
375
376 if (page_do_bit17_swizzling)
377 ret = __copy_to_user_swizzled(user_data,
378 vaddr, shmem_page_offset,
379 page_length);
380 else
381 ret = __copy_to_user(user_data,
382 vaddr + shmem_page_offset,
383 page_length);
384 kunmap(page);
385
386 return ret;
387}
388
389static int
390i915_gem_shmem_pread(struct drm_device *dev,
391 struct drm_i915_gem_object *obj,
392 struct drm_i915_gem_pread *args,
393 struct drm_file *file)
394{
395 struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping;
396 char __user *user_data;
397 ssize_t remain;
398 loff_t offset;
399 int shmem_page_offset, page_length, ret = 0;
400 int obj_do_bit17_swizzling, page_do_bit17_swizzling;
401 int hit_slowpath = 0;
402 int prefaulted = 0;
403 int needs_clflush = 0;
404 int release_page;
405
406 user_data = (char __user *) (uintptr_t) args->data_ptr;
407 remain = args->size;
408
409 obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
410
411 if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU)) {
412 /* If we're not in the cpu read domain, set ourself into the gtt
413 * read domain and manually flush cachelines (if required). This
414 * optimizes for the case when the gpu will dirty the data
415 * anyway again before the next pread happens. */
416 if (obj->cache_level == I915_CACHE_NONE)
417 needs_clflush = 1;
418 ret = i915_gem_object_set_to_gtt_domain(obj, false);
419 if (ret)
420 return ret;
421 }
422
423 offset = args->offset;
424
425 while (remain > 0) {
426 struct page *page;
427
428 /* Operation in this page
429 *
430 * shmem_page_offset = offset within page in shmem file
431 * page_length = bytes to copy for this page
432 */
433 shmem_page_offset = offset_in_page(offset);
434 page_length = remain;
435 if ((shmem_page_offset + page_length) > PAGE_SIZE)
436 page_length = PAGE_SIZE - shmem_page_offset;
437
438 if (obj->pages) {
439 page = obj->pages[offset >> PAGE_SHIFT];
440 release_page = 0;
441 } else {
442 page = shmem_read_mapping_page(mapping, offset >> PAGE_SHIFT);
443 if (IS_ERR(page)) {
444 ret = PTR_ERR(page);
445 goto out;
446 }
447 release_page = 1;
448 }
449
450 page_do_bit17_swizzling = obj_do_bit17_swizzling &&
451 (page_to_phys(page) & (1 << 17)) != 0;
452
453 ret = shmem_pread_fast(page, shmem_page_offset, page_length,
454 user_data, page_do_bit17_swizzling,
455 needs_clflush);
456 if (ret == 0)
457 goto next_page;
458
459 hit_slowpath = 1;
460 page_cache_get(page);
461 mutex_unlock(&dev->struct_mutex);
462
463 if (!prefaulted) {
464 ret = fault_in_multipages_writeable(user_data, remain);
465 /* Userspace is tricking us, but we've already clobbered
466 * its pages with the prefault and promised to write the
467 * data up to the first fault. Hence ignore any errors
468 * and just continue. */
469 (void)ret;
470 prefaulted = 1;
471 }
472
473 ret = shmem_pread_slow(page, shmem_page_offset, page_length,
474 user_data, page_do_bit17_swizzling,
475 needs_clflush);
476
477 mutex_lock(&dev->struct_mutex);
478 page_cache_release(page);
479next_page:
480 mark_page_accessed(page);
481 if (release_page)
482 page_cache_release(page);
483
484 if (ret) {
485 ret = -EFAULT;
486 goto out;
487 }
488
489 remain -= page_length;
490 user_data += page_length;
491 offset += page_length;
492 }
493
494out:
495 if (hit_slowpath) {
496 /* Fixup: Kill any reinstated backing storage pages */
497 if (obj->madv == __I915_MADV_PURGED)
498 i915_gem_object_truncate(obj);
499 }
500
501 return ret;
502}
503
504/**
505 * Reads data from the object referenced by handle.
506 *
507 * On error, the contents of *data are undefined.
508 */
509int
510i915_gem_pread_ioctl(struct drm_device *dev, void *data,
511 struct drm_file *file)
512{
513 struct drm_i915_gem_pread *args = data;
514 struct drm_i915_gem_object *obj;
515 int ret = 0;
516
517 if (args->size == 0)
518 return 0;
519
520 if (!access_ok(VERIFY_WRITE,
521 (char __user *)(uintptr_t)args->data_ptr,
522 args->size))
523 return -EFAULT;
524
525 ret = i915_mutex_lock_interruptible(dev);
526 if (ret)
527 return ret;
528
529 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
530 if (&obj->base == NULL) {
531 ret = -ENOENT;
532 goto unlock;
533 }
534
535 /* Bounds check source. */
536 if (args->offset > obj->base.size ||
537 args->size > obj->base.size - args->offset) {
538 ret = -EINVAL;
539 goto out;
540 }
541
542 /* prime objects have no backing filp to GEM pread/pwrite
543 * pages from.
544 */
545 if (!obj->base.filp) {
546 ret = -EINVAL;
547 goto out;
548 }
549
550 trace_i915_gem_object_pread(obj, args->offset, args->size);
551
552 ret = i915_gem_shmem_pread(dev, obj, args, file);
553
554out:
555 drm_gem_object_unreference(&obj->base);
556unlock:
557 mutex_unlock(&dev->struct_mutex);
558 return ret;
559}
560
561/* This is the fast write path which cannot handle
562 * page faults in the source data
563 */
564
565static inline int
566fast_user_write(struct io_mapping *mapping,
567 loff_t page_base, int page_offset,
568 char __user *user_data,
569 int length)
570{
571 void __iomem *vaddr_atomic;
572 void *vaddr;
573 unsigned long unwritten;
574
575 vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base);
576 /* We can use the cpu mem copy function because this is X86. */
577 vaddr = (void __force*)vaddr_atomic + page_offset;
578 unwritten = __copy_from_user_inatomic_nocache(vaddr,
579 user_data, length);
580 io_mapping_unmap_atomic(vaddr_atomic);
581 return unwritten;
582}
583
584/**
585 * This is the fast pwrite path, where we copy the data directly from the
586 * user into the GTT, uncached.
587 */
588static int
589i915_gem_gtt_pwrite_fast(struct drm_device *dev,
590 struct drm_i915_gem_object *obj,
591 struct drm_i915_gem_pwrite *args,
592 struct drm_file *file)
593{
594 drm_i915_private_t *dev_priv = dev->dev_private;
595 ssize_t remain;
596 loff_t offset, page_base;
597 char __user *user_data;
598 int page_offset, page_length, ret;
599
600 ret = i915_gem_object_pin(obj, 0, true);
601 if (ret)
602 goto out;
603
604 ret = i915_gem_object_set_to_gtt_domain(obj, true);
605 if (ret)
606 goto out_unpin;
607
608 ret = i915_gem_object_put_fence(obj);
609 if (ret)
610 goto out_unpin;
611
612 user_data = (char __user *) (uintptr_t) args->data_ptr;
613 remain = args->size;
614
615 offset = obj->gtt_offset + args->offset;
616
617 while (remain > 0) {
618 /* Operation in this page
619 *
620 * page_base = page offset within aperture
621 * page_offset = offset within page
622 * page_length = bytes to copy for this page
623 */
624 page_base = offset & PAGE_MASK;
625 page_offset = offset_in_page(offset);
626 page_length = remain;
627 if ((page_offset + remain) > PAGE_SIZE)
628 page_length = PAGE_SIZE - page_offset;
629
630 /* If we get a fault while copying data, then (presumably) our
631 * source page isn't available. Return the error and we'll
632 * retry in the slow path.
633 */
634 if (fast_user_write(dev_priv->mm.gtt_mapping, page_base,
635 page_offset, user_data, page_length)) {
636 ret = -EFAULT;
637 goto out_unpin;
638 }
639
640 remain -= page_length;
641 user_data += page_length;
642 offset += page_length;
643 }
644
645out_unpin:
646 i915_gem_object_unpin(obj);
647out:
648 return ret;
649}
650
651/* Per-page copy function for the shmem pwrite fastpath.
652 * Flushes invalid cachelines before writing to the target if
653 * needs_clflush_before is set and flushes out any written cachelines after
654 * writing if needs_clflush is set. */
655static int
656shmem_pwrite_fast(struct page *page, int shmem_page_offset, int page_length,
657 char __user *user_data,
658 bool page_do_bit17_swizzling,
659 bool needs_clflush_before,
660 bool needs_clflush_after)
661{
662 char *vaddr;
663 int ret;
664
665 if (unlikely(page_do_bit17_swizzling))
666 return -EINVAL;
667
668 vaddr = kmap_atomic(page);
669 if (needs_clflush_before)
670 drm_clflush_virt_range(vaddr + shmem_page_offset,
671 page_length);
672 ret = __copy_from_user_inatomic_nocache(vaddr + shmem_page_offset,
673 user_data,
674 page_length);
675 if (needs_clflush_after)
676 drm_clflush_virt_range(vaddr + shmem_page_offset,
677 page_length);
678 kunmap_atomic(vaddr);
679
680 return ret;
681}
682
683/* Only difference to the fast-path function is that this can handle bit17
684 * and uses non-atomic copy and kmap functions. */
685static int
686shmem_pwrite_slow(struct page *page, int shmem_page_offset, int page_length,
687 char __user *user_data,
688 bool page_do_bit17_swizzling,
689 bool needs_clflush_before,
690 bool needs_clflush_after)
691{
692 char *vaddr;
693 int ret;
694
695 vaddr = kmap(page);
696 if (unlikely(needs_clflush_before || page_do_bit17_swizzling))
697 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
698 page_length,
699 page_do_bit17_swizzling);
700 if (page_do_bit17_swizzling)
701 ret = __copy_from_user_swizzled(vaddr, shmem_page_offset,
702 user_data,
703 page_length);
704 else
705 ret = __copy_from_user(vaddr + shmem_page_offset,
706 user_data,
707 page_length);
708 if (needs_clflush_after)
709 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
710 page_length,
711 page_do_bit17_swizzling);
712 kunmap(page);
713
714 return ret;
715}
716
717static int
718i915_gem_shmem_pwrite(struct drm_device *dev,
719 struct drm_i915_gem_object *obj,
720 struct drm_i915_gem_pwrite *args,
721 struct drm_file *file)
722{
723 struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping;
724 ssize_t remain;
725 loff_t offset;
726 char __user *user_data;
727 int shmem_page_offset, page_length, ret = 0;
728 int obj_do_bit17_swizzling, page_do_bit17_swizzling;
729 int hit_slowpath = 0;
730 int needs_clflush_after = 0;
731 int needs_clflush_before = 0;
732 int release_page;
733
734 user_data = (char __user *) (uintptr_t) args->data_ptr;
735 remain = args->size;
736
737 obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
738
739 if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
740 /* If we're not in the cpu write domain, set ourself into the gtt
741 * write domain and manually flush cachelines (if required). This
742 * optimizes for the case when the gpu will use the data
743 * right away and we therefore have to clflush anyway. */
744 if (obj->cache_level == I915_CACHE_NONE)
745 needs_clflush_after = 1;
746 ret = i915_gem_object_set_to_gtt_domain(obj, true);
747 if (ret)
748 return ret;
749 }
750 /* Same trick applies for invalidate partially written cachelines before
751 * writing. */
752 if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU)
753 && obj->cache_level == I915_CACHE_NONE)
754 needs_clflush_before = 1;
755
756 offset = args->offset;
757 obj->dirty = 1;
758
759 while (remain > 0) {
760 struct page *page;
761 int partial_cacheline_write;
762
763 /* Operation in this page
764 *
765 * shmem_page_offset = offset within page in shmem file
766 * page_length = bytes to copy for this page
767 */
768 shmem_page_offset = offset_in_page(offset);
769
770 page_length = remain;
771 if ((shmem_page_offset + page_length) > PAGE_SIZE)
772 page_length = PAGE_SIZE - shmem_page_offset;
773
774 /* If we don't overwrite a cacheline completely we need to be
775 * careful to have up-to-date data by first clflushing. Don't
776 * overcomplicate things and flush the entire patch. */
777 partial_cacheline_write = needs_clflush_before &&
778 ((shmem_page_offset | page_length)
779 & (boot_cpu_data.x86_clflush_size - 1));
780
781 if (obj->pages) {
782 page = obj->pages[offset >> PAGE_SHIFT];
783 release_page = 0;
784 } else {
785 page = shmem_read_mapping_page(mapping, offset >> PAGE_SHIFT);
786 if (IS_ERR(page)) {
787 ret = PTR_ERR(page);
788 goto out;
789 }
790 release_page = 1;
791 }
792
793 page_do_bit17_swizzling = obj_do_bit17_swizzling &&
794 (page_to_phys(page) & (1 << 17)) != 0;
795
796 ret = shmem_pwrite_fast(page, shmem_page_offset, page_length,
797 user_data, page_do_bit17_swizzling,
798 partial_cacheline_write,
799 needs_clflush_after);
800 if (ret == 0)
801 goto next_page;
802
803 hit_slowpath = 1;
804 page_cache_get(page);
805 mutex_unlock(&dev->struct_mutex);
806
807 ret = shmem_pwrite_slow(page, shmem_page_offset, page_length,
808 user_data, page_do_bit17_swizzling,
809 partial_cacheline_write,
810 needs_clflush_after);
811
812 mutex_lock(&dev->struct_mutex);
813 page_cache_release(page);
814next_page:
815 set_page_dirty(page);
816 mark_page_accessed(page);
817 if (release_page)
818 page_cache_release(page);
819
820 if (ret) {
821 ret = -EFAULT;
822 goto out;
823 }
824
825 remain -= page_length;
826 user_data += page_length;
827 offset += page_length;
828 }
829
830out:
831 if (hit_slowpath) {
832 /* Fixup: Kill any reinstated backing storage pages */
833 if (obj->madv == __I915_MADV_PURGED)
834 i915_gem_object_truncate(obj);
835 /* and flush dirty cachelines in case the object isn't in the cpu write
836 * domain anymore. */
837 if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
838 i915_gem_clflush_object(obj);
839 intel_gtt_chipset_flush();
840 }
841 }
842
843 if (needs_clflush_after)
844 intel_gtt_chipset_flush();
845
846 return ret;
847}
848
849/**
850 * Writes data to the object referenced by handle.
851 *
852 * On error, the contents of the buffer that were to be modified are undefined.
853 */
854int
855i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
856 struct drm_file *file)
857{
858 struct drm_i915_gem_pwrite *args = data;
859 struct drm_i915_gem_object *obj;
860 int ret;
861
862 if (args->size == 0)
863 return 0;
864
865 if (!access_ok(VERIFY_READ,
866 (char __user *)(uintptr_t)args->data_ptr,
867 args->size))
868 return -EFAULT;
869
870 ret = fault_in_multipages_readable((char __user *)(uintptr_t)args->data_ptr,
871 args->size);
872 if (ret)
873 return -EFAULT;
874
875 ret = i915_mutex_lock_interruptible(dev);
876 if (ret)
877 return ret;
878
879 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
880 if (&obj->base == NULL) {
881 ret = -ENOENT;
882 goto unlock;
883 }
884
885 /* Bounds check destination. */
886 if (args->offset > obj->base.size ||
887 args->size > obj->base.size - args->offset) {
888 ret = -EINVAL;
889 goto out;
890 }
891
892 /* prime objects have no backing filp to GEM pread/pwrite
893 * pages from.
894 */
895 if (!obj->base.filp) {
896 ret = -EINVAL;
897 goto out;
898 }
899
900 trace_i915_gem_object_pwrite(obj, args->offset, args->size);
901
902 ret = -EFAULT;
903 /* We can only do the GTT pwrite on untiled buffers, as otherwise
904 * it would end up going through the fenced access, and we'll get
905 * different detiling behavior between reading and writing.
906 * pread/pwrite currently are reading and writing from the CPU
907 * perspective, requiring manual detiling by the client.
908 */
909 if (obj->phys_obj) {
910 ret = i915_gem_phys_pwrite(dev, obj, args, file);
911 goto out;
912 }
913
914 if (obj->gtt_space &&
915 obj->cache_level == I915_CACHE_NONE &&
916 obj->tiling_mode == I915_TILING_NONE &&
917 obj->map_and_fenceable &&
918 obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
919 ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file);
920 /* Note that the gtt paths might fail with non-page-backed user
921 * pointers (e.g. gtt mappings when moving data between
922 * textures). Fallback to the shmem path in that case. */
923 }
924
925 if (ret == -EFAULT)
926 ret = i915_gem_shmem_pwrite(dev, obj, args, file);
927
928out:
929 drm_gem_object_unreference(&obj->base);
930unlock:
931 mutex_unlock(&dev->struct_mutex);
932 return ret;
933}
934
935/**
936 * Called when user space prepares to use an object with the CPU, either
937 * through the mmap ioctl's mapping or a GTT mapping.
938 */
939int
940i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
941 struct drm_file *file)
942{
943 struct drm_i915_gem_set_domain *args = data;
944 struct drm_i915_gem_object *obj;
945 uint32_t read_domains = args->read_domains;
946 uint32_t write_domain = args->write_domain;
947 int ret;
948
949 /* Only handle setting domains to types used by the CPU. */
950 if (write_domain & I915_GEM_GPU_DOMAINS)
951 return -EINVAL;
952
953 if (read_domains & I915_GEM_GPU_DOMAINS)
954 return -EINVAL;
955
956 /* Having something in the write domain implies it's in the read
957 * domain, and only that read domain. Enforce that in the request.
958 */
959 if (write_domain != 0 && read_domains != write_domain)
960 return -EINVAL;
961
962 ret = i915_mutex_lock_interruptible(dev);
963 if (ret)
964 return ret;
965
966 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
967 if (&obj->base == NULL) {
968 ret = -ENOENT;
969 goto unlock;
970 }
971
972 if (read_domains & I915_GEM_DOMAIN_GTT) {
973 ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0);
974
975 /* Silently promote "you're not bound, there was nothing to do"
976 * to success, since the client was just asking us to
977 * make sure everything was done.
978 */
979 if (ret == -EINVAL)
980 ret = 0;
981 } else {
982 ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0);
983 }
984
985 drm_gem_object_unreference(&obj->base);
986unlock:
987 mutex_unlock(&dev->struct_mutex);
988 return ret;
989}
990
991/**
992 * Called when user space has done writes to this buffer
993 */
994int
995i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
996 struct drm_file *file)
997{
998 struct drm_i915_gem_sw_finish *args = data;
999 struct drm_i915_gem_object *obj;
1000 int ret = 0;
1001
1002 ret = i915_mutex_lock_interruptible(dev);
1003 if (ret)
1004 return ret;
1005
1006 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
1007 if (&obj->base == NULL) {
1008 ret = -ENOENT;
1009 goto unlock;
1010 }
1011
1012 /* Pinned buffers may be scanout, so flush the cache */
1013 if (obj->pin_count)
1014 i915_gem_object_flush_cpu_write_domain(obj);
1015
1016 drm_gem_object_unreference(&obj->base);
1017unlock:
1018 mutex_unlock(&dev->struct_mutex);
1019 return ret;
1020}
1021
1022/**
1023 * Maps the contents of an object, returning the address it is mapped
1024 * into.
1025 *
1026 * While the mapping holds a reference on the contents of the object, it doesn't
1027 * imply a ref on the object itself.
1028 */
1029int
1030i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
1031 struct drm_file *file)
1032{
1033 struct drm_i915_gem_mmap *args = data;
1034 struct drm_gem_object *obj;
1035 unsigned long addr;
1036
1037 obj = drm_gem_object_lookup(dev, file, args->handle);
1038 if (obj == NULL)
1039 return -ENOENT;
1040
1041 /* prime objects have no backing filp to GEM mmap
1042 * pages from.
1043 */
1044 if (!obj->filp) {
1045 drm_gem_object_unreference_unlocked(obj);
1046 return -EINVAL;
1047 }
1048
1049 addr = vm_mmap(obj->filp, 0, args->size,
1050 PROT_READ | PROT_WRITE, MAP_SHARED,
1051 args->offset);
1052 drm_gem_object_unreference_unlocked(obj);
1053 if (IS_ERR((void *)addr))
1054 return addr;
1055
1056 args->addr_ptr = (uint64_t) addr;
1057
1058 return 0;
1059}
1060
1061/**
1062 * i915_gem_fault - fault a page into the GTT
1063 * vma: VMA in question
1064 * vmf: fault info
1065 *
1066 * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
1067 * from userspace. The fault handler takes care of binding the object to
1068 * the GTT (if needed), allocating and programming a fence register (again,
1069 * only if needed based on whether the old reg is still valid or the object
1070 * is tiled) and inserting a new PTE into the faulting process.
1071 *
1072 * Note that the faulting process may involve evicting existing objects
1073 * from the GTT and/or fence registers to make room. So performance may
1074 * suffer if the GTT working set is large or there are few fence registers
1075 * left.
1076 */
1077int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
1078{
1079 struct drm_i915_gem_object *obj = to_intel_bo(vma->vm_private_data);
1080 struct drm_device *dev = obj->base.dev;
1081 drm_i915_private_t *dev_priv = dev->dev_private;
1082 pgoff_t page_offset;
1083 unsigned long pfn;
1084 int ret = 0;
1085 bool write = !!(vmf->flags & FAULT_FLAG_WRITE);
1086
1087 /* We don't use vmf->pgoff since that has the fake offset */
1088 page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >>
1089 PAGE_SHIFT;
1090
1091 ret = i915_mutex_lock_interruptible(dev);
1092 if (ret)
1093 goto out;
1094
1095 trace_i915_gem_object_fault(obj, page_offset, true, write);
1096
1097 /* Now bind it into the GTT if needed */
1098 if (!obj->map_and_fenceable) {
1099 ret = i915_gem_object_unbind(obj);
1100 if (ret)
1101 goto unlock;
1102 }
1103 if (!obj->gtt_space) {
1104 ret = i915_gem_object_bind_to_gtt(obj, 0, true);
1105 if (ret)
1106 goto unlock;
1107
1108 ret = i915_gem_object_set_to_gtt_domain(obj, write);
1109 if (ret)
1110 goto unlock;
1111 }
1112
1113 if (!obj->has_global_gtt_mapping)
1114 i915_gem_gtt_bind_object(obj, obj->cache_level);
1115
1116 ret = i915_gem_object_get_fence(obj);
1117 if (ret)
1118 goto unlock;
1119
1120 if (i915_gem_object_is_inactive(obj))
1121 list_move_tail(&obj->mm_list, &dev_priv->mm.inactive_list);
1122
1123 obj->fault_mappable = true;
1124
1125 pfn = ((dev->agp->base + obj->gtt_offset) >> PAGE_SHIFT) +
1126 page_offset;
1127
1128 /* Finally, remap it using the new GTT offset */
1129 ret = vm_insert_pfn(vma, (unsigned long)vmf->virtual_address, pfn);
1130unlock:
1131 mutex_unlock(&dev->struct_mutex);
1132out:
1133 switch (ret) {
1134 case -EIO:
1135 case -EAGAIN:
1136 /* Give the error handler a chance to run and move the
1137 * objects off the GPU active list. Next time we service the
1138 * fault, we should be able to transition the page into the
1139 * GTT without touching the GPU (and so avoid further
1140 * EIO/EGAIN). If the GPU is wedged, then there is no issue
1141 * with coherency, just lost writes.
1142 */
1143 set_need_resched();
1144 case 0:
1145 case -ERESTARTSYS:
1146 case -EINTR:
1147 return VM_FAULT_NOPAGE;
1148 case -ENOMEM:
1149 return VM_FAULT_OOM;
1150 default:
1151 return VM_FAULT_SIGBUS;
1152 }
1153}
1154
1155/**
1156 * i915_gem_release_mmap - remove physical page mappings
1157 * @obj: obj in question
1158 *
1159 * Preserve the reservation of the mmapping with the DRM core code, but
1160 * relinquish ownership of the pages back to the system.
1161 *
1162 * It is vital that we remove the page mapping if we have mapped a tiled
1163 * object through the GTT and then lose the fence register due to
1164 * resource pressure. Similarly if the object has been moved out of the
1165 * aperture, than pages mapped into userspace must be revoked. Removing the
1166 * mapping will then trigger a page fault on the next user access, allowing
1167 * fixup by i915_gem_fault().
1168 */
1169void
1170i915_gem_release_mmap(struct drm_i915_gem_object *obj)
1171{
1172 if (!obj->fault_mappable)
1173 return;
1174
1175 if (obj->base.dev->dev_mapping)
1176 unmap_mapping_range(obj->base.dev->dev_mapping,
1177 (loff_t)obj->base.map_list.hash.key<<PAGE_SHIFT,
1178 obj->base.size, 1);
1179
1180 obj->fault_mappable = false;
1181}
1182
1183static uint32_t
1184i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode)
1185{
1186 uint32_t gtt_size;
1187
1188 if (INTEL_INFO(dev)->gen >= 4 ||
1189 tiling_mode == I915_TILING_NONE)
1190 return size;
1191
1192 /* Previous chips need a power-of-two fence region when tiling */
1193 if (INTEL_INFO(dev)->gen == 3)
1194 gtt_size = 1024*1024;
1195 else
1196 gtt_size = 512*1024;
1197
1198 while (gtt_size < size)
1199 gtt_size <<= 1;
1200
1201 return gtt_size;
1202}
1203
1204/**
1205 * i915_gem_get_gtt_alignment - return required GTT alignment for an object
1206 * @obj: object to check
1207 *
1208 * Return the required GTT alignment for an object, taking into account
1209 * potential fence register mapping.
1210 */
1211static uint32_t
1212i915_gem_get_gtt_alignment(struct drm_device *dev,
1213 uint32_t size,
1214 int tiling_mode)
1215{
1216 /*
1217 * Minimum alignment is 4k (GTT page size), but might be greater
1218 * if a fence register is needed for the object.
1219 */
1220 if (INTEL_INFO(dev)->gen >= 4 ||
1221 tiling_mode == I915_TILING_NONE)
1222 return 4096;
1223
1224 /*
1225 * Previous chips need to be aligned to the size of the smallest
1226 * fence register that can contain the object.
1227 */
1228 return i915_gem_get_gtt_size(dev, size, tiling_mode);
1229}
1230
1231/**
1232 * i915_gem_get_unfenced_gtt_alignment - return required GTT alignment for an
1233 * unfenced object
1234 * @dev: the device
1235 * @size: size of the object
1236 * @tiling_mode: tiling mode of the object
1237 *
1238 * Return the required GTT alignment for an object, only taking into account
1239 * unfenced tiled surface requirements.
1240 */
1241uint32_t
1242i915_gem_get_unfenced_gtt_alignment(struct drm_device *dev,
1243 uint32_t size,
1244 int tiling_mode)
1245{
1246 /*
1247 * Minimum alignment is 4k (GTT page size) for sane hw.
1248 */
1249 if (INTEL_INFO(dev)->gen >= 4 || IS_G33(dev) ||
1250 tiling_mode == I915_TILING_NONE)
1251 return 4096;
1252
1253 /* Previous hardware however needs to be aligned to a power-of-two
1254 * tile height. The simplest method for determining this is to reuse
1255 * the power-of-tile object size.
1256 */
1257 return i915_gem_get_gtt_size(dev, size, tiling_mode);
1258}
1259
1260int
1261i915_gem_mmap_gtt(struct drm_file *file,
1262 struct drm_device *dev,
1263 uint32_t handle,
1264 uint64_t *offset)
1265{
1266 struct drm_i915_private *dev_priv = dev->dev_private;
1267 struct drm_i915_gem_object *obj;
1268 int ret;
1269
1270 ret = i915_mutex_lock_interruptible(dev);
1271 if (ret)
1272 return ret;
1273
1274 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
1275 if (&obj->base == NULL) {
1276 ret = -ENOENT;
1277 goto unlock;
1278 }
1279
1280 if (obj->base.size > dev_priv->mm.gtt_mappable_end) {
1281 ret = -E2BIG;
1282 goto out;
1283 }
1284
1285 if (obj->madv != I915_MADV_WILLNEED) {
1286 DRM_ERROR("Attempting to mmap a purgeable buffer\n");
1287 ret = -EINVAL;
1288 goto out;
1289 }
1290
1291 if (!obj->base.map_list.map) {
1292 ret = drm_gem_create_mmap_offset(&obj->base);
1293 if (ret)
1294 goto out;
1295 }
1296
1297 *offset = (u64)obj->base.map_list.hash.key << PAGE_SHIFT;
1298
1299out:
1300 drm_gem_object_unreference(&obj->base);
1301unlock:
1302 mutex_unlock(&dev->struct_mutex);
1303 return ret;
1304}
1305
1306/**
1307 * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
1308 * @dev: DRM device
1309 * @data: GTT mapping ioctl data
1310 * @file: GEM object info
1311 *
1312 * Simply returns the fake offset to userspace so it can mmap it.
1313 * The mmap call will end up in drm_gem_mmap(), which will set things
1314 * up so we can get faults in the handler above.
1315 *
1316 * The fault handler will take care of binding the object into the GTT
1317 * (since it may have been evicted to make room for something), allocating
1318 * a fence register, and mapping the appropriate aperture address into
1319 * userspace.
1320 */
1321int
1322i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
1323 struct drm_file *file)
1324{
1325 struct drm_i915_gem_mmap_gtt *args = data;
1326
1327 return i915_gem_mmap_gtt(file, dev, args->handle, &args->offset);
1328}
1329
1330int
1331i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj,
1332 gfp_t gfpmask)
1333{
1334 int page_count, i;
1335 struct address_space *mapping;
1336 struct inode *inode;
1337 struct page *page;
1338
1339 if (obj->pages || obj->sg_table)
1340 return 0;
1341
1342 /* Get the list of pages out of our struct file. They'll be pinned
1343 * at this point until we release them.
1344 */
1345 page_count = obj->base.size / PAGE_SIZE;
1346 BUG_ON(obj->pages != NULL);
1347 obj->pages = drm_malloc_ab(page_count, sizeof(struct page *));
1348 if (obj->pages == NULL)
1349 return -ENOMEM;
1350
1351 inode = obj->base.filp->f_path.dentry->d_inode;
1352 mapping = inode->i_mapping;
1353 gfpmask |= mapping_gfp_mask(mapping);
1354
1355 for (i = 0; i < page_count; i++) {
1356 page = shmem_read_mapping_page_gfp(mapping, i, gfpmask);
1357 if (IS_ERR(page))
1358 goto err_pages;
1359
1360 obj->pages[i] = page;
1361 }
1362
1363 if (i915_gem_object_needs_bit17_swizzle(obj))
1364 i915_gem_object_do_bit_17_swizzle(obj);
1365
1366 return 0;
1367
1368err_pages:
1369 while (i--)
1370 page_cache_release(obj->pages[i]);
1371
1372 drm_free_large(obj->pages);
1373 obj->pages = NULL;
1374 return PTR_ERR(page);
1375}
1376
1377static void
1378i915_gem_object_put_pages_gtt(struct drm_i915_gem_object *obj)
1379{
1380 int page_count = obj->base.size / PAGE_SIZE;
1381 int i;
1382
1383 if (!obj->pages)
1384 return;
1385
1386 BUG_ON(obj->madv == __I915_MADV_PURGED);
1387
1388 if (i915_gem_object_needs_bit17_swizzle(obj))
1389 i915_gem_object_save_bit_17_swizzle(obj);
1390
1391 if (obj->madv == I915_MADV_DONTNEED)
1392 obj->dirty = 0;
1393
1394 for (i = 0; i < page_count; i++) {
1395 if (obj->dirty)
1396 set_page_dirty(obj->pages[i]);
1397
1398 if (obj->madv == I915_MADV_WILLNEED)
1399 mark_page_accessed(obj->pages[i]);
1400
1401 page_cache_release(obj->pages[i]);
1402 }
1403 obj->dirty = 0;
1404
1405 drm_free_large(obj->pages);
1406 obj->pages = NULL;
1407}
1408
1409void
1410i915_gem_object_move_to_active(struct drm_i915_gem_object *obj,
1411 struct intel_ring_buffer *ring,
1412 u32 seqno)
1413{
1414 struct drm_device *dev = obj->base.dev;
1415 struct drm_i915_private *dev_priv = dev->dev_private;
1416
1417 BUG_ON(ring == NULL);
1418 obj->ring = ring;
1419
1420 /* Add a reference if we're newly entering the active list. */
1421 if (!obj->active) {
1422 drm_gem_object_reference(&obj->base);
1423 obj->active = 1;
1424 }
1425
1426 /* Move from whatever list we were on to the tail of execution. */
1427 list_move_tail(&obj->mm_list, &dev_priv->mm.active_list);
1428 list_move_tail(&obj->ring_list, &ring->active_list);
1429
1430 obj->last_rendering_seqno = seqno;
1431
1432 if (obj->fenced_gpu_access) {
1433 obj->last_fenced_seqno = seqno;
1434
1435 /* Bump MRU to take account of the delayed flush */
1436 if (obj->fence_reg != I915_FENCE_REG_NONE) {
1437 struct drm_i915_fence_reg *reg;
1438
1439 reg = &dev_priv->fence_regs[obj->fence_reg];
1440 list_move_tail(®->lru_list,
1441 &dev_priv->mm.fence_list);
1442 }
1443 }
1444}
1445
1446static void
1447i915_gem_object_move_off_active(struct drm_i915_gem_object *obj)
1448{
1449 list_del_init(&obj->ring_list);
1450 obj->last_rendering_seqno = 0;
1451 obj->last_fenced_seqno = 0;
1452}
1453
1454static void
1455i915_gem_object_move_to_flushing(struct drm_i915_gem_object *obj)
1456{
1457 struct drm_device *dev = obj->base.dev;
1458 drm_i915_private_t *dev_priv = dev->dev_private;
1459
1460 BUG_ON(!obj->active);
1461 list_move_tail(&obj->mm_list, &dev_priv->mm.flushing_list);
1462
1463 i915_gem_object_move_off_active(obj);
1464}
1465
1466static void
1467i915_gem_object_move_to_inactive(struct drm_i915_gem_object *obj)
1468{
1469 struct drm_device *dev = obj->base.dev;
1470 struct drm_i915_private *dev_priv = dev->dev_private;
1471
1472 list_move_tail(&obj->mm_list, &dev_priv->mm.inactive_list);
1473
1474 BUG_ON(!list_empty(&obj->gpu_write_list));
1475 BUG_ON(!obj->active);
1476 obj->ring = NULL;
1477
1478 i915_gem_object_move_off_active(obj);
1479 obj->fenced_gpu_access = false;
1480
1481 obj->active = 0;
1482 obj->pending_gpu_write = false;
1483 drm_gem_object_unreference(&obj->base);
1484
1485 WARN_ON(i915_verify_lists(dev));
1486}
1487
1488/* Immediately discard the backing storage */
1489static void
1490i915_gem_object_truncate(struct drm_i915_gem_object *obj)
1491{
1492 struct inode *inode;
1493
1494 /* Our goal here is to return as much of the memory as
1495 * is possible back to the system as we are called from OOM.
1496 * To do this we must instruct the shmfs to drop all of its
1497 * backing pages, *now*.
1498 */
1499 inode = obj->base.filp->f_path.dentry->d_inode;
1500 shmem_truncate_range(inode, 0, (loff_t)-1);
1501
1502 if (obj->base.map_list.map)
1503 drm_gem_free_mmap_offset(&obj->base);
1504
1505 obj->madv = __I915_MADV_PURGED;
1506}
1507
1508static inline int
1509i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj)
1510{
1511 return obj->madv == I915_MADV_DONTNEED;
1512}
1513
1514static void
1515i915_gem_process_flushing_list(struct intel_ring_buffer *ring,
1516 uint32_t flush_domains)
1517{
1518 struct drm_i915_gem_object *obj, *next;
1519
1520 list_for_each_entry_safe(obj, next,
1521 &ring->gpu_write_list,
1522 gpu_write_list) {
1523 if (obj->base.write_domain & flush_domains) {
1524 uint32_t old_write_domain = obj->base.write_domain;
1525
1526 obj->base.write_domain = 0;
1527 list_del_init(&obj->gpu_write_list);
1528 i915_gem_object_move_to_active(obj, ring,
1529 i915_gem_next_request_seqno(ring));
1530
1531 trace_i915_gem_object_change_domain(obj,
1532 obj->base.read_domains,
1533 old_write_domain);
1534 }
1535 }
1536}
1537
1538static u32
1539i915_gem_get_seqno(struct drm_device *dev)
1540{
1541 drm_i915_private_t *dev_priv = dev->dev_private;
1542 u32 seqno = dev_priv->next_seqno;
1543
1544 /* reserve 0 for non-seqno */
1545 if (++dev_priv->next_seqno == 0)
1546 dev_priv->next_seqno = 1;
1547
1548 return seqno;
1549}
1550
1551u32
1552i915_gem_next_request_seqno(struct intel_ring_buffer *ring)
1553{
1554 if (ring->outstanding_lazy_request == 0)
1555 ring->outstanding_lazy_request = i915_gem_get_seqno(ring->dev);
1556
1557 return ring->outstanding_lazy_request;
1558}
1559
1560int
1561i915_add_request(struct intel_ring_buffer *ring,
1562 struct drm_file *file,
1563 struct drm_i915_gem_request *request)
1564{
1565 drm_i915_private_t *dev_priv = ring->dev->dev_private;
1566 uint32_t seqno;
1567 u32 request_ring_position;
1568 int was_empty;
1569 int ret;
1570
1571 BUG_ON(request == NULL);
1572 seqno = i915_gem_next_request_seqno(ring);
1573
1574 /* Record the position of the start of the request so that
1575 * should we detect the updated seqno part-way through the
1576 * GPU processing the request, we never over-estimate the
1577 * position of the head.
1578 */
1579 request_ring_position = intel_ring_get_tail(ring);
1580
1581 ret = ring->add_request(ring, &seqno);
1582 if (ret)
1583 return ret;
1584
1585 trace_i915_gem_request_add(ring, seqno);
1586
1587 request->seqno = seqno;
1588 request->ring = ring;
1589 request->tail = request_ring_position;
1590 request->emitted_jiffies = jiffies;
1591 was_empty = list_empty(&ring->request_list);
1592 list_add_tail(&request->list, &ring->request_list);
1593
1594 if (file) {
1595 struct drm_i915_file_private *file_priv = file->driver_priv;
1596
1597 spin_lock(&file_priv->mm.lock);
1598 request->file_priv = file_priv;
1599 list_add_tail(&request->client_list,
1600 &file_priv->mm.request_list);
1601 spin_unlock(&file_priv->mm.lock);
1602 }
1603
1604 ring->outstanding_lazy_request = 0;
1605
1606 if (!dev_priv->mm.suspended) {
1607 if (i915_enable_hangcheck) {
1608 mod_timer(&dev_priv->hangcheck_timer,
1609 jiffies +
1610 msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD));
1611 }
1612 if (was_empty)
1613 queue_delayed_work(dev_priv->wq,
1614 &dev_priv->mm.retire_work, HZ);
1615 }
1616 return 0;
1617}
1618
1619static inline void
1620i915_gem_request_remove_from_client(struct drm_i915_gem_request *request)
1621{
1622 struct drm_i915_file_private *file_priv = request->file_priv;
1623
1624 if (!file_priv)
1625 return;
1626
1627 spin_lock(&file_priv->mm.lock);
1628 if (request->file_priv) {
1629 list_del(&request->client_list);
1630 request->file_priv = NULL;
1631 }
1632 spin_unlock(&file_priv->mm.lock);
1633}
1634
1635static void i915_gem_reset_ring_lists(struct drm_i915_private *dev_priv,
1636 struct intel_ring_buffer *ring)
1637{
1638 while (!list_empty(&ring->request_list)) {
1639 struct drm_i915_gem_request *request;
1640
1641 request = list_first_entry(&ring->request_list,
1642 struct drm_i915_gem_request,
1643 list);
1644
1645 list_del(&request->list);
1646 i915_gem_request_remove_from_client(request);
1647 kfree(request);
1648 }
1649
1650 while (!list_empty(&ring->active_list)) {
1651 struct drm_i915_gem_object *obj;
1652
1653 obj = list_first_entry(&ring->active_list,
1654 struct drm_i915_gem_object,
1655 ring_list);
1656
1657 obj->base.write_domain = 0;
1658 list_del_init(&obj->gpu_write_list);
1659 i915_gem_object_move_to_inactive(obj);
1660 }
1661}
1662
1663static void i915_gem_reset_fences(struct drm_device *dev)
1664{
1665 struct drm_i915_private *dev_priv = dev->dev_private;
1666 int i;
1667
1668 for (i = 0; i < dev_priv->num_fence_regs; i++) {
1669 struct drm_i915_fence_reg *reg = &dev_priv->fence_regs[i];
1670
1671 i915_gem_write_fence(dev, i, NULL);
1672
1673 if (reg->obj)
1674 i915_gem_object_fence_lost(reg->obj);
1675
1676 reg->pin_count = 0;
1677 reg->obj = NULL;
1678 INIT_LIST_HEAD(®->lru_list);
1679 }
1680
1681 INIT_LIST_HEAD(&dev_priv->mm.fence_list);
1682}
1683
1684void i915_gem_reset(struct drm_device *dev)
1685{
1686 struct drm_i915_private *dev_priv = dev->dev_private;
1687 struct drm_i915_gem_object *obj;
1688 struct intel_ring_buffer *ring;
1689 int i;
1690
1691 for_each_ring(ring, dev_priv, i)
1692 i915_gem_reset_ring_lists(dev_priv, ring);
1693
1694 /* Remove anything from the flushing lists. The GPU cache is likely
1695 * to be lost on reset along with the data, so simply move the
1696 * lost bo to the inactive list.
1697 */
1698 while (!list_empty(&dev_priv->mm.flushing_list)) {
1699 obj = list_first_entry(&dev_priv->mm.flushing_list,
1700 struct drm_i915_gem_object,
1701 mm_list);
1702
1703 obj->base.write_domain = 0;
1704 list_del_init(&obj->gpu_write_list);
1705 i915_gem_object_move_to_inactive(obj);
1706 }
1707
1708 /* Move everything out of the GPU domains to ensure we do any
1709 * necessary invalidation upon reuse.
1710 */
1711 list_for_each_entry(obj,
1712 &dev_priv->mm.inactive_list,
1713 mm_list)
1714 {
1715 obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS;
1716 }
1717
1718 /* The fence registers are invalidated so clear them out */
1719 i915_gem_reset_fences(dev);
1720}
1721
1722/**
1723 * This function clears the request list as sequence numbers are passed.
1724 */
1725void
1726i915_gem_retire_requests_ring(struct intel_ring_buffer *ring)
1727{
1728 uint32_t seqno;
1729 int i;
1730
1731 if (list_empty(&ring->request_list))
1732 return;
1733
1734 WARN_ON(i915_verify_lists(ring->dev));
1735
1736 seqno = ring->get_seqno(ring);
1737
1738 for (i = 0; i < ARRAY_SIZE(ring->sync_seqno); i++)
1739 if (seqno >= ring->sync_seqno[i])
1740 ring->sync_seqno[i] = 0;
1741
1742 while (!list_empty(&ring->request_list)) {
1743 struct drm_i915_gem_request *request;
1744
1745 request = list_first_entry(&ring->request_list,
1746 struct drm_i915_gem_request,
1747 list);
1748
1749 if (!i915_seqno_passed(seqno, request->seqno))
1750 break;
1751
1752 trace_i915_gem_request_retire(ring, request->seqno);
1753 /* We know the GPU must have read the request to have
1754 * sent us the seqno + interrupt, so use the position
1755 * of tail of the request to update the last known position
1756 * of the GPU head.
1757 */
1758 ring->last_retired_head = request->tail;
1759
1760 list_del(&request->list);
1761 i915_gem_request_remove_from_client(request);
1762 kfree(request);
1763 }
1764
1765 /* Move any buffers on the active list that are no longer referenced
1766 * by the ringbuffer to the flushing/inactive lists as appropriate.
1767 */
1768 while (!list_empty(&ring->active_list)) {
1769 struct drm_i915_gem_object *obj;
1770
1771 obj = list_first_entry(&ring->active_list,
1772 struct drm_i915_gem_object,
1773 ring_list);
1774
1775 if (!i915_seqno_passed(seqno, obj->last_rendering_seqno))
1776 break;
1777
1778 if (obj->base.write_domain != 0)
1779 i915_gem_object_move_to_flushing(obj);
1780 else
1781 i915_gem_object_move_to_inactive(obj);
1782 }
1783
1784 if (unlikely(ring->trace_irq_seqno &&
1785 i915_seqno_passed(seqno, ring->trace_irq_seqno))) {
1786 ring->irq_put(ring);
1787 ring->trace_irq_seqno = 0;
1788 }
1789
1790 WARN_ON(i915_verify_lists(ring->dev));
1791}
1792
1793void
1794i915_gem_retire_requests(struct drm_device *dev)
1795{
1796 drm_i915_private_t *dev_priv = dev->dev_private;
1797 struct intel_ring_buffer *ring;
1798 int i;
1799
1800 for_each_ring(ring, dev_priv, i)
1801 i915_gem_retire_requests_ring(ring);
1802}
1803
1804static void
1805i915_gem_retire_work_handler(struct work_struct *work)
1806{
1807 drm_i915_private_t *dev_priv;
1808 struct drm_device *dev;
1809 struct intel_ring_buffer *ring;
1810 bool idle;
1811 int i;
1812
1813 dev_priv = container_of(work, drm_i915_private_t,
1814 mm.retire_work.work);
1815 dev = dev_priv->dev;
1816
1817 /* Come back later if the device is busy... */
1818 if (!mutex_trylock(&dev->struct_mutex)) {
1819 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ);
1820 return;
1821 }
1822
1823 i915_gem_retire_requests(dev);
1824
1825 /* Send a periodic flush down the ring so we don't hold onto GEM
1826 * objects indefinitely.
1827 */
1828 idle = true;
1829 for_each_ring(ring, dev_priv, i) {
1830 if (!list_empty(&ring->gpu_write_list)) {
1831 struct drm_i915_gem_request *request;
1832 int ret;
1833
1834 ret = i915_gem_flush_ring(ring,
1835 0, I915_GEM_GPU_DOMAINS);
1836 request = kzalloc(sizeof(*request), GFP_KERNEL);
1837 if (ret || request == NULL ||
1838 i915_add_request(ring, NULL, request))
1839 kfree(request);
1840 }
1841
1842 idle &= list_empty(&ring->request_list);
1843 }
1844
1845 if (!dev_priv->mm.suspended && !idle)
1846 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ);
1847
1848 mutex_unlock(&dev->struct_mutex);
1849}
1850
1851static int
1852i915_gem_check_wedge(struct drm_i915_private *dev_priv)
1853{
1854 BUG_ON(!mutex_is_locked(&dev_priv->dev->struct_mutex));
1855
1856 if (atomic_read(&dev_priv->mm.wedged)) {
1857 struct completion *x = &dev_priv->error_completion;
1858 bool recovery_complete;
1859 unsigned long flags;
1860
1861 /* Give the error handler a chance to run. */
1862 spin_lock_irqsave(&x->wait.lock, flags);
1863 recovery_complete = x->done > 0;
1864 spin_unlock_irqrestore(&x->wait.lock, flags);
1865
1866 return recovery_complete ? -EIO : -EAGAIN;
1867 }
1868
1869 return 0;
1870}
1871
1872/*
1873 * Compare seqno against outstanding lazy request. Emit a request if they are
1874 * equal.
1875 */
1876static int
1877i915_gem_check_olr(struct intel_ring_buffer *ring, u32 seqno)
1878{
1879 int ret = 0;
1880
1881 BUG_ON(!mutex_is_locked(&ring->dev->struct_mutex));
1882
1883 if (seqno == ring->outstanding_lazy_request) {
1884 struct drm_i915_gem_request *request;
1885
1886 request = kzalloc(sizeof(*request), GFP_KERNEL);
1887 if (request == NULL)
1888 return -ENOMEM;
1889
1890 ret = i915_add_request(ring, NULL, request);
1891 if (ret) {
1892 kfree(request);
1893 return ret;
1894 }
1895
1896 BUG_ON(seqno != request->seqno);
1897 }
1898
1899 return ret;
1900}
1901
1902static int __wait_seqno(struct intel_ring_buffer *ring, u32 seqno,
1903 bool interruptible)
1904{
1905 drm_i915_private_t *dev_priv = ring->dev->dev_private;
1906 int ret = 0;
1907
1908 if (i915_seqno_passed(ring->get_seqno(ring), seqno))
1909 return 0;
1910
1911 trace_i915_gem_request_wait_begin(ring, seqno);
1912 if (WARN_ON(!ring->irq_get(ring)))
1913 return -ENODEV;
1914
1915#define EXIT_COND \
1916 (i915_seqno_passed(ring->get_seqno(ring), seqno) || \
1917 atomic_read(&dev_priv->mm.wedged))
1918
1919 if (interruptible)
1920 ret = wait_event_interruptible(ring->irq_queue,
1921 EXIT_COND);
1922 else
1923 wait_event(ring->irq_queue, EXIT_COND);
1924
1925 ring->irq_put(ring);
1926 trace_i915_gem_request_wait_end(ring, seqno);
1927#undef EXIT_COND
1928
1929 return ret;
1930}
1931
1932/**
1933 * Waits for a sequence number to be signaled, and cleans up the
1934 * request and object lists appropriately for that event.
1935 */
1936int
1937i915_wait_request(struct intel_ring_buffer *ring,
1938 uint32_t seqno)
1939{
1940 drm_i915_private_t *dev_priv = ring->dev->dev_private;
1941 int ret = 0;
1942
1943 BUG_ON(seqno == 0);
1944
1945 ret = i915_gem_check_wedge(dev_priv);
1946 if (ret)
1947 return ret;
1948
1949 ret = i915_gem_check_olr(ring, seqno);
1950 if (ret)
1951 return ret;
1952
1953 ret = __wait_seqno(ring, seqno, dev_priv->mm.interruptible);
1954 if (atomic_read(&dev_priv->mm.wedged))
1955 ret = -EAGAIN;
1956
1957 return ret;
1958}
1959
1960/**
1961 * Ensures that all rendering to the object has completed and the object is
1962 * safe to unbind from the GTT or access from the CPU.
1963 */
1964int
1965i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj)
1966{
1967 int ret;
1968
1969 /* This function only exists to support waiting for existing rendering,
1970 * not for emitting required flushes.
1971 */
1972 BUG_ON((obj->base.write_domain & I915_GEM_GPU_DOMAINS) != 0);
1973
1974 /* If there is rendering queued on the buffer being evicted, wait for
1975 * it.
1976 */
1977 if (obj->active) {
1978 ret = i915_wait_request(obj->ring, obj->last_rendering_seqno);
1979 if (ret)
1980 return ret;
1981 i915_gem_retire_requests_ring(obj->ring);
1982 }
1983
1984 return 0;
1985}
1986
1987/**
1988 * i915_gem_object_sync - sync an object to a ring.
1989 *
1990 * @obj: object which may be in use on another ring.
1991 * @to: ring we wish to use the object on. May be NULL.
1992 *
1993 * This code is meant to abstract object synchronization with the GPU.
1994 * Calling with NULL implies synchronizing the object with the CPU
1995 * rather than a particular GPU ring.
1996 *
1997 * Returns 0 if successful, else propagates up the lower layer error.
1998 */
1999int
2000i915_gem_object_sync(struct drm_i915_gem_object *obj,
2001 struct intel_ring_buffer *to)
2002{
2003 struct intel_ring_buffer *from = obj->ring;
2004 u32 seqno;
2005 int ret, idx;
2006
2007 if (from == NULL || to == from)
2008 return 0;
2009
2010 if (to == NULL || !i915_semaphore_is_enabled(obj->base.dev))
2011 return i915_gem_object_wait_rendering(obj);
2012
2013 idx = intel_ring_sync_index(from, to);
2014
2015 seqno = obj->last_rendering_seqno;
2016 if (seqno <= from->sync_seqno[idx])
2017 return 0;
2018
2019 ret = i915_gem_check_olr(obj->ring, seqno);
2020 if (ret)
2021 return ret;
2022
2023 ret = to->sync_to(to, from, seqno);
2024 if (!ret)
2025 from->sync_seqno[idx] = seqno;
2026
2027 return ret;
2028}
2029
2030static void i915_gem_object_finish_gtt(struct drm_i915_gem_object *obj)
2031{
2032 u32 old_write_domain, old_read_domains;
2033
2034 /* Act a barrier for all accesses through the GTT */
2035 mb();
2036
2037 /* Force a pagefault for domain tracking on next user access */
2038 i915_gem_release_mmap(obj);
2039
2040 if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0)
2041 return;
2042
2043 old_read_domains = obj->base.read_domains;
2044 old_write_domain = obj->base.write_domain;
2045
2046 obj->base.read_domains &= ~I915_GEM_DOMAIN_GTT;
2047 obj->base.write_domain &= ~I915_GEM_DOMAIN_GTT;
2048
2049 trace_i915_gem_object_change_domain(obj,
2050 old_read_domains,
2051 old_write_domain);
2052}
2053
2054/**
2055 * Unbinds an object from the GTT aperture.
2056 */
2057int
2058i915_gem_object_unbind(struct drm_i915_gem_object *obj)
2059{
2060 drm_i915_private_t *dev_priv = obj->base.dev->dev_private;
2061 int ret = 0;
2062
2063 if (obj->gtt_space == NULL)
2064 return 0;
2065
2066 if (obj->pin_count)
2067 return -EBUSY;
2068
2069 ret = i915_gem_object_finish_gpu(obj);
2070 if (ret)
2071 return ret;
2072 /* Continue on if we fail due to EIO, the GPU is hung so we
2073 * should be safe and we need to cleanup or else we might
2074 * cause memory corruption through use-after-free.
2075 */
2076
2077 i915_gem_object_finish_gtt(obj);
2078
2079 /* Move the object to the CPU domain to ensure that
2080 * any possible CPU writes while it's not in the GTT
2081 * are flushed when we go to remap it.
2082 */
2083 if (ret == 0)
2084 ret = i915_gem_object_set_to_cpu_domain(obj, 1);
2085 if (ret == -ERESTARTSYS)
2086 return ret;
2087 if (ret) {
2088 /* In the event of a disaster, abandon all caches and
2089 * hope for the best.
2090 */
2091 i915_gem_clflush_object(obj);
2092 obj->base.read_domains = obj->base.write_domain = I915_GEM_DOMAIN_CPU;
2093 }
2094
2095 /* release the fence reg _after_ flushing */
2096 ret = i915_gem_object_put_fence(obj);
2097 if (ret)
2098 return ret;
2099
2100 trace_i915_gem_object_unbind(obj);
2101
2102 if (obj->has_global_gtt_mapping)
2103 i915_gem_gtt_unbind_object(obj);
2104 if (obj->has_aliasing_ppgtt_mapping) {
2105 i915_ppgtt_unbind_object(dev_priv->mm.aliasing_ppgtt, obj);
2106 obj->has_aliasing_ppgtt_mapping = 0;
2107 }
2108 i915_gem_gtt_finish_object(obj);
2109
2110 i915_gem_object_put_pages_gtt(obj);
2111
2112 list_del_init(&obj->gtt_list);
2113 list_del_init(&obj->mm_list);
2114 /* Avoid an unnecessary call to unbind on rebind. */
2115 obj->map_and_fenceable = true;
2116
2117 drm_mm_put_block(obj->gtt_space);
2118 obj->gtt_space = NULL;
2119 obj->gtt_offset = 0;
2120
2121 if (i915_gem_object_is_purgeable(obj))
2122 i915_gem_object_truncate(obj);
2123
2124 return ret;
2125}
2126
2127int
2128i915_gem_flush_ring(struct intel_ring_buffer *ring,
2129 uint32_t invalidate_domains,
2130 uint32_t flush_domains)
2131{
2132 int ret;
2133
2134 if (((invalidate_domains | flush_domains) & I915_GEM_GPU_DOMAINS) == 0)
2135 return 0;
2136
2137 trace_i915_gem_ring_flush(ring, invalidate_domains, flush_domains);
2138
2139 ret = ring->flush(ring, invalidate_domains, flush_domains);
2140 if (ret)
2141 return ret;
2142
2143 if (flush_domains & I915_GEM_GPU_DOMAINS)
2144 i915_gem_process_flushing_list(ring, flush_domains);
2145
2146 return 0;
2147}
2148
2149static int i915_ring_idle(struct intel_ring_buffer *ring)
2150{
2151 int ret;
2152
2153 if (list_empty(&ring->gpu_write_list) && list_empty(&ring->active_list))
2154 return 0;
2155
2156 if (!list_empty(&ring->gpu_write_list)) {
2157 ret = i915_gem_flush_ring(ring,
2158 I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
2159 if (ret)
2160 return ret;
2161 }
2162
2163 return i915_wait_request(ring, i915_gem_next_request_seqno(ring));
2164}
2165
2166int i915_gpu_idle(struct drm_device *dev)
2167{
2168 drm_i915_private_t *dev_priv = dev->dev_private;
2169 struct intel_ring_buffer *ring;
2170 int ret, i;
2171
2172 /* Flush everything onto the inactive list. */
2173 for_each_ring(ring, dev_priv, i) {
2174 ret = i915_ring_idle(ring);
2175 if (ret)
2176 return ret;
2177
2178 /* Is the device fubar? */
2179 if (WARN_ON(!list_empty(&ring->gpu_write_list)))
2180 return -EBUSY;
2181 }
2182
2183 return 0;
2184}
2185
2186static void sandybridge_write_fence_reg(struct drm_device *dev, int reg,
2187 struct drm_i915_gem_object *obj)
2188{
2189 drm_i915_private_t *dev_priv = dev->dev_private;
2190 uint64_t val;
2191
2192 if (obj) {
2193 u32 size = obj->gtt_space->size;
2194
2195 val = (uint64_t)((obj->gtt_offset + size - 4096) &
2196 0xfffff000) << 32;
2197 val |= obj->gtt_offset & 0xfffff000;
2198 val |= (uint64_t)((obj->stride / 128) - 1) <<
2199 SANDYBRIDGE_FENCE_PITCH_SHIFT;
2200
2201 if (obj->tiling_mode == I915_TILING_Y)
2202 val |= 1 << I965_FENCE_TILING_Y_SHIFT;
2203 val |= I965_FENCE_REG_VALID;
2204 } else
2205 val = 0;
2206
2207 I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + reg * 8, val);
2208 POSTING_READ(FENCE_REG_SANDYBRIDGE_0 + reg * 8);
2209}
2210
2211static void i965_write_fence_reg(struct drm_device *dev, int reg,
2212 struct drm_i915_gem_object *obj)
2213{
2214 drm_i915_private_t *dev_priv = dev->dev_private;
2215 uint64_t val;
2216
2217 if (obj) {
2218 u32 size = obj->gtt_space->size;
2219
2220 val = (uint64_t)((obj->gtt_offset + size - 4096) &
2221 0xfffff000) << 32;
2222 val |= obj->gtt_offset & 0xfffff000;
2223 val |= ((obj->stride / 128) - 1) << I965_FENCE_PITCH_SHIFT;
2224 if (obj->tiling_mode == I915_TILING_Y)
2225 val |= 1 << I965_FENCE_TILING_Y_SHIFT;
2226 val |= I965_FENCE_REG_VALID;
2227 } else
2228 val = 0;
2229
2230 I915_WRITE64(FENCE_REG_965_0 + reg * 8, val);
2231 POSTING_READ(FENCE_REG_965_0 + reg * 8);
2232}
2233
2234static void i915_write_fence_reg(struct drm_device *dev, int reg,
2235 struct drm_i915_gem_object *obj)
2236{
2237 drm_i915_private_t *dev_priv = dev->dev_private;
2238 u32 val;
2239
2240 if (obj) {
2241 u32 size = obj->gtt_space->size;
2242 int pitch_val;
2243 int tile_width;
2244
2245 WARN((obj->gtt_offset & ~I915_FENCE_START_MASK) ||
2246 (size & -size) != size ||
2247 (obj->gtt_offset & (size - 1)),
2248 "object 0x%08x [fenceable? %d] not 1M or pot-size (0x%08x) aligned\n",
2249 obj->gtt_offset, obj->map_and_fenceable, size);
2250
2251 if (obj->tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev))
2252 tile_width = 128;
2253 else
2254 tile_width = 512;
2255
2256 /* Note: pitch better be a power of two tile widths */
2257 pitch_val = obj->stride / tile_width;
2258 pitch_val = ffs(pitch_val) - 1;
2259
2260 val = obj->gtt_offset;
2261 if (obj->tiling_mode == I915_TILING_Y)
2262 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
2263 val |= I915_FENCE_SIZE_BITS(size);
2264 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
2265 val |= I830_FENCE_REG_VALID;
2266 } else
2267 val = 0;
2268
2269 if (reg < 8)
2270 reg = FENCE_REG_830_0 + reg * 4;
2271 else
2272 reg = FENCE_REG_945_8 + (reg - 8) * 4;
2273
2274 I915_WRITE(reg, val);
2275 POSTING_READ(reg);
2276}
2277
2278static void i830_write_fence_reg(struct drm_device *dev, int reg,
2279 struct drm_i915_gem_object *obj)
2280{
2281 drm_i915_private_t *dev_priv = dev->dev_private;
2282 uint32_t val;
2283
2284 if (obj) {
2285 u32 size = obj->gtt_space->size;
2286 uint32_t pitch_val;
2287
2288 WARN((obj->gtt_offset & ~I830_FENCE_START_MASK) ||
2289 (size & -size) != size ||
2290 (obj->gtt_offset & (size - 1)),
2291 "object 0x%08x not 512K or pot-size 0x%08x aligned\n",
2292 obj->gtt_offset, size);
2293
2294 pitch_val = obj->stride / 128;
2295 pitch_val = ffs(pitch_val) - 1;
2296
2297 val = obj->gtt_offset;
2298 if (obj->tiling_mode == I915_TILING_Y)
2299 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
2300 val |= I830_FENCE_SIZE_BITS(size);
2301 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
2302 val |= I830_FENCE_REG_VALID;
2303 } else
2304 val = 0;
2305
2306 I915_WRITE(FENCE_REG_830_0 + reg * 4, val);
2307 POSTING_READ(FENCE_REG_830_0 + reg * 4);
2308}
2309
2310static void i915_gem_write_fence(struct drm_device *dev, int reg,
2311 struct drm_i915_gem_object *obj)
2312{
2313 switch (INTEL_INFO(dev)->gen) {
2314 case 7:
2315 case 6: sandybridge_write_fence_reg(dev, reg, obj); break;
2316 case 5:
2317 case 4: i965_write_fence_reg(dev, reg, obj); break;
2318 case 3: i915_write_fence_reg(dev, reg, obj); break;
2319 case 2: i830_write_fence_reg(dev, reg, obj); break;
2320 default: break;
2321 }
2322}
2323
2324static inline int fence_number(struct drm_i915_private *dev_priv,
2325 struct drm_i915_fence_reg *fence)
2326{
2327 return fence - dev_priv->fence_regs;
2328}
2329
2330static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj,
2331 struct drm_i915_fence_reg *fence,
2332 bool enable)
2333{
2334 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2335 int reg = fence_number(dev_priv, fence);
2336
2337 i915_gem_write_fence(obj->base.dev, reg, enable ? obj : NULL);
2338
2339 if (enable) {
2340 obj->fence_reg = reg;
2341 fence->obj = obj;
2342 list_move_tail(&fence->lru_list, &dev_priv->mm.fence_list);
2343 } else {
2344 obj->fence_reg = I915_FENCE_REG_NONE;
2345 fence->obj = NULL;
2346 list_del_init(&fence->lru_list);
2347 }
2348}
2349
2350static int
2351i915_gem_object_flush_fence(struct drm_i915_gem_object *obj)
2352{
2353 int ret;
2354
2355 if (obj->fenced_gpu_access) {
2356 if (obj->base.write_domain & I915_GEM_GPU_DOMAINS) {
2357 ret = i915_gem_flush_ring(obj->ring,
2358 0, obj->base.write_domain);
2359 if (ret)
2360 return ret;
2361 }
2362
2363 obj->fenced_gpu_access = false;
2364 }
2365
2366 if (obj->last_fenced_seqno) {
2367 ret = i915_wait_request(obj->ring, obj->last_fenced_seqno);
2368 if (ret)
2369 return ret;
2370
2371 obj->last_fenced_seqno = 0;
2372 }
2373
2374 /* Ensure that all CPU reads are completed before installing a fence
2375 * and all writes before removing the fence.
2376 */
2377 if (obj->base.read_domains & I915_GEM_DOMAIN_GTT)
2378 mb();
2379
2380 return 0;
2381}
2382
2383int
2384i915_gem_object_put_fence(struct drm_i915_gem_object *obj)
2385{
2386 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2387 int ret;
2388
2389 ret = i915_gem_object_flush_fence(obj);
2390 if (ret)
2391 return ret;
2392
2393 if (obj->fence_reg == I915_FENCE_REG_NONE)
2394 return 0;
2395
2396 i915_gem_object_update_fence(obj,
2397 &dev_priv->fence_regs[obj->fence_reg],
2398 false);
2399 i915_gem_object_fence_lost(obj);
2400
2401 return 0;
2402}
2403
2404static struct drm_i915_fence_reg *
2405i915_find_fence_reg(struct drm_device *dev)
2406{
2407 struct drm_i915_private *dev_priv = dev->dev_private;
2408 struct drm_i915_fence_reg *reg, *avail;
2409 int i;
2410
2411 /* First try to find a free reg */
2412 avail = NULL;
2413 for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) {
2414 reg = &dev_priv->fence_regs[i];
2415 if (!reg->obj)
2416 return reg;
2417
2418 if (!reg->pin_count)
2419 avail = reg;
2420 }
2421
2422 if (avail == NULL)
2423 return NULL;
2424
2425 /* None available, try to steal one or wait for a user to finish */
2426 list_for_each_entry(reg, &dev_priv->mm.fence_list, lru_list) {
2427 if (reg->pin_count)
2428 continue;
2429
2430 return reg;
2431 }
2432
2433 return NULL;
2434}
2435
2436/**
2437 * i915_gem_object_get_fence - set up fencing for an object
2438 * @obj: object to map through a fence reg
2439 *
2440 * When mapping objects through the GTT, userspace wants to be able to write
2441 * to them without having to worry about swizzling if the object is tiled.
2442 * This function walks the fence regs looking for a free one for @obj,
2443 * stealing one if it can't find any.
2444 *
2445 * It then sets up the reg based on the object's properties: address, pitch
2446 * and tiling format.
2447 *
2448 * For an untiled surface, this removes any existing fence.
2449 */
2450int
2451i915_gem_object_get_fence(struct drm_i915_gem_object *obj)
2452{
2453 struct drm_device *dev = obj->base.dev;
2454 struct drm_i915_private *dev_priv = dev->dev_private;
2455 bool enable = obj->tiling_mode != I915_TILING_NONE;
2456 struct drm_i915_fence_reg *reg;
2457 int ret;
2458
2459 /* Have we updated the tiling parameters upon the object and so
2460 * will need to serialise the write to the associated fence register?
2461 */
2462 if (obj->fence_dirty) {
2463 ret = i915_gem_object_flush_fence(obj);
2464 if (ret)
2465 return ret;
2466 }
2467
2468 /* Just update our place in the LRU if our fence is getting reused. */
2469 if (obj->fence_reg != I915_FENCE_REG_NONE) {
2470 reg = &dev_priv->fence_regs[obj->fence_reg];
2471 if (!obj->fence_dirty) {
2472 list_move_tail(®->lru_list,
2473 &dev_priv->mm.fence_list);
2474 return 0;
2475 }
2476 } else if (enable) {
2477 reg = i915_find_fence_reg(dev);
2478 if (reg == NULL)
2479 return -EDEADLK;
2480
2481 if (reg->obj) {
2482 struct drm_i915_gem_object *old = reg->obj;
2483
2484 ret = i915_gem_object_flush_fence(old);
2485 if (ret)
2486 return ret;
2487
2488 i915_gem_object_fence_lost(old);
2489 }
2490 } else
2491 return 0;
2492
2493 i915_gem_object_update_fence(obj, reg, enable);
2494 obj->fence_dirty = false;
2495
2496 return 0;
2497}
2498
2499/**
2500 * Finds free space in the GTT aperture and binds the object there.
2501 */
2502static int
2503i915_gem_object_bind_to_gtt(struct drm_i915_gem_object *obj,
2504 unsigned alignment,
2505 bool map_and_fenceable)
2506{
2507 struct drm_device *dev = obj->base.dev;
2508 drm_i915_private_t *dev_priv = dev->dev_private;
2509 struct drm_mm_node *free_space;
2510 gfp_t gfpmask = __GFP_NORETRY | __GFP_NOWARN;
2511 u32 size, fence_size, fence_alignment, unfenced_alignment;
2512 bool mappable, fenceable;
2513 int ret;
2514
2515 if (obj->madv != I915_MADV_WILLNEED) {
2516 DRM_ERROR("Attempting to bind a purgeable object\n");
2517 return -EINVAL;
2518 }
2519
2520 fence_size = i915_gem_get_gtt_size(dev,
2521 obj->base.size,
2522 obj->tiling_mode);
2523 fence_alignment = i915_gem_get_gtt_alignment(dev,
2524 obj->base.size,
2525 obj->tiling_mode);
2526 unfenced_alignment =
2527 i915_gem_get_unfenced_gtt_alignment(dev,
2528 obj->base.size,
2529 obj->tiling_mode);
2530
2531 if (alignment == 0)
2532 alignment = map_and_fenceable ? fence_alignment :
2533 unfenced_alignment;
2534 if (map_and_fenceable && alignment & (fence_alignment - 1)) {
2535 DRM_ERROR("Invalid object alignment requested %u\n", alignment);
2536 return -EINVAL;
2537 }
2538
2539 size = map_and_fenceable ? fence_size : obj->base.size;
2540
2541 /* If the object is bigger than the entire aperture, reject it early
2542 * before evicting everything in a vain attempt to find space.
2543 */
2544 if (obj->base.size >
2545 (map_and_fenceable ? dev_priv->mm.gtt_mappable_end : dev_priv->mm.gtt_total)) {
2546 DRM_ERROR("Attempting to bind an object larger than the aperture\n");
2547 return -E2BIG;
2548 }
2549
2550 search_free:
2551 if (map_and_fenceable)
2552 free_space =
2553 drm_mm_search_free_in_range(&dev_priv->mm.gtt_space,
2554 size, alignment, 0,
2555 dev_priv->mm.gtt_mappable_end,
2556 0);
2557 else
2558 free_space = drm_mm_search_free(&dev_priv->mm.gtt_space,
2559 size, alignment, 0);
2560
2561 if (free_space != NULL) {
2562 if (map_and_fenceable)
2563 obj->gtt_space =
2564 drm_mm_get_block_range_generic(free_space,
2565 size, alignment, 0,
2566 dev_priv->mm.gtt_mappable_end,
2567 0);
2568 else
2569 obj->gtt_space =
2570 drm_mm_get_block(free_space, size, alignment);
2571 }
2572 if (obj->gtt_space == NULL) {
2573 /* If the gtt is empty and we're still having trouble
2574 * fitting our object in, we're out of memory.
2575 */
2576 ret = i915_gem_evict_something(dev, size, alignment,
2577 map_and_fenceable);
2578 if (ret)
2579 return ret;
2580
2581 goto search_free;
2582 }
2583
2584 ret = i915_gem_object_get_pages_gtt(obj, gfpmask);
2585 if (ret) {
2586 drm_mm_put_block(obj->gtt_space);
2587 obj->gtt_space = NULL;
2588
2589 if (ret == -ENOMEM) {
2590 /* first try to reclaim some memory by clearing the GTT */
2591 ret = i915_gem_evict_everything(dev, false);
2592 if (ret) {
2593 /* now try to shrink everyone else */
2594 if (gfpmask) {
2595 gfpmask = 0;
2596 goto search_free;
2597 }
2598
2599 return -ENOMEM;
2600 }
2601
2602 goto search_free;
2603 }
2604
2605 return ret;
2606 }
2607
2608 ret = i915_gem_gtt_prepare_object(obj);
2609 if (ret) {
2610 i915_gem_object_put_pages_gtt(obj);
2611 drm_mm_put_block(obj->gtt_space);
2612 obj->gtt_space = NULL;
2613
2614 if (i915_gem_evict_everything(dev, false))
2615 return ret;
2616
2617 goto search_free;
2618 }
2619
2620 if (!dev_priv->mm.aliasing_ppgtt)
2621 i915_gem_gtt_bind_object(obj, obj->cache_level);
2622
2623 list_add_tail(&obj->gtt_list, &dev_priv->mm.gtt_list);
2624 list_add_tail(&obj->mm_list, &dev_priv->mm.inactive_list);
2625
2626 /* Assert that the object is not currently in any GPU domain. As it
2627 * wasn't in the GTT, there shouldn't be any way it could have been in
2628 * a GPU cache
2629 */
2630 BUG_ON(obj->base.read_domains & I915_GEM_GPU_DOMAINS);
2631 BUG_ON(obj->base.write_domain & I915_GEM_GPU_DOMAINS);
2632
2633 obj->gtt_offset = obj->gtt_space->start;
2634
2635 fenceable =
2636 obj->gtt_space->size == fence_size &&
2637 (obj->gtt_space->start & (fence_alignment - 1)) == 0;
2638
2639 mappable =
2640 obj->gtt_offset + obj->base.size <= dev_priv->mm.gtt_mappable_end;
2641
2642 obj->map_and_fenceable = mappable && fenceable;
2643
2644 trace_i915_gem_object_bind(obj, map_and_fenceable);
2645 return 0;
2646}
2647
2648void
2649i915_gem_clflush_object(struct drm_i915_gem_object *obj)
2650{
2651 /* If we don't have a page list set up, then we're not pinned
2652 * to GPU, and we can ignore the cache flush because it'll happen
2653 * again at bind time.
2654 */
2655 if (obj->pages == NULL)
2656 return;
2657
2658 /* If the GPU is snooping the contents of the CPU cache,
2659 * we do not need to manually clear the CPU cache lines. However,
2660 * the caches are only snooped when the render cache is
2661 * flushed/invalidated. As we always have to emit invalidations
2662 * and flushes when moving into and out of the RENDER domain, correct
2663 * snooping behaviour occurs naturally as the result of our domain
2664 * tracking.
2665 */
2666 if (obj->cache_level != I915_CACHE_NONE)
2667 return;
2668
2669 trace_i915_gem_object_clflush(obj);
2670
2671 drm_clflush_pages(obj->pages, obj->base.size / PAGE_SIZE);
2672}
2673
2674/** Flushes any GPU write domain for the object if it's dirty. */
2675static int
2676i915_gem_object_flush_gpu_write_domain(struct drm_i915_gem_object *obj)
2677{
2678 if ((obj->base.write_domain & I915_GEM_GPU_DOMAINS) == 0)
2679 return 0;
2680
2681 /* Queue the GPU write cache flushing we need. */
2682 return i915_gem_flush_ring(obj->ring, 0, obj->base.write_domain);
2683}
2684
2685/** Flushes the GTT write domain for the object if it's dirty. */
2686static void
2687i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj)
2688{
2689 uint32_t old_write_domain;
2690
2691 if (obj->base.write_domain != I915_GEM_DOMAIN_GTT)
2692 return;
2693
2694 /* No actual flushing is required for the GTT write domain. Writes
2695 * to it immediately go to main memory as far as we know, so there's
2696 * no chipset flush. It also doesn't land in render cache.
2697 *
2698 * However, we do have to enforce the order so that all writes through
2699 * the GTT land before any writes to the device, such as updates to
2700 * the GATT itself.
2701 */
2702 wmb();
2703
2704 old_write_domain = obj->base.write_domain;
2705 obj->base.write_domain = 0;
2706
2707 trace_i915_gem_object_change_domain(obj,
2708 obj->base.read_domains,
2709 old_write_domain);
2710}
2711
2712/** Flushes the CPU write domain for the object if it's dirty. */
2713static void
2714i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj)
2715{
2716 uint32_t old_write_domain;
2717
2718 if (obj->base.write_domain != I915_GEM_DOMAIN_CPU)
2719 return;
2720
2721 i915_gem_clflush_object(obj);
2722 intel_gtt_chipset_flush();
2723 old_write_domain = obj->base.write_domain;
2724 obj->base.write_domain = 0;
2725
2726 trace_i915_gem_object_change_domain(obj,
2727 obj->base.read_domains,
2728 old_write_domain);
2729}
2730
2731/**
2732 * Moves a single object to the GTT read, and possibly write domain.
2733 *
2734 * This function returns when the move is complete, including waiting on
2735 * flushes to occur.
2736 */
2737int
2738i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write)
2739{
2740 drm_i915_private_t *dev_priv = obj->base.dev->dev_private;
2741 uint32_t old_write_domain, old_read_domains;
2742 int ret;
2743
2744 /* Not valid to be called on unbound objects. */
2745 if (obj->gtt_space == NULL)
2746 return -EINVAL;
2747
2748 if (obj->base.write_domain == I915_GEM_DOMAIN_GTT)
2749 return 0;
2750
2751 ret = i915_gem_object_flush_gpu_write_domain(obj);
2752 if (ret)
2753 return ret;
2754
2755 if (obj->pending_gpu_write || write) {
2756 ret = i915_gem_object_wait_rendering(obj);
2757 if (ret)
2758 return ret;
2759 }
2760
2761 i915_gem_object_flush_cpu_write_domain(obj);
2762
2763 old_write_domain = obj->base.write_domain;
2764 old_read_domains = obj->base.read_domains;
2765
2766 /* It should now be out of any other write domains, and we can update
2767 * the domain values for our changes.
2768 */
2769 BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) != 0);
2770 obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
2771 if (write) {
2772 obj->base.read_domains = I915_GEM_DOMAIN_GTT;
2773 obj->base.write_domain = I915_GEM_DOMAIN_GTT;
2774 obj->dirty = 1;
2775 }
2776
2777 trace_i915_gem_object_change_domain(obj,
2778 old_read_domains,
2779 old_write_domain);
2780
2781 /* And bump the LRU for this access */
2782 if (i915_gem_object_is_inactive(obj))
2783 list_move_tail(&obj->mm_list, &dev_priv->mm.inactive_list);
2784
2785 return 0;
2786}
2787
2788int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
2789 enum i915_cache_level cache_level)
2790{
2791 struct drm_device *dev = obj->base.dev;
2792 drm_i915_private_t *dev_priv = dev->dev_private;
2793 int ret;
2794
2795 if (obj->cache_level == cache_level)
2796 return 0;
2797
2798 if (obj->pin_count) {
2799 DRM_DEBUG("can not change the cache level of pinned objects\n");
2800 return -EBUSY;
2801 }
2802
2803 if (obj->gtt_space) {
2804 ret = i915_gem_object_finish_gpu(obj);
2805 if (ret)
2806 return ret;
2807
2808 i915_gem_object_finish_gtt(obj);
2809
2810 /* Before SandyBridge, you could not use tiling or fence
2811 * registers with snooped memory, so relinquish any fences
2812 * currently pointing to our region in the aperture.
2813 */
2814 if (INTEL_INFO(obj->base.dev)->gen < 6) {
2815 ret = i915_gem_object_put_fence(obj);
2816 if (ret)
2817 return ret;
2818 }
2819
2820 if (obj->has_global_gtt_mapping)
2821 i915_gem_gtt_bind_object(obj, cache_level);
2822 if (obj->has_aliasing_ppgtt_mapping)
2823 i915_ppgtt_bind_object(dev_priv->mm.aliasing_ppgtt,
2824 obj, cache_level);
2825 }
2826
2827 if (cache_level == I915_CACHE_NONE) {
2828 u32 old_read_domains, old_write_domain;
2829
2830 /* If we're coming from LLC cached, then we haven't
2831 * actually been tracking whether the data is in the
2832 * CPU cache or not, since we only allow one bit set
2833 * in obj->write_domain and have been skipping the clflushes.
2834 * Just set it to the CPU cache for now.
2835 */
2836 WARN_ON(obj->base.write_domain & ~I915_GEM_DOMAIN_CPU);
2837 WARN_ON(obj->base.read_domains & ~I915_GEM_DOMAIN_CPU);
2838
2839 old_read_domains = obj->base.read_domains;
2840 old_write_domain = obj->base.write_domain;
2841
2842 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
2843 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
2844
2845 trace_i915_gem_object_change_domain(obj,
2846 old_read_domains,
2847 old_write_domain);
2848 }
2849
2850 obj->cache_level = cache_level;
2851 return 0;
2852}
2853
2854/*
2855 * Prepare buffer for display plane (scanout, cursors, etc).
2856 * Can be called from an uninterruptible phase (modesetting) and allows
2857 * any flushes to be pipelined (for pageflips).
2858 */
2859int
2860i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
2861 u32 alignment,
2862 struct intel_ring_buffer *pipelined)
2863{
2864 u32 old_read_domains, old_write_domain;
2865 int ret;
2866
2867 ret = i915_gem_object_flush_gpu_write_domain(obj);
2868 if (ret)
2869 return ret;
2870
2871 if (pipelined != obj->ring) {
2872 ret = i915_gem_object_sync(obj, pipelined);
2873 if (ret)
2874 return ret;
2875 }
2876
2877 /* The display engine is not coherent with the LLC cache on gen6. As
2878 * a result, we make sure that the pinning that is about to occur is
2879 * done with uncached PTEs. This is lowest common denominator for all
2880 * chipsets.
2881 *
2882 * However for gen6+, we could do better by using the GFDT bit instead
2883 * of uncaching, which would allow us to flush all the LLC-cached data
2884 * with that bit in the PTE to main memory with just one PIPE_CONTROL.
2885 */
2886 ret = i915_gem_object_set_cache_level(obj, I915_CACHE_NONE);
2887 if (ret)
2888 return ret;
2889
2890 /* As the user may map the buffer once pinned in the display plane
2891 * (e.g. libkms for the bootup splash), we have to ensure that we
2892 * always use map_and_fenceable for all scanout buffers.
2893 */
2894 ret = i915_gem_object_pin(obj, alignment, true);
2895 if (ret)
2896 return ret;
2897
2898 i915_gem_object_flush_cpu_write_domain(obj);
2899
2900 old_write_domain = obj->base.write_domain;
2901 old_read_domains = obj->base.read_domains;
2902
2903 /* It should now be out of any other write domains, and we can update
2904 * the domain values for our changes.
2905 */
2906 BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) != 0);
2907 obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
2908
2909 trace_i915_gem_object_change_domain(obj,
2910 old_read_domains,
2911 old_write_domain);
2912
2913 return 0;
2914}
2915
2916int
2917i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj)
2918{
2919 int ret;
2920
2921 if ((obj->base.read_domains & I915_GEM_GPU_DOMAINS) == 0)
2922 return 0;
2923
2924 if (obj->base.write_domain & I915_GEM_GPU_DOMAINS) {
2925 ret = i915_gem_flush_ring(obj->ring, 0, obj->base.write_domain);
2926 if (ret)
2927 return ret;
2928 }
2929
2930 ret = i915_gem_object_wait_rendering(obj);
2931 if (ret)
2932 return ret;
2933
2934 /* Ensure that we invalidate the GPU's caches and TLBs. */
2935 obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS;
2936 return 0;
2937}
2938
2939/**
2940 * Moves a single object to the CPU read, and possibly write domain.
2941 *
2942 * This function returns when the move is complete, including waiting on
2943 * flushes to occur.
2944 */
2945int
2946i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write)
2947{
2948 uint32_t old_write_domain, old_read_domains;
2949 int ret;
2950
2951 if (obj->base.write_domain == I915_GEM_DOMAIN_CPU)
2952 return 0;
2953
2954 ret = i915_gem_object_flush_gpu_write_domain(obj);
2955 if (ret)
2956 return ret;
2957
2958 if (write || obj->pending_gpu_write) {
2959 ret = i915_gem_object_wait_rendering(obj);
2960 if (ret)
2961 return ret;
2962 }
2963
2964 i915_gem_object_flush_gtt_write_domain(obj);
2965
2966 old_write_domain = obj->base.write_domain;
2967 old_read_domains = obj->base.read_domains;
2968
2969 /* Flush the CPU cache if it's still invalid. */
2970 if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) {
2971 i915_gem_clflush_object(obj);
2972
2973 obj->base.read_domains |= I915_GEM_DOMAIN_CPU;
2974 }
2975
2976 /* It should now be out of any other write domains, and we can update
2977 * the domain values for our changes.
2978 */
2979 BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
2980
2981 /* If we're writing through the CPU, then the GPU read domains will
2982 * need to be invalidated at next use.
2983 */
2984 if (write) {
2985 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
2986 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
2987 }
2988
2989 trace_i915_gem_object_change_domain(obj,
2990 old_read_domains,
2991 old_write_domain);
2992
2993 return 0;
2994}
2995
2996/* Throttle our rendering by waiting until the ring has completed our requests
2997 * emitted over 20 msec ago.
2998 *
2999 * Note that if we were to use the current jiffies each time around the loop,
3000 * we wouldn't escape the function with any frames outstanding if the time to
3001 * render a frame was over 20ms.
3002 *
3003 * This should get us reasonable parallelism between CPU and GPU but also
3004 * relatively low latency when blocking on a particular request to finish.
3005 */
3006static int
3007i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file)
3008{
3009 struct drm_i915_private *dev_priv = dev->dev_private;
3010 struct drm_i915_file_private *file_priv = file->driver_priv;
3011 unsigned long recent_enough = jiffies - msecs_to_jiffies(20);
3012 struct drm_i915_gem_request *request;
3013 struct intel_ring_buffer *ring = NULL;
3014 u32 seqno = 0;
3015 int ret;
3016
3017 if (atomic_read(&dev_priv->mm.wedged))
3018 return -EIO;
3019
3020 spin_lock(&file_priv->mm.lock);
3021 list_for_each_entry(request, &file_priv->mm.request_list, client_list) {
3022 if (time_after_eq(request->emitted_jiffies, recent_enough))
3023 break;
3024
3025 ring = request->ring;
3026 seqno = request->seqno;
3027 }
3028 spin_unlock(&file_priv->mm.lock);
3029
3030 if (seqno == 0)
3031 return 0;
3032
3033 ret = __wait_seqno(ring, seqno, true);
3034 if (ret == 0)
3035 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, 0);
3036
3037 return ret;
3038}
3039
3040int
3041i915_gem_object_pin(struct drm_i915_gem_object *obj,
3042 uint32_t alignment,
3043 bool map_and_fenceable)
3044{
3045 int ret;
3046
3047 if (WARN_ON(obj->pin_count == DRM_I915_GEM_OBJECT_MAX_PIN_COUNT))
3048 return -EBUSY;
3049
3050 if (obj->gtt_space != NULL) {
3051 if ((alignment && obj->gtt_offset & (alignment - 1)) ||
3052 (map_and_fenceable && !obj->map_and_fenceable)) {
3053 WARN(obj->pin_count,
3054 "bo is already pinned with incorrect alignment:"
3055 " offset=%x, req.alignment=%x, req.map_and_fenceable=%d,"
3056 " obj->map_and_fenceable=%d\n",
3057 obj->gtt_offset, alignment,
3058 map_and_fenceable,
3059 obj->map_and_fenceable);
3060 ret = i915_gem_object_unbind(obj);
3061 if (ret)
3062 return ret;
3063 }
3064 }
3065
3066 if (obj->gtt_space == NULL) {
3067 ret = i915_gem_object_bind_to_gtt(obj, alignment,
3068 map_and_fenceable);
3069 if (ret)
3070 return ret;
3071 }
3072
3073 if (!obj->has_global_gtt_mapping && map_and_fenceable)
3074 i915_gem_gtt_bind_object(obj, obj->cache_level);
3075
3076 obj->pin_count++;
3077 obj->pin_mappable |= map_and_fenceable;
3078
3079 return 0;
3080}
3081
3082void
3083i915_gem_object_unpin(struct drm_i915_gem_object *obj)
3084{
3085 BUG_ON(obj->pin_count == 0);
3086 BUG_ON(obj->gtt_space == NULL);
3087
3088 if (--obj->pin_count == 0)
3089 obj->pin_mappable = false;
3090}
3091
3092int
3093i915_gem_pin_ioctl(struct drm_device *dev, void *data,
3094 struct drm_file *file)
3095{
3096 struct drm_i915_gem_pin *args = data;
3097 struct drm_i915_gem_object *obj;
3098 int ret;
3099
3100 ret = i915_mutex_lock_interruptible(dev);
3101 if (ret)
3102 return ret;
3103
3104 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3105 if (&obj->base == NULL) {
3106 ret = -ENOENT;
3107 goto unlock;
3108 }
3109
3110 if (obj->madv != I915_MADV_WILLNEED) {
3111 DRM_ERROR("Attempting to pin a purgeable buffer\n");
3112 ret = -EINVAL;
3113 goto out;
3114 }
3115
3116 if (obj->pin_filp != NULL && obj->pin_filp != file) {
3117 DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n",
3118 args->handle);
3119 ret = -EINVAL;
3120 goto out;
3121 }
3122
3123 obj->user_pin_count++;
3124 obj->pin_filp = file;
3125 if (obj->user_pin_count == 1) {
3126 ret = i915_gem_object_pin(obj, args->alignment, true);
3127 if (ret)
3128 goto out;
3129 }
3130
3131 /* XXX - flush the CPU caches for pinned objects
3132 * as the X server doesn't manage domains yet
3133 */
3134 i915_gem_object_flush_cpu_write_domain(obj);
3135 args->offset = obj->gtt_offset;
3136out:
3137 drm_gem_object_unreference(&obj->base);
3138unlock:
3139 mutex_unlock(&dev->struct_mutex);
3140 return ret;
3141}
3142
3143int
3144i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
3145 struct drm_file *file)
3146{
3147 struct drm_i915_gem_pin *args = data;
3148 struct drm_i915_gem_object *obj;
3149 int ret;
3150
3151 ret = i915_mutex_lock_interruptible(dev);
3152 if (ret)
3153 return ret;
3154
3155 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3156 if (&obj->base == NULL) {
3157 ret = -ENOENT;
3158 goto unlock;
3159 }
3160
3161 if (obj->pin_filp != file) {
3162 DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n",
3163 args->handle);
3164 ret = -EINVAL;
3165 goto out;
3166 }
3167 obj->user_pin_count--;
3168 if (obj->user_pin_count == 0) {
3169 obj->pin_filp = NULL;
3170 i915_gem_object_unpin(obj);
3171 }
3172
3173out:
3174 drm_gem_object_unreference(&obj->base);
3175unlock:
3176 mutex_unlock(&dev->struct_mutex);
3177 return ret;
3178}
3179
3180int
3181i915_gem_busy_ioctl(struct drm_device *dev, void *data,
3182 struct drm_file *file)
3183{
3184 struct drm_i915_gem_busy *args = data;
3185 struct drm_i915_gem_object *obj;
3186 int ret;
3187
3188 ret = i915_mutex_lock_interruptible(dev);
3189 if (ret)
3190 return ret;
3191
3192 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3193 if (&obj->base == NULL) {
3194 ret = -ENOENT;
3195 goto unlock;
3196 }
3197
3198 /* Count all active objects as busy, even if they are currently not used
3199 * by the gpu. Users of this interface expect objects to eventually
3200 * become non-busy without any further actions, therefore emit any
3201 * necessary flushes here.
3202 */
3203 args->busy = obj->active;
3204 if (args->busy) {
3205 /* Unconditionally flush objects, even when the gpu still uses this
3206 * object. Userspace calling this function indicates that it wants to
3207 * use this buffer rather sooner than later, so issuing the required
3208 * flush earlier is beneficial.
3209 */
3210 if (obj->base.write_domain & I915_GEM_GPU_DOMAINS) {
3211 ret = i915_gem_flush_ring(obj->ring,
3212 0, obj->base.write_domain);
3213 } else {
3214 ret = i915_gem_check_olr(obj->ring,
3215 obj->last_rendering_seqno);
3216 }
3217
3218 /* Update the active list for the hardware's current position.
3219 * Otherwise this only updates on a delayed timer or when irqs
3220 * are actually unmasked, and our working set ends up being
3221 * larger than required.
3222 */
3223 i915_gem_retire_requests_ring(obj->ring);
3224
3225 args->busy = obj->active;
3226 }
3227
3228 drm_gem_object_unreference(&obj->base);
3229unlock:
3230 mutex_unlock(&dev->struct_mutex);
3231 return ret;
3232}
3233
3234int
3235i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
3236 struct drm_file *file_priv)
3237{
3238 return i915_gem_ring_throttle(dev, file_priv);
3239}
3240
3241int
3242i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
3243 struct drm_file *file_priv)
3244{
3245 struct drm_i915_gem_madvise *args = data;
3246 struct drm_i915_gem_object *obj;
3247 int ret;
3248
3249 switch (args->madv) {
3250 case I915_MADV_DONTNEED:
3251 case I915_MADV_WILLNEED:
3252 break;
3253 default:
3254 return -EINVAL;
3255 }
3256
3257 ret = i915_mutex_lock_interruptible(dev);
3258 if (ret)
3259 return ret;
3260
3261 obj = to_intel_bo(drm_gem_object_lookup(dev, file_priv, args->handle));
3262 if (&obj->base == NULL) {
3263 ret = -ENOENT;
3264 goto unlock;
3265 }
3266
3267 if (obj->pin_count) {
3268 ret = -EINVAL;
3269 goto out;
3270 }
3271
3272 if (obj->madv != __I915_MADV_PURGED)
3273 obj->madv = args->madv;
3274
3275 /* if the object is no longer bound, discard its backing storage */
3276 if (i915_gem_object_is_purgeable(obj) &&
3277 obj->gtt_space == NULL)
3278 i915_gem_object_truncate(obj);
3279
3280 args->retained = obj->madv != __I915_MADV_PURGED;
3281
3282out:
3283 drm_gem_object_unreference(&obj->base);
3284unlock:
3285 mutex_unlock(&dev->struct_mutex);
3286 return ret;
3287}
3288
3289struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev,
3290 size_t size)
3291{
3292 struct drm_i915_private *dev_priv = dev->dev_private;
3293 struct drm_i915_gem_object *obj;
3294 struct address_space *mapping;
3295 u32 mask;
3296
3297 obj = kzalloc(sizeof(*obj), GFP_KERNEL);
3298 if (obj == NULL)
3299 return NULL;
3300
3301 if (drm_gem_object_init(dev, &obj->base, size) != 0) {
3302 kfree(obj);
3303 return NULL;
3304 }
3305
3306 mask = GFP_HIGHUSER | __GFP_RECLAIMABLE;
3307 if (IS_CRESTLINE(dev) || IS_BROADWATER(dev)) {
3308 /* 965gm cannot relocate objects above 4GiB. */
3309 mask &= ~__GFP_HIGHMEM;
3310 mask |= __GFP_DMA32;
3311 }
3312
3313 mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping;
3314 mapping_set_gfp_mask(mapping, mask);
3315
3316 i915_gem_info_add_obj(dev_priv, size);
3317
3318 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
3319 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
3320
3321 if (HAS_LLC(dev)) {
3322 /* On some devices, we can have the GPU use the LLC (the CPU
3323 * cache) for about a 10% performance improvement
3324 * compared to uncached. Graphics requests other than
3325 * display scanout are coherent with the CPU in
3326 * accessing this cache. This means in this mode we
3327 * don't need to clflush on the CPU side, and on the
3328 * GPU side we only need to flush internal caches to
3329 * get data visible to the CPU.
3330 *
3331 * However, we maintain the display planes as UC, and so
3332 * need to rebind when first used as such.
3333 */
3334 obj->cache_level = I915_CACHE_LLC;
3335 } else
3336 obj->cache_level = I915_CACHE_NONE;
3337
3338 obj->base.driver_private = NULL;
3339 obj->fence_reg = I915_FENCE_REG_NONE;
3340 INIT_LIST_HEAD(&obj->mm_list);
3341 INIT_LIST_HEAD(&obj->gtt_list);
3342 INIT_LIST_HEAD(&obj->ring_list);
3343 INIT_LIST_HEAD(&obj->exec_list);
3344 INIT_LIST_HEAD(&obj->gpu_write_list);
3345 obj->madv = I915_MADV_WILLNEED;
3346 /* Avoid an unnecessary call to unbind on the first bind. */
3347 obj->map_and_fenceable = true;
3348
3349 return obj;
3350}
3351
3352int i915_gem_init_object(struct drm_gem_object *obj)
3353{
3354 BUG();
3355
3356 return 0;
3357}
3358
3359void i915_gem_free_object(struct drm_gem_object *gem_obj)
3360{
3361 struct drm_i915_gem_object *obj = to_intel_bo(gem_obj);
3362 struct drm_device *dev = obj->base.dev;
3363 drm_i915_private_t *dev_priv = dev->dev_private;
3364
3365 trace_i915_gem_object_destroy(obj);
3366
3367 if (gem_obj->import_attach)
3368 drm_prime_gem_destroy(gem_obj, obj->sg_table);
3369
3370 if (obj->phys_obj)
3371 i915_gem_detach_phys_object(dev, obj);
3372
3373 obj->pin_count = 0;
3374 if (WARN_ON(i915_gem_object_unbind(obj) == -ERESTARTSYS)) {
3375 bool was_interruptible;
3376
3377 was_interruptible = dev_priv->mm.interruptible;
3378 dev_priv->mm.interruptible = false;
3379
3380 WARN_ON(i915_gem_object_unbind(obj));
3381
3382 dev_priv->mm.interruptible = was_interruptible;
3383 }
3384
3385 if (obj->base.map_list.map)
3386 drm_gem_free_mmap_offset(&obj->base);
3387
3388 drm_gem_object_release(&obj->base);
3389 i915_gem_info_remove_obj(dev_priv, obj->base.size);
3390
3391 kfree(obj->bit_17);
3392 kfree(obj);
3393}
3394
3395int
3396i915_gem_idle(struct drm_device *dev)
3397{
3398 drm_i915_private_t *dev_priv = dev->dev_private;
3399 int ret;
3400
3401 mutex_lock(&dev->struct_mutex);
3402
3403 if (dev_priv->mm.suspended) {
3404 mutex_unlock(&dev->struct_mutex);
3405 return 0;
3406 }
3407
3408 ret = i915_gpu_idle(dev);
3409 if (ret) {
3410 mutex_unlock(&dev->struct_mutex);
3411 return ret;
3412 }
3413 i915_gem_retire_requests(dev);
3414
3415 /* Under UMS, be paranoid and evict. */
3416 if (!drm_core_check_feature(dev, DRIVER_MODESET))
3417 i915_gem_evict_everything(dev, false);
3418
3419 i915_gem_reset_fences(dev);
3420
3421 /* Hack! Don't let anybody do execbuf while we don't control the chip.
3422 * We need to replace this with a semaphore, or something.
3423 * And not confound mm.suspended!
3424 */
3425 dev_priv->mm.suspended = 1;
3426 del_timer_sync(&dev_priv->hangcheck_timer);
3427
3428 i915_kernel_lost_context(dev);
3429 i915_gem_cleanup_ringbuffer(dev);
3430
3431 mutex_unlock(&dev->struct_mutex);
3432
3433 /* Cancel the retire work handler, which should be idle now. */
3434 cancel_delayed_work_sync(&dev_priv->mm.retire_work);
3435
3436 return 0;
3437}
3438
3439void i915_gem_init_swizzling(struct drm_device *dev)
3440{
3441 drm_i915_private_t *dev_priv = dev->dev_private;
3442
3443 if (INTEL_INFO(dev)->gen < 5 ||
3444 dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE)
3445 return;
3446
3447 I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) |
3448 DISP_TILE_SURFACE_SWIZZLING);
3449
3450 if (IS_GEN5(dev))
3451 return;
3452
3453 I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_SWZCTL);
3454 if (IS_GEN6(dev))
3455 I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB));
3456 else
3457 I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB));
3458}
3459
3460void i915_gem_init_ppgtt(struct drm_device *dev)
3461{
3462 drm_i915_private_t *dev_priv = dev->dev_private;
3463 uint32_t pd_offset;
3464 struct intel_ring_buffer *ring;
3465 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
3466 uint32_t __iomem *pd_addr;
3467 uint32_t pd_entry;
3468 int i;
3469
3470 if (!dev_priv->mm.aliasing_ppgtt)
3471 return;
3472
3473
3474 pd_addr = dev_priv->mm.gtt->gtt + ppgtt->pd_offset/sizeof(uint32_t);
3475 for (i = 0; i < ppgtt->num_pd_entries; i++) {
3476 dma_addr_t pt_addr;
3477
3478 if (dev_priv->mm.gtt->needs_dmar)
3479 pt_addr = ppgtt->pt_dma_addr[i];
3480 else
3481 pt_addr = page_to_phys(ppgtt->pt_pages[i]);
3482
3483 pd_entry = GEN6_PDE_ADDR_ENCODE(pt_addr);
3484 pd_entry |= GEN6_PDE_VALID;
3485
3486 writel(pd_entry, pd_addr + i);
3487 }
3488 readl(pd_addr);
3489
3490 pd_offset = ppgtt->pd_offset;
3491 pd_offset /= 64; /* in cachelines, */
3492 pd_offset <<= 16;
3493
3494 if (INTEL_INFO(dev)->gen == 6) {
3495 uint32_t ecochk, gab_ctl, ecobits;
3496
3497 ecobits = I915_READ(GAC_ECO_BITS);
3498 I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_PPGTT_CACHE64B);
3499
3500 gab_ctl = I915_READ(GAB_CTL);
3501 I915_WRITE(GAB_CTL, gab_ctl | GAB_CTL_CONT_AFTER_PAGEFAULT);
3502
3503 ecochk = I915_READ(GAM_ECOCHK);
3504 I915_WRITE(GAM_ECOCHK, ecochk | ECOCHK_SNB_BIT |
3505 ECOCHK_PPGTT_CACHE64B);
3506 I915_WRITE(GFX_MODE, _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
3507 } else if (INTEL_INFO(dev)->gen >= 7) {
3508 I915_WRITE(GAM_ECOCHK, ECOCHK_PPGTT_CACHE64B);
3509 /* GFX_MODE is per-ring on gen7+ */
3510 }
3511
3512 for_each_ring(ring, dev_priv, i) {
3513 if (INTEL_INFO(dev)->gen >= 7)
3514 I915_WRITE(RING_MODE_GEN7(ring),
3515 _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
3516
3517 I915_WRITE(RING_PP_DIR_DCLV(ring), PP_DIR_DCLV_2G);
3518 I915_WRITE(RING_PP_DIR_BASE(ring), pd_offset);
3519 }
3520}
3521
3522int
3523i915_gem_init_hw(struct drm_device *dev)
3524{
3525 drm_i915_private_t *dev_priv = dev->dev_private;
3526 int ret;
3527
3528 i915_gem_init_swizzling(dev);
3529
3530 ret = intel_init_render_ring_buffer(dev);
3531 if (ret)
3532 return ret;
3533
3534 if (HAS_BSD(dev)) {
3535 ret = intel_init_bsd_ring_buffer(dev);
3536 if (ret)
3537 goto cleanup_render_ring;
3538 }
3539
3540 if (HAS_BLT(dev)) {
3541 ret = intel_init_blt_ring_buffer(dev);
3542 if (ret)
3543 goto cleanup_bsd_ring;
3544 }
3545
3546 dev_priv->next_seqno = 1;
3547
3548 i915_gem_init_ppgtt(dev);
3549
3550 return 0;
3551
3552cleanup_bsd_ring:
3553 intel_cleanup_ring_buffer(&dev_priv->ring[VCS]);
3554cleanup_render_ring:
3555 intel_cleanup_ring_buffer(&dev_priv->ring[RCS]);
3556 return ret;
3557}
3558
3559static bool
3560intel_enable_ppgtt(struct drm_device *dev)
3561{
3562 if (i915_enable_ppgtt >= 0)
3563 return i915_enable_ppgtt;
3564
3565#ifdef CONFIG_INTEL_IOMMU
3566 /* Disable ppgtt on SNB if VT-d is on. */
3567 if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped)
3568 return false;
3569#endif
3570
3571 return true;
3572}
3573
3574int i915_gem_init(struct drm_device *dev)
3575{
3576 struct drm_i915_private *dev_priv = dev->dev_private;
3577 unsigned long gtt_size, mappable_size;
3578 int ret;
3579
3580 gtt_size = dev_priv->mm.gtt->gtt_total_entries << PAGE_SHIFT;
3581 mappable_size = dev_priv->mm.gtt->gtt_mappable_entries << PAGE_SHIFT;
3582
3583 mutex_lock(&dev->struct_mutex);
3584 if (intel_enable_ppgtt(dev) && HAS_ALIASING_PPGTT(dev)) {
3585 /* PPGTT pdes are stolen from global gtt ptes, so shrink the
3586 * aperture accordingly when using aliasing ppgtt. */
3587 gtt_size -= I915_PPGTT_PD_ENTRIES*PAGE_SIZE;
3588
3589 i915_gem_init_global_gtt(dev, 0, mappable_size, gtt_size);
3590
3591 ret = i915_gem_init_aliasing_ppgtt(dev);
3592 if (ret) {
3593 mutex_unlock(&dev->struct_mutex);
3594 return ret;
3595 }
3596 } else {
3597 /* Let GEM Manage all of the aperture.
3598 *
3599 * However, leave one page at the end still bound to the scratch
3600 * page. There are a number of places where the hardware
3601 * apparently prefetches past the end of the object, and we've
3602 * seen multiple hangs with the GPU head pointer stuck in a
3603 * batchbuffer bound at the last page of the aperture. One page
3604 * should be enough to keep any prefetching inside of the
3605 * aperture.
3606 */
3607 i915_gem_init_global_gtt(dev, 0, mappable_size,
3608 gtt_size);
3609 }
3610
3611 ret = i915_gem_init_hw(dev);
3612 mutex_unlock(&dev->struct_mutex);
3613 if (ret) {
3614 i915_gem_cleanup_aliasing_ppgtt(dev);
3615 return ret;
3616 }
3617
3618 /* Allow hardware batchbuffers unless told otherwise, but not for KMS. */
3619 if (!drm_core_check_feature(dev, DRIVER_MODESET))
3620 dev_priv->dri1.allow_batchbuffer = 1;
3621 return 0;
3622}
3623
3624void
3625i915_gem_cleanup_ringbuffer(struct drm_device *dev)
3626{
3627 drm_i915_private_t *dev_priv = dev->dev_private;
3628 struct intel_ring_buffer *ring;
3629 int i;
3630
3631 for_each_ring(ring, dev_priv, i)
3632 intel_cleanup_ring_buffer(ring);
3633}
3634
3635int
3636i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
3637 struct drm_file *file_priv)
3638{
3639 drm_i915_private_t *dev_priv = dev->dev_private;
3640 int ret;
3641
3642 if (drm_core_check_feature(dev, DRIVER_MODESET))
3643 return 0;
3644
3645 if (atomic_read(&dev_priv->mm.wedged)) {
3646 DRM_ERROR("Reenabling wedged hardware, good luck\n");
3647 atomic_set(&dev_priv->mm.wedged, 0);
3648 }
3649
3650 mutex_lock(&dev->struct_mutex);
3651 dev_priv->mm.suspended = 0;
3652
3653 ret = i915_gem_init_hw(dev);
3654 if (ret != 0) {
3655 mutex_unlock(&dev->struct_mutex);
3656 return ret;
3657 }
3658
3659 BUG_ON(!list_empty(&dev_priv->mm.active_list));
3660 BUG_ON(!list_empty(&dev_priv->mm.flushing_list));
3661 BUG_ON(!list_empty(&dev_priv->mm.inactive_list));
3662 mutex_unlock(&dev->struct_mutex);
3663
3664 ret = drm_irq_install(dev);
3665 if (ret)
3666 goto cleanup_ringbuffer;
3667
3668 return 0;
3669
3670cleanup_ringbuffer:
3671 mutex_lock(&dev->struct_mutex);
3672 i915_gem_cleanup_ringbuffer(dev);
3673 dev_priv->mm.suspended = 1;
3674 mutex_unlock(&dev->struct_mutex);
3675
3676 return ret;
3677}
3678
3679int
3680i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
3681 struct drm_file *file_priv)
3682{
3683 if (drm_core_check_feature(dev, DRIVER_MODESET))
3684 return 0;
3685
3686 drm_irq_uninstall(dev);
3687 return i915_gem_idle(dev);
3688}
3689
3690void
3691i915_gem_lastclose(struct drm_device *dev)
3692{
3693 int ret;
3694
3695 if (drm_core_check_feature(dev, DRIVER_MODESET))
3696 return;
3697
3698 ret = i915_gem_idle(dev);
3699 if (ret)
3700 DRM_ERROR("failed to idle hardware: %d\n", ret);
3701}
3702
3703static void
3704init_ring_lists(struct intel_ring_buffer *ring)
3705{
3706 INIT_LIST_HEAD(&ring->active_list);
3707 INIT_LIST_HEAD(&ring->request_list);
3708 INIT_LIST_HEAD(&ring->gpu_write_list);
3709}
3710
3711void
3712i915_gem_load(struct drm_device *dev)
3713{
3714 int i;
3715 drm_i915_private_t *dev_priv = dev->dev_private;
3716
3717 INIT_LIST_HEAD(&dev_priv->mm.active_list);
3718 INIT_LIST_HEAD(&dev_priv->mm.flushing_list);
3719 INIT_LIST_HEAD(&dev_priv->mm.inactive_list);
3720 INIT_LIST_HEAD(&dev_priv->mm.fence_list);
3721 INIT_LIST_HEAD(&dev_priv->mm.gtt_list);
3722 for (i = 0; i < I915_NUM_RINGS; i++)
3723 init_ring_lists(&dev_priv->ring[i]);
3724 for (i = 0; i < I915_MAX_NUM_FENCES; i++)
3725 INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list);
3726 INIT_DELAYED_WORK(&dev_priv->mm.retire_work,
3727 i915_gem_retire_work_handler);
3728 init_completion(&dev_priv->error_completion);
3729
3730 /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
3731 if (IS_GEN3(dev)) {
3732 I915_WRITE(MI_ARB_STATE,
3733 _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE));
3734 }
3735
3736 dev_priv->relative_constants_mode = I915_EXEC_CONSTANTS_REL_GENERAL;
3737
3738 /* Old X drivers will take 0-2 for front, back, depth buffers */
3739 if (!drm_core_check_feature(dev, DRIVER_MODESET))
3740 dev_priv->fence_reg_start = 3;
3741
3742 if (INTEL_INFO(dev)->gen >= 4 || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
3743 dev_priv->num_fence_regs = 16;
3744 else
3745 dev_priv->num_fence_regs = 8;
3746
3747 /* Initialize fence registers to zero */
3748 i915_gem_reset_fences(dev);
3749
3750 i915_gem_detect_bit_6_swizzle(dev);
3751 init_waitqueue_head(&dev_priv->pending_flip_queue);
3752
3753 dev_priv->mm.interruptible = true;
3754
3755 dev_priv->mm.inactive_shrinker.shrink = i915_gem_inactive_shrink;
3756 dev_priv->mm.inactive_shrinker.seeks = DEFAULT_SEEKS;
3757 register_shrinker(&dev_priv->mm.inactive_shrinker);
3758}
3759
3760/*
3761 * Create a physically contiguous memory object for this object
3762 * e.g. for cursor + overlay regs
3763 */
3764static int i915_gem_init_phys_object(struct drm_device *dev,
3765 int id, int size, int align)
3766{
3767 drm_i915_private_t *dev_priv = dev->dev_private;
3768 struct drm_i915_gem_phys_object *phys_obj;
3769 int ret;
3770
3771 if (dev_priv->mm.phys_objs[id - 1] || !size)
3772 return 0;
3773
3774 phys_obj = kzalloc(sizeof(struct drm_i915_gem_phys_object), GFP_KERNEL);
3775 if (!phys_obj)
3776 return -ENOMEM;
3777
3778 phys_obj->id = id;
3779
3780 phys_obj->handle = drm_pci_alloc(dev, size, align);
3781 if (!phys_obj->handle) {
3782 ret = -ENOMEM;
3783 goto kfree_obj;
3784 }
3785#ifdef CONFIG_X86
3786 set_memory_wc((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE);
3787#endif
3788
3789 dev_priv->mm.phys_objs[id - 1] = phys_obj;
3790
3791 return 0;
3792kfree_obj:
3793 kfree(phys_obj);
3794 return ret;
3795}
3796
3797static void i915_gem_free_phys_object(struct drm_device *dev, int id)
3798{
3799 drm_i915_private_t *dev_priv = dev->dev_private;
3800 struct drm_i915_gem_phys_object *phys_obj;
3801
3802 if (!dev_priv->mm.phys_objs[id - 1])
3803 return;
3804
3805 phys_obj = dev_priv->mm.phys_objs[id - 1];
3806 if (phys_obj->cur_obj) {
3807 i915_gem_detach_phys_object(dev, phys_obj->cur_obj);
3808 }
3809
3810#ifdef CONFIG_X86
3811 set_memory_wb((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE);
3812#endif
3813 drm_pci_free(dev, phys_obj->handle);
3814 kfree(phys_obj);
3815 dev_priv->mm.phys_objs[id - 1] = NULL;
3816}
3817
3818void i915_gem_free_all_phys_object(struct drm_device *dev)
3819{
3820 int i;
3821
3822 for (i = I915_GEM_PHYS_CURSOR_0; i <= I915_MAX_PHYS_OBJECT; i++)
3823 i915_gem_free_phys_object(dev, i);
3824}
3825
3826void i915_gem_detach_phys_object(struct drm_device *dev,
3827 struct drm_i915_gem_object *obj)
3828{
3829 struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping;
3830 char *vaddr;
3831 int i;
3832 int page_count;
3833
3834 if (!obj->phys_obj)
3835 return;
3836 vaddr = obj->phys_obj->handle->vaddr;
3837
3838 page_count = obj->base.size / PAGE_SIZE;
3839 for (i = 0; i < page_count; i++) {
3840 struct page *page = shmem_read_mapping_page(mapping, i);
3841 if (!IS_ERR(page)) {
3842 char *dst = kmap_atomic(page);
3843 memcpy(dst, vaddr + i*PAGE_SIZE, PAGE_SIZE);
3844 kunmap_atomic(dst);
3845
3846 drm_clflush_pages(&page, 1);
3847
3848 set_page_dirty(page);
3849 mark_page_accessed(page);
3850 page_cache_release(page);
3851 }
3852 }
3853 intel_gtt_chipset_flush();
3854
3855 obj->phys_obj->cur_obj = NULL;
3856 obj->phys_obj = NULL;
3857}
3858
3859int
3860i915_gem_attach_phys_object(struct drm_device *dev,
3861 struct drm_i915_gem_object *obj,
3862 int id,
3863 int align)
3864{
3865 struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping;
3866 drm_i915_private_t *dev_priv = dev->dev_private;
3867 int ret = 0;
3868 int page_count;
3869 int i;
3870
3871 if (id > I915_MAX_PHYS_OBJECT)
3872 return -EINVAL;
3873
3874 if (obj->phys_obj) {
3875 if (obj->phys_obj->id == id)
3876 return 0;
3877 i915_gem_detach_phys_object(dev, obj);
3878 }
3879
3880 /* create a new object */
3881 if (!dev_priv->mm.phys_objs[id - 1]) {
3882 ret = i915_gem_init_phys_object(dev, id,
3883 obj->base.size, align);
3884 if (ret) {
3885 DRM_ERROR("failed to init phys object %d size: %zu\n",
3886 id, obj->base.size);
3887 return ret;
3888 }
3889 }
3890
3891 /* bind to the object */
3892 obj->phys_obj = dev_priv->mm.phys_objs[id - 1];
3893 obj->phys_obj->cur_obj = obj;
3894
3895 page_count = obj->base.size / PAGE_SIZE;
3896
3897 for (i = 0; i < page_count; i++) {
3898 struct page *page;
3899 char *dst, *src;
3900
3901 page = shmem_read_mapping_page(mapping, i);
3902 if (IS_ERR(page))
3903 return PTR_ERR(page);
3904
3905 src = kmap_atomic(page);
3906 dst = obj->phys_obj->handle->vaddr + (i * PAGE_SIZE);
3907 memcpy(dst, src, PAGE_SIZE);
3908 kunmap_atomic(src);
3909
3910 mark_page_accessed(page);
3911 page_cache_release(page);
3912 }
3913
3914 return 0;
3915}
3916
3917static int
3918i915_gem_phys_pwrite(struct drm_device *dev,
3919 struct drm_i915_gem_object *obj,
3920 struct drm_i915_gem_pwrite *args,
3921 struct drm_file *file_priv)
3922{
3923 void *vaddr = obj->phys_obj->handle->vaddr + args->offset;
3924 char __user *user_data = (char __user *) (uintptr_t) args->data_ptr;
3925
3926 if (__copy_from_user_inatomic_nocache(vaddr, user_data, args->size)) {
3927 unsigned long unwritten;
3928
3929 /* The physical object once assigned is fixed for the lifetime
3930 * of the obj, so we can safely drop the lock and continue
3931 * to access vaddr.
3932 */
3933 mutex_unlock(&dev->struct_mutex);
3934 unwritten = copy_from_user(vaddr, user_data, args->size);
3935 mutex_lock(&dev->struct_mutex);
3936 if (unwritten)
3937 return -EFAULT;
3938 }
3939
3940 intel_gtt_chipset_flush();
3941 return 0;
3942}
3943
3944void i915_gem_release(struct drm_device *dev, struct drm_file *file)
3945{
3946 struct drm_i915_file_private *file_priv = file->driver_priv;
3947
3948 /* Clean up our request list when the client is going away, so that
3949 * later retire_requests won't dereference our soon-to-be-gone
3950 * file_priv.
3951 */
3952 spin_lock(&file_priv->mm.lock);
3953 while (!list_empty(&file_priv->mm.request_list)) {
3954 struct drm_i915_gem_request *request;
3955
3956 request = list_first_entry(&file_priv->mm.request_list,
3957 struct drm_i915_gem_request,
3958 client_list);
3959 list_del(&request->client_list);
3960 request->file_priv = NULL;
3961 }
3962 spin_unlock(&file_priv->mm.lock);
3963}
3964
3965static int
3966i915_gpu_is_active(struct drm_device *dev)
3967{
3968 drm_i915_private_t *dev_priv = dev->dev_private;
3969 int lists_empty;
3970
3971 lists_empty = list_empty(&dev_priv->mm.flushing_list) &&
3972 list_empty(&dev_priv->mm.active_list);
3973
3974 return !lists_empty;
3975}
3976
3977static int
3978i915_gem_inactive_shrink(struct shrinker *shrinker, struct shrink_control *sc)
3979{
3980 struct drm_i915_private *dev_priv =
3981 container_of(shrinker,
3982 struct drm_i915_private,
3983 mm.inactive_shrinker);
3984 struct drm_device *dev = dev_priv->dev;
3985 struct drm_i915_gem_object *obj, *next;
3986 int nr_to_scan = sc->nr_to_scan;
3987 int cnt;
3988
3989 if (!mutex_trylock(&dev->struct_mutex))
3990 return 0;
3991
3992 /* "fast-path" to count number of available objects */
3993 if (nr_to_scan == 0) {
3994 cnt = 0;
3995 list_for_each_entry(obj,
3996 &dev_priv->mm.inactive_list,
3997 mm_list)
3998 cnt++;
3999 mutex_unlock(&dev->struct_mutex);
4000 return cnt / 100 * sysctl_vfs_cache_pressure;
4001 }
4002
4003rescan:
4004 /* first scan for clean buffers */
4005 i915_gem_retire_requests(dev);
4006
4007 list_for_each_entry_safe(obj, next,
4008 &dev_priv->mm.inactive_list,
4009 mm_list) {
4010 if (i915_gem_object_is_purgeable(obj)) {
4011 if (i915_gem_object_unbind(obj) == 0 &&
4012 --nr_to_scan == 0)
4013 break;
4014 }
4015 }
4016
4017 /* second pass, evict/count anything still on the inactive list */
4018 cnt = 0;
4019 list_for_each_entry_safe(obj, next,
4020 &dev_priv->mm.inactive_list,
4021 mm_list) {
4022 if (nr_to_scan &&
4023 i915_gem_object_unbind(obj) == 0)
4024 nr_to_scan--;
4025 else
4026 cnt++;
4027 }
4028
4029 if (nr_to_scan && i915_gpu_is_active(dev)) {
4030 /*
4031 * We are desperate for pages, so as a last resort, wait
4032 * for the GPU to finish and discard whatever we can.
4033 * This has a dramatic impact to reduce the number of
4034 * OOM-killer events whilst running the GPU aggressively.
4035 */
4036 if (i915_gpu_idle(dev) == 0)
4037 goto rescan;
4038 }
4039 mutex_unlock(&dev->struct_mutex);
4040 return cnt / 100 * sysctl_vfs_cache_pressure;
4041}