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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * gadget.c - DesignWare USB3 DRD Controller Gadget Framework Link
4 *
5 * Copyright (C) 2010-2011 Texas Instruments Incorporated - https://www.ti.com
6 *
7 * Authors: Felipe Balbi <balbi@ti.com>,
8 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
9 */
10
11#include <linux/kernel.h>
12#include <linux/delay.h>
13#include <linux/slab.h>
14#include <linux/spinlock.h>
15#include <linux/platform_device.h>
16#include <linux/pm_runtime.h>
17#include <linux/interrupt.h>
18#include <linux/io.h>
19#include <linux/list.h>
20#include <linux/dma-mapping.h>
21
22#include <linux/usb/ch9.h>
23#include <linux/usb/gadget.h>
24
25#include "debug.h"
26#include "core.h"
27#include "gadget.h"
28#include "io.h"
29
30#define DWC3_ALIGN_FRAME(d, n) (((d)->frame_number + ((d)->interval * (n))) \
31 & ~((d)->interval - 1))
32
33/**
34 * dwc3_gadget_set_test_mode - enables usb2 test modes
35 * @dwc: pointer to our context structure
36 * @mode: the mode to set (J, K SE0 NAK, Force Enable)
37 *
38 * Caller should take care of locking. This function will return 0 on
39 * success or -EINVAL if wrong Test Selector is passed.
40 */
41int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode)
42{
43 u32 reg;
44
45 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
46 reg &= ~DWC3_DCTL_TSTCTRL_MASK;
47
48 switch (mode) {
49 case USB_TEST_J:
50 case USB_TEST_K:
51 case USB_TEST_SE0_NAK:
52 case USB_TEST_PACKET:
53 case USB_TEST_FORCE_ENABLE:
54 reg |= mode << 1;
55 break;
56 default:
57 return -EINVAL;
58 }
59
60 dwc3_gadget_dctl_write_safe(dwc, reg);
61
62 return 0;
63}
64
65/**
66 * dwc3_gadget_get_link_state - gets current state of usb link
67 * @dwc: pointer to our context structure
68 *
69 * Caller should take care of locking. This function will
70 * return the link state on success (>= 0) or -ETIMEDOUT.
71 */
72int dwc3_gadget_get_link_state(struct dwc3 *dwc)
73{
74 u32 reg;
75
76 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
77
78 return DWC3_DSTS_USBLNKST(reg);
79}
80
81/**
82 * dwc3_gadget_set_link_state - sets usb link to a particular state
83 * @dwc: pointer to our context structure
84 * @state: the state to put link into
85 *
86 * Caller should take care of locking. This function will
87 * return 0 on success or -ETIMEDOUT.
88 */
89int dwc3_gadget_set_link_state(struct dwc3 *dwc, enum dwc3_link_state state)
90{
91 int retries = 10000;
92 u32 reg;
93
94 /*
95 * Wait until device controller is ready. Only applies to 1.94a and
96 * later RTL.
97 */
98 if (!DWC3_VER_IS_PRIOR(DWC3, 194A)) {
99 while (--retries) {
100 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
101 if (reg & DWC3_DSTS_DCNRD)
102 udelay(5);
103 else
104 break;
105 }
106
107 if (retries <= 0)
108 return -ETIMEDOUT;
109 }
110
111 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
112 reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;
113
114 /* set no action before sending new link state change */
115 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
116
117 /* set requested state */
118 reg |= DWC3_DCTL_ULSTCHNGREQ(state);
119 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
120
121 /*
122 * The following code is racy when called from dwc3_gadget_wakeup,
123 * and is not needed, at least on newer versions
124 */
125 if (!DWC3_VER_IS_PRIOR(DWC3, 194A))
126 return 0;
127
128 /* wait for a change in DSTS */
129 retries = 10000;
130 while (--retries) {
131 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
132
133 if (DWC3_DSTS_USBLNKST(reg) == state)
134 return 0;
135
136 udelay(5);
137 }
138
139 return -ETIMEDOUT;
140}
141
142static void dwc3_ep0_reset_state(struct dwc3 *dwc)
143{
144 unsigned int dir;
145
146 if (dwc->ep0state != EP0_SETUP_PHASE) {
147 dir = !!dwc->ep0_expect_in;
148 if (dwc->ep0state == EP0_DATA_PHASE)
149 dwc3_ep0_end_control_data(dwc, dwc->eps[dir]);
150 else
151 dwc3_ep0_end_control_data(dwc, dwc->eps[!dir]);
152
153 dwc->eps[0]->trb_enqueue = 0;
154 dwc->eps[1]->trb_enqueue = 0;
155
156 dwc3_ep0_stall_and_restart(dwc);
157 }
158}
159
160/**
161 * dwc3_ep_inc_trb - increment a trb index.
162 * @index: Pointer to the TRB index to increment.
163 *
164 * The index should never point to the link TRB. After incrementing,
165 * if it is point to the link TRB, wrap around to the beginning. The
166 * link TRB is always at the last TRB entry.
167 */
168static void dwc3_ep_inc_trb(u8 *index)
169{
170 (*index)++;
171 if (*index == (DWC3_TRB_NUM - 1))
172 *index = 0;
173}
174
175/**
176 * dwc3_ep_inc_enq - increment endpoint's enqueue pointer
177 * @dep: The endpoint whose enqueue pointer we're incrementing
178 */
179static void dwc3_ep_inc_enq(struct dwc3_ep *dep)
180{
181 dwc3_ep_inc_trb(&dep->trb_enqueue);
182}
183
184/**
185 * dwc3_ep_inc_deq - increment endpoint's dequeue pointer
186 * @dep: The endpoint whose enqueue pointer we're incrementing
187 */
188static void dwc3_ep_inc_deq(struct dwc3_ep *dep)
189{
190 dwc3_ep_inc_trb(&dep->trb_dequeue);
191}
192
193static void dwc3_gadget_del_and_unmap_request(struct dwc3_ep *dep,
194 struct dwc3_request *req, int status)
195{
196 struct dwc3 *dwc = dep->dwc;
197
198 list_del(&req->list);
199 req->remaining = 0;
200 req->num_trbs = 0;
201
202 if (req->request.status == -EINPROGRESS)
203 req->request.status = status;
204
205 if (req->trb)
206 usb_gadget_unmap_request_by_dev(dwc->sysdev,
207 &req->request, req->direction);
208
209 req->trb = NULL;
210 trace_dwc3_gadget_giveback(req);
211
212 if (dep->number > 1)
213 pm_runtime_put(dwc->dev);
214}
215
216/**
217 * dwc3_gadget_giveback - call struct usb_request's ->complete callback
218 * @dep: The endpoint to whom the request belongs to
219 * @req: The request we're giving back
220 * @status: completion code for the request
221 *
222 * Must be called with controller's lock held and interrupts disabled. This
223 * function will unmap @req and call its ->complete() callback to notify upper
224 * layers that it has completed.
225 */
226void dwc3_gadget_giveback(struct dwc3_ep *dep, struct dwc3_request *req,
227 int status)
228{
229 struct dwc3 *dwc = dep->dwc;
230
231 dwc3_gadget_del_and_unmap_request(dep, req, status);
232 req->status = DWC3_REQUEST_STATUS_COMPLETED;
233
234 spin_unlock(&dwc->lock);
235 usb_gadget_giveback_request(&dep->endpoint, &req->request);
236 spin_lock(&dwc->lock);
237}
238
239/**
240 * dwc3_send_gadget_generic_command - issue a generic command for the controller
241 * @dwc: pointer to the controller context
242 * @cmd: the command to be issued
243 * @param: command parameter
244 *
245 * Caller should take care of locking. Issue @cmd with a given @param to @dwc
246 * and wait for its completion.
247 */
248int dwc3_send_gadget_generic_command(struct dwc3 *dwc, unsigned int cmd,
249 u32 param)
250{
251 u32 timeout = 500;
252 int status = 0;
253 int ret = 0;
254 u32 reg;
255
256 dwc3_writel(dwc->regs, DWC3_DGCMDPAR, param);
257 dwc3_writel(dwc->regs, DWC3_DGCMD, cmd | DWC3_DGCMD_CMDACT);
258
259 do {
260 reg = dwc3_readl(dwc->regs, DWC3_DGCMD);
261 if (!(reg & DWC3_DGCMD_CMDACT)) {
262 status = DWC3_DGCMD_STATUS(reg);
263 if (status)
264 ret = -EINVAL;
265 break;
266 }
267 } while (--timeout);
268
269 if (!timeout) {
270 ret = -ETIMEDOUT;
271 status = -ETIMEDOUT;
272 }
273
274 trace_dwc3_gadget_generic_cmd(cmd, param, status);
275
276 return ret;
277}
278
279static int __dwc3_gadget_wakeup(struct dwc3 *dwc, bool async);
280
281/**
282 * dwc3_send_gadget_ep_cmd - issue an endpoint command
283 * @dep: the endpoint to which the command is going to be issued
284 * @cmd: the command to be issued
285 * @params: parameters to the command
286 *
287 * Caller should handle locking. This function will issue @cmd with given
288 * @params to @dep and wait for its completion.
289 *
290 * According to the programming guide, if the link state is in L1/L2/U3,
291 * then sending the Start Transfer command may not complete. The
292 * programming guide suggested to bring the link state back to ON/U0 by
293 * performing remote wakeup prior to sending the command. However, don't
294 * initiate remote wakeup when the user/function does not send wakeup
295 * request via wakeup ops. Send the command when it's allowed.
296 *
297 * Notes:
298 * For L1 link state, issuing a command requires the clearing of
299 * GUSB2PHYCFG.SUSPENDUSB2, which turns on the signal required to complete
300 * the given command (usually within 50us). This should happen within the
301 * command timeout set by driver. No additional step is needed.
302 *
303 * For L2 or U3 link state, the gadget is in USB suspend. Care should be
304 * taken when sending Start Transfer command to ensure that it's done after
305 * USB resume.
306 */
307int dwc3_send_gadget_ep_cmd(struct dwc3_ep *dep, unsigned int cmd,
308 struct dwc3_gadget_ep_cmd_params *params)
309{
310 const struct usb_endpoint_descriptor *desc = dep->endpoint.desc;
311 struct dwc3 *dwc = dep->dwc;
312 u32 timeout = 5000;
313 u32 saved_config = 0;
314 u32 reg;
315
316 int cmd_status = 0;
317 int ret = -EINVAL;
318
319 /*
320 * When operating in USB 2.0 speeds (HS/FS), if GUSB2PHYCFG.ENBLSLPM or
321 * GUSB2PHYCFG.SUSPHY is set, it must be cleared before issuing an
322 * endpoint command.
323 *
324 * Save and clear both GUSB2PHYCFG.ENBLSLPM and GUSB2PHYCFG.SUSPHY
325 * settings. Restore them after the command is completed.
326 *
327 * DWC_usb3 3.30a and DWC_usb31 1.90a programming guide section 3.2.2
328 */
329 if (dwc->gadget->speed <= USB_SPEED_HIGH ||
330 DWC3_DEPCMD_CMD(cmd) == DWC3_DEPCMD_ENDTRANSFER) {
331 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
332 if (unlikely(reg & DWC3_GUSB2PHYCFG_SUSPHY)) {
333 saved_config |= DWC3_GUSB2PHYCFG_SUSPHY;
334 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
335 }
336
337 if (reg & DWC3_GUSB2PHYCFG_ENBLSLPM) {
338 saved_config |= DWC3_GUSB2PHYCFG_ENBLSLPM;
339 reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM;
340 }
341
342 if (saved_config)
343 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
344 }
345
346 /*
347 * For some commands such as Update Transfer command, DEPCMDPARn
348 * registers are reserved. Since the driver often sends Update Transfer
349 * command, don't write to DEPCMDPARn to avoid register write delays and
350 * improve performance.
351 */
352 if (DWC3_DEPCMD_CMD(cmd) != DWC3_DEPCMD_UPDATETRANSFER) {
353 dwc3_writel(dep->regs, DWC3_DEPCMDPAR0, params->param0);
354 dwc3_writel(dep->regs, DWC3_DEPCMDPAR1, params->param1);
355 dwc3_writel(dep->regs, DWC3_DEPCMDPAR2, params->param2);
356 }
357
358 /*
359 * Synopsys Databook 2.60a states in section 6.3.2.5.6 of that if we're
360 * not relying on XferNotReady, we can make use of a special "No
361 * Response Update Transfer" command where we should clear both CmdAct
362 * and CmdIOC bits.
363 *
364 * With this, we don't need to wait for command completion and can
365 * straight away issue further commands to the endpoint.
366 *
367 * NOTICE: We're making an assumption that control endpoints will never
368 * make use of Update Transfer command. This is a safe assumption
369 * because we can never have more than one request at a time with
370 * Control Endpoints. If anybody changes that assumption, this chunk
371 * needs to be updated accordingly.
372 */
373 if (DWC3_DEPCMD_CMD(cmd) == DWC3_DEPCMD_UPDATETRANSFER &&
374 !usb_endpoint_xfer_isoc(desc))
375 cmd &= ~(DWC3_DEPCMD_CMDIOC | DWC3_DEPCMD_CMDACT);
376 else
377 cmd |= DWC3_DEPCMD_CMDACT;
378
379 dwc3_writel(dep->regs, DWC3_DEPCMD, cmd);
380
381 if (!(cmd & DWC3_DEPCMD_CMDACT) ||
382 (DWC3_DEPCMD_CMD(cmd) == DWC3_DEPCMD_ENDTRANSFER &&
383 !(cmd & DWC3_DEPCMD_CMDIOC))) {
384 ret = 0;
385 goto skip_status;
386 }
387
388 do {
389 reg = dwc3_readl(dep->regs, DWC3_DEPCMD);
390 if (!(reg & DWC3_DEPCMD_CMDACT)) {
391 cmd_status = DWC3_DEPCMD_STATUS(reg);
392
393 switch (cmd_status) {
394 case 0:
395 ret = 0;
396 break;
397 case DEPEVT_TRANSFER_NO_RESOURCE:
398 dev_WARN(dwc->dev, "No resource for %s\n",
399 dep->name);
400 ret = -EINVAL;
401 break;
402 case DEPEVT_TRANSFER_BUS_EXPIRY:
403 /*
404 * SW issues START TRANSFER command to
405 * isochronous ep with future frame interval. If
406 * future interval time has already passed when
407 * core receives the command, it will respond
408 * with an error status of 'Bus Expiry'.
409 *
410 * Instead of always returning -EINVAL, let's
411 * give a hint to the gadget driver that this is
412 * the case by returning -EAGAIN.
413 */
414 ret = -EAGAIN;
415 break;
416 default:
417 dev_WARN(dwc->dev, "UNKNOWN cmd status\n");
418 }
419
420 break;
421 }
422 } while (--timeout);
423
424 if (timeout == 0) {
425 ret = -ETIMEDOUT;
426 cmd_status = -ETIMEDOUT;
427 }
428
429skip_status:
430 trace_dwc3_gadget_ep_cmd(dep, cmd, params, cmd_status);
431
432 if (DWC3_DEPCMD_CMD(cmd) == DWC3_DEPCMD_STARTTRANSFER) {
433 if (ret == 0)
434 dep->flags |= DWC3_EP_TRANSFER_STARTED;
435
436 if (ret != -ETIMEDOUT)
437 dwc3_gadget_ep_get_transfer_index(dep);
438 }
439
440 if (DWC3_DEPCMD_CMD(cmd) == DWC3_DEPCMD_ENDTRANSFER &&
441 !(cmd & DWC3_DEPCMD_CMDIOC))
442 mdelay(1);
443
444 if (saved_config) {
445 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
446 reg |= saved_config;
447 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
448 }
449
450 return ret;
451}
452
453static int dwc3_send_clear_stall_ep_cmd(struct dwc3_ep *dep)
454{
455 struct dwc3 *dwc = dep->dwc;
456 struct dwc3_gadget_ep_cmd_params params;
457 u32 cmd = DWC3_DEPCMD_CLEARSTALL;
458
459 /*
460 * As of core revision 2.60a the recommended programming model
461 * is to set the ClearPendIN bit when issuing a Clear Stall EP
462 * command for IN endpoints. This is to prevent an issue where
463 * some (non-compliant) hosts may not send ACK TPs for pending
464 * IN transfers due to a mishandled error condition. Synopsys
465 * STAR 9000614252.
466 */
467 if (dep->direction &&
468 !DWC3_VER_IS_PRIOR(DWC3, 260A) &&
469 (dwc->gadget->speed >= USB_SPEED_SUPER))
470 cmd |= DWC3_DEPCMD_CLEARPENDIN;
471
472 memset(¶ms, 0, sizeof(params));
473
474 return dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms);
475}
476
477static dma_addr_t dwc3_trb_dma_offset(struct dwc3_ep *dep,
478 struct dwc3_trb *trb)
479{
480 u32 offset = (char *) trb - (char *) dep->trb_pool;
481
482 return dep->trb_pool_dma + offset;
483}
484
485static int dwc3_alloc_trb_pool(struct dwc3_ep *dep)
486{
487 struct dwc3 *dwc = dep->dwc;
488
489 if (dep->trb_pool)
490 return 0;
491
492 dep->trb_pool = dma_alloc_coherent(dwc->sysdev,
493 sizeof(struct dwc3_trb) * DWC3_TRB_NUM,
494 &dep->trb_pool_dma, GFP_KERNEL);
495 if (!dep->trb_pool) {
496 dev_err(dep->dwc->dev, "failed to allocate trb pool for %s\n",
497 dep->name);
498 return -ENOMEM;
499 }
500
501 return 0;
502}
503
504static void dwc3_free_trb_pool(struct dwc3_ep *dep)
505{
506 struct dwc3 *dwc = dep->dwc;
507
508 dma_free_coherent(dwc->sysdev, sizeof(struct dwc3_trb) * DWC3_TRB_NUM,
509 dep->trb_pool, dep->trb_pool_dma);
510
511 dep->trb_pool = NULL;
512 dep->trb_pool_dma = 0;
513}
514
515static int dwc3_gadget_set_xfer_resource(struct dwc3_ep *dep)
516{
517 struct dwc3_gadget_ep_cmd_params params;
518 int ret;
519
520 if (dep->flags & DWC3_EP_RESOURCE_ALLOCATED)
521 return 0;
522
523 memset(¶ms, 0x00, sizeof(params));
524
525 params.param0 = DWC3_DEPXFERCFG_NUM_XFER_RES(1);
526
527 ret = dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_SETTRANSFRESOURCE,
528 ¶ms);
529 if (ret)
530 return ret;
531
532 dep->flags |= DWC3_EP_RESOURCE_ALLOCATED;
533 return 0;
534}
535
536/**
537 * dwc3_gadget_start_config - reset endpoint resources
538 * @dwc: pointer to the DWC3 context
539 * @resource_index: DEPSTARTCFG.XferRscIdx value (must be 0 or 2)
540 *
541 * Set resource_index=0 to reset all endpoints' resources allocation. Do this as
542 * part of the power-on/soft-reset initialization.
543 *
544 * Set resource_index=2 to reset only non-control endpoints' resources. Do this
545 * on receiving the SET_CONFIGURATION request or hibernation resume.
546 */
547int dwc3_gadget_start_config(struct dwc3 *dwc, unsigned int resource_index)
548{
549 struct dwc3_gadget_ep_cmd_params params;
550 u32 cmd;
551 int i;
552 int ret;
553
554 if (resource_index != 0 && resource_index != 2)
555 return -EINVAL;
556
557 memset(¶ms, 0x00, sizeof(params));
558 cmd = DWC3_DEPCMD_DEPSTARTCFG;
559 cmd |= DWC3_DEPCMD_PARAM(resource_index);
560
561 ret = dwc3_send_gadget_ep_cmd(dwc->eps[0], cmd, ¶ms);
562 if (ret)
563 return ret;
564
565 /* Reset resource allocation flags */
566 for (i = resource_index; i < dwc->num_eps && dwc->eps[i]; i++)
567 dwc->eps[i]->flags &= ~DWC3_EP_RESOURCE_ALLOCATED;
568
569 return 0;
570}
571
572static int dwc3_gadget_set_ep_config(struct dwc3_ep *dep, unsigned int action)
573{
574 const struct usb_ss_ep_comp_descriptor *comp_desc;
575 const struct usb_endpoint_descriptor *desc;
576 struct dwc3_gadget_ep_cmd_params params;
577 struct dwc3 *dwc = dep->dwc;
578
579 comp_desc = dep->endpoint.comp_desc;
580 desc = dep->endpoint.desc;
581
582 memset(¶ms, 0x00, sizeof(params));
583
584 params.param0 = DWC3_DEPCFG_EP_TYPE(usb_endpoint_type(desc))
585 | DWC3_DEPCFG_MAX_PACKET_SIZE(usb_endpoint_maxp(desc));
586
587 /* Burst size is only needed in SuperSpeed mode */
588 if (dwc->gadget->speed >= USB_SPEED_SUPER) {
589 u32 burst = dep->endpoint.maxburst;
590
591 params.param0 |= DWC3_DEPCFG_BURST_SIZE(burst - 1);
592 }
593
594 params.param0 |= action;
595 if (action == DWC3_DEPCFG_ACTION_RESTORE)
596 params.param2 |= dep->saved_state;
597
598 if (usb_endpoint_xfer_control(desc))
599 params.param1 = DWC3_DEPCFG_XFER_COMPLETE_EN;
600
601 if (dep->number <= 1 || usb_endpoint_xfer_isoc(desc))
602 params.param1 |= DWC3_DEPCFG_XFER_NOT_READY_EN;
603
604 if (usb_ss_max_streams(comp_desc) && usb_endpoint_xfer_bulk(desc)) {
605 params.param1 |= DWC3_DEPCFG_STREAM_CAPABLE
606 | DWC3_DEPCFG_XFER_COMPLETE_EN
607 | DWC3_DEPCFG_STREAM_EVENT_EN;
608 dep->stream_capable = true;
609 }
610
611 if (!usb_endpoint_xfer_control(desc))
612 params.param1 |= DWC3_DEPCFG_XFER_IN_PROGRESS_EN;
613
614 /*
615 * We are doing 1:1 mapping for endpoints, meaning
616 * Physical Endpoints 2 maps to Logical Endpoint 2 and
617 * so on. We consider the direction bit as part of the physical
618 * endpoint number. So USB endpoint 0x81 is 0x03.
619 */
620 params.param1 |= DWC3_DEPCFG_EP_NUMBER(dep->number);
621
622 /*
623 * We must use the lower 16 TX FIFOs even though
624 * HW might have more
625 */
626 if (dep->direction)
627 params.param0 |= DWC3_DEPCFG_FIFO_NUMBER(dep->number >> 1);
628
629 if (desc->bInterval) {
630 u8 bInterval_m1;
631
632 /*
633 * Valid range for DEPCFG.bInterval_m1 is from 0 to 13.
634 *
635 * NOTE: The programming guide incorrectly stated bInterval_m1
636 * must be set to 0 when operating in fullspeed. Internally the
637 * controller does not have this limitation. See DWC_usb3x
638 * programming guide section 3.2.2.1.
639 */
640 bInterval_m1 = min_t(u8, desc->bInterval - 1, 13);
641
642 if (usb_endpoint_type(desc) == USB_ENDPOINT_XFER_INT &&
643 dwc->gadget->speed == USB_SPEED_FULL)
644 dep->interval = desc->bInterval;
645 else
646 dep->interval = 1 << (desc->bInterval - 1);
647
648 params.param1 |= DWC3_DEPCFG_BINTERVAL_M1(bInterval_m1);
649 }
650
651 return dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_SETEPCONFIG, ¶ms);
652}
653
654/**
655 * dwc3_gadget_calc_tx_fifo_size - calculates the txfifo size value
656 * @dwc: pointer to the DWC3 context
657 * @mult: multiplier to be used when calculating the fifo_size
658 *
659 * Calculates the size value based on the equation below:
660 *
661 * DWC3 revision 280A and prior:
662 * fifo_size = mult * (max_packet / mdwidth) + 1;
663 *
664 * DWC3 revision 290A and onwards:
665 * fifo_size = mult * ((max_packet + mdwidth)/mdwidth + 1) + 1
666 *
667 * The max packet size is set to 1024, as the txfifo requirements mainly apply
668 * to super speed USB use cases. However, it is safe to overestimate the fifo
669 * allocations for other scenarios, i.e. high speed USB.
670 */
671static int dwc3_gadget_calc_tx_fifo_size(struct dwc3 *dwc, int mult)
672{
673 int max_packet = 1024;
674 int fifo_size;
675 int mdwidth;
676
677 mdwidth = dwc3_mdwidth(dwc);
678
679 /* MDWIDTH is represented in bits, we need it in bytes */
680 mdwidth >>= 3;
681
682 if (DWC3_VER_IS_PRIOR(DWC3, 290A))
683 fifo_size = mult * (max_packet / mdwidth) + 1;
684 else
685 fifo_size = mult * ((max_packet + mdwidth) / mdwidth) + 1;
686 return fifo_size;
687}
688
689/**
690 * dwc3_gadget_calc_ram_depth - calculates the ram depth for txfifo
691 * @dwc: pointer to the DWC3 context
692 */
693static int dwc3_gadget_calc_ram_depth(struct dwc3 *dwc)
694{
695 int ram_depth;
696 int fifo_0_start;
697 bool is_single_port_ram;
698
699 /* Check supporting RAM type by HW */
700 is_single_port_ram = DWC3_SPRAM_TYPE(dwc->hwparams.hwparams1);
701
702 /*
703 * If a single port RAM is utilized, then allocate TxFIFOs from
704 * RAM0. otherwise, allocate them from RAM1.
705 */
706 ram_depth = is_single_port_ram ? DWC3_RAM0_DEPTH(dwc->hwparams.hwparams6) :
707 DWC3_RAM1_DEPTH(dwc->hwparams.hwparams7);
708
709 /*
710 * In a single port RAM configuration, the available RAM is shared
711 * between the RX and TX FIFOs. This means that the txfifo can begin
712 * at a non-zero address.
713 */
714 if (is_single_port_ram) {
715 u32 reg;
716
717 /* Check if TXFIFOs start at non-zero addr */
718 reg = dwc3_readl(dwc->regs, DWC3_GTXFIFOSIZ(0));
719 fifo_0_start = DWC3_GTXFIFOSIZ_TXFSTADDR(reg);
720
721 ram_depth -= (fifo_0_start >> 16);
722 }
723
724 return ram_depth;
725}
726
727/**
728 * dwc3_gadget_clear_tx_fifos - Clears txfifo allocation
729 * @dwc: pointer to the DWC3 context
730 *
731 * Iterates through all the endpoint registers and clears the previous txfifo
732 * allocations.
733 */
734void dwc3_gadget_clear_tx_fifos(struct dwc3 *dwc)
735{
736 struct dwc3_ep *dep;
737 int fifo_depth;
738 int size;
739 int num;
740
741 if (!dwc->do_fifo_resize)
742 return;
743
744 /* Read ep0IN related TXFIFO size */
745 dep = dwc->eps[1];
746 size = dwc3_readl(dwc->regs, DWC3_GTXFIFOSIZ(0));
747 if (DWC3_IP_IS(DWC3))
748 fifo_depth = DWC3_GTXFIFOSIZ_TXFDEP(size);
749 else
750 fifo_depth = DWC31_GTXFIFOSIZ_TXFDEP(size);
751
752 dwc->last_fifo_depth = fifo_depth;
753 /* Clear existing TXFIFO for all IN eps except ep0 */
754 for (num = 3; num < min_t(int, dwc->num_eps, DWC3_ENDPOINTS_NUM);
755 num += 2) {
756 dep = dwc->eps[num];
757 /* Don't change TXFRAMNUM on usb31 version */
758 size = DWC3_IP_IS(DWC3) ? 0 :
759 dwc3_readl(dwc->regs, DWC3_GTXFIFOSIZ(num >> 1)) &
760 DWC31_GTXFIFOSIZ_TXFRAMNUM;
761
762 dwc3_writel(dwc->regs, DWC3_GTXFIFOSIZ(num >> 1), size);
763 dep->flags &= ~DWC3_EP_TXFIFO_RESIZED;
764 }
765 dwc->num_ep_resized = 0;
766}
767
768/*
769 * dwc3_gadget_resize_tx_fifos - reallocate fifo spaces for current use-case
770 * @dwc: pointer to our context structure
771 *
772 * This function will a best effort FIFO allocation in order
773 * to improve FIFO usage and throughput, while still allowing
774 * us to enable as many endpoints as possible.
775 *
776 * Keep in mind that this operation will be highly dependent
777 * on the configured size for RAM1 - which contains TxFifo -,
778 * the amount of endpoints enabled on coreConsultant tool, and
779 * the width of the Master Bus.
780 *
781 * In general, FIFO depths are represented with the following equation:
782 *
783 * fifo_size = mult * ((max_packet + mdwidth)/mdwidth + 1) + 1
784 *
785 * In conjunction with dwc3_gadget_check_config(), this resizing logic will
786 * ensure that all endpoints will have enough internal memory for one max
787 * packet per endpoint.
788 */
789static int dwc3_gadget_resize_tx_fifos(struct dwc3_ep *dep)
790{
791 struct dwc3 *dwc = dep->dwc;
792 int fifo_0_start;
793 int ram_depth;
794 int fifo_size;
795 int min_depth;
796 int num_in_ep;
797 int remaining;
798 int num_fifos = 1;
799 int fifo;
800 int tmp;
801
802 if (!dwc->do_fifo_resize)
803 return 0;
804
805 /* resize IN endpoints except ep0 */
806 if (!usb_endpoint_dir_in(dep->endpoint.desc) || dep->number <= 1)
807 return 0;
808
809 /* bail if already resized */
810 if (dep->flags & DWC3_EP_TXFIFO_RESIZED)
811 return 0;
812
813 ram_depth = dwc3_gadget_calc_ram_depth(dwc);
814
815 switch (dwc->gadget->speed) {
816 case USB_SPEED_SUPER_PLUS:
817 case USB_SPEED_SUPER:
818 if (usb_endpoint_xfer_bulk(dep->endpoint.desc) ||
819 usb_endpoint_xfer_isoc(dep->endpoint.desc))
820 num_fifos = min_t(unsigned int,
821 dep->endpoint.maxburst,
822 dwc->tx_fifo_resize_max_num);
823 break;
824 case USB_SPEED_HIGH:
825 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
826 num_fifos = min_t(unsigned int,
827 usb_endpoint_maxp_mult(dep->endpoint.desc) + 1,
828 dwc->tx_fifo_resize_max_num);
829 break;
830 }
831 fallthrough;
832 case USB_SPEED_FULL:
833 if (usb_endpoint_xfer_bulk(dep->endpoint.desc))
834 num_fifos = 2;
835 break;
836 default:
837 break;
838 }
839
840 /* FIFO size for a single buffer */
841 fifo = dwc3_gadget_calc_tx_fifo_size(dwc, 1);
842
843 /* Calculate the number of remaining EPs w/o any FIFO */
844 num_in_ep = dwc->max_cfg_eps;
845 num_in_ep -= dwc->num_ep_resized;
846
847 /* Reserve at least one FIFO for the number of IN EPs */
848 min_depth = num_in_ep * (fifo + 1);
849 remaining = ram_depth - min_depth - dwc->last_fifo_depth;
850 remaining = max_t(int, 0, remaining);
851 /*
852 * We've already reserved 1 FIFO per EP, so check what we can fit in
853 * addition to it. If there is not enough remaining space, allocate
854 * all the remaining space to the EP.
855 */
856 fifo_size = (num_fifos - 1) * fifo;
857 if (remaining < fifo_size)
858 fifo_size = remaining;
859
860 fifo_size += fifo;
861 /* Last increment according to the TX FIFO size equation */
862 fifo_size++;
863
864 /* Check if TXFIFOs start at non-zero addr */
865 tmp = dwc3_readl(dwc->regs, DWC3_GTXFIFOSIZ(0));
866 fifo_0_start = DWC3_GTXFIFOSIZ_TXFSTADDR(tmp);
867
868 fifo_size |= (fifo_0_start + (dwc->last_fifo_depth << 16));
869 if (DWC3_IP_IS(DWC3))
870 dwc->last_fifo_depth += DWC3_GTXFIFOSIZ_TXFDEP(fifo_size);
871 else
872 dwc->last_fifo_depth += DWC31_GTXFIFOSIZ_TXFDEP(fifo_size);
873
874 /* Check fifo size allocation doesn't exceed available RAM size. */
875 if (dwc->last_fifo_depth >= ram_depth) {
876 dev_err(dwc->dev, "Fifosize(%d) > RAM size(%d) %s depth:%d\n",
877 dwc->last_fifo_depth, ram_depth,
878 dep->endpoint.name, fifo_size);
879 if (DWC3_IP_IS(DWC3))
880 fifo_size = DWC3_GTXFIFOSIZ_TXFDEP(fifo_size);
881 else
882 fifo_size = DWC31_GTXFIFOSIZ_TXFDEP(fifo_size);
883
884 dwc->last_fifo_depth -= fifo_size;
885 return -ENOMEM;
886 }
887
888 dwc3_writel(dwc->regs, DWC3_GTXFIFOSIZ(dep->number >> 1), fifo_size);
889 dep->flags |= DWC3_EP_TXFIFO_RESIZED;
890 dwc->num_ep_resized++;
891
892 return 0;
893}
894
895/**
896 * __dwc3_gadget_ep_enable - initializes a hw endpoint
897 * @dep: endpoint to be initialized
898 * @action: one of INIT, MODIFY or RESTORE
899 *
900 * Caller should take care of locking. Execute all necessary commands to
901 * initialize a HW endpoint so it can be used by a gadget driver.
902 */
903static int __dwc3_gadget_ep_enable(struct dwc3_ep *dep, unsigned int action)
904{
905 const struct usb_endpoint_descriptor *desc = dep->endpoint.desc;
906 struct dwc3 *dwc = dep->dwc;
907
908 u32 reg;
909 int ret;
910
911 if (!(dep->flags & DWC3_EP_ENABLED)) {
912 ret = dwc3_gadget_resize_tx_fifos(dep);
913 if (ret)
914 return ret;
915 }
916
917 ret = dwc3_gadget_set_ep_config(dep, action);
918 if (ret)
919 return ret;
920
921 if (!(dep->flags & DWC3_EP_RESOURCE_ALLOCATED)) {
922 ret = dwc3_gadget_set_xfer_resource(dep);
923 if (ret)
924 return ret;
925 }
926
927 if (!(dep->flags & DWC3_EP_ENABLED)) {
928 struct dwc3_trb *trb_st_hw;
929 struct dwc3_trb *trb_link;
930
931 dep->type = usb_endpoint_type(desc);
932 dep->flags |= DWC3_EP_ENABLED;
933
934 reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
935 reg |= DWC3_DALEPENA_EP(dep->number);
936 dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
937
938 dep->trb_dequeue = 0;
939 dep->trb_enqueue = 0;
940
941 if (usb_endpoint_xfer_control(desc))
942 goto out;
943
944 /* Initialize the TRB ring */
945 memset(dep->trb_pool, 0,
946 sizeof(struct dwc3_trb) * DWC3_TRB_NUM);
947
948 /* Link TRB. The HWO bit is never reset */
949 trb_st_hw = &dep->trb_pool[0];
950
951 trb_link = &dep->trb_pool[DWC3_TRB_NUM - 1];
952 trb_link->bpl = lower_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw));
953 trb_link->bph = upper_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw));
954 trb_link->ctrl |= DWC3_TRBCTL_LINK_TRB;
955 trb_link->ctrl |= DWC3_TRB_CTRL_HWO;
956 }
957
958 /*
959 * Issue StartTransfer here with no-op TRB so we can always rely on No
960 * Response Update Transfer command.
961 */
962 if (usb_endpoint_xfer_bulk(desc) ||
963 usb_endpoint_xfer_int(desc)) {
964 struct dwc3_gadget_ep_cmd_params params;
965 struct dwc3_trb *trb;
966 dma_addr_t trb_dma;
967 u32 cmd;
968
969 memset(¶ms, 0, sizeof(params));
970 trb = &dep->trb_pool[0];
971 trb_dma = dwc3_trb_dma_offset(dep, trb);
972
973 params.param0 = upper_32_bits(trb_dma);
974 params.param1 = lower_32_bits(trb_dma);
975
976 cmd = DWC3_DEPCMD_STARTTRANSFER;
977
978 ret = dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms);
979 if (ret < 0)
980 return ret;
981
982 if (dep->stream_capable) {
983 /*
984 * For streams, at start, there maybe a race where the
985 * host primes the endpoint before the function driver
986 * queues a request to initiate a stream. In that case,
987 * the controller will not see the prime to generate the
988 * ERDY and start stream. To workaround this, issue a
989 * no-op TRB as normal, but end it immediately. As a
990 * result, when the function driver queues the request,
991 * the next START_TRANSFER command will cause the
992 * controller to generate an ERDY to initiate the
993 * stream.
994 */
995 dwc3_stop_active_transfer(dep, true, true);
996
997 /*
998 * All stream eps will reinitiate stream on NoStream
999 * rejection until we can determine that the host can
1000 * prime after the first transfer.
1001 *
1002 * However, if the controller is capable of
1003 * TXF_FLUSH_BYPASS, then IN direction endpoints will
1004 * automatically restart the stream without the driver
1005 * initiation.
1006 */
1007 if (!dep->direction ||
1008 !(dwc->hwparams.hwparams9 &
1009 DWC3_GHWPARAMS9_DEV_TXF_FLUSH_BYPASS))
1010 dep->flags |= DWC3_EP_FORCE_RESTART_STREAM;
1011 }
1012 }
1013
1014out:
1015 trace_dwc3_gadget_ep_enable(dep);
1016
1017 return 0;
1018}
1019
1020void dwc3_remove_requests(struct dwc3 *dwc, struct dwc3_ep *dep, int status)
1021{
1022 struct dwc3_request *req;
1023
1024 dwc3_stop_active_transfer(dep, true, false);
1025
1026 /* If endxfer is delayed, avoid unmapping requests */
1027 if (dep->flags & DWC3_EP_DELAY_STOP)
1028 return;
1029
1030 /* - giveback all requests to gadget driver */
1031 while (!list_empty(&dep->started_list)) {
1032 req = next_request(&dep->started_list);
1033
1034 dwc3_gadget_giveback(dep, req, status);
1035 }
1036
1037 while (!list_empty(&dep->pending_list)) {
1038 req = next_request(&dep->pending_list);
1039
1040 dwc3_gadget_giveback(dep, req, status);
1041 }
1042
1043 while (!list_empty(&dep->cancelled_list)) {
1044 req = next_request(&dep->cancelled_list);
1045
1046 dwc3_gadget_giveback(dep, req, status);
1047 }
1048}
1049
1050/**
1051 * __dwc3_gadget_ep_disable - disables a hw endpoint
1052 * @dep: the endpoint to disable
1053 *
1054 * This function undoes what __dwc3_gadget_ep_enable did and also removes
1055 * requests which are currently being processed by the hardware and those which
1056 * are not yet scheduled.
1057 *
1058 * Caller should take care of locking.
1059 */
1060static int __dwc3_gadget_ep_disable(struct dwc3_ep *dep)
1061{
1062 struct dwc3 *dwc = dep->dwc;
1063 u32 reg;
1064 u32 mask;
1065
1066 trace_dwc3_gadget_ep_disable(dep);
1067
1068 /* make sure HW endpoint isn't stalled */
1069 if (dep->flags & DWC3_EP_STALL)
1070 __dwc3_gadget_ep_set_halt(dep, 0, false);
1071
1072 reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
1073 reg &= ~DWC3_DALEPENA_EP(dep->number);
1074 dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
1075
1076 dwc3_remove_requests(dwc, dep, -ESHUTDOWN);
1077
1078 dep->stream_capable = false;
1079 dep->type = 0;
1080 mask = DWC3_EP_TXFIFO_RESIZED | DWC3_EP_RESOURCE_ALLOCATED;
1081 /*
1082 * dwc3_remove_requests() can exit early if DWC3 EP delayed stop is
1083 * set. Do not clear DEP flags, so that the end transfer command will
1084 * be reattempted during the next SETUP stage.
1085 */
1086 if (dep->flags & DWC3_EP_DELAY_STOP)
1087 mask |= (DWC3_EP_DELAY_STOP | DWC3_EP_TRANSFER_STARTED);
1088 dep->flags &= mask;
1089
1090 /* Clear out the ep descriptors for non-ep0 */
1091 if (dep->number > 1) {
1092 dep->endpoint.comp_desc = NULL;
1093 dep->endpoint.desc = NULL;
1094 }
1095
1096 return 0;
1097}
1098
1099/* -------------------------------------------------------------------------- */
1100
1101static int dwc3_gadget_ep0_enable(struct usb_ep *ep,
1102 const struct usb_endpoint_descriptor *desc)
1103{
1104 return -EINVAL;
1105}
1106
1107static int dwc3_gadget_ep0_disable(struct usb_ep *ep)
1108{
1109 return -EINVAL;
1110}
1111
1112/* -------------------------------------------------------------------------- */
1113
1114static int dwc3_gadget_ep_enable(struct usb_ep *ep,
1115 const struct usb_endpoint_descriptor *desc)
1116{
1117 struct dwc3_ep *dep;
1118 struct dwc3 *dwc;
1119 unsigned long flags;
1120 int ret;
1121
1122 if (!ep || !desc || desc->bDescriptorType != USB_DT_ENDPOINT) {
1123 pr_debug("dwc3: invalid parameters\n");
1124 return -EINVAL;
1125 }
1126
1127 if (!desc->wMaxPacketSize) {
1128 pr_debug("dwc3: missing wMaxPacketSize\n");
1129 return -EINVAL;
1130 }
1131
1132 dep = to_dwc3_ep(ep);
1133 dwc = dep->dwc;
1134
1135 if (dev_WARN_ONCE(dwc->dev, dep->flags & DWC3_EP_ENABLED,
1136 "%s is already enabled\n",
1137 dep->name))
1138 return 0;
1139
1140 spin_lock_irqsave(&dwc->lock, flags);
1141 ret = __dwc3_gadget_ep_enable(dep, DWC3_DEPCFG_ACTION_INIT);
1142 spin_unlock_irqrestore(&dwc->lock, flags);
1143
1144 return ret;
1145}
1146
1147static int dwc3_gadget_ep_disable(struct usb_ep *ep)
1148{
1149 struct dwc3_ep *dep;
1150 struct dwc3 *dwc;
1151 unsigned long flags;
1152 int ret;
1153
1154 if (!ep) {
1155 pr_debug("dwc3: invalid parameters\n");
1156 return -EINVAL;
1157 }
1158
1159 dep = to_dwc3_ep(ep);
1160 dwc = dep->dwc;
1161
1162 if (dev_WARN_ONCE(dwc->dev, !(dep->flags & DWC3_EP_ENABLED),
1163 "%s is already disabled\n",
1164 dep->name))
1165 return 0;
1166
1167 spin_lock_irqsave(&dwc->lock, flags);
1168 ret = __dwc3_gadget_ep_disable(dep);
1169 spin_unlock_irqrestore(&dwc->lock, flags);
1170
1171 return ret;
1172}
1173
1174static struct usb_request *dwc3_gadget_ep_alloc_request(struct usb_ep *ep,
1175 gfp_t gfp_flags)
1176{
1177 struct dwc3_request *req;
1178 struct dwc3_ep *dep = to_dwc3_ep(ep);
1179
1180 req = kzalloc(sizeof(*req), gfp_flags);
1181 if (!req)
1182 return NULL;
1183
1184 req->direction = dep->direction;
1185 req->epnum = dep->number;
1186 req->dep = dep;
1187 req->status = DWC3_REQUEST_STATUS_UNKNOWN;
1188
1189 trace_dwc3_alloc_request(req);
1190
1191 return &req->request;
1192}
1193
1194static void dwc3_gadget_ep_free_request(struct usb_ep *ep,
1195 struct usb_request *request)
1196{
1197 struct dwc3_request *req = to_dwc3_request(request);
1198
1199 trace_dwc3_free_request(req);
1200 kfree(req);
1201}
1202
1203/**
1204 * dwc3_ep_prev_trb - returns the previous TRB in the ring
1205 * @dep: The endpoint with the TRB ring
1206 * @index: The index of the current TRB in the ring
1207 *
1208 * Returns the TRB prior to the one pointed to by the index. If the
1209 * index is 0, we will wrap backwards, skip the link TRB, and return
1210 * the one just before that.
1211 */
1212static struct dwc3_trb *dwc3_ep_prev_trb(struct dwc3_ep *dep, u8 index)
1213{
1214 u8 tmp = index;
1215
1216 if (!tmp)
1217 tmp = DWC3_TRB_NUM - 1;
1218
1219 return &dep->trb_pool[tmp - 1];
1220}
1221
1222static u32 dwc3_calc_trbs_left(struct dwc3_ep *dep)
1223{
1224 u8 trbs_left;
1225
1226 /*
1227 * If the enqueue & dequeue are equal then the TRB ring is either full
1228 * or empty. It's considered full when there are DWC3_TRB_NUM-1 of TRBs
1229 * pending to be processed by the driver.
1230 */
1231 if (dep->trb_enqueue == dep->trb_dequeue) {
1232 struct dwc3_request *req;
1233
1234 /*
1235 * If there is any request remained in the started_list with
1236 * active TRBs at this point, then there is no TRB available.
1237 */
1238 req = next_request(&dep->started_list);
1239 if (req && req->num_trbs)
1240 return 0;
1241
1242 return DWC3_TRB_NUM - 1;
1243 }
1244
1245 trbs_left = dep->trb_dequeue - dep->trb_enqueue;
1246 trbs_left &= (DWC3_TRB_NUM - 1);
1247
1248 if (dep->trb_dequeue < dep->trb_enqueue)
1249 trbs_left--;
1250
1251 return trbs_left;
1252}
1253
1254/**
1255 * dwc3_prepare_one_trb - setup one TRB from one request
1256 * @dep: endpoint for which this request is prepared
1257 * @req: dwc3_request pointer
1258 * @trb_length: buffer size of the TRB
1259 * @chain: should this TRB be chained to the next?
1260 * @node: only for isochronous endpoints. First TRB needs different type.
1261 * @use_bounce_buffer: set to use bounce buffer
1262 * @must_interrupt: set to interrupt on TRB completion
1263 */
1264static void dwc3_prepare_one_trb(struct dwc3_ep *dep,
1265 struct dwc3_request *req, unsigned int trb_length,
1266 unsigned int chain, unsigned int node, bool use_bounce_buffer,
1267 bool must_interrupt)
1268{
1269 struct dwc3_trb *trb;
1270 dma_addr_t dma;
1271 unsigned int stream_id = req->request.stream_id;
1272 unsigned int short_not_ok = req->request.short_not_ok;
1273 unsigned int no_interrupt = req->request.no_interrupt;
1274 unsigned int is_last = req->request.is_last;
1275 struct dwc3 *dwc = dep->dwc;
1276 struct usb_gadget *gadget = dwc->gadget;
1277 enum usb_device_speed speed = gadget->speed;
1278
1279 if (use_bounce_buffer)
1280 dma = dep->dwc->bounce_addr;
1281 else if (req->request.num_sgs > 0)
1282 dma = sg_dma_address(req->start_sg);
1283 else
1284 dma = req->request.dma;
1285
1286 trb = &dep->trb_pool[dep->trb_enqueue];
1287
1288 if (!req->trb) {
1289 dwc3_gadget_move_started_request(req);
1290 req->trb = trb;
1291 req->trb_dma = dwc3_trb_dma_offset(dep, trb);
1292 }
1293
1294 req->num_trbs++;
1295
1296 trb->size = DWC3_TRB_SIZE_LENGTH(trb_length);
1297 trb->bpl = lower_32_bits(dma);
1298 trb->bph = upper_32_bits(dma);
1299
1300 switch (usb_endpoint_type(dep->endpoint.desc)) {
1301 case USB_ENDPOINT_XFER_CONTROL:
1302 trb->ctrl = DWC3_TRBCTL_CONTROL_SETUP;
1303 break;
1304
1305 case USB_ENDPOINT_XFER_ISOC:
1306 if (!node) {
1307 trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS_FIRST;
1308
1309 /*
1310 * USB Specification 2.0 Section 5.9.2 states that: "If
1311 * there is only a single transaction in the microframe,
1312 * only a DATA0 data packet PID is used. If there are
1313 * two transactions per microframe, DATA1 is used for
1314 * the first transaction data packet and DATA0 is used
1315 * for the second transaction data packet. If there are
1316 * three transactions per microframe, DATA2 is used for
1317 * the first transaction data packet, DATA1 is used for
1318 * the second, and DATA0 is used for the third."
1319 *
1320 * IOW, we should satisfy the following cases:
1321 *
1322 * 1) length <= maxpacket
1323 * - DATA0
1324 *
1325 * 2) maxpacket < length <= (2 * maxpacket)
1326 * - DATA1, DATA0
1327 *
1328 * 3) (2 * maxpacket) < length <= (3 * maxpacket)
1329 * - DATA2, DATA1, DATA0
1330 */
1331 if (speed == USB_SPEED_HIGH) {
1332 struct usb_ep *ep = &dep->endpoint;
1333 unsigned int mult = 2;
1334 unsigned int maxp = usb_endpoint_maxp(ep->desc);
1335
1336 if (req->request.length <= (2 * maxp))
1337 mult--;
1338
1339 if (req->request.length <= maxp)
1340 mult--;
1341
1342 trb->size |= DWC3_TRB_SIZE_PCM1(mult);
1343 }
1344 } else {
1345 trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS;
1346 }
1347
1348 if (!no_interrupt && !chain)
1349 trb->ctrl |= DWC3_TRB_CTRL_ISP_IMI;
1350 break;
1351
1352 case USB_ENDPOINT_XFER_BULK:
1353 case USB_ENDPOINT_XFER_INT:
1354 trb->ctrl = DWC3_TRBCTL_NORMAL;
1355 break;
1356 default:
1357 /*
1358 * This is only possible with faulty memory because we
1359 * checked it already :)
1360 */
1361 dev_WARN(dwc->dev, "Unknown endpoint type %d\n",
1362 usb_endpoint_type(dep->endpoint.desc));
1363 }
1364
1365 /*
1366 * Enable Continue on Short Packet
1367 * when endpoint is not a stream capable
1368 */
1369 if (usb_endpoint_dir_out(dep->endpoint.desc)) {
1370 if (!dep->stream_capable)
1371 trb->ctrl |= DWC3_TRB_CTRL_CSP;
1372
1373 if (short_not_ok)
1374 trb->ctrl |= DWC3_TRB_CTRL_ISP_IMI;
1375 }
1376
1377 /* All TRBs setup for MST must set CSP=1 when LST=0 */
1378 if (dep->stream_capable && DWC3_MST_CAPABLE(&dwc->hwparams))
1379 trb->ctrl |= DWC3_TRB_CTRL_CSP;
1380
1381 if ((!no_interrupt && !chain) || must_interrupt)
1382 trb->ctrl |= DWC3_TRB_CTRL_IOC;
1383
1384 if (chain)
1385 trb->ctrl |= DWC3_TRB_CTRL_CHN;
1386 else if (dep->stream_capable && is_last &&
1387 !DWC3_MST_CAPABLE(&dwc->hwparams))
1388 trb->ctrl |= DWC3_TRB_CTRL_LST;
1389
1390 if (usb_endpoint_xfer_bulk(dep->endpoint.desc) && dep->stream_capable)
1391 trb->ctrl |= DWC3_TRB_CTRL_SID_SOFN(stream_id);
1392
1393 /*
1394 * As per data book 4.2.3.2TRB Control Bit Rules section
1395 *
1396 * The controller autonomously checks the HWO field of a TRB to determine if the
1397 * entire TRB is valid. Therefore, software must ensure that the rest of the TRB
1398 * is valid before setting the HWO field to '1'. In most systems, this means that
1399 * software must update the fourth DWORD of a TRB last.
1400 *
1401 * However there is a possibility of CPU re-ordering here which can cause
1402 * controller to observe the HWO bit set prematurely.
1403 * Add a write memory barrier to prevent CPU re-ordering.
1404 */
1405 wmb();
1406 trb->ctrl |= DWC3_TRB_CTRL_HWO;
1407
1408 dwc3_ep_inc_enq(dep);
1409
1410 trace_dwc3_prepare_trb(dep, trb);
1411}
1412
1413static bool dwc3_needs_extra_trb(struct dwc3_ep *dep, struct dwc3_request *req)
1414{
1415 unsigned int maxp = usb_endpoint_maxp(dep->endpoint.desc);
1416 unsigned int rem = req->request.length % maxp;
1417
1418 if ((req->request.length && req->request.zero && !rem &&
1419 !usb_endpoint_xfer_isoc(dep->endpoint.desc)) ||
1420 (!req->direction && rem))
1421 return true;
1422
1423 return false;
1424}
1425
1426/**
1427 * dwc3_prepare_last_sg - prepare TRBs for the last SG entry
1428 * @dep: The endpoint that the request belongs to
1429 * @req: The request to prepare
1430 * @entry_length: The last SG entry size
1431 * @node: Indicates whether this is not the first entry (for isoc only)
1432 *
1433 * Return the number of TRBs prepared.
1434 */
1435static int dwc3_prepare_last_sg(struct dwc3_ep *dep,
1436 struct dwc3_request *req, unsigned int entry_length,
1437 unsigned int node)
1438{
1439 unsigned int maxp = usb_endpoint_maxp(dep->endpoint.desc);
1440 unsigned int rem = req->request.length % maxp;
1441 unsigned int num_trbs = 1;
1442 bool needs_extra_trb;
1443
1444 if (dwc3_needs_extra_trb(dep, req))
1445 num_trbs++;
1446
1447 if (dwc3_calc_trbs_left(dep) < num_trbs)
1448 return 0;
1449
1450 needs_extra_trb = num_trbs > 1;
1451
1452 /* Prepare a normal TRB */
1453 if (req->direction || req->request.length)
1454 dwc3_prepare_one_trb(dep, req, entry_length,
1455 needs_extra_trb, node, false, false);
1456
1457 /* Prepare extra TRBs for ZLP and MPS OUT transfer alignment */
1458 if ((!req->direction && !req->request.length) || needs_extra_trb)
1459 dwc3_prepare_one_trb(dep, req,
1460 req->direction ? 0 : maxp - rem,
1461 false, 1, true, false);
1462
1463 return num_trbs;
1464}
1465
1466static int dwc3_prepare_trbs_sg(struct dwc3_ep *dep,
1467 struct dwc3_request *req)
1468{
1469 struct scatterlist *sg = req->start_sg;
1470 struct scatterlist *s;
1471 int i;
1472 unsigned int length = req->request.length;
1473 unsigned int remaining = req->num_pending_sgs;
1474 unsigned int num_queued_sgs = req->request.num_mapped_sgs - remaining;
1475 unsigned int num_trbs = req->num_trbs;
1476 bool needs_extra_trb = dwc3_needs_extra_trb(dep, req);
1477
1478 /*
1479 * If we resume preparing the request, then get the remaining length of
1480 * the request and resume where we left off.
1481 */
1482 for_each_sg(req->request.sg, s, num_queued_sgs, i)
1483 length -= sg_dma_len(s);
1484
1485 for_each_sg(sg, s, remaining, i) {
1486 unsigned int num_trbs_left = dwc3_calc_trbs_left(dep);
1487 unsigned int trb_length;
1488 bool must_interrupt = false;
1489 bool last_sg = false;
1490
1491 trb_length = min_t(unsigned int, length, sg_dma_len(s));
1492
1493 length -= trb_length;
1494
1495 /*
1496 * IOMMU driver is coalescing the list of sgs which shares a
1497 * page boundary into one and giving it to USB driver. With
1498 * this the number of sgs mapped is not equal to the number of
1499 * sgs passed. So mark the chain bit to false if it isthe last
1500 * mapped sg.
1501 */
1502 if ((i == remaining - 1) || !length)
1503 last_sg = true;
1504
1505 if (!num_trbs_left)
1506 break;
1507
1508 if (last_sg) {
1509 if (!dwc3_prepare_last_sg(dep, req, trb_length, i))
1510 break;
1511 } else {
1512 /*
1513 * Look ahead to check if we have enough TRBs for the
1514 * next SG entry. If not, set interrupt on this TRB to
1515 * resume preparing the next SG entry when more TRBs are
1516 * free.
1517 */
1518 if (num_trbs_left == 1 || (needs_extra_trb &&
1519 num_trbs_left <= 2 &&
1520 sg_dma_len(sg_next(s)) >= length)) {
1521 struct dwc3_request *r;
1522
1523 /* Check if previous requests already set IOC */
1524 list_for_each_entry(r, &dep->started_list, list) {
1525 if (r != req && !r->request.no_interrupt)
1526 break;
1527
1528 if (r == req)
1529 must_interrupt = true;
1530 }
1531 }
1532
1533 dwc3_prepare_one_trb(dep, req, trb_length, 1, i, false,
1534 must_interrupt);
1535 }
1536
1537 /*
1538 * There can be a situation where all sgs in sglist are not
1539 * queued because of insufficient trb number. To handle this
1540 * case, update start_sg to next sg to be queued, so that
1541 * we have free trbs we can continue queuing from where we
1542 * previously stopped
1543 */
1544 if (!last_sg)
1545 req->start_sg = sg_next(s);
1546
1547 req->num_pending_sgs--;
1548
1549 /*
1550 * The number of pending SG entries may not correspond to the
1551 * number of mapped SG entries. If all the data are queued, then
1552 * don't include unused SG entries.
1553 */
1554 if (length == 0) {
1555 req->num_pending_sgs = 0;
1556 break;
1557 }
1558
1559 if (must_interrupt)
1560 break;
1561 }
1562
1563 return req->num_trbs - num_trbs;
1564}
1565
1566static int dwc3_prepare_trbs_linear(struct dwc3_ep *dep,
1567 struct dwc3_request *req)
1568{
1569 return dwc3_prepare_last_sg(dep, req, req->request.length, 0);
1570}
1571
1572/*
1573 * dwc3_prepare_trbs - setup TRBs from requests
1574 * @dep: endpoint for which requests are being prepared
1575 *
1576 * The function goes through the requests list and sets up TRBs for the
1577 * transfers. The function returns once there are no more TRBs available or
1578 * it runs out of requests.
1579 *
1580 * Returns the number of TRBs prepared or negative errno.
1581 */
1582static int dwc3_prepare_trbs(struct dwc3_ep *dep)
1583{
1584 struct dwc3_request *req, *n;
1585 int ret = 0;
1586
1587 BUILD_BUG_ON_NOT_POWER_OF_2(DWC3_TRB_NUM);
1588
1589 /*
1590 * We can get in a situation where there's a request in the started list
1591 * but there weren't enough TRBs to fully kick it in the first time
1592 * around, so it has been waiting for more TRBs to be freed up.
1593 *
1594 * In that case, we should check if we have a request with pending_sgs
1595 * in the started list and prepare TRBs for that request first,
1596 * otherwise we will prepare TRBs completely out of order and that will
1597 * break things.
1598 */
1599 list_for_each_entry(req, &dep->started_list, list) {
1600 if (req->num_pending_sgs > 0) {
1601 ret = dwc3_prepare_trbs_sg(dep, req);
1602 if (!ret || req->num_pending_sgs)
1603 return ret;
1604 }
1605
1606 if (!dwc3_calc_trbs_left(dep))
1607 return ret;
1608
1609 /*
1610 * Don't prepare beyond a transfer. In DWC_usb32, its transfer
1611 * burst capability may try to read and use TRBs beyond the
1612 * active transfer instead of stopping.
1613 */
1614 if (dep->stream_capable && req->request.is_last &&
1615 !DWC3_MST_CAPABLE(&dep->dwc->hwparams))
1616 return ret;
1617 }
1618
1619 list_for_each_entry_safe(req, n, &dep->pending_list, list) {
1620 struct dwc3 *dwc = dep->dwc;
1621
1622 ret = usb_gadget_map_request_by_dev(dwc->sysdev, &req->request,
1623 dep->direction);
1624 if (ret)
1625 return ret;
1626
1627 req->start_sg = req->request.sg;
1628 req->num_pending_sgs = req->request.num_mapped_sgs;
1629
1630 if (req->num_pending_sgs > 0) {
1631 ret = dwc3_prepare_trbs_sg(dep, req);
1632 if (req->num_pending_sgs)
1633 return ret;
1634 } else {
1635 ret = dwc3_prepare_trbs_linear(dep, req);
1636 }
1637
1638 if (!ret || !dwc3_calc_trbs_left(dep))
1639 return ret;
1640
1641 /*
1642 * Don't prepare beyond a transfer. In DWC_usb32, its transfer
1643 * burst capability may try to read and use TRBs beyond the
1644 * active transfer instead of stopping.
1645 */
1646 if (dep->stream_capable && req->request.is_last &&
1647 !DWC3_MST_CAPABLE(&dwc->hwparams))
1648 return ret;
1649 }
1650
1651 return ret;
1652}
1653
1654static void dwc3_gadget_ep_cleanup_cancelled_requests(struct dwc3_ep *dep);
1655
1656static int __dwc3_gadget_kick_transfer(struct dwc3_ep *dep)
1657{
1658 struct dwc3_gadget_ep_cmd_params params;
1659 struct dwc3_request *req;
1660 int starting;
1661 int ret;
1662 u32 cmd;
1663
1664 /*
1665 * Note that it's normal to have no new TRBs prepared (i.e. ret == 0).
1666 * This happens when we need to stop and restart a transfer such as in
1667 * the case of reinitiating a stream or retrying an isoc transfer.
1668 */
1669 ret = dwc3_prepare_trbs(dep);
1670 if (ret < 0)
1671 return ret;
1672
1673 starting = !(dep->flags & DWC3_EP_TRANSFER_STARTED);
1674
1675 /*
1676 * If there's no new TRB prepared and we don't need to restart a
1677 * transfer, there's no need to update the transfer.
1678 */
1679 if (!ret && !starting)
1680 return ret;
1681
1682 req = next_request(&dep->started_list);
1683 if (!req) {
1684 dep->flags |= DWC3_EP_PENDING_REQUEST;
1685 return 0;
1686 }
1687
1688 memset(¶ms, 0, sizeof(params));
1689
1690 if (starting) {
1691 params.param0 = upper_32_bits(req->trb_dma);
1692 params.param1 = lower_32_bits(req->trb_dma);
1693 cmd = DWC3_DEPCMD_STARTTRANSFER;
1694
1695 if (dep->stream_capable)
1696 cmd |= DWC3_DEPCMD_PARAM(req->request.stream_id);
1697
1698 if (usb_endpoint_xfer_isoc(dep->endpoint.desc))
1699 cmd |= DWC3_DEPCMD_PARAM(dep->frame_number);
1700 } else {
1701 cmd = DWC3_DEPCMD_UPDATETRANSFER |
1702 DWC3_DEPCMD_PARAM(dep->resource_index);
1703 }
1704
1705 ret = dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms);
1706 if (ret < 0) {
1707 struct dwc3_request *tmp;
1708
1709 if (ret == -EAGAIN)
1710 return ret;
1711
1712 dwc3_stop_active_transfer(dep, true, true);
1713
1714 list_for_each_entry_safe(req, tmp, &dep->started_list, list)
1715 dwc3_gadget_move_cancelled_request(req, DWC3_REQUEST_STATUS_DEQUEUED);
1716
1717 /* If ep isn't started, then there's no end transfer pending */
1718 if (!(dep->flags & DWC3_EP_END_TRANSFER_PENDING))
1719 dwc3_gadget_ep_cleanup_cancelled_requests(dep);
1720
1721 return ret;
1722 }
1723
1724 if (dep->stream_capable && req->request.is_last &&
1725 !DWC3_MST_CAPABLE(&dep->dwc->hwparams))
1726 dep->flags |= DWC3_EP_WAIT_TRANSFER_COMPLETE;
1727
1728 return 0;
1729}
1730
1731static int __dwc3_gadget_get_frame(struct dwc3 *dwc)
1732{
1733 u32 reg;
1734
1735 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1736 return DWC3_DSTS_SOFFN(reg);
1737}
1738
1739/**
1740 * __dwc3_stop_active_transfer - stop the current active transfer
1741 * @dep: isoc endpoint
1742 * @force: set forcerm bit in the command
1743 * @interrupt: command complete interrupt after End Transfer command
1744 *
1745 * When setting force, the ForceRM bit will be set. In that case
1746 * the controller won't update the TRB progress on command
1747 * completion. It also won't clear the HWO bit in the TRB.
1748 * The command will also not complete immediately in that case.
1749 */
1750static int __dwc3_stop_active_transfer(struct dwc3_ep *dep, bool force, bool interrupt)
1751{
1752 struct dwc3_gadget_ep_cmd_params params;
1753 u32 cmd;
1754 int ret;
1755
1756 cmd = DWC3_DEPCMD_ENDTRANSFER;
1757 cmd |= force ? DWC3_DEPCMD_HIPRI_FORCERM : 0;
1758 cmd |= interrupt ? DWC3_DEPCMD_CMDIOC : 0;
1759 cmd |= DWC3_DEPCMD_PARAM(dep->resource_index);
1760 memset(¶ms, 0, sizeof(params));
1761 ret = dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms);
1762 /*
1763 * If the End Transfer command was timed out while the device is
1764 * not in SETUP phase, it's possible that an incoming Setup packet
1765 * may prevent the command's completion. Let's retry when the
1766 * ep0state returns to EP0_SETUP_PHASE.
1767 */
1768 if (ret == -ETIMEDOUT && dep->dwc->ep0state != EP0_SETUP_PHASE) {
1769 dep->flags |= DWC3_EP_DELAY_STOP;
1770 return 0;
1771 }
1772 WARN_ON_ONCE(ret);
1773 dep->resource_index = 0;
1774
1775 if (!interrupt)
1776 dep->flags &= ~DWC3_EP_TRANSFER_STARTED;
1777 else if (!ret)
1778 dep->flags |= DWC3_EP_END_TRANSFER_PENDING;
1779
1780 dep->flags &= ~DWC3_EP_DELAY_STOP;
1781 return ret;
1782}
1783
1784/**
1785 * dwc3_gadget_start_isoc_quirk - workaround invalid frame number
1786 * @dep: isoc endpoint
1787 *
1788 * This function tests for the correct combination of BIT[15:14] from the 16-bit
1789 * microframe number reported by the XferNotReady event for the future frame
1790 * number to start the isoc transfer.
1791 *
1792 * In DWC_usb31 version 1.70a-ea06 and prior, for highspeed and fullspeed
1793 * isochronous IN, BIT[15:14] of the 16-bit microframe number reported by the
1794 * XferNotReady event are invalid. The driver uses this number to schedule the
1795 * isochronous transfer and passes it to the START TRANSFER command. Because
1796 * this number is invalid, the command may fail. If BIT[15:14] matches the
1797 * internal 16-bit microframe, the START TRANSFER command will pass and the
1798 * transfer will start at the scheduled time, if it is off by 1, the command
1799 * will still pass, but the transfer will start 2 seconds in the future. For all
1800 * other conditions, the START TRANSFER command will fail with bus-expiry.
1801 *
1802 * In order to workaround this issue, we can test for the correct combination of
1803 * BIT[15:14] by sending START TRANSFER commands with different values of
1804 * BIT[15:14]: 'b00, 'b01, 'b10, and 'b11. Each combination is 2^14 uframe apart
1805 * (or 2 seconds). 4 seconds into the future will result in a bus-expiry status.
1806 * As the result, within the 4 possible combinations for BIT[15:14], there will
1807 * be 2 successful and 2 failure START COMMAND status. One of the 2 successful
1808 * command status will result in a 2-second delay start. The smaller BIT[15:14]
1809 * value is the correct combination.
1810 *
1811 * Since there are only 4 outcomes and the results are ordered, we can simply
1812 * test 2 START TRANSFER commands with BIT[15:14] combinations 'b00 and 'b01 to
1813 * deduce the smaller successful combination.
1814 *
1815 * Let test0 = test status for combination 'b00 and test1 = test status for 'b01
1816 * of BIT[15:14]. The correct combination is as follow:
1817 *
1818 * if test0 fails and test1 passes, BIT[15:14] is 'b01
1819 * if test0 fails and test1 fails, BIT[15:14] is 'b10
1820 * if test0 passes and test1 fails, BIT[15:14] is 'b11
1821 * if test0 passes and test1 passes, BIT[15:14] is 'b00
1822 *
1823 * Synopsys STAR 9001202023: Wrong microframe number for isochronous IN
1824 * endpoints.
1825 */
1826static int dwc3_gadget_start_isoc_quirk(struct dwc3_ep *dep)
1827{
1828 int cmd_status = 0;
1829 bool test0;
1830 bool test1;
1831
1832 while (dep->combo_num < 2) {
1833 struct dwc3_gadget_ep_cmd_params params;
1834 u32 test_frame_number;
1835 u32 cmd;
1836
1837 /*
1838 * Check if we can start isoc transfer on the next interval or
1839 * 4 uframes in the future with BIT[15:14] as dep->combo_num
1840 */
1841 test_frame_number = dep->frame_number & DWC3_FRNUMBER_MASK;
1842 test_frame_number |= dep->combo_num << 14;
1843 test_frame_number += max_t(u32, 4, dep->interval);
1844
1845 params.param0 = upper_32_bits(dep->dwc->bounce_addr);
1846 params.param1 = lower_32_bits(dep->dwc->bounce_addr);
1847
1848 cmd = DWC3_DEPCMD_STARTTRANSFER;
1849 cmd |= DWC3_DEPCMD_PARAM(test_frame_number);
1850 cmd_status = dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms);
1851
1852 /* Redo if some other failure beside bus-expiry is received */
1853 if (cmd_status && cmd_status != -EAGAIN) {
1854 dep->start_cmd_status = 0;
1855 dep->combo_num = 0;
1856 return 0;
1857 }
1858
1859 /* Store the first test status */
1860 if (dep->combo_num == 0)
1861 dep->start_cmd_status = cmd_status;
1862
1863 dep->combo_num++;
1864
1865 /*
1866 * End the transfer if the START_TRANSFER command is successful
1867 * to wait for the next XferNotReady to test the command again
1868 */
1869 if (cmd_status == 0) {
1870 dwc3_stop_active_transfer(dep, true, true);
1871 return 0;
1872 }
1873 }
1874
1875 /* test0 and test1 are both completed at this point */
1876 test0 = (dep->start_cmd_status == 0);
1877 test1 = (cmd_status == 0);
1878
1879 if (!test0 && test1)
1880 dep->combo_num = 1;
1881 else if (!test0 && !test1)
1882 dep->combo_num = 2;
1883 else if (test0 && !test1)
1884 dep->combo_num = 3;
1885 else if (test0 && test1)
1886 dep->combo_num = 0;
1887
1888 dep->frame_number &= DWC3_FRNUMBER_MASK;
1889 dep->frame_number |= dep->combo_num << 14;
1890 dep->frame_number += max_t(u32, 4, dep->interval);
1891
1892 /* Reinitialize test variables */
1893 dep->start_cmd_status = 0;
1894 dep->combo_num = 0;
1895
1896 return __dwc3_gadget_kick_transfer(dep);
1897}
1898
1899static int __dwc3_gadget_start_isoc(struct dwc3_ep *dep)
1900{
1901 const struct usb_endpoint_descriptor *desc = dep->endpoint.desc;
1902 struct dwc3 *dwc = dep->dwc;
1903 int ret;
1904 int i;
1905
1906 if (list_empty(&dep->pending_list) &&
1907 list_empty(&dep->started_list)) {
1908 dep->flags |= DWC3_EP_PENDING_REQUEST;
1909 return -EAGAIN;
1910 }
1911
1912 if (!dwc->dis_start_transfer_quirk &&
1913 (DWC3_VER_IS_PRIOR(DWC31, 170A) ||
1914 DWC3_VER_TYPE_IS_WITHIN(DWC31, 170A, EA01, EA06))) {
1915 if (dwc->gadget->speed <= USB_SPEED_HIGH && dep->direction)
1916 return dwc3_gadget_start_isoc_quirk(dep);
1917 }
1918
1919 if (desc->bInterval <= 14 &&
1920 dwc->gadget->speed >= USB_SPEED_HIGH) {
1921 u32 frame = __dwc3_gadget_get_frame(dwc);
1922 bool rollover = frame <
1923 (dep->frame_number & DWC3_FRNUMBER_MASK);
1924
1925 /*
1926 * frame_number is set from XferNotReady and may be already
1927 * out of date. DSTS only provides the lower 14 bit of the
1928 * current frame number. So add the upper two bits of
1929 * frame_number and handle a possible rollover.
1930 * This will provide the correct frame_number unless more than
1931 * rollover has happened since XferNotReady.
1932 */
1933
1934 dep->frame_number = (dep->frame_number & ~DWC3_FRNUMBER_MASK) |
1935 frame;
1936 if (rollover)
1937 dep->frame_number += BIT(14);
1938 }
1939
1940 for (i = 0; i < DWC3_ISOC_MAX_RETRIES; i++) {
1941 int future_interval = i + 1;
1942
1943 /* Give the controller at least 500us to schedule transfers */
1944 if (desc->bInterval < 3)
1945 future_interval += 3 - desc->bInterval;
1946
1947 dep->frame_number = DWC3_ALIGN_FRAME(dep, future_interval);
1948
1949 ret = __dwc3_gadget_kick_transfer(dep);
1950 if (ret != -EAGAIN)
1951 break;
1952 }
1953
1954 /*
1955 * After a number of unsuccessful start attempts due to bus-expiry
1956 * status, issue END_TRANSFER command and retry on the next XferNotReady
1957 * event.
1958 */
1959 if (ret == -EAGAIN)
1960 ret = __dwc3_stop_active_transfer(dep, false, true);
1961
1962 return ret;
1963}
1964
1965static int __dwc3_gadget_ep_queue(struct dwc3_ep *dep, struct dwc3_request *req)
1966{
1967 struct dwc3 *dwc = dep->dwc;
1968
1969 if (!dep->endpoint.desc || !dwc->pullups_connected || !dwc->connected) {
1970 dev_dbg(dwc->dev, "%s: can't queue to disabled endpoint\n",
1971 dep->name);
1972 return -ESHUTDOWN;
1973 }
1974
1975 if (WARN(req->dep != dep, "request %pK belongs to '%s'\n",
1976 &req->request, req->dep->name))
1977 return -EINVAL;
1978
1979 if (WARN(req->status < DWC3_REQUEST_STATUS_COMPLETED,
1980 "%s: request %pK already in flight\n",
1981 dep->name, &req->request))
1982 return -EINVAL;
1983
1984 pm_runtime_get(dwc->dev);
1985
1986 req->request.actual = 0;
1987 req->request.status = -EINPROGRESS;
1988
1989 trace_dwc3_ep_queue(req);
1990
1991 list_add_tail(&req->list, &dep->pending_list);
1992 req->status = DWC3_REQUEST_STATUS_QUEUED;
1993
1994 if (dep->flags & DWC3_EP_WAIT_TRANSFER_COMPLETE)
1995 return 0;
1996
1997 /*
1998 * Start the transfer only after the END_TRANSFER is completed
1999 * and endpoint STALL is cleared.
2000 */
2001 if ((dep->flags & DWC3_EP_END_TRANSFER_PENDING) ||
2002 (dep->flags & DWC3_EP_WEDGE) ||
2003 (dep->flags & DWC3_EP_DELAY_STOP) ||
2004 (dep->flags & DWC3_EP_STALL)) {
2005 dep->flags |= DWC3_EP_DELAY_START;
2006 return 0;
2007 }
2008
2009 /*
2010 * NOTICE: Isochronous endpoints should NEVER be prestarted. We must
2011 * wait for a XferNotReady event so we will know what's the current
2012 * (micro-)frame number.
2013 *
2014 * Without this trick, we are very, very likely gonna get Bus Expiry
2015 * errors which will force us issue EndTransfer command.
2016 */
2017 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
2018 if (!(dep->flags & DWC3_EP_TRANSFER_STARTED)) {
2019 if ((dep->flags & DWC3_EP_PENDING_REQUEST))
2020 return __dwc3_gadget_start_isoc(dep);
2021
2022 return 0;
2023 }
2024 }
2025
2026 __dwc3_gadget_kick_transfer(dep);
2027
2028 return 0;
2029}
2030
2031static int dwc3_gadget_ep_queue(struct usb_ep *ep, struct usb_request *request,
2032 gfp_t gfp_flags)
2033{
2034 struct dwc3_request *req = to_dwc3_request(request);
2035 struct dwc3_ep *dep = to_dwc3_ep(ep);
2036 struct dwc3 *dwc = dep->dwc;
2037
2038 unsigned long flags;
2039
2040 int ret;
2041
2042 spin_lock_irqsave(&dwc->lock, flags);
2043 ret = __dwc3_gadget_ep_queue(dep, req);
2044 spin_unlock_irqrestore(&dwc->lock, flags);
2045
2046 return ret;
2047}
2048
2049static void dwc3_gadget_ep_skip_trbs(struct dwc3_ep *dep, struct dwc3_request *req)
2050{
2051 int i;
2052
2053 /* If req->trb is not set, then the request has not started */
2054 if (!req->trb)
2055 return;
2056
2057 /*
2058 * If request was already started, this means we had to
2059 * stop the transfer. With that we also need to ignore
2060 * all TRBs used by the request, however TRBs can only
2061 * be modified after completion of END_TRANSFER
2062 * command. So what we do here is that we wait for
2063 * END_TRANSFER completion and only after that, we jump
2064 * over TRBs by clearing HWO and incrementing dequeue
2065 * pointer.
2066 */
2067 for (i = 0; i < req->num_trbs; i++) {
2068 struct dwc3_trb *trb;
2069
2070 trb = &dep->trb_pool[dep->trb_dequeue];
2071 trb->ctrl &= ~DWC3_TRB_CTRL_HWO;
2072 dwc3_ep_inc_deq(dep);
2073 }
2074
2075 req->num_trbs = 0;
2076}
2077
2078static void dwc3_gadget_ep_cleanup_cancelled_requests(struct dwc3_ep *dep)
2079{
2080 struct dwc3_request *req;
2081 struct dwc3 *dwc = dep->dwc;
2082
2083 while (!list_empty(&dep->cancelled_list)) {
2084 req = next_request(&dep->cancelled_list);
2085 dwc3_gadget_ep_skip_trbs(dep, req);
2086 switch (req->status) {
2087 case DWC3_REQUEST_STATUS_DISCONNECTED:
2088 dwc3_gadget_giveback(dep, req, -ESHUTDOWN);
2089 break;
2090 case DWC3_REQUEST_STATUS_DEQUEUED:
2091 dwc3_gadget_giveback(dep, req, -ECONNRESET);
2092 break;
2093 case DWC3_REQUEST_STATUS_STALLED:
2094 dwc3_gadget_giveback(dep, req, -EPIPE);
2095 break;
2096 default:
2097 dev_err(dwc->dev, "request cancelled with wrong reason:%d\n", req->status);
2098 dwc3_gadget_giveback(dep, req, -ECONNRESET);
2099 break;
2100 }
2101 /*
2102 * The endpoint is disabled, let the dwc3_remove_requests()
2103 * handle the cleanup.
2104 */
2105 if (!dep->endpoint.desc)
2106 break;
2107 }
2108}
2109
2110static int dwc3_gadget_ep_dequeue(struct usb_ep *ep,
2111 struct usb_request *request)
2112{
2113 struct dwc3_request *req = to_dwc3_request(request);
2114 struct dwc3_request *r = NULL;
2115
2116 struct dwc3_ep *dep = to_dwc3_ep(ep);
2117 struct dwc3 *dwc = dep->dwc;
2118
2119 unsigned long flags;
2120 int ret = 0;
2121
2122 trace_dwc3_ep_dequeue(req);
2123
2124 spin_lock_irqsave(&dwc->lock, flags);
2125
2126 list_for_each_entry(r, &dep->cancelled_list, list) {
2127 if (r == req)
2128 goto out;
2129 }
2130
2131 list_for_each_entry(r, &dep->pending_list, list) {
2132 if (r == req) {
2133 /*
2134 * Explicitly check for EP0/1 as dequeue for those
2135 * EPs need to be handled differently. Control EP
2136 * only deals with one USB req, and giveback will
2137 * occur during dwc3_ep0_stall_and_restart(). EP0
2138 * requests are never added to started_list.
2139 */
2140 if (dep->number > 1)
2141 dwc3_gadget_giveback(dep, req, -ECONNRESET);
2142 else
2143 dwc3_ep0_reset_state(dwc);
2144 goto out;
2145 }
2146 }
2147
2148 list_for_each_entry(r, &dep->started_list, list) {
2149 if (r == req) {
2150 struct dwc3_request *t;
2151
2152 /* wait until it is processed */
2153 dwc3_stop_active_transfer(dep, true, true);
2154
2155 /*
2156 * Remove any started request if the transfer is
2157 * cancelled.
2158 */
2159 list_for_each_entry_safe(r, t, &dep->started_list, list)
2160 dwc3_gadget_move_cancelled_request(r,
2161 DWC3_REQUEST_STATUS_DEQUEUED);
2162
2163 dep->flags &= ~DWC3_EP_WAIT_TRANSFER_COMPLETE;
2164
2165 goto out;
2166 }
2167 }
2168
2169 dev_err(dwc->dev, "request %pK was not queued to %s\n",
2170 request, ep->name);
2171 ret = -EINVAL;
2172out:
2173 spin_unlock_irqrestore(&dwc->lock, flags);
2174
2175 return ret;
2176}
2177
2178int __dwc3_gadget_ep_set_halt(struct dwc3_ep *dep, int value, int protocol)
2179{
2180 struct dwc3_gadget_ep_cmd_params params;
2181 struct dwc3 *dwc = dep->dwc;
2182 struct dwc3_request *req;
2183 struct dwc3_request *tmp;
2184 int ret;
2185
2186 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
2187 dev_err(dwc->dev, "%s is of Isochronous type\n", dep->name);
2188 return -EINVAL;
2189 }
2190
2191 memset(¶ms, 0x00, sizeof(params));
2192
2193 if (value) {
2194 struct dwc3_trb *trb;
2195
2196 unsigned int transfer_in_flight;
2197 unsigned int started;
2198
2199 if (dep->number > 1)
2200 trb = dwc3_ep_prev_trb(dep, dep->trb_enqueue);
2201 else
2202 trb = &dwc->ep0_trb[dep->trb_enqueue];
2203
2204 transfer_in_flight = trb->ctrl & DWC3_TRB_CTRL_HWO;
2205 started = !list_empty(&dep->started_list);
2206
2207 if (!protocol && ((dep->direction && transfer_in_flight) ||
2208 (!dep->direction && started))) {
2209 return -EAGAIN;
2210 }
2211
2212 ret = dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_SETSTALL,
2213 ¶ms);
2214 if (ret)
2215 dev_err(dwc->dev, "failed to set STALL on %s\n",
2216 dep->name);
2217 else
2218 dep->flags |= DWC3_EP_STALL;
2219 } else {
2220 /*
2221 * Don't issue CLEAR_STALL command to control endpoints. The
2222 * controller automatically clears the STALL when it receives
2223 * the SETUP token.
2224 */
2225 if (dep->number <= 1) {
2226 dep->flags &= ~(DWC3_EP_STALL | DWC3_EP_WEDGE);
2227 return 0;
2228 }
2229
2230 dwc3_stop_active_transfer(dep, true, true);
2231
2232 list_for_each_entry_safe(req, tmp, &dep->started_list, list)
2233 dwc3_gadget_move_cancelled_request(req, DWC3_REQUEST_STATUS_STALLED);
2234
2235 if (dep->flags & DWC3_EP_END_TRANSFER_PENDING ||
2236 (dep->flags & DWC3_EP_DELAY_STOP)) {
2237 dep->flags |= DWC3_EP_PENDING_CLEAR_STALL;
2238 if (protocol)
2239 dwc->clear_stall_protocol = dep->number;
2240
2241 return 0;
2242 }
2243
2244 dwc3_gadget_ep_cleanup_cancelled_requests(dep);
2245
2246 ret = dwc3_send_clear_stall_ep_cmd(dep);
2247 if (ret) {
2248 dev_err(dwc->dev, "failed to clear STALL on %s\n",
2249 dep->name);
2250 return ret;
2251 }
2252
2253 dep->flags &= ~(DWC3_EP_STALL | DWC3_EP_WEDGE);
2254
2255 if ((dep->flags & DWC3_EP_DELAY_START) &&
2256 !usb_endpoint_xfer_isoc(dep->endpoint.desc))
2257 __dwc3_gadget_kick_transfer(dep);
2258
2259 dep->flags &= ~DWC3_EP_DELAY_START;
2260 }
2261
2262 return ret;
2263}
2264
2265static int dwc3_gadget_ep_set_halt(struct usb_ep *ep, int value)
2266{
2267 struct dwc3_ep *dep = to_dwc3_ep(ep);
2268 struct dwc3 *dwc = dep->dwc;
2269
2270 unsigned long flags;
2271
2272 int ret;
2273
2274 spin_lock_irqsave(&dwc->lock, flags);
2275 ret = __dwc3_gadget_ep_set_halt(dep, value, false);
2276 spin_unlock_irqrestore(&dwc->lock, flags);
2277
2278 return ret;
2279}
2280
2281static int dwc3_gadget_ep_set_wedge(struct usb_ep *ep)
2282{
2283 struct dwc3_ep *dep = to_dwc3_ep(ep);
2284 struct dwc3 *dwc = dep->dwc;
2285 unsigned long flags;
2286 int ret;
2287
2288 spin_lock_irqsave(&dwc->lock, flags);
2289 dep->flags |= DWC3_EP_WEDGE;
2290
2291 if (dep->number == 0 || dep->number == 1)
2292 ret = __dwc3_gadget_ep0_set_halt(ep, 1);
2293 else
2294 ret = __dwc3_gadget_ep_set_halt(dep, 1, false);
2295 spin_unlock_irqrestore(&dwc->lock, flags);
2296
2297 return ret;
2298}
2299
2300/* -------------------------------------------------------------------------- */
2301
2302static struct usb_endpoint_descriptor dwc3_gadget_ep0_desc = {
2303 .bLength = USB_DT_ENDPOINT_SIZE,
2304 .bDescriptorType = USB_DT_ENDPOINT,
2305 .bmAttributes = USB_ENDPOINT_XFER_CONTROL,
2306};
2307
2308static const struct usb_ep_ops dwc3_gadget_ep0_ops = {
2309 .enable = dwc3_gadget_ep0_enable,
2310 .disable = dwc3_gadget_ep0_disable,
2311 .alloc_request = dwc3_gadget_ep_alloc_request,
2312 .free_request = dwc3_gadget_ep_free_request,
2313 .queue = dwc3_gadget_ep0_queue,
2314 .dequeue = dwc3_gadget_ep_dequeue,
2315 .set_halt = dwc3_gadget_ep0_set_halt,
2316 .set_wedge = dwc3_gadget_ep_set_wedge,
2317};
2318
2319static const struct usb_ep_ops dwc3_gadget_ep_ops = {
2320 .enable = dwc3_gadget_ep_enable,
2321 .disable = dwc3_gadget_ep_disable,
2322 .alloc_request = dwc3_gadget_ep_alloc_request,
2323 .free_request = dwc3_gadget_ep_free_request,
2324 .queue = dwc3_gadget_ep_queue,
2325 .dequeue = dwc3_gadget_ep_dequeue,
2326 .set_halt = dwc3_gadget_ep_set_halt,
2327 .set_wedge = dwc3_gadget_ep_set_wedge,
2328};
2329
2330/* -------------------------------------------------------------------------- */
2331
2332static void dwc3_gadget_enable_linksts_evts(struct dwc3 *dwc, bool set)
2333{
2334 u32 reg;
2335
2336 if (DWC3_VER_IS_PRIOR(DWC3, 250A))
2337 return;
2338
2339 reg = dwc3_readl(dwc->regs, DWC3_DEVTEN);
2340 if (set)
2341 reg |= DWC3_DEVTEN_ULSTCNGEN;
2342 else
2343 reg &= ~DWC3_DEVTEN_ULSTCNGEN;
2344
2345 dwc3_writel(dwc->regs, DWC3_DEVTEN, reg);
2346}
2347
2348static int dwc3_gadget_get_frame(struct usb_gadget *g)
2349{
2350 struct dwc3 *dwc = gadget_to_dwc(g);
2351
2352 return __dwc3_gadget_get_frame(dwc);
2353}
2354
2355static int __dwc3_gadget_wakeup(struct dwc3 *dwc, bool async)
2356{
2357 int retries;
2358
2359 int ret;
2360 u32 reg;
2361
2362 u8 link_state;
2363
2364 /*
2365 * According to the Databook Remote wakeup request should
2366 * be issued only when the device is in early suspend state.
2367 *
2368 * We can check that via USB Link State bits in DSTS register.
2369 */
2370 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
2371
2372 link_state = DWC3_DSTS_USBLNKST(reg);
2373
2374 switch (link_state) {
2375 case DWC3_LINK_STATE_RESET:
2376 case DWC3_LINK_STATE_RX_DET: /* in HS, means Early Suspend */
2377 case DWC3_LINK_STATE_U3: /* in HS, means SUSPEND */
2378 case DWC3_LINK_STATE_U2: /* in HS, means Sleep (L1) */
2379 case DWC3_LINK_STATE_U1:
2380 case DWC3_LINK_STATE_RESUME:
2381 break;
2382 default:
2383 return -EINVAL;
2384 }
2385
2386 if (async)
2387 dwc3_gadget_enable_linksts_evts(dwc, true);
2388
2389 ret = dwc3_gadget_set_link_state(dwc, DWC3_LINK_STATE_RECOV);
2390 if (ret < 0) {
2391 dev_err(dwc->dev, "failed to put link in Recovery\n");
2392 dwc3_gadget_enable_linksts_evts(dwc, false);
2393 return ret;
2394 }
2395
2396 /* Recent versions do this automatically */
2397 if (DWC3_VER_IS_PRIOR(DWC3, 194A)) {
2398 /* write zeroes to Link Change Request */
2399 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2400 reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;
2401 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2402 }
2403
2404 /*
2405 * Since link status change events are enabled we will receive
2406 * an U0 event when wakeup is successful. So bail out.
2407 */
2408 if (async)
2409 return 0;
2410
2411 /* poll until Link State changes to ON */
2412 retries = 20000;
2413
2414 while (retries--) {
2415 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
2416
2417 /* in HS, means ON */
2418 if (DWC3_DSTS_USBLNKST(reg) == DWC3_LINK_STATE_U0)
2419 break;
2420 }
2421
2422 if (DWC3_DSTS_USBLNKST(reg) != DWC3_LINK_STATE_U0) {
2423 dev_err(dwc->dev, "failed to send remote wakeup\n");
2424 return -EINVAL;
2425 }
2426
2427 return 0;
2428}
2429
2430static int dwc3_gadget_wakeup(struct usb_gadget *g)
2431{
2432 struct dwc3 *dwc = gadget_to_dwc(g);
2433 unsigned long flags;
2434 int ret;
2435
2436 if (!dwc->wakeup_configured) {
2437 dev_err(dwc->dev, "remote wakeup not configured\n");
2438 return -EINVAL;
2439 }
2440
2441 spin_lock_irqsave(&dwc->lock, flags);
2442 if (!dwc->gadget->wakeup_armed) {
2443 dev_err(dwc->dev, "not armed for remote wakeup\n");
2444 spin_unlock_irqrestore(&dwc->lock, flags);
2445 return -EINVAL;
2446 }
2447 ret = __dwc3_gadget_wakeup(dwc, true);
2448
2449 spin_unlock_irqrestore(&dwc->lock, flags);
2450
2451 return ret;
2452}
2453
2454static void dwc3_resume_gadget(struct dwc3 *dwc);
2455
2456static int dwc3_gadget_func_wakeup(struct usb_gadget *g, int intf_id)
2457{
2458 struct dwc3 *dwc = gadget_to_dwc(g);
2459 unsigned long flags;
2460 int ret;
2461 int link_state;
2462
2463 if (!dwc->wakeup_configured) {
2464 dev_err(dwc->dev, "remote wakeup not configured\n");
2465 return -EINVAL;
2466 }
2467
2468 spin_lock_irqsave(&dwc->lock, flags);
2469 /*
2470 * If the link is in U3, signal for remote wakeup and wait for the
2471 * link to transition to U0 before sending device notification.
2472 */
2473 link_state = dwc3_gadget_get_link_state(dwc);
2474 if (link_state == DWC3_LINK_STATE_U3) {
2475 ret = __dwc3_gadget_wakeup(dwc, false);
2476 if (ret) {
2477 spin_unlock_irqrestore(&dwc->lock, flags);
2478 return -EINVAL;
2479 }
2480 dwc3_resume_gadget(dwc);
2481 dwc->suspended = false;
2482 dwc->link_state = DWC3_LINK_STATE_U0;
2483 }
2484
2485 ret = dwc3_send_gadget_generic_command(dwc, DWC3_DGCMD_DEV_NOTIFICATION,
2486 DWC3_DGCMDPAR_DN_FUNC_WAKE |
2487 DWC3_DGCMDPAR_INTF_SEL(intf_id));
2488 if (ret)
2489 dev_err(dwc->dev, "function remote wakeup failed, ret:%d\n", ret);
2490
2491 spin_unlock_irqrestore(&dwc->lock, flags);
2492
2493 return ret;
2494}
2495
2496static int dwc3_gadget_set_remote_wakeup(struct usb_gadget *g, int set)
2497{
2498 struct dwc3 *dwc = gadget_to_dwc(g);
2499 unsigned long flags;
2500
2501 spin_lock_irqsave(&dwc->lock, flags);
2502 dwc->wakeup_configured = !!set;
2503 spin_unlock_irqrestore(&dwc->lock, flags);
2504
2505 return 0;
2506}
2507
2508static int dwc3_gadget_set_selfpowered(struct usb_gadget *g,
2509 int is_selfpowered)
2510{
2511 struct dwc3 *dwc = gadget_to_dwc(g);
2512 unsigned long flags;
2513
2514 spin_lock_irqsave(&dwc->lock, flags);
2515 g->is_selfpowered = !!is_selfpowered;
2516 spin_unlock_irqrestore(&dwc->lock, flags);
2517
2518 return 0;
2519}
2520
2521static void dwc3_stop_active_transfers(struct dwc3 *dwc)
2522{
2523 u32 epnum;
2524
2525 for (epnum = 2; epnum < dwc->num_eps; epnum++) {
2526 struct dwc3_ep *dep;
2527
2528 dep = dwc->eps[epnum];
2529 if (!dep)
2530 continue;
2531
2532 dwc3_remove_requests(dwc, dep, -ESHUTDOWN);
2533 }
2534}
2535
2536static void __dwc3_gadget_set_ssp_rate(struct dwc3 *dwc)
2537{
2538 enum usb_ssp_rate ssp_rate = dwc->gadget_ssp_rate;
2539 u32 reg;
2540
2541 if (ssp_rate == USB_SSP_GEN_UNKNOWN)
2542 ssp_rate = dwc->max_ssp_rate;
2543
2544 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2545 reg &= ~DWC3_DCFG_SPEED_MASK;
2546 reg &= ~DWC3_DCFG_NUMLANES(~0);
2547
2548 if (ssp_rate == USB_SSP_GEN_1x2)
2549 reg |= DWC3_DCFG_SUPERSPEED;
2550 else if (dwc->max_ssp_rate != USB_SSP_GEN_1x2)
2551 reg |= DWC3_DCFG_SUPERSPEED_PLUS;
2552
2553 if (ssp_rate != USB_SSP_GEN_2x1 &&
2554 dwc->max_ssp_rate != USB_SSP_GEN_2x1)
2555 reg |= DWC3_DCFG_NUMLANES(1);
2556
2557 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2558}
2559
2560static void __dwc3_gadget_set_speed(struct dwc3 *dwc)
2561{
2562 enum usb_device_speed speed;
2563 u32 reg;
2564
2565 speed = dwc->gadget_max_speed;
2566 if (speed == USB_SPEED_UNKNOWN || speed > dwc->maximum_speed)
2567 speed = dwc->maximum_speed;
2568
2569 if (speed == USB_SPEED_SUPER_PLUS &&
2570 DWC3_IP_IS(DWC32)) {
2571 __dwc3_gadget_set_ssp_rate(dwc);
2572 return;
2573 }
2574
2575 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2576 reg &= ~(DWC3_DCFG_SPEED_MASK);
2577
2578 /*
2579 * WORKAROUND: DWC3 revision < 2.20a have an issue
2580 * which would cause metastability state on Run/Stop
2581 * bit if we try to force the IP to USB2-only mode.
2582 *
2583 * Because of that, we cannot configure the IP to any
2584 * speed other than the SuperSpeed
2585 *
2586 * Refers to:
2587 *
2588 * STAR#9000525659: Clock Domain Crossing on DCTL in
2589 * USB 2.0 Mode
2590 */
2591 if (DWC3_VER_IS_PRIOR(DWC3, 220A) &&
2592 !dwc->dis_metastability_quirk) {
2593 reg |= DWC3_DCFG_SUPERSPEED;
2594 } else {
2595 switch (speed) {
2596 case USB_SPEED_FULL:
2597 reg |= DWC3_DCFG_FULLSPEED;
2598 break;
2599 case USB_SPEED_HIGH:
2600 reg |= DWC3_DCFG_HIGHSPEED;
2601 break;
2602 case USB_SPEED_SUPER:
2603 reg |= DWC3_DCFG_SUPERSPEED;
2604 break;
2605 case USB_SPEED_SUPER_PLUS:
2606 if (DWC3_IP_IS(DWC3))
2607 reg |= DWC3_DCFG_SUPERSPEED;
2608 else
2609 reg |= DWC3_DCFG_SUPERSPEED_PLUS;
2610 break;
2611 default:
2612 dev_err(dwc->dev, "invalid speed (%d)\n", speed);
2613
2614 if (DWC3_IP_IS(DWC3))
2615 reg |= DWC3_DCFG_SUPERSPEED;
2616 else
2617 reg |= DWC3_DCFG_SUPERSPEED_PLUS;
2618 }
2619 }
2620
2621 if (DWC3_IP_IS(DWC32) &&
2622 speed > USB_SPEED_UNKNOWN &&
2623 speed < USB_SPEED_SUPER_PLUS)
2624 reg &= ~DWC3_DCFG_NUMLANES(~0);
2625
2626 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2627}
2628
2629static int dwc3_gadget_run_stop(struct dwc3 *dwc, int is_on)
2630{
2631 u32 reg;
2632 u32 timeout = 2000;
2633 u32 saved_config = 0;
2634
2635 if (pm_runtime_suspended(dwc->dev))
2636 return 0;
2637
2638 /*
2639 * When operating in USB 2.0 speeds (HS/FS), ensure that
2640 * GUSB2PHYCFG.ENBLSLPM and GUSB2PHYCFG.SUSPHY are cleared before starting
2641 * or stopping the controller. This resolves timeout issues that occur
2642 * during frequent role switches between host and device modes.
2643 *
2644 * Save and clear these settings, then restore them after completing the
2645 * controller start or stop sequence.
2646 *
2647 * This solution was discovered through experimentation as it is not
2648 * mentioned in the dwc3 programming guide. It has been tested on an
2649 * Exynos platforms.
2650 */
2651 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
2652 if (reg & DWC3_GUSB2PHYCFG_SUSPHY) {
2653 saved_config |= DWC3_GUSB2PHYCFG_SUSPHY;
2654 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
2655 }
2656
2657 if (reg & DWC3_GUSB2PHYCFG_ENBLSLPM) {
2658 saved_config |= DWC3_GUSB2PHYCFG_ENBLSLPM;
2659 reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM;
2660 }
2661
2662 if (saved_config)
2663 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
2664
2665 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2666 if (is_on) {
2667 if (DWC3_VER_IS_WITHIN(DWC3, ANY, 187A)) {
2668 reg &= ~DWC3_DCTL_TRGTULST_MASK;
2669 reg |= DWC3_DCTL_TRGTULST_RX_DET;
2670 }
2671
2672 if (!DWC3_VER_IS_PRIOR(DWC3, 194A))
2673 reg &= ~DWC3_DCTL_KEEP_CONNECT;
2674 reg |= DWC3_DCTL_RUN_STOP;
2675
2676 __dwc3_gadget_set_speed(dwc);
2677 dwc->pullups_connected = true;
2678 } else {
2679 reg &= ~DWC3_DCTL_RUN_STOP;
2680
2681 dwc->pullups_connected = false;
2682 }
2683
2684 dwc3_gadget_dctl_write_safe(dwc, reg);
2685
2686 do {
2687 usleep_range(1000, 2000);
2688 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
2689 reg &= DWC3_DSTS_DEVCTRLHLT;
2690 } while (--timeout && !(!is_on ^ !reg));
2691
2692 if (saved_config) {
2693 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
2694 reg |= saved_config;
2695 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
2696 }
2697
2698 if (!timeout)
2699 return -ETIMEDOUT;
2700
2701 return 0;
2702}
2703
2704static void dwc3_gadget_disable_irq(struct dwc3 *dwc);
2705static void __dwc3_gadget_stop(struct dwc3 *dwc);
2706static int __dwc3_gadget_start(struct dwc3 *dwc);
2707
2708static int dwc3_gadget_soft_disconnect(struct dwc3 *dwc)
2709{
2710 unsigned long flags;
2711 int ret;
2712
2713 spin_lock_irqsave(&dwc->lock, flags);
2714 if (!dwc->pullups_connected) {
2715 spin_unlock_irqrestore(&dwc->lock, flags);
2716 return 0;
2717 }
2718
2719 dwc->connected = false;
2720
2721 /*
2722 * Attempt to end pending SETUP status phase, and not wait for the
2723 * function to do so.
2724 */
2725 if (dwc->delayed_status)
2726 dwc3_ep0_send_delayed_status(dwc);
2727
2728 /*
2729 * In the Synopsys DesignWare Cores USB3 Databook Rev. 3.30a
2730 * Section 4.1.8 Table 4-7, it states that for a device-initiated
2731 * disconnect, the SW needs to ensure that it sends "a DEPENDXFER
2732 * command for any active transfers" before clearing the RunStop
2733 * bit.
2734 */
2735 dwc3_stop_active_transfers(dwc);
2736 spin_unlock_irqrestore(&dwc->lock, flags);
2737
2738 /*
2739 * Per databook, when we want to stop the gadget, if a control transfer
2740 * is still in process, complete it and get the core into setup phase.
2741 * In case the host is unresponsive to a SETUP transaction, forcefully
2742 * stall the transfer, and move back to the SETUP phase, so that any
2743 * pending endxfers can be executed.
2744 */
2745 if (dwc->ep0state != EP0_SETUP_PHASE) {
2746 reinit_completion(&dwc->ep0_in_setup);
2747
2748 ret = wait_for_completion_timeout(&dwc->ep0_in_setup,
2749 msecs_to_jiffies(DWC3_PULL_UP_TIMEOUT));
2750 if (ret == 0) {
2751 dev_warn(dwc->dev, "wait for SETUP phase timed out\n");
2752 spin_lock_irqsave(&dwc->lock, flags);
2753 dwc3_ep0_reset_state(dwc);
2754 spin_unlock_irqrestore(&dwc->lock, flags);
2755 }
2756 }
2757
2758 /*
2759 * Note: if the GEVNTCOUNT indicates events in the event buffer, the
2760 * driver needs to acknowledge them before the controller can halt.
2761 * Simply let the interrupt handler acknowledges and handle the
2762 * remaining event generated by the controller while polling for
2763 * DSTS.DEVCTLHLT.
2764 */
2765 ret = dwc3_gadget_run_stop(dwc, false);
2766
2767 /*
2768 * Stop the gadget after controller is halted, so that if needed, the
2769 * events to update EP0 state can still occur while the run/stop
2770 * routine polls for the halted state. DEVTEN is cleared as part of
2771 * gadget stop.
2772 */
2773 spin_lock_irqsave(&dwc->lock, flags);
2774 __dwc3_gadget_stop(dwc);
2775 spin_unlock_irqrestore(&dwc->lock, flags);
2776
2777 return ret;
2778}
2779
2780static int dwc3_gadget_soft_connect(struct dwc3 *dwc)
2781{
2782 int ret;
2783
2784 /*
2785 * In the Synopsys DWC_usb31 1.90a programming guide section
2786 * 4.1.9, it specifies that for a reconnect after a
2787 * device-initiated disconnect requires a core soft reset
2788 * (DCTL.CSftRst) before enabling the run/stop bit.
2789 */
2790 ret = dwc3_core_soft_reset(dwc);
2791 if (ret)
2792 return ret;
2793
2794 dwc3_event_buffers_setup(dwc);
2795 __dwc3_gadget_start(dwc);
2796 return dwc3_gadget_run_stop(dwc, true);
2797}
2798
2799static int dwc3_gadget_pullup(struct usb_gadget *g, int is_on)
2800{
2801 struct dwc3 *dwc = gadget_to_dwc(g);
2802 int ret;
2803
2804 is_on = !!is_on;
2805
2806 dwc->softconnect = is_on;
2807
2808 /*
2809 * Avoid issuing a runtime resume if the device is already in the
2810 * suspended state during gadget disconnect. DWC3 gadget was already
2811 * halted/stopped during runtime suspend.
2812 */
2813 if (!is_on) {
2814 pm_runtime_barrier(dwc->dev);
2815 if (pm_runtime_suspended(dwc->dev))
2816 return 0;
2817 }
2818
2819 /*
2820 * Check the return value for successful resume, or error. For a
2821 * successful resume, the DWC3 runtime PM resume routine will handle
2822 * the run stop sequence, so avoid duplicate operations here.
2823 */
2824 ret = pm_runtime_get_sync(dwc->dev);
2825 if (!ret || ret < 0) {
2826 pm_runtime_put(dwc->dev);
2827 if (ret < 0)
2828 pm_runtime_set_suspended(dwc->dev);
2829 return ret;
2830 }
2831
2832 if (dwc->pullups_connected == is_on) {
2833 pm_runtime_put(dwc->dev);
2834 return 0;
2835 }
2836
2837 synchronize_irq(dwc->irq_gadget);
2838
2839 if (!is_on)
2840 ret = dwc3_gadget_soft_disconnect(dwc);
2841 else
2842 ret = dwc3_gadget_soft_connect(dwc);
2843
2844 pm_runtime_put(dwc->dev);
2845
2846 return ret;
2847}
2848
2849static void dwc3_gadget_enable_irq(struct dwc3 *dwc)
2850{
2851 u32 reg;
2852
2853 /* Enable all but Start and End of Frame IRQs */
2854 reg = (DWC3_DEVTEN_EVNTOVERFLOWEN |
2855 DWC3_DEVTEN_CMDCMPLTEN |
2856 DWC3_DEVTEN_ERRTICERREN |
2857 DWC3_DEVTEN_WKUPEVTEN |
2858 DWC3_DEVTEN_CONNECTDONEEN |
2859 DWC3_DEVTEN_USBRSTEN |
2860 DWC3_DEVTEN_DISCONNEVTEN);
2861
2862 if (DWC3_VER_IS_PRIOR(DWC3, 250A))
2863 reg |= DWC3_DEVTEN_ULSTCNGEN;
2864
2865 /* On 2.30a and above this bit enables U3/L2-L1 Suspend Events */
2866 if (!DWC3_VER_IS_PRIOR(DWC3, 230A))
2867 reg |= DWC3_DEVTEN_U3L2L1SUSPEN;
2868
2869 dwc3_writel(dwc->regs, DWC3_DEVTEN, reg);
2870}
2871
2872static void dwc3_gadget_disable_irq(struct dwc3 *dwc)
2873{
2874 /* mask all interrupts */
2875 dwc3_writel(dwc->regs, DWC3_DEVTEN, 0x00);
2876}
2877
2878static irqreturn_t dwc3_interrupt(int irq, void *_dwc);
2879static irqreturn_t dwc3_thread_interrupt(int irq, void *_dwc);
2880
2881/**
2882 * dwc3_gadget_setup_nump - calculate and initialize NUMP field of %DWC3_DCFG
2883 * @dwc: pointer to our context structure
2884 *
2885 * The following looks like complex but it's actually very simple. In order to
2886 * calculate the number of packets we can burst at once on OUT transfers, we're
2887 * gonna use RxFIFO size.
2888 *
2889 * To calculate RxFIFO size we need two numbers:
2890 * MDWIDTH = size, in bits, of the internal memory bus
2891 * RAM2_DEPTH = depth, in MDWIDTH, of internal RAM2 (where RxFIFO sits)
2892 *
2893 * Given these two numbers, the formula is simple:
2894 *
2895 * RxFIFO Size = (RAM2_DEPTH * MDWIDTH / 8) - 24 - 16;
2896 *
2897 * 24 bytes is for 3x SETUP packets
2898 * 16 bytes is a clock domain crossing tolerance
2899 *
2900 * Given RxFIFO Size, NUMP = RxFIFOSize / 1024;
2901 */
2902static void dwc3_gadget_setup_nump(struct dwc3 *dwc)
2903{
2904 u32 ram2_depth;
2905 u32 mdwidth;
2906 u32 nump;
2907 u32 reg;
2908
2909 ram2_depth = DWC3_GHWPARAMS7_RAM2_DEPTH(dwc->hwparams.hwparams7);
2910 mdwidth = dwc3_mdwidth(dwc);
2911
2912 nump = ((ram2_depth * mdwidth / 8) - 24 - 16) / 1024;
2913 nump = min_t(u32, nump, 16);
2914
2915 /* update NumP */
2916 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2917 reg &= ~DWC3_DCFG_NUMP_MASK;
2918 reg |= nump << DWC3_DCFG_NUMP_SHIFT;
2919 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2920}
2921
2922static int __dwc3_gadget_start(struct dwc3 *dwc)
2923{
2924 struct dwc3_ep *dep;
2925 int ret = 0;
2926 u32 reg;
2927
2928 /*
2929 * Use IMOD if enabled via dwc->imod_interval. Otherwise, if
2930 * the core supports IMOD, disable it.
2931 */
2932 if (dwc->imod_interval) {
2933 dwc3_writel(dwc->regs, DWC3_DEV_IMOD(0), dwc->imod_interval);
2934 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), DWC3_GEVNTCOUNT_EHB);
2935 } else if (dwc3_has_imod(dwc)) {
2936 dwc3_writel(dwc->regs, DWC3_DEV_IMOD(0), 0);
2937 }
2938
2939 /*
2940 * We are telling dwc3 that we want to use DCFG.NUMP as ACK TP's NUMP
2941 * field instead of letting dwc3 itself calculate that automatically.
2942 *
2943 * This way, we maximize the chances that we'll be able to get several
2944 * bursts of data without going through any sort of endpoint throttling.
2945 */
2946 reg = dwc3_readl(dwc->regs, DWC3_GRXTHRCFG);
2947 if (DWC3_IP_IS(DWC3))
2948 reg &= ~DWC3_GRXTHRCFG_PKTCNTSEL;
2949 else
2950 reg &= ~DWC31_GRXTHRCFG_PKTCNTSEL;
2951
2952 dwc3_writel(dwc->regs, DWC3_GRXTHRCFG, reg);
2953
2954 dwc3_gadget_setup_nump(dwc);
2955
2956 /*
2957 * Currently the controller handles single stream only. So, Ignore
2958 * Packet Pending bit for stream selection and don't search for another
2959 * stream if the host sends Data Packet with PP=0 (for OUT direction) or
2960 * ACK with NumP=0 and PP=0 (for IN direction). This slightly improves
2961 * the stream performance.
2962 */
2963 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2964 reg |= DWC3_DCFG_IGNSTRMPP;
2965 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2966
2967 /* Enable MST by default if the device is capable of MST */
2968 if (DWC3_MST_CAPABLE(&dwc->hwparams)) {
2969 reg = dwc3_readl(dwc->regs, DWC3_DCFG1);
2970 reg &= ~DWC3_DCFG1_DIS_MST_ENH;
2971 dwc3_writel(dwc->regs, DWC3_DCFG1, reg);
2972 }
2973
2974 /* Start with SuperSpeed Default */
2975 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
2976
2977 ret = dwc3_gadget_start_config(dwc, 0);
2978 if (ret) {
2979 dev_err(dwc->dev, "failed to config endpoints\n");
2980 return ret;
2981 }
2982
2983 dep = dwc->eps[0];
2984 dep->flags = 0;
2985 ret = __dwc3_gadget_ep_enable(dep, DWC3_DEPCFG_ACTION_INIT);
2986 if (ret) {
2987 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
2988 goto err0;
2989 }
2990
2991 dep = dwc->eps[1];
2992 dep->flags = 0;
2993 ret = __dwc3_gadget_ep_enable(dep, DWC3_DEPCFG_ACTION_INIT);
2994 if (ret) {
2995 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
2996 goto err1;
2997 }
2998
2999 /* begin to receive SETUP packets */
3000 dwc->ep0state = EP0_SETUP_PHASE;
3001 dwc->ep0_bounced = false;
3002 dwc->link_state = DWC3_LINK_STATE_SS_DIS;
3003 dwc->delayed_status = false;
3004 dwc3_ep0_out_start(dwc);
3005
3006 dwc3_gadget_enable_irq(dwc);
3007 dwc3_enable_susphy(dwc, true);
3008
3009 return 0;
3010
3011err1:
3012 __dwc3_gadget_ep_disable(dwc->eps[0]);
3013
3014err0:
3015 return ret;
3016}
3017
3018static int dwc3_gadget_start(struct usb_gadget *g,
3019 struct usb_gadget_driver *driver)
3020{
3021 struct dwc3 *dwc = gadget_to_dwc(g);
3022 unsigned long flags;
3023 int ret;
3024 int irq;
3025
3026 irq = dwc->irq_gadget;
3027 ret = request_threaded_irq(irq, dwc3_interrupt, dwc3_thread_interrupt,
3028 IRQF_SHARED, "dwc3", dwc->ev_buf);
3029 if (ret) {
3030 dev_err(dwc->dev, "failed to request irq #%d --> %d\n",
3031 irq, ret);
3032 return ret;
3033 }
3034
3035 spin_lock_irqsave(&dwc->lock, flags);
3036 dwc->gadget_driver = driver;
3037 spin_unlock_irqrestore(&dwc->lock, flags);
3038
3039 if (dwc->sys_wakeup)
3040 device_wakeup_enable(dwc->sysdev);
3041
3042 return 0;
3043}
3044
3045static void __dwc3_gadget_stop(struct dwc3 *dwc)
3046{
3047 dwc3_gadget_disable_irq(dwc);
3048 __dwc3_gadget_ep_disable(dwc->eps[0]);
3049 __dwc3_gadget_ep_disable(dwc->eps[1]);
3050}
3051
3052static int dwc3_gadget_stop(struct usb_gadget *g)
3053{
3054 struct dwc3 *dwc = gadget_to_dwc(g);
3055 unsigned long flags;
3056
3057 if (dwc->sys_wakeup)
3058 device_wakeup_disable(dwc->sysdev);
3059
3060 spin_lock_irqsave(&dwc->lock, flags);
3061 dwc->gadget_driver = NULL;
3062 dwc->max_cfg_eps = 0;
3063 spin_unlock_irqrestore(&dwc->lock, flags);
3064
3065 free_irq(dwc->irq_gadget, dwc->ev_buf);
3066
3067 return 0;
3068}
3069
3070static void dwc3_gadget_config_params(struct usb_gadget *g,
3071 struct usb_dcd_config_params *params)
3072{
3073 struct dwc3 *dwc = gadget_to_dwc(g);
3074
3075 params->besl_baseline = USB_DEFAULT_BESL_UNSPECIFIED;
3076 params->besl_deep = USB_DEFAULT_BESL_UNSPECIFIED;
3077
3078 /* Recommended BESL */
3079 if (!dwc->dis_enblslpm_quirk) {
3080 /*
3081 * If the recommended BESL baseline is 0 or if the BESL deep is
3082 * less than 2, Microsoft's Windows 10 host usb stack will issue
3083 * a usb reset immediately after it receives the extended BOS
3084 * descriptor and the enumeration will fail. To maintain
3085 * compatibility with the Windows' usb stack, let's set the
3086 * recommended BESL baseline to 1 and clamp the BESL deep to be
3087 * within 2 to 15.
3088 */
3089 params->besl_baseline = 1;
3090 if (dwc->is_utmi_l1_suspend)
3091 params->besl_deep =
3092 clamp_t(u8, dwc->hird_threshold, 2, 15);
3093 }
3094
3095 /* U1 Device exit Latency */
3096 if (dwc->dis_u1_entry_quirk)
3097 params->bU1devExitLat = 0;
3098 else
3099 params->bU1devExitLat = DWC3_DEFAULT_U1_DEV_EXIT_LAT;
3100
3101 /* U2 Device exit Latency */
3102 if (dwc->dis_u2_entry_quirk)
3103 params->bU2DevExitLat = 0;
3104 else
3105 params->bU2DevExitLat =
3106 cpu_to_le16(DWC3_DEFAULT_U2_DEV_EXIT_LAT);
3107}
3108
3109static void dwc3_gadget_set_speed(struct usb_gadget *g,
3110 enum usb_device_speed speed)
3111{
3112 struct dwc3 *dwc = gadget_to_dwc(g);
3113 unsigned long flags;
3114
3115 spin_lock_irqsave(&dwc->lock, flags);
3116 dwc->gadget_max_speed = speed;
3117 spin_unlock_irqrestore(&dwc->lock, flags);
3118}
3119
3120static void dwc3_gadget_set_ssp_rate(struct usb_gadget *g,
3121 enum usb_ssp_rate rate)
3122{
3123 struct dwc3 *dwc = gadget_to_dwc(g);
3124 unsigned long flags;
3125
3126 spin_lock_irqsave(&dwc->lock, flags);
3127 dwc->gadget_max_speed = USB_SPEED_SUPER_PLUS;
3128 dwc->gadget_ssp_rate = rate;
3129 spin_unlock_irqrestore(&dwc->lock, flags);
3130}
3131
3132static int dwc3_gadget_vbus_draw(struct usb_gadget *g, unsigned int mA)
3133{
3134 struct dwc3 *dwc = gadget_to_dwc(g);
3135 union power_supply_propval val = {0};
3136 int ret;
3137
3138 if (dwc->usb2_phy)
3139 return usb_phy_set_power(dwc->usb2_phy, mA);
3140
3141 if (!dwc->usb_psy)
3142 return -EOPNOTSUPP;
3143
3144 val.intval = 1000 * mA;
3145 ret = power_supply_set_property(dwc->usb_psy, POWER_SUPPLY_PROP_INPUT_CURRENT_LIMIT, &val);
3146
3147 return ret;
3148}
3149
3150/**
3151 * dwc3_gadget_check_config - ensure dwc3 can support the USB configuration
3152 * @g: pointer to the USB gadget
3153 *
3154 * Used to record the maximum number of endpoints being used in a USB composite
3155 * device. (across all configurations) This is to be used in the calculation
3156 * of the TXFIFO sizes when resizing internal memory for individual endpoints.
3157 * It will help ensured that the resizing logic reserves enough space for at
3158 * least one max packet.
3159 */
3160static int dwc3_gadget_check_config(struct usb_gadget *g)
3161{
3162 struct dwc3 *dwc = gadget_to_dwc(g);
3163 struct usb_ep *ep;
3164 int fifo_size = 0;
3165 int ram_depth;
3166 int ep_num = 0;
3167
3168 if (!dwc->do_fifo_resize)
3169 return 0;
3170
3171 list_for_each_entry(ep, &g->ep_list, ep_list) {
3172 /* Only interested in the IN endpoints */
3173 if (ep->claimed && (ep->address & USB_DIR_IN))
3174 ep_num++;
3175 }
3176
3177 if (ep_num <= dwc->max_cfg_eps)
3178 return 0;
3179
3180 /* Update the max number of eps in the composition */
3181 dwc->max_cfg_eps = ep_num;
3182
3183 fifo_size = dwc3_gadget_calc_tx_fifo_size(dwc, dwc->max_cfg_eps);
3184 /* Based on the equation, increment by one for every ep */
3185 fifo_size += dwc->max_cfg_eps;
3186
3187 /* Check if we can fit a single fifo per endpoint */
3188 ram_depth = dwc3_gadget_calc_ram_depth(dwc);
3189 if (fifo_size > ram_depth)
3190 return -ENOMEM;
3191
3192 return 0;
3193}
3194
3195static void dwc3_gadget_async_callbacks(struct usb_gadget *g, bool enable)
3196{
3197 struct dwc3 *dwc = gadget_to_dwc(g);
3198 unsigned long flags;
3199
3200 spin_lock_irqsave(&dwc->lock, flags);
3201 dwc->async_callbacks = enable;
3202 spin_unlock_irqrestore(&dwc->lock, flags);
3203}
3204
3205static const struct usb_gadget_ops dwc3_gadget_ops = {
3206 .get_frame = dwc3_gadget_get_frame,
3207 .wakeup = dwc3_gadget_wakeup,
3208 .func_wakeup = dwc3_gadget_func_wakeup,
3209 .set_remote_wakeup = dwc3_gadget_set_remote_wakeup,
3210 .set_selfpowered = dwc3_gadget_set_selfpowered,
3211 .pullup = dwc3_gadget_pullup,
3212 .udc_start = dwc3_gadget_start,
3213 .udc_stop = dwc3_gadget_stop,
3214 .udc_set_speed = dwc3_gadget_set_speed,
3215 .udc_set_ssp_rate = dwc3_gadget_set_ssp_rate,
3216 .get_config_params = dwc3_gadget_config_params,
3217 .vbus_draw = dwc3_gadget_vbus_draw,
3218 .check_config = dwc3_gadget_check_config,
3219 .udc_async_callbacks = dwc3_gadget_async_callbacks,
3220};
3221
3222/* -------------------------------------------------------------------------- */
3223
3224static int dwc3_gadget_init_control_endpoint(struct dwc3_ep *dep)
3225{
3226 struct dwc3 *dwc = dep->dwc;
3227
3228 usb_ep_set_maxpacket_limit(&dep->endpoint, 512);
3229 dep->endpoint.maxburst = 1;
3230 dep->endpoint.ops = &dwc3_gadget_ep0_ops;
3231 if (!dep->direction)
3232 dwc->gadget->ep0 = &dep->endpoint;
3233
3234 dep->endpoint.caps.type_control = true;
3235
3236 return 0;
3237}
3238
3239static int dwc3_gadget_init_in_endpoint(struct dwc3_ep *dep)
3240{
3241 struct dwc3 *dwc = dep->dwc;
3242 u32 mdwidth;
3243 int size;
3244 int maxpacket;
3245
3246 mdwidth = dwc3_mdwidth(dwc);
3247
3248 /* MDWIDTH is represented in bits, we need it in bytes */
3249 mdwidth /= 8;
3250
3251 size = dwc3_readl(dwc->regs, DWC3_GTXFIFOSIZ(dep->number >> 1));
3252 if (DWC3_IP_IS(DWC3))
3253 size = DWC3_GTXFIFOSIZ_TXFDEP(size);
3254 else
3255 size = DWC31_GTXFIFOSIZ_TXFDEP(size);
3256
3257 /*
3258 * maxpacket size is determined as part of the following, after assuming
3259 * a mult value of one maxpacket:
3260 * DWC3 revision 280A and prior:
3261 * fifo_size = mult * (max_packet / mdwidth) + 1;
3262 * maxpacket = mdwidth * (fifo_size - 1);
3263 *
3264 * DWC3 revision 290A and onwards:
3265 * fifo_size = mult * ((max_packet + mdwidth)/mdwidth + 1) + 1
3266 * maxpacket = mdwidth * ((fifo_size - 1) - 1) - mdwidth;
3267 */
3268 if (DWC3_VER_IS_PRIOR(DWC3, 290A))
3269 maxpacket = mdwidth * (size - 1);
3270 else
3271 maxpacket = mdwidth * ((size - 1) - 1) - mdwidth;
3272
3273 /* Functionally, space for one max packet is sufficient */
3274 size = min_t(int, maxpacket, 1024);
3275 usb_ep_set_maxpacket_limit(&dep->endpoint, size);
3276
3277 dep->endpoint.max_streams = 16;
3278 dep->endpoint.ops = &dwc3_gadget_ep_ops;
3279 list_add_tail(&dep->endpoint.ep_list,
3280 &dwc->gadget->ep_list);
3281 dep->endpoint.caps.type_iso = true;
3282 dep->endpoint.caps.type_bulk = true;
3283 dep->endpoint.caps.type_int = true;
3284
3285 return dwc3_alloc_trb_pool(dep);
3286}
3287
3288static int dwc3_gadget_init_out_endpoint(struct dwc3_ep *dep)
3289{
3290 struct dwc3 *dwc = dep->dwc;
3291 u32 mdwidth;
3292 int size;
3293
3294 mdwidth = dwc3_mdwidth(dwc);
3295
3296 /* MDWIDTH is represented in bits, convert to bytes */
3297 mdwidth /= 8;
3298
3299 /* All OUT endpoints share a single RxFIFO space */
3300 size = dwc3_readl(dwc->regs, DWC3_GRXFIFOSIZ(0));
3301 if (DWC3_IP_IS(DWC3))
3302 size = DWC3_GRXFIFOSIZ_RXFDEP(size);
3303 else
3304 size = DWC31_GRXFIFOSIZ_RXFDEP(size);
3305
3306 /* FIFO depth is in MDWDITH bytes */
3307 size *= mdwidth;
3308
3309 /*
3310 * To meet performance requirement, a minimum recommended RxFIFO size
3311 * is defined as follow:
3312 * RxFIFO size >= (3 x MaxPacketSize) +
3313 * (3 x 8 bytes setup packets size) + (16 bytes clock crossing margin)
3314 *
3315 * Then calculate the max packet limit as below.
3316 */
3317 size -= (3 * 8) + 16;
3318 if (size < 0)
3319 size = 0;
3320 else
3321 size /= 3;
3322
3323 usb_ep_set_maxpacket_limit(&dep->endpoint, size);
3324 dep->endpoint.max_streams = 16;
3325 dep->endpoint.ops = &dwc3_gadget_ep_ops;
3326 list_add_tail(&dep->endpoint.ep_list,
3327 &dwc->gadget->ep_list);
3328 dep->endpoint.caps.type_iso = true;
3329 dep->endpoint.caps.type_bulk = true;
3330 dep->endpoint.caps.type_int = true;
3331
3332 return dwc3_alloc_trb_pool(dep);
3333}
3334
3335static int dwc3_gadget_init_endpoint(struct dwc3 *dwc, u8 epnum)
3336{
3337 struct dwc3_ep *dep;
3338 bool direction = epnum & 1;
3339 int ret;
3340 u8 num = epnum >> 1;
3341
3342 dep = kzalloc(sizeof(*dep), GFP_KERNEL);
3343 if (!dep)
3344 return -ENOMEM;
3345
3346 dep->dwc = dwc;
3347 dep->number = epnum;
3348 dep->direction = direction;
3349 dep->regs = dwc->regs + DWC3_DEP_BASE(epnum);
3350 dwc->eps[epnum] = dep;
3351 dep->combo_num = 0;
3352 dep->start_cmd_status = 0;
3353
3354 snprintf(dep->name, sizeof(dep->name), "ep%u%s", num,
3355 direction ? "in" : "out");
3356
3357 dep->endpoint.name = dep->name;
3358
3359 if (!(dep->number > 1)) {
3360 dep->endpoint.desc = &dwc3_gadget_ep0_desc;
3361 dep->endpoint.comp_desc = NULL;
3362 }
3363
3364 if (num == 0)
3365 ret = dwc3_gadget_init_control_endpoint(dep);
3366 else if (direction)
3367 ret = dwc3_gadget_init_in_endpoint(dep);
3368 else
3369 ret = dwc3_gadget_init_out_endpoint(dep);
3370
3371 if (ret)
3372 return ret;
3373
3374 dep->endpoint.caps.dir_in = direction;
3375 dep->endpoint.caps.dir_out = !direction;
3376
3377 INIT_LIST_HEAD(&dep->pending_list);
3378 INIT_LIST_HEAD(&dep->started_list);
3379 INIT_LIST_HEAD(&dep->cancelled_list);
3380
3381 dwc3_debugfs_create_endpoint_dir(dep);
3382
3383 return 0;
3384}
3385
3386static int dwc3_gadget_init_endpoints(struct dwc3 *dwc, u8 total)
3387{
3388 u8 epnum;
3389
3390 INIT_LIST_HEAD(&dwc->gadget->ep_list);
3391
3392 for (epnum = 0; epnum < total; epnum++) {
3393 int ret;
3394
3395 ret = dwc3_gadget_init_endpoint(dwc, epnum);
3396 if (ret)
3397 return ret;
3398 }
3399
3400 return 0;
3401}
3402
3403static void dwc3_gadget_free_endpoints(struct dwc3 *dwc)
3404{
3405 struct dwc3_ep *dep;
3406 u8 epnum;
3407
3408 for (epnum = 0; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
3409 dep = dwc->eps[epnum];
3410 if (!dep)
3411 continue;
3412 /*
3413 * Physical endpoints 0 and 1 are special; they form the
3414 * bi-directional USB endpoint 0.
3415 *
3416 * For those two physical endpoints, we don't allocate a TRB
3417 * pool nor do we add them the endpoints list. Due to that, we
3418 * shouldn't do these two operations otherwise we would end up
3419 * with all sorts of bugs when removing dwc3.ko.
3420 */
3421 if (epnum != 0 && epnum != 1) {
3422 dwc3_free_trb_pool(dep);
3423 list_del(&dep->endpoint.ep_list);
3424 }
3425
3426 dwc3_debugfs_remove_endpoint_dir(dep);
3427 kfree(dep);
3428 }
3429}
3430
3431/* -------------------------------------------------------------------------- */
3432
3433static int dwc3_gadget_ep_reclaim_completed_trb(struct dwc3_ep *dep,
3434 struct dwc3_request *req, struct dwc3_trb *trb,
3435 const struct dwc3_event_depevt *event, int status, int chain)
3436{
3437 unsigned int count;
3438
3439 dwc3_ep_inc_deq(dep);
3440
3441 trace_dwc3_complete_trb(dep, trb);
3442 req->num_trbs--;
3443
3444 /*
3445 * If we're in the middle of series of chained TRBs and we
3446 * receive a short transfer along the way, DWC3 will skip
3447 * through all TRBs including the last TRB in the chain (the
3448 * where CHN bit is zero. DWC3 will also avoid clearing HWO
3449 * bit and SW has to do it manually.
3450 *
3451 * We're going to do that here to avoid problems of HW trying
3452 * to use bogus TRBs for transfers.
3453 */
3454 if (chain && (trb->ctrl & DWC3_TRB_CTRL_HWO))
3455 trb->ctrl &= ~DWC3_TRB_CTRL_HWO;
3456
3457 /*
3458 * For isochronous transfers, the first TRB in a service interval must
3459 * have the Isoc-First type. Track and report its interval frame number.
3460 */
3461 if (usb_endpoint_xfer_isoc(dep->endpoint.desc) &&
3462 (trb->ctrl & DWC3_TRBCTL_ISOCHRONOUS_FIRST)) {
3463 unsigned int frame_number;
3464
3465 frame_number = DWC3_TRB_CTRL_GET_SID_SOFN(trb->ctrl);
3466 frame_number &= ~(dep->interval - 1);
3467 req->request.frame_number = frame_number;
3468 }
3469
3470 /*
3471 * We use bounce buffer for requests that needs extra TRB or OUT ZLP. If
3472 * this TRB points to the bounce buffer address, it's a MPS alignment
3473 * TRB. Don't add it to req->remaining calculation.
3474 */
3475 if (trb->bpl == lower_32_bits(dep->dwc->bounce_addr) &&
3476 trb->bph == upper_32_bits(dep->dwc->bounce_addr)) {
3477 trb->ctrl &= ~DWC3_TRB_CTRL_HWO;
3478 return 1;
3479 }
3480
3481 count = trb->size & DWC3_TRB_SIZE_MASK;
3482 req->remaining += count;
3483
3484 if ((trb->ctrl & DWC3_TRB_CTRL_HWO) && status != -ESHUTDOWN)
3485 return 1;
3486
3487 if (event->status & DEPEVT_STATUS_SHORT && !chain)
3488 return 1;
3489
3490 if ((trb->ctrl & DWC3_TRB_CTRL_ISP_IMI) &&
3491 DWC3_TRB_SIZE_TRBSTS(trb->size) == DWC3_TRBSTS_MISSED_ISOC)
3492 return 1;
3493
3494 if ((trb->ctrl & DWC3_TRB_CTRL_IOC) ||
3495 (trb->ctrl & DWC3_TRB_CTRL_LST))
3496 return 1;
3497
3498 return 0;
3499}
3500
3501static int dwc3_gadget_ep_reclaim_trb_sg(struct dwc3_ep *dep,
3502 struct dwc3_request *req, const struct dwc3_event_depevt *event,
3503 int status)
3504{
3505 struct dwc3_trb *trb;
3506 unsigned int num_completed_trbs = req->num_trbs;
3507 unsigned int i;
3508 int ret = 0;
3509
3510 for (i = 0; i < num_completed_trbs; i++) {
3511 trb = &dep->trb_pool[dep->trb_dequeue];
3512
3513 ret = dwc3_gadget_ep_reclaim_completed_trb(dep, req,
3514 trb, event, status,
3515 !!(trb->ctrl & DWC3_TRB_CTRL_CHN));
3516 if (ret)
3517 break;
3518 }
3519
3520 return ret;
3521}
3522
3523static bool dwc3_gadget_ep_request_completed(struct dwc3_request *req)
3524{
3525 return req->num_pending_sgs == 0 && req->num_trbs == 0;
3526}
3527
3528static int dwc3_gadget_ep_cleanup_completed_request(struct dwc3_ep *dep,
3529 const struct dwc3_event_depevt *event,
3530 struct dwc3_request *req, int status)
3531{
3532 int request_status;
3533 int ret;
3534
3535 ret = dwc3_gadget_ep_reclaim_trb_sg(dep, req, event, status);
3536
3537 req->request.actual = req->request.length - req->remaining;
3538
3539 if (!dwc3_gadget_ep_request_completed(req))
3540 goto out;
3541
3542 /*
3543 * The event status only reflects the status of the TRB with IOC set.
3544 * For the requests that don't set interrupt on completion, the driver
3545 * needs to check and return the status of the completed TRBs associated
3546 * with the request. Use the status of the last TRB of the request.
3547 */
3548 if (req->request.no_interrupt) {
3549 struct dwc3_trb *trb;
3550
3551 trb = dwc3_ep_prev_trb(dep, dep->trb_dequeue);
3552 switch (DWC3_TRB_SIZE_TRBSTS(trb->size)) {
3553 case DWC3_TRBSTS_MISSED_ISOC:
3554 /* Isoc endpoint only */
3555 request_status = -EXDEV;
3556 break;
3557 case DWC3_TRB_STS_XFER_IN_PROG:
3558 /* Applicable when End Transfer with ForceRM=0 */
3559 case DWC3_TRBSTS_SETUP_PENDING:
3560 /* Control endpoint only */
3561 case DWC3_TRBSTS_OK:
3562 default:
3563 request_status = 0;
3564 break;
3565 }
3566 } else {
3567 request_status = status;
3568 }
3569
3570 dwc3_gadget_giveback(dep, req, request_status);
3571
3572out:
3573 return ret;
3574}
3575
3576static void dwc3_gadget_ep_cleanup_completed_requests(struct dwc3_ep *dep,
3577 const struct dwc3_event_depevt *event, int status)
3578{
3579 struct dwc3_request *req;
3580
3581 while (!list_empty(&dep->started_list)) {
3582 int ret;
3583
3584 req = next_request(&dep->started_list);
3585 ret = dwc3_gadget_ep_cleanup_completed_request(dep, event,
3586 req, status);
3587 if (ret)
3588 break;
3589 /*
3590 * The endpoint is disabled, let the dwc3_remove_requests()
3591 * handle the cleanup.
3592 */
3593 if (!dep->endpoint.desc)
3594 break;
3595 }
3596}
3597
3598static bool dwc3_gadget_ep_should_continue(struct dwc3_ep *dep)
3599{
3600 struct dwc3_request *req;
3601 struct dwc3 *dwc = dep->dwc;
3602
3603 if (!dep->endpoint.desc || !dwc->pullups_connected ||
3604 !dwc->connected)
3605 return false;
3606
3607 if (!list_empty(&dep->pending_list))
3608 return true;
3609
3610 /*
3611 * We only need to check the first entry of the started list. We can
3612 * assume the completed requests are removed from the started list.
3613 */
3614 req = next_request(&dep->started_list);
3615 if (!req)
3616 return false;
3617
3618 return !dwc3_gadget_ep_request_completed(req);
3619}
3620
3621static void dwc3_gadget_endpoint_frame_from_event(struct dwc3_ep *dep,
3622 const struct dwc3_event_depevt *event)
3623{
3624 dep->frame_number = event->parameters;
3625}
3626
3627static bool dwc3_gadget_endpoint_trbs_complete(struct dwc3_ep *dep,
3628 const struct dwc3_event_depevt *event, int status)
3629{
3630 struct dwc3 *dwc = dep->dwc;
3631 bool no_started_trb = true;
3632
3633 dwc3_gadget_ep_cleanup_completed_requests(dep, event, status);
3634
3635 if (dep->flags & DWC3_EP_END_TRANSFER_PENDING)
3636 goto out;
3637
3638 if (!dep->endpoint.desc)
3639 return no_started_trb;
3640
3641 if (usb_endpoint_xfer_isoc(dep->endpoint.desc) &&
3642 list_empty(&dep->started_list) &&
3643 (list_empty(&dep->pending_list) || status == -EXDEV))
3644 dwc3_stop_active_transfer(dep, true, true);
3645 else if (dwc3_gadget_ep_should_continue(dep))
3646 if (__dwc3_gadget_kick_transfer(dep) == 0)
3647 no_started_trb = false;
3648
3649out:
3650 /*
3651 * WORKAROUND: This is the 2nd half of U1/U2 -> U0 workaround.
3652 * See dwc3_gadget_linksts_change_interrupt() for 1st half.
3653 */
3654 if (DWC3_VER_IS_PRIOR(DWC3, 183A)) {
3655 u32 reg;
3656 int i;
3657
3658 for (i = 0; i < DWC3_ENDPOINTS_NUM; i++) {
3659 dep = dwc->eps[i];
3660
3661 if (!(dep->flags & DWC3_EP_ENABLED))
3662 continue;
3663
3664 if (!list_empty(&dep->started_list))
3665 return no_started_trb;
3666 }
3667
3668 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
3669 reg |= dwc->u1u2;
3670 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
3671
3672 dwc->u1u2 = 0;
3673 }
3674
3675 return no_started_trb;
3676}
3677
3678static void dwc3_gadget_endpoint_transfer_in_progress(struct dwc3_ep *dep,
3679 const struct dwc3_event_depevt *event)
3680{
3681 int status = 0;
3682
3683 if (!dep->endpoint.desc)
3684 return;
3685
3686 if (usb_endpoint_xfer_isoc(dep->endpoint.desc))
3687 dwc3_gadget_endpoint_frame_from_event(dep, event);
3688
3689 if (event->status & DEPEVT_STATUS_BUSERR)
3690 status = -ECONNRESET;
3691
3692 if (event->status & DEPEVT_STATUS_MISSED_ISOC)
3693 status = -EXDEV;
3694
3695 dwc3_gadget_endpoint_trbs_complete(dep, event, status);
3696}
3697
3698static void dwc3_gadget_endpoint_transfer_complete(struct dwc3_ep *dep,
3699 const struct dwc3_event_depevt *event)
3700{
3701 int status = 0;
3702
3703 dep->flags &= ~DWC3_EP_TRANSFER_STARTED;
3704
3705 if (event->status & DEPEVT_STATUS_BUSERR)
3706 status = -ECONNRESET;
3707
3708 if (dwc3_gadget_endpoint_trbs_complete(dep, event, status))
3709 dep->flags &= ~DWC3_EP_WAIT_TRANSFER_COMPLETE;
3710}
3711
3712static void dwc3_gadget_endpoint_transfer_not_ready(struct dwc3_ep *dep,
3713 const struct dwc3_event_depevt *event)
3714{
3715 dwc3_gadget_endpoint_frame_from_event(dep, event);
3716
3717 /*
3718 * The XferNotReady event is generated only once before the endpoint
3719 * starts. It will be generated again when END_TRANSFER command is
3720 * issued. For some controller versions, the XferNotReady event may be
3721 * generated while the END_TRANSFER command is still in process. Ignore
3722 * it and wait for the next XferNotReady event after the command is
3723 * completed.
3724 */
3725 if (dep->flags & DWC3_EP_END_TRANSFER_PENDING)
3726 return;
3727
3728 (void) __dwc3_gadget_start_isoc(dep);
3729}
3730
3731static void dwc3_gadget_endpoint_command_complete(struct dwc3_ep *dep,
3732 const struct dwc3_event_depevt *event)
3733{
3734 u8 cmd = DEPEVT_PARAMETER_CMD(event->parameters);
3735
3736 if (cmd != DWC3_DEPCMD_ENDTRANSFER)
3737 return;
3738
3739 /*
3740 * The END_TRANSFER command will cause the controller to generate a
3741 * NoStream Event, and it's not due to the host DP NoStream rejection.
3742 * Ignore the next NoStream event.
3743 */
3744 if (dep->stream_capable)
3745 dep->flags |= DWC3_EP_IGNORE_NEXT_NOSTREAM;
3746
3747 dep->flags &= ~DWC3_EP_END_TRANSFER_PENDING;
3748 dep->flags &= ~DWC3_EP_TRANSFER_STARTED;
3749 dwc3_gadget_ep_cleanup_cancelled_requests(dep);
3750
3751 if (dep->flags & DWC3_EP_PENDING_CLEAR_STALL) {
3752 struct dwc3 *dwc = dep->dwc;
3753
3754 dep->flags &= ~DWC3_EP_PENDING_CLEAR_STALL;
3755 if (dwc3_send_clear_stall_ep_cmd(dep)) {
3756 struct usb_ep *ep0 = &dwc->eps[0]->endpoint;
3757
3758 dev_err(dwc->dev, "failed to clear STALL on %s\n", dep->name);
3759 if (dwc->delayed_status)
3760 __dwc3_gadget_ep0_set_halt(ep0, 1);
3761 return;
3762 }
3763
3764 dep->flags &= ~(DWC3_EP_STALL | DWC3_EP_WEDGE);
3765 if (dwc->clear_stall_protocol == dep->number)
3766 dwc3_ep0_send_delayed_status(dwc);
3767 }
3768
3769 if ((dep->flags & DWC3_EP_DELAY_START) &&
3770 !usb_endpoint_xfer_isoc(dep->endpoint.desc))
3771 __dwc3_gadget_kick_transfer(dep);
3772
3773 dep->flags &= ~DWC3_EP_DELAY_START;
3774}
3775
3776static void dwc3_gadget_endpoint_stream_event(struct dwc3_ep *dep,
3777 const struct dwc3_event_depevt *event)
3778{
3779 struct dwc3 *dwc = dep->dwc;
3780
3781 if (event->status == DEPEVT_STREAMEVT_FOUND) {
3782 dep->flags |= DWC3_EP_FIRST_STREAM_PRIMED;
3783 goto out;
3784 }
3785
3786 /* Note: NoStream rejection event param value is 0 and not 0xFFFF */
3787 switch (event->parameters) {
3788 case DEPEVT_STREAM_PRIME:
3789 /*
3790 * If the host can properly transition the endpoint state from
3791 * idle to prime after a NoStream rejection, there's no need to
3792 * force restarting the endpoint to reinitiate the stream. To
3793 * simplify the check, assume the host follows the USB spec if
3794 * it primed the endpoint more than once.
3795 */
3796 if (dep->flags & DWC3_EP_FORCE_RESTART_STREAM) {
3797 if (dep->flags & DWC3_EP_FIRST_STREAM_PRIMED)
3798 dep->flags &= ~DWC3_EP_FORCE_RESTART_STREAM;
3799 else
3800 dep->flags |= DWC3_EP_FIRST_STREAM_PRIMED;
3801 }
3802
3803 break;
3804 case DEPEVT_STREAM_NOSTREAM:
3805 if ((dep->flags & DWC3_EP_IGNORE_NEXT_NOSTREAM) ||
3806 !(dep->flags & DWC3_EP_FORCE_RESTART_STREAM) ||
3807 (!DWC3_MST_CAPABLE(&dwc->hwparams) &&
3808 !(dep->flags & DWC3_EP_WAIT_TRANSFER_COMPLETE)))
3809 break;
3810
3811 /*
3812 * If the host rejects a stream due to no active stream, by the
3813 * USB and xHCI spec, the endpoint will be put back to idle
3814 * state. When the host is ready (buffer added/updated), it will
3815 * prime the endpoint to inform the usb device controller. This
3816 * triggers the device controller to issue ERDY to restart the
3817 * stream. However, some hosts don't follow this and keep the
3818 * endpoint in the idle state. No prime will come despite host
3819 * streams are updated, and the device controller will not be
3820 * triggered to generate ERDY to move the next stream data. To
3821 * workaround this and maintain compatibility with various
3822 * hosts, force to reinitiate the stream until the host is ready
3823 * instead of waiting for the host to prime the endpoint.
3824 */
3825 if (DWC3_VER_IS_WITHIN(DWC32, 100A, ANY)) {
3826 unsigned int cmd = DWC3_DGCMD_SET_ENDPOINT_PRIME;
3827
3828 dwc3_send_gadget_generic_command(dwc, cmd, dep->number);
3829 } else {
3830 dep->flags |= DWC3_EP_DELAY_START;
3831 dwc3_stop_active_transfer(dep, true, true);
3832 return;
3833 }
3834 break;
3835 }
3836
3837out:
3838 dep->flags &= ~DWC3_EP_IGNORE_NEXT_NOSTREAM;
3839}
3840
3841static void dwc3_endpoint_interrupt(struct dwc3 *dwc,
3842 const struct dwc3_event_depevt *event)
3843{
3844 struct dwc3_ep *dep;
3845 u8 epnum = event->endpoint_number;
3846
3847 dep = dwc->eps[epnum];
3848
3849 if (!(dep->flags & DWC3_EP_ENABLED)) {
3850 if ((epnum > 1) && !(dep->flags & DWC3_EP_TRANSFER_STARTED))
3851 return;
3852
3853 /* Handle only EPCMDCMPLT when EP disabled */
3854 if ((event->endpoint_event != DWC3_DEPEVT_EPCMDCMPLT) &&
3855 !(epnum <= 1 && event->endpoint_event == DWC3_DEPEVT_XFERCOMPLETE))
3856 return;
3857 }
3858
3859 if (epnum == 0 || epnum == 1) {
3860 dwc3_ep0_interrupt(dwc, event);
3861 return;
3862 }
3863
3864 switch (event->endpoint_event) {
3865 case DWC3_DEPEVT_XFERINPROGRESS:
3866 dwc3_gadget_endpoint_transfer_in_progress(dep, event);
3867 break;
3868 case DWC3_DEPEVT_XFERNOTREADY:
3869 dwc3_gadget_endpoint_transfer_not_ready(dep, event);
3870 break;
3871 case DWC3_DEPEVT_EPCMDCMPLT:
3872 dwc3_gadget_endpoint_command_complete(dep, event);
3873 break;
3874 case DWC3_DEPEVT_XFERCOMPLETE:
3875 dwc3_gadget_endpoint_transfer_complete(dep, event);
3876 break;
3877 case DWC3_DEPEVT_STREAMEVT:
3878 dwc3_gadget_endpoint_stream_event(dep, event);
3879 break;
3880 case DWC3_DEPEVT_RXTXFIFOEVT:
3881 break;
3882 default:
3883 dev_err(dwc->dev, "unknown endpoint event %d\n", event->endpoint_event);
3884 break;
3885 }
3886}
3887
3888static void dwc3_disconnect_gadget(struct dwc3 *dwc)
3889{
3890 if (dwc->async_callbacks && dwc->gadget_driver->disconnect) {
3891 spin_unlock(&dwc->lock);
3892 dwc->gadget_driver->disconnect(dwc->gadget);
3893 spin_lock(&dwc->lock);
3894 }
3895}
3896
3897static void dwc3_suspend_gadget(struct dwc3 *dwc)
3898{
3899 if (dwc->async_callbacks && dwc->gadget_driver->suspend) {
3900 spin_unlock(&dwc->lock);
3901 dwc->gadget_driver->suspend(dwc->gadget);
3902 spin_lock(&dwc->lock);
3903 }
3904}
3905
3906static void dwc3_resume_gadget(struct dwc3 *dwc)
3907{
3908 if (dwc->async_callbacks && dwc->gadget_driver->resume) {
3909 spin_unlock(&dwc->lock);
3910 dwc->gadget_driver->resume(dwc->gadget);
3911 spin_lock(&dwc->lock);
3912 }
3913}
3914
3915static void dwc3_reset_gadget(struct dwc3 *dwc)
3916{
3917 if (!dwc->gadget_driver)
3918 return;
3919
3920 if (dwc->async_callbacks && dwc->gadget->speed != USB_SPEED_UNKNOWN) {
3921 spin_unlock(&dwc->lock);
3922 usb_gadget_udc_reset(dwc->gadget, dwc->gadget_driver);
3923 spin_lock(&dwc->lock);
3924 }
3925}
3926
3927void dwc3_stop_active_transfer(struct dwc3_ep *dep, bool force,
3928 bool interrupt)
3929{
3930 struct dwc3 *dwc = dep->dwc;
3931
3932 /*
3933 * Only issue End Transfer command to the control endpoint of a started
3934 * Data Phase. Typically we should only do so in error cases such as
3935 * invalid/unexpected direction as described in the control transfer
3936 * flow of the programming guide.
3937 */
3938 if (dep->number <= 1 && dwc->ep0state != EP0_DATA_PHASE)
3939 return;
3940
3941 if (interrupt && (dep->flags & DWC3_EP_DELAY_STOP))
3942 return;
3943
3944 if (!(dep->flags & DWC3_EP_TRANSFER_STARTED) ||
3945 (dep->flags & DWC3_EP_END_TRANSFER_PENDING))
3946 return;
3947
3948 /*
3949 * If a Setup packet is received but yet to DMA out, the controller will
3950 * not process the End Transfer command of any endpoint. Polling of its
3951 * DEPCMD.CmdAct may block setting up TRB for Setup packet, causing a
3952 * timeout. Delay issuing the End Transfer command until the Setup TRB is
3953 * prepared.
3954 */
3955 if (dwc->ep0state != EP0_SETUP_PHASE && !dwc->delayed_status) {
3956 dep->flags |= DWC3_EP_DELAY_STOP;
3957 return;
3958 }
3959
3960 /*
3961 * NOTICE: We are violating what the Databook says about the
3962 * EndTransfer command. Ideally we would _always_ wait for the
3963 * EndTransfer Command Completion IRQ, but that's causing too
3964 * much trouble synchronizing between us and gadget driver.
3965 *
3966 * We have discussed this with the IP Provider and it was
3967 * suggested to giveback all requests here.
3968 *
3969 * Note also that a similar handling was tested by Synopsys
3970 * (thanks a lot Paul) and nothing bad has come out of it.
3971 * In short, what we're doing is issuing EndTransfer with
3972 * CMDIOC bit set and delay kicking transfer until the
3973 * EndTransfer command had completed.
3974 *
3975 * As of IP version 3.10a of the DWC_usb3 IP, the controller
3976 * supports a mode to work around the above limitation. The
3977 * software can poll the CMDACT bit in the DEPCMD register
3978 * after issuing a EndTransfer command. This mode is enabled
3979 * by writing GUCTL2[14]. This polling is already done in the
3980 * dwc3_send_gadget_ep_cmd() function so if the mode is
3981 * enabled, the EndTransfer command will have completed upon
3982 * returning from this function.
3983 *
3984 * This mode is NOT available on the DWC_usb31 IP. In this
3985 * case, if the IOC bit is not set, then delay by 1ms
3986 * after issuing the EndTransfer command. This allows for the
3987 * controller to handle the command completely before DWC3
3988 * remove requests attempts to unmap USB request buffers.
3989 */
3990
3991 __dwc3_stop_active_transfer(dep, force, interrupt);
3992}
3993
3994static void dwc3_clear_stall_all_ep(struct dwc3 *dwc)
3995{
3996 u32 epnum;
3997
3998 for (epnum = 1; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
3999 struct dwc3_ep *dep;
4000 int ret;
4001
4002 dep = dwc->eps[epnum];
4003 if (!dep)
4004 continue;
4005
4006 if (!(dep->flags & DWC3_EP_STALL))
4007 continue;
4008
4009 dep->flags &= ~DWC3_EP_STALL;
4010
4011 ret = dwc3_send_clear_stall_ep_cmd(dep);
4012 WARN_ON_ONCE(ret);
4013 }
4014}
4015
4016static void dwc3_gadget_disconnect_interrupt(struct dwc3 *dwc)
4017{
4018 int reg;
4019
4020 dwc->suspended = false;
4021
4022 dwc3_gadget_set_link_state(dwc, DWC3_LINK_STATE_RX_DET);
4023
4024 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
4025 reg &= ~DWC3_DCTL_INITU1ENA;
4026 reg &= ~DWC3_DCTL_INITU2ENA;
4027 dwc3_gadget_dctl_write_safe(dwc, reg);
4028
4029 dwc->connected = false;
4030
4031 dwc3_disconnect_gadget(dwc);
4032
4033 dwc->gadget->speed = USB_SPEED_UNKNOWN;
4034 dwc->setup_packet_pending = false;
4035 dwc->gadget->wakeup_armed = false;
4036 dwc3_gadget_enable_linksts_evts(dwc, false);
4037 usb_gadget_set_state(dwc->gadget, USB_STATE_NOTATTACHED);
4038
4039 dwc3_ep0_reset_state(dwc);
4040
4041 /*
4042 * Request PM idle to address condition where usage count is
4043 * already decremented to zero, but waiting for the disconnect
4044 * interrupt to set dwc->connected to FALSE.
4045 */
4046 pm_request_idle(dwc->dev);
4047}
4048
4049static void dwc3_gadget_reset_interrupt(struct dwc3 *dwc)
4050{
4051 u32 reg;
4052
4053 dwc->suspended = false;
4054
4055 /*
4056 * Ideally, dwc3_reset_gadget() would trigger the function
4057 * drivers to stop any active transfers through ep disable.
4058 * However, for functions which defer ep disable, such as mass
4059 * storage, we will need to rely on the call to stop active
4060 * transfers here, and avoid allowing of request queuing.
4061 */
4062 dwc->connected = false;
4063
4064 /*
4065 * WORKAROUND: DWC3 revisions <1.88a have an issue which
4066 * would cause a missing Disconnect Event if there's a
4067 * pending Setup Packet in the FIFO.
4068 *
4069 * There's no suggested workaround on the official Bug
4070 * report, which states that "unless the driver/application
4071 * is doing any special handling of a disconnect event,
4072 * there is no functional issue".
4073 *
4074 * Unfortunately, it turns out that we _do_ some special
4075 * handling of a disconnect event, namely complete all
4076 * pending transfers, notify gadget driver of the
4077 * disconnection, and so on.
4078 *
4079 * Our suggested workaround is to follow the Disconnect
4080 * Event steps here, instead, based on a setup_packet_pending
4081 * flag. Such flag gets set whenever we have a SETUP_PENDING
4082 * status for EP0 TRBs and gets cleared on XferComplete for the
4083 * same endpoint.
4084 *
4085 * Refers to:
4086 *
4087 * STAR#9000466709: RTL: Device : Disconnect event not
4088 * generated if setup packet pending in FIFO
4089 */
4090 if (DWC3_VER_IS_PRIOR(DWC3, 188A)) {
4091 if (dwc->setup_packet_pending)
4092 dwc3_gadget_disconnect_interrupt(dwc);
4093 }
4094
4095 dwc3_reset_gadget(dwc);
4096
4097 /*
4098 * From SNPS databook section 8.1.2, the EP0 should be in setup
4099 * phase. So ensure that EP0 is in setup phase by issuing a stall
4100 * and restart if EP0 is not in setup phase.
4101 */
4102 dwc3_ep0_reset_state(dwc);
4103
4104 /*
4105 * In the Synopsis DesignWare Cores USB3 Databook Rev. 3.30a
4106 * Section 4.1.2 Table 4-2, it states that during a USB reset, the SW
4107 * needs to ensure that it sends "a DEPENDXFER command for any active
4108 * transfers."
4109 */
4110 dwc3_stop_active_transfers(dwc);
4111 dwc->connected = true;
4112
4113 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
4114 reg &= ~DWC3_DCTL_TSTCTRL_MASK;
4115 dwc3_gadget_dctl_write_safe(dwc, reg);
4116 dwc->test_mode = false;
4117 dwc->gadget->wakeup_armed = false;
4118 dwc3_gadget_enable_linksts_evts(dwc, false);
4119 dwc3_clear_stall_all_ep(dwc);
4120
4121 /* Reset device address to zero */
4122 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
4123 reg &= ~(DWC3_DCFG_DEVADDR_MASK);
4124 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
4125}
4126
4127static void dwc3_gadget_conndone_interrupt(struct dwc3 *dwc)
4128{
4129 struct dwc3_ep *dep;
4130 int ret;
4131 u32 reg;
4132 u8 lanes = 1;
4133 u8 speed;
4134
4135 if (!dwc->softconnect)
4136 return;
4137
4138 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
4139 speed = reg & DWC3_DSTS_CONNECTSPD;
4140 dwc->speed = speed;
4141
4142 if (DWC3_IP_IS(DWC32))
4143 lanes = DWC3_DSTS_CONNLANES(reg) + 1;
4144
4145 dwc->gadget->ssp_rate = USB_SSP_GEN_UNKNOWN;
4146
4147 /*
4148 * RAMClkSel is reset to 0 after USB reset, so it must be reprogrammed
4149 * each time on Connect Done.
4150 *
4151 * Currently we always use the reset value. If any platform
4152 * wants to set this to a different value, we need to add a
4153 * setting and update GCTL.RAMCLKSEL here.
4154 */
4155
4156 switch (speed) {
4157 case DWC3_DSTS_SUPERSPEED_PLUS:
4158 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
4159 dwc->gadget->ep0->maxpacket = 512;
4160 dwc->gadget->speed = USB_SPEED_SUPER_PLUS;
4161
4162 if (lanes > 1)
4163 dwc->gadget->ssp_rate = USB_SSP_GEN_2x2;
4164 else
4165 dwc->gadget->ssp_rate = USB_SSP_GEN_2x1;
4166 break;
4167 case DWC3_DSTS_SUPERSPEED:
4168 /*
4169 * WORKAROUND: DWC3 revisions <1.90a have an issue which
4170 * would cause a missing USB3 Reset event.
4171 *
4172 * In such situations, we should force a USB3 Reset
4173 * event by calling our dwc3_gadget_reset_interrupt()
4174 * routine.
4175 *
4176 * Refers to:
4177 *
4178 * STAR#9000483510: RTL: SS : USB3 reset event may
4179 * not be generated always when the link enters poll
4180 */
4181 if (DWC3_VER_IS_PRIOR(DWC3, 190A))
4182 dwc3_gadget_reset_interrupt(dwc);
4183
4184 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
4185 dwc->gadget->ep0->maxpacket = 512;
4186 dwc->gadget->speed = USB_SPEED_SUPER;
4187
4188 if (lanes > 1) {
4189 dwc->gadget->speed = USB_SPEED_SUPER_PLUS;
4190 dwc->gadget->ssp_rate = USB_SSP_GEN_1x2;
4191 }
4192 break;
4193 case DWC3_DSTS_HIGHSPEED:
4194 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
4195 dwc->gadget->ep0->maxpacket = 64;
4196 dwc->gadget->speed = USB_SPEED_HIGH;
4197 break;
4198 case DWC3_DSTS_FULLSPEED:
4199 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
4200 dwc->gadget->ep0->maxpacket = 64;
4201 dwc->gadget->speed = USB_SPEED_FULL;
4202 break;
4203 }
4204
4205 dwc->eps[1]->endpoint.maxpacket = dwc->gadget->ep0->maxpacket;
4206
4207 /* Enable USB2 LPM Capability */
4208
4209 if (!DWC3_VER_IS_WITHIN(DWC3, ANY, 194A) &&
4210 !dwc->usb2_gadget_lpm_disable &&
4211 (speed != DWC3_DSTS_SUPERSPEED) &&
4212 (speed != DWC3_DSTS_SUPERSPEED_PLUS)) {
4213 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
4214 reg |= DWC3_DCFG_LPM_CAP;
4215 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
4216
4217 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
4218 reg &= ~(DWC3_DCTL_HIRD_THRES_MASK | DWC3_DCTL_L1_HIBER_EN);
4219
4220 reg |= DWC3_DCTL_HIRD_THRES(dwc->hird_threshold |
4221 (dwc->is_utmi_l1_suspend << 4));
4222
4223 /*
4224 * When dwc3 revisions >= 2.40a, LPM Erratum is enabled and
4225 * DCFG.LPMCap is set, core responses with an ACK and the
4226 * BESL value in the LPM token is less than or equal to LPM
4227 * NYET threshold.
4228 */
4229 WARN_ONCE(DWC3_VER_IS_PRIOR(DWC3, 240A) && dwc->has_lpm_erratum,
4230 "LPM Erratum not available on dwc3 revisions < 2.40a\n");
4231
4232 if (dwc->has_lpm_erratum && !DWC3_VER_IS_PRIOR(DWC3, 240A)) {
4233 reg &= ~DWC3_DCTL_NYET_THRES_MASK;
4234 reg |= DWC3_DCTL_NYET_THRES(dwc->lpm_nyet_threshold);
4235 }
4236
4237 dwc3_gadget_dctl_write_safe(dwc, reg);
4238 } else {
4239 if (dwc->usb2_gadget_lpm_disable) {
4240 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
4241 reg &= ~DWC3_DCFG_LPM_CAP;
4242 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
4243 }
4244
4245 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
4246 reg &= ~DWC3_DCTL_HIRD_THRES_MASK;
4247 dwc3_gadget_dctl_write_safe(dwc, reg);
4248 }
4249
4250 dep = dwc->eps[0];
4251 ret = __dwc3_gadget_ep_enable(dep, DWC3_DEPCFG_ACTION_MODIFY);
4252 if (ret) {
4253 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
4254 return;
4255 }
4256
4257 dep = dwc->eps[1];
4258 ret = __dwc3_gadget_ep_enable(dep, DWC3_DEPCFG_ACTION_MODIFY);
4259 if (ret) {
4260 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
4261 return;
4262 }
4263
4264 /*
4265 * Configure PHY via GUSB3PIPECTLn if required.
4266 *
4267 * Update GTXFIFOSIZn
4268 *
4269 * In both cases reset values should be sufficient.
4270 */
4271}
4272
4273static void dwc3_gadget_wakeup_interrupt(struct dwc3 *dwc, unsigned int evtinfo)
4274{
4275 dwc->suspended = false;
4276
4277 /*
4278 * TODO take core out of low power mode when that's
4279 * implemented.
4280 */
4281
4282 if (dwc->async_callbacks && dwc->gadget_driver->resume) {
4283 spin_unlock(&dwc->lock);
4284 dwc->gadget_driver->resume(dwc->gadget);
4285 spin_lock(&dwc->lock);
4286 }
4287
4288 dwc->link_state = evtinfo & DWC3_LINK_STATE_MASK;
4289}
4290
4291static void dwc3_gadget_linksts_change_interrupt(struct dwc3 *dwc,
4292 unsigned int evtinfo)
4293{
4294 enum dwc3_link_state next = evtinfo & DWC3_LINK_STATE_MASK;
4295 unsigned int pwropt;
4296
4297 /*
4298 * WORKAROUND: DWC3 < 2.50a have an issue when configured without
4299 * Hibernation mode enabled which would show up when device detects
4300 * host-initiated U3 exit.
4301 *
4302 * In that case, device will generate a Link State Change Interrupt
4303 * from U3 to RESUME which is only necessary if Hibernation is
4304 * configured in.
4305 *
4306 * There are no functional changes due to such spurious event and we
4307 * just need to ignore it.
4308 *
4309 * Refers to:
4310 *
4311 * STAR#9000570034 RTL: SS Resume event generated in non-Hibernation
4312 * operational mode
4313 */
4314 pwropt = DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1);
4315 if (DWC3_VER_IS_PRIOR(DWC3, 250A) &&
4316 (pwropt != DWC3_GHWPARAMS1_EN_PWROPT_HIB)) {
4317 if ((dwc->link_state == DWC3_LINK_STATE_U3) &&
4318 (next == DWC3_LINK_STATE_RESUME)) {
4319 return;
4320 }
4321 }
4322
4323 /*
4324 * WORKAROUND: DWC3 Revisions <1.83a have an issue which, depending
4325 * on the link partner, the USB session might do multiple entry/exit
4326 * of low power states before a transfer takes place.
4327 *
4328 * Due to this problem, we might experience lower throughput. The
4329 * suggested workaround is to disable DCTL[12:9] bits if we're
4330 * transitioning from U1/U2 to U0 and enable those bits again
4331 * after a transfer completes and there are no pending transfers
4332 * on any of the enabled endpoints.
4333 *
4334 * This is the first half of that workaround.
4335 *
4336 * Refers to:
4337 *
4338 * STAR#9000446952: RTL: Device SS : if U1/U2 ->U0 takes >128us
4339 * core send LGO_Ux entering U0
4340 */
4341 if (DWC3_VER_IS_PRIOR(DWC3, 183A)) {
4342 if (next == DWC3_LINK_STATE_U0) {
4343 u32 u1u2;
4344 u32 reg;
4345
4346 switch (dwc->link_state) {
4347 case DWC3_LINK_STATE_U1:
4348 case DWC3_LINK_STATE_U2:
4349 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
4350 u1u2 = reg & (DWC3_DCTL_INITU2ENA
4351 | DWC3_DCTL_ACCEPTU2ENA
4352 | DWC3_DCTL_INITU1ENA
4353 | DWC3_DCTL_ACCEPTU1ENA);
4354
4355 if (!dwc->u1u2)
4356 dwc->u1u2 = reg & u1u2;
4357
4358 reg &= ~u1u2;
4359
4360 dwc3_gadget_dctl_write_safe(dwc, reg);
4361 break;
4362 default:
4363 /* do nothing */
4364 break;
4365 }
4366 }
4367 }
4368
4369 switch (next) {
4370 case DWC3_LINK_STATE_U0:
4371 if (dwc->gadget->wakeup_armed) {
4372 dwc3_gadget_enable_linksts_evts(dwc, false);
4373 dwc3_resume_gadget(dwc);
4374 dwc->suspended = false;
4375 }
4376 break;
4377 case DWC3_LINK_STATE_U1:
4378 if (dwc->speed == USB_SPEED_SUPER)
4379 dwc3_suspend_gadget(dwc);
4380 break;
4381 case DWC3_LINK_STATE_U2:
4382 case DWC3_LINK_STATE_U3:
4383 dwc3_suspend_gadget(dwc);
4384 break;
4385 case DWC3_LINK_STATE_RESUME:
4386 dwc3_resume_gadget(dwc);
4387 break;
4388 default:
4389 /* do nothing */
4390 break;
4391 }
4392
4393 dwc->link_state = next;
4394}
4395
4396static void dwc3_gadget_suspend_interrupt(struct dwc3 *dwc,
4397 unsigned int evtinfo)
4398{
4399 enum dwc3_link_state next = evtinfo & DWC3_LINK_STATE_MASK;
4400
4401 if (!dwc->suspended && next == DWC3_LINK_STATE_U3) {
4402 dwc->suspended = true;
4403 dwc3_suspend_gadget(dwc);
4404 }
4405
4406 dwc->link_state = next;
4407}
4408
4409static void dwc3_gadget_interrupt(struct dwc3 *dwc,
4410 const struct dwc3_event_devt *event)
4411{
4412 switch (event->type) {
4413 case DWC3_DEVICE_EVENT_DISCONNECT:
4414 dwc3_gadget_disconnect_interrupt(dwc);
4415 break;
4416 case DWC3_DEVICE_EVENT_RESET:
4417 dwc3_gadget_reset_interrupt(dwc);
4418 break;
4419 case DWC3_DEVICE_EVENT_CONNECT_DONE:
4420 dwc3_gadget_conndone_interrupt(dwc);
4421 break;
4422 case DWC3_DEVICE_EVENT_WAKEUP:
4423 dwc3_gadget_wakeup_interrupt(dwc, event->event_info);
4424 break;
4425 case DWC3_DEVICE_EVENT_HIBER_REQ:
4426 dev_WARN_ONCE(dwc->dev, true, "unexpected hibernation event\n");
4427 break;
4428 case DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE:
4429 dwc3_gadget_linksts_change_interrupt(dwc, event->event_info);
4430 break;
4431 case DWC3_DEVICE_EVENT_SUSPEND:
4432 /* It changed to be suspend event for version 2.30a and above */
4433 if (!DWC3_VER_IS_PRIOR(DWC3, 230A))
4434 dwc3_gadget_suspend_interrupt(dwc, event->event_info);
4435 break;
4436 case DWC3_DEVICE_EVENT_SOF:
4437 case DWC3_DEVICE_EVENT_ERRATIC_ERROR:
4438 case DWC3_DEVICE_EVENT_CMD_CMPL:
4439 case DWC3_DEVICE_EVENT_OVERFLOW:
4440 break;
4441 default:
4442 dev_WARN(dwc->dev, "UNKNOWN IRQ %d\n", event->type);
4443 }
4444}
4445
4446static void dwc3_process_event_entry(struct dwc3 *dwc,
4447 const union dwc3_event *event)
4448{
4449 trace_dwc3_event(event->raw, dwc);
4450
4451 if (!event->type.is_devspec)
4452 dwc3_endpoint_interrupt(dwc, &event->depevt);
4453 else if (event->type.type == DWC3_EVENT_TYPE_DEV)
4454 dwc3_gadget_interrupt(dwc, &event->devt);
4455 else
4456 dev_err(dwc->dev, "UNKNOWN IRQ type %d\n", event->raw);
4457}
4458
4459static irqreturn_t dwc3_process_event_buf(struct dwc3_event_buffer *evt)
4460{
4461 struct dwc3 *dwc = evt->dwc;
4462 irqreturn_t ret = IRQ_NONE;
4463 int left;
4464
4465 left = evt->count;
4466
4467 if (!(evt->flags & DWC3_EVENT_PENDING))
4468 return IRQ_NONE;
4469
4470 while (left > 0) {
4471 union dwc3_event event;
4472
4473 event.raw = *(u32 *) (evt->cache + evt->lpos);
4474
4475 dwc3_process_event_entry(dwc, &event);
4476
4477 /*
4478 * FIXME we wrap around correctly to the next entry as
4479 * almost all entries are 4 bytes in size. There is one
4480 * entry which has 12 bytes which is a regular entry
4481 * followed by 8 bytes data. ATM I don't know how
4482 * things are organized if we get next to the a
4483 * boundary so I worry about that once we try to handle
4484 * that.
4485 */
4486 evt->lpos = (evt->lpos + 4) % evt->length;
4487 left -= 4;
4488 }
4489
4490 evt->count = 0;
4491 ret = IRQ_HANDLED;
4492
4493 /* Unmask interrupt */
4494 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0),
4495 DWC3_GEVNTSIZ_SIZE(evt->length));
4496
4497 evt->flags &= ~DWC3_EVENT_PENDING;
4498 /*
4499 * Add an explicit write memory barrier to make sure that the update of
4500 * clearing DWC3_EVENT_PENDING is observed in dwc3_check_event_buf()
4501 */
4502 wmb();
4503
4504 if (dwc->imod_interval) {
4505 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), DWC3_GEVNTCOUNT_EHB);
4506 dwc3_writel(dwc->regs, DWC3_DEV_IMOD(0), dwc->imod_interval);
4507 }
4508
4509 return ret;
4510}
4511
4512static irqreturn_t dwc3_thread_interrupt(int irq, void *_evt)
4513{
4514 struct dwc3_event_buffer *evt = _evt;
4515 struct dwc3 *dwc = evt->dwc;
4516 unsigned long flags;
4517 irqreturn_t ret = IRQ_NONE;
4518
4519 local_bh_disable();
4520 spin_lock_irqsave(&dwc->lock, flags);
4521 ret = dwc3_process_event_buf(evt);
4522 spin_unlock_irqrestore(&dwc->lock, flags);
4523 local_bh_enable();
4524
4525 return ret;
4526}
4527
4528static irqreturn_t dwc3_check_event_buf(struct dwc3_event_buffer *evt)
4529{
4530 struct dwc3 *dwc = evt->dwc;
4531 u32 amount;
4532 u32 count;
4533
4534 if (pm_runtime_suspended(dwc->dev)) {
4535 dwc->pending_events = true;
4536 /*
4537 * Trigger runtime resume. The get() function will be balanced
4538 * after processing the pending events in dwc3_process_pending
4539 * events().
4540 */
4541 pm_runtime_get(dwc->dev);
4542 disable_irq_nosync(dwc->irq_gadget);
4543 return IRQ_HANDLED;
4544 }
4545
4546 /*
4547 * With PCIe legacy interrupt, test shows that top-half irq handler can
4548 * be called again after HW interrupt deassertion. Check if bottom-half
4549 * irq event handler completes before caching new event to prevent
4550 * losing events.
4551 */
4552 if (evt->flags & DWC3_EVENT_PENDING)
4553 return IRQ_HANDLED;
4554
4555 count = dwc3_readl(dwc->regs, DWC3_GEVNTCOUNT(0));
4556 count &= DWC3_GEVNTCOUNT_MASK;
4557 if (!count)
4558 return IRQ_NONE;
4559
4560 evt->count = count;
4561 evt->flags |= DWC3_EVENT_PENDING;
4562
4563 /* Mask interrupt */
4564 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0),
4565 DWC3_GEVNTSIZ_INTMASK | DWC3_GEVNTSIZ_SIZE(evt->length));
4566
4567 amount = min(count, evt->length - evt->lpos);
4568 memcpy(evt->cache + evt->lpos, evt->buf + evt->lpos, amount);
4569
4570 if (amount < count)
4571 memcpy(evt->cache, evt->buf, count - amount);
4572
4573 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), count);
4574
4575 return IRQ_WAKE_THREAD;
4576}
4577
4578static irqreturn_t dwc3_interrupt(int irq, void *_evt)
4579{
4580 struct dwc3_event_buffer *evt = _evt;
4581
4582 return dwc3_check_event_buf(evt);
4583}
4584
4585static int dwc3_gadget_get_irq(struct dwc3 *dwc)
4586{
4587 struct platform_device *dwc3_pdev = to_platform_device(dwc->dev);
4588 int irq;
4589
4590 irq = platform_get_irq_byname_optional(dwc3_pdev, "peripheral");
4591 if (irq > 0)
4592 goto out;
4593
4594 if (irq == -EPROBE_DEFER)
4595 goto out;
4596
4597 irq = platform_get_irq_byname_optional(dwc3_pdev, "dwc_usb3");
4598 if (irq > 0)
4599 goto out;
4600
4601 if (irq == -EPROBE_DEFER)
4602 goto out;
4603
4604 irq = platform_get_irq(dwc3_pdev, 0);
4605
4606out:
4607 return irq;
4608}
4609
4610static void dwc_gadget_release(struct device *dev)
4611{
4612 struct usb_gadget *gadget = container_of(dev, struct usb_gadget, dev);
4613
4614 kfree(gadget);
4615}
4616
4617/**
4618 * dwc3_gadget_init - initializes gadget related registers
4619 * @dwc: pointer to our controller context structure
4620 *
4621 * Returns 0 on success otherwise negative errno.
4622 */
4623int dwc3_gadget_init(struct dwc3 *dwc)
4624{
4625 int ret;
4626 int irq;
4627 struct device *dev;
4628
4629 irq = dwc3_gadget_get_irq(dwc);
4630 if (irq < 0) {
4631 ret = irq;
4632 goto err0;
4633 }
4634
4635 dwc->irq_gadget = irq;
4636
4637 dwc->ep0_trb = dma_alloc_coherent(dwc->sysdev,
4638 sizeof(*dwc->ep0_trb) * 2,
4639 &dwc->ep0_trb_addr, GFP_KERNEL);
4640 if (!dwc->ep0_trb) {
4641 dev_err(dwc->dev, "failed to allocate ep0 trb\n");
4642 ret = -ENOMEM;
4643 goto err0;
4644 }
4645
4646 dwc->setup_buf = kzalloc(DWC3_EP0_SETUP_SIZE, GFP_KERNEL);
4647 if (!dwc->setup_buf) {
4648 ret = -ENOMEM;
4649 goto err1;
4650 }
4651
4652 dwc->bounce = dma_alloc_coherent(dwc->sysdev, DWC3_BOUNCE_SIZE,
4653 &dwc->bounce_addr, GFP_KERNEL);
4654 if (!dwc->bounce) {
4655 ret = -ENOMEM;
4656 goto err2;
4657 }
4658
4659 init_completion(&dwc->ep0_in_setup);
4660 dwc->gadget = kzalloc(sizeof(struct usb_gadget), GFP_KERNEL);
4661 if (!dwc->gadget) {
4662 ret = -ENOMEM;
4663 goto err3;
4664 }
4665
4666
4667 usb_initialize_gadget(dwc->dev, dwc->gadget, dwc_gadget_release);
4668 dev = &dwc->gadget->dev;
4669 dev->platform_data = dwc;
4670 dwc->gadget->ops = &dwc3_gadget_ops;
4671 dwc->gadget->speed = USB_SPEED_UNKNOWN;
4672 dwc->gadget->ssp_rate = USB_SSP_GEN_UNKNOWN;
4673 dwc->gadget->sg_supported = true;
4674 dwc->gadget->name = "dwc3-gadget";
4675 dwc->gadget->lpm_capable = !dwc->usb2_gadget_lpm_disable;
4676 dwc->gadget->wakeup_capable = true;
4677
4678 /*
4679 * FIXME We might be setting max_speed to <SUPER, however versions
4680 * <2.20a of dwc3 have an issue with metastability (documented
4681 * elsewhere in this driver) which tells us we can't set max speed to
4682 * anything lower than SUPER.
4683 *
4684 * Because gadget.max_speed is only used by composite.c and function
4685 * drivers (i.e. it won't go into dwc3's registers) we are allowing this
4686 * to happen so we avoid sending SuperSpeed Capability descriptor
4687 * together with our BOS descriptor as that could confuse host into
4688 * thinking we can handle super speed.
4689 *
4690 * Note that, in fact, we won't even support GetBOS requests when speed
4691 * is less than super speed because we don't have means, yet, to tell
4692 * composite.c that we are USB 2.0 + LPM ECN.
4693 */
4694 if (DWC3_VER_IS_PRIOR(DWC3, 220A) &&
4695 !dwc->dis_metastability_quirk)
4696 dev_info(dwc->dev, "changing max_speed on rev %08x\n",
4697 dwc->revision);
4698
4699 dwc->gadget->max_speed = dwc->maximum_speed;
4700 dwc->gadget->max_ssp_rate = dwc->max_ssp_rate;
4701
4702 /*
4703 * REVISIT: Here we should clear all pending IRQs to be
4704 * sure we're starting from a well known location.
4705 */
4706
4707 ret = dwc3_gadget_init_endpoints(dwc, dwc->num_eps);
4708 if (ret)
4709 goto err4;
4710
4711 ret = usb_add_gadget(dwc->gadget);
4712 if (ret) {
4713 dev_err(dwc->dev, "failed to add gadget\n");
4714 goto err5;
4715 }
4716
4717 if (DWC3_IP_IS(DWC32) && dwc->maximum_speed == USB_SPEED_SUPER_PLUS)
4718 dwc3_gadget_set_ssp_rate(dwc->gadget, dwc->max_ssp_rate);
4719 else
4720 dwc3_gadget_set_speed(dwc->gadget, dwc->maximum_speed);
4721
4722 /* No system wakeup if no gadget driver bound */
4723 if (dwc->sys_wakeup)
4724 device_wakeup_disable(dwc->sysdev);
4725
4726 return 0;
4727
4728err5:
4729 dwc3_gadget_free_endpoints(dwc);
4730err4:
4731 usb_put_gadget(dwc->gadget);
4732 dwc->gadget = NULL;
4733err3:
4734 dma_free_coherent(dwc->sysdev, DWC3_BOUNCE_SIZE, dwc->bounce,
4735 dwc->bounce_addr);
4736
4737err2:
4738 kfree(dwc->setup_buf);
4739
4740err1:
4741 dma_free_coherent(dwc->sysdev, sizeof(*dwc->ep0_trb) * 2,
4742 dwc->ep0_trb, dwc->ep0_trb_addr);
4743
4744err0:
4745 return ret;
4746}
4747
4748/* -------------------------------------------------------------------------- */
4749
4750void dwc3_gadget_exit(struct dwc3 *dwc)
4751{
4752 if (!dwc->gadget)
4753 return;
4754
4755 dwc3_enable_susphy(dwc, false);
4756 usb_del_gadget(dwc->gadget);
4757 dwc3_gadget_free_endpoints(dwc);
4758 usb_put_gadget(dwc->gadget);
4759 dma_free_coherent(dwc->sysdev, DWC3_BOUNCE_SIZE, dwc->bounce,
4760 dwc->bounce_addr);
4761 kfree(dwc->setup_buf);
4762 dma_free_coherent(dwc->sysdev, sizeof(*dwc->ep0_trb) * 2,
4763 dwc->ep0_trb, dwc->ep0_trb_addr);
4764}
4765
4766int dwc3_gadget_suspend(struct dwc3 *dwc)
4767{
4768 unsigned long flags;
4769 int ret;
4770
4771 ret = dwc3_gadget_soft_disconnect(dwc);
4772 if (ret)
4773 goto err;
4774
4775 spin_lock_irqsave(&dwc->lock, flags);
4776 if (dwc->gadget_driver)
4777 dwc3_disconnect_gadget(dwc);
4778 spin_unlock_irqrestore(&dwc->lock, flags);
4779
4780 return 0;
4781
4782err:
4783 /*
4784 * Attempt to reset the controller's state. Likely no
4785 * communication can be established until the host
4786 * performs a port reset.
4787 */
4788 if (dwc->softconnect)
4789 dwc3_gadget_soft_connect(dwc);
4790
4791 return ret;
4792}
4793
4794int dwc3_gadget_resume(struct dwc3 *dwc)
4795{
4796 if (!dwc->gadget_driver || !dwc->softconnect)
4797 return 0;
4798
4799 return dwc3_gadget_soft_connect(dwc);
4800}
1/**
2 * gadget.c - DesignWare USB3 DRD Controller Gadget Framework Link
3 *
4 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
5 *
6 * Authors: Felipe Balbi <balbi@ti.com>,
7 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
8 *
9 * This program is free software: you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 of
11 * the License as published by the Free Software Foundation.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 */
18
19#include <linux/kernel.h>
20#include <linux/delay.h>
21#include <linux/slab.h>
22#include <linux/spinlock.h>
23#include <linux/platform_device.h>
24#include <linux/pm_runtime.h>
25#include <linux/interrupt.h>
26#include <linux/io.h>
27#include <linux/list.h>
28#include <linux/dma-mapping.h>
29
30#include <linux/usb/ch9.h>
31#include <linux/usb/gadget.h>
32
33#include "core.h"
34#include "gadget.h"
35#include "io.h"
36
37/**
38 * dwc3_gadget_set_test_mode - Enables USB2 Test Modes
39 * @dwc: pointer to our context structure
40 * @mode: the mode to set (J, K SE0 NAK, Force Enable)
41 *
42 * Caller should take care of locking. This function will
43 * return 0 on success or -EINVAL if wrong Test Selector
44 * is passed
45 */
46int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode)
47{
48 u32 reg;
49
50 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
51 reg &= ~DWC3_DCTL_TSTCTRL_MASK;
52
53 switch (mode) {
54 case TEST_J:
55 case TEST_K:
56 case TEST_SE0_NAK:
57 case TEST_PACKET:
58 case TEST_FORCE_EN:
59 reg |= mode << 1;
60 break;
61 default:
62 return -EINVAL;
63 }
64
65 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
66
67 return 0;
68}
69
70/**
71 * dwc3_gadget_get_link_state - Gets current state of USB Link
72 * @dwc: pointer to our context structure
73 *
74 * Caller should take care of locking. This function will
75 * return the link state on success (>= 0) or -ETIMEDOUT.
76 */
77int dwc3_gadget_get_link_state(struct dwc3 *dwc)
78{
79 u32 reg;
80
81 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
82
83 return DWC3_DSTS_USBLNKST(reg);
84}
85
86/**
87 * dwc3_gadget_set_link_state - Sets USB Link to a particular State
88 * @dwc: pointer to our context structure
89 * @state: the state to put link into
90 *
91 * Caller should take care of locking. This function will
92 * return 0 on success or -ETIMEDOUT.
93 */
94int dwc3_gadget_set_link_state(struct dwc3 *dwc, enum dwc3_link_state state)
95{
96 int retries = 10000;
97 u32 reg;
98
99 /*
100 * Wait until device controller is ready. Only applies to 1.94a and
101 * later RTL.
102 */
103 if (dwc->revision >= DWC3_REVISION_194A) {
104 while (--retries) {
105 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
106 if (reg & DWC3_DSTS_DCNRD)
107 udelay(5);
108 else
109 break;
110 }
111
112 if (retries <= 0)
113 return -ETIMEDOUT;
114 }
115
116 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
117 reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;
118
119 /* set requested state */
120 reg |= DWC3_DCTL_ULSTCHNGREQ(state);
121 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
122
123 /*
124 * The following code is racy when called from dwc3_gadget_wakeup,
125 * and is not needed, at least on newer versions
126 */
127 if (dwc->revision >= DWC3_REVISION_194A)
128 return 0;
129
130 /* wait for a change in DSTS */
131 retries = 10000;
132 while (--retries) {
133 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
134
135 if (DWC3_DSTS_USBLNKST(reg) == state)
136 return 0;
137
138 udelay(5);
139 }
140
141 dev_vdbg(dwc->dev, "link state change request timed out\n");
142
143 return -ETIMEDOUT;
144}
145
146/**
147 * dwc3_gadget_resize_tx_fifos - reallocate fifo spaces for current use-case
148 * @dwc: pointer to our context structure
149 *
150 * This function will a best effort FIFO allocation in order
151 * to improve FIFO usage and throughput, while still allowing
152 * us to enable as many endpoints as possible.
153 *
154 * Keep in mind that this operation will be highly dependent
155 * on the configured size for RAM1 - which contains TxFifo -,
156 * the amount of endpoints enabled on coreConsultant tool, and
157 * the width of the Master Bus.
158 *
159 * In the ideal world, we would always be able to satisfy the
160 * following equation:
161 *
162 * ((512 + 2 * MDWIDTH-Bytes) + (Number of IN Endpoints - 1) * \
163 * (3 * (1024 + MDWIDTH-Bytes) + MDWIDTH-Bytes)) / MDWIDTH-Bytes
164 *
165 * Unfortunately, due to many variables that's not always the case.
166 */
167int dwc3_gadget_resize_tx_fifos(struct dwc3 *dwc)
168{
169 int last_fifo_depth = 0;
170 int ram1_depth;
171 int fifo_size;
172 int mdwidth;
173 int num;
174
175 if (!dwc->needs_fifo_resize)
176 return 0;
177
178 ram1_depth = DWC3_RAM1_DEPTH(dwc->hwparams.hwparams7);
179 mdwidth = DWC3_MDWIDTH(dwc->hwparams.hwparams0);
180
181 /* MDWIDTH is represented in bits, we need it in bytes */
182 mdwidth >>= 3;
183
184 /*
185 * FIXME For now we will only allocate 1 wMaxPacketSize space
186 * for each enabled endpoint, later patches will come to
187 * improve this algorithm so that we better use the internal
188 * FIFO space
189 */
190 for (num = 0; num < dwc->num_in_eps; num++) {
191 /* bit0 indicates direction; 1 means IN ep */
192 struct dwc3_ep *dep = dwc->eps[(num << 1) | 1];
193 int mult = 1;
194 int tmp;
195
196 if (!(dep->flags & DWC3_EP_ENABLED))
197 continue;
198
199 if (usb_endpoint_xfer_bulk(dep->endpoint.desc)
200 || usb_endpoint_xfer_isoc(dep->endpoint.desc))
201 mult = 3;
202
203 /*
204 * REVISIT: the following assumes we will always have enough
205 * space available on the FIFO RAM for all possible use cases.
206 * Make sure that's true somehow and change FIFO allocation
207 * accordingly.
208 *
209 * If we have Bulk or Isochronous endpoints, we want
210 * them to be able to be very, very fast. So we're giving
211 * those endpoints a fifo_size which is enough for 3 full
212 * packets
213 */
214 tmp = mult * (dep->endpoint.maxpacket + mdwidth);
215 tmp += mdwidth;
216
217 fifo_size = DIV_ROUND_UP(tmp, mdwidth);
218
219 fifo_size |= (last_fifo_depth << 16);
220
221 dev_vdbg(dwc->dev, "%s: Fifo Addr %04x Size %d\n",
222 dep->name, last_fifo_depth, fifo_size & 0xffff);
223
224 dwc3_writel(dwc->regs, DWC3_GTXFIFOSIZ(num), fifo_size);
225
226 last_fifo_depth += (fifo_size & 0xffff);
227 }
228
229 return 0;
230}
231
232void dwc3_gadget_giveback(struct dwc3_ep *dep, struct dwc3_request *req,
233 int status)
234{
235 struct dwc3 *dwc = dep->dwc;
236 int i;
237
238 if (req->queued) {
239 i = 0;
240 do {
241 dep->busy_slot++;
242 /*
243 * Skip LINK TRB. We can't use req->trb and check for
244 * DWC3_TRBCTL_LINK_TRB because it points the TRB we
245 * just completed (not the LINK TRB).
246 */
247 if (((dep->busy_slot & DWC3_TRB_MASK) ==
248 DWC3_TRB_NUM- 1) &&
249 usb_endpoint_xfer_isoc(dep->endpoint.desc))
250 dep->busy_slot++;
251 } while(++i < req->request.num_mapped_sgs);
252 req->queued = false;
253 }
254 list_del(&req->list);
255 req->trb = NULL;
256
257 if (req->request.status == -EINPROGRESS)
258 req->request.status = status;
259
260 if (dwc->ep0_bounced && dep->number == 0)
261 dwc->ep0_bounced = false;
262 else
263 usb_gadget_unmap_request(&dwc->gadget, &req->request,
264 req->direction);
265
266 dev_dbg(dwc->dev, "request %p from %s completed %d/%d ===> %d\n",
267 req, dep->name, req->request.actual,
268 req->request.length, status);
269
270 spin_unlock(&dwc->lock);
271 req->request.complete(&dep->endpoint, &req->request);
272 spin_lock(&dwc->lock);
273}
274
275static const char *dwc3_gadget_ep_cmd_string(u8 cmd)
276{
277 switch (cmd) {
278 case DWC3_DEPCMD_DEPSTARTCFG:
279 return "Start New Configuration";
280 case DWC3_DEPCMD_ENDTRANSFER:
281 return "End Transfer";
282 case DWC3_DEPCMD_UPDATETRANSFER:
283 return "Update Transfer";
284 case DWC3_DEPCMD_STARTTRANSFER:
285 return "Start Transfer";
286 case DWC3_DEPCMD_CLEARSTALL:
287 return "Clear Stall";
288 case DWC3_DEPCMD_SETSTALL:
289 return "Set Stall";
290 case DWC3_DEPCMD_GETEPSTATE:
291 return "Get Endpoint State";
292 case DWC3_DEPCMD_SETTRANSFRESOURCE:
293 return "Set Endpoint Transfer Resource";
294 case DWC3_DEPCMD_SETEPCONFIG:
295 return "Set Endpoint Configuration";
296 default:
297 return "UNKNOWN command";
298 }
299}
300
301int dwc3_send_gadget_generic_command(struct dwc3 *dwc, int cmd, u32 param)
302{
303 u32 timeout = 500;
304 u32 reg;
305
306 dwc3_writel(dwc->regs, DWC3_DGCMDPAR, param);
307 dwc3_writel(dwc->regs, DWC3_DGCMD, cmd | DWC3_DGCMD_CMDACT);
308
309 do {
310 reg = dwc3_readl(dwc->regs, DWC3_DGCMD);
311 if (!(reg & DWC3_DGCMD_CMDACT)) {
312 dev_vdbg(dwc->dev, "Command Complete --> %d\n",
313 DWC3_DGCMD_STATUS(reg));
314 return 0;
315 }
316
317 /*
318 * We can't sleep here, because it's also called from
319 * interrupt context.
320 */
321 timeout--;
322 if (!timeout)
323 return -ETIMEDOUT;
324 udelay(1);
325 } while (1);
326}
327
328int dwc3_send_gadget_ep_cmd(struct dwc3 *dwc, unsigned ep,
329 unsigned cmd, struct dwc3_gadget_ep_cmd_params *params)
330{
331 struct dwc3_ep *dep = dwc->eps[ep];
332 u32 timeout = 500;
333 u32 reg;
334
335 dev_vdbg(dwc->dev, "%s: cmd '%s' params %08x %08x %08x\n",
336 dep->name,
337 dwc3_gadget_ep_cmd_string(cmd), params->param0,
338 params->param1, params->param2);
339
340 dwc3_writel(dwc->regs, DWC3_DEPCMDPAR0(ep), params->param0);
341 dwc3_writel(dwc->regs, DWC3_DEPCMDPAR1(ep), params->param1);
342 dwc3_writel(dwc->regs, DWC3_DEPCMDPAR2(ep), params->param2);
343
344 dwc3_writel(dwc->regs, DWC3_DEPCMD(ep), cmd | DWC3_DEPCMD_CMDACT);
345 do {
346 reg = dwc3_readl(dwc->regs, DWC3_DEPCMD(ep));
347 if (!(reg & DWC3_DEPCMD_CMDACT)) {
348 dev_vdbg(dwc->dev, "Command Complete --> %d\n",
349 DWC3_DEPCMD_STATUS(reg));
350 return 0;
351 }
352
353 /*
354 * We can't sleep here, because it is also called from
355 * interrupt context.
356 */
357 timeout--;
358 if (!timeout)
359 return -ETIMEDOUT;
360
361 udelay(1);
362 } while (1);
363}
364
365static dma_addr_t dwc3_trb_dma_offset(struct dwc3_ep *dep,
366 struct dwc3_trb *trb)
367{
368 u32 offset = (char *) trb - (char *) dep->trb_pool;
369
370 return dep->trb_pool_dma + offset;
371}
372
373static int dwc3_alloc_trb_pool(struct dwc3_ep *dep)
374{
375 struct dwc3 *dwc = dep->dwc;
376
377 if (dep->trb_pool)
378 return 0;
379
380 if (dep->number == 0 || dep->number == 1)
381 return 0;
382
383 dep->trb_pool = dma_alloc_coherent(dwc->dev,
384 sizeof(struct dwc3_trb) * DWC3_TRB_NUM,
385 &dep->trb_pool_dma, GFP_KERNEL);
386 if (!dep->trb_pool) {
387 dev_err(dep->dwc->dev, "failed to allocate trb pool for %s\n",
388 dep->name);
389 return -ENOMEM;
390 }
391
392 return 0;
393}
394
395static void dwc3_free_trb_pool(struct dwc3_ep *dep)
396{
397 struct dwc3 *dwc = dep->dwc;
398
399 dma_free_coherent(dwc->dev, sizeof(struct dwc3_trb) * DWC3_TRB_NUM,
400 dep->trb_pool, dep->trb_pool_dma);
401
402 dep->trb_pool = NULL;
403 dep->trb_pool_dma = 0;
404}
405
406static int dwc3_gadget_start_config(struct dwc3 *dwc, struct dwc3_ep *dep)
407{
408 struct dwc3_gadget_ep_cmd_params params;
409 u32 cmd;
410
411 memset(¶ms, 0x00, sizeof(params));
412
413 if (dep->number != 1) {
414 cmd = DWC3_DEPCMD_DEPSTARTCFG;
415 /* XferRscIdx == 0 for ep0 and 2 for the remaining */
416 if (dep->number > 1) {
417 if (dwc->start_config_issued)
418 return 0;
419 dwc->start_config_issued = true;
420 cmd |= DWC3_DEPCMD_PARAM(2);
421 }
422
423 return dwc3_send_gadget_ep_cmd(dwc, 0, cmd, ¶ms);
424 }
425
426 return 0;
427}
428
429static int dwc3_gadget_set_ep_config(struct dwc3 *dwc, struct dwc3_ep *dep,
430 const struct usb_endpoint_descriptor *desc,
431 const struct usb_ss_ep_comp_descriptor *comp_desc,
432 bool ignore, bool restore)
433{
434 struct dwc3_gadget_ep_cmd_params params;
435
436 memset(¶ms, 0x00, sizeof(params));
437
438 params.param0 = DWC3_DEPCFG_EP_TYPE(usb_endpoint_type(desc))
439 | DWC3_DEPCFG_MAX_PACKET_SIZE(usb_endpoint_maxp(desc));
440
441 /* Burst size is only needed in SuperSpeed mode */
442 if (dwc->gadget.speed == USB_SPEED_SUPER) {
443 u32 burst = dep->endpoint.maxburst - 1;
444
445 params.param0 |= DWC3_DEPCFG_BURST_SIZE(burst);
446 }
447
448 if (ignore)
449 params.param0 |= DWC3_DEPCFG_IGN_SEQ_NUM;
450
451 if (restore) {
452 params.param0 |= DWC3_DEPCFG_ACTION_RESTORE;
453 params.param2 |= dep->saved_state;
454 }
455
456 params.param1 = DWC3_DEPCFG_XFER_COMPLETE_EN
457 | DWC3_DEPCFG_XFER_NOT_READY_EN;
458
459 if (usb_ss_max_streams(comp_desc) && usb_endpoint_xfer_bulk(desc)) {
460 params.param1 |= DWC3_DEPCFG_STREAM_CAPABLE
461 | DWC3_DEPCFG_STREAM_EVENT_EN;
462 dep->stream_capable = true;
463 }
464
465 if (usb_endpoint_xfer_isoc(desc))
466 params.param1 |= DWC3_DEPCFG_XFER_IN_PROGRESS_EN;
467
468 /*
469 * We are doing 1:1 mapping for endpoints, meaning
470 * Physical Endpoints 2 maps to Logical Endpoint 2 and
471 * so on. We consider the direction bit as part of the physical
472 * endpoint number. So USB endpoint 0x81 is 0x03.
473 */
474 params.param1 |= DWC3_DEPCFG_EP_NUMBER(dep->number);
475
476 /*
477 * We must use the lower 16 TX FIFOs even though
478 * HW might have more
479 */
480 if (dep->direction)
481 params.param0 |= DWC3_DEPCFG_FIFO_NUMBER(dep->number >> 1);
482
483 if (desc->bInterval) {
484 params.param1 |= DWC3_DEPCFG_BINTERVAL_M1(desc->bInterval - 1);
485 dep->interval = 1 << (desc->bInterval - 1);
486 }
487
488 return dwc3_send_gadget_ep_cmd(dwc, dep->number,
489 DWC3_DEPCMD_SETEPCONFIG, ¶ms);
490}
491
492static int dwc3_gadget_set_xfer_resource(struct dwc3 *dwc, struct dwc3_ep *dep)
493{
494 struct dwc3_gadget_ep_cmd_params params;
495
496 memset(¶ms, 0x00, sizeof(params));
497
498 params.param0 = DWC3_DEPXFERCFG_NUM_XFER_RES(1);
499
500 return dwc3_send_gadget_ep_cmd(dwc, dep->number,
501 DWC3_DEPCMD_SETTRANSFRESOURCE, ¶ms);
502}
503
504/**
505 * __dwc3_gadget_ep_enable - Initializes a HW endpoint
506 * @dep: endpoint to be initialized
507 * @desc: USB Endpoint Descriptor
508 *
509 * Caller should take care of locking
510 */
511static int __dwc3_gadget_ep_enable(struct dwc3_ep *dep,
512 const struct usb_endpoint_descriptor *desc,
513 const struct usb_ss_ep_comp_descriptor *comp_desc,
514 bool ignore, bool restore)
515{
516 struct dwc3 *dwc = dep->dwc;
517 u32 reg;
518 int ret = -ENOMEM;
519
520 dev_vdbg(dwc->dev, "Enabling %s\n", dep->name);
521
522 if (!(dep->flags & DWC3_EP_ENABLED)) {
523 ret = dwc3_gadget_start_config(dwc, dep);
524 if (ret)
525 return ret;
526 }
527
528 ret = dwc3_gadget_set_ep_config(dwc, dep, desc, comp_desc, ignore,
529 restore);
530 if (ret)
531 return ret;
532
533 if (!(dep->flags & DWC3_EP_ENABLED)) {
534 struct dwc3_trb *trb_st_hw;
535 struct dwc3_trb *trb_link;
536
537 ret = dwc3_gadget_set_xfer_resource(dwc, dep);
538 if (ret)
539 return ret;
540
541 dep->endpoint.desc = desc;
542 dep->comp_desc = comp_desc;
543 dep->type = usb_endpoint_type(desc);
544 dep->flags |= DWC3_EP_ENABLED;
545
546 reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
547 reg |= DWC3_DALEPENA_EP(dep->number);
548 dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
549
550 if (!usb_endpoint_xfer_isoc(desc))
551 return 0;
552
553 memset(&trb_link, 0, sizeof(trb_link));
554
555 /* Link TRB for ISOC. The HWO bit is never reset */
556 trb_st_hw = &dep->trb_pool[0];
557
558 trb_link = &dep->trb_pool[DWC3_TRB_NUM - 1];
559
560 trb_link->bpl = lower_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw));
561 trb_link->bph = upper_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw));
562 trb_link->ctrl |= DWC3_TRBCTL_LINK_TRB;
563 trb_link->ctrl |= DWC3_TRB_CTRL_HWO;
564 }
565
566 return 0;
567}
568
569static void dwc3_stop_active_transfer(struct dwc3 *dwc, u32 epnum, bool force);
570static void dwc3_remove_requests(struct dwc3 *dwc, struct dwc3_ep *dep)
571{
572 struct dwc3_request *req;
573
574 if (!list_empty(&dep->req_queued)) {
575 dwc3_stop_active_transfer(dwc, dep->number, true);
576
577 /* - giveback all requests to gadget driver */
578 while (!list_empty(&dep->req_queued)) {
579 req = next_request(&dep->req_queued);
580
581 dwc3_gadget_giveback(dep, req, -ESHUTDOWN);
582 }
583 }
584
585 while (!list_empty(&dep->request_list)) {
586 req = next_request(&dep->request_list);
587
588 dwc3_gadget_giveback(dep, req, -ESHUTDOWN);
589 }
590}
591
592/**
593 * __dwc3_gadget_ep_disable - Disables a HW endpoint
594 * @dep: the endpoint to disable
595 *
596 * This function also removes requests which are currently processed ny the
597 * hardware and those which are not yet scheduled.
598 * Caller should take care of locking.
599 */
600static int __dwc3_gadget_ep_disable(struct dwc3_ep *dep)
601{
602 struct dwc3 *dwc = dep->dwc;
603 u32 reg;
604
605 dwc3_remove_requests(dwc, dep);
606
607 reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
608 reg &= ~DWC3_DALEPENA_EP(dep->number);
609 dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
610
611 dep->stream_capable = false;
612 dep->endpoint.desc = NULL;
613 dep->comp_desc = NULL;
614 dep->type = 0;
615 dep->flags = 0;
616
617 return 0;
618}
619
620/* -------------------------------------------------------------------------- */
621
622static int dwc3_gadget_ep0_enable(struct usb_ep *ep,
623 const struct usb_endpoint_descriptor *desc)
624{
625 return -EINVAL;
626}
627
628static int dwc3_gadget_ep0_disable(struct usb_ep *ep)
629{
630 return -EINVAL;
631}
632
633/* -------------------------------------------------------------------------- */
634
635static int dwc3_gadget_ep_enable(struct usb_ep *ep,
636 const struct usb_endpoint_descriptor *desc)
637{
638 struct dwc3_ep *dep;
639 struct dwc3 *dwc;
640 unsigned long flags;
641 int ret;
642
643 if (!ep || !desc || desc->bDescriptorType != USB_DT_ENDPOINT) {
644 pr_debug("dwc3: invalid parameters\n");
645 return -EINVAL;
646 }
647
648 if (!desc->wMaxPacketSize) {
649 pr_debug("dwc3: missing wMaxPacketSize\n");
650 return -EINVAL;
651 }
652
653 dep = to_dwc3_ep(ep);
654 dwc = dep->dwc;
655
656 if (dep->flags & DWC3_EP_ENABLED) {
657 dev_WARN_ONCE(dwc->dev, true, "%s is already enabled\n",
658 dep->name);
659 return 0;
660 }
661
662 switch (usb_endpoint_type(desc)) {
663 case USB_ENDPOINT_XFER_CONTROL:
664 strlcat(dep->name, "-control", sizeof(dep->name));
665 break;
666 case USB_ENDPOINT_XFER_ISOC:
667 strlcat(dep->name, "-isoc", sizeof(dep->name));
668 break;
669 case USB_ENDPOINT_XFER_BULK:
670 strlcat(dep->name, "-bulk", sizeof(dep->name));
671 break;
672 case USB_ENDPOINT_XFER_INT:
673 strlcat(dep->name, "-int", sizeof(dep->name));
674 break;
675 default:
676 dev_err(dwc->dev, "invalid endpoint transfer type\n");
677 }
678
679 spin_lock_irqsave(&dwc->lock, flags);
680 ret = __dwc3_gadget_ep_enable(dep, desc, ep->comp_desc, false, false);
681 spin_unlock_irqrestore(&dwc->lock, flags);
682
683 return ret;
684}
685
686static int dwc3_gadget_ep_disable(struct usb_ep *ep)
687{
688 struct dwc3_ep *dep;
689 struct dwc3 *dwc;
690 unsigned long flags;
691 int ret;
692
693 if (!ep) {
694 pr_debug("dwc3: invalid parameters\n");
695 return -EINVAL;
696 }
697
698 dep = to_dwc3_ep(ep);
699 dwc = dep->dwc;
700
701 if (!(dep->flags & DWC3_EP_ENABLED)) {
702 dev_WARN_ONCE(dwc->dev, true, "%s is already disabled\n",
703 dep->name);
704 return 0;
705 }
706
707 snprintf(dep->name, sizeof(dep->name), "ep%d%s",
708 dep->number >> 1,
709 (dep->number & 1) ? "in" : "out");
710
711 spin_lock_irqsave(&dwc->lock, flags);
712 ret = __dwc3_gadget_ep_disable(dep);
713 spin_unlock_irqrestore(&dwc->lock, flags);
714
715 return ret;
716}
717
718static struct usb_request *dwc3_gadget_ep_alloc_request(struct usb_ep *ep,
719 gfp_t gfp_flags)
720{
721 struct dwc3_request *req;
722 struct dwc3_ep *dep = to_dwc3_ep(ep);
723 struct dwc3 *dwc = dep->dwc;
724
725 req = kzalloc(sizeof(*req), gfp_flags);
726 if (!req) {
727 dev_err(dwc->dev, "not enough memory\n");
728 return NULL;
729 }
730
731 req->epnum = dep->number;
732 req->dep = dep;
733
734 return &req->request;
735}
736
737static void dwc3_gadget_ep_free_request(struct usb_ep *ep,
738 struct usb_request *request)
739{
740 struct dwc3_request *req = to_dwc3_request(request);
741
742 kfree(req);
743}
744
745/**
746 * dwc3_prepare_one_trb - setup one TRB from one request
747 * @dep: endpoint for which this request is prepared
748 * @req: dwc3_request pointer
749 */
750static void dwc3_prepare_one_trb(struct dwc3_ep *dep,
751 struct dwc3_request *req, dma_addr_t dma,
752 unsigned length, unsigned last, unsigned chain, unsigned node)
753{
754 struct dwc3 *dwc = dep->dwc;
755 struct dwc3_trb *trb;
756
757 dev_vdbg(dwc->dev, "%s: req %p dma %08llx length %d%s%s\n",
758 dep->name, req, (unsigned long long) dma,
759 length, last ? " last" : "",
760 chain ? " chain" : "");
761
762 /* Skip the LINK-TRB on ISOC */
763 if (((dep->free_slot & DWC3_TRB_MASK) == DWC3_TRB_NUM - 1) &&
764 usb_endpoint_xfer_isoc(dep->endpoint.desc))
765 dep->free_slot++;
766
767 trb = &dep->trb_pool[dep->free_slot & DWC3_TRB_MASK];
768
769 if (!req->trb) {
770 dwc3_gadget_move_request_queued(req);
771 req->trb = trb;
772 req->trb_dma = dwc3_trb_dma_offset(dep, trb);
773 req->start_slot = dep->free_slot & DWC3_TRB_MASK;
774 }
775
776 dep->free_slot++;
777
778 trb->size = DWC3_TRB_SIZE_LENGTH(length);
779 trb->bpl = lower_32_bits(dma);
780 trb->bph = upper_32_bits(dma);
781
782 switch (usb_endpoint_type(dep->endpoint.desc)) {
783 case USB_ENDPOINT_XFER_CONTROL:
784 trb->ctrl = DWC3_TRBCTL_CONTROL_SETUP;
785 break;
786
787 case USB_ENDPOINT_XFER_ISOC:
788 if (!node)
789 trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS_FIRST;
790 else
791 trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS;
792 break;
793
794 case USB_ENDPOINT_XFER_BULK:
795 case USB_ENDPOINT_XFER_INT:
796 trb->ctrl = DWC3_TRBCTL_NORMAL;
797 break;
798 default:
799 /*
800 * This is only possible with faulty memory because we
801 * checked it already :)
802 */
803 BUG();
804 }
805
806 if (!req->request.no_interrupt && !chain)
807 trb->ctrl |= DWC3_TRB_CTRL_IOC;
808
809 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
810 trb->ctrl |= DWC3_TRB_CTRL_ISP_IMI;
811 trb->ctrl |= DWC3_TRB_CTRL_CSP;
812 } else if (last) {
813 trb->ctrl |= DWC3_TRB_CTRL_LST;
814 }
815
816 if (chain)
817 trb->ctrl |= DWC3_TRB_CTRL_CHN;
818
819 if (usb_endpoint_xfer_bulk(dep->endpoint.desc) && dep->stream_capable)
820 trb->ctrl |= DWC3_TRB_CTRL_SID_SOFN(req->request.stream_id);
821
822 trb->ctrl |= DWC3_TRB_CTRL_HWO;
823}
824
825/*
826 * dwc3_prepare_trbs - setup TRBs from requests
827 * @dep: endpoint for which requests are being prepared
828 * @starting: true if the endpoint is idle and no requests are queued.
829 *
830 * The function goes through the requests list and sets up TRBs for the
831 * transfers. The function returns once there are no more TRBs available or
832 * it runs out of requests.
833 */
834static void dwc3_prepare_trbs(struct dwc3_ep *dep, bool starting)
835{
836 struct dwc3_request *req, *n;
837 u32 trbs_left;
838 u32 max;
839 unsigned int last_one = 0;
840
841 BUILD_BUG_ON_NOT_POWER_OF_2(DWC3_TRB_NUM);
842
843 /* the first request must not be queued */
844 trbs_left = (dep->busy_slot - dep->free_slot) & DWC3_TRB_MASK;
845
846 /* Can't wrap around on a non-isoc EP since there's no link TRB */
847 if (!usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
848 max = DWC3_TRB_NUM - (dep->free_slot & DWC3_TRB_MASK);
849 if (trbs_left > max)
850 trbs_left = max;
851 }
852
853 /*
854 * If busy & slot are equal than it is either full or empty. If we are
855 * starting to process requests then we are empty. Otherwise we are
856 * full and don't do anything
857 */
858 if (!trbs_left) {
859 if (!starting)
860 return;
861 trbs_left = DWC3_TRB_NUM;
862 /*
863 * In case we start from scratch, we queue the ISOC requests
864 * starting from slot 1. This is done because we use ring
865 * buffer and have no LST bit to stop us. Instead, we place
866 * IOC bit every TRB_NUM/4. We try to avoid having an interrupt
867 * after the first request so we start at slot 1 and have
868 * 7 requests proceed before we hit the first IOC.
869 * Other transfer types don't use the ring buffer and are
870 * processed from the first TRB until the last one. Since we
871 * don't wrap around we have to start at the beginning.
872 */
873 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
874 dep->busy_slot = 1;
875 dep->free_slot = 1;
876 } else {
877 dep->busy_slot = 0;
878 dep->free_slot = 0;
879 }
880 }
881
882 /* The last TRB is a link TRB, not used for xfer */
883 if ((trbs_left <= 1) && usb_endpoint_xfer_isoc(dep->endpoint.desc))
884 return;
885
886 list_for_each_entry_safe(req, n, &dep->request_list, list) {
887 unsigned length;
888 dma_addr_t dma;
889 last_one = false;
890
891 if (req->request.num_mapped_sgs > 0) {
892 struct usb_request *request = &req->request;
893 struct scatterlist *sg = request->sg;
894 struct scatterlist *s;
895 int i;
896
897 for_each_sg(sg, s, request->num_mapped_sgs, i) {
898 unsigned chain = true;
899
900 length = sg_dma_len(s);
901 dma = sg_dma_address(s);
902
903 if (i == (request->num_mapped_sgs - 1) ||
904 sg_is_last(s)) {
905 if (list_is_last(&req->list,
906 &dep->request_list))
907 last_one = true;
908 chain = false;
909 }
910
911 trbs_left--;
912 if (!trbs_left)
913 last_one = true;
914
915 if (last_one)
916 chain = false;
917
918 dwc3_prepare_one_trb(dep, req, dma, length,
919 last_one, chain, i);
920
921 if (last_one)
922 break;
923 }
924 } else {
925 dma = req->request.dma;
926 length = req->request.length;
927 trbs_left--;
928
929 if (!trbs_left)
930 last_one = 1;
931
932 /* Is this the last request? */
933 if (list_is_last(&req->list, &dep->request_list))
934 last_one = 1;
935
936 dwc3_prepare_one_trb(dep, req, dma, length,
937 last_one, false, 0);
938
939 if (last_one)
940 break;
941 }
942 }
943}
944
945static int __dwc3_gadget_kick_transfer(struct dwc3_ep *dep, u16 cmd_param,
946 int start_new)
947{
948 struct dwc3_gadget_ep_cmd_params params;
949 struct dwc3_request *req;
950 struct dwc3 *dwc = dep->dwc;
951 int ret;
952 u32 cmd;
953
954 if (start_new && (dep->flags & DWC3_EP_BUSY)) {
955 dev_vdbg(dwc->dev, "%s: endpoint busy\n", dep->name);
956 return -EBUSY;
957 }
958 dep->flags &= ~DWC3_EP_PENDING_REQUEST;
959
960 /*
961 * If we are getting here after a short-out-packet we don't enqueue any
962 * new requests as we try to set the IOC bit only on the last request.
963 */
964 if (start_new) {
965 if (list_empty(&dep->req_queued))
966 dwc3_prepare_trbs(dep, start_new);
967
968 /* req points to the first request which will be sent */
969 req = next_request(&dep->req_queued);
970 } else {
971 dwc3_prepare_trbs(dep, start_new);
972
973 /*
974 * req points to the first request where HWO changed from 0 to 1
975 */
976 req = next_request(&dep->req_queued);
977 }
978 if (!req) {
979 dep->flags |= DWC3_EP_PENDING_REQUEST;
980 return 0;
981 }
982
983 memset(¶ms, 0, sizeof(params));
984
985 if (start_new) {
986 params.param0 = upper_32_bits(req->trb_dma);
987 params.param1 = lower_32_bits(req->trb_dma);
988 cmd = DWC3_DEPCMD_STARTTRANSFER;
989 } else {
990 cmd = DWC3_DEPCMD_UPDATETRANSFER;
991 }
992
993 cmd |= DWC3_DEPCMD_PARAM(cmd_param);
994 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, cmd, ¶ms);
995 if (ret < 0) {
996 dev_dbg(dwc->dev, "failed to send STARTTRANSFER command\n");
997
998 /*
999 * FIXME we need to iterate over the list of requests
1000 * here and stop, unmap, free and del each of the linked
1001 * requests instead of what we do now.
1002 */
1003 usb_gadget_unmap_request(&dwc->gadget, &req->request,
1004 req->direction);
1005 list_del(&req->list);
1006 return ret;
1007 }
1008
1009 dep->flags |= DWC3_EP_BUSY;
1010
1011 if (start_new) {
1012 dep->resource_index = dwc3_gadget_ep_get_transfer_index(dwc,
1013 dep->number);
1014 WARN_ON_ONCE(!dep->resource_index);
1015 }
1016
1017 return 0;
1018}
1019
1020static void __dwc3_gadget_start_isoc(struct dwc3 *dwc,
1021 struct dwc3_ep *dep, u32 cur_uf)
1022{
1023 u32 uf;
1024
1025 if (list_empty(&dep->request_list)) {
1026 dev_vdbg(dwc->dev, "ISOC ep %s run out for requests.\n",
1027 dep->name);
1028 dep->flags |= DWC3_EP_PENDING_REQUEST;
1029 return;
1030 }
1031
1032 /* 4 micro frames in the future */
1033 uf = cur_uf + dep->interval * 4;
1034
1035 __dwc3_gadget_kick_transfer(dep, uf, 1);
1036}
1037
1038static void dwc3_gadget_start_isoc(struct dwc3 *dwc,
1039 struct dwc3_ep *dep, const struct dwc3_event_depevt *event)
1040{
1041 u32 cur_uf, mask;
1042
1043 mask = ~(dep->interval - 1);
1044 cur_uf = event->parameters & mask;
1045
1046 __dwc3_gadget_start_isoc(dwc, dep, cur_uf);
1047}
1048
1049static int __dwc3_gadget_ep_queue(struct dwc3_ep *dep, struct dwc3_request *req)
1050{
1051 struct dwc3 *dwc = dep->dwc;
1052 int ret;
1053
1054 req->request.actual = 0;
1055 req->request.status = -EINPROGRESS;
1056 req->direction = dep->direction;
1057 req->epnum = dep->number;
1058
1059 /*
1060 * We only add to our list of requests now and
1061 * start consuming the list once we get XferNotReady
1062 * IRQ.
1063 *
1064 * That way, we avoid doing anything that we don't need
1065 * to do now and defer it until the point we receive a
1066 * particular token from the Host side.
1067 *
1068 * This will also avoid Host cancelling URBs due to too
1069 * many NAKs.
1070 */
1071 ret = usb_gadget_map_request(&dwc->gadget, &req->request,
1072 dep->direction);
1073 if (ret)
1074 return ret;
1075
1076 list_add_tail(&req->list, &dep->request_list);
1077
1078 /*
1079 * There are a few special cases:
1080 *
1081 * 1. XferNotReady with empty list of requests. We need to kick the
1082 * transfer here in that situation, otherwise we will be NAKing
1083 * forever. If we get XferNotReady before gadget driver has a
1084 * chance to queue a request, we will ACK the IRQ but won't be
1085 * able to receive the data until the next request is queued.
1086 * The following code is handling exactly that.
1087 *
1088 */
1089 if (dep->flags & DWC3_EP_PENDING_REQUEST) {
1090 /*
1091 * If xfernotready is already elapsed and it is a case
1092 * of isoc transfer, then issue END TRANSFER, so that
1093 * you can receive xfernotready again and can have
1094 * notion of current microframe.
1095 */
1096 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1097 if (list_empty(&dep->req_queued)) {
1098 dwc3_stop_active_transfer(dwc, dep->number, true);
1099 dep->flags = DWC3_EP_ENABLED;
1100 }
1101 return 0;
1102 }
1103
1104 ret = __dwc3_gadget_kick_transfer(dep, 0, true);
1105 if (ret && ret != -EBUSY)
1106 dev_dbg(dwc->dev, "%s: failed to kick transfers\n",
1107 dep->name);
1108 return ret;
1109 }
1110
1111 /*
1112 * 2. XferInProgress on Isoc EP with an active transfer. We need to
1113 * kick the transfer here after queuing a request, otherwise the
1114 * core may not see the modified TRB(s).
1115 */
1116 if (usb_endpoint_xfer_isoc(dep->endpoint.desc) &&
1117 (dep->flags & DWC3_EP_BUSY) &&
1118 !(dep->flags & DWC3_EP_MISSED_ISOC)) {
1119 WARN_ON_ONCE(!dep->resource_index);
1120 ret = __dwc3_gadget_kick_transfer(dep, dep->resource_index,
1121 false);
1122 if (ret && ret != -EBUSY)
1123 dev_dbg(dwc->dev, "%s: failed to kick transfers\n",
1124 dep->name);
1125 return ret;
1126 }
1127
1128 /*
1129 * 4. Stream Capable Bulk Endpoints. We need to start the transfer
1130 * right away, otherwise host will not know we have streams to be
1131 * handled.
1132 */
1133 if (dep->stream_capable) {
1134 int ret;
1135
1136 ret = __dwc3_gadget_kick_transfer(dep, 0, true);
1137 if (ret && ret != -EBUSY) {
1138 struct dwc3 *dwc = dep->dwc;
1139
1140 dev_dbg(dwc->dev, "%s: failed to kick transfers\n",
1141 dep->name);
1142 }
1143 }
1144
1145 return 0;
1146}
1147
1148static int dwc3_gadget_ep_queue(struct usb_ep *ep, struct usb_request *request,
1149 gfp_t gfp_flags)
1150{
1151 struct dwc3_request *req = to_dwc3_request(request);
1152 struct dwc3_ep *dep = to_dwc3_ep(ep);
1153 struct dwc3 *dwc = dep->dwc;
1154
1155 unsigned long flags;
1156
1157 int ret;
1158
1159 if (!dep->endpoint.desc) {
1160 dev_dbg(dwc->dev, "trying to queue request %p to disabled %s\n",
1161 request, ep->name);
1162 return -ESHUTDOWN;
1163 }
1164
1165 dev_vdbg(dwc->dev, "queing request %p to %s length %d\n",
1166 request, ep->name, request->length);
1167
1168 spin_lock_irqsave(&dwc->lock, flags);
1169 ret = __dwc3_gadget_ep_queue(dep, req);
1170 spin_unlock_irqrestore(&dwc->lock, flags);
1171
1172 return ret;
1173}
1174
1175static int dwc3_gadget_ep_dequeue(struct usb_ep *ep,
1176 struct usb_request *request)
1177{
1178 struct dwc3_request *req = to_dwc3_request(request);
1179 struct dwc3_request *r = NULL;
1180
1181 struct dwc3_ep *dep = to_dwc3_ep(ep);
1182 struct dwc3 *dwc = dep->dwc;
1183
1184 unsigned long flags;
1185 int ret = 0;
1186
1187 spin_lock_irqsave(&dwc->lock, flags);
1188
1189 list_for_each_entry(r, &dep->request_list, list) {
1190 if (r == req)
1191 break;
1192 }
1193
1194 if (r != req) {
1195 list_for_each_entry(r, &dep->req_queued, list) {
1196 if (r == req)
1197 break;
1198 }
1199 if (r == req) {
1200 /* wait until it is processed */
1201 dwc3_stop_active_transfer(dwc, dep->number, true);
1202 goto out1;
1203 }
1204 dev_err(dwc->dev, "request %p was not queued to %s\n",
1205 request, ep->name);
1206 ret = -EINVAL;
1207 goto out0;
1208 }
1209
1210out1:
1211 /* giveback the request */
1212 dwc3_gadget_giveback(dep, req, -ECONNRESET);
1213
1214out0:
1215 spin_unlock_irqrestore(&dwc->lock, flags);
1216
1217 return ret;
1218}
1219
1220int __dwc3_gadget_ep_set_halt(struct dwc3_ep *dep, int value)
1221{
1222 struct dwc3_gadget_ep_cmd_params params;
1223 struct dwc3 *dwc = dep->dwc;
1224 int ret;
1225
1226 memset(¶ms, 0x00, sizeof(params));
1227
1228 if (value) {
1229 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number,
1230 DWC3_DEPCMD_SETSTALL, ¶ms);
1231 if (ret)
1232 dev_err(dwc->dev, "failed to set STALL on %s\n",
1233 dep->name);
1234 else
1235 dep->flags |= DWC3_EP_STALL;
1236 } else {
1237 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number,
1238 DWC3_DEPCMD_CLEARSTALL, ¶ms);
1239 if (ret)
1240 dev_err(dwc->dev, "failed to clear STALL on %s\n",
1241 dep->name);
1242 else
1243 dep->flags &= ~(DWC3_EP_STALL | DWC3_EP_WEDGE);
1244 }
1245
1246 return ret;
1247}
1248
1249static int dwc3_gadget_ep_set_halt(struct usb_ep *ep, int value)
1250{
1251 struct dwc3_ep *dep = to_dwc3_ep(ep);
1252 struct dwc3 *dwc = dep->dwc;
1253
1254 unsigned long flags;
1255
1256 int ret;
1257
1258 spin_lock_irqsave(&dwc->lock, flags);
1259
1260 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1261 dev_err(dwc->dev, "%s is of Isochronous type\n", dep->name);
1262 ret = -EINVAL;
1263 goto out;
1264 }
1265
1266 ret = __dwc3_gadget_ep_set_halt(dep, value);
1267out:
1268 spin_unlock_irqrestore(&dwc->lock, flags);
1269
1270 return ret;
1271}
1272
1273static int dwc3_gadget_ep_set_wedge(struct usb_ep *ep)
1274{
1275 struct dwc3_ep *dep = to_dwc3_ep(ep);
1276 struct dwc3 *dwc = dep->dwc;
1277 unsigned long flags;
1278
1279 spin_lock_irqsave(&dwc->lock, flags);
1280 dep->flags |= DWC3_EP_WEDGE;
1281 spin_unlock_irqrestore(&dwc->lock, flags);
1282
1283 if (dep->number == 0 || dep->number == 1)
1284 return dwc3_gadget_ep0_set_halt(ep, 1);
1285 else
1286 return dwc3_gadget_ep_set_halt(ep, 1);
1287}
1288
1289/* -------------------------------------------------------------------------- */
1290
1291static struct usb_endpoint_descriptor dwc3_gadget_ep0_desc = {
1292 .bLength = USB_DT_ENDPOINT_SIZE,
1293 .bDescriptorType = USB_DT_ENDPOINT,
1294 .bmAttributes = USB_ENDPOINT_XFER_CONTROL,
1295};
1296
1297static const struct usb_ep_ops dwc3_gadget_ep0_ops = {
1298 .enable = dwc3_gadget_ep0_enable,
1299 .disable = dwc3_gadget_ep0_disable,
1300 .alloc_request = dwc3_gadget_ep_alloc_request,
1301 .free_request = dwc3_gadget_ep_free_request,
1302 .queue = dwc3_gadget_ep0_queue,
1303 .dequeue = dwc3_gadget_ep_dequeue,
1304 .set_halt = dwc3_gadget_ep0_set_halt,
1305 .set_wedge = dwc3_gadget_ep_set_wedge,
1306};
1307
1308static const struct usb_ep_ops dwc3_gadget_ep_ops = {
1309 .enable = dwc3_gadget_ep_enable,
1310 .disable = dwc3_gadget_ep_disable,
1311 .alloc_request = dwc3_gadget_ep_alloc_request,
1312 .free_request = dwc3_gadget_ep_free_request,
1313 .queue = dwc3_gadget_ep_queue,
1314 .dequeue = dwc3_gadget_ep_dequeue,
1315 .set_halt = dwc3_gadget_ep_set_halt,
1316 .set_wedge = dwc3_gadget_ep_set_wedge,
1317};
1318
1319/* -------------------------------------------------------------------------- */
1320
1321static int dwc3_gadget_get_frame(struct usb_gadget *g)
1322{
1323 struct dwc3 *dwc = gadget_to_dwc(g);
1324 u32 reg;
1325
1326 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1327 return DWC3_DSTS_SOFFN(reg);
1328}
1329
1330static int dwc3_gadget_wakeup(struct usb_gadget *g)
1331{
1332 struct dwc3 *dwc = gadget_to_dwc(g);
1333
1334 unsigned long timeout;
1335 unsigned long flags;
1336
1337 u32 reg;
1338
1339 int ret = 0;
1340
1341 u8 link_state;
1342 u8 speed;
1343
1344 spin_lock_irqsave(&dwc->lock, flags);
1345
1346 /*
1347 * According to the Databook Remote wakeup request should
1348 * be issued only when the device is in early suspend state.
1349 *
1350 * We can check that via USB Link State bits in DSTS register.
1351 */
1352 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1353
1354 speed = reg & DWC3_DSTS_CONNECTSPD;
1355 if (speed == DWC3_DSTS_SUPERSPEED) {
1356 dev_dbg(dwc->dev, "no wakeup on SuperSpeed\n");
1357 ret = -EINVAL;
1358 goto out;
1359 }
1360
1361 link_state = DWC3_DSTS_USBLNKST(reg);
1362
1363 switch (link_state) {
1364 case DWC3_LINK_STATE_RX_DET: /* in HS, means Early Suspend */
1365 case DWC3_LINK_STATE_U3: /* in HS, means SUSPEND */
1366 break;
1367 default:
1368 dev_dbg(dwc->dev, "can't wakeup from link state %d\n",
1369 link_state);
1370 ret = -EINVAL;
1371 goto out;
1372 }
1373
1374 ret = dwc3_gadget_set_link_state(dwc, DWC3_LINK_STATE_RECOV);
1375 if (ret < 0) {
1376 dev_err(dwc->dev, "failed to put link in Recovery\n");
1377 goto out;
1378 }
1379
1380 /* Recent versions do this automatically */
1381 if (dwc->revision < DWC3_REVISION_194A) {
1382 /* write zeroes to Link Change Request */
1383 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
1384 reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;
1385 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1386 }
1387
1388 /* poll until Link State changes to ON */
1389 timeout = jiffies + msecs_to_jiffies(100);
1390
1391 while (!time_after(jiffies, timeout)) {
1392 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1393
1394 /* in HS, means ON */
1395 if (DWC3_DSTS_USBLNKST(reg) == DWC3_LINK_STATE_U0)
1396 break;
1397 }
1398
1399 if (DWC3_DSTS_USBLNKST(reg) != DWC3_LINK_STATE_U0) {
1400 dev_err(dwc->dev, "failed to send remote wakeup\n");
1401 ret = -EINVAL;
1402 }
1403
1404out:
1405 spin_unlock_irqrestore(&dwc->lock, flags);
1406
1407 return ret;
1408}
1409
1410static int dwc3_gadget_set_selfpowered(struct usb_gadget *g,
1411 int is_selfpowered)
1412{
1413 struct dwc3 *dwc = gadget_to_dwc(g);
1414 unsigned long flags;
1415
1416 spin_lock_irqsave(&dwc->lock, flags);
1417 dwc->is_selfpowered = !!is_selfpowered;
1418 spin_unlock_irqrestore(&dwc->lock, flags);
1419
1420 return 0;
1421}
1422
1423static int dwc3_gadget_run_stop(struct dwc3 *dwc, int is_on, int suspend)
1424{
1425 u32 reg;
1426 u32 timeout = 500;
1427
1428 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
1429 if (is_on) {
1430 if (dwc->revision <= DWC3_REVISION_187A) {
1431 reg &= ~DWC3_DCTL_TRGTULST_MASK;
1432 reg |= DWC3_DCTL_TRGTULST_RX_DET;
1433 }
1434
1435 if (dwc->revision >= DWC3_REVISION_194A)
1436 reg &= ~DWC3_DCTL_KEEP_CONNECT;
1437 reg |= DWC3_DCTL_RUN_STOP;
1438
1439 if (dwc->has_hibernation)
1440 reg |= DWC3_DCTL_KEEP_CONNECT;
1441
1442 dwc->pullups_connected = true;
1443 } else {
1444 reg &= ~DWC3_DCTL_RUN_STOP;
1445
1446 if (dwc->has_hibernation && !suspend)
1447 reg &= ~DWC3_DCTL_KEEP_CONNECT;
1448
1449 dwc->pullups_connected = false;
1450 }
1451
1452 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1453
1454 do {
1455 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1456 if (is_on) {
1457 if (!(reg & DWC3_DSTS_DEVCTRLHLT))
1458 break;
1459 } else {
1460 if (reg & DWC3_DSTS_DEVCTRLHLT)
1461 break;
1462 }
1463 timeout--;
1464 if (!timeout)
1465 return -ETIMEDOUT;
1466 udelay(1);
1467 } while (1);
1468
1469 dev_vdbg(dwc->dev, "gadget %s data soft-%s\n",
1470 dwc->gadget_driver
1471 ? dwc->gadget_driver->function : "no-function",
1472 is_on ? "connect" : "disconnect");
1473
1474 return 0;
1475}
1476
1477static int dwc3_gadget_pullup(struct usb_gadget *g, int is_on)
1478{
1479 struct dwc3 *dwc = gadget_to_dwc(g);
1480 unsigned long flags;
1481 int ret;
1482
1483 is_on = !!is_on;
1484
1485 spin_lock_irqsave(&dwc->lock, flags);
1486 ret = dwc3_gadget_run_stop(dwc, is_on, false);
1487 spin_unlock_irqrestore(&dwc->lock, flags);
1488
1489 return ret;
1490}
1491
1492static void dwc3_gadget_enable_irq(struct dwc3 *dwc)
1493{
1494 u32 reg;
1495
1496 /* Enable all but Start and End of Frame IRQs */
1497 reg = (DWC3_DEVTEN_VNDRDEVTSTRCVEDEN |
1498 DWC3_DEVTEN_EVNTOVERFLOWEN |
1499 DWC3_DEVTEN_CMDCMPLTEN |
1500 DWC3_DEVTEN_ERRTICERREN |
1501 DWC3_DEVTEN_WKUPEVTEN |
1502 DWC3_DEVTEN_ULSTCNGEN |
1503 DWC3_DEVTEN_CONNECTDONEEN |
1504 DWC3_DEVTEN_USBRSTEN |
1505 DWC3_DEVTEN_DISCONNEVTEN);
1506
1507 dwc3_writel(dwc->regs, DWC3_DEVTEN, reg);
1508}
1509
1510static void dwc3_gadget_disable_irq(struct dwc3 *dwc)
1511{
1512 /* mask all interrupts */
1513 dwc3_writel(dwc->regs, DWC3_DEVTEN, 0x00);
1514}
1515
1516static irqreturn_t dwc3_interrupt(int irq, void *_dwc);
1517static irqreturn_t dwc3_thread_interrupt(int irq, void *_dwc);
1518
1519static int dwc3_gadget_start(struct usb_gadget *g,
1520 struct usb_gadget_driver *driver)
1521{
1522 struct dwc3 *dwc = gadget_to_dwc(g);
1523 struct dwc3_ep *dep;
1524 unsigned long flags;
1525 int ret = 0;
1526 int irq;
1527 u32 reg;
1528
1529 irq = platform_get_irq(to_platform_device(dwc->dev), 0);
1530 ret = request_threaded_irq(irq, dwc3_interrupt, dwc3_thread_interrupt,
1531 IRQF_SHARED, "dwc3", dwc);
1532 if (ret) {
1533 dev_err(dwc->dev, "failed to request irq #%d --> %d\n",
1534 irq, ret);
1535 goto err0;
1536 }
1537
1538 spin_lock_irqsave(&dwc->lock, flags);
1539
1540 if (dwc->gadget_driver) {
1541 dev_err(dwc->dev, "%s is already bound to %s\n",
1542 dwc->gadget.name,
1543 dwc->gadget_driver->driver.name);
1544 ret = -EBUSY;
1545 goto err1;
1546 }
1547
1548 dwc->gadget_driver = driver;
1549
1550 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
1551 reg &= ~(DWC3_DCFG_SPEED_MASK);
1552
1553 /**
1554 * WORKAROUND: DWC3 revision < 2.20a have an issue
1555 * which would cause metastability state on Run/Stop
1556 * bit if we try to force the IP to USB2-only mode.
1557 *
1558 * Because of that, we cannot configure the IP to any
1559 * speed other than the SuperSpeed
1560 *
1561 * Refers to:
1562 *
1563 * STAR#9000525659: Clock Domain Crossing on DCTL in
1564 * USB 2.0 Mode
1565 */
1566 if (dwc->revision < DWC3_REVISION_220A) {
1567 reg |= DWC3_DCFG_SUPERSPEED;
1568 } else {
1569 switch (dwc->maximum_speed) {
1570 case USB_SPEED_LOW:
1571 reg |= DWC3_DSTS_LOWSPEED;
1572 break;
1573 case USB_SPEED_FULL:
1574 reg |= DWC3_DSTS_FULLSPEED1;
1575 break;
1576 case USB_SPEED_HIGH:
1577 reg |= DWC3_DSTS_HIGHSPEED;
1578 break;
1579 case USB_SPEED_SUPER: /* FALLTHROUGH */
1580 case USB_SPEED_UNKNOWN: /* FALTHROUGH */
1581 default:
1582 reg |= DWC3_DSTS_SUPERSPEED;
1583 }
1584 }
1585 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
1586
1587 dwc->start_config_issued = false;
1588
1589 /* Start with SuperSpeed Default */
1590 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
1591
1592 dep = dwc->eps[0];
1593 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, false,
1594 false);
1595 if (ret) {
1596 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
1597 goto err2;
1598 }
1599
1600 dep = dwc->eps[1];
1601 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, false,
1602 false);
1603 if (ret) {
1604 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
1605 goto err3;
1606 }
1607
1608 /* begin to receive SETUP packets */
1609 dwc->ep0state = EP0_SETUP_PHASE;
1610 dwc3_ep0_out_start(dwc);
1611
1612 dwc3_gadget_enable_irq(dwc);
1613
1614 spin_unlock_irqrestore(&dwc->lock, flags);
1615
1616 return 0;
1617
1618err3:
1619 __dwc3_gadget_ep_disable(dwc->eps[0]);
1620
1621err2:
1622 dwc->gadget_driver = NULL;
1623
1624err1:
1625 spin_unlock_irqrestore(&dwc->lock, flags);
1626
1627 free_irq(irq, dwc);
1628
1629err0:
1630 return ret;
1631}
1632
1633static int dwc3_gadget_stop(struct usb_gadget *g,
1634 struct usb_gadget_driver *driver)
1635{
1636 struct dwc3 *dwc = gadget_to_dwc(g);
1637 unsigned long flags;
1638 int irq;
1639
1640 spin_lock_irqsave(&dwc->lock, flags);
1641
1642 dwc3_gadget_disable_irq(dwc);
1643 __dwc3_gadget_ep_disable(dwc->eps[0]);
1644 __dwc3_gadget_ep_disable(dwc->eps[1]);
1645
1646 dwc->gadget_driver = NULL;
1647
1648 spin_unlock_irqrestore(&dwc->lock, flags);
1649
1650 irq = platform_get_irq(to_platform_device(dwc->dev), 0);
1651 free_irq(irq, dwc);
1652
1653 return 0;
1654}
1655
1656static const struct usb_gadget_ops dwc3_gadget_ops = {
1657 .get_frame = dwc3_gadget_get_frame,
1658 .wakeup = dwc3_gadget_wakeup,
1659 .set_selfpowered = dwc3_gadget_set_selfpowered,
1660 .pullup = dwc3_gadget_pullup,
1661 .udc_start = dwc3_gadget_start,
1662 .udc_stop = dwc3_gadget_stop,
1663};
1664
1665/* -------------------------------------------------------------------------- */
1666
1667static int dwc3_gadget_init_hw_endpoints(struct dwc3 *dwc,
1668 u8 num, u32 direction)
1669{
1670 struct dwc3_ep *dep;
1671 u8 i;
1672
1673 for (i = 0; i < num; i++) {
1674 u8 epnum = (i << 1) | (!!direction);
1675
1676 dep = kzalloc(sizeof(*dep), GFP_KERNEL);
1677 if (!dep) {
1678 dev_err(dwc->dev, "can't allocate endpoint %d\n",
1679 epnum);
1680 return -ENOMEM;
1681 }
1682
1683 dep->dwc = dwc;
1684 dep->number = epnum;
1685 dep->direction = !!direction;
1686 dwc->eps[epnum] = dep;
1687
1688 snprintf(dep->name, sizeof(dep->name), "ep%d%s", epnum >> 1,
1689 (epnum & 1) ? "in" : "out");
1690
1691 dep->endpoint.name = dep->name;
1692
1693 dev_vdbg(dwc->dev, "initializing %s\n", dep->name);
1694
1695 if (epnum == 0 || epnum == 1) {
1696 usb_ep_set_maxpacket_limit(&dep->endpoint, 512);
1697 dep->endpoint.maxburst = 1;
1698 dep->endpoint.ops = &dwc3_gadget_ep0_ops;
1699 if (!epnum)
1700 dwc->gadget.ep0 = &dep->endpoint;
1701 } else {
1702 int ret;
1703
1704 usb_ep_set_maxpacket_limit(&dep->endpoint, 1024);
1705 dep->endpoint.max_streams = 15;
1706 dep->endpoint.ops = &dwc3_gadget_ep_ops;
1707 list_add_tail(&dep->endpoint.ep_list,
1708 &dwc->gadget.ep_list);
1709
1710 ret = dwc3_alloc_trb_pool(dep);
1711 if (ret)
1712 return ret;
1713 }
1714
1715 INIT_LIST_HEAD(&dep->request_list);
1716 INIT_LIST_HEAD(&dep->req_queued);
1717 }
1718
1719 return 0;
1720}
1721
1722static int dwc3_gadget_init_endpoints(struct dwc3 *dwc)
1723{
1724 int ret;
1725
1726 INIT_LIST_HEAD(&dwc->gadget.ep_list);
1727
1728 ret = dwc3_gadget_init_hw_endpoints(dwc, dwc->num_out_eps, 0);
1729 if (ret < 0) {
1730 dev_vdbg(dwc->dev, "failed to allocate OUT endpoints\n");
1731 return ret;
1732 }
1733
1734 ret = dwc3_gadget_init_hw_endpoints(dwc, dwc->num_in_eps, 1);
1735 if (ret < 0) {
1736 dev_vdbg(dwc->dev, "failed to allocate IN endpoints\n");
1737 return ret;
1738 }
1739
1740 return 0;
1741}
1742
1743static void dwc3_gadget_free_endpoints(struct dwc3 *dwc)
1744{
1745 struct dwc3_ep *dep;
1746 u8 epnum;
1747
1748 for (epnum = 0; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
1749 dep = dwc->eps[epnum];
1750 if (!dep)
1751 continue;
1752 /*
1753 * Physical endpoints 0 and 1 are special; they form the
1754 * bi-directional USB endpoint 0.
1755 *
1756 * For those two physical endpoints, we don't allocate a TRB
1757 * pool nor do we add them the endpoints list. Due to that, we
1758 * shouldn't do these two operations otherwise we would end up
1759 * with all sorts of bugs when removing dwc3.ko.
1760 */
1761 if (epnum != 0 && epnum != 1) {
1762 dwc3_free_trb_pool(dep);
1763 list_del(&dep->endpoint.ep_list);
1764 }
1765
1766 kfree(dep);
1767 }
1768}
1769
1770/* -------------------------------------------------------------------------- */
1771
1772static int __dwc3_cleanup_done_trbs(struct dwc3 *dwc, struct dwc3_ep *dep,
1773 struct dwc3_request *req, struct dwc3_trb *trb,
1774 const struct dwc3_event_depevt *event, int status)
1775{
1776 unsigned int count;
1777 unsigned int s_pkt = 0;
1778 unsigned int trb_status;
1779
1780 if ((trb->ctrl & DWC3_TRB_CTRL_HWO) && status != -ESHUTDOWN)
1781 /*
1782 * We continue despite the error. There is not much we
1783 * can do. If we don't clean it up we loop forever. If
1784 * we skip the TRB then it gets overwritten after a
1785 * while since we use them in a ring buffer. A BUG()
1786 * would help. Lets hope that if this occurs, someone
1787 * fixes the root cause instead of looking away :)
1788 */
1789 dev_err(dwc->dev, "%s's TRB (%p) still owned by HW\n",
1790 dep->name, trb);
1791 count = trb->size & DWC3_TRB_SIZE_MASK;
1792
1793 if (dep->direction) {
1794 if (count) {
1795 trb_status = DWC3_TRB_SIZE_TRBSTS(trb->size);
1796 if (trb_status == DWC3_TRBSTS_MISSED_ISOC) {
1797 dev_dbg(dwc->dev, "incomplete IN transfer %s\n",
1798 dep->name);
1799 /*
1800 * If missed isoc occurred and there is
1801 * no request queued then issue END
1802 * TRANSFER, so that core generates
1803 * next xfernotready and we will issue
1804 * a fresh START TRANSFER.
1805 * If there are still queued request
1806 * then wait, do not issue either END
1807 * or UPDATE TRANSFER, just attach next
1808 * request in request_list during
1809 * giveback.If any future queued request
1810 * is successfully transferred then we
1811 * will issue UPDATE TRANSFER for all
1812 * request in the request_list.
1813 */
1814 dep->flags |= DWC3_EP_MISSED_ISOC;
1815 } else {
1816 dev_err(dwc->dev, "incomplete IN transfer %s\n",
1817 dep->name);
1818 status = -ECONNRESET;
1819 }
1820 } else {
1821 dep->flags &= ~DWC3_EP_MISSED_ISOC;
1822 }
1823 } else {
1824 if (count && (event->status & DEPEVT_STATUS_SHORT))
1825 s_pkt = 1;
1826 }
1827
1828 /*
1829 * We assume here we will always receive the entire data block
1830 * which we should receive. Meaning, if we program RX to
1831 * receive 4K but we receive only 2K, we assume that's all we
1832 * should receive and we simply bounce the request back to the
1833 * gadget driver for further processing.
1834 */
1835 req->request.actual += req->request.length - count;
1836 if (s_pkt)
1837 return 1;
1838 if ((event->status & DEPEVT_STATUS_LST) &&
1839 (trb->ctrl & (DWC3_TRB_CTRL_LST |
1840 DWC3_TRB_CTRL_HWO)))
1841 return 1;
1842 if ((event->status & DEPEVT_STATUS_IOC) &&
1843 (trb->ctrl & DWC3_TRB_CTRL_IOC))
1844 return 1;
1845 return 0;
1846}
1847
1848static int dwc3_cleanup_done_reqs(struct dwc3 *dwc, struct dwc3_ep *dep,
1849 const struct dwc3_event_depevt *event, int status)
1850{
1851 struct dwc3_request *req;
1852 struct dwc3_trb *trb;
1853 unsigned int slot;
1854 unsigned int i;
1855 int ret;
1856
1857 do {
1858 req = next_request(&dep->req_queued);
1859 if (!req) {
1860 WARN_ON_ONCE(1);
1861 return 1;
1862 }
1863 i = 0;
1864 do {
1865 slot = req->start_slot + i;
1866 if ((slot == DWC3_TRB_NUM - 1) &&
1867 usb_endpoint_xfer_isoc(dep->endpoint.desc))
1868 slot++;
1869 slot %= DWC3_TRB_NUM;
1870 trb = &dep->trb_pool[slot];
1871
1872 ret = __dwc3_cleanup_done_trbs(dwc, dep, req, trb,
1873 event, status);
1874 if (ret)
1875 break;
1876 }while (++i < req->request.num_mapped_sgs);
1877
1878 dwc3_gadget_giveback(dep, req, status);
1879
1880 if (ret)
1881 break;
1882 } while (1);
1883
1884 if (usb_endpoint_xfer_isoc(dep->endpoint.desc) &&
1885 list_empty(&dep->req_queued)) {
1886 if (list_empty(&dep->request_list)) {
1887 /*
1888 * If there is no entry in request list then do
1889 * not issue END TRANSFER now. Just set PENDING
1890 * flag, so that END TRANSFER is issued when an
1891 * entry is added into request list.
1892 */
1893 dep->flags = DWC3_EP_PENDING_REQUEST;
1894 } else {
1895 dwc3_stop_active_transfer(dwc, dep->number, true);
1896 dep->flags = DWC3_EP_ENABLED;
1897 }
1898 return 1;
1899 }
1900
1901 return 1;
1902}
1903
1904static void dwc3_endpoint_transfer_complete(struct dwc3 *dwc,
1905 struct dwc3_ep *dep, const struct dwc3_event_depevt *event,
1906 int start_new)
1907{
1908 unsigned status = 0;
1909 int clean_busy;
1910
1911 if (event->status & DEPEVT_STATUS_BUSERR)
1912 status = -ECONNRESET;
1913
1914 clean_busy = dwc3_cleanup_done_reqs(dwc, dep, event, status);
1915 if (clean_busy)
1916 dep->flags &= ~DWC3_EP_BUSY;
1917
1918 /*
1919 * WORKAROUND: This is the 2nd half of U1/U2 -> U0 workaround.
1920 * See dwc3_gadget_linksts_change_interrupt() for 1st half.
1921 */
1922 if (dwc->revision < DWC3_REVISION_183A) {
1923 u32 reg;
1924 int i;
1925
1926 for (i = 0; i < DWC3_ENDPOINTS_NUM; i++) {
1927 dep = dwc->eps[i];
1928
1929 if (!(dep->flags & DWC3_EP_ENABLED))
1930 continue;
1931
1932 if (!list_empty(&dep->req_queued))
1933 return;
1934 }
1935
1936 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
1937 reg |= dwc->u1u2;
1938 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1939
1940 dwc->u1u2 = 0;
1941 }
1942}
1943
1944static void dwc3_endpoint_interrupt(struct dwc3 *dwc,
1945 const struct dwc3_event_depevt *event)
1946{
1947 struct dwc3_ep *dep;
1948 u8 epnum = event->endpoint_number;
1949
1950 dep = dwc->eps[epnum];
1951
1952 if (!(dep->flags & DWC3_EP_ENABLED))
1953 return;
1954
1955 dev_vdbg(dwc->dev, "%s: %s\n", dep->name,
1956 dwc3_ep_event_string(event->endpoint_event));
1957
1958 if (epnum == 0 || epnum == 1) {
1959 dwc3_ep0_interrupt(dwc, event);
1960 return;
1961 }
1962
1963 switch (event->endpoint_event) {
1964 case DWC3_DEPEVT_XFERCOMPLETE:
1965 dep->resource_index = 0;
1966
1967 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1968 dev_dbg(dwc->dev, "%s is an Isochronous endpoint\n",
1969 dep->name);
1970 return;
1971 }
1972
1973 dwc3_endpoint_transfer_complete(dwc, dep, event, 1);
1974 break;
1975 case DWC3_DEPEVT_XFERINPROGRESS:
1976 if (!usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1977 dev_dbg(dwc->dev, "%s is not an Isochronous endpoint\n",
1978 dep->name);
1979 return;
1980 }
1981
1982 dwc3_endpoint_transfer_complete(dwc, dep, event, 0);
1983 break;
1984 case DWC3_DEPEVT_XFERNOTREADY:
1985 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1986 dwc3_gadget_start_isoc(dwc, dep, event);
1987 } else {
1988 int ret;
1989
1990 dev_vdbg(dwc->dev, "%s: reason %s\n",
1991 dep->name, event->status &
1992 DEPEVT_STATUS_TRANSFER_ACTIVE
1993 ? "Transfer Active"
1994 : "Transfer Not Active");
1995
1996 ret = __dwc3_gadget_kick_transfer(dep, 0, 1);
1997 if (!ret || ret == -EBUSY)
1998 return;
1999
2000 dev_dbg(dwc->dev, "%s: failed to kick transfers\n",
2001 dep->name);
2002 }
2003
2004 break;
2005 case DWC3_DEPEVT_STREAMEVT:
2006 if (!usb_endpoint_xfer_bulk(dep->endpoint.desc)) {
2007 dev_err(dwc->dev, "Stream event for non-Bulk %s\n",
2008 dep->name);
2009 return;
2010 }
2011
2012 switch (event->status) {
2013 case DEPEVT_STREAMEVT_FOUND:
2014 dev_vdbg(dwc->dev, "Stream %d found and started\n",
2015 event->parameters);
2016
2017 break;
2018 case DEPEVT_STREAMEVT_NOTFOUND:
2019 /* FALLTHROUGH */
2020 default:
2021 dev_dbg(dwc->dev, "Couldn't find suitable stream\n");
2022 }
2023 break;
2024 case DWC3_DEPEVT_RXTXFIFOEVT:
2025 dev_dbg(dwc->dev, "%s FIFO Overrun\n", dep->name);
2026 break;
2027 case DWC3_DEPEVT_EPCMDCMPLT:
2028 dev_vdbg(dwc->dev, "Endpoint Command Complete\n");
2029 break;
2030 }
2031}
2032
2033static void dwc3_disconnect_gadget(struct dwc3 *dwc)
2034{
2035 if (dwc->gadget_driver && dwc->gadget_driver->disconnect) {
2036 spin_unlock(&dwc->lock);
2037 dwc->gadget_driver->disconnect(&dwc->gadget);
2038 spin_lock(&dwc->lock);
2039 }
2040}
2041
2042static void dwc3_suspend_gadget(struct dwc3 *dwc)
2043{
2044 if (dwc->gadget_driver && dwc->gadget_driver->suspend) {
2045 spin_unlock(&dwc->lock);
2046 dwc->gadget_driver->suspend(&dwc->gadget);
2047 spin_lock(&dwc->lock);
2048 }
2049}
2050
2051static void dwc3_resume_gadget(struct dwc3 *dwc)
2052{
2053 if (dwc->gadget_driver && dwc->gadget_driver->resume) {
2054 spin_unlock(&dwc->lock);
2055 dwc->gadget_driver->resume(&dwc->gadget);
2056 spin_lock(&dwc->lock);
2057 }
2058}
2059
2060static void dwc3_stop_active_transfer(struct dwc3 *dwc, u32 epnum, bool force)
2061{
2062 struct dwc3_ep *dep;
2063 struct dwc3_gadget_ep_cmd_params params;
2064 u32 cmd;
2065 int ret;
2066
2067 dep = dwc->eps[epnum];
2068
2069 if (!dep->resource_index)
2070 return;
2071
2072 /*
2073 * NOTICE: We are violating what the Databook says about the
2074 * EndTransfer command. Ideally we would _always_ wait for the
2075 * EndTransfer Command Completion IRQ, but that's causing too
2076 * much trouble synchronizing between us and gadget driver.
2077 *
2078 * We have discussed this with the IP Provider and it was
2079 * suggested to giveback all requests here, but give HW some
2080 * extra time to synchronize with the interconnect. We're using
2081 * an arbitraty 100us delay for that.
2082 *
2083 * Note also that a similar handling was tested by Synopsys
2084 * (thanks a lot Paul) and nothing bad has come out of it.
2085 * In short, what we're doing is:
2086 *
2087 * - Issue EndTransfer WITH CMDIOC bit set
2088 * - Wait 100us
2089 */
2090
2091 cmd = DWC3_DEPCMD_ENDTRANSFER;
2092 cmd |= force ? DWC3_DEPCMD_HIPRI_FORCERM : 0;
2093 cmd |= DWC3_DEPCMD_CMDIOC;
2094 cmd |= DWC3_DEPCMD_PARAM(dep->resource_index);
2095 memset(¶ms, 0, sizeof(params));
2096 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, cmd, ¶ms);
2097 WARN_ON_ONCE(ret);
2098 dep->resource_index = 0;
2099 dep->flags &= ~DWC3_EP_BUSY;
2100 udelay(100);
2101}
2102
2103static void dwc3_stop_active_transfers(struct dwc3 *dwc)
2104{
2105 u32 epnum;
2106
2107 for (epnum = 2; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
2108 struct dwc3_ep *dep;
2109
2110 dep = dwc->eps[epnum];
2111 if (!dep)
2112 continue;
2113
2114 if (!(dep->flags & DWC3_EP_ENABLED))
2115 continue;
2116
2117 dwc3_remove_requests(dwc, dep);
2118 }
2119}
2120
2121static void dwc3_clear_stall_all_ep(struct dwc3 *dwc)
2122{
2123 u32 epnum;
2124
2125 for (epnum = 1; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
2126 struct dwc3_ep *dep;
2127 struct dwc3_gadget_ep_cmd_params params;
2128 int ret;
2129
2130 dep = dwc->eps[epnum];
2131 if (!dep)
2132 continue;
2133
2134 if (!(dep->flags & DWC3_EP_STALL))
2135 continue;
2136
2137 dep->flags &= ~DWC3_EP_STALL;
2138
2139 memset(¶ms, 0, sizeof(params));
2140 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number,
2141 DWC3_DEPCMD_CLEARSTALL, ¶ms);
2142 WARN_ON_ONCE(ret);
2143 }
2144}
2145
2146static void dwc3_gadget_disconnect_interrupt(struct dwc3 *dwc)
2147{
2148 int reg;
2149
2150 dev_vdbg(dwc->dev, "%s\n", __func__);
2151
2152 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2153 reg &= ~DWC3_DCTL_INITU1ENA;
2154 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2155
2156 reg &= ~DWC3_DCTL_INITU2ENA;
2157 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2158
2159 dwc3_disconnect_gadget(dwc);
2160 dwc->start_config_issued = false;
2161
2162 dwc->gadget.speed = USB_SPEED_UNKNOWN;
2163 dwc->setup_packet_pending = false;
2164}
2165
2166static void dwc3_gadget_reset_interrupt(struct dwc3 *dwc)
2167{
2168 u32 reg;
2169
2170 dev_vdbg(dwc->dev, "%s\n", __func__);
2171
2172 /*
2173 * WORKAROUND: DWC3 revisions <1.88a have an issue which
2174 * would cause a missing Disconnect Event if there's a
2175 * pending Setup Packet in the FIFO.
2176 *
2177 * There's no suggested workaround on the official Bug
2178 * report, which states that "unless the driver/application
2179 * is doing any special handling of a disconnect event,
2180 * there is no functional issue".
2181 *
2182 * Unfortunately, it turns out that we _do_ some special
2183 * handling of a disconnect event, namely complete all
2184 * pending transfers, notify gadget driver of the
2185 * disconnection, and so on.
2186 *
2187 * Our suggested workaround is to follow the Disconnect
2188 * Event steps here, instead, based on a setup_packet_pending
2189 * flag. Such flag gets set whenever we have a XferNotReady
2190 * event on EP0 and gets cleared on XferComplete for the
2191 * same endpoint.
2192 *
2193 * Refers to:
2194 *
2195 * STAR#9000466709: RTL: Device : Disconnect event not
2196 * generated if setup packet pending in FIFO
2197 */
2198 if (dwc->revision < DWC3_REVISION_188A) {
2199 if (dwc->setup_packet_pending)
2200 dwc3_gadget_disconnect_interrupt(dwc);
2201 }
2202
2203 /* after reset -> Default State */
2204 usb_gadget_set_state(&dwc->gadget, USB_STATE_DEFAULT);
2205
2206 if (dwc->gadget.speed != USB_SPEED_UNKNOWN)
2207 dwc3_disconnect_gadget(dwc);
2208
2209 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2210 reg &= ~DWC3_DCTL_TSTCTRL_MASK;
2211 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2212 dwc->test_mode = false;
2213
2214 dwc3_stop_active_transfers(dwc);
2215 dwc3_clear_stall_all_ep(dwc);
2216 dwc->start_config_issued = false;
2217
2218 /* Reset device address to zero */
2219 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2220 reg &= ~(DWC3_DCFG_DEVADDR_MASK);
2221 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2222}
2223
2224static void dwc3_update_ram_clk_sel(struct dwc3 *dwc, u32 speed)
2225{
2226 u32 reg;
2227 u32 usb30_clock = DWC3_GCTL_CLK_BUS;
2228
2229 /*
2230 * We change the clock only at SS but I dunno why I would want to do
2231 * this. Maybe it becomes part of the power saving plan.
2232 */
2233
2234 if (speed != DWC3_DSTS_SUPERSPEED)
2235 return;
2236
2237 /*
2238 * RAMClkSel is reset to 0 after USB reset, so it must be reprogrammed
2239 * each time on Connect Done.
2240 */
2241 if (!usb30_clock)
2242 return;
2243
2244 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
2245 reg |= DWC3_GCTL_RAMCLKSEL(usb30_clock);
2246 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
2247}
2248
2249static void dwc3_gadget_conndone_interrupt(struct dwc3 *dwc)
2250{
2251 struct dwc3_ep *dep;
2252 int ret;
2253 u32 reg;
2254 u8 speed;
2255
2256 dev_vdbg(dwc->dev, "%s\n", __func__);
2257
2258 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
2259 speed = reg & DWC3_DSTS_CONNECTSPD;
2260 dwc->speed = speed;
2261
2262 dwc3_update_ram_clk_sel(dwc, speed);
2263
2264 switch (speed) {
2265 case DWC3_DCFG_SUPERSPEED:
2266 /*
2267 * WORKAROUND: DWC3 revisions <1.90a have an issue which
2268 * would cause a missing USB3 Reset event.
2269 *
2270 * In such situations, we should force a USB3 Reset
2271 * event by calling our dwc3_gadget_reset_interrupt()
2272 * routine.
2273 *
2274 * Refers to:
2275 *
2276 * STAR#9000483510: RTL: SS : USB3 reset event may
2277 * not be generated always when the link enters poll
2278 */
2279 if (dwc->revision < DWC3_REVISION_190A)
2280 dwc3_gadget_reset_interrupt(dwc);
2281
2282 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
2283 dwc->gadget.ep0->maxpacket = 512;
2284 dwc->gadget.speed = USB_SPEED_SUPER;
2285 break;
2286 case DWC3_DCFG_HIGHSPEED:
2287 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
2288 dwc->gadget.ep0->maxpacket = 64;
2289 dwc->gadget.speed = USB_SPEED_HIGH;
2290 break;
2291 case DWC3_DCFG_FULLSPEED2:
2292 case DWC3_DCFG_FULLSPEED1:
2293 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
2294 dwc->gadget.ep0->maxpacket = 64;
2295 dwc->gadget.speed = USB_SPEED_FULL;
2296 break;
2297 case DWC3_DCFG_LOWSPEED:
2298 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(8);
2299 dwc->gadget.ep0->maxpacket = 8;
2300 dwc->gadget.speed = USB_SPEED_LOW;
2301 break;
2302 }
2303
2304 /* Enable USB2 LPM Capability */
2305
2306 if ((dwc->revision > DWC3_REVISION_194A)
2307 && (speed != DWC3_DCFG_SUPERSPEED)) {
2308 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2309 reg |= DWC3_DCFG_LPM_CAP;
2310 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2311
2312 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2313 reg &= ~(DWC3_DCTL_HIRD_THRES_MASK | DWC3_DCTL_L1_HIBER_EN);
2314
2315 /*
2316 * TODO: This should be configurable. For now using
2317 * maximum allowed HIRD threshold value of 0b1100
2318 */
2319 reg |= DWC3_DCTL_HIRD_THRES(12);
2320
2321 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2322 } else {
2323 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2324 reg &= ~DWC3_DCTL_HIRD_THRES_MASK;
2325 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2326 }
2327
2328 dep = dwc->eps[0];
2329 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, true,
2330 false);
2331 if (ret) {
2332 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
2333 return;
2334 }
2335
2336 dep = dwc->eps[1];
2337 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, true,
2338 false);
2339 if (ret) {
2340 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
2341 return;
2342 }
2343
2344 /*
2345 * Configure PHY via GUSB3PIPECTLn if required.
2346 *
2347 * Update GTXFIFOSIZn
2348 *
2349 * In both cases reset values should be sufficient.
2350 */
2351}
2352
2353static void dwc3_gadget_wakeup_interrupt(struct dwc3 *dwc)
2354{
2355 dev_vdbg(dwc->dev, "%s\n", __func__);
2356
2357 /*
2358 * TODO take core out of low power mode when that's
2359 * implemented.
2360 */
2361
2362 dwc->gadget_driver->resume(&dwc->gadget);
2363}
2364
2365static void dwc3_gadget_linksts_change_interrupt(struct dwc3 *dwc,
2366 unsigned int evtinfo)
2367{
2368 enum dwc3_link_state next = evtinfo & DWC3_LINK_STATE_MASK;
2369 unsigned int pwropt;
2370
2371 /*
2372 * WORKAROUND: DWC3 < 2.50a have an issue when configured without
2373 * Hibernation mode enabled which would show up when device detects
2374 * host-initiated U3 exit.
2375 *
2376 * In that case, device will generate a Link State Change Interrupt
2377 * from U3 to RESUME which is only necessary if Hibernation is
2378 * configured in.
2379 *
2380 * There are no functional changes due to such spurious event and we
2381 * just need to ignore it.
2382 *
2383 * Refers to:
2384 *
2385 * STAR#9000570034 RTL: SS Resume event generated in non-Hibernation
2386 * operational mode
2387 */
2388 pwropt = DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1);
2389 if ((dwc->revision < DWC3_REVISION_250A) &&
2390 (pwropt != DWC3_GHWPARAMS1_EN_PWROPT_HIB)) {
2391 if ((dwc->link_state == DWC3_LINK_STATE_U3) &&
2392 (next == DWC3_LINK_STATE_RESUME)) {
2393 dev_vdbg(dwc->dev, "ignoring transition U3 -> Resume\n");
2394 return;
2395 }
2396 }
2397
2398 /*
2399 * WORKAROUND: DWC3 Revisions <1.83a have an issue which, depending
2400 * on the link partner, the USB session might do multiple entry/exit
2401 * of low power states before a transfer takes place.
2402 *
2403 * Due to this problem, we might experience lower throughput. The
2404 * suggested workaround is to disable DCTL[12:9] bits if we're
2405 * transitioning from U1/U2 to U0 and enable those bits again
2406 * after a transfer completes and there are no pending transfers
2407 * on any of the enabled endpoints.
2408 *
2409 * This is the first half of that workaround.
2410 *
2411 * Refers to:
2412 *
2413 * STAR#9000446952: RTL: Device SS : if U1/U2 ->U0 takes >128us
2414 * core send LGO_Ux entering U0
2415 */
2416 if (dwc->revision < DWC3_REVISION_183A) {
2417 if (next == DWC3_LINK_STATE_U0) {
2418 u32 u1u2;
2419 u32 reg;
2420
2421 switch (dwc->link_state) {
2422 case DWC3_LINK_STATE_U1:
2423 case DWC3_LINK_STATE_U2:
2424 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2425 u1u2 = reg & (DWC3_DCTL_INITU2ENA
2426 | DWC3_DCTL_ACCEPTU2ENA
2427 | DWC3_DCTL_INITU1ENA
2428 | DWC3_DCTL_ACCEPTU1ENA);
2429
2430 if (!dwc->u1u2)
2431 dwc->u1u2 = reg & u1u2;
2432
2433 reg &= ~u1u2;
2434
2435 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2436 break;
2437 default:
2438 /* do nothing */
2439 break;
2440 }
2441 }
2442 }
2443
2444 dwc->link_state = next;
2445
2446 switch (next) {
2447 case DWC3_LINK_STATE_U1:
2448 if (dwc->speed == USB_SPEED_SUPER)
2449 dwc3_suspend_gadget(dwc);
2450 break;
2451 case DWC3_LINK_STATE_U2:
2452 case DWC3_LINK_STATE_U3:
2453 dwc3_suspend_gadget(dwc);
2454 break;
2455 case DWC3_LINK_STATE_RESUME:
2456 dwc3_resume_gadget(dwc);
2457 break;
2458 default:
2459 /* do nothing */
2460 break;
2461 }
2462
2463 dev_vdbg(dwc->dev, "%s link %d\n", __func__, dwc->link_state);
2464}
2465
2466static void dwc3_gadget_hibernation_interrupt(struct dwc3 *dwc,
2467 unsigned int evtinfo)
2468{
2469 unsigned int is_ss = evtinfo & BIT(4);
2470
2471 /**
2472 * WORKAROUND: DWC3 revison 2.20a with hibernation support
2473 * have a known issue which can cause USB CV TD.9.23 to fail
2474 * randomly.
2475 *
2476 * Because of this issue, core could generate bogus hibernation
2477 * events which SW needs to ignore.
2478 *
2479 * Refers to:
2480 *
2481 * STAR#9000546576: Device Mode Hibernation: Issue in USB 2.0
2482 * Device Fallback from SuperSpeed
2483 */
2484 if (is_ss ^ (dwc->speed == USB_SPEED_SUPER))
2485 return;
2486
2487 /* enter hibernation here */
2488}
2489
2490static void dwc3_gadget_interrupt(struct dwc3 *dwc,
2491 const struct dwc3_event_devt *event)
2492{
2493 switch (event->type) {
2494 case DWC3_DEVICE_EVENT_DISCONNECT:
2495 dwc3_gadget_disconnect_interrupt(dwc);
2496 break;
2497 case DWC3_DEVICE_EVENT_RESET:
2498 dwc3_gadget_reset_interrupt(dwc);
2499 break;
2500 case DWC3_DEVICE_EVENT_CONNECT_DONE:
2501 dwc3_gadget_conndone_interrupt(dwc);
2502 break;
2503 case DWC3_DEVICE_EVENT_WAKEUP:
2504 dwc3_gadget_wakeup_interrupt(dwc);
2505 break;
2506 case DWC3_DEVICE_EVENT_HIBER_REQ:
2507 if (dev_WARN_ONCE(dwc->dev, !dwc->has_hibernation,
2508 "unexpected hibernation event\n"))
2509 break;
2510
2511 dwc3_gadget_hibernation_interrupt(dwc, event->event_info);
2512 break;
2513 case DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE:
2514 dwc3_gadget_linksts_change_interrupt(dwc, event->event_info);
2515 break;
2516 case DWC3_DEVICE_EVENT_EOPF:
2517 dev_vdbg(dwc->dev, "End of Periodic Frame\n");
2518 break;
2519 case DWC3_DEVICE_EVENT_SOF:
2520 dev_vdbg(dwc->dev, "Start of Periodic Frame\n");
2521 break;
2522 case DWC3_DEVICE_EVENT_ERRATIC_ERROR:
2523 dev_vdbg(dwc->dev, "Erratic Error\n");
2524 break;
2525 case DWC3_DEVICE_EVENT_CMD_CMPL:
2526 dev_vdbg(dwc->dev, "Command Complete\n");
2527 break;
2528 case DWC3_DEVICE_EVENT_OVERFLOW:
2529 dev_vdbg(dwc->dev, "Overflow\n");
2530 break;
2531 default:
2532 dev_dbg(dwc->dev, "UNKNOWN IRQ %d\n", event->type);
2533 }
2534}
2535
2536static void dwc3_process_event_entry(struct dwc3 *dwc,
2537 const union dwc3_event *event)
2538{
2539 /* Endpoint IRQ, handle it and return early */
2540 if (event->type.is_devspec == 0) {
2541 /* depevt */
2542 return dwc3_endpoint_interrupt(dwc, &event->depevt);
2543 }
2544
2545 switch (event->type.type) {
2546 case DWC3_EVENT_TYPE_DEV:
2547 dwc3_gadget_interrupt(dwc, &event->devt);
2548 break;
2549 /* REVISIT what to do with Carkit and I2C events ? */
2550 default:
2551 dev_err(dwc->dev, "UNKNOWN IRQ type %d\n", event->raw);
2552 }
2553}
2554
2555static irqreturn_t dwc3_process_event_buf(struct dwc3 *dwc, u32 buf)
2556{
2557 struct dwc3_event_buffer *evt;
2558 irqreturn_t ret = IRQ_NONE;
2559 int left;
2560 u32 reg;
2561
2562 evt = dwc->ev_buffs[buf];
2563 left = evt->count;
2564
2565 if (!(evt->flags & DWC3_EVENT_PENDING))
2566 return IRQ_NONE;
2567
2568 while (left > 0) {
2569 union dwc3_event event;
2570
2571 event.raw = *(u32 *) (evt->buf + evt->lpos);
2572
2573 dwc3_process_event_entry(dwc, &event);
2574
2575 /*
2576 * FIXME we wrap around correctly to the next entry as
2577 * almost all entries are 4 bytes in size. There is one
2578 * entry which has 12 bytes which is a regular entry
2579 * followed by 8 bytes data. ATM I don't know how
2580 * things are organized if we get next to the a
2581 * boundary so I worry about that once we try to handle
2582 * that.
2583 */
2584 evt->lpos = (evt->lpos + 4) % DWC3_EVENT_BUFFERS_SIZE;
2585 left -= 4;
2586
2587 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(buf), 4);
2588 }
2589
2590 evt->count = 0;
2591 evt->flags &= ~DWC3_EVENT_PENDING;
2592 ret = IRQ_HANDLED;
2593
2594 /* Unmask interrupt */
2595 reg = dwc3_readl(dwc->regs, DWC3_GEVNTSIZ(buf));
2596 reg &= ~DWC3_GEVNTSIZ_INTMASK;
2597 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(buf), reg);
2598
2599 return ret;
2600}
2601
2602static irqreturn_t dwc3_thread_interrupt(int irq, void *_dwc)
2603{
2604 struct dwc3 *dwc = _dwc;
2605 unsigned long flags;
2606 irqreturn_t ret = IRQ_NONE;
2607 int i;
2608
2609 spin_lock_irqsave(&dwc->lock, flags);
2610
2611 for (i = 0; i < dwc->num_event_buffers; i++)
2612 ret |= dwc3_process_event_buf(dwc, i);
2613
2614 spin_unlock_irqrestore(&dwc->lock, flags);
2615
2616 return ret;
2617}
2618
2619static irqreturn_t dwc3_check_event_buf(struct dwc3 *dwc, u32 buf)
2620{
2621 struct dwc3_event_buffer *evt;
2622 u32 count;
2623 u32 reg;
2624
2625 evt = dwc->ev_buffs[buf];
2626
2627 count = dwc3_readl(dwc->regs, DWC3_GEVNTCOUNT(buf));
2628 count &= DWC3_GEVNTCOUNT_MASK;
2629 if (!count)
2630 return IRQ_NONE;
2631
2632 evt->count = count;
2633 evt->flags |= DWC3_EVENT_PENDING;
2634
2635 /* Mask interrupt */
2636 reg = dwc3_readl(dwc->regs, DWC3_GEVNTSIZ(buf));
2637 reg |= DWC3_GEVNTSIZ_INTMASK;
2638 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(buf), reg);
2639
2640 return IRQ_WAKE_THREAD;
2641}
2642
2643static irqreturn_t dwc3_interrupt(int irq, void *_dwc)
2644{
2645 struct dwc3 *dwc = _dwc;
2646 int i;
2647 irqreturn_t ret = IRQ_NONE;
2648
2649 spin_lock(&dwc->lock);
2650
2651 for (i = 0; i < dwc->num_event_buffers; i++) {
2652 irqreturn_t status;
2653
2654 status = dwc3_check_event_buf(dwc, i);
2655 if (status == IRQ_WAKE_THREAD)
2656 ret = status;
2657 }
2658
2659 spin_unlock(&dwc->lock);
2660
2661 return ret;
2662}
2663
2664/**
2665 * dwc3_gadget_init - Initializes gadget related registers
2666 * @dwc: pointer to our controller context structure
2667 *
2668 * Returns 0 on success otherwise negative errno.
2669 */
2670int dwc3_gadget_init(struct dwc3 *dwc)
2671{
2672 int ret;
2673
2674 dwc->ctrl_req = dma_alloc_coherent(dwc->dev, sizeof(*dwc->ctrl_req),
2675 &dwc->ctrl_req_addr, GFP_KERNEL);
2676 if (!dwc->ctrl_req) {
2677 dev_err(dwc->dev, "failed to allocate ctrl request\n");
2678 ret = -ENOMEM;
2679 goto err0;
2680 }
2681
2682 dwc->ep0_trb = dma_alloc_coherent(dwc->dev, sizeof(*dwc->ep0_trb),
2683 &dwc->ep0_trb_addr, GFP_KERNEL);
2684 if (!dwc->ep0_trb) {
2685 dev_err(dwc->dev, "failed to allocate ep0 trb\n");
2686 ret = -ENOMEM;
2687 goto err1;
2688 }
2689
2690 dwc->setup_buf = kzalloc(DWC3_EP0_BOUNCE_SIZE, GFP_KERNEL);
2691 if (!dwc->setup_buf) {
2692 dev_err(dwc->dev, "failed to allocate setup buffer\n");
2693 ret = -ENOMEM;
2694 goto err2;
2695 }
2696
2697 dwc->ep0_bounce = dma_alloc_coherent(dwc->dev,
2698 DWC3_EP0_BOUNCE_SIZE, &dwc->ep0_bounce_addr,
2699 GFP_KERNEL);
2700 if (!dwc->ep0_bounce) {
2701 dev_err(dwc->dev, "failed to allocate ep0 bounce buffer\n");
2702 ret = -ENOMEM;
2703 goto err3;
2704 }
2705
2706 dwc->gadget.ops = &dwc3_gadget_ops;
2707 dwc->gadget.max_speed = USB_SPEED_SUPER;
2708 dwc->gadget.speed = USB_SPEED_UNKNOWN;
2709 dwc->gadget.sg_supported = true;
2710 dwc->gadget.name = "dwc3-gadget";
2711
2712 /*
2713 * Per databook, DWC3 needs buffer size to be aligned to MaxPacketSize
2714 * on ep out.
2715 */
2716 dwc->gadget.quirk_ep_out_aligned_size = true;
2717
2718 /*
2719 * REVISIT: Here we should clear all pending IRQs to be
2720 * sure we're starting from a well known location.
2721 */
2722
2723 ret = dwc3_gadget_init_endpoints(dwc);
2724 if (ret)
2725 goto err4;
2726
2727 ret = usb_add_gadget_udc(dwc->dev, &dwc->gadget);
2728 if (ret) {
2729 dev_err(dwc->dev, "failed to register udc\n");
2730 goto err4;
2731 }
2732
2733 return 0;
2734
2735err4:
2736 dwc3_gadget_free_endpoints(dwc);
2737 dma_free_coherent(dwc->dev, DWC3_EP0_BOUNCE_SIZE,
2738 dwc->ep0_bounce, dwc->ep0_bounce_addr);
2739
2740err3:
2741 kfree(dwc->setup_buf);
2742
2743err2:
2744 dma_free_coherent(dwc->dev, sizeof(*dwc->ep0_trb),
2745 dwc->ep0_trb, dwc->ep0_trb_addr);
2746
2747err1:
2748 dma_free_coherent(dwc->dev, sizeof(*dwc->ctrl_req),
2749 dwc->ctrl_req, dwc->ctrl_req_addr);
2750
2751err0:
2752 return ret;
2753}
2754
2755/* -------------------------------------------------------------------------- */
2756
2757void dwc3_gadget_exit(struct dwc3 *dwc)
2758{
2759 usb_del_gadget_udc(&dwc->gadget);
2760
2761 dwc3_gadget_free_endpoints(dwc);
2762
2763 dma_free_coherent(dwc->dev, DWC3_EP0_BOUNCE_SIZE,
2764 dwc->ep0_bounce, dwc->ep0_bounce_addr);
2765
2766 kfree(dwc->setup_buf);
2767
2768 dma_free_coherent(dwc->dev, sizeof(*dwc->ep0_trb),
2769 dwc->ep0_trb, dwc->ep0_trb_addr);
2770
2771 dma_free_coherent(dwc->dev, sizeof(*dwc->ctrl_req),
2772 dwc->ctrl_req, dwc->ctrl_req_addr);
2773}
2774
2775int dwc3_gadget_prepare(struct dwc3 *dwc)
2776{
2777 if (dwc->pullups_connected) {
2778 dwc3_gadget_disable_irq(dwc);
2779 dwc3_gadget_run_stop(dwc, true, true);
2780 }
2781
2782 return 0;
2783}
2784
2785void dwc3_gadget_complete(struct dwc3 *dwc)
2786{
2787 if (dwc->pullups_connected) {
2788 dwc3_gadget_enable_irq(dwc);
2789 dwc3_gadget_run_stop(dwc, true, false);
2790 }
2791}
2792
2793int dwc3_gadget_suspend(struct dwc3 *dwc)
2794{
2795 __dwc3_gadget_ep_disable(dwc->eps[0]);
2796 __dwc3_gadget_ep_disable(dwc->eps[1]);
2797
2798 dwc->dcfg = dwc3_readl(dwc->regs, DWC3_DCFG);
2799
2800 return 0;
2801}
2802
2803int dwc3_gadget_resume(struct dwc3 *dwc)
2804{
2805 struct dwc3_ep *dep;
2806 int ret;
2807
2808 /* Start with SuperSpeed Default */
2809 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
2810
2811 dep = dwc->eps[0];
2812 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, false,
2813 false);
2814 if (ret)
2815 goto err0;
2816
2817 dep = dwc->eps[1];
2818 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, false,
2819 false);
2820 if (ret)
2821 goto err1;
2822
2823 /* begin to receive SETUP packets */
2824 dwc->ep0state = EP0_SETUP_PHASE;
2825 dwc3_ep0_out_start(dwc);
2826
2827 dwc3_writel(dwc->regs, DWC3_DCFG, dwc->dcfg);
2828
2829 return 0;
2830
2831err1:
2832 __dwc3_gadget_ep_disable(dwc->eps[0]);
2833
2834err0:
2835 return ret;
2836}