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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * gadget.c - DesignWare USB3 DRD Controller Gadget Framework Link
4 *
5 * Copyright (C) 2010-2011 Texas Instruments Incorporated - https://www.ti.com
6 *
7 * Authors: Felipe Balbi <balbi@ti.com>,
8 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
9 */
10
11#include <linux/kernel.h>
12#include <linux/delay.h>
13#include <linux/slab.h>
14#include <linux/spinlock.h>
15#include <linux/platform_device.h>
16#include <linux/pm_runtime.h>
17#include <linux/interrupt.h>
18#include <linux/io.h>
19#include <linux/list.h>
20#include <linux/dma-mapping.h>
21
22#include <linux/usb/ch9.h>
23#include <linux/usb/gadget.h>
24
25#include "debug.h"
26#include "core.h"
27#include "gadget.h"
28#include "io.h"
29
30#define DWC3_ALIGN_FRAME(d, n) (((d)->frame_number + ((d)->interval * (n))) \
31 & ~((d)->interval - 1))
32
33/**
34 * dwc3_gadget_set_test_mode - enables usb2 test modes
35 * @dwc: pointer to our context structure
36 * @mode: the mode to set (J, K SE0 NAK, Force Enable)
37 *
38 * Caller should take care of locking. This function will return 0 on
39 * success or -EINVAL if wrong Test Selector is passed.
40 */
41int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode)
42{
43 u32 reg;
44
45 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
46 reg &= ~DWC3_DCTL_TSTCTRL_MASK;
47
48 switch (mode) {
49 case USB_TEST_J:
50 case USB_TEST_K:
51 case USB_TEST_SE0_NAK:
52 case USB_TEST_PACKET:
53 case USB_TEST_FORCE_ENABLE:
54 reg |= mode << 1;
55 break;
56 default:
57 return -EINVAL;
58 }
59
60 dwc3_gadget_dctl_write_safe(dwc, reg);
61
62 return 0;
63}
64
65/**
66 * dwc3_gadget_get_link_state - gets current state of usb link
67 * @dwc: pointer to our context structure
68 *
69 * Caller should take care of locking. This function will
70 * return the link state on success (>= 0) or -ETIMEDOUT.
71 */
72int dwc3_gadget_get_link_state(struct dwc3 *dwc)
73{
74 u32 reg;
75
76 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
77
78 return DWC3_DSTS_USBLNKST(reg);
79}
80
81/**
82 * dwc3_gadget_set_link_state - sets usb link to a particular state
83 * @dwc: pointer to our context structure
84 * @state: the state to put link into
85 *
86 * Caller should take care of locking. This function will
87 * return 0 on success or -ETIMEDOUT.
88 */
89int dwc3_gadget_set_link_state(struct dwc3 *dwc, enum dwc3_link_state state)
90{
91 int retries = 10000;
92 u32 reg;
93
94 /*
95 * Wait until device controller is ready. Only applies to 1.94a and
96 * later RTL.
97 */
98 if (!DWC3_VER_IS_PRIOR(DWC3, 194A)) {
99 while (--retries) {
100 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
101 if (reg & DWC3_DSTS_DCNRD)
102 udelay(5);
103 else
104 break;
105 }
106
107 if (retries <= 0)
108 return -ETIMEDOUT;
109 }
110
111 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
112 reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;
113
114 /* set no action before sending new link state change */
115 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
116
117 /* set requested state */
118 reg |= DWC3_DCTL_ULSTCHNGREQ(state);
119 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
120
121 /*
122 * The following code is racy when called from dwc3_gadget_wakeup,
123 * and is not needed, at least on newer versions
124 */
125 if (!DWC3_VER_IS_PRIOR(DWC3, 194A))
126 return 0;
127
128 /* wait for a change in DSTS */
129 retries = 10000;
130 while (--retries) {
131 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
132
133 if (DWC3_DSTS_USBLNKST(reg) == state)
134 return 0;
135
136 udelay(5);
137 }
138
139 return -ETIMEDOUT;
140}
141
142static void dwc3_ep0_reset_state(struct dwc3 *dwc)
143{
144 unsigned int dir;
145
146 if (dwc->ep0state != EP0_SETUP_PHASE) {
147 dir = !!dwc->ep0_expect_in;
148 if (dwc->ep0state == EP0_DATA_PHASE)
149 dwc3_ep0_end_control_data(dwc, dwc->eps[dir]);
150 else
151 dwc3_ep0_end_control_data(dwc, dwc->eps[!dir]);
152
153 dwc->eps[0]->trb_enqueue = 0;
154 dwc->eps[1]->trb_enqueue = 0;
155
156 dwc3_ep0_stall_and_restart(dwc);
157 }
158}
159
160/**
161 * dwc3_ep_inc_trb - increment a trb index.
162 * @index: Pointer to the TRB index to increment.
163 *
164 * The index should never point to the link TRB. After incrementing,
165 * if it is point to the link TRB, wrap around to the beginning. The
166 * link TRB is always at the last TRB entry.
167 */
168static void dwc3_ep_inc_trb(u8 *index)
169{
170 (*index)++;
171 if (*index == (DWC3_TRB_NUM - 1))
172 *index = 0;
173}
174
175/**
176 * dwc3_ep_inc_enq - increment endpoint's enqueue pointer
177 * @dep: The endpoint whose enqueue pointer we're incrementing
178 */
179static void dwc3_ep_inc_enq(struct dwc3_ep *dep)
180{
181 dwc3_ep_inc_trb(&dep->trb_enqueue);
182}
183
184/**
185 * dwc3_ep_inc_deq - increment endpoint's dequeue pointer
186 * @dep: The endpoint whose enqueue pointer we're incrementing
187 */
188static void dwc3_ep_inc_deq(struct dwc3_ep *dep)
189{
190 dwc3_ep_inc_trb(&dep->trb_dequeue);
191}
192
193static void dwc3_gadget_del_and_unmap_request(struct dwc3_ep *dep,
194 struct dwc3_request *req, int status)
195{
196 struct dwc3 *dwc = dep->dwc;
197
198 list_del(&req->list);
199 req->remaining = 0;
200 req->num_trbs = 0;
201
202 if (req->request.status == -EINPROGRESS)
203 req->request.status = status;
204
205 if (req->trb)
206 usb_gadget_unmap_request_by_dev(dwc->sysdev,
207 &req->request, req->direction);
208
209 req->trb = NULL;
210 trace_dwc3_gadget_giveback(req);
211
212 if (dep->number > 1)
213 pm_runtime_put(dwc->dev);
214}
215
216/**
217 * dwc3_gadget_giveback - call struct usb_request's ->complete callback
218 * @dep: The endpoint to whom the request belongs to
219 * @req: The request we're giving back
220 * @status: completion code for the request
221 *
222 * Must be called with controller's lock held and interrupts disabled. This
223 * function will unmap @req and call its ->complete() callback to notify upper
224 * layers that it has completed.
225 */
226void dwc3_gadget_giveback(struct dwc3_ep *dep, struct dwc3_request *req,
227 int status)
228{
229 struct dwc3 *dwc = dep->dwc;
230
231 dwc3_gadget_del_and_unmap_request(dep, req, status);
232 req->status = DWC3_REQUEST_STATUS_COMPLETED;
233
234 spin_unlock(&dwc->lock);
235 usb_gadget_giveback_request(&dep->endpoint, &req->request);
236 spin_lock(&dwc->lock);
237}
238
239/**
240 * dwc3_send_gadget_generic_command - issue a generic command for the controller
241 * @dwc: pointer to the controller context
242 * @cmd: the command to be issued
243 * @param: command parameter
244 *
245 * Caller should take care of locking. Issue @cmd with a given @param to @dwc
246 * and wait for its completion.
247 */
248int dwc3_send_gadget_generic_command(struct dwc3 *dwc, unsigned int cmd,
249 u32 param)
250{
251 u32 timeout = 500;
252 int status = 0;
253 int ret = 0;
254 u32 reg;
255
256 dwc3_writel(dwc->regs, DWC3_DGCMDPAR, param);
257 dwc3_writel(dwc->regs, DWC3_DGCMD, cmd | DWC3_DGCMD_CMDACT);
258
259 do {
260 reg = dwc3_readl(dwc->regs, DWC3_DGCMD);
261 if (!(reg & DWC3_DGCMD_CMDACT)) {
262 status = DWC3_DGCMD_STATUS(reg);
263 if (status)
264 ret = -EINVAL;
265 break;
266 }
267 } while (--timeout);
268
269 if (!timeout) {
270 ret = -ETIMEDOUT;
271 status = -ETIMEDOUT;
272 }
273
274 trace_dwc3_gadget_generic_cmd(cmd, param, status);
275
276 return ret;
277}
278
279static int __dwc3_gadget_wakeup(struct dwc3 *dwc, bool async);
280
281/**
282 * dwc3_send_gadget_ep_cmd - issue an endpoint command
283 * @dep: the endpoint to which the command is going to be issued
284 * @cmd: the command to be issued
285 * @params: parameters to the command
286 *
287 * Caller should handle locking. This function will issue @cmd with given
288 * @params to @dep and wait for its completion.
289 *
290 * According to the programming guide, if the link state is in L1/L2/U3,
291 * then sending the Start Transfer command may not complete. The
292 * programming guide suggested to bring the link state back to ON/U0 by
293 * performing remote wakeup prior to sending the command. However, don't
294 * initiate remote wakeup when the user/function does not send wakeup
295 * request via wakeup ops. Send the command when it's allowed.
296 *
297 * Notes:
298 * For L1 link state, issuing a command requires the clearing of
299 * GUSB2PHYCFG.SUSPENDUSB2, which turns on the signal required to complete
300 * the given command (usually within 50us). This should happen within the
301 * command timeout set by driver. No additional step is needed.
302 *
303 * For L2 or U3 link state, the gadget is in USB suspend. Care should be
304 * taken when sending Start Transfer command to ensure that it's done after
305 * USB resume.
306 */
307int dwc3_send_gadget_ep_cmd(struct dwc3_ep *dep, unsigned int cmd,
308 struct dwc3_gadget_ep_cmd_params *params)
309{
310 const struct usb_endpoint_descriptor *desc = dep->endpoint.desc;
311 struct dwc3 *dwc = dep->dwc;
312 u32 timeout = 5000;
313 u32 saved_config = 0;
314 u32 reg;
315
316 int cmd_status = 0;
317 int ret = -EINVAL;
318
319 /*
320 * When operating in USB 2.0 speeds (HS/FS), if GUSB2PHYCFG.ENBLSLPM or
321 * GUSB2PHYCFG.SUSPHY is set, it must be cleared before issuing an
322 * endpoint command.
323 *
324 * Save and clear both GUSB2PHYCFG.ENBLSLPM and GUSB2PHYCFG.SUSPHY
325 * settings. Restore them after the command is completed.
326 *
327 * DWC_usb3 3.30a and DWC_usb31 1.90a programming guide section 3.2.2
328 */
329 if (dwc->gadget->speed <= USB_SPEED_HIGH ||
330 DWC3_DEPCMD_CMD(cmd) == DWC3_DEPCMD_ENDTRANSFER) {
331 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
332 if (unlikely(reg & DWC3_GUSB2PHYCFG_SUSPHY)) {
333 saved_config |= DWC3_GUSB2PHYCFG_SUSPHY;
334 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
335 }
336
337 if (reg & DWC3_GUSB2PHYCFG_ENBLSLPM) {
338 saved_config |= DWC3_GUSB2PHYCFG_ENBLSLPM;
339 reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM;
340 }
341
342 if (saved_config)
343 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
344 }
345
346 /*
347 * For some commands such as Update Transfer command, DEPCMDPARn
348 * registers are reserved. Since the driver often sends Update Transfer
349 * command, don't write to DEPCMDPARn to avoid register write delays and
350 * improve performance.
351 */
352 if (DWC3_DEPCMD_CMD(cmd) != DWC3_DEPCMD_UPDATETRANSFER) {
353 dwc3_writel(dep->regs, DWC3_DEPCMDPAR0, params->param0);
354 dwc3_writel(dep->regs, DWC3_DEPCMDPAR1, params->param1);
355 dwc3_writel(dep->regs, DWC3_DEPCMDPAR2, params->param2);
356 }
357
358 /*
359 * Synopsys Databook 2.60a states in section 6.3.2.5.6 of that if we're
360 * not relying on XferNotReady, we can make use of a special "No
361 * Response Update Transfer" command where we should clear both CmdAct
362 * and CmdIOC bits.
363 *
364 * With this, we don't need to wait for command completion and can
365 * straight away issue further commands to the endpoint.
366 *
367 * NOTICE: We're making an assumption that control endpoints will never
368 * make use of Update Transfer command. This is a safe assumption
369 * because we can never have more than one request at a time with
370 * Control Endpoints. If anybody changes that assumption, this chunk
371 * needs to be updated accordingly.
372 */
373 if (DWC3_DEPCMD_CMD(cmd) == DWC3_DEPCMD_UPDATETRANSFER &&
374 !usb_endpoint_xfer_isoc(desc))
375 cmd &= ~(DWC3_DEPCMD_CMDIOC | DWC3_DEPCMD_CMDACT);
376 else
377 cmd |= DWC3_DEPCMD_CMDACT;
378
379 dwc3_writel(dep->regs, DWC3_DEPCMD, cmd);
380
381 if (!(cmd & DWC3_DEPCMD_CMDACT) ||
382 (DWC3_DEPCMD_CMD(cmd) == DWC3_DEPCMD_ENDTRANSFER &&
383 !(cmd & DWC3_DEPCMD_CMDIOC))) {
384 ret = 0;
385 goto skip_status;
386 }
387
388 do {
389 reg = dwc3_readl(dep->regs, DWC3_DEPCMD);
390 if (!(reg & DWC3_DEPCMD_CMDACT)) {
391 cmd_status = DWC3_DEPCMD_STATUS(reg);
392
393 switch (cmd_status) {
394 case 0:
395 ret = 0;
396 break;
397 case DEPEVT_TRANSFER_NO_RESOURCE:
398 dev_WARN(dwc->dev, "No resource for %s\n",
399 dep->name);
400 ret = -EINVAL;
401 break;
402 case DEPEVT_TRANSFER_BUS_EXPIRY:
403 /*
404 * SW issues START TRANSFER command to
405 * isochronous ep with future frame interval. If
406 * future interval time has already passed when
407 * core receives the command, it will respond
408 * with an error status of 'Bus Expiry'.
409 *
410 * Instead of always returning -EINVAL, let's
411 * give a hint to the gadget driver that this is
412 * the case by returning -EAGAIN.
413 */
414 ret = -EAGAIN;
415 break;
416 default:
417 dev_WARN(dwc->dev, "UNKNOWN cmd status\n");
418 }
419
420 break;
421 }
422 } while (--timeout);
423
424 if (timeout == 0) {
425 ret = -ETIMEDOUT;
426 cmd_status = -ETIMEDOUT;
427 }
428
429skip_status:
430 trace_dwc3_gadget_ep_cmd(dep, cmd, params, cmd_status);
431
432 if (DWC3_DEPCMD_CMD(cmd) == DWC3_DEPCMD_STARTTRANSFER) {
433 if (ret == 0)
434 dep->flags |= DWC3_EP_TRANSFER_STARTED;
435
436 if (ret != -ETIMEDOUT)
437 dwc3_gadget_ep_get_transfer_index(dep);
438 }
439
440 if (DWC3_DEPCMD_CMD(cmd) == DWC3_DEPCMD_ENDTRANSFER &&
441 !(cmd & DWC3_DEPCMD_CMDIOC))
442 mdelay(1);
443
444 if (saved_config) {
445 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
446 reg |= saved_config;
447 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
448 }
449
450 return ret;
451}
452
453static int dwc3_send_clear_stall_ep_cmd(struct dwc3_ep *dep)
454{
455 struct dwc3 *dwc = dep->dwc;
456 struct dwc3_gadget_ep_cmd_params params;
457 u32 cmd = DWC3_DEPCMD_CLEARSTALL;
458
459 /*
460 * As of core revision 2.60a the recommended programming model
461 * is to set the ClearPendIN bit when issuing a Clear Stall EP
462 * command for IN endpoints. This is to prevent an issue where
463 * some (non-compliant) hosts may not send ACK TPs for pending
464 * IN transfers due to a mishandled error condition. Synopsys
465 * STAR 9000614252.
466 */
467 if (dep->direction &&
468 !DWC3_VER_IS_PRIOR(DWC3, 260A) &&
469 (dwc->gadget->speed >= USB_SPEED_SUPER))
470 cmd |= DWC3_DEPCMD_CLEARPENDIN;
471
472 memset(¶ms, 0, sizeof(params));
473
474 return dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms);
475}
476
477static dma_addr_t dwc3_trb_dma_offset(struct dwc3_ep *dep,
478 struct dwc3_trb *trb)
479{
480 u32 offset = (char *) trb - (char *) dep->trb_pool;
481
482 return dep->trb_pool_dma + offset;
483}
484
485static int dwc3_alloc_trb_pool(struct dwc3_ep *dep)
486{
487 struct dwc3 *dwc = dep->dwc;
488
489 if (dep->trb_pool)
490 return 0;
491
492 dep->trb_pool = dma_alloc_coherent(dwc->sysdev,
493 sizeof(struct dwc3_trb) * DWC3_TRB_NUM,
494 &dep->trb_pool_dma, GFP_KERNEL);
495 if (!dep->trb_pool) {
496 dev_err(dep->dwc->dev, "failed to allocate trb pool for %s\n",
497 dep->name);
498 return -ENOMEM;
499 }
500
501 return 0;
502}
503
504static void dwc3_free_trb_pool(struct dwc3_ep *dep)
505{
506 struct dwc3 *dwc = dep->dwc;
507
508 dma_free_coherent(dwc->sysdev, sizeof(struct dwc3_trb) * DWC3_TRB_NUM,
509 dep->trb_pool, dep->trb_pool_dma);
510
511 dep->trb_pool = NULL;
512 dep->trb_pool_dma = 0;
513}
514
515static int dwc3_gadget_set_xfer_resource(struct dwc3_ep *dep)
516{
517 struct dwc3_gadget_ep_cmd_params params;
518 int ret;
519
520 if (dep->flags & DWC3_EP_RESOURCE_ALLOCATED)
521 return 0;
522
523 memset(¶ms, 0x00, sizeof(params));
524
525 params.param0 = DWC3_DEPXFERCFG_NUM_XFER_RES(1);
526
527 ret = dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_SETTRANSFRESOURCE,
528 ¶ms);
529 if (ret)
530 return ret;
531
532 dep->flags |= DWC3_EP_RESOURCE_ALLOCATED;
533 return 0;
534}
535
536/**
537 * dwc3_gadget_start_config - reset endpoint resources
538 * @dwc: pointer to the DWC3 context
539 * @resource_index: DEPSTARTCFG.XferRscIdx value (must be 0 or 2)
540 *
541 * Set resource_index=0 to reset all endpoints' resources allocation. Do this as
542 * part of the power-on/soft-reset initialization.
543 *
544 * Set resource_index=2 to reset only non-control endpoints' resources. Do this
545 * on receiving the SET_CONFIGURATION request or hibernation resume.
546 */
547int dwc3_gadget_start_config(struct dwc3 *dwc, unsigned int resource_index)
548{
549 struct dwc3_gadget_ep_cmd_params params;
550 u32 cmd;
551 int i;
552 int ret;
553
554 if (resource_index != 0 && resource_index != 2)
555 return -EINVAL;
556
557 memset(¶ms, 0x00, sizeof(params));
558 cmd = DWC3_DEPCMD_DEPSTARTCFG;
559 cmd |= DWC3_DEPCMD_PARAM(resource_index);
560
561 ret = dwc3_send_gadget_ep_cmd(dwc->eps[0], cmd, ¶ms);
562 if (ret)
563 return ret;
564
565 /* Reset resource allocation flags */
566 for (i = resource_index; i < dwc->num_eps && dwc->eps[i]; i++)
567 dwc->eps[i]->flags &= ~DWC3_EP_RESOURCE_ALLOCATED;
568
569 return 0;
570}
571
572static int dwc3_gadget_set_ep_config(struct dwc3_ep *dep, unsigned int action)
573{
574 const struct usb_ss_ep_comp_descriptor *comp_desc;
575 const struct usb_endpoint_descriptor *desc;
576 struct dwc3_gadget_ep_cmd_params params;
577 struct dwc3 *dwc = dep->dwc;
578
579 comp_desc = dep->endpoint.comp_desc;
580 desc = dep->endpoint.desc;
581
582 memset(¶ms, 0x00, sizeof(params));
583
584 params.param0 = DWC3_DEPCFG_EP_TYPE(usb_endpoint_type(desc))
585 | DWC3_DEPCFG_MAX_PACKET_SIZE(usb_endpoint_maxp(desc));
586
587 /* Burst size is only needed in SuperSpeed mode */
588 if (dwc->gadget->speed >= USB_SPEED_SUPER) {
589 u32 burst = dep->endpoint.maxburst;
590
591 params.param0 |= DWC3_DEPCFG_BURST_SIZE(burst - 1);
592 }
593
594 params.param0 |= action;
595 if (action == DWC3_DEPCFG_ACTION_RESTORE)
596 params.param2 |= dep->saved_state;
597
598 if (usb_endpoint_xfer_control(desc))
599 params.param1 = DWC3_DEPCFG_XFER_COMPLETE_EN;
600
601 if (dep->number <= 1 || usb_endpoint_xfer_isoc(desc))
602 params.param1 |= DWC3_DEPCFG_XFER_NOT_READY_EN;
603
604 if (usb_ss_max_streams(comp_desc) && usb_endpoint_xfer_bulk(desc)) {
605 params.param1 |= DWC3_DEPCFG_STREAM_CAPABLE
606 | DWC3_DEPCFG_XFER_COMPLETE_EN
607 | DWC3_DEPCFG_STREAM_EVENT_EN;
608 dep->stream_capable = true;
609 }
610
611 if (!usb_endpoint_xfer_control(desc))
612 params.param1 |= DWC3_DEPCFG_XFER_IN_PROGRESS_EN;
613
614 /*
615 * We are doing 1:1 mapping for endpoints, meaning
616 * Physical Endpoints 2 maps to Logical Endpoint 2 and
617 * so on. We consider the direction bit as part of the physical
618 * endpoint number. So USB endpoint 0x81 is 0x03.
619 */
620 params.param1 |= DWC3_DEPCFG_EP_NUMBER(dep->number);
621
622 /*
623 * We must use the lower 16 TX FIFOs even though
624 * HW might have more
625 */
626 if (dep->direction)
627 params.param0 |= DWC3_DEPCFG_FIFO_NUMBER(dep->number >> 1);
628
629 if (desc->bInterval) {
630 u8 bInterval_m1;
631
632 /*
633 * Valid range for DEPCFG.bInterval_m1 is from 0 to 13.
634 *
635 * NOTE: The programming guide incorrectly stated bInterval_m1
636 * must be set to 0 when operating in fullspeed. Internally the
637 * controller does not have this limitation. See DWC_usb3x
638 * programming guide section 3.2.2.1.
639 */
640 bInterval_m1 = min_t(u8, desc->bInterval - 1, 13);
641
642 if (usb_endpoint_type(desc) == USB_ENDPOINT_XFER_INT &&
643 dwc->gadget->speed == USB_SPEED_FULL)
644 dep->interval = desc->bInterval;
645 else
646 dep->interval = 1 << (desc->bInterval - 1);
647
648 params.param1 |= DWC3_DEPCFG_BINTERVAL_M1(bInterval_m1);
649 }
650
651 return dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_SETEPCONFIG, ¶ms);
652}
653
654/**
655 * dwc3_gadget_calc_tx_fifo_size - calculates the txfifo size value
656 * @dwc: pointer to the DWC3 context
657 * @mult: multiplier to be used when calculating the fifo_size
658 *
659 * Calculates the size value based on the equation below:
660 *
661 * DWC3 revision 280A and prior:
662 * fifo_size = mult * (max_packet / mdwidth) + 1;
663 *
664 * DWC3 revision 290A and onwards:
665 * fifo_size = mult * ((max_packet + mdwidth)/mdwidth + 1) + 1
666 *
667 * The max packet size is set to 1024, as the txfifo requirements mainly apply
668 * to super speed USB use cases. However, it is safe to overestimate the fifo
669 * allocations for other scenarios, i.e. high speed USB.
670 */
671static int dwc3_gadget_calc_tx_fifo_size(struct dwc3 *dwc, int mult)
672{
673 int max_packet = 1024;
674 int fifo_size;
675 int mdwidth;
676
677 mdwidth = dwc3_mdwidth(dwc);
678
679 /* MDWIDTH is represented in bits, we need it in bytes */
680 mdwidth >>= 3;
681
682 if (DWC3_VER_IS_PRIOR(DWC3, 290A))
683 fifo_size = mult * (max_packet / mdwidth) + 1;
684 else
685 fifo_size = mult * ((max_packet + mdwidth) / mdwidth) + 1;
686 return fifo_size;
687}
688
689/**
690 * dwc3_gadget_calc_ram_depth - calculates the ram depth for txfifo
691 * @dwc: pointer to the DWC3 context
692 */
693static int dwc3_gadget_calc_ram_depth(struct dwc3 *dwc)
694{
695 int ram_depth;
696 int fifo_0_start;
697 bool is_single_port_ram;
698
699 /* Check supporting RAM type by HW */
700 is_single_port_ram = DWC3_SPRAM_TYPE(dwc->hwparams.hwparams1);
701
702 /*
703 * If a single port RAM is utilized, then allocate TxFIFOs from
704 * RAM0. otherwise, allocate them from RAM1.
705 */
706 ram_depth = is_single_port_ram ? DWC3_RAM0_DEPTH(dwc->hwparams.hwparams6) :
707 DWC3_RAM1_DEPTH(dwc->hwparams.hwparams7);
708
709 /*
710 * In a single port RAM configuration, the available RAM is shared
711 * between the RX and TX FIFOs. This means that the txfifo can begin
712 * at a non-zero address.
713 */
714 if (is_single_port_ram) {
715 u32 reg;
716
717 /* Check if TXFIFOs start at non-zero addr */
718 reg = dwc3_readl(dwc->regs, DWC3_GTXFIFOSIZ(0));
719 fifo_0_start = DWC3_GTXFIFOSIZ_TXFSTADDR(reg);
720
721 ram_depth -= (fifo_0_start >> 16);
722 }
723
724 return ram_depth;
725}
726
727/**
728 * dwc3_gadget_clear_tx_fifos - Clears txfifo allocation
729 * @dwc: pointer to the DWC3 context
730 *
731 * Iterates through all the endpoint registers and clears the previous txfifo
732 * allocations.
733 */
734void dwc3_gadget_clear_tx_fifos(struct dwc3 *dwc)
735{
736 struct dwc3_ep *dep;
737 int fifo_depth;
738 int size;
739 int num;
740
741 if (!dwc->do_fifo_resize)
742 return;
743
744 /* Read ep0IN related TXFIFO size */
745 dep = dwc->eps[1];
746 size = dwc3_readl(dwc->regs, DWC3_GTXFIFOSIZ(0));
747 if (DWC3_IP_IS(DWC3))
748 fifo_depth = DWC3_GTXFIFOSIZ_TXFDEP(size);
749 else
750 fifo_depth = DWC31_GTXFIFOSIZ_TXFDEP(size);
751
752 dwc->last_fifo_depth = fifo_depth;
753 /* Clear existing TXFIFO for all IN eps except ep0 */
754 for (num = 3; num < min_t(int, dwc->num_eps, DWC3_ENDPOINTS_NUM);
755 num += 2) {
756 dep = dwc->eps[num];
757 /* Don't change TXFRAMNUM on usb31 version */
758 size = DWC3_IP_IS(DWC3) ? 0 :
759 dwc3_readl(dwc->regs, DWC3_GTXFIFOSIZ(num >> 1)) &
760 DWC31_GTXFIFOSIZ_TXFRAMNUM;
761
762 dwc3_writel(dwc->regs, DWC3_GTXFIFOSIZ(num >> 1), size);
763 dep->flags &= ~DWC3_EP_TXFIFO_RESIZED;
764 }
765 dwc->num_ep_resized = 0;
766}
767
768/*
769 * dwc3_gadget_resize_tx_fifos - reallocate fifo spaces for current use-case
770 * @dwc: pointer to our context structure
771 *
772 * This function will a best effort FIFO allocation in order
773 * to improve FIFO usage and throughput, while still allowing
774 * us to enable as many endpoints as possible.
775 *
776 * Keep in mind that this operation will be highly dependent
777 * on the configured size for RAM1 - which contains TxFifo -,
778 * the amount of endpoints enabled on coreConsultant tool, and
779 * the width of the Master Bus.
780 *
781 * In general, FIFO depths are represented with the following equation:
782 *
783 * fifo_size = mult * ((max_packet + mdwidth)/mdwidth + 1) + 1
784 *
785 * In conjunction with dwc3_gadget_check_config(), this resizing logic will
786 * ensure that all endpoints will have enough internal memory for one max
787 * packet per endpoint.
788 */
789static int dwc3_gadget_resize_tx_fifos(struct dwc3_ep *dep)
790{
791 struct dwc3 *dwc = dep->dwc;
792 int fifo_0_start;
793 int ram_depth;
794 int fifo_size;
795 int min_depth;
796 int num_in_ep;
797 int remaining;
798 int num_fifos = 1;
799 int fifo;
800 int tmp;
801
802 if (!dwc->do_fifo_resize)
803 return 0;
804
805 /* resize IN endpoints except ep0 */
806 if (!usb_endpoint_dir_in(dep->endpoint.desc) || dep->number <= 1)
807 return 0;
808
809 /* bail if already resized */
810 if (dep->flags & DWC3_EP_TXFIFO_RESIZED)
811 return 0;
812
813 ram_depth = dwc3_gadget_calc_ram_depth(dwc);
814
815 switch (dwc->gadget->speed) {
816 case USB_SPEED_SUPER_PLUS:
817 case USB_SPEED_SUPER:
818 if (usb_endpoint_xfer_bulk(dep->endpoint.desc) ||
819 usb_endpoint_xfer_isoc(dep->endpoint.desc))
820 num_fifos = min_t(unsigned int,
821 dep->endpoint.maxburst,
822 dwc->tx_fifo_resize_max_num);
823 break;
824 case USB_SPEED_HIGH:
825 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
826 num_fifos = min_t(unsigned int,
827 usb_endpoint_maxp_mult(dep->endpoint.desc) + 1,
828 dwc->tx_fifo_resize_max_num);
829 break;
830 }
831 fallthrough;
832 case USB_SPEED_FULL:
833 if (usb_endpoint_xfer_bulk(dep->endpoint.desc))
834 num_fifos = 2;
835 break;
836 default:
837 break;
838 }
839
840 /* FIFO size for a single buffer */
841 fifo = dwc3_gadget_calc_tx_fifo_size(dwc, 1);
842
843 /* Calculate the number of remaining EPs w/o any FIFO */
844 num_in_ep = dwc->max_cfg_eps;
845 num_in_ep -= dwc->num_ep_resized;
846
847 /* Reserve at least one FIFO for the number of IN EPs */
848 min_depth = num_in_ep * (fifo + 1);
849 remaining = ram_depth - min_depth - dwc->last_fifo_depth;
850 remaining = max_t(int, 0, remaining);
851 /*
852 * We've already reserved 1 FIFO per EP, so check what we can fit in
853 * addition to it. If there is not enough remaining space, allocate
854 * all the remaining space to the EP.
855 */
856 fifo_size = (num_fifos - 1) * fifo;
857 if (remaining < fifo_size)
858 fifo_size = remaining;
859
860 fifo_size += fifo;
861 /* Last increment according to the TX FIFO size equation */
862 fifo_size++;
863
864 /* Check if TXFIFOs start at non-zero addr */
865 tmp = dwc3_readl(dwc->regs, DWC3_GTXFIFOSIZ(0));
866 fifo_0_start = DWC3_GTXFIFOSIZ_TXFSTADDR(tmp);
867
868 fifo_size |= (fifo_0_start + (dwc->last_fifo_depth << 16));
869 if (DWC3_IP_IS(DWC3))
870 dwc->last_fifo_depth += DWC3_GTXFIFOSIZ_TXFDEP(fifo_size);
871 else
872 dwc->last_fifo_depth += DWC31_GTXFIFOSIZ_TXFDEP(fifo_size);
873
874 /* Check fifo size allocation doesn't exceed available RAM size. */
875 if (dwc->last_fifo_depth >= ram_depth) {
876 dev_err(dwc->dev, "Fifosize(%d) > RAM size(%d) %s depth:%d\n",
877 dwc->last_fifo_depth, ram_depth,
878 dep->endpoint.name, fifo_size);
879 if (DWC3_IP_IS(DWC3))
880 fifo_size = DWC3_GTXFIFOSIZ_TXFDEP(fifo_size);
881 else
882 fifo_size = DWC31_GTXFIFOSIZ_TXFDEP(fifo_size);
883
884 dwc->last_fifo_depth -= fifo_size;
885 return -ENOMEM;
886 }
887
888 dwc3_writel(dwc->regs, DWC3_GTXFIFOSIZ(dep->number >> 1), fifo_size);
889 dep->flags |= DWC3_EP_TXFIFO_RESIZED;
890 dwc->num_ep_resized++;
891
892 return 0;
893}
894
895/**
896 * __dwc3_gadget_ep_enable - initializes a hw endpoint
897 * @dep: endpoint to be initialized
898 * @action: one of INIT, MODIFY or RESTORE
899 *
900 * Caller should take care of locking. Execute all necessary commands to
901 * initialize a HW endpoint so it can be used by a gadget driver.
902 */
903static int __dwc3_gadget_ep_enable(struct dwc3_ep *dep, unsigned int action)
904{
905 const struct usb_endpoint_descriptor *desc = dep->endpoint.desc;
906 struct dwc3 *dwc = dep->dwc;
907
908 u32 reg;
909 int ret;
910
911 if (!(dep->flags & DWC3_EP_ENABLED)) {
912 ret = dwc3_gadget_resize_tx_fifos(dep);
913 if (ret)
914 return ret;
915 }
916
917 ret = dwc3_gadget_set_ep_config(dep, action);
918 if (ret)
919 return ret;
920
921 if (!(dep->flags & DWC3_EP_RESOURCE_ALLOCATED)) {
922 ret = dwc3_gadget_set_xfer_resource(dep);
923 if (ret)
924 return ret;
925 }
926
927 if (!(dep->flags & DWC3_EP_ENABLED)) {
928 struct dwc3_trb *trb_st_hw;
929 struct dwc3_trb *trb_link;
930
931 dep->type = usb_endpoint_type(desc);
932 dep->flags |= DWC3_EP_ENABLED;
933
934 reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
935 reg |= DWC3_DALEPENA_EP(dep->number);
936 dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
937
938 dep->trb_dequeue = 0;
939 dep->trb_enqueue = 0;
940
941 if (usb_endpoint_xfer_control(desc))
942 goto out;
943
944 /* Initialize the TRB ring */
945 memset(dep->trb_pool, 0,
946 sizeof(struct dwc3_trb) * DWC3_TRB_NUM);
947
948 /* Link TRB. The HWO bit is never reset */
949 trb_st_hw = &dep->trb_pool[0];
950
951 trb_link = &dep->trb_pool[DWC3_TRB_NUM - 1];
952 trb_link->bpl = lower_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw));
953 trb_link->bph = upper_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw));
954 trb_link->ctrl |= DWC3_TRBCTL_LINK_TRB;
955 trb_link->ctrl |= DWC3_TRB_CTRL_HWO;
956 }
957
958 /*
959 * Issue StartTransfer here with no-op TRB so we can always rely on No
960 * Response Update Transfer command.
961 */
962 if (usb_endpoint_xfer_bulk(desc) ||
963 usb_endpoint_xfer_int(desc)) {
964 struct dwc3_gadget_ep_cmd_params params;
965 struct dwc3_trb *trb;
966 dma_addr_t trb_dma;
967 u32 cmd;
968
969 memset(¶ms, 0, sizeof(params));
970 trb = &dep->trb_pool[0];
971 trb_dma = dwc3_trb_dma_offset(dep, trb);
972
973 params.param0 = upper_32_bits(trb_dma);
974 params.param1 = lower_32_bits(trb_dma);
975
976 cmd = DWC3_DEPCMD_STARTTRANSFER;
977
978 ret = dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms);
979 if (ret < 0)
980 return ret;
981
982 if (dep->stream_capable) {
983 /*
984 * For streams, at start, there maybe a race where the
985 * host primes the endpoint before the function driver
986 * queues a request to initiate a stream. In that case,
987 * the controller will not see the prime to generate the
988 * ERDY and start stream. To workaround this, issue a
989 * no-op TRB as normal, but end it immediately. As a
990 * result, when the function driver queues the request,
991 * the next START_TRANSFER command will cause the
992 * controller to generate an ERDY to initiate the
993 * stream.
994 */
995 dwc3_stop_active_transfer(dep, true, true);
996
997 /*
998 * All stream eps will reinitiate stream on NoStream
999 * rejection until we can determine that the host can
1000 * prime after the first transfer.
1001 *
1002 * However, if the controller is capable of
1003 * TXF_FLUSH_BYPASS, then IN direction endpoints will
1004 * automatically restart the stream without the driver
1005 * initiation.
1006 */
1007 if (!dep->direction ||
1008 !(dwc->hwparams.hwparams9 &
1009 DWC3_GHWPARAMS9_DEV_TXF_FLUSH_BYPASS))
1010 dep->flags |= DWC3_EP_FORCE_RESTART_STREAM;
1011 }
1012 }
1013
1014out:
1015 trace_dwc3_gadget_ep_enable(dep);
1016
1017 return 0;
1018}
1019
1020void dwc3_remove_requests(struct dwc3 *dwc, struct dwc3_ep *dep, int status)
1021{
1022 struct dwc3_request *req;
1023
1024 dwc3_stop_active_transfer(dep, true, false);
1025
1026 /* If endxfer is delayed, avoid unmapping requests */
1027 if (dep->flags & DWC3_EP_DELAY_STOP)
1028 return;
1029
1030 /* - giveback all requests to gadget driver */
1031 while (!list_empty(&dep->started_list)) {
1032 req = next_request(&dep->started_list);
1033
1034 dwc3_gadget_giveback(dep, req, status);
1035 }
1036
1037 while (!list_empty(&dep->pending_list)) {
1038 req = next_request(&dep->pending_list);
1039
1040 dwc3_gadget_giveback(dep, req, status);
1041 }
1042
1043 while (!list_empty(&dep->cancelled_list)) {
1044 req = next_request(&dep->cancelled_list);
1045
1046 dwc3_gadget_giveback(dep, req, status);
1047 }
1048}
1049
1050/**
1051 * __dwc3_gadget_ep_disable - disables a hw endpoint
1052 * @dep: the endpoint to disable
1053 *
1054 * This function undoes what __dwc3_gadget_ep_enable did and also removes
1055 * requests which are currently being processed by the hardware and those which
1056 * are not yet scheduled.
1057 *
1058 * Caller should take care of locking.
1059 */
1060static int __dwc3_gadget_ep_disable(struct dwc3_ep *dep)
1061{
1062 struct dwc3 *dwc = dep->dwc;
1063 u32 reg;
1064 u32 mask;
1065
1066 trace_dwc3_gadget_ep_disable(dep);
1067
1068 /* make sure HW endpoint isn't stalled */
1069 if (dep->flags & DWC3_EP_STALL)
1070 __dwc3_gadget_ep_set_halt(dep, 0, false);
1071
1072 reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
1073 reg &= ~DWC3_DALEPENA_EP(dep->number);
1074 dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
1075
1076 dwc3_remove_requests(dwc, dep, -ESHUTDOWN);
1077
1078 dep->stream_capable = false;
1079 dep->type = 0;
1080 mask = DWC3_EP_TXFIFO_RESIZED | DWC3_EP_RESOURCE_ALLOCATED;
1081 /*
1082 * dwc3_remove_requests() can exit early if DWC3 EP delayed stop is
1083 * set. Do not clear DEP flags, so that the end transfer command will
1084 * be reattempted during the next SETUP stage.
1085 */
1086 if (dep->flags & DWC3_EP_DELAY_STOP)
1087 mask |= (DWC3_EP_DELAY_STOP | DWC3_EP_TRANSFER_STARTED);
1088 dep->flags &= mask;
1089
1090 /* Clear out the ep descriptors for non-ep0 */
1091 if (dep->number > 1) {
1092 dep->endpoint.comp_desc = NULL;
1093 dep->endpoint.desc = NULL;
1094 }
1095
1096 return 0;
1097}
1098
1099/* -------------------------------------------------------------------------- */
1100
1101static int dwc3_gadget_ep0_enable(struct usb_ep *ep,
1102 const struct usb_endpoint_descriptor *desc)
1103{
1104 return -EINVAL;
1105}
1106
1107static int dwc3_gadget_ep0_disable(struct usb_ep *ep)
1108{
1109 return -EINVAL;
1110}
1111
1112/* -------------------------------------------------------------------------- */
1113
1114static int dwc3_gadget_ep_enable(struct usb_ep *ep,
1115 const struct usb_endpoint_descriptor *desc)
1116{
1117 struct dwc3_ep *dep;
1118 struct dwc3 *dwc;
1119 unsigned long flags;
1120 int ret;
1121
1122 if (!ep || !desc || desc->bDescriptorType != USB_DT_ENDPOINT) {
1123 pr_debug("dwc3: invalid parameters\n");
1124 return -EINVAL;
1125 }
1126
1127 if (!desc->wMaxPacketSize) {
1128 pr_debug("dwc3: missing wMaxPacketSize\n");
1129 return -EINVAL;
1130 }
1131
1132 dep = to_dwc3_ep(ep);
1133 dwc = dep->dwc;
1134
1135 if (dev_WARN_ONCE(dwc->dev, dep->flags & DWC3_EP_ENABLED,
1136 "%s is already enabled\n",
1137 dep->name))
1138 return 0;
1139
1140 spin_lock_irqsave(&dwc->lock, flags);
1141 ret = __dwc3_gadget_ep_enable(dep, DWC3_DEPCFG_ACTION_INIT);
1142 spin_unlock_irqrestore(&dwc->lock, flags);
1143
1144 return ret;
1145}
1146
1147static int dwc3_gadget_ep_disable(struct usb_ep *ep)
1148{
1149 struct dwc3_ep *dep;
1150 struct dwc3 *dwc;
1151 unsigned long flags;
1152 int ret;
1153
1154 if (!ep) {
1155 pr_debug("dwc3: invalid parameters\n");
1156 return -EINVAL;
1157 }
1158
1159 dep = to_dwc3_ep(ep);
1160 dwc = dep->dwc;
1161
1162 if (dev_WARN_ONCE(dwc->dev, !(dep->flags & DWC3_EP_ENABLED),
1163 "%s is already disabled\n",
1164 dep->name))
1165 return 0;
1166
1167 spin_lock_irqsave(&dwc->lock, flags);
1168 ret = __dwc3_gadget_ep_disable(dep);
1169 spin_unlock_irqrestore(&dwc->lock, flags);
1170
1171 return ret;
1172}
1173
1174static struct usb_request *dwc3_gadget_ep_alloc_request(struct usb_ep *ep,
1175 gfp_t gfp_flags)
1176{
1177 struct dwc3_request *req;
1178 struct dwc3_ep *dep = to_dwc3_ep(ep);
1179
1180 req = kzalloc(sizeof(*req), gfp_flags);
1181 if (!req)
1182 return NULL;
1183
1184 req->direction = dep->direction;
1185 req->epnum = dep->number;
1186 req->dep = dep;
1187 req->status = DWC3_REQUEST_STATUS_UNKNOWN;
1188
1189 trace_dwc3_alloc_request(req);
1190
1191 return &req->request;
1192}
1193
1194static void dwc3_gadget_ep_free_request(struct usb_ep *ep,
1195 struct usb_request *request)
1196{
1197 struct dwc3_request *req = to_dwc3_request(request);
1198
1199 trace_dwc3_free_request(req);
1200 kfree(req);
1201}
1202
1203/**
1204 * dwc3_ep_prev_trb - returns the previous TRB in the ring
1205 * @dep: The endpoint with the TRB ring
1206 * @index: The index of the current TRB in the ring
1207 *
1208 * Returns the TRB prior to the one pointed to by the index. If the
1209 * index is 0, we will wrap backwards, skip the link TRB, and return
1210 * the one just before that.
1211 */
1212static struct dwc3_trb *dwc3_ep_prev_trb(struct dwc3_ep *dep, u8 index)
1213{
1214 u8 tmp = index;
1215
1216 if (!tmp)
1217 tmp = DWC3_TRB_NUM - 1;
1218
1219 return &dep->trb_pool[tmp - 1];
1220}
1221
1222static u32 dwc3_calc_trbs_left(struct dwc3_ep *dep)
1223{
1224 u8 trbs_left;
1225
1226 /*
1227 * If the enqueue & dequeue are equal then the TRB ring is either full
1228 * or empty. It's considered full when there are DWC3_TRB_NUM-1 of TRBs
1229 * pending to be processed by the driver.
1230 */
1231 if (dep->trb_enqueue == dep->trb_dequeue) {
1232 struct dwc3_request *req;
1233
1234 /*
1235 * If there is any request remained in the started_list with
1236 * active TRBs at this point, then there is no TRB available.
1237 */
1238 req = next_request(&dep->started_list);
1239 if (req && req->num_trbs)
1240 return 0;
1241
1242 return DWC3_TRB_NUM - 1;
1243 }
1244
1245 trbs_left = dep->trb_dequeue - dep->trb_enqueue;
1246 trbs_left &= (DWC3_TRB_NUM - 1);
1247
1248 if (dep->trb_dequeue < dep->trb_enqueue)
1249 trbs_left--;
1250
1251 return trbs_left;
1252}
1253
1254/**
1255 * dwc3_prepare_one_trb - setup one TRB from one request
1256 * @dep: endpoint for which this request is prepared
1257 * @req: dwc3_request pointer
1258 * @trb_length: buffer size of the TRB
1259 * @chain: should this TRB be chained to the next?
1260 * @node: only for isochronous endpoints. First TRB needs different type.
1261 * @use_bounce_buffer: set to use bounce buffer
1262 * @must_interrupt: set to interrupt on TRB completion
1263 */
1264static void dwc3_prepare_one_trb(struct dwc3_ep *dep,
1265 struct dwc3_request *req, unsigned int trb_length,
1266 unsigned int chain, unsigned int node, bool use_bounce_buffer,
1267 bool must_interrupt)
1268{
1269 struct dwc3_trb *trb;
1270 dma_addr_t dma;
1271 unsigned int stream_id = req->request.stream_id;
1272 unsigned int short_not_ok = req->request.short_not_ok;
1273 unsigned int no_interrupt = req->request.no_interrupt;
1274 unsigned int is_last = req->request.is_last;
1275 struct dwc3 *dwc = dep->dwc;
1276 struct usb_gadget *gadget = dwc->gadget;
1277 enum usb_device_speed speed = gadget->speed;
1278
1279 if (use_bounce_buffer)
1280 dma = dep->dwc->bounce_addr;
1281 else if (req->request.num_sgs > 0)
1282 dma = sg_dma_address(req->start_sg);
1283 else
1284 dma = req->request.dma;
1285
1286 trb = &dep->trb_pool[dep->trb_enqueue];
1287
1288 if (!req->trb) {
1289 dwc3_gadget_move_started_request(req);
1290 req->trb = trb;
1291 req->trb_dma = dwc3_trb_dma_offset(dep, trb);
1292 }
1293
1294 req->num_trbs++;
1295
1296 trb->size = DWC3_TRB_SIZE_LENGTH(trb_length);
1297 trb->bpl = lower_32_bits(dma);
1298 trb->bph = upper_32_bits(dma);
1299
1300 switch (usb_endpoint_type(dep->endpoint.desc)) {
1301 case USB_ENDPOINT_XFER_CONTROL:
1302 trb->ctrl = DWC3_TRBCTL_CONTROL_SETUP;
1303 break;
1304
1305 case USB_ENDPOINT_XFER_ISOC:
1306 if (!node) {
1307 trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS_FIRST;
1308
1309 /*
1310 * USB Specification 2.0 Section 5.9.2 states that: "If
1311 * there is only a single transaction in the microframe,
1312 * only a DATA0 data packet PID is used. If there are
1313 * two transactions per microframe, DATA1 is used for
1314 * the first transaction data packet and DATA0 is used
1315 * for the second transaction data packet. If there are
1316 * three transactions per microframe, DATA2 is used for
1317 * the first transaction data packet, DATA1 is used for
1318 * the second, and DATA0 is used for the third."
1319 *
1320 * IOW, we should satisfy the following cases:
1321 *
1322 * 1) length <= maxpacket
1323 * - DATA0
1324 *
1325 * 2) maxpacket < length <= (2 * maxpacket)
1326 * - DATA1, DATA0
1327 *
1328 * 3) (2 * maxpacket) < length <= (3 * maxpacket)
1329 * - DATA2, DATA1, DATA0
1330 */
1331 if (speed == USB_SPEED_HIGH) {
1332 struct usb_ep *ep = &dep->endpoint;
1333 unsigned int mult = 2;
1334 unsigned int maxp = usb_endpoint_maxp(ep->desc);
1335
1336 if (req->request.length <= (2 * maxp))
1337 mult--;
1338
1339 if (req->request.length <= maxp)
1340 mult--;
1341
1342 trb->size |= DWC3_TRB_SIZE_PCM1(mult);
1343 }
1344 } else {
1345 trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS;
1346 }
1347
1348 if (!no_interrupt && !chain)
1349 trb->ctrl |= DWC3_TRB_CTRL_ISP_IMI;
1350 break;
1351
1352 case USB_ENDPOINT_XFER_BULK:
1353 case USB_ENDPOINT_XFER_INT:
1354 trb->ctrl = DWC3_TRBCTL_NORMAL;
1355 break;
1356 default:
1357 /*
1358 * This is only possible with faulty memory because we
1359 * checked it already :)
1360 */
1361 dev_WARN(dwc->dev, "Unknown endpoint type %d\n",
1362 usb_endpoint_type(dep->endpoint.desc));
1363 }
1364
1365 /*
1366 * Enable Continue on Short Packet
1367 * when endpoint is not a stream capable
1368 */
1369 if (usb_endpoint_dir_out(dep->endpoint.desc)) {
1370 if (!dep->stream_capable)
1371 trb->ctrl |= DWC3_TRB_CTRL_CSP;
1372
1373 if (short_not_ok)
1374 trb->ctrl |= DWC3_TRB_CTRL_ISP_IMI;
1375 }
1376
1377 /* All TRBs setup for MST must set CSP=1 when LST=0 */
1378 if (dep->stream_capable && DWC3_MST_CAPABLE(&dwc->hwparams))
1379 trb->ctrl |= DWC3_TRB_CTRL_CSP;
1380
1381 if ((!no_interrupt && !chain) || must_interrupt)
1382 trb->ctrl |= DWC3_TRB_CTRL_IOC;
1383
1384 if (chain)
1385 trb->ctrl |= DWC3_TRB_CTRL_CHN;
1386 else if (dep->stream_capable && is_last &&
1387 !DWC3_MST_CAPABLE(&dwc->hwparams))
1388 trb->ctrl |= DWC3_TRB_CTRL_LST;
1389
1390 if (usb_endpoint_xfer_bulk(dep->endpoint.desc) && dep->stream_capable)
1391 trb->ctrl |= DWC3_TRB_CTRL_SID_SOFN(stream_id);
1392
1393 /*
1394 * As per data book 4.2.3.2TRB Control Bit Rules section
1395 *
1396 * The controller autonomously checks the HWO field of a TRB to determine if the
1397 * entire TRB is valid. Therefore, software must ensure that the rest of the TRB
1398 * is valid before setting the HWO field to '1'. In most systems, this means that
1399 * software must update the fourth DWORD of a TRB last.
1400 *
1401 * However there is a possibility of CPU re-ordering here which can cause
1402 * controller to observe the HWO bit set prematurely.
1403 * Add a write memory barrier to prevent CPU re-ordering.
1404 */
1405 wmb();
1406 trb->ctrl |= DWC3_TRB_CTRL_HWO;
1407
1408 dwc3_ep_inc_enq(dep);
1409
1410 trace_dwc3_prepare_trb(dep, trb);
1411}
1412
1413static bool dwc3_needs_extra_trb(struct dwc3_ep *dep, struct dwc3_request *req)
1414{
1415 unsigned int maxp = usb_endpoint_maxp(dep->endpoint.desc);
1416 unsigned int rem = req->request.length % maxp;
1417
1418 if ((req->request.length && req->request.zero && !rem &&
1419 !usb_endpoint_xfer_isoc(dep->endpoint.desc)) ||
1420 (!req->direction && rem))
1421 return true;
1422
1423 return false;
1424}
1425
1426/**
1427 * dwc3_prepare_last_sg - prepare TRBs for the last SG entry
1428 * @dep: The endpoint that the request belongs to
1429 * @req: The request to prepare
1430 * @entry_length: The last SG entry size
1431 * @node: Indicates whether this is not the first entry (for isoc only)
1432 *
1433 * Return the number of TRBs prepared.
1434 */
1435static int dwc3_prepare_last_sg(struct dwc3_ep *dep,
1436 struct dwc3_request *req, unsigned int entry_length,
1437 unsigned int node)
1438{
1439 unsigned int maxp = usb_endpoint_maxp(dep->endpoint.desc);
1440 unsigned int rem = req->request.length % maxp;
1441 unsigned int num_trbs = 1;
1442 bool needs_extra_trb;
1443
1444 if (dwc3_needs_extra_trb(dep, req))
1445 num_trbs++;
1446
1447 if (dwc3_calc_trbs_left(dep) < num_trbs)
1448 return 0;
1449
1450 needs_extra_trb = num_trbs > 1;
1451
1452 /* Prepare a normal TRB */
1453 if (req->direction || req->request.length)
1454 dwc3_prepare_one_trb(dep, req, entry_length,
1455 needs_extra_trb, node, false, false);
1456
1457 /* Prepare extra TRBs for ZLP and MPS OUT transfer alignment */
1458 if ((!req->direction && !req->request.length) || needs_extra_trb)
1459 dwc3_prepare_one_trb(dep, req,
1460 req->direction ? 0 : maxp - rem,
1461 false, 1, true, false);
1462
1463 return num_trbs;
1464}
1465
1466static int dwc3_prepare_trbs_sg(struct dwc3_ep *dep,
1467 struct dwc3_request *req)
1468{
1469 struct scatterlist *sg = req->start_sg;
1470 struct scatterlist *s;
1471 int i;
1472 unsigned int length = req->request.length;
1473 unsigned int remaining = req->num_pending_sgs;
1474 unsigned int num_queued_sgs = req->request.num_mapped_sgs - remaining;
1475 unsigned int num_trbs = req->num_trbs;
1476 bool needs_extra_trb = dwc3_needs_extra_trb(dep, req);
1477
1478 /*
1479 * If we resume preparing the request, then get the remaining length of
1480 * the request and resume where we left off.
1481 */
1482 for_each_sg(req->request.sg, s, num_queued_sgs, i)
1483 length -= sg_dma_len(s);
1484
1485 for_each_sg(sg, s, remaining, i) {
1486 unsigned int num_trbs_left = dwc3_calc_trbs_left(dep);
1487 unsigned int trb_length;
1488 bool must_interrupt = false;
1489 bool last_sg = false;
1490
1491 trb_length = min_t(unsigned int, length, sg_dma_len(s));
1492
1493 length -= trb_length;
1494
1495 /*
1496 * IOMMU driver is coalescing the list of sgs which shares a
1497 * page boundary into one and giving it to USB driver. With
1498 * this the number of sgs mapped is not equal to the number of
1499 * sgs passed. So mark the chain bit to false if it isthe last
1500 * mapped sg.
1501 */
1502 if ((i == remaining - 1) || !length)
1503 last_sg = true;
1504
1505 if (!num_trbs_left)
1506 break;
1507
1508 if (last_sg) {
1509 if (!dwc3_prepare_last_sg(dep, req, trb_length, i))
1510 break;
1511 } else {
1512 /*
1513 * Look ahead to check if we have enough TRBs for the
1514 * next SG entry. If not, set interrupt on this TRB to
1515 * resume preparing the next SG entry when more TRBs are
1516 * free.
1517 */
1518 if (num_trbs_left == 1 || (needs_extra_trb &&
1519 num_trbs_left <= 2 &&
1520 sg_dma_len(sg_next(s)) >= length)) {
1521 struct dwc3_request *r;
1522
1523 /* Check if previous requests already set IOC */
1524 list_for_each_entry(r, &dep->started_list, list) {
1525 if (r != req && !r->request.no_interrupt)
1526 break;
1527
1528 if (r == req)
1529 must_interrupt = true;
1530 }
1531 }
1532
1533 dwc3_prepare_one_trb(dep, req, trb_length, 1, i, false,
1534 must_interrupt);
1535 }
1536
1537 /*
1538 * There can be a situation where all sgs in sglist are not
1539 * queued because of insufficient trb number. To handle this
1540 * case, update start_sg to next sg to be queued, so that
1541 * we have free trbs we can continue queuing from where we
1542 * previously stopped
1543 */
1544 if (!last_sg)
1545 req->start_sg = sg_next(s);
1546
1547 req->num_pending_sgs--;
1548
1549 /*
1550 * The number of pending SG entries may not correspond to the
1551 * number of mapped SG entries. If all the data are queued, then
1552 * don't include unused SG entries.
1553 */
1554 if (length == 0) {
1555 req->num_pending_sgs = 0;
1556 break;
1557 }
1558
1559 if (must_interrupt)
1560 break;
1561 }
1562
1563 return req->num_trbs - num_trbs;
1564}
1565
1566static int dwc3_prepare_trbs_linear(struct dwc3_ep *dep,
1567 struct dwc3_request *req)
1568{
1569 return dwc3_prepare_last_sg(dep, req, req->request.length, 0);
1570}
1571
1572/*
1573 * dwc3_prepare_trbs - setup TRBs from requests
1574 * @dep: endpoint for which requests are being prepared
1575 *
1576 * The function goes through the requests list and sets up TRBs for the
1577 * transfers. The function returns once there are no more TRBs available or
1578 * it runs out of requests.
1579 *
1580 * Returns the number of TRBs prepared or negative errno.
1581 */
1582static int dwc3_prepare_trbs(struct dwc3_ep *dep)
1583{
1584 struct dwc3_request *req, *n;
1585 int ret = 0;
1586
1587 BUILD_BUG_ON_NOT_POWER_OF_2(DWC3_TRB_NUM);
1588
1589 /*
1590 * We can get in a situation where there's a request in the started list
1591 * but there weren't enough TRBs to fully kick it in the first time
1592 * around, so it has been waiting for more TRBs to be freed up.
1593 *
1594 * In that case, we should check if we have a request with pending_sgs
1595 * in the started list and prepare TRBs for that request first,
1596 * otherwise we will prepare TRBs completely out of order and that will
1597 * break things.
1598 */
1599 list_for_each_entry(req, &dep->started_list, list) {
1600 if (req->num_pending_sgs > 0) {
1601 ret = dwc3_prepare_trbs_sg(dep, req);
1602 if (!ret || req->num_pending_sgs)
1603 return ret;
1604 }
1605
1606 if (!dwc3_calc_trbs_left(dep))
1607 return ret;
1608
1609 /*
1610 * Don't prepare beyond a transfer. In DWC_usb32, its transfer
1611 * burst capability may try to read and use TRBs beyond the
1612 * active transfer instead of stopping.
1613 */
1614 if (dep->stream_capable && req->request.is_last &&
1615 !DWC3_MST_CAPABLE(&dep->dwc->hwparams))
1616 return ret;
1617 }
1618
1619 list_for_each_entry_safe(req, n, &dep->pending_list, list) {
1620 struct dwc3 *dwc = dep->dwc;
1621
1622 ret = usb_gadget_map_request_by_dev(dwc->sysdev, &req->request,
1623 dep->direction);
1624 if (ret)
1625 return ret;
1626
1627 req->start_sg = req->request.sg;
1628 req->num_pending_sgs = req->request.num_mapped_sgs;
1629
1630 if (req->num_pending_sgs > 0) {
1631 ret = dwc3_prepare_trbs_sg(dep, req);
1632 if (req->num_pending_sgs)
1633 return ret;
1634 } else {
1635 ret = dwc3_prepare_trbs_linear(dep, req);
1636 }
1637
1638 if (!ret || !dwc3_calc_trbs_left(dep))
1639 return ret;
1640
1641 /*
1642 * Don't prepare beyond a transfer. In DWC_usb32, its transfer
1643 * burst capability may try to read and use TRBs beyond the
1644 * active transfer instead of stopping.
1645 */
1646 if (dep->stream_capable && req->request.is_last &&
1647 !DWC3_MST_CAPABLE(&dwc->hwparams))
1648 return ret;
1649 }
1650
1651 return ret;
1652}
1653
1654static void dwc3_gadget_ep_cleanup_cancelled_requests(struct dwc3_ep *dep);
1655
1656static int __dwc3_gadget_kick_transfer(struct dwc3_ep *dep)
1657{
1658 struct dwc3_gadget_ep_cmd_params params;
1659 struct dwc3_request *req;
1660 int starting;
1661 int ret;
1662 u32 cmd;
1663
1664 /*
1665 * Note that it's normal to have no new TRBs prepared (i.e. ret == 0).
1666 * This happens when we need to stop and restart a transfer such as in
1667 * the case of reinitiating a stream or retrying an isoc transfer.
1668 */
1669 ret = dwc3_prepare_trbs(dep);
1670 if (ret < 0)
1671 return ret;
1672
1673 starting = !(dep->flags & DWC3_EP_TRANSFER_STARTED);
1674
1675 /*
1676 * If there's no new TRB prepared and we don't need to restart a
1677 * transfer, there's no need to update the transfer.
1678 */
1679 if (!ret && !starting)
1680 return ret;
1681
1682 req = next_request(&dep->started_list);
1683 if (!req) {
1684 dep->flags |= DWC3_EP_PENDING_REQUEST;
1685 return 0;
1686 }
1687
1688 memset(¶ms, 0, sizeof(params));
1689
1690 if (starting) {
1691 params.param0 = upper_32_bits(req->trb_dma);
1692 params.param1 = lower_32_bits(req->trb_dma);
1693 cmd = DWC3_DEPCMD_STARTTRANSFER;
1694
1695 if (dep->stream_capable)
1696 cmd |= DWC3_DEPCMD_PARAM(req->request.stream_id);
1697
1698 if (usb_endpoint_xfer_isoc(dep->endpoint.desc))
1699 cmd |= DWC3_DEPCMD_PARAM(dep->frame_number);
1700 } else {
1701 cmd = DWC3_DEPCMD_UPDATETRANSFER |
1702 DWC3_DEPCMD_PARAM(dep->resource_index);
1703 }
1704
1705 ret = dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms);
1706 if (ret < 0) {
1707 struct dwc3_request *tmp;
1708
1709 if (ret == -EAGAIN)
1710 return ret;
1711
1712 dwc3_stop_active_transfer(dep, true, true);
1713
1714 list_for_each_entry_safe(req, tmp, &dep->started_list, list)
1715 dwc3_gadget_move_cancelled_request(req, DWC3_REQUEST_STATUS_DEQUEUED);
1716
1717 /* If ep isn't started, then there's no end transfer pending */
1718 if (!(dep->flags & DWC3_EP_END_TRANSFER_PENDING))
1719 dwc3_gadget_ep_cleanup_cancelled_requests(dep);
1720
1721 return ret;
1722 }
1723
1724 if (dep->stream_capable && req->request.is_last &&
1725 !DWC3_MST_CAPABLE(&dep->dwc->hwparams))
1726 dep->flags |= DWC3_EP_WAIT_TRANSFER_COMPLETE;
1727
1728 return 0;
1729}
1730
1731static int __dwc3_gadget_get_frame(struct dwc3 *dwc)
1732{
1733 u32 reg;
1734
1735 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1736 return DWC3_DSTS_SOFFN(reg);
1737}
1738
1739/**
1740 * __dwc3_stop_active_transfer - stop the current active transfer
1741 * @dep: isoc endpoint
1742 * @force: set forcerm bit in the command
1743 * @interrupt: command complete interrupt after End Transfer command
1744 *
1745 * When setting force, the ForceRM bit will be set. In that case
1746 * the controller won't update the TRB progress on command
1747 * completion. It also won't clear the HWO bit in the TRB.
1748 * The command will also not complete immediately in that case.
1749 */
1750static int __dwc3_stop_active_transfer(struct dwc3_ep *dep, bool force, bool interrupt)
1751{
1752 struct dwc3_gadget_ep_cmd_params params;
1753 u32 cmd;
1754 int ret;
1755
1756 cmd = DWC3_DEPCMD_ENDTRANSFER;
1757 cmd |= force ? DWC3_DEPCMD_HIPRI_FORCERM : 0;
1758 cmd |= interrupt ? DWC3_DEPCMD_CMDIOC : 0;
1759 cmd |= DWC3_DEPCMD_PARAM(dep->resource_index);
1760 memset(¶ms, 0, sizeof(params));
1761 ret = dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms);
1762 /*
1763 * If the End Transfer command was timed out while the device is
1764 * not in SETUP phase, it's possible that an incoming Setup packet
1765 * may prevent the command's completion. Let's retry when the
1766 * ep0state returns to EP0_SETUP_PHASE.
1767 */
1768 if (ret == -ETIMEDOUT && dep->dwc->ep0state != EP0_SETUP_PHASE) {
1769 dep->flags |= DWC3_EP_DELAY_STOP;
1770 return 0;
1771 }
1772 WARN_ON_ONCE(ret);
1773 dep->resource_index = 0;
1774
1775 if (!interrupt)
1776 dep->flags &= ~DWC3_EP_TRANSFER_STARTED;
1777 else if (!ret)
1778 dep->flags |= DWC3_EP_END_TRANSFER_PENDING;
1779
1780 dep->flags &= ~DWC3_EP_DELAY_STOP;
1781 return ret;
1782}
1783
1784/**
1785 * dwc3_gadget_start_isoc_quirk - workaround invalid frame number
1786 * @dep: isoc endpoint
1787 *
1788 * This function tests for the correct combination of BIT[15:14] from the 16-bit
1789 * microframe number reported by the XferNotReady event for the future frame
1790 * number to start the isoc transfer.
1791 *
1792 * In DWC_usb31 version 1.70a-ea06 and prior, for highspeed and fullspeed
1793 * isochronous IN, BIT[15:14] of the 16-bit microframe number reported by the
1794 * XferNotReady event are invalid. The driver uses this number to schedule the
1795 * isochronous transfer and passes it to the START TRANSFER command. Because
1796 * this number is invalid, the command may fail. If BIT[15:14] matches the
1797 * internal 16-bit microframe, the START TRANSFER command will pass and the
1798 * transfer will start at the scheduled time, if it is off by 1, the command
1799 * will still pass, but the transfer will start 2 seconds in the future. For all
1800 * other conditions, the START TRANSFER command will fail with bus-expiry.
1801 *
1802 * In order to workaround this issue, we can test for the correct combination of
1803 * BIT[15:14] by sending START TRANSFER commands with different values of
1804 * BIT[15:14]: 'b00, 'b01, 'b10, and 'b11. Each combination is 2^14 uframe apart
1805 * (or 2 seconds). 4 seconds into the future will result in a bus-expiry status.
1806 * As the result, within the 4 possible combinations for BIT[15:14], there will
1807 * be 2 successful and 2 failure START COMMAND status. One of the 2 successful
1808 * command status will result in a 2-second delay start. The smaller BIT[15:14]
1809 * value is the correct combination.
1810 *
1811 * Since there are only 4 outcomes and the results are ordered, we can simply
1812 * test 2 START TRANSFER commands with BIT[15:14] combinations 'b00 and 'b01 to
1813 * deduce the smaller successful combination.
1814 *
1815 * Let test0 = test status for combination 'b00 and test1 = test status for 'b01
1816 * of BIT[15:14]. The correct combination is as follow:
1817 *
1818 * if test0 fails and test1 passes, BIT[15:14] is 'b01
1819 * if test0 fails and test1 fails, BIT[15:14] is 'b10
1820 * if test0 passes and test1 fails, BIT[15:14] is 'b11
1821 * if test0 passes and test1 passes, BIT[15:14] is 'b00
1822 *
1823 * Synopsys STAR 9001202023: Wrong microframe number for isochronous IN
1824 * endpoints.
1825 */
1826static int dwc3_gadget_start_isoc_quirk(struct dwc3_ep *dep)
1827{
1828 int cmd_status = 0;
1829 bool test0;
1830 bool test1;
1831
1832 while (dep->combo_num < 2) {
1833 struct dwc3_gadget_ep_cmd_params params;
1834 u32 test_frame_number;
1835 u32 cmd;
1836
1837 /*
1838 * Check if we can start isoc transfer on the next interval or
1839 * 4 uframes in the future with BIT[15:14] as dep->combo_num
1840 */
1841 test_frame_number = dep->frame_number & DWC3_FRNUMBER_MASK;
1842 test_frame_number |= dep->combo_num << 14;
1843 test_frame_number += max_t(u32, 4, dep->interval);
1844
1845 params.param0 = upper_32_bits(dep->dwc->bounce_addr);
1846 params.param1 = lower_32_bits(dep->dwc->bounce_addr);
1847
1848 cmd = DWC3_DEPCMD_STARTTRANSFER;
1849 cmd |= DWC3_DEPCMD_PARAM(test_frame_number);
1850 cmd_status = dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms);
1851
1852 /* Redo if some other failure beside bus-expiry is received */
1853 if (cmd_status && cmd_status != -EAGAIN) {
1854 dep->start_cmd_status = 0;
1855 dep->combo_num = 0;
1856 return 0;
1857 }
1858
1859 /* Store the first test status */
1860 if (dep->combo_num == 0)
1861 dep->start_cmd_status = cmd_status;
1862
1863 dep->combo_num++;
1864
1865 /*
1866 * End the transfer if the START_TRANSFER command is successful
1867 * to wait for the next XferNotReady to test the command again
1868 */
1869 if (cmd_status == 0) {
1870 dwc3_stop_active_transfer(dep, true, true);
1871 return 0;
1872 }
1873 }
1874
1875 /* test0 and test1 are both completed at this point */
1876 test0 = (dep->start_cmd_status == 0);
1877 test1 = (cmd_status == 0);
1878
1879 if (!test0 && test1)
1880 dep->combo_num = 1;
1881 else if (!test0 && !test1)
1882 dep->combo_num = 2;
1883 else if (test0 && !test1)
1884 dep->combo_num = 3;
1885 else if (test0 && test1)
1886 dep->combo_num = 0;
1887
1888 dep->frame_number &= DWC3_FRNUMBER_MASK;
1889 dep->frame_number |= dep->combo_num << 14;
1890 dep->frame_number += max_t(u32, 4, dep->interval);
1891
1892 /* Reinitialize test variables */
1893 dep->start_cmd_status = 0;
1894 dep->combo_num = 0;
1895
1896 return __dwc3_gadget_kick_transfer(dep);
1897}
1898
1899static int __dwc3_gadget_start_isoc(struct dwc3_ep *dep)
1900{
1901 const struct usb_endpoint_descriptor *desc = dep->endpoint.desc;
1902 struct dwc3 *dwc = dep->dwc;
1903 int ret;
1904 int i;
1905
1906 if (list_empty(&dep->pending_list) &&
1907 list_empty(&dep->started_list)) {
1908 dep->flags |= DWC3_EP_PENDING_REQUEST;
1909 return -EAGAIN;
1910 }
1911
1912 if (!dwc->dis_start_transfer_quirk &&
1913 (DWC3_VER_IS_PRIOR(DWC31, 170A) ||
1914 DWC3_VER_TYPE_IS_WITHIN(DWC31, 170A, EA01, EA06))) {
1915 if (dwc->gadget->speed <= USB_SPEED_HIGH && dep->direction)
1916 return dwc3_gadget_start_isoc_quirk(dep);
1917 }
1918
1919 if (desc->bInterval <= 14 &&
1920 dwc->gadget->speed >= USB_SPEED_HIGH) {
1921 u32 frame = __dwc3_gadget_get_frame(dwc);
1922 bool rollover = frame <
1923 (dep->frame_number & DWC3_FRNUMBER_MASK);
1924
1925 /*
1926 * frame_number is set from XferNotReady and may be already
1927 * out of date. DSTS only provides the lower 14 bit of the
1928 * current frame number. So add the upper two bits of
1929 * frame_number and handle a possible rollover.
1930 * This will provide the correct frame_number unless more than
1931 * rollover has happened since XferNotReady.
1932 */
1933
1934 dep->frame_number = (dep->frame_number & ~DWC3_FRNUMBER_MASK) |
1935 frame;
1936 if (rollover)
1937 dep->frame_number += BIT(14);
1938 }
1939
1940 for (i = 0; i < DWC3_ISOC_MAX_RETRIES; i++) {
1941 int future_interval = i + 1;
1942
1943 /* Give the controller at least 500us to schedule transfers */
1944 if (desc->bInterval < 3)
1945 future_interval += 3 - desc->bInterval;
1946
1947 dep->frame_number = DWC3_ALIGN_FRAME(dep, future_interval);
1948
1949 ret = __dwc3_gadget_kick_transfer(dep);
1950 if (ret != -EAGAIN)
1951 break;
1952 }
1953
1954 /*
1955 * After a number of unsuccessful start attempts due to bus-expiry
1956 * status, issue END_TRANSFER command and retry on the next XferNotReady
1957 * event.
1958 */
1959 if (ret == -EAGAIN)
1960 ret = __dwc3_stop_active_transfer(dep, false, true);
1961
1962 return ret;
1963}
1964
1965static int __dwc3_gadget_ep_queue(struct dwc3_ep *dep, struct dwc3_request *req)
1966{
1967 struct dwc3 *dwc = dep->dwc;
1968
1969 if (!dep->endpoint.desc || !dwc->pullups_connected || !dwc->connected) {
1970 dev_dbg(dwc->dev, "%s: can't queue to disabled endpoint\n",
1971 dep->name);
1972 return -ESHUTDOWN;
1973 }
1974
1975 if (WARN(req->dep != dep, "request %pK belongs to '%s'\n",
1976 &req->request, req->dep->name))
1977 return -EINVAL;
1978
1979 if (WARN(req->status < DWC3_REQUEST_STATUS_COMPLETED,
1980 "%s: request %pK already in flight\n",
1981 dep->name, &req->request))
1982 return -EINVAL;
1983
1984 pm_runtime_get(dwc->dev);
1985
1986 req->request.actual = 0;
1987 req->request.status = -EINPROGRESS;
1988
1989 trace_dwc3_ep_queue(req);
1990
1991 list_add_tail(&req->list, &dep->pending_list);
1992 req->status = DWC3_REQUEST_STATUS_QUEUED;
1993
1994 if (dep->flags & DWC3_EP_WAIT_TRANSFER_COMPLETE)
1995 return 0;
1996
1997 /*
1998 * Start the transfer only after the END_TRANSFER is completed
1999 * and endpoint STALL is cleared.
2000 */
2001 if ((dep->flags & DWC3_EP_END_TRANSFER_PENDING) ||
2002 (dep->flags & DWC3_EP_WEDGE) ||
2003 (dep->flags & DWC3_EP_DELAY_STOP) ||
2004 (dep->flags & DWC3_EP_STALL)) {
2005 dep->flags |= DWC3_EP_DELAY_START;
2006 return 0;
2007 }
2008
2009 /*
2010 * NOTICE: Isochronous endpoints should NEVER be prestarted. We must
2011 * wait for a XferNotReady event so we will know what's the current
2012 * (micro-)frame number.
2013 *
2014 * Without this trick, we are very, very likely gonna get Bus Expiry
2015 * errors which will force us issue EndTransfer command.
2016 */
2017 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
2018 if (!(dep->flags & DWC3_EP_TRANSFER_STARTED)) {
2019 if ((dep->flags & DWC3_EP_PENDING_REQUEST))
2020 return __dwc3_gadget_start_isoc(dep);
2021
2022 return 0;
2023 }
2024 }
2025
2026 __dwc3_gadget_kick_transfer(dep);
2027
2028 return 0;
2029}
2030
2031static int dwc3_gadget_ep_queue(struct usb_ep *ep, struct usb_request *request,
2032 gfp_t gfp_flags)
2033{
2034 struct dwc3_request *req = to_dwc3_request(request);
2035 struct dwc3_ep *dep = to_dwc3_ep(ep);
2036 struct dwc3 *dwc = dep->dwc;
2037
2038 unsigned long flags;
2039
2040 int ret;
2041
2042 spin_lock_irqsave(&dwc->lock, flags);
2043 ret = __dwc3_gadget_ep_queue(dep, req);
2044 spin_unlock_irqrestore(&dwc->lock, flags);
2045
2046 return ret;
2047}
2048
2049static void dwc3_gadget_ep_skip_trbs(struct dwc3_ep *dep, struct dwc3_request *req)
2050{
2051 int i;
2052
2053 /* If req->trb is not set, then the request has not started */
2054 if (!req->trb)
2055 return;
2056
2057 /*
2058 * If request was already started, this means we had to
2059 * stop the transfer. With that we also need to ignore
2060 * all TRBs used by the request, however TRBs can only
2061 * be modified after completion of END_TRANSFER
2062 * command. So what we do here is that we wait for
2063 * END_TRANSFER completion and only after that, we jump
2064 * over TRBs by clearing HWO and incrementing dequeue
2065 * pointer.
2066 */
2067 for (i = 0; i < req->num_trbs; i++) {
2068 struct dwc3_trb *trb;
2069
2070 trb = &dep->trb_pool[dep->trb_dequeue];
2071 trb->ctrl &= ~DWC3_TRB_CTRL_HWO;
2072 dwc3_ep_inc_deq(dep);
2073 }
2074
2075 req->num_trbs = 0;
2076}
2077
2078static void dwc3_gadget_ep_cleanup_cancelled_requests(struct dwc3_ep *dep)
2079{
2080 struct dwc3_request *req;
2081 struct dwc3 *dwc = dep->dwc;
2082
2083 while (!list_empty(&dep->cancelled_list)) {
2084 req = next_request(&dep->cancelled_list);
2085 dwc3_gadget_ep_skip_trbs(dep, req);
2086 switch (req->status) {
2087 case DWC3_REQUEST_STATUS_DISCONNECTED:
2088 dwc3_gadget_giveback(dep, req, -ESHUTDOWN);
2089 break;
2090 case DWC3_REQUEST_STATUS_DEQUEUED:
2091 dwc3_gadget_giveback(dep, req, -ECONNRESET);
2092 break;
2093 case DWC3_REQUEST_STATUS_STALLED:
2094 dwc3_gadget_giveback(dep, req, -EPIPE);
2095 break;
2096 default:
2097 dev_err(dwc->dev, "request cancelled with wrong reason:%d\n", req->status);
2098 dwc3_gadget_giveback(dep, req, -ECONNRESET);
2099 break;
2100 }
2101 /*
2102 * The endpoint is disabled, let the dwc3_remove_requests()
2103 * handle the cleanup.
2104 */
2105 if (!dep->endpoint.desc)
2106 break;
2107 }
2108}
2109
2110static int dwc3_gadget_ep_dequeue(struct usb_ep *ep,
2111 struct usb_request *request)
2112{
2113 struct dwc3_request *req = to_dwc3_request(request);
2114 struct dwc3_request *r = NULL;
2115
2116 struct dwc3_ep *dep = to_dwc3_ep(ep);
2117 struct dwc3 *dwc = dep->dwc;
2118
2119 unsigned long flags;
2120 int ret = 0;
2121
2122 trace_dwc3_ep_dequeue(req);
2123
2124 spin_lock_irqsave(&dwc->lock, flags);
2125
2126 list_for_each_entry(r, &dep->cancelled_list, list) {
2127 if (r == req)
2128 goto out;
2129 }
2130
2131 list_for_each_entry(r, &dep->pending_list, list) {
2132 if (r == req) {
2133 /*
2134 * Explicitly check for EP0/1 as dequeue for those
2135 * EPs need to be handled differently. Control EP
2136 * only deals with one USB req, and giveback will
2137 * occur during dwc3_ep0_stall_and_restart(). EP0
2138 * requests are never added to started_list.
2139 */
2140 if (dep->number > 1)
2141 dwc3_gadget_giveback(dep, req, -ECONNRESET);
2142 else
2143 dwc3_ep0_reset_state(dwc);
2144 goto out;
2145 }
2146 }
2147
2148 list_for_each_entry(r, &dep->started_list, list) {
2149 if (r == req) {
2150 struct dwc3_request *t;
2151
2152 /* wait until it is processed */
2153 dwc3_stop_active_transfer(dep, true, true);
2154
2155 /*
2156 * Remove any started request if the transfer is
2157 * cancelled.
2158 */
2159 list_for_each_entry_safe(r, t, &dep->started_list, list)
2160 dwc3_gadget_move_cancelled_request(r,
2161 DWC3_REQUEST_STATUS_DEQUEUED);
2162
2163 dep->flags &= ~DWC3_EP_WAIT_TRANSFER_COMPLETE;
2164
2165 goto out;
2166 }
2167 }
2168
2169 dev_err(dwc->dev, "request %pK was not queued to %s\n",
2170 request, ep->name);
2171 ret = -EINVAL;
2172out:
2173 spin_unlock_irqrestore(&dwc->lock, flags);
2174
2175 return ret;
2176}
2177
2178int __dwc3_gadget_ep_set_halt(struct dwc3_ep *dep, int value, int protocol)
2179{
2180 struct dwc3_gadget_ep_cmd_params params;
2181 struct dwc3 *dwc = dep->dwc;
2182 struct dwc3_request *req;
2183 struct dwc3_request *tmp;
2184 int ret;
2185
2186 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
2187 dev_err(dwc->dev, "%s is of Isochronous type\n", dep->name);
2188 return -EINVAL;
2189 }
2190
2191 memset(¶ms, 0x00, sizeof(params));
2192
2193 if (value) {
2194 struct dwc3_trb *trb;
2195
2196 unsigned int transfer_in_flight;
2197 unsigned int started;
2198
2199 if (dep->number > 1)
2200 trb = dwc3_ep_prev_trb(dep, dep->trb_enqueue);
2201 else
2202 trb = &dwc->ep0_trb[dep->trb_enqueue];
2203
2204 transfer_in_flight = trb->ctrl & DWC3_TRB_CTRL_HWO;
2205 started = !list_empty(&dep->started_list);
2206
2207 if (!protocol && ((dep->direction && transfer_in_flight) ||
2208 (!dep->direction && started))) {
2209 return -EAGAIN;
2210 }
2211
2212 ret = dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_SETSTALL,
2213 ¶ms);
2214 if (ret)
2215 dev_err(dwc->dev, "failed to set STALL on %s\n",
2216 dep->name);
2217 else
2218 dep->flags |= DWC3_EP_STALL;
2219 } else {
2220 /*
2221 * Don't issue CLEAR_STALL command to control endpoints. The
2222 * controller automatically clears the STALL when it receives
2223 * the SETUP token.
2224 */
2225 if (dep->number <= 1) {
2226 dep->flags &= ~(DWC3_EP_STALL | DWC3_EP_WEDGE);
2227 return 0;
2228 }
2229
2230 dwc3_stop_active_transfer(dep, true, true);
2231
2232 list_for_each_entry_safe(req, tmp, &dep->started_list, list)
2233 dwc3_gadget_move_cancelled_request(req, DWC3_REQUEST_STATUS_STALLED);
2234
2235 if (dep->flags & DWC3_EP_END_TRANSFER_PENDING ||
2236 (dep->flags & DWC3_EP_DELAY_STOP)) {
2237 dep->flags |= DWC3_EP_PENDING_CLEAR_STALL;
2238 if (protocol)
2239 dwc->clear_stall_protocol = dep->number;
2240
2241 return 0;
2242 }
2243
2244 dwc3_gadget_ep_cleanup_cancelled_requests(dep);
2245
2246 ret = dwc3_send_clear_stall_ep_cmd(dep);
2247 if (ret) {
2248 dev_err(dwc->dev, "failed to clear STALL on %s\n",
2249 dep->name);
2250 return ret;
2251 }
2252
2253 dep->flags &= ~(DWC3_EP_STALL | DWC3_EP_WEDGE);
2254
2255 if ((dep->flags & DWC3_EP_DELAY_START) &&
2256 !usb_endpoint_xfer_isoc(dep->endpoint.desc))
2257 __dwc3_gadget_kick_transfer(dep);
2258
2259 dep->flags &= ~DWC3_EP_DELAY_START;
2260 }
2261
2262 return ret;
2263}
2264
2265static int dwc3_gadget_ep_set_halt(struct usb_ep *ep, int value)
2266{
2267 struct dwc3_ep *dep = to_dwc3_ep(ep);
2268 struct dwc3 *dwc = dep->dwc;
2269
2270 unsigned long flags;
2271
2272 int ret;
2273
2274 spin_lock_irqsave(&dwc->lock, flags);
2275 ret = __dwc3_gadget_ep_set_halt(dep, value, false);
2276 spin_unlock_irqrestore(&dwc->lock, flags);
2277
2278 return ret;
2279}
2280
2281static int dwc3_gadget_ep_set_wedge(struct usb_ep *ep)
2282{
2283 struct dwc3_ep *dep = to_dwc3_ep(ep);
2284 struct dwc3 *dwc = dep->dwc;
2285 unsigned long flags;
2286 int ret;
2287
2288 spin_lock_irqsave(&dwc->lock, flags);
2289 dep->flags |= DWC3_EP_WEDGE;
2290
2291 if (dep->number == 0 || dep->number == 1)
2292 ret = __dwc3_gadget_ep0_set_halt(ep, 1);
2293 else
2294 ret = __dwc3_gadget_ep_set_halt(dep, 1, false);
2295 spin_unlock_irqrestore(&dwc->lock, flags);
2296
2297 return ret;
2298}
2299
2300/* -------------------------------------------------------------------------- */
2301
2302static struct usb_endpoint_descriptor dwc3_gadget_ep0_desc = {
2303 .bLength = USB_DT_ENDPOINT_SIZE,
2304 .bDescriptorType = USB_DT_ENDPOINT,
2305 .bmAttributes = USB_ENDPOINT_XFER_CONTROL,
2306};
2307
2308static const struct usb_ep_ops dwc3_gadget_ep0_ops = {
2309 .enable = dwc3_gadget_ep0_enable,
2310 .disable = dwc3_gadget_ep0_disable,
2311 .alloc_request = dwc3_gadget_ep_alloc_request,
2312 .free_request = dwc3_gadget_ep_free_request,
2313 .queue = dwc3_gadget_ep0_queue,
2314 .dequeue = dwc3_gadget_ep_dequeue,
2315 .set_halt = dwc3_gadget_ep0_set_halt,
2316 .set_wedge = dwc3_gadget_ep_set_wedge,
2317};
2318
2319static const struct usb_ep_ops dwc3_gadget_ep_ops = {
2320 .enable = dwc3_gadget_ep_enable,
2321 .disable = dwc3_gadget_ep_disable,
2322 .alloc_request = dwc3_gadget_ep_alloc_request,
2323 .free_request = dwc3_gadget_ep_free_request,
2324 .queue = dwc3_gadget_ep_queue,
2325 .dequeue = dwc3_gadget_ep_dequeue,
2326 .set_halt = dwc3_gadget_ep_set_halt,
2327 .set_wedge = dwc3_gadget_ep_set_wedge,
2328};
2329
2330/* -------------------------------------------------------------------------- */
2331
2332static void dwc3_gadget_enable_linksts_evts(struct dwc3 *dwc, bool set)
2333{
2334 u32 reg;
2335
2336 if (DWC3_VER_IS_PRIOR(DWC3, 250A))
2337 return;
2338
2339 reg = dwc3_readl(dwc->regs, DWC3_DEVTEN);
2340 if (set)
2341 reg |= DWC3_DEVTEN_ULSTCNGEN;
2342 else
2343 reg &= ~DWC3_DEVTEN_ULSTCNGEN;
2344
2345 dwc3_writel(dwc->regs, DWC3_DEVTEN, reg);
2346}
2347
2348static int dwc3_gadget_get_frame(struct usb_gadget *g)
2349{
2350 struct dwc3 *dwc = gadget_to_dwc(g);
2351
2352 return __dwc3_gadget_get_frame(dwc);
2353}
2354
2355static int __dwc3_gadget_wakeup(struct dwc3 *dwc, bool async)
2356{
2357 int retries;
2358
2359 int ret;
2360 u32 reg;
2361
2362 u8 link_state;
2363
2364 /*
2365 * According to the Databook Remote wakeup request should
2366 * be issued only when the device is in early suspend state.
2367 *
2368 * We can check that via USB Link State bits in DSTS register.
2369 */
2370 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
2371
2372 link_state = DWC3_DSTS_USBLNKST(reg);
2373
2374 switch (link_state) {
2375 case DWC3_LINK_STATE_RESET:
2376 case DWC3_LINK_STATE_RX_DET: /* in HS, means Early Suspend */
2377 case DWC3_LINK_STATE_U3: /* in HS, means SUSPEND */
2378 case DWC3_LINK_STATE_U2: /* in HS, means Sleep (L1) */
2379 case DWC3_LINK_STATE_U1:
2380 case DWC3_LINK_STATE_RESUME:
2381 break;
2382 default:
2383 return -EINVAL;
2384 }
2385
2386 if (async)
2387 dwc3_gadget_enable_linksts_evts(dwc, true);
2388
2389 ret = dwc3_gadget_set_link_state(dwc, DWC3_LINK_STATE_RECOV);
2390 if (ret < 0) {
2391 dev_err(dwc->dev, "failed to put link in Recovery\n");
2392 dwc3_gadget_enable_linksts_evts(dwc, false);
2393 return ret;
2394 }
2395
2396 /* Recent versions do this automatically */
2397 if (DWC3_VER_IS_PRIOR(DWC3, 194A)) {
2398 /* write zeroes to Link Change Request */
2399 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2400 reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;
2401 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2402 }
2403
2404 /*
2405 * Since link status change events are enabled we will receive
2406 * an U0 event when wakeup is successful. So bail out.
2407 */
2408 if (async)
2409 return 0;
2410
2411 /* poll until Link State changes to ON */
2412 retries = 20000;
2413
2414 while (retries--) {
2415 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
2416
2417 /* in HS, means ON */
2418 if (DWC3_DSTS_USBLNKST(reg) == DWC3_LINK_STATE_U0)
2419 break;
2420 }
2421
2422 if (DWC3_DSTS_USBLNKST(reg) != DWC3_LINK_STATE_U0) {
2423 dev_err(dwc->dev, "failed to send remote wakeup\n");
2424 return -EINVAL;
2425 }
2426
2427 return 0;
2428}
2429
2430static int dwc3_gadget_wakeup(struct usb_gadget *g)
2431{
2432 struct dwc3 *dwc = gadget_to_dwc(g);
2433 unsigned long flags;
2434 int ret;
2435
2436 if (!dwc->wakeup_configured) {
2437 dev_err(dwc->dev, "remote wakeup not configured\n");
2438 return -EINVAL;
2439 }
2440
2441 spin_lock_irqsave(&dwc->lock, flags);
2442 if (!dwc->gadget->wakeup_armed) {
2443 dev_err(dwc->dev, "not armed for remote wakeup\n");
2444 spin_unlock_irqrestore(&dwc->lock, flags);
2445 return -EINVAL;
2446 }
2447 ret = __dwc3_gadget_wakeup(dwc, true);
2448
2449 spin_unlock_irqrestore(&dwc->lock, flags);
2450
2451 return ret;
2452}
2453
2454static void dwc3_resume_gadget(struct dwc3 *dwc);
2455
2456static int dwc3_gadget_func_wakeup(struct usb_gadget *g, int intf_id)
2457{
2458 struct dwc3 *dwc = gadget_to_dwc(g);
2459 unsigned long flags;
2460 int ret;
2461 int link_state;
2462
2463 if (!dwc->wakeup_configured) {
2464 dev_err(dwc->dev, "remote wakeup not configured\n");
2465 return -EINVAL;
2466 }
2467
2468 spin_lock_irqsave(&dwc->lock, flags);
2469 /*
2470 * If the link is in U3, signal for remote wakeup and wait for the
2471 * link to transition to U0 before sending device notification.
2472 */
2473 link_state = dwc3_gadget_get_link_state(dwc);
2474 if (link_state == DWC3_LINK_STATE_U3) {
2475 ret = __dwc3_gadget_wakeup(dwc, false);
2476 if (ret) {
2477 spin_unlock_irqrestore(&dwc->lock, flags);
2478 return -EINVAL;
2479 }
2480 dwc3_resume_gadget(dwc);
2481 dwc->suspended = false;
2482 dwc->link_state = DWC3_LINK_STATE_U0;
2483 }
2484
2485 ret = dwc3_send_gadget_generic_command(dwc, DWC3_DGCMD_DEV_NOTIFICATION,
2486 DWC3_DGCMDPAR_DN_FUNC_WAKE |
2487 DWC3_DGCMDPAR_INTF_SEL(intf_id));
2488 if (ret)
2489 dev_err(dwc->dev, "function remote wakeup failed, ret:%d\n", ret);
2490
2491 spin_unlock_irqrestore(&dwc->lock, flags);
2492
2493 return ret;
2494}
2495
2496static int dwc3_gadget_set_remote_wakeup(struct usb_gadget *g, int set)
2497{
2498 struct dwc3 *dwc = gadget_to_dwc(g);
2499 unsigned long flags;
2500
2501 spin_lock_irqsave(&dwc->lock, flags);
2502 dwc->wakeup_configured = !!set;
2503 spin_unlock_irqrestore(&dwc->lock, flags);
2504
2505 return 0;
2506}
2507
2508static int dwc3_gadget_set_selfpowered(struct usb_gadget *g,
2509 int is_selfpowered)
2510{
2511 struct dwc3 *dwc = gadget_to_dwc(g);
2512 unsigned long flags;
2513
2514 spin_lock_irqsave(&dwc->lock, flags);
2515 g->is_selfpowered = !!is_selfpowered;
2516 spin_unlock_irqrestore(&dwc->lock, flags);
2517
2518 return 0;
2519}
2520
2521static void dwc3_stop_active_transfers(struct dwc3 *dwc)
2522{
2523 u32 epnum;
2524
2525 for (epnum = 2; epnum < dwc->num_eps; epnum++) {
2526 struct dwc3_ep *dep;
2527
2528 dep = dwc->eps[epnum];
2529 if (!dep)
2530 continue;
2531
2532 dwc3_remove_requests(dwc, dep, -ESHUTDOWN);
2533 }
2534}
2535
2536static void __dwc3_gadget_set_ssp_rate(struct dwc3 *dwc)
2537{
2538 enum usb_ssp_rate ssp_rate = dwc->gadget_ssp_rate;
2539 u32 reg;
2540
2541 if (ssp_rate == USB_SSP_GEN_UNKNOWN)
2542 ssp_rate = dwc->max_ssp_rate;
2543
2544 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2545 reg &= ~DWC3_DCFG_SPEED_MASK;
2546 reg &= ~DWC3_DCFG_NUMLANES(~0);
2547
2548 if (ssp_rate == USB_SSP_GEN_1x2)
2549 reg |= DWC3_DCFG_SUPERSPEED;
2550 else if (dwc->max_ssp_rate != USB_SSP_GEN_1x2)
2551 reg |= DWC3_DCFG_SUPERSPEED_PLUS;
2552
2553 if (ssp_rate != USB_SSP_GEN_2x1 &&
2554 dwc->max_ssp_rate != USB_SSP_GEN_2x1)
2555 reg |= DWC3_DCFG_NUMLANES(1);
2556
2557 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2558}
2559
2560static void __dwc3_gadget_set_speed(struct dwc3 *dwc)
2561{
2562 enum usb_device_speed speed;
2563 u32 reg;
2564
2565 speed = dwc->gadget_max_speed;
2566 if (speed == USB_SPEED_UNKNOWN || speed > dwc->maximum_speed)
2567 speed = dwc->maximum_speed;
2568
2569 if (speed == USB_SPEED_SUPER_PLUS &&
2570 DWC3_IP_IS(DWC32)) {
2571 __dwc3_gadget_set_ssp_rate(dwc);
2572 return;
2573 }
2574
2575 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2576 reg &= ~(DWC3_DCFG_SPEED_MASK);
2577
2578 /*
2579 * WORKAROUND: DWC3 revision < 2.20a have an issue
2580 * which would cause metastability state on Run/Stop
2581 * bit if we try to force the IP to USB2-only mode.
2582 *
2583 * Because of that, we cannot configure the IP to any
2584 * speed other than the SuperSpeed
2585 *
2586 * Refers to:
2587 *
2588 * STAR#9000525659: Clock Domain Crossing on DCTL in
2589 * USB 2.0 Mode
2590 */
2591 if (DWC3_VER_IS_PRIOR(DWC3, 220A) &&
2592 !dwc->dis_metastability_quirk) {
2593 reg |= DWC3_DCFG_SUPERSPEED;
2594 } else {
2595 switch (speed) {
2596 case USB_SPEED_FULL:
2597 reg |= DWC3_DCFG_FULLSPEED;
2598 break;
2599 case USB_SPEED_HIGH:
2600 reg |= DWC3_DCFG_HIGHSPEED;
2601 break;
2602 case USB_SPEED_SUPER:
2603 reg |= DWC3_DCFG_SUPERSPEED;
2604 break;
2605 case USB_SPEED_SUPER_PLUS:
2606 if (DWC3_IP_IS(DWC3))
2607 reg |= DWC3_DCFG_SUPERSPEED;
2608 else
2609 reg |= DWC3_DCFG_SUPERSPEED_PLUS;
2610 break;
2611 default:
2612 dev_err(dwc->dev, "invalid speed (%d)\n", speed);
2613
2614 if (DWC3_IP_IS(DWC3))
2615 reg |= DWC3_DCFG_SUPERSPEED;
2616 else
2617 reg |= DWC3_DCFG_SUPERSPEED_PLUS;
2618 }
2619 }
2620
2621 if (DWC3_IP_IS(DWC32) &&
2622 speed > USB_SPEED_UNKNOWN &&
2623 speed < USB_SPEED_SUPER_PLUS)
2624 reg &= ~DWC3_DCFG_NUMLANES(~0);
2625
2626 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2627}
2628
2629static int dwc3_gadget_run_stop(struct dwc3 *dwc, int is_on)
2630{
2631 u32 reg;
2632 u32 timeout = 2000;
2633 u32 saved_config = 0;
2634
2635 if (pm_runtime_suspended(dwc->dev))
2636 return 0;
2637
2638 /*
2639 * When operating in USB 2.0 speeds (HS/FS), ensure that
2640 * GUSB2PHYCFG.ENBLSLPM and GUSB2PHYCFG.SUSPHY are cleared before starting
2641 * or stopping the controller. This resolves timeout issues that occur
2642 * during frequent role switches between host and device modes.
2643 *
2644 * Save and clear these settings, then restore them after completing the
2645 * controller start or stop sequence.
2646 *
2647 * This solution was discovered through experimentation as it is not
2648 * mentioned in the dwc3 programming guide. It has been tested on an
2649 * Exynos platforms.
2650 */
2651 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
2652 if (reg & DWC3_GUSB2PHYCFG_SUSPHY) {
2653 saved_config |= DWC3_GUSB2PHYCFG_SUSPHY;
2654 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
2655 }
2656
2657 if (reg & DWC3_GUSB2PHYCFG_ENBLSLPM) {
2658 saved_config |= DWC3_GUSB2PHYCFG_ENBLSLPM;
2659 reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM;
2660 }
2661
2662 if (saved_config)
2663 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
2664
2665 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2666 if (is_on) {
2667 if (DWC3_VER_IS_WITHIN(DWC3, ANY, 187A)) {
2668 reg &= ~DWC3_DCTL_TRGTULST_MASK;
2669 reg |= DWC3_DCTL_TRGTULST_RX_DET;
2670 }
2671
2672 if (!DWC3_VER_IS_PRIOR(DWC3, 194A))
2673 reg &= ~DWC3_DCTL_KEEP_CONNECT;
2674 reg |= DWC3_DCTL_RUN_STOP;
2675
2676 __dwc3_gadget_set_speed(dwc);
2677 dwc->pullups_connected = true;
2678 } else {
2679 reg &= ~DWC3_DCTL_RUN_STOP;
2680
2681 dwc->pullups_connected = false;
2682 }
2683
2684 dwc3_gadget_dctl_write_safe(dwc, reg);
2685
2686 do {
2687 usleep_range(1000, 2000);
2688 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
2689 reg &= DWC3_DSTS_DEVCTRLHLT;
2690 } while (--timeout && !(!is_on ^ !reg));
2691
2692 if (saved_config) {
2693 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
2694 reg |= saved_config;
2695 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
2696 }
2697
2698 if (!timeout)
2699 return -ETIMEDOUT;
2700
2701 return 0;
2702}
2703
2704static void dwc3_gadget_disable_irq(struct dwc3 *dwc);
2705static void __dwc3_gadget_stop(struct dwc3 *dwc);
2706static int __dwc3_gadget_start(struct dwc3 *dwc);
2707
2708static int dwc3_gadget_soft_disconnect(struct dwc3 *dwc)
2709{
2710 unsigned long flags;
2711 int ret;
2712
2713 spin_lock_irqsave(&dwc->lock, flags);
2714 if (!dwc->pullups_connected) {
2715 spin_unlock_irqrestore(&dwc->lock, flags);
2716 return 0;
2717 }
2718
2719 dwc->connected = false;
2720
2721 /*
2722 * Attempt to end pending SETUP status phase, and not wait for the
2723 * function to do so.
2724 */
2725 if (dwc->delayed_status)
2726 dwc3_ep0_send_delayed_status(dwc);
2727
2728 /*
2729 * In the Synopsys DesignWare Cores USB3 Databook Rev. 3.30a
2730 * Section 4.1.8 Table 4-7, it states that for a device-initiated
2731 * disconnect, the SW needs to ensure that it sends "a DEPENDXFER
2732 * command for any active transfers" before clearing the RunStop
2733 * bit.
2734 */
2735 dwc3_stop_active_transfers(dwc);
2736 spin_unlock_irqrestore(&dwc->lock, flags);
2737
2738 /*
2739 * Per databook, when we want to stop the gadget, if a control transfer
2740 * is still in process, complete it and get the core into setup phase.
2741 * In case the host is unresponsive to a SETUP transaction, forcefully
2742 * stall the transfer, and move back to the SETUP phase, so that any
2743 * pending endxfers can be executed.
2744 */
2745 if (dwc->ep0state != EP0_SETUP_PHASE) {
2746 reinit_completion(&dwc->ep0_in_setup);
2747
2748 ret = wait_for_completion_timeout(&dwc->ep0_in_setup,
2749 msecs_to_jiffies(DWC3_PULL_UP_TIMEOUT));
2750 if (ret == 0) {
2751 dev_warn(dwc->dev, "wait for SETUP phase timed out\n");
2752 spin_lock_irqsave(&dwc->lock, flags);
2753 dwc3_ep0_reset_state(dwc);
2754 spin_unlock_irqrestore(&dwc->lock, flags);
2755 }
2756 }
2757
2758 /*
2759 * Note: if the GEVNTCOUNT indicates events in the event buffer, the
2760 * driver needs to acknowledge them before the controller can halt.
2761 * Simply let the interrupt handler acknowledges and handle the
2762 * remaining event generated by the controller while polling for
2763 * DSTS.DEVCTLHLT.
2764 */
2765 ret = dwc3_gadget_run_stop(dwc, false);
2766
2767 /*
2768 * Stop the gadget after controller is halted, so that if needed, the
2769 * events to update EP0 state can still occur while the run/stop
2770 * routine polls for the halted state. DEVTEN is cleared as part of
2771 * gadget stop.
2772 */
2773 spin_lock_irqsave(&dwc->lock, flags);
2774 __dwc3_gadget_stop(dwc);
2775 spin_unlock_irqrestore(&dwc->lock, flags);
2776
2777 return ret;
2778}
2779
2780static int dwc3_gadget_soft_connect(struct dwc3 *dwc)
2781{
2782 int ret;
2783
2784 /*
2785 * In the Synopsys DWC_usb31 1.90a programming guide section
2786 * 4.1.9, it specifies that for a reconnect after a
2787 * device-initiated disconnect requires a core soft reset
2788 * (DCTL.CSftRst) before enabling the run/stop bit.
2789 */
2790 ret = dwc3_core_soft_reset(dwc);
2791 if (ret)
2792 return ret;
2793
2794 dwc3_event_buffers_setup(dwc);
2795 __dwc3_gadget_start(dwc);
2796 return dwc3_gadget_run_stop(dwc, true);
2797}
2798
2799static int dwc3_gadget_pullup(struct usb_gadget *g, int is_on)
2800{
2801 struct dwc3 *dwc = gadget_to_dwc(g);
2802 int ret;
2803
2804 is_on = !!is_on;
2805
2806 dwc->softconnect = is_on;
2807
2808 /*
2809 * Avoid issuing a runtime resume if the device is already in the
2810 * suspended state during gadget disconnect. DWC3 gadget was already
2811 * halted/stopped during runtime suspend.
2812 */
2813 if (!is_on) {
2814 pm_runtime_barrier(dwc->dev);
2815 if (pm_runtime_suspended(dwc->dev))
2816 return 0;
2817 }
2818
2819 /*
2820 * Check the return value for successful resume, or error. For a
2821 * successful resume, the DWC3 runtime PM resume routine will handle
2822 * the run stop sequence, so avoid duplicate operations here.
2823 */
2824 ret = pm_runtime_get_sync(dwc->dev);
2825 if (!ret || ret < 0) {
2826 pm_runtime_put(dwc->dev);
2827 if (ret < 0)
2828 pm_runtime_set_suspended(dwc->dev);
2829 return ret;
2830 }
2831
2832 if (dwc->pullups_connected == is_on) {
2833 pm_runtime_put(dwc->dev);
2834 return 0;
2835 }
2836
2837 synchronize_irq(dwc->irq_gadget);
2838
2839 if (!is_on)
2840 ret = dwc3_gadget_soft_disconnect(dwc);
2841 else
2842 ret = dwc3_gadget_soft_connect(dwc);
2843
2844 pm_runtime_put(dwc->dev);
2845
2846 return ret;
2847}
2848
2849static void dwc3_gadget_enable_irq(struct dwc3 *dwc)
2850{
2851 u32 reg;
2852
2853 /* Enable all but Start and End of Frame IRQs */
2854 reg = (DWC3_DEVTEN_EVNTOVERFLOWEN |
2855 DWC3_DEVTEN_CMDCMPLTEN |
2856 DWC3_DEVTEN_ERRTICERREN |
2857 DWC3_DEVTEN_WKUPEVTEN |
2858 DWC3_DEVTEN_CONNECTDONEEN |
2859 DWC3_DEVTEN_USBRSTEN |
2860 DWC3_DEVTEN_DISCONNEVTEN);
2861
2862 if (DWC3_VER_IS_PRIOR(DWC3, 250A))
2863 reg |= DWC3_DEVTEN_ULSTCNGEN;
2864
2865 /* On 2.30a and above this bit enables U3/L2-L1 Suspend Events */
2866 if (!DWC3_VER_IS_PRIOR(DWC3, 230A))
2867 reg |= DWC3_DEVTEN_U3L2L1SUSPEN;
2868
2869 dwc3_writel(dwc->regs, DWC3_DEVTEN, reg);
2870}
2871
2872static void dwc3_gadget_disable_irq(struct dwc3 *dwc)
2873{
2874 /* mask all interrupts */
2875 dwc3_writel(dwc->regs, DWC3_DEVTEN, 0x00);
2876}
2877
2878static irqreturn_t dwc3_interrupt(int irq, void *_dwc);
2879static irqreturn_t dwc3_thread_interrupt(int irq, void *_dwc);
2880
2881/**
2882 * dwc3_gadget_setup_nump - calculate and initialize NUMP field of %DWC3_DCFG
2883 * @dwc: pointer to our context structure
2884 *
2885 * The following looks like complex but it's actually very simple. In order to
2886 * calculate the number of packets we can burst at once on OUT transfers, we're
2887 * gonna use RxFIFO size.
2888 *
2889 * To calculate RxFIFO size we need two numbers:
2890 * MDWIDTH = size, in bits, of the internal memory bus
2891 * RAM2_DEPTH = depth, in MDWIDTH, of internal RAM2 (where RxFIFO sits)
2892 *
2893 * Given these two numbers, the formula is simple:
2894 *
2895 * RxFIFO Size = (RAM2_DEPTH * MDWIDTH / 8) - 24 - 16;
2896 *
2897 * 24 bytes is for 3x SETUP packets
2898 * 16 bytes is a clock domain crossing tolerance
2899 *
2900 * Given RxFIFO Size, NUMP = RxFIFOSize / 1024;
2901 */
2902static void dwc3_gadget_setup_nump(struct dwc3 *dwc)
2903{
2904 u32 ram2_depth;
2905 u32 mdwidth;
2906 u32 nump;
2907 u32 reg;
2908
2909 ram2_depth = DWC3_GHWPARAMS7_RAM2_DEPTH(dwc->hwparams.hwparams7);
2910 mdwidth = dwc3_mdwidth(dwc);
2911
2912 nump = ((ram2_depth * mdwidth / 8) - 24 - 16) / 1024;
2913 nump = min_t(u32, nump, 16);
2914
2915 /* update NumP */
2916 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2917 reg &= ~DWC3_DCFG_NUMP_MASK;
2918 reg |= nump << DWC3_DCFG_NUMP_SHIFT;
2919 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2920}
2921
2922static int __dwc3_gadget_start(struct dwc3 *dwc)
2923{
2924 struct dwc3_ep *dep;
2925 int ret = 0;
2926 u32 reg;
2927
2928 /*
2929 * Use IMOD if enabled via dwc->imod_interval. Otherwise, if
2930 * the core supports IMOD, disable it.
2931 */
2932 if (dwc->imod_interval) {
2933 dwc3_writel(dwc->regs, DWC3_DEV_IMOD(0), dwc->imod_interval);
2934 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), DWC3_GEVNTCOUNT_EHB);
2935 } else if (dwc3_has_imod(dwc)) {
2936 dwc3_writel(dwc->regs, DWC3_DEV_IMOD(0), 0);
2937 }
2938
2939 /*
2940 * We are telling dwc3 that we want to use DCFG.NUMP as ACK TP's NUMP
2941 * field instead of letting dwc3 itself calculate that automatically.
2942 *
2943 * This way, we maximize the chances that we'll be able to get several
2944 * bursts of data without going through any sort of endpoint throttling.
2945 */
2946 reg = dwc3_readl(dwc->regs, DWC3_GRXTHRCFG);
2947 if (DWC3_IP_IS(DWC3))
2948 reg &= ~DWC3_GRXTHRCFG_PKTCNTSEL;
2949 else
2950 reg &= ~DWC31_GRXTHRCFG_PKTCNTSEL;
2951
2952 dwc3_writel(dwc->regs, DWC3_GRXTHRCFG, reg);
2953
2954 dwc3_gadget_setup_nump(dwc);
2955
2956 /*
2957 * Currently the controller handles single stream only. So, Ignore
2958 * Packet Pending bit for stream selection and don't search for another
2959 * stream if the host sends Data Packet with PP=0 (for OUT direction) or
2960 * ACK with NumP=0 and PP=0 (for IN direction). This slightly improves
2961 * the stream performance.
2962 */
2963 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2964 reg |= DWC3_DCFG_IGNSTRMPP;
2965 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2966
2967 /* Enable MST by default if the device is capable of MST */
2968 if (DWC3_MST_CAPABLE(&dwc->hwparams)) {
2969 reg = dwc3_readl(dwc->regs, DWC3_DCFG1);
2970 reg &= ~DWC3_DCFG1_DIS_MST_ENH;
2971 dwc3_writel(dwc->regs, DWC3_DCFG1, reg);
2972 }
2973
2974 /* Start with SuperSpeed Default */
2975 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
2976
2977 ret = dwc3_gadget_start_config(dwc, 0);
2978 if (ret) {
2979 dev_err(dwc->dev, "failed to config endpoints\n");
2980 return ret;
2981 }
2982
2983 dep = dwc->eps[0];
2984 dep->flags = 0;
2985 ret = __dwc3_gadget_ep_enable(dep, DWC3_DEPCFG_ACTION_INIT);
2986 if (ret) {
2987 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
2988 goto err0;
2989 }
2990
2991 dep = dwc->eps[1];
2992 dep->flags = 0;
2993 ret = __dwc3_gadget_ep_enable(dep, DWC3_DEPCFG_ACTION_INIT);
2994 if (ret) {
2995 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
2996 goto err1;
2997 }
2998
2999 /* begin to receive SETUP packets */
3000 dwc->ep0state = EP0_SETUP_PHASE;
3001 dwc->ep0_bounced = false;
3002 dwc->link_state = DWC3_LINK_STATE_SS_DIS;
3003 dwc->delayed_status = false;
3004 dwc3_ep0_out_start(dwc);
3005
3006 dwc3_gadget_enable_irq(dwc);
3007 dwc3_enable_susphy(dwc, true);
3008
3009 return 0;
3010
3011err1:
3012 __dwc3_gadget_ep_disable(dwc->eps[0]);
3013
3014err0:
3015 return ret;
3016}
3017
3018static int dwc3_gadget_start(struct usb_gadget *g,
3019 struct usb_gadget_driver *driver)
3020{
3021 struct dwc3 *dwc = gadget_to_dwc(g);
3022 unsigned long flags;
3023 int ret;
3024 int irq;
3025
3026 irq = dwc->irq_gadget;
3027 ret = request_threaded_irq(irq, dwc3_interrupt, dwc3_thread_interrupt,
3028 IRQF_SHARED, "dwc3", dwc->ev_buf);
3029 if (ret) {
3030 dev_err(dwc->dev, "failed to request irq #%d --> %d\n",
3031 irq, ret);
3032 return ret;
3033 }
3034
3035 spin_lock_irqsave(&dwc->lock, flags);
3036 dwc->gadget_driver = driver;
3037 spin_unlock_irqrestore(&dwc->lock, flags);
3038
3039 if (dwc->sys_wakeup)
3040 device_wakeup_enable(dwc->sysdev);
3041
3042 return 0;
3043}
3044
3045static void __dwc3_gadget_stop(struct dwc3 *dwc)
3046{
3047 dwc3_gadget_disable_irq(dwc);
3048 __dwc3_gadget_ep_disable(dwc->eps[0]);
3049 __dwc3_gadget_ep_disable(dwc->eps[1]);
3050}
3051
3052static int dwc3_gadget_stop(struct usb_gadget *g)
3053{
3054 struct dwc3 *dwc = gadget_to_dwc(g);
3055 unsigned long flags;
3056
3057 if (dwc->sys_wakeup)
3058 device_wakeup_disable(dwc->sysdev);
3059
3060 spin_lock_irqsave(&dwc->lock, flags);
3061 dwc->gadget_driver = NULL;
3062 dwc->max_cfg_eps = 0;
3063 spin_unlock_irqrestore(&dwc->lock, flags);
3064
3065 free_irq(dwc->irq_gadget, dwc->ev_buf);
3066
3067 return 0;
3068}
3069
3070static void dwc3_gadget_config_params(struct usb_gadget *g,
3071 struct usb_dcd_config_params *params)
3072{
3073 struct dwc3 *dwc = gadget_to_dwc(g);
3074
3075 params->besl_baseline = USB_DEFAULT_BESL_UNSPECIFIED;
3076 params->besl_deep = USB_DEFAULT_BESL_UNSPECIFIED;
3077
3078 /* Recommended BESL */
3079 if (!dwc->dis_enblslpm_quirk) {
3080 /*
3081 * If the recommended BESL baseline is 0 or if the BESL deep is
3082 * less than 2, Microsoft's Windows 10 host usb stack will issue
3083 * a usb reset immediately after it receives the extended BOS
3084 * descriptor and the enumeration will fail. To maintain
3085 * compatibility with the Windows' usb stack, let's set the
3086 * recommended BESL baseline to 1 and clamp the BESL deep to be
3087 * within 2 to 15.
3088 */
3089 params->besl_baseline = 1;
3090 if (dwc->is_utmi_l1_suspend)
3091 params->besl_deep =
3092 clamp_t(u8, dwc->hird_threshold, 2, 15);
3093 }
3094
3095 /* U1 Device exit Latency */
3096 if (dwc->dis_u1_entry_quirk)
3097 params->bU1devExitLat = 0;
3098 else
3099 params->bU1devExitLat = DWC3_DEFAULT_U1_DEV_EXIT_LAT;
3100
3101 /* U2 Device exit Latency */
3102 if (dwc->dis_u2_entry_quirk)
3103 params->bU2DevExitLat = 0;
3104 else
3105 params->bU2DevExitLat =
3106 cpu_to_le16(DWC3_DEFAULT_U2_DEV_EXIT_LAT);
3107}
3108
3109static void dwc3_gadget_set_speed(struct usb_gadget *g,
3110 enum usb_device_speed speed)
3111{
3112 struct dwc3 *dwc = gadget_to_dwc(g);
3113 unsigned long flags;
3114
3115 spin_lock_irqsave(&dwc->lock, flags);
3116 dwc->gadget_max_speed = speed;
3117 spin_unlock_irqrestore(&dwc->lock, flags);
3118}
3119
3120static void dwc3_gadget_set_ssp_rate(struct usb_gadget *g,
3121 enum usb_ssp_rate rate)
3122{
3123 struct dwc3 *dwc = gadget_to_dwc(g);
3124 unsigned long flags;
3125
3126 spin_lock_irqsave(&dwc->lock, flags);
3127 dwc->gadget_max_speed = USB_SPEED_SUPER_PLUS;
3128 dwc->gadget_ssp_rate = rate;
3129 spin_unlock_irqrestore(&dwc->lock, flags);
3130}
3131
3132static int dwc3_gadget_vbus_draw(struct usb_gadget *g, unsigned int mA)
3133{
3134 struct dwc3 *dwc = gadget_to_dwc(g);
3135 union power_supply_propval val = {0};
3136 int ret;
3137
3138 if (dwc->usb2_phy)
3139 return usb_phy_set_power(dwc->usb2_phy, mA);
3140
3141 if (!dwc->usb_psy)
3142 return -EOPNOTSUPP;
3143
3144 val.intval = 1000 * mA;
3145 ret = power_supply_set_property(dwc->usb_psy, POWER_SUPPLY_PROP_INPUT_CURRENT_LIMIT, &val);
3146
3147 return ret;
3148}
3149
3150/**
3151 * dwc3_gadget_check_config - ensure dwc3 can support the USB configuration
3152 * @g: pointer to the USB gadget
3153 *
3154 * Used to record the maximum number of endpoints being used in a USB composite
3155 * device. (across all configurations) This is to be used in the calculation
3156 * of the TXFIFO sizes when resizing internal memory for individual endpoints.
3157 * It will help ensured that the resizing logic reserves enough space for at
3158 * least one max packet.
3159 */
3160static int dwc3_gadget_check_config(struct usb_gadget *g)
3161{
3162 struct dwc3 *dwc = gadget_to_dwc(g);
3163 struct usb_ep *ep;
3164 int fifo_size = 0;
3165 int ram_depth;
3166 int ep_num = 0;
3167
3168 if (!dwc->do_fifo_resize)
3169 return 0;
3170
3171 list_for_each_entry(ep, &g->ep_list, ep_list) {
3172 /* Only interested in the IN endpoints */
3173 if (ep->claimed && (ep->address & USB_DIR_IN))
3174 ep_num++;
3175 }
3176
3177 if (ep_num <= dwc->max_cfg_eps)
3178 return 0;
3179
3180 /* Update the max number of eps in the composition */
3181 dwc->max_cfg_eps = ep_num;
3182
3183 fifo_size = dwc3_gadget_calc_tx_fifo_size(dwc, dwc->max_cfg_eps);
3184 /* Based on the equation, increment by one for every ep */
3185 fifo_size += dwc->max_cfg_eps;
3186
3187 /* Check if we can fit a single fifo per endpoint */
3188 ram_depth = dwc3_gadget_calc_ram_depth(dwc);
3189 if (fifo_size > ram_depth)
3190 return -ENOMEM;
3191
3192 return 0;
3193}
3194
3195static void dwc3_gadget_async_callbacks(struct usb_gadget *g, bool enable)
3196{
3197 struct dwc3 *dwc = gadget_to_dwc(g);
3198 unsigned long flags;
3199
3200 spin_lock_irqsave(&dwc->lock, flags);
3201 dwc->async_callbacks = enable;
3202 spin_unlock_irqrestore(&dwc->lock, flags);
3203}
3204
3205static const struct usb_gadget_ops dwc3_gadget_ops = {
3206 .get_frame = dwc3_gadget_get_frame,
3207 .wakeup = dwc3_gadget_wakeup,
3208 .func_wakeup = dwc3_gadget_func_wakeup,
3209 .set_remote_wakeup = dwc3_gadget_set_remote_wakeup,
3210 .set_selfpowered = dwc3_gadget_set_selfpowered,
3211 .pullup = dwc3_gadget_pullup,
3212 .udc_start = dwc3_gadget_start,
3213 .udc_stop = dwc3_gadget_stop,
3214 .udc_set_speed = dwc3_gadget_set_speed,
3215 .udc_set_ssp_rate = dwc3_gadget_set_ssp_rate,
3216 .get_config_params = dwc3_gadget_config_params,
3217 .vbus_draw = dwc3_gadget_vbus_draw,
3218 .check_config = dwc3_gadget_check_config,
3219 .udc_async_callbacks = dwc3_gadget_async_callbacks,
3220};
3221
3222/* -------------------------------------------------------------------------- */
3223
3224static int dwc3_gadget_init_control_endpoint(struct dwc3_ep *dep)
3225{
3226 struct dwc3 *dwc = dep->dwc;
3227
3228 usb_ep_set_maxpacket_limit(&dep->endpoint, 512);
3229 dep->endpoint.maxburst = 1;
3230 dep->endpoint.ops = &dwc3_gadget_ep0_ops;
3231 if (!dep->direction)
3232 dwc->gadget->ep0 = &dep->endpoint;
3233
3234 dep->endpoint.caps.type_control = true;
3235
3236 return 0;
3237}
3238
3239static int dwc3_gadget_init_in_endpoint(struct dwc3_ep *dep)
3240{
3241 struct dwc3 *dwc = dep->dwc;
3242 u32 mdwidth;
3243 int size;
3244 int maxpacket;
3245
3246 mdwidth = dwc3_mdwidth(dwc);
3247
3248 /* MDWIDTH is represented in bits, we need it in bytes */
3249 mdwidth /= 8;
3250
3251 size = dwc3_readl(dwc->regs, DWC3_GTXFIFOSIZ(dep->number >> 1));
3252 if (DWC3_IP_IS(DWC3))
3253 size = DWC3_GTXFIFOSIZ_TXFDEP(size);
3254 else
3255 size = DWC31_GTXFIFOSIZ_TXFDEP(size);
3256
3257 /*
3258 * maxpacket size is determined as part of the following, after assuming
3259 * a mult value of one maxpacket:
3260 * DWC3 revision 280A and prior:
3261 * fifo_size = mult * (max_packet / mdwidth) + 1;
3262 * maxpacket = mdwidth * (fifo_size - 1);
3263 *
3264 * DWC3 revision 290A and onwards:
3265 * fifo_size = mult * ((max_packet + mdwidth)/mdwidth + 1) + 1
3266 * maxpacket = mdwidth * ((fifo_size - 1) - 1) - mdwidth;
3267 */
3268 if (DWC3_VER_IS_PRIOR(DWC3, 290A))
3269 maxpacket = mdwidth * (size - 1);
3270 else
3271 maxpacket = mdwidth * ((size - 1) - 1) - mdwidth;
3272
3273 /* Functionally, space for one max packet is sufficient */
3274 size = min_t(int, maxpacket, 1024);
3275 usb_ep_set_maxpacket_limit(&dep->endpoint, size);
3276
3277 dep->endpoint.max_streams = 16;
3278 dep->endpoint.ops = &dwc3_gadget_ep_ops;
3279 list_add_tail(&dep->endpoint.ep_list,
3280 &dwc->gadget->ep_list);
3281 dep->endpoint.caps.type_iso = true;
3282 dep->endpoint.caps.type_bulk = true;
3283 dep->endpoint.caps.type_int = true;
3284
3285 return dwc3_alloc_trb_pool(dep);
3286}
3287
3288static int dwc3_gadget_init_out_endpoint(struct dwc3_ep *dep)
3289{
3290 struct dwc3 *dwc = dep->dwc;
3291 u32 mdwidth;
3292 int size;
3293
3294 mdwidth = dwc3_mdwidth(dwc);
3295
3296 /* MDWIDTH is represented in bits, convert to bytes */
3297 mdwidth /= 8;
3298
3299 /* All OUT endpoints share a single RxFIFO space */
3300 size = dwc3_readl(dwc->regs, DWC3_GRXFIFOSIZ(0));
3301 if (DWC3_IP_IS(DWC3))
3302 size = DWC3_GRXFIFOSIZ_RXFDEP(size);
3303 else
3304 size = DWC31_GRXFIFOSIZ_RXFDEP(size);
3305
3306 /* FIFO depth is in MDWDITH bytes */
3307 size *= mdwidth;
3308
3309 /*
3310 * To meet performance requirement, a minimum recommended RxFIFO size
3311 * is defined as follow:
3312 * RxFIFO size >= (3 x MaxPacketSize) +
3313 * (3 x 8 bytes setup packets size) + (16 bytes clock crossing margin)
3314 *
3315 * Then calculate the max packet limit as below.
3316 */
3317 size -= (3 * 8) + 16;
3318 if (size < 0)
3319 size = 0;
3320 else
3321 size /= 3;
3322
3323 usb_ep_set_maxpacket_limit(&dep->endpoint, size);
3324 dep->endpoint.max_streams = 16;
3325 dep->endpoint.ops = &dwc3_gadget_ep_ops;
3326 list_add_tail(&dep->endpoint.ep_list,
3327 &dwc->gadget->ep_list);
3328 dep->endpoint.caps.type_iso = true;
3329 dep->endpoint.caps.type_bulk = true;
3330 dep->endpoint.caps.type_int = true;
3331
3332 return dwc3_alloc_trb_pool(dep);
3333}
3334
3335static int dwc3_gadget_init_endpoint(struct dwc3 *dwc, u8 epnum)
3336{
3337 struct dwc3_ep *dep;
3338 bool direction = epnum & 1;
3339 int ret;
3340 u8 num = epnum >> 1;
3341
3342 dep = kzalloc(sizeof(*dep), GFP_KERNEL);
3343 if (!dep)
3344 return -ENOMEM;
3345
3346 dep->dwc = dwc;
3347 dep->number = epnum;
3348 dep->direction = direction;
3349 dep->regs = dwc->regs + DWC3_DEP_BASE(epnum);
3350 dwc->eps[epnum] = dep;
3351 dep->combo_num = 0;
3352 dep->start_cmd_status = 0;
3353
3354 snprintf(dep->name, sizeof(dep->name), "ep%u%s", num,
3355 direction ? "in" : "out");
3356
3357 dep->endpoint.name = dep->name;
3358
3359 if (!(dep->number > 1)) {
3360 dep->endpoint.desc = &dwc3_gadget_ep0_desc;
3361 dep->endpoint.comp_desc = NULL;
3362 }
3363
3364 if (num == 0)
3365 ret = dwc3_gadget_init_control_endpoint(dep);
3366 else if (direction)
3367 ret = dwc3_gadget_init_in_endpoint(dep);
3368 else
3369 ret = dwc3_gadget_init_out_endpoint(dep);
3370
3371 if (ret)
3372 return ret;
3373
3374 dep->endpoint.caps.dir_in = direction;
3375 dep->endpoint.caps.dir_out = !direction;
3376
3377 INIT_LIST_HEAD(&dep->pending_list);
3378 INIT_LIST_HEAD(&dep->started_list);
3379 INIT_LIST_HEAD(&dep->cancelled_list);
3380
3381 dwc3_debugfs_create_endpoint_dir(dep);
3382
3383 return 0;
3384}
3385
3386static int dwc3_gadget_init_endpoints(struct dwc3 *dwc, u8 total)
3387{
3388 u8 epnum;
3389
3390 INIT_LIST_HEAD(&dwc->gadget->ep_list);
3391
3392 for (epnum = 0; epnum < total; epnum++) {
3393 int ret;
3394
3395 ret = dwc3_gadget_init_endpoint(dwc, epnum);
3396 if (ret)
3397 return ret;
3398 }
3399
3400 return 0;
3401}
3402
3403static void dwc3_gadget_free_endpoints(struct dwc3 *dwc)
3404{
3405 struct dwc3_ep *dep;
3406 u8 epnum;
3407
3408 for (epnum = 0; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
3409 dep = dwc->eps[epnum];
3410 if (!dep)
3411 continue;
3412 /*
3413 * Physical endpoints 0 and 1 are special; they form the
3414 * bi-directional USB endpoint 0.
3415 *
3416 * For those two physical endpoints, we don't allocate a TRB
3417 * pool nor do we add them the endpoints list. Due to that, we
3418 * shouldn't do these two operations otherwise we would end up
3419 * with all sorts of bugs when removing dwc3.ko.
3420 */
3421 if (epnum != 0 && epnum != 1) {
3422 dwc3_free_trb_pool(dep);
3423 list_del(&dep->endpoint.ep_list);
3424 }
3425
3426 dwc3_debugfs_remove_endpoint_dir(dep);
3427 kfree(dep);
3428 }
3429}
3430
3431/* -------------------------------------------------------------------------- */
3432
3433static int dwc3_gadget_ep_reclaim_completed_trb(struct dwc3_ep *dep,
3434 struct dwc3_request *req, struct dwc3_trb *trb,
3435 const struct dwc3_event_depevt *event, int status, int chain)
3436{
3437 unsigned int count;
3438
3439 dwc3_ep_inc_deq(dep);
3440
3441 trace_dwc3_complete_trb(dep, trb);
3442 req->num_trbs--;
3443
3444 /*
3445 * If we're in the middle of series of chained TRBs and we
3446 * receive a short transfer along the way, DWC3 will skip
3447 * through all TRBs including the last TRB in the chain (the
3448 * where CHN bit is zero. DWC3 will also avoid clearing HWO
3449 * bit and SW has to do it manually.
3450 *
3451 * We're going to do that here to avoid problems of HW trying
3452 * to use bogus TRBs for transfers.
3453 */
3454 if (chain && (trb->ctrl & DWC3_TRB_CTRL_HWO))
3455 trb->ctrl &= ~DWC3_TRB_CTRL_HWO;
3456
3457 /*
3458 * For isochronous transfers, the first TRB in a service interval must
3459 * have the Isoc-First type. Track and report its interval frame number.
3460 */
3461 if (usb_endpoint_xfer_isoc(dep->endpoint.desc) &&
3462 (trb->ctrl & DWC3_TRBCTL_ISOCHRONOUS_FIRST)) {
3463 unsigned int frame_number;
3464
3465 frame_number = DWC3_TRB_CTRL_GET_SID_SOFN(trb->ctrl);
3466 frame_number &= ~(dep->interval - 1);
3467 req->request.frame_number = frame_number;
3468 }
3469
3470 /*
3471 * We use bounce buffer for requests that needs extra TRB or OUT ZLP. If
3472 * this TRB points to the bounce buffer address, it's a MPS alignment
3473 * TRB. Don't add it to req->remaining calculation.
3474 */
3475 if (trb->bpl == lower_32_bits(dep->dwc->bounce_addr) &&
3476 trb->bph == upper_32_bits(dep->dwc->bounce_addr)) {
3477 trb->ctrl &= ~DWC3_TRB_CTRL_HWO;
3478 return 1;
3479 }
3480
3481 count = trb->size & DWC3_TRB_SIZE_MASK;
3482 req->remaining += count;
3483
3484 if ((trb->ctrl & DWC3_TRB_CTRL_HWO) && status != -ESHUTDOWN)
3485 return 1;
3486
3487 if (event->status & DEPEVT_STATUS_SHORT && !chain)
3488 return 1;
3489
3490 if ((trb->ctrl & DWC3_TRB_CTRL_ISP_IMI) &&
3491 DWC3_TRB_SIZE_TRBSTS(trb->size) == DWC3_TRBSTS_MISSED_ISOC)
3492 return 1;
3493
3494 if ((trb->ctrl & DWC3_TRB_CTRL_IOC) ||
3495 (trb->ctrl & DWC3_TRB_CTRL_LST))
3496 return 1;
3497
3498 return 0;
3499}
3500
3501static int dwc3_gadget_ep_reclaim_trb_sg(struct dwc3_ep *dep,
3502 struct dwc3_request *req, const struct dwc3_event_depevt *event,
3503 int status)
3504{
3505 struct dwc3_trb *trb;
3506 unsigned int num_completed_trbs = req->num_trbs;
3507 unsigned int i;
3508 int ret = 0;
3509
3510 for (i = 0; i < num_completed_trbs; i++) {
3511 trb = &dep->trb_pool[dep->trb_dequeue];
3512
3513 ret = dwc3_gadget_ep_reclaim_completed_trb(dep, req,
3514 trb, event, status,
3515 !!(trb->ctrl & DWC3_TRB_CTRL_CHN));
3516 if (ret)
3517 break;
3518 }
3519
3520 return ret;
3521}
3522
3523static bool dwc3_gadget_ep_request_completed(struct dwc3_request *req)
3524{
3525 return req->num_pending_sgs == 0 && req->num_trbs == 0;
3526}
3527
3528static int dwc3_gadget_ep_cleanup_completed_request(struct dwc3_ep *dep,
3529 const struct dwc3_event_depevt *event,
3530 struct dwc3_request *req, int status)
3531{
3532 int request_status;
3533 int ret;
3534
3535 ret = dwc3_gadget_ep_reclaim_trb_sg(dep, req, event, status);
3536
3537 req->request.actual = req->request.length - req->remaining;
3538
3539 if (!dwc3_gadget_ep_request_completed(req))
3540 goto out;
3541
3542 /*
3543 * The event status only reflects the status of the TRB with IOC set.
3544 * For the requests that don't set interrupt on completion, the driver
3545 * needs to check and return the status of the completed TRBs associated
3546 * with the request. Use the status of the last TRB of the request.
3547 */
3548 if (req->request.no_interrupt) {
3549 struct dwc3_trb *trb;
3550
3551 trb = dwc3_ep_prev_trb(dep, dep->trb_dequeue);
3552 switch (DWC3_TRB_SIZE_TRBSTS(trb->size)) {
3553 case DWC3_TRBSTS_MISSED_ISOC:
3554 /* Isoc endpoint only */
3555 request_status = -EXDEV;
3556 break;
3557 case DWC3_TRB_STS_XFER_IN_PROG:
3558 /* Applicable when End Transfer with ForceRM=0 */
3559 case DWC3_TRBSTS_SETUP_PENDING:
3560 /* Control endpoint only */
3561 case DWC3_TRBSTS_OK:
3562 default:
3563 request_status = 0;
3564 break;
3565 }
3566 } else {
3567 request_status = status;
3568 }
3569
3570 dwc3_gadget_giveback(dep, req, request_status);
3571
3572out:
3573 return ret;
3574}
3575
3576static void dwc3_gadget_ep_cleanup_completed_requests(struct dwc3_ep *dep,
3577 const struct dwc3_event_depevt *event, int status)
3578{
3579 struct dwc3_request *req;
3580
3581 while (!list_empty(&dep->started_list)) {
3582 int ret;
3583
3584 req = next_request(&dep->started_list);
3585 ret = dwc3_gadget_ep_cleanup_completed_request(dep, event,
3586 req, status);
3587 if (ret)
3588 break;
3589 /*
3590 * The endpoint is disabled, let the dwc3_remove_requests()
3591 * handle the cleanup.
3592 */
3593 if (!dep->endpoint.desc)
3594 break;
3595 }
3596}
3597
3598static bool dwc3_gadget_ep_should_continue(struct dwc3_ep *dep)
3599{
3600 struct dwc3_request *req;
3601 struct dwc3 *dwc = dep->dwc;
3602
3603 if (!dep->endpoint.desc || !dwc->pullups_connected ||
3604 !dwc->connected)
3605 return false;
3606
3607 if (!list_empty(&dep->pending_list))
3608 return true;
3609
3610 /*
3611 * We only need to check the first entry of the started list. We can
3612 * assume the completed requests are removed from the started list.
3613 */
3614 req = next_request(&dep->started_list);
3615 if (!req)
3616 return false;
3617
3618 return !dwc3_gadget_ep_request_completed(req);
3619}
3620
3621static void dwc3_gadget_endpoint_frame_from_event(struct dwc3_ep *dep,
3622 const struct dwc3_event_depevt *event)
3623{
3624 dep->frame_number = event->parameters;
3625}
3626
3627static bool dwc3_gadget_endpoint_trbs_complete(struct dwc3_ep *dep,
3628 const struct dwc3_event_depevt *event, int status)
3629{
3630 struct dwc3 *dwc = dep->dwc;
3631 bool no_started_trb = true;
3632
3633 dwc3_gadget_ep_cleanup_completed_requests(dep, event, status);
3634
3635 if (dep->flags & DWC3_EP_END_TRANSFER_PENDING)
3636 goto out;
3637
3638 if (!dep->endpoint.desc)
3639 return no_started_trb;
3640
3641 if (usb_endpoint_xfer_isoc(dep->endpoint.desc) &&
3642 list_empty(&dep->started_list) &&
3643 (list_empty(&dep->pending_list) || status == -EXDEV))
3644 dwc3_stop_active_transfer(dep, true, true);
3645 else if (dwc3_gadget_ep_should_continue(dep))
3646 if (__dwc3_gadget_kick_transfer(dep) == 0)
3647 no_started_trb = false;
3648
3649out:
3650 /*
3651 * WORKAROUND: This is the 2nd half of U1/U2 -> U0 workaround.
3652 * See dwc3_gadget_linksts_change_interrupt() for 1st half.
3653 */
3654 if (DWC3_VER_IS_PRIOR(DWC3, 183A)) {
3655 u32 reg;
3656 int i;
3657
3658 for (i = 0; i < DWC3_ENDPOINTS_NUM; i++) {
3659 dep = dwc->eps[i];
3660
3661 if (!(dep->flags & DWC3_EP_ENABLED))
3662 continue;
3663
3664 if (!list_empty(&dep->started_list))
3665 return no_started_trb;
3666 }
3667
3668 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
3669 reg |= dwc->u1u2;
3670 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
3671
3672 dwc->u1u2 = 0;
3673 }
3674
3675 return no_started_trb;
3676}
3677
3678static void dwc3_gadget_endpoint_transfer_in_progress(struct dwc3_ep *dep,
3679 const struct dwc3_event_depevt *event)
3680{
3681 int status = 0;
3682
3683 if (!dep->endpoint.desc)
3684 return;
3685
3686 if (usb_endpoint_xfer_isoc(dep->endpoint.desc))
3687 dwc3_gadget_endpoint_frame_from_event(dep, event);
3688
3689 if (event->status & DEPEVT_STATUS_BUSERR)
3690 status = -ECONNRESET;
3691
3692 if (event->status & DEPEVT_STATUS_MISSED_ISOC)
3693 status = -EXDEV;
3694
3695 dwc3_gadget_endpoint_trbs_complete(dep, event, status);
3696}
3697
3698static void dwc3_gadget_endpoint_transfer_complete(struct dwc3_ep *dep,
3699 const struct dwc3_event_depevt *event)
3700{
3701 int status = 0;
3702
3703 dep->flags &= ~DWC3_EP_TRANSFER_STARTED;
3704
3705 if (event->status & DEPEVT_STATUS_BUSERR)
3706 status = -ECONNRESET;
3707
3708 if (dwc3_gadget_endpoint_trbs_complete(dep, event, status))
3709 dep->flags &= ~DWC3_EP_WAIT_TRANSFER_COMPLETE;
3710}
3711
3712static void dwc3_gadget_endpoint_transfer_not_ready(struct dwc3_ep *dep,
3713 const struct dwc3_event_depevt *event)
3714{
3715 dwc3_gadget_endpoint_frame_from_event(dep, event);
3716
3717 /*
3718 * The XferNotReady event is generated only once before the endpoint
3719 * starts. It will be generated again when END_TRANSFER command is
3720 * issued. For some controller versions, the XferNotReady event may be
3721 * generated while the END_TRANSFER command is still in process. Ignore
3722 * it and wait for the next XferNotReady event after the command is
3723 * completed.
3724 */
3725 if (dep->flags & DWC3_EP_END_TRANSFER_PENDING)
3726 return;
3727
3728 (void) __dwc3_gadget_start_isoc(dep);
3729}
3730
3731static void dwc3_gadget_endpoint_command_complete(struct dwc3_ep *dep,
3732 const struct dwc3_event_depevt *event)
3733{
3734 u8 cmd = DEPEVT_PARAMETER_CMD(event->parameters);
3735
3736 if (cmd != DWC3_DEPCMD_ENDTRANSFER)
3737 return;
3738
3739 /*
3740 * The END_TRANSFER command will cause the controller to generate a
3741 * NoStream Event, and it's not due to the host DP NoStream rejection.
3742 * Ignore the next NoStream event.
3743 */
3744 if (dep->stream_capable)
3745 dep->flags |= DWC3_EP_IGNORE_NEXT_NOSTREAM;
3746
3747 dep->flags &= ~DWC3_EP_END_TRANSFER_PENDING;
3748 dep->flags &= ~DWC3_EP_TRANSFER_STARTED;
3749 dwc3_gadget_ep_cleanup_cancelled_requests(dep);
3750
3751 if (dep->flags & DWC3_EP_PENDING_CLEAR_STALL) {
3752 struct dwc3 *dwc = dep->dwc;
3753
3754 dep->flags &= ~DWC3_EP_PENDING_CLEAR_STALL;
3755 if (dwc3_send_clear_stall_ep_cmd(dep)) {
3756 struct usb_ep *ep0 = &dwc->eps[0]->endpoint;
3757
3758 dev_err(dwc->dev, "failed to clear STALL on %s\n", dep->name);
3759 if (dwc->delayed_status)
3760 __dwc3_gadget_ep0_set_halt(ep0, 1);
3761 return;
3762 }
3763
3764 dep->flags &= ~(DWC3_EP_STALL | DWC3_EP_WEDGE);
3765 if (dwc->clear_stall_protocol == dep->number)
3766 dwc3_ep0_send_delayed_status(dwc);
3767 }
3768
3769 if ((dep->flags & DWC3_EP_DELAY_START) &&
3770 !usb_endpoint_xfer_isoc(dep->endpoint.desc))
3771 __dwc3_gadget_kick_transfer(dep);
3772
3773 dep->flags &= ~DWC3_EP_DELAY_START;
3774}
3775
3776static void dwc3_gadget_endpoint_stream_event(struct dwc3_ep *dep,
3777 const struct dwc3_event_depevt *event)
3778{
3779 struct dwc3 *dwc = dep->dwc;
3780
3781 if (event->status == DEPEVT_STREAMEVT_FOUND) {
3782 dep->flags |= DWC3_EP_FIRST_STREAM_PRIMED;
3783 goto out;
3784 }
3785
3786 /* Note: NoStream rejection event param value is 0 and not 0xFFFF */
3787 switch (event->parameters) {
3788 case DEPEVT_STREAM_PRIME:
3789 /*
3790 * If the host can properly transition the endpoint state from
3791 * idle to prime after a NoStream rejection, there's no need to
3792 * force restarting the endpoint to reinitiate the stream. To
3793 * simplify the check, assume the host follows the USB spec if
3794 * it primed the endpoint more than once.
3795 */
3796 if (dep->flags & DWC3_EP_FORCE_RESTART_STREAM) {
3797 if (dep->flags & DWC3_EP_FIRST_STREAM_PRIMED)
3798 dep->flags &= ~DWC3_EP_FORCE_RESTART_STREAM;
3799 else
3800 dep->flags |= DWC3_EP_FIRST_STREAM_PRIMED;
3801 }
3802
3803 break;
3804 case DEPEVT_STREAM_NOSTREAM:
3805 if ((dep->flags & DWC3_EP_IGNORE_NEXT_NOSTREAM) ||
3806 !(dep->flags & DWC3_EP_FORCE_RESTART_STREAM) ||
3807 (!DWC3_MST_CAPABLE(&dwc->hwparams) &&
3808 !(dep->flags & DWC3_EP_WAIT_TRANSFER_COMPLETE)))
3809 break;
3810
3811 /*
3812 * If the host rejects a stream due to no active stream, by the
3813 * USB and xHCI spec, the endpoint will be put back to idle
3814 * state. When the host is ready (buffer added/updated), it will
3815 * prime the endpoint to inform the usb device controller. This
3816 * triggers the device controller to issue ERDY to restart the
3817 * stream. However, some hosts don't follow this and keep the
3818 * endpoint in the idle state. No prime will come despite host
3819 * streams are updated, and the device controller will not be
3820 * triggered to generate ERDY to move the next stream data. To
3821 * workaround this and maintain compatibility with various
3822 * hosts, force to reinitiate the stream until the host is ready
3823 * instead of waiting for the host to prime the endpoint.
3824 */
3825 if (DWC3_VER_IS_WITHIN(DWC32, 100A, ANY)) {
3826 unsigned int cmd = DWC3_DGCMD_SET_ENDPOINT_PRIME;
3827
3828 dwc3_send_gadget_generic_command(dwc, cmd, dep->number);
3829 } else {
3830 dep->flags |= DWC3_EP_DELAY_START;
3831 dwc3_stop_active_transfer(dep, true, true);
3832 return;
3833 }
3834 break;
3835 }
3836
3837out:
3838 dep->flags &= ~DWC3_EP_IGNORE_NEXT_NOSTREAM;
3839}
3840
3841static void dwc3_endpoint_interrupt(struct dwc3 *dwc,
3842 const struct dwc3_event_depevt *event)
3843{
3844 struct dwc3_ep *dep;
3845 u8 epnum = event->endpoint_number;
3846
3847 dep = dwc->eps[epnum];
3848
3849 if (!(dep->flags & DWC3_EP_ENABLED)) {
3850 if ((epnum > 1) && !(dep->flags & DWC3_EP_TRANSFER_STARTED))
3851 return;
3852
3853 /* Handle only EPCMDCMPLT when EP disabled */
3854 if ((event->endpoint_event != DWC3_DEPEVT_EPCMDCMPLT) &&
3855 !(epnum <= 1 && event->endpoint_event == DWC3_DEPEVT_XFERCOMPLETE))
3856 return;
3857 }
3858
3859 if (epnum == 0 || epnum == 1) {
3860 dwc3_ep0_interrupt(dwc, event);
3861 return;
3862 }
3863
3864 switch (event->endpoint_event) {
3865 case DWC3_DEPEVT_XFERINPROGRESS:
3866 dwc3_gadget_endpoint_transfer_in_progress(dep, event);
3867 break;
3868 case DWC3_DEPEVT_XFERNOTREADY:
3869 dwc3_gadget_endpoint_transfer_not_ready(dep, event);
3870 break;
3871 case DWC3_DEPEVT_EPCMDCMPLT:
3872 dwc3_gadget_endpoint_command_complete(dep, event);
3873 break;
3874 case DWC3_DEPEVT_XFERCOMPLETE:
3875 dwc3_gadget_endpoint_transfer_complete(dep, event);
3876 break;
3877 case DWC3_DEPEVT_STREAMEVT:
3878 dwc3_gadget_endpoint_stream_event(dep, event);
3879 break;
3880 case DWC3_DEPEVT_RXTXFIFOEVT:
3881 break;
3882 default:
3883 dev_err(dwc->dev, "unknown endpoint event %d\n", event->endpoint_event);
3884 break;
3885 }
3886}
3887
3888static void dwc3_disconnect_gadget(struct dwc3 *dwc)
3889{
3890 if (dwc->async_callbacks && dwc->gadget_driver->disconnect) {
3891 spin_unlock(&dwc->lock);
3892 dwc->gadget_driver->disconnect(dwc->gadget);
3893 spin_lock(&dwc->lock);
3894 }
3895}
3896
3897static void dwc3_suspend_gadget(struct dwc3 *dwc)
3898{
3899 if (dwc->async_callbacks && dwc->gadget_driver->suspend) {
3900 spin_unlock(&dwc->lock);
3901 dwc->gadget_driver->suspend(dwc->gadget);
3902 spin_lock(&dwc->lock);
3903 }
3904}
3905
3906static void dwc3_resume_gadget(struct dwc3 *dwc)
3907{
3908 if (dwc->async_callbacks && dwc->gadget_driver->resume) {
3909 spin_unlock(&dwc->lock);
3910 dwc->gadget_driver->resume(dwc->gadget);
3911 spin_lock(&dwc->lock);
3912 }
3913}
3914
3915static void dwc3_reset_gadget(struct dwc3 *dwc)
3916{
3917 if (!dwc->gadget_driver)
3918 return;
3919
3920 if (dwc->async_callbacks && dwc->gadget->speed != USB_SPEED_UNKNOWN) {
3921 spin_unlock(&dwc->lock);
3922 usb_gadget_udc_reset(dwc->gadget, dwc->gadget_driver);
3923 spin_lock(&dwc->lock);
3924 }
3925}
3926
3927void dwc3_stop_active_transfer(struct dwc3_ep *dep, bool force,
3928 bool interrupt)
3929{
3930 struct dwc3 *dwc = dep->dwc;
3931
3932 /*
3933 * Only issue End Transfer command to the control endpoint of a started
3934 * Data Phase. Typically we should only do so in error cases such as
3935 * invalid/unexpected direction as described in the control transfer
3936 * flow of the programming guide.
3937 */
3938 if (dep->number <= 1 && dwc->ep0state != EP0_DATA_PHASE)
3939 return;
3940
3941 if (interrupt && (dep->flags & DWC3_EP_DELAY_STOP))
3942 return;
3943
3944 if (!(dep->flags & DWC3_EP_TRANSFER_STARTED) ||
3945 (dep->flags & DWC3_EP_END_TRANSFER_PENDING))
3946 return;
3947
3948 /*
3949 * If a Setup packet is received but yet to DMA out, the controller will
3950 * not process the End Transfer command of any endpoint. Polling of its
3951 * DEPCMD.CmdAct may block setting up TRB for Setup packet, causing a
3952 * timeout. Delay issuing the End Transfer command until the Setup TRB is
3953 * prepared.
3954 */
3955 if (dwc->ep0state != EP0_SETUP_PHASE && !dwc->delayed_status) {
3956 dep->flags |= DWC3_EP_DELAY_STOP;
3957 return;
3958 }
3959
3960 /*
3961 * NOTICE: We are violating what the Databook says about the
3962 * EndTransfer command. Ideally we would _always_ wait for the
3963 * EndTransfer Command Completion IRQ, but that's causing too
3964 * much trouble synchronizing between us and gadget driver.
3965 *
3966 * We have discussed this with the IP Provider and it was
3967 * suggested to giveback all requests here.
3968 *
3969 * Note also that a similar handling was tested by Synopsys
3970 * (thanks a lot Paul) and nothing bad has come out of it.
3971 * In short, what we're doing is issuing EndTransfer with
3972 * CMDIOC bit set and delay kicking transfer until the
3973 * EndTransfer command had completed.
3974 *
3975 * As of IP version 3.10a of the DWC_usb3 IP, the controller
3976 * supports a mode to work around the above limitation. The
3977 * software can poll the CMDACT bit in the DEPCMD register
3978 * after issuing a EndTransfer command. This mode is enabled
3979 * by writing GUCTL2[14]. This polling is already done in the
3980 * dwc3_send_gadget_ep_cmd() function so if the mode is
3981 * enabled, the EndTransfer command will have completed upon
3982 * returning from this function.
3983 *
3984 * This mode is NOT available on the DWC_usb31 IP. In this
3985 * case, if the IOC bit is not set, then delay by 1ms
3986 * after issuing the EndTransfer command. This allows for the
3987 * controller to handle the command completely before DWC3
3988 * remove requests attempts to unmap USB request buffers.
3989 */
3990
3991 __dwc3_stop_active_transfer(dep, force, interrupt);
3992}
3993
3994static void dwc3_clear_stall_all_ep(struct dwc3 *dwc)
3995{
3996 u32 epnum;
3997
3998 for (epnum = 1; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
3999 struct dwc3_ep *dep;
4000 int ret;
4001
4002 dep = dwc->eps[epnum];
4003 if (!dep)
4004 continue;
4005
4006 if (!(dep->flags & DWC3_EP_STALL))
4007 continue;
4008
4009 dep->flags &= ~DWC3_EP_STALL;
4010
4011 ret = dwc3_send_clear_stall_ep_cmd(dep);
4012 WARN_ON_ONCE(ret);
4013 }
4014}
4015
4016static void dwc3_gadget_disconnect_interrupt(struct dwc3 *dwc)
4017{
4018 int reg;
4019
4020 dwc->suspended = false;
4021
4022 dwc3_gadget_set_link_state(dwc, DWC3_LINK_STATE_RX_DET);
4023
4024 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
4025 reg &= ~DWC3_DCTL_INITU1ENA;
4026 reg &= ~DWC3_DCTL_INITU2ENA;
4027 dwc3_gadget_dctl_write_safe(dwc, reg);
4028
4029 dwc->connected = false;
4030
4031 dwc3_disconnect_gadget(dwc);
4032
4033 dwc->gadget->speed = USB_SPEED_UNKNOWN;
4034 dwc->setup_packet_pending = false;
4035 dwc->gadget->wakeup_armed = false;
4036 dwc3_gadget_enable_linksts_evts(dwc, false);
4037 usb_gadget_set_state(dwc->gadget, USB_STATE_NOTATTACHED);
4038
4039 dwc3_ep0_reset_state(dwc);
4040
4041 /*
4042 * Request PM idle to address condition where usage count is
4043 * already decremented to zero, but waiting for the disconnect
4044 * interrupt to set dwc->connected to FALSE.
4045 */
4046 pm_request_idle(dwc->dev);
4047}
4048
4049static void dwc3_gadget_reset_interrupt(struct dwc3 *dwc)
4050{
4051 u32 reg;
4052
4053 dwc->suspended = false;
4054
4055 /*
4056 * Ideally, dwc3_reset_gadget() would trigger the function
4057 * drivers to stop any active transfers through ep disable.
4058 * However, for functions which defer ep disable, such as mass
4059 * storage, we will need to rely on the call to stop active
4060 * transfers here, and avoid allowing of request queuing.
4061 */
4062 dwc->connected = false;
4063
4064 /*
4065 * WORKAROUND: DWC3 revisions <1.88a have an issue which
4066 * would cause a missing Disconnect Event if there's a
4067 * pending Setup Packet in the FIFO.
4068 *
4069 * There's no suggested workaround on the official Bug
4070 * report, which states that "unless the driver/application
4071 * is doing any special handling of a disconnect event,
4072 * there is no functional issue".
4073 *
4074 * Unfortunately, it turns out that we _do_ some special
4075 * handling of a disconnect event, namely complete all
4076 * pending transfers, notify gadget driver of the
4077 * disconnection, and so on.
4078 *
4079 * Our suggested workaround is to follow the Disconnect
4080 * Event steps here, instead, based on a setup_packet_pending
4081 * flag. Such flag gets set whenever we have a SETUP_PENDING
4082 * status for EP0 TRBs and gets cleared on XferComplete for the
4083 * same endpoint.
4084 *
4085 * Refers to:
4086 *
4087 * STAR#9000466709: RTL: Device : Disconnect event not
4088 * generated if setup packet pending in FIFO
4089 */
4090 if (DWC3_VER_IS_PRIOR(DWC3, 188A)) {
4091 if (dwc->setup_packet_pending)
4092 dwc3_gadget_disconnect_interrupt(dwc);
4093 }
4094
4095 dwc3_reset_gadget(dwc);
4096
4097 /*
4098 * From SNPS databook section 8.1.2, the EP0 should be in setup
4099 * phase. So ensure that EP0 is in setup phase by issuing a stall
4100 * and restart if EP0 is not in setup phase.
4101 */
4102 dwc3_ep0_reset_state(dwc);
4103
4104 /*
4105 * In the Synopsis DesignWare Cores USB3 Databook Rev. 3.30a
4106 * Section 4.1.2 Table 4-2, it states that during a USB reset, the SW
4107 * needs to ensure that it sends "a DEPENDXFER command for any active
4108 * transfers."
4109 */
4110 dwc3_stop_active_transfers(dwc);
4111 dwc->connected = true;
4112
4113 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
4114 reg &= ~DWC3_DCTL_TSTCTRL_MASK;
4115 dwc3_gadget_dctl_write_safe(dwc, reg);
4116 dwc->test_mode = false;
4117 dwc->gadget->wakeup_armed = false;
4118 dwc3_gadget_enable_linksts_evts(dwc, false);
4119 dwc3_clear_stall_all_ep(dwc);
4120
4121 /* Reset device address to zero */
4122 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
4123 reg &= ~(DWC3_DCFG_DEVADDR_MASK);
4124 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
4125}
4126
4127static void dwc3_gadget_conndone_interrupt(struct dwc3 *dwc)
4128{
4129 struct dwc3_ep *dep;
4130 int ret;
4131 u32 reg;
4132 u8 lanes = 1;
4133 u8 speed;
4134
4135 if (!dwc->softconnect)
4136 return;
4137
4138 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
4139 speed = reg & DWC3_DSTS_CONNECTSPD;
4140 dwc->speed = speed;
4141
4142 if (DWC3_IP_IS(DWC32))
4143 lanes = DWC3_DSTS_CONNLANES(reg) + 1;
4144
4145 dwc->gadget->ssp_rate = USB_SSP_GEN_UNKNOWN;
4146
4147 /*
4148 * RAMClkSel is reset to 0 after USB reset, so it must be reprogrammed
4149 * each time on Connect Done.
4150 *
4151 * Currently we always use the reset value. If any platform
4152 * wants to set this to a different value, we need to add a
4153 * setting and update GCTL.RAMCLKSEL here.
4154 */
4155
4156 switch (speed) {
4157 case DWC3_DSTS_SUPERSPEED_PLUS:
4158 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
4159 dwc->gadget->ep0->maxpacket = 512;
4160 dwc->gadget->speed = USB_SPEED_SUPER_PLUS;
4161
4162 if (lanes > 1)
4163 dwc->gadget->ssp_rate = USB_SSP_GEN_2x2;
4164 else
4165 dwc->gadget->ssp_rate = USB_SSP_GEN_2x1;
4166 break;
4167 case DWC3_DSTS_SUPERSPEED:
4168 /*
4169 * WORKAROUND: DWC3 revisions <1.90a have an issue which
4170 * would cause a missing USB3 Reset event.
4171 *
4172 * In such situations, we should force a USB3 Reset
4173 * event by calling our dwc3_gadget_reset_interrupt()
4174 * routine.
4175 *
4176 * Refers to:
4177 *
4178 * STAR#9000483510: RTL: SS : USB3 reset event may
4179 * not be generated always when the link enters poll
4180 */
4181 if (DWC3_VER_IS_PRIOR(DWC3, 190A))
4182 dwc3_gadget_reset_interrupt(dwc);
4183
4184 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
4185 dwc->gadget->ep0->maxpacket = 512;
4186 dwc->gadget->speed = USB_SPEED_SUPER;
4187
4188 if (lanes > 1) {
4189 dwc->gadget->speed = USB_SPEED_SUPER_PLUS;
4190 dwc->gadget->ssp_rate = USB_SSP_GEN_1x2;
4191 }
4192 break;
4193 case DWC3_DSTS_HIGHSPEED:
4194 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
4195 dwc->gadget->ep0->maxpacket = 64;
4196 dwc->gadget->speed = USB_SPEED_HIGH;
4197 break;
4198 case DWC3_DSTS_FULLSPEED:
4199 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
4200 dwc->gadget->ep0->maxpacket = 64;
4201 dwc->gadget->speed = USB_SPEED_FULL;
4202 break;
4203 }
4204
4205 dwc->eps[1]->endpoint.maxpacket = dwc->gadget->ep0->maxpacket;
4206
4207 /* Enable USB2 LPM Capability */
4208
4209 if (!DWC3_VER_IS_WITHIN(DWC3, ANY, 194A) &&
4210 !dwc->usb2_gadget_lpm_disable &&
4211 (speed != DWC3_DSTS_SUPERSPEED) &&
4212 (speed != DWC3_DSTS_SUPERSPEED_PLUS)) {
4213 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
4214 reg |= DWC3_DCFG_LPM_CAP;
4215 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
4216
4217 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
4218 reg &= ~(DWC3_DCTL_HIRD_THRES_MASK | DWC3_DCTL_L1_HIBER_EN);
4219
4220 reg |= DWC3_DCTL_HIRD_THRES(dwc->hird_threshold |
4221 (dwc->is_utmi_l1_suspend << 4));
4222
4223 /*
4224 * When dwc3 revisions >= 2.40a, LPM Erratum is enabled and
4225 * DCFG.LPMCap is set, core responses with an ACK and the
4226 * BESL value in the LPM token is less than or equal to LPM
4227 * NYET threshold.
4228 */
4229 WARN_ONCE(DWC3_VER_IS_PRIOR(DWC3, 240A) && dwc->has_lpm_erratum,
4230 "LPM Erratum not available on dwc3 revisions < 2.40a\n");
4231
4232 if (dwc->has_lpm_erratum && !DWC3_VER_IS_PRIOR(DWC3, 240A)) {
4233 reg &= ~DWC3_DCTL_NYET_THRES_MASK;
4234 reg |= DWC3_DCTL_NYET_THRES(dwc->lpm_nyet_threshold);
4235 }
4236
4237 dwc3_gadget_dctl_write_safe(dwc, reg);
4238 } else {
4239 if (dwc->usb2_gadget_lpm_disable) {
4240 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
4241 reg &= ~DWC3_DCFG_LPM_CAP;
4242 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
4243 }
4244
4245 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
4246 reg &= ~DWC3_DCTL_HIRD_THRES_MASK;
4247 dwc3_gadget_dctl_write_safe(dwc, reg);
4248 }
4249
4250 dep = dwc->eps[0];
4251 ret = __dwc3_gadget_ep_enable(dep, DWC3_DEPCFG_ACTION_MODIFY);
4252 if (ret) {
4253 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
4254 return;
4255 }
4256
4257 dep = dwc->eps[1];
4258 ret = __dwc3_gadget_ep_enable(dep, DWC3_DEPCFG_ACTION_MODIFY);
4259 if (ret) {
4260 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
4261 return;
4262 }
4263
4264 /*
4265 * Configure PHY via GUSB3PIPECTLn if required.
4266 *
4267 * Update GTXFIFOSIZn
4268 *
4269 * In both cases reset values should be sufficient.
4270 */
4271}
4272
4273static void dwc3_gadget_wakeup_interrupt(struct dwc3 *dwc, unsigned int evtinfo)
4274{
4275 dwc->suspended = false;
4276
4277 /*
4278 * TODO take core out of low power mode when that's
4279 * implemented.
4280 */
4281
4282 if (dwc->async_callbacks && dwc->gadget_driver->resume) {
4283 spin_unlock(&dwc->lock);
4284 dwc->gadget_driver->resume(dwc->gadget);
4285 spin_lock(&dwc->lock);
4286 }
4287
4288 dwc->link_state = evtinfo & DWC3_LINK_STATE_MASK;
4289}
4290
4291static void dwc3_gadget_linksts_change_interrupt(struct dwc3 *dwc,
4292 unsigned int evtinfo)
4293{
4294 enum dwc3_link_state next = evtinfo & DWC3_LINK_STATE_MASK;
4295 unsigned int pwropt;
4296
4297 /*
4298 * WORKAROUND: DWC3 < 2.50a have an issue when configured without
4299 * Hibernation mode enabled which would show up when device detects
4300 * host-initiated U3 exit.
4301 *
4302 * In that case, device will generate a Link State Change Interrupt
4303 * from U3 to RESUME which is only necessary if Hibernation is
4304 * configured in.
4305 *
4306 * There are no functional changes due to such spurious event and we
4307 * just need to ignore it.
4308 *
4309 * Refers to:
4310 *
4311 * STAR#9000570034 RTL: SS Resume event generated in non-Hibernation
4312 * operational mode
4313 */
4314 pwropt = DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1);
4315 if (DWC3_VER_IS_PRIOR(DWC3, 250A) &&
4316 (pwropt != DWC3_GHWPARAMS1_EN_PWROPT_HIB)) {
4317 if ((dwc->link_state == DWC3_LINK_STATE_U3) &&
4318 (next == DWC3_LINK_STATE_RESUME)) {
4319 return;
4320 }
4321 }
4322
4323 /*
4324 * WORKAROUND: DWC3 Revisions <1.83a have an issue which, depending
4325 * on the link partner, the USB session might do multiple entry/exit
4326 * of low power states before a transfer takes place.
4327 *
4328 * Due to this problem, we might experience lower throughput. The
4329 * suggested workaround is to disable DCTL[12:9] bits if we're
4330 * transitioning from U1/U2 to U0 and enable those bits again
4331 * after a transfer completes and there are no pending transfers
4332 * on any of the enabled endpoints.
4333 *
4334 * This is the first half of that workaround.
4335 *
4336 * Refers to:
4337 *
4338 * STAR#9000446952: RTL: Device SS : if U1/U2 ->U0 takes >128us
4339 * core send LGO_Ux entering U0
4340 */
4341 if (DWC3_VER_IS_PRIOR(DWC3, 183A)) {
4342 if (next == DWC3_LINK_STATE_U0) {
4343 u32 u1u2;
4344 u32 reg;
4345
4346 switch (dwc->link_state) {
4347 case DWC3_LINK_STATE_U1:
4348 case DWC3_LINK_STATE_U2:
4349 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
4350 u1u2 = reg & (DWC3_DCTL_INITU2ENA
4351 | DWC3_DCTL_ACCEPTU2ENA
4352 | DWC3_DCTL_INITU1ENA
4353 | DWC3_DCTL_ACCEPTU1ENA);
4354
4355 if (!dwc->u1u2)
4356 dwc->u1u2 = reg & u1u2;
4357
4358 reg &= ~u1u2;
4359
4360 dwc3_gadget_dctl_write_safe(dwc, reg);
4361 break;
4362 default:
4363 /* do nothing */
4364 break;
4365 }
4366 }
4367 }
4368
4369 switch (next) {
4370 case DWC3_LINK_STATE_U0:
4371 if (dwc->gadget->wakeup_armed) {
4372 dwc3_gadget_enable_linksts_evts(dwc, false);
4373 dwc3_resume_gadget(dwc);
4374 dwc->suspended = false;
4375 }
4376 break;
4377 case DWC3_LINK_STATE_U1:
4378 if (dwc->speed == USB_SPEED_SUPER)
4379 dwc3_suspend_gadget(dwc);
4380 break;
4381 case DWC3_LINK_STATE_U2:
4382 case DWC3_LINK_STATE_U3:
4383 dwc3_suspend_gadget(dwc);
4384 break;
4385 case DWC3_LINK_STATE_RESUME:
4386 dwc3_resume_gadget(dwc);
4387 break;
4388 default:
4389 /* do nothing */
4390 break;
4391 }
4392
4393 dwc->link_state = next;
4394}
4395
4396static void dwc3_gadget_suspend_interrupt(struct dwc3 *dwc,
4397 unsigned int evtinfo)
4398{
4399 enum dwc3_link_state next = evtinfo & DWC3_LINK_STATE_MASK;
4400
4401 if (!dwc->suspended && next == DWC3_LINK_STATE_U3) {
4402 dwc->suspended = true;
4403 dwc3_suspend_gadget(dwc);
4404 }
4405
4406 dwc->link_state = next;
4407}
4408
4409static void dwc3_gadget_interrupt(struct dwc3 *dwc,
4410 const struct dwc3_event_devt *event)
4411{
4412 switch (event->type) {
4413 case DWC3_DEVICE_EVENT_DISCONNECT:
4414 dwc3_gadget_disconnect_interrupt(dwc);
4415 break;
4416 case DWC3_DEVICE_EVENT_RESET:
4417 dwc3_gadget_reset_interrupt(dwc);
4418 break;
4419 case DWC3_DEVICE_EVENT_CONNECT_DONE:
4420 dwc3_gadget_conndone_interrupt(dwc);
4421 break;
4422 case DWC3_DEVICE_EVENT_WAKEUP:
4423 dwc3_gadget_wakeup_interrupt(dwc, event->event_info);
4424 break;
4425 case DWC3_DEVICE_EVENT_HIBER_REQ:
4426 dev_WARN_ONCE(dwc->dev, true, "unexpected hibernation event\n");
4427 break;
4428 case DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE:
4429 dwc3_gadget_linksts_change_interrupt(dwc, event->event_info);
4430 break;
4431 case DWC3_DEVICE_EVENT_SUSPEND:
4432 /* It changed to be suspend event for version 2.30a and above */
4433 if (!DWC3_VER_IS_PRIOR(DWC3, 230A))
4434 dwc3_gadget_suspend_interrupt(dwc, event->event_info);
4435 break;
4436 case DWC3_DEVICE_EVENT_SOF:
4437 case DWC3_DEVICE_EVENT_ERRATIC_ERROR:
4438 case DWC3_DEVICE_EVENT_CMD_CMPL:
4439 case DWC3_DEVICE_EVENT_OVERFLOW:
4440 break;
4441 default:
4442 dev_WARN(dwc->dev, "UNKNOWN IRQ %d\n", event->type);
4443 }
4444}
4445
4446static void dwc3_process_event_entry(struct dwc3 *dwc,
4447 const union dwc3_event *event)
4448{
4449 trace_dwc3_event(event->raw, dwc);
4450
4451 if (!event->type.is_devspec)
4452 dwc3_endpoint_interrupt(dwc, &event->depevt);
4453 else if (event->type.type == DWC3_EVENT_TYPE_DEV)
4454 dwc3_gadget_interrupt(dwc, &event->devt);
4455 else
4456 dev_err(dwc->dev, "UNKNOWN IRQ type %d\n", event->raw);
4457}
4458
4459static irqreturn_t dwc3_process_event_buf(struct dwc3_event_buffer *evt)
4460{
4461 struct dwc3 *dwc = evt->dwc;
4462 irqreturn_t ret = IRQ_NONE;
4463 int left;
4464
4465 left = evt->count;
4466
4467 if (!(evt->flags & DWC3_EVENT_PENDING))
4468 return IRQ_NONE;
4469
4470 while (left > 0) {
4471 union dwc3_event event;
4472
4473 event.raw = *(u32 *) (evt->cache + evt->lpos);
4474
4475 dwc3_process_event_entry(dwc, &event);
4476
4477 /*
4478 * FIXME we wrap around correctly to the next entry as
4479 * almost all entries are 4 bytes in size. There is one
4480 * entry which has 12 bytes which is a regular entry
4481 * followed by 8 bytes data. ATM I don't know how
4482 * things are organized if we get next to the a
4483 * boundary so I worry about that once we try to handle
4484 * that.
4485 */
4486 evt->lpos = (evt->lpos + 4) % evt->length;
4487 left -= 4;
4488 }
4489
4490 evt->count = 0;
4491 ret = IRQ_HANDLED;
4492
4493 /* Unmask interrupt */
4494 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0),
4495 DWC3_GEVNTSIZ_SIZE(evt->length));
4496
4497 evt->flags &= ~DWC3_EVENT_PENDING;
4498 /*
4499 * Add an explicit write memory barrier to make sure that the update of
4500 * clearing DWC3_EVENT_PENDING is observed in dwc3_check_event_buf()
4501 */
4502 wmb();
4503
4504 if (dwc->imod_interval) {
4505 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), DWC3_GEVNTCOUNT_EHB);
4506 dwc3_writel(dwc->regs, DWC3_DEV_IMOD(0), dwc->imod_interval);
4507 }
4508
4509 return ret;
4510}
4511
4512static irqreturn_t dwc3_thread_interrupt(int irq, void *_evt)
4513{
4514 struct dwc3_event_buffer *evt = _evt;
4515 struct dwc3 *dwc = evt->dwc;
4516 unsigned long flags;
4517 irqreturn_t ret = IRQ_NONE;
4518
4519 local_bh_disable();
4520 spin_lock_irqsave(&dwc->lock, flags);
4521 ret = dwc3_process_event_buf(evt);
4522 spin_unlock_irqrestore(&dwc->lock, flags);
4523 local_bh_enable();
4524
4525 return ret;
4526}
4527
4528static irqreturn_t dwc3_check_event_buf(struct dwc3_event_buffer *evt)
4529{
4530 struct dwc3 *dwc = evt->dwc;
4531 u32 amount;
4532 u32 count;
4533
4534 if (pm_runtime_suspended(dwc->dev)) {
4535 dwc->pending_events = true;
4536 /*
4537 * Trigger runtime resume. The get() function will be balanced
4538 * after processing the pending events in dwc3_process_pending
4539 * events().
4540 */
4541 pm_runtime_get(dwc->dev);
4542 disable_irq_nosync(dwc->irq_gadget);
4543 return IRQ_HANDLED;
4544 }
4545
4546 /*
4547 * With PCIe legacy interrupt, test shows that top-half irq handler can
4548 * be called again after HW interrupt deassertion. Check if bottom-half
4549 * irq event handler completes before caching new event to prevent
4550 * losing events.
4551 */
4552 if (evt->flags & DWC3_EVENT_PENDING)
4553 return IRQ_HANDLED;
4554
4555 count = dwc3_readl(dwc->regs, DWC3_GEVNTCOUNT(0));
4556 count &= DWC3_GEVNTCOUNT_MASK;
4557 if (!count)
4558 return IRQ_NONE;
4559
4560 evt->count = count;
4561 evt->flags |= DWC3_EVENT_PENDING;
4562
4563 /* Mask interrupt */
4564 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0),
4565 DWC3_GEVNTSIZ_INTMASK | DWC3_GEVNTSIZ_SIZE(evt->length));
4566
4567 amount = min(count, evt->length - evt->lpos);
4568 memcpy(evt->cache + evt->lpos, evt->buf + evt->lpos, amount);
4569
4570 if (amount < count)
4571 memcpy(evt->cache, evt->buf, count - amount);
4572
4573 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), count);
4574
4575 return IRQ_WAKE_THREAD;
4576}
4577
4578static irqreturn_t dwc3_interrupt(int irq, void *_evt)
4579{
4580 struct dwc3_event_buffer *evt = _evt;
4581
4582 return dwc3_check_event_buf(evt);
4583}
4584
4585static int dwc3_gadget_get_irq(struct dwc3 *dwc)
4586{
4587 struct platform_device *dwc3_pdev = to_platform_device(dwc->dev);
4588 int irq;
4589
4590 irq = platform_get_irq_byname_optional(dwc3_pdev, "peripheral");
4591 if (irq > 0)
4592 goto out;
4593
4594 if (irq == -EPROBE_DEFER)
4595 goto out;
4596
4597 irq = platform_get_irq_byname_optional(dwc3_pdev, "dwc_usb3");
4598 if (irq > 0)
4599 goto out;
4600
4601 if (irq == -EPROBE_DEFER)
4602 goto out;
4603
4604 irq = platform_get_irq(dwc3_pdev, 0);
4605
4606out:
4607 return irq;
4608}
4609
4610static void dwc_gadget_release(struct device *dev)
4611{
4612 struct usb_gadget *gadget = container_of(dev, struct usb_gadget, dev);
4613
4614 kfree(gadget);
4615}
4616
4617/**
4618 * dwc3_gadget_init - initializes gadget related registers
4619 * @dwc: pointer to our controller context structure
4620 *
4621 * Returns 0 on success otherwise negative errno.
4622 */
4623int dwc3_gadget_init(struct dwc3 *dwc)
4624{
4625 int ret;
4626 int irq;
4627 struct device *dev;
4628
4629 irq = dwc3_gadget_get_irq(dwc);
4630 if (irq < 0) {
4631 ret = irq;
4632 goto err0;
4633 }
4634
4635 dwc->irq_gadget = irq;
4636
4637 dwc->ep0_trb = dma_alloc_coherent(dwc->sysdev,
4638 sizeof(*dwc->ep0_trb) * 2,
4639 &dwc->ep0_trb_addr, GFP_KERNEL);
4640 if (!dwc->ep0_trb) {
4641 dev_err(dwc->dev, "failed to allocate ep0 trb\n");
4642 ret = -ENOMEM;
4643 goto err0;
4644 }
4645
4646 dwc->setup_buf = kzalloc(DWC3_EP0_SETUP_SIZE, GFP_KERNEL);
4647 if (!dwc->setup_buf) {
4648 ret = -ENOMEM;
4649 goto err1;
4650 }
4651
4652 dwc->bounce = dma_alloc_coherent(dwc->sysdev, DWC3_BOUNCE_SIZE,
4653 &dwc->bounce_addr, GFP_KERNEL);
4654 if (!dwc->bounce) {
4655 ret = -ENOMEM;
4656 goto err2;
4657 }
4658
4659 init_completion(&dwc->ep0_in_setup);
4660 dwc->gadget = kzalloc(sizeof(struct usb_gadget), GFP_KERNEL);
4661 if (!dwc->gadget) {
4662 ret = -ENOMEM;
4663 goto err3;
4664 }
4665
4666
4667 usb_initialize_gadget(dwc->dev, dwc->gadget, dwc_gadget_release);
4668 dev = &dwc->gadget->dev;
4669 dev->platform_data = dwc;
4670 dwc->gadget->ops = &dwc3_gadget_ops;
4671 dwc->gadget->speed = USB_SPEED_UNKNOWN;
4672 dwc->gadget->ssp_rate = USB_SSP_GEN_UNKNOWN;
4673 dwc->gadget->sg_supported = true;
4674 dwc->gadget->name = "dwc3-gadget";
4675 dwc->gadget->lpm_capable = !dwc->usb2_gadget_lpm_disable;
4676 dwc->gadget->wakeup_capable = true;
4677
4678 /*
4679 * FIXME We might be setting max_speed to <SUPER, however versions
4680 * <2.20a of dwc3 have an issue with metastability (documented
4681 * elsewhere in this driver) which tells us we can't set max speed to
4682 * anything lower than SUPER.
4683 *
4684 * Because gadget.max_speed is only used by composite.c and function
4685 * drivers (i.e. it won't go into dwc3's registers) we are allowing this
4686 * to happen so we avoid sending SuperSpeed Capability descriptor
4687 * together with our BOS descriptor as that could confuse host into
4688 * thinking we can handle super speed.
4689 *
4690 * Note that, in fact, we won't even support GetBOS requests when speed
4691 * is less than super speed because we don't have means, yet, to tell
4692 * composite.c that we are USB 2.0 + LPM ECN.
4693 */
4694 if (DWC3_VER_IS_PRIOR(DWC3, 220A) &&
4695 !dwc->dis_metastability_quirk)
4696 dev_info(dwc->dev, "changing max_speed on rev %08x\n",
4697 dwc->revision);
4698
4699 dwc->gadget->max_speed = dwc->maximum_speed;
4700 dwc->gadget->max_ssp_rate = dwc->max_ssp_rate;
4701
4702 /*
4703 * REVISIT: Here we should clear all pending IRQs to be
4704 * sure we're starting from a well known location.
4705 */
4706
4707 ret = dwc3_gadget_init_endpoints(dwc, dwc->num_eps);
4708 if (ret)
4709 goto err4;
4710
4711 ret = usb_add_gadget(dwc->gadget);
4712 if (ret) {
4713 dev_err(dwc->dev, "failed to add gadget\n");
4714 goto err5;
4715 }
4716
4717 if (DWC3_IP_IS(DWC32) && dwc->maximum_speed == USB_SPEED_SUPER_PLUS)
4718 dwc3_gadget_set_ssp_rate(dwc->gadget, dwc->max_ssp_rate);
4719 else
4720 dwc3_gadget_set_speed(dwc->gadget, dwc->maximum_speed);
4721
4722 /* No system wakeup if no gadget driver bound */
4723 if (dwc->sys_wakeup)
4724 device_wakeup_disable(dwc->sysdev);
4725
4726 return 0;
4727
4728err5:
4729 dwc3_gadget_free_endpoints(dwc);
4730err4:
4731 usb_put_gadget(dwc->gadget);
4732 dwc->gadget = NULL;
4733err3:
4734 dma_free_coherent(dwc->sysdev, DWC3_BOUNCE_SIZE, dwc->bounce,
4735 dwc->bounce_addr);
4736
4737err2:
4738 kfree(dwc->setup_buf);
4739
4740err1:
4741 dma_free_coherent(dwc->sysdev, sizeof(*dwc->ep0_trb) * 2,
4742 dwc->ep0_trb, dwc->ep0_trb_addr);
4743
4744err0:
4745 return ret;
4746}
4747
4748/* -------------------------------------------------------------------------- */
4749
4750void dwc3_gadget_exit(struct dwc3 *dwc)
4751{
4752 if (!dwc->gadget)
4753 return;
4754
4755 dwc3_enable_susphy(dwc, false);
4756 usb_del_gadget(dwc->gadget);
4757 dwc3_gadget_free_endpoints(dwc);
4758 usb_put_gadget(dwc->gadget);
4759 dma_free_coherent(dwc->sysdev, DWC3_BOUNCE_SIZE, dwc->bounce,
4760 dwc->bounce_addr);
4761 kfree(dwc->setup_buf);
4762 dma_free_coherent(dwc->sysdev, sizeof(*dwc->ep0_trb) * 2,
4763 dwc->ep0_trb, dwc->ep0_trb_addr);
4764}
4765
4766int dwc3_gadget_suspend(struct dwc3 *dwc)
4767{
4768 unsigned long flags;
4769 int ret;
4770
4771 ret = dwc3_gadget_soft_disconnect(dwc);
4772 if (ret)
4773 goto err;
4774
4775 spin_lock_irqsave(&dwc->lock, flags);
4776 if (dwc->gadget_driver)
4777 dwc3_disconnect_gadget(dwc);
4778 spin_unlock_irqrestore(&dwc->lock, flags);
4779
4780 return 0;
4781
4782err:
4783 /*
4784 * Attempt to reset the controller's state. Likely no
4785 * communication can be established until the host
4786 * performs a port reset.
4787 */
4788 if (dwc->softconnect)
4789 dwc3_gadget_soft_connect(dwc);
4790
4791 return ret;
4792}
4793
4794int dwc3_gadget_resume(struct dwc3 *dwc)
4795{
4796 if (!dwc->gadget_driver || !dwc->softconnect)
4797 return 0;
4798
4799 return dwc3_gadget_soft_connect(dwc);
4800}
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * gadget.c - DesignWare USB3 DRD Controller Gadget Framework Link
4 *
5 * Copyright (C) 2010-2011 Texas Instruments Incorporated - https://www.ti.com
6 *
7 * Authors: Felipe Balbi <balbi@ti.com>,
8 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
9 */
10
11#include <linux/kernel.h>
12#include <linux/delay.h>
13#include <linux/slab.h>
14#include <linux/spinlock.h>
15#include <linux/platform_device.h>
16#include <linux/pm_runtime.h>
17#include <linux/interrupt.h>
18#include <linux/io.h>
19#include <linux/list.h>
20#include <linux/dma-mapping.h>
21
22#include <linux/usb/ch9.h>
23#include <linux/usb/gadget.h>
24
25#include "debug.h"
26#include "core.h"
27#include "gadget.h"
28#include "io.h"
29
30#define DWC3_ALIGN_FRAME(d, n) (((d)->frame_number + ((d)->interval * (n))) \
31 & ~((d)->interval - 1))
32
33/**
34 * dwc3_gadget_set_test_mode - enables usb2 test modes
35 * @dwc: pointer to our context structure
36 * @mode: the mode to set (J, K SE0 NAK, Force Enable)
37 *
38 * Caller should take care of locking. This function will return 0 on
39 * success or -EINVAL if wrong Test Selector is passed.
40 */
41int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode)
42{
43 u32 reg;
44
45 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
46 reg &= ~DWC3_DCTL_TSTCTRL_MASK;
47
48 switch (mode) {
49 case USB_TEST_J:
50 case USB_TEST_K:
51 case USB_TEST_SE0_NAK:
52 case USB_TEST_PACKET:
53 case USB_TEST_FORCE_ENABLE:
54 reg |= mode << 1;
55 break;
56 default:
57 return -EINVAL;
58 }
59
60 dwc3_gadget_dctl_write_safe(dwc, reg);
61
62 return 0;
63}
64
65/**
66 * dwc3_gadget_get_link_state - gets current state of usb link
67 * @dwc: pointer to our context structure
68 *
69 * Caller should take care of locking. This function will
70 * return the link state on success (>= 0) or -ETIMEDOUT.
71 */
72int dwc3_gadget_get_link_state(struct dwc3 *dwc)
73{
74 u32 reg;
75
76 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
77
78 return DWC3_DSTS_USBLNKST(reg);
79}
80
81/**
82 * dwc3_gadget_set_link_state - sets usb link to a particular state
83 * @dwc: pointer to our context structure
84 * @state: the state to put link into
85 *
86 * Caller should take care of locking. This function will
87 * return 0 on success or -ETIMEDOUT.
88 */
89int dwc3_gadget_set_link_state(struct dwc3 *dwc, enum dwc3_link_state state)
90{
91 int retries = 10000;
92 u32 reg;
93
94 /*
95 * Wait until device controller is ready. Only applies to 1.94a and
96 * later RTL.
97 */
98 if (!DWC3_VER_IS_PRIOR(DWC3, 194A)) {
99 while (--retries) {
100 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
101 if (reg & DWC3_DSTS_DCNRD)
102 udelay(5);
103 else
104 break;
105 }
106
107 if (retries <= 0)
108 return -ETIMEDOUT;
109 }
110
111 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
112 reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;
113
114 /* set no action before sending new link state change */
115 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
116
117 /* set requested state */
118 reg |= DWC3_DCTL_ULSTCHNGREQ(state);
119 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
120
121 /*
122 * The following code is racy when called from dwc3_gadget_wakeup,
123 * and is not needed, at least on newer versions
124 */
125 if (!DWC3_VER_IS_PRIOR(DWC3, 194A))
126 return 0;
127
128 /* wait for a change in DSTS */
129 retries = 10000;
130 while (--retries) {
131 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
132
133 if (DWC3_DSTS_USBLNKST(reg) == state)
134 return 0;
135
136 udelay(5);
137 }
138
139 return -ETIMEDOUT;
140}
141
142static void dwc3_ep0_reset_state(struct dwc3 *dwc)
143{
144 unsigned int dir;
145
146 if (dwc->ep0state != EP0_SETUP_PHASE) {
147 dir = !!dwc->ep0_expect_in;
148 if (dwc->ep0state == EP0_DATA_PHASE)
149 dwc3_ep0_end_control_data(dwc, dwc->eps[dir]);
150 else
151 dwc3_ep0_end_control_data(dwc, dwc->eps[!dir]);
152
153 dwc->eps[0]->trb_enqueue = 0;
154 dwc->eps[1]->trb_enqueue = 0;
155
156 dwc3_ep0_stall_and_restart(dwc);
157 }
158}
159
160/**
161 * dwc3_ep_inc_trb - increment a trb index.
162 * @index: Pointer to the TRB index to increment.
163 *
164 * The index should never point to the link TRB. After incrementing,
165 * if it is point to the link TRB, wrap around to the beginning. The
166 * link TRB is always at the last TRB entry.
167 */
168static void dwc3_ep_inc_trb(u8 *index)
169{
170 (*index)++;
171 if (*index == (DWC3_TRB_NUM - 1))
172 *index = 0;
173}
174
175/**
176 * dwc3_ep_inc_enq - increment endpoint's enqueue pointer
177 * @dep: The endpoint whose enqueue pointer we're incrementing
178 */
179static void dwc3_ep_inc_enq(struct dwc3_ep *dep)
180{
181 dwc3_ep_inc_trb(&dep->trb_enqueue);
182}
183
184/**
185 * dwc3_ep_inc_deq - increment endpoint's dequeue pointer
186 * @dep: The endpoint whose enqueue pointer we're incrementing
187 */
188static void dwc3_ep_inc_deq(struct dwc3_ep *dep)
189{
190 dwc3_ep_inc_trb(&dep->trb_dequeue);
191}
192
193static void dwc3_gadget_del_and_unmap_request(struct dwc3_ep *dep,
194 struct dwc3_request *req, int status)
195{
196 struct dwc3 *dwc = dep->dwc;
197
198 list_del(&req->list);
199 req->remaining = 0;
200 req->needs_extra_trb = false;
201 req->num_trbs = 0;
202
203 if (req->request.status == -EINPROGRESS)
204 req->request.status = status;
205
206 if (req->trb)
207 usb_gadget_unmap_request_by_dev(dwc->sysdev,
208 &req->request, req->direction);
209
210 req->trb = NULL;
211 trace_dwc3_gadget_giveback(req);
212
213 if (dep->number > 1)
214 pm_runtime_put(dwc->dev);
215}
216
217/**
218 * dwc3_gadget_giveback - call struct usb_request's ->complete callback
219 * @dep: The endpoint to whom the request belongs to
220 * @req: The request we're giving back
221 * @status: completion code for the request
222 *
223 * Must be called with controller's lock held and interrupts disabled. This
224 * function will unmap @req and call its ->complete() callback to notify upper
225 * layers that it has completed.
226 */
227void dwc3_gadget_giveback(struct dwc3_ep *dep, struct dwc3_request *req,
228 int status)
229{
230 struct dwc3 *dwc = dep->dwc;
231
232 dwc3_gadget_del_and_unmap_request(dep, req, status);
233 req->status = DWC3_REQUEST_STATUS_COMPLETED;
234
235 spin_unlock(&dwc->lock);
236 usb_gadget_giveback_request(&dep->endpoint, &req->request);
237 spin_lock(&dwc->lock);
238}
239
240/**
241 * dwc3_send_gadget_generic_command - issue a generic command for the controller
242 * @dwc: pointer to the controller context
243 * @cmd: the command to be issued
244 * @param: command parameter
245 *
246 * Caller should take care of locking. Issue @cmd with a given @param to @dwc
247 * and wait for its completion.
248 */
249int dwc3_send_gadget_generic_command(struct dwc3 *dwc, unsigned int cmd,
250 u32 param)
251{
252 u32 timeout = 500;
253 int status = 0;
254 int ret = 0;
255 u32 reg;
256
257 dwc3_writel(dwc->regs, DWC3_DGCMDPAR, param);
258 dwc3_writel(dwc->regs, DWC3_DGCMD, cmd | DWC3_DGCMD_CMDACT);
259
260 do {
261 reg = dwc3_readl(dwc->regs, DWC3_DGCMD);
262 if (!(reg & DWC3_DGCMD_CMDACT)) {
263 status = DWC3_DGCMD_STATUS(reg);
264 if (status)
265 ret = -EINVAL;
266 break;
267 }
268 } while (--timeout);
269
270 if (!timeout) {
271 ret = -ETIMEDOUT;
272 status = -ETIMEDOUT;
273 }
274
275 trace_dwc3_gadget_generic_cmd(cmd, param, status);
276
277 return ret;
278}
279
280static int __dwc3_gadget_wakeup(struct dwc3 *dwc, bool async);
281
282/**
283 * dwc3_send_gadget_ep_cmd - issue an endpoint command
284 * @dep: the endpoint to which the command is going to be issued
285 * @cmd: the command to be issued
286 * @params: parameters to the command
287 *
288 * Caller should handle locking. This function will issue @cmd with given
289 * @params to @dep and wait for its completion.
290 */
291int dwc3_send_gadget_ep_cmd(struct dwc3_ep *dep, unsigned int cmd,
292 struct dwc3_gadget_ep_cmd_params *params)
293{
294 const struct usb_endpoint_descriptor *desc = dep->endpoint.desc;
295 struct dwc3 *dwc = dep->dwc;
296 u32 timeout = 5000;
297 u32 saved_config = 0;
298 u32 reg;
299
300 int cmd_status = 0;
301 int ret = -EINVAL;
302
303 /*
304 * When operating in USB 2.0 speeds (HS/FS), if GUSB2PHYCFG.ENBLSLPM or
305 * GUSB2PHYCFG.SUSPHY is set, it must be cleared before issuing an
306 * endpoint command.
307 *
308 * Save and clear both GUSB2PHYCFG.ENBLSLPM and GUSB2PHYCFG.SUSPHY
309 * settings. Restore them after the command is completed.
310 *
311 * DWC_usb3 3.30a and DWC_usb31 1.90a programming guide section 3.2.2
312 */
313 if (dwc->gadget->speed <= USB_SPEED_HIGH ||
314 DWC3_DEPCMD_CMD(cmd) == DWC3_DEPCMD_ENDTRANSFER) {
315 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
316 if (unlikely(reg & DWC3_GUSB2PHYCFG_SUSPHY)) {
317 saved_config |= DWC3_GUSB2PHYCFG_SUSPHY;
318 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
319 }
320
321 if (reg & DWC3_GUSB2PHYCFG_ENBLSLPM) {
322 saved_config |= DWC3_GUSB2PHYCFG_ENBLSLPM;
323 reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM;
324 }
325
326 if (saved_config)
327 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
328 }
329
330 if (DWC3_DEPCMD_CMD(cmd) == DWC3_DEPCMD_STARTTRANSFER) {
331 int link_state;
332
333 /*
334 * Initiate remote wakeup if the link state is in U3 when
335 * operating in SS/SSP or L1/L2 when operating in HS/FS. If the
336 * link state is in U1/U2, no remote wakeup is needed. The Start
337 * Transfer command will initiate the link recovery.
338 */
339 link_state = dwc3_gadget_get_link_state(dwc);
340 switch (link_state) {
341 case DWC3_LINK_STATE_U2:
342 if (dwc->gadget->speed >= USB_SPEED_SUPER)
343 break;
344
345 fallthrough;
346 case DWC3_LINK_STATE_U3:
347 ret = __dwc3_gadget_wakeup(dwc, false);
348 dev_WARN_ONCE(dwc->dev, ret, "wakeup failed --> %d\n",
349 ret);
350 break;
351 }
352 }
353
354 /*
355 * For some commands such as Update Transfer command, DEPCMDPARn
356 * registers are reserved. Since the driver often sends Update Transfer
357 * command, don't write to DEPCMDPARn to avoid register write delays and
358 * improve performance.
359 */
360 if (DWC3_DEPCMD_CMD(cmd) != DWC3_DEPCMD_UPDATETRANSFER) {
361 dwc3_writel(dep->regs, DWC3_DEPCMDPAR0, params->param0);
362 dwc3_writel(dep->regs, DWC3_DEPCMDPAR1, params->param1);
363 dwc3_writel(dep->regs, DWC3_DEPCMDPAR2, params->param2);
364 }
365
366 /*
367 * Synopsys Databook 2.60a states in section 6.3.2.5.6 of that if we're
368 * not relying on XferNotReady, we can make use of a special "No
369 * Response Update Transfer" command where we should clear both CmdAct
370 * and CmdIOC bits.
371 *
372 * With this, we don't need to wait for command completion and can
373 * straight away issue further commands to the endpoint.
374 *
375 * NOTICE: We're making an assumption that control endpoints will never
376 * make use of Update Transfer command. This is a safe assumption
377 * because we can never have more than one request at a time with
378 * Control Endpoints. If anybody changes that assumption, this chunk
379 * needs to be updated accordingly.
380 */
381 if (DWC3_DEPCMD_CMD(cmd) == DWC3_DEPCMD_UPDATETRANSFER &&
382 !usb_endpoint_xfer_isoc(desc))
383 cmd &= ~(DWC3_DEPCMD_CMDIOC | DWC3_DEPCMD_CMDACT);
384 else
385 cmd |= DWC3_DEPCMD_CMDACT;
386
387 dwc3_writel(dep->regs, DWC3_DEPCMD, cmd);
388
389 if (!(cmd & DWC3_DEPCMD_CMDACT) ||
390 (DWC3_DEPCMD_CMD(cmd) == DWC3_DEPCMD_ENDTRANSFER &&
391 !(cmd & DWC3_DEPCMD_CMDIOC))) {
392 ret = 0;
393 goto skip_status;
394 }
395
396 do {
397 reg = dwc3_readl(dep->regs, DWC3_DEPCMD);
398 if (!(reg & DWC3_DEPCMD_CMDACT)) {
399 cmd_status = DWC3_DEPCMD_STATUS(reg);
400
401 switch (cmd_status) {
402 case 0:
403 ret = 0;
404 break;
405 case DEPEVT_TRANSFER_NO_RESOURCE:
406 dev_WARN(dwc->dev, "No resource for %s\n",
407 dep->name);
408 ret = -EINVAL;
409 break;
410 case DEPEVT_TRANSFER_BUS_EXPIRY:
411 /*
412 * SW issues START TRANSFER command to
413 * isochronous ep with future frame interval. If
414 * future interval time has already passed when
415 * core receives the command, it will respond
416 * with an error status of 'Bus Expiry'.
417 *
418 * Instead of always returning -EINVAL, let's
419 * give a hint to the gadget driver that this is
420 * the case by returning -EAGAIN.
421 */
422 ret = -EAGAIN;
423 break;
424 default:
425 dev_WARN(dwc->dev, "UNKNOWN cmd status\n");
426 }
427
428 break;
429 }
430 } while (--timeout);
431
432 if (timeout == 0) {
433 ret = -ETIMEDOUT;
434 cmd_status = -ETIMEDOUT;
435 }
436
437skip_status:
438 trace_dwc3_gadget_ep_cmd(dep, cmd, params, cmd_status);
439
440 if (DWC3_DEPCMD_CMD(cmd) == DWC3_DEPCMD_STARTTRANSFER) {
441 if (ret == 0)
442 dep->flags |= DWC3_EP_TRANSFER_STARTED;
443
444 if (ret != -ETIMEDOUT)
445 dwc3_gadget_ep_get_transfer_index(dep);
446 }
447
448 if (saved_config) {
449 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
450 reg |= saved_config;
451 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
452 }
453
454 return ret;
455}
456
457static int dwc3_send_clear_stall_ep_cmd(struct dwc3_ep *dep)
458{
459 struct dwc3 *dwc = dep->dwc;
460 struct dwc3_gadget_ep_cmd_params params;
461 u32 cmd = DWC3_DEPCMD_CLEARSTALL;
462
463 /*
464 * As of core revision 2.60a the recommended programming model
465 * is to set the ClearPendIN bit when issuing a Clear Stall EP
466 * command for IN endpoints. This is to prevent an issue where
467 * some (non-compliant) hosts may not send ACK TPs for pending
468 * IN transfers due to a mishandled error condition. Synopsys
469 * STAR 9000614252.
470 */
471 if (dep->direction &&
472 !DWC3_VER_IS_PRIOR(DWC3, 260A) &&
473 (dwc->gadget->speed >= USB_SPEED_SUPER))
474 cmd |= DWC3_DEPCMD_CLEARPENDIN;
475
476 memset(¶ms, 0, sizeof(params));
477
478 return dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms);
479}
480
481static dma_addr_t dwc3_trb_dma_offset(struct dwc3_ep *dep,
482 struct dwc3_trb *trb)
483{
484 u32 offset = (char *) trb - (char *) dep->trb_pool;
485
486 return dep->trb_pool_dma + offset;
487}
488
489static int dwc3_alloc_trb_pool(struct dwc3_ep *dep)
490{
491 struct dwc3 *dwc = dep->dwc;
492
493 if (dep->trb_pool)
494 return 0;
495
496 dep->trb_pool = dma_alloc_coherent(dwc->sysdev,
497 sizeof(struct dwc3_trb) * DWC3_TRB_NUM,
498 &dep->trb_pool_dma, GFP_KERNEL);
499 if (!dep->trb_pool) {
500 dev_err(dep->dwc->dev, "failed to allocate trb pool for %s\n",
501 dep->name);
502 return -ENOMEM;
503 }
504
505 return 0;
506}
507
508static void dwc3_free_trb_pool(struct dwc3_ep *dep)
509{
510 struct dwc3 *dwc = dep->dwc;
511
512 dma_free_coherent(dwc->sysdev, sizeof(struct dwc3_trb) * DWC3_TRB_NUM,
513 dep->trb_pool, dep->trb_pool_dma);
514
515 dep->trb_pool = NULL;
516 dep->trb_pool_dma = 0;
517}
518
519static int dwc3_gadget_set_xfer_resource(struct dwc3_ep *dep)
520{
521 struct dwc3_gadget_ep_cmd_params params;
522 int ret;
523
524 if (dep->flags & DWC3_EP_RESOURCE_ALLOCATED)
525 return 0;
526
527 memset(¶ms, 0x00, sizeof(params));
528
529 params.param0 = DWC3_DEPXFERCFG_NUM_XFER_RES(1);
530
531 ret = dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_SETTRANSFRESOURCE,
532 ¶ms);
533 if (ret)
534 return ret;
535
536 dep->flags |= DWC3_EP_RESOURCE_ALLOCATED;
537 return 0;
538}
539
540/**
541 * dwc3_gadget_start_config - reset endpoint resources
542 * @dwc: pointer to the DWC3 context
543 * @resource_index: DEPSTARTCFG.XferRscIdx value (must be 0 or 2)
544 *
545 * Set resource_index=0 to reset all endpoints' resources allocation. Do this as
546 * part of the power-on/soft-reset initialization.
547 *
548 * Set resource_index=2 to reset only non-control endpoints' resources. Do this
549 * on receiving the SET_CONFIGURATION request or hibernation resume.
550 */
551int dwc3_gadget_start_config(struct dwc3 *dwc, unsigned int resource_index)
552{
553 struct dwc3_gadget_ep_cmd_params params;
554 u32 cmd;
555 int i;
556 int ret;
557
558 if (resource_index != 0 && resource_index != 2)
559 return -EINVAL;
560
561 memset(¶ms, 0x00, sizeof(params));
562 cmd = DWC3_DEPCMD_DEPSTARTCFG;
563 cmd |= DWC3_DEPCMD_PARAM(resource_index);
564
565 ret = dwc3_send_gadget_ep_cmd(dwc->eps[0], cmd, ¶ms);
566 if (ret)
567 return ret;
568
569 /* Reset resource allocation flags */
570 for (i = resource_index; i < dwc->num_eps && dwc->eps[i]; i++)
571 dwc->eps[i]->flags &= ~DWC3_EP_RESOURCE_ALLOCATED;
572
573 return 0;
574}
575
576static int dwc3_gadget_set_ep_config(struct dwc3_ep *dep, unsigned int action)
577{
578 const struct usb_ss_ep_comp_descriptor *comp_desc;
579 const struct usb_endpoint_descriptor *desc;
580 struct dwc3_gadget_ep_cmd_params params;
581 struct dwc3 *dwc = dep->dwc;
582
583 comp_desc = dep->endpoint.comp_desc;
584 desc = dep->endpoint.desc;
585
586 memset(¶ms, 0x00, sizeof(params));
587
588 params.param0 = DWC3_DEPCFG_EP_TYPE(usb_endpoint_type(desc))
589 | DWC3_DEPCFG_MAX_PACKET_SIZE(usb_endpoint_maxp(desc));
590
591 /* Burst size is only needed in SuperSpeed mode */
592 if (dwc->gadget->speed >= USB_SPEED_SUPER) {
593 u32 burst = dep->endpoint.maxburst;
594
595 params.param0 |= DWC3_DEPCFG_BURST_SIZE(burst - 1);
596 }
597
598 params.param0 |= action;
599 if (action == DWC3_DEPCFG_ACTION_RESTORE)
600 params.param2 |= dep->saved_state;
601
602 if (usb_endpoint_xfer_control(desc))
603 params.param1 = DWC3_DEPCFG_XFER_COMPLETE_EN;
604
605 if (dep->number <= 1 || usb_endpoint_xfer_isoc(desc))
606 params.param1 |= DWC3_DEPCFG_XFER_NOT_READY_EN;
607
608 if (usb_ss_max_streams(comp_desc) && usb_endpoint_xfer_bulk(desc)) {
609 params.param1 |= DWC3_DEPCFG_STREAM_CAPABLE
610 | DWC3_DEPCFG_XFER_COMPLETE_EN
611 | DWC3_DEPCFG_STREAM_EVENT_EN;
612 dep->stream_capable = true;
613 }
614
615 if (!usb_endpoint_xfer_control(desc))
616 params.param1 |= DWC3_DEPCFG_XFER_IN_PROGRESS_EN;
617
618 /*
619 * We are doing 1:1 mapping for endpoints, meaning
620 * Physical Endpoints 2 maps to Logical Endpoint 2 and
621 * so on. We consider the direction bit as part of the physical
622 * endpoint number. So USB endpoint 0x81 is 0x03.
623 */
624 params.param1 |= DWC3_DEPCFG_EP_NUMBER(dep->number);
625
626 /*
627 * We must use the lower 16 TX FIFOs even though
628 * HW might have more
629 */
630 if (dep->direction)
631 params.param0 |= DWC3_DEPCFG_FIFO_NUMBER(dep->number >> 1);
632
633 if (desc->bInterval) {
634 u8 bInterval_m1;
635
636 /*
637 * Valid range for DEPCFG.bInterval_m1 is from 0 to 13.
638 *
639 * NOTE: The programming guide incorrectly stated bInterval_m1
640 * must be set to 0 when operating in fullspeed. Internally the
641 * controller does not have this limitation. See DWC_usb3x
642 * programming guide section 3.2.2.1.
643 */
644 bInterval_m1 = min_t(u8, desc->bInterval - 1, 13);
645
646 if (usb_endpoint_type(desc) == USB_ENDPOINT_XFER_INT &&
647 dwc->gadget->speed == USB_SPEED_FULL)
648 dep->interval = desc->bInterval;
649 else
650 dep->interval = 1 << (desc->bInterval - 1);
651
652 params.param1 |= DWC3_DEPCFG_BINTERVAL_M1(bInterval_m1);
653 }
654
655 return dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_SETEPCONFIG, ¶ms);
656}
657
658/**
659 * dwc3_gadget_calc_tx_fifo_size - calculates the txfifo size value
660 * @dwc: pointer to the DWC3 context
661 * @mult: multiplier to be used when calculating the fifo_size
662 *
663 * Calculates the size value based on the equation below:
664 *
665 * DWC3 revision 280A and prior:
666 * fifo_size = mult * (max_packet / mdwidth) + 1;
667 *
668 * DWC3 revision 290A and onwards:
669 * fifo_size = mult * ((max_packet + mdwidth)/mdwidth + 1) + 1
670 *
671 * The max packet size is set to 1024, as the txfifo requirements mainly apply
672 * to super speed USB use cases. However, it is safe to overestimate the fifo
673 * allocations for other scenarios, i.e. high speed USB.
674 */
675static int dwc3_gadget_calc_tx_fifo_size(struct dwc3 *dwc, int mult)
676{
677 int max_packet = 1024;
678 int fifo_size;
679 int mdwidth;
680
681 mdwidth = dwc3_mdwidth(dwc);
682
683 /* MDWIDTH is represented in bits, we need it in bytes */
684 mdwidth >>= 3;
685
686 if (DWC3_VER_IS_PRIOR(DWC3, 290A))
687 fifo_size = mult * (max_packet / mdwidth) + 1;
688 else
689 fifo_size = mult * ((max_packet + mdwidth) / mdwidth) + 1;
690 return fifo_size;
691}
692
693/**
694 * dwc3_gadget_clear_tx_fifos - Clears txfifo allocation
695 * @dwc: pointer to the DWC3 context
696 *
697 * Iterates through all the endpoint registers and clears the previous txfifo
698 * allocations.
699 */
700void dwc3_gadget_clear_tx_fifos(struct dwc3 *dwc)
701{
702 struct dwc3_ep *dep;
703 int fifo_depth;
704 int size;
705 int num;
706
707 if (!dwc->do_fifo_resize)
708 return;
709
710 /* Read ep0IN related TXFIFO size */
711 dep = dwc->eps[1];
712 size = dwc3_readl(dwc->regs, DWC3_GTXFIFOSIZ(0));
713 if (DWC3_IP_IS(DWC3))
714 fifo_depth = DWC3_GTXFIFOSIZ_TXFDEP(size);
715 else
716 fifo_depth = DWC31_GTXFIFOSIZ_TXFDEP(size);
717
718 dwc->last_fifo_depth = fifo_depth;
719 /* Clear existing TXFIFO for all IN eps except ep0 */
720 for (num = 3; num < min_t(int, dwc->num_eps, DWC3_ENDPOINTS_NUM);
721 num += 2) {
722 dep = dwc->eps[num];
723 /* Don't change TXFRAMNUM on usb31 version */
724 size = DWC3_IP_IS(DWC3) ? 0 :
725 dwc3_readl(dwc->regs, DWC3_GTXFIFOSIZ(num >> 1)) &
726 DWC31_GTXFIFOSIZ_TXFRAMNUM;
727
728 dwc3_writel(dwc->regs, DWC3_GTXFIFOSIZ(num >> 1), size);
729 dep->flags &= ~DWC3_EP_TXFIFO_RESIZED;
730 }
731 dwc->num_ep_resized = 0;
732}
733
734/*
735 * dwc3_gadget_resize_tx_fifos - reallocate fifo spaces for current use-case
736 * @dwc: pointer to our context structure
737 *
738 * This function will a best effort FIFO allocation in order
739 * to improve FIFO usage and throughput, while still allowing
740 * us to enable as many endpoints as possible.
741 *
742 * Keep in mind that this operation will be highly dependent
743 * on the configured size for RAM1 - which contains TxFifo -,
744 * the amount of endpoints enabled on coreConsultant tool, and
745 * the width of the Master Bus.
746 *
747 * In general, FIFO depths are represented with the following equation:
748 *
749 * fifo_size = mult * ((max_packet + mdwidth)/mdwidth + 1) + 1
750 *
751 * In conjunction with dwc3_gadget_check_config(), this resizing logic will
752 * ensure that all endpoints will have enough internal memory for one max
753 * packet per endpoint.
754 */
755static int dwc3_gadget_resize_tx_fifos(struct dwc3_ep *dep)
756{
757 struct dwc3 *dwc = dep->dwc;
758 int fifo_0_start;
759 int ram1_depth;
760 int fifo_size;
761 int min_depth;
762 int num_in_ep;
763 int remaining;
764 int num_fifos = 1;
765 int fifo;
766 int tmp;
767
768 if (!dwc->do_fifo_resize)
769 return 0;
770
771 /* resize IN endpoints except ep0 */
772 if (!usb_endpoint_dir_in(dep->endpoint.desc) || dep->number <= 1)
773 return 0;
774
775 /* bail if already resized */
776 if (dep->flags & DWC3_EP_TXFIFO_RESIZED)
777 return 0;
778
779 ram1_depth = DWC3_RAM1_DEPTH(dwc->hwparams.hwparams7);
780
781 if ((dep->endpoint.maxburst > 1 &&
782 usb_endpoint_xfer_bulk(dep->endpoint.desc)) ||
783 usb_endpoint_xfer_isoc(dep->endpoint.desc))
784 num_fifos = 3;
785
786 if (dep->endpoint.maxburst > 6 &&
787 (usb_endpoint_xfer_bulk(dep->endpoint.desc) ||
788 usb_endpoint_xfer_isoc(dep->endpoint.desc)) && DWC3_IP_IS(DWC31))
789 num_fifos = dwc->tx_fifo_resize_max_num;
790
791 /* FIFO size for a single buffer */
792 fifo = dwc3_gadget_calc_tx_fifo_size(dwc, 1);
793
794 /* Calculate the number of remaining EPs w/o any FIFO */
795 num_in_ep = dwc->max_cfg_eps;
796 num_in_ep -= dwc->num_ep_resized;
797
798 /* Reserve at least one FIFO for the number of IN EPs */
799 min_depth = num_in_ep * (fifo + 1);
800 remaining = ram1_depth - min_depth - dwc->last_fifo_depth;
801 remaining = max_t(int, 0, remaining);
802 /*
803 * We've already reserved 1 FIFO per EP, so check what we can fit in
804 * addition to it. If there is not enough remaining space, allocate
805 * all the remaining space to the EP.
806 */
807 fifo_size = (num_fifos - 1) * fifo;
808 if (remaining < fifo_size)
809 fifo_size = remaining;
810
811 fifo_size += fifo;
812 /* Last increment according to the TX FIFO size equation */
813 fifo_size++;
814
815 /* Check if TXFIFOs start at non-zero addr */
816 tmp = dwc3_readl(dwc->regs, DWC3_GTXFIFOSIZ(0));
817 fifo_0_start = DWC3_GTXFIFOSIZ_TXFSTADDR(tmp);
818
819 fifo_size |= (fifo_0_start + (dwc->last_fifo_depth << 16));
820 if (DWC3_IP_IS(DWC3))
821 dwc->last_fifo_depth += DWC3_GTXFIFOSIZ_TXFDEP(fifo_size);
822 else
823 dwc->last_fifo_depth += DWC31_GTXFIFOSIZ_TXFDEP(fifo_size);
824
825 /* Check fifo size allocation doesn't exceed available RAM size. */
826 if (dwc->last_fifo_depth >= ram1_depth) {
827 dev_err(dwc->dev, "Fifosize(%d) > RAM size(%d) %s depth:%d\n",
828 dwc->last_fifo_depth, ram1_depth,
829 dep->endpoint.name, fifo_size);
830 if (DWC3_IP_IS(DWC3))
831 fifo_size = DWC3_GTXFIFOSIZ_TXFDEP(fifo_size);
832 else
833 fifo_size = DWC31_GTXFIFOSIZ_TXFDEP(fifo_size);
834
835 dwc->last_fifo_depth -= fifo_size;
836 return -ENOMEM;
837 }
838
839 dwc3_writel(dwc->regs, DWC3_GTXFIFOSIZ(dep->number >> 1), fifo_size);
840 dep->flags |= DWC3_EP_TXFIFO_RESIZED;
841 dwc->num_ep_resized++;
842
843 return 0;
844}
845
846/**
847 * __dwc3_gadget_ep_enable - initializes a hw endpoint
848 * @dep: endpoint to be initialized
849 * @action: one of INIT, MODIFY or RESTORE
850 *
851 * Caller should take care of locking. Execute all necessary commands to
852 * initialize a HW endpoint so it can be used by a gadget driver.
853 */
854static int __dwc3_gadget_ep_enable(struct dwc3_ep *dep, unsigned int action)
855{
856 const struct usb_endpoint_descriptor *desc = dep->endpoint.desc;
857 struct dwc3 *dwc = dep->dwc;
858
859 u32 reg;
860 int ret;
861
862 if (!(dep->flags & DWC3_EP_ENABLED)) {
863 ret = dwc3_gadget_resize_tx_fifos(dep);
864 if (ret)
865 return ret;
866 }
867
868 ret = dwc3_gadget_set_ep_config(dep, action);
869 if (ret)
870 return ret;
871
872 if (!(dep->flags & DWC3_EP_RESOURCE_ALLOCATED)) {
873 ret = dwc3_gadget_set_xfer_resource(dep);
874 if (ret)
875 return ret;
876 }
877
878 if (!(dep->flags & DWC3_EP_ENABLED)) {
879 struct dwc3_trb *trb_st_hw;
880 struct dwc3_trb *trb_link;
881
882 dep->type = usb_endpoint_type(desc);
883 dep->flags |= DWC3_EP_ENABLED;
884
885 reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
886 reg |= DWC3_DALEPENA_EP(dep->number);
887 dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
888
889 dep->trb_dequeue = 0;
890 dep->trb_enqueue = 0;
891
892 if (usb_endpoint_xfer_control(desc))
893 goto out;
894
895 /* Initialize the TRB ring */
896 memset(dep->trb_pool, 0,
897 sizeof(struct dwc3_trb) * DWC3_TRB_NUM);
898
899 /* Link TRB. The HWO bit is never reset */
900 trb_st_hw = &dep->trb_pool[0];
901
902 trb_link = &dep->trb_pool[DWC3_TRB_NUM - 1];
903 trb_link->bpl = lower_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw));
904 trb_link->bph = upper_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw));
905 trb_link->ctrl |= DWC3_TRBCTL_LINK_TRB;
906 trb_link->ctrl |= DWC3_TRB_CTRL_HWO;
907 }
908
909 /*
910 * Issue StartTransfer here with no-op TRB so we can always rely on No
911 * Response Update Transfer command.
912 */
913 if (usb_endpoint_xfer_bulk(desc) ||
914 usb_endpoint_xfer_int(desc)) {
915 struct dwc3_gadget_ep_cmd_params params;
916 struct dwc3_trb *trb;
917 dma_addr_t trb_dma;
918 u32 cmd;
919
920 memset(¶ms, 0, sizeof(params));
921 trb = &dep->trb_pool[0];
922 trb_dma = dwc3_trb_dma_offset(dep, trb);
923
924 params.param0 = upper_32_bits(trb_dma);
925 params.param1 = lower_32_bits(trb_dma);
926
927 cmd = DWC3_DEPCMD_STARTTRANSFER;
928
929 ret = dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms);
930 if (ret < 0)
931 return ret;
932
933 if (dep->stream_capable) {
934 /*
935 * For streams, at start, there maybe a race where the
936 * host primes the endpoint before the function driver
937 * queues a request to initiate a stream. In that case,
938 * the controller will not see the prime to generate the
939 * ERDY and start stream. To workaround this, issue a
940 * no-op TRB as normal, but end it immediately. As a
941 * result, when the function driver queues the request,
942 * the next START_TRANSFER command will cause the
943 * controller to generate an ERDY to initiate the
944 * stream.
945 */
946 dwc3_stop_active_transfer(dep, true, true);
947
948 /*
949 * All stream eps will reinitiate stream on NoStream
950 * rejection until we can determine that the host can
951 * prime after the first transfer.
952 *
953 * However, if the controller is capable of
954 * TXF_FLUSH_BYPASS, then IN direction endpoints will
955 * automatically restart the stream without the driver
956 * initiation.
957 */
958 if (!dep->direction ||
959 !(dwc->hwparams.hwparams9 &
960 DWC3_GHWPARAMS9_DEV_TXF_FLUSH_BYPASS))
961 dep->flags |= DWC3_EP_FORCE_RESTART_STREAM;
962 }
963 }
964
965out:
966 trace_dwc3_gadget_ep_enable(dep);
967
968 return 0;
969}
970
971void dwc3_remove_requests(struct dwc3 *dwc, struct dwc3_ep *dep, int status)
972{
973 struct dwc3_request *req;
974
975 dwc3_stop_active_transfer(dep, true, false);
976
977 /* If endxfer is delayed, avoid unmapping requests */
978 if (dep->flags & DWC3_EP_DELAY_STOP)
979 return;
980
981 /* - giveback all requests to gadget driver */
982 while (!list_empty(&dep->started_list)) {
983 req = next_request(&dep->started_list);
984
985 dwc3_gadget_giveback(dep, req, status);
986 }
987
988 while (!list_empty(&dep->pending_list)) {
989 req = next_request(&dep->pending_list);
990
991 dwc3_gadget_giveback(dep, req, status);
992 }
993
994 while (!list_empty(&dep->cancelled_list)) {
995 req = next_request(&dep->cancelled_list);
996
997 dwc3_gadget_giveback(dep, req, status);
998 }
999}
1000
1001/**
1002 * __dwc3_gadget_ep_disable - disables a hw endpoint
1003 * @dep: the endpoint to disable
1004 *
1005 * This function undoes what __dwc3_gadget_ep_enable did and also removes
1006 * requests which are currently being processed by the hardware and those which
1007 * are not yet scheduled.
1008 *
1009 * Caller should take care of locking.
1010 */
1011static int __dwc3_gadget_ep_disable(struct dwc3_ep *dep)
1012{
1013 struct dwc3 *dwc = dep->dwc;
1014 u32 reg;
1015 u32 mask;
1016
1017 trace_dwc3_gadget_ep_disable(dep);
1018
1019 /* make sure HW endpoint isn't stalled */
1020 if (dep->flags & DWC3_EP_STALL)
1021 __dwc3_gadget_ep_set_halt(dep, 0, false);
1022
1023 reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
1024 reg &= ~DWC3_DALEPENA_EP(dep->number);
1025 dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
1026
1027 dwc3_remove_requests(dwc, dep, -ESHUTDOWN);
1028
1029 dep->stream_capable = false;
1030 dep->type = 0;
1031 mask = DWC3_EP_TXFIFO_RESIZED | DWC3_EP_RESOURCE_ALLOCATED;
1032 /*
1033 * dwc3_remove_requests() can exit early if DWC3 EP delayed stop is
1034 * set. Do not clear DEP flags, so that the end transfer command will
1035 * be reattempted during the next SETUP stage.
1036 */
1037 if (dep->flags & DWC3_EP_DELAY_STOP)
1038 mask |= (DWC3_EP_DELAY_STOP | DWC3_EP_TRANSFER_STARTED);
1039 dep->flags &= mask;
1040
1041 /* Clear out the ep descriptors for non-ep0 */
1042 if (dep->number > 1) {
1043 dep->endpoint.comp_desc = NULL;
1044 dep->endpoint.desc = NULL;
1045 }
1046
1047 return 0;
1048}
1049
1050/* -------------------------------------------------------------------------- */
1051
1052static int dwc3_gadget_ep0_enable(struct usb_ep *ep,
1053 const struct usb_endpoint_descriptor *desc)
1054{
1055 return -EINVAL;
1056}
1057
1058static int dwc3_gadget_ep0_disable(struct usb_ep *ep)
1059{
1060 return -EINVAL;
1061}
1062
1063/* -------------------------------------------------------------------------- */
1064
1065static int dwc3_gadget_ep_enable(struct usb_ep *ep,
1066 const struct usb_endpoint_descriptor *desc)
1067{
1068 struct dwc3_ep *dep;
1069 struct dwc3 *dwc;
1070 unsigned long flags;
1071 int ret;
1072
1073 if (!ep || !desc || desc->bDescriptorType != USB_DT_ENDPOINT) {
1074 pr_debug("dwc3: invalid parameters\n");
1075 return -EINVAL;
1076 }
1077
1078 if (!desc->wMaxPacketSize) {
1079 pr_debug("dwc3: missing wMaxPacketSize\n");
1080 return -EINVAL;
1081 }
1082
1083 dep = to_dwc3_ep(ep);
1084 dwc = dep->dwc;
1085
1086 if (dev_WARN_ONCE(dwc->dev, dep->flags & DWC3_EP_ENABLED,
1087 "%s is already enabled\n",
1088 dep->name))
1089 return 0;
1090
1091 spin_lock_irqsave(&dwc->lock, flags);
1092 ret = __dwc3_gadget_ep_enable(dep, DWC3_DEPCFG_ACTION_INIT);
1093 spin_unlock_irqrestore(&dwc->lock, flags);
1094
1095 return ret;
1096}
1097
1098static int dwc3_gadget_ep_disable(struct usb_ep *ep)
1099{
1100 struct dwc3_ep *dep;
1101 struct dwc3 *dwc;
1102 unsigned long flags;
1103 int ret;
1104
1105 if (!ep) {
1106 pr_debug("dwc3: invalid parameters\n");
1107 return -EINVAL;
1108 }
1109
1110 dep = to_dwc3_ep(ep);
1111 dwc = dep->dwc;
1112
1113 if (dev_WARN_ONCE(dwc->dev, !(dep->flags & DWC3_EP_ENABLED),
1114 "%s is already disabled\n",
1115 dep->name))
1116 return 0;
1117
1118 spin_lock_irqsave(&dwc->lock, flags);
1119 ret = __dwc3_gadget_ep_disable(dep);
1120 spin_unlock_irqrestore(&dwc->lock, flags);
1121
1122 return ret;
1123}
1124
1125static struct usb_request *dwc3_gadget_ep_alloc_request(struct usb_ep *ep,
1126 gfp_t gfp_flags)
1127{
1128 struct dwc3_request *req;
1129 struct dwc3_ep *dep = to_dwc3_ep(ep);
1130
1131 req = kzalloc(sizeof(*req), gfp_flags);
1132 if (!req)
1133 return NULL;
1134
1135 req->direction = dep->direction;
1136 req->epnum = dep->number;
1137 req->dep = dep;
1138 req->status = DWC3_REQUEST_STATUS_UNKNOWN;
1139
1140 trace_dwc3_alloc_request(req);
1141
1142 return &req->request;
1143}
1144
1145static void dwc3_gadget_ep_free_request(struct usb_ep *ep,
1146 struct usb_request *request)
1147{
1148 struct dwc3_request *req = to_dwc3_request(request);
1149
1150 trace_dwc3_free_request(req);
1151 kfree(req);
1152}
1153
1154/**
1155 * dwc3_ep_prev_trb - returns the previous TRB in the ring
1156 * @dep: The endpoint with the TRB ring
1157 * @index: The index of the current TRB in the ring
1158 *
1159 * Returns the TRB prior to the one pointed to by the index. If the
1160 * index is 0, we will wrap backwards, skip the link TRB, and return
1161 * the one just before that.
1162 */
1163static struct dwc3_trb *dwc3_ep_prev_trb(struct dwc3_ep *dep, u8 index)
1164{
1165 u8 tmp = index;
1166
1167 if (!tmp)
1168 tmp = DWC3_TRB_NUM - 1;
1169
1170 return &dep->trb_pool[tmp - 1];
1171}
1172
1173static u32 dwc3_calc_trbs_left(struct dwc3_ep *dep)
1174{
1175 u8 trbs_left;
1176
1177 /*
1178 * If the enqueue & dequeue are equal then the TRB ring is either full
1179 * or empty. It's considered full when there are DWC3_TRB_NUM-1 of TRBs
1180 * pending to be processed by the driver.
1181 */
1182 if (dep->trb_enqueue == dep->trb_dequeue) {
1183 /*
1184 * If there is any request remained in the started_list at
1185 * this point, that means there is no TRB available.
1186 */
1187 if (!list_empty(&dep->started_list))
1188 return 0;
1189
1190 return DWC3_TRB_NUM - 1;
1191 }
1192
1193 trbs_left = dep->trb_dequeue - dep->trb_enqueue;
1194 trbs_left &= (DWC3_TRB_NUM - 1);
1195
1196 if (dep->trb_dequeue < dep->trb_enqueue)
1197 trbs_left--;
1198
1199 return trbs_left;
1200}
1201
1202/**
1203 * dwc3_prepare_one_trb - setup one TRB from one request
1204 * @dep: endpoint for which this request is prepared
1205 * @req: dwc3_request pointer
1206 * @trb_length: buffer size of the TRB
1207 * @chain: should this TRB be chained to the next?
1208 * @node: only for isochronous endpoints. First TRB needs different type.
1209 * @use_bounce_buffer: set to use bounce buffer
1210 * @must_interrupt: set to interrupt on TRB completion
1211 */
1212static void dwc3_prepare_one_trb(struct dwc3_ep *dep,
1213 struct dwc3_request *req, unsigned int trb_length,
1214 unsigned int chain, unsigned int node, bool use_bounce_buffer,
1215 bool must_interrupt)
1216{
1217 struct dwc3_trb *trb;
1218 dma_addr_t dma;
1219 unsigned int stream_id = req->request.stream_id;
1220 unsigned int short_not_ok = req->request.short_not_ok;
1221 unsigned int no_interrupt = req->request.no_interrupt;
1222 unsigned int is_last = req->request.is_last;
1223 struct dwc3 *dwc = dep->dwc;
1224 struct usb_gadget *gadget = dwc->gadget;
1225 enum usb_device_speed speed = gadget->speed;
1226
1227 if (use_bounce_buffer)
1228 dma = dep->dwc->bounce_addr;
1229 else if (req->request.num_sgs > 0)
1230 dma = sg_dma_address(req->start_sg);
1231 else
1232 dma = req->request.dma;
1233
1234 trb = &dep->trb_pool[dep->trb_enqueue];
1235
1236 if (!req->trb) {
1237 dwc3_gadget_move_started_request(req);
1238 req->trb = trb;
1239 req->trb_dma = dwc3_trb_dma_offset(dep, trb);
1240 }
1241
1242 req->num_trbs++;
1243
1244 trb->size = DWC3_TRB_SIZE_LENGTH(trb_length);
1245 trb->bpl = lower_32_bits(dma);
1246 trb->bph = upper_32_bits(dma);
1247
1248 switch (usb_endpoint_type(dep->endpoint.desc)) {
1249 case USB_ENDPOINT_XFER_CONTROL:
1250 trb->ctrl = DWC3_TRBCTL_CONTROL_SETUP;
1251 break;
1252
1253 case USB_ENDPOINT_XFER_ISOC:
1254 if (!node) {
1255 trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS_FIRST;
1256
1257 /*
1258 * USB Specification 2.0 Section 5.9.2 states that: "If
1259 * there is only a single transaction in the microframe,
1260 * only a DATA0 data packet PID is used. If there are
1261 * two transactions per microframe, DATA1 is used for
1262 * the first transaction data packet and DATA0 is used
1263 * for the second transaction data packet. If there are
1264 * three transactions per microframe, DATA2 is used for
1265 * the first transaction data packet, DATA1 is used for
1266 * the second, and DATA0 is used for the third."
1267 *
1268 * IOW, we should satisfy the following cases:
1269 *
1270 * 1) length <= maxpacket
1271 * - DATA0
1272 *
1273 * 2) maxpacket < length <= (2 * maxpacket)
1274 * - DATA1, DATA0
1275 *
1276 * 3) (2 * maxpacket) < length <= (3 * maxpacket)
1277 * - DATA2, DATA1, DATA0
1278 */
1279 if (speed == USB_SPEED_HIGH) {
1280 struct usb_ep *ep = &dep->endpoint;
1281 unsigned int mult = 2;
1282 unsigned int maxp = usb_endpoint_maxp(ep->desc);
1283
1284 if (req->request.length <= (2 * maxp))
1285 mult--;
1286
1287 if (req->request.length <= maxp)
1288 mult--;
1289
1290 trb->size |= DWC3_TRB_SIZE_PCM1(mult);
1291 }
1292 } else {
1293 trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS;
1294 }
1295
1296 if (!no_interrupt && !chain)
1297 trb->ctrl |= DWC3_TRB_CTRL_ISP_IMI;
1298 break;
1299
1300 case USB_ENDPOINT_XFER_BULK:
1301 case USB_ENDPOINT_XFER_INT:
1302 trb->ctrl = DWC3_TRBCTL_NORMAL;
1303 break;
1304 default:
1305 /*
1306 * This is only possible with faulty memory because we
1307 * checked it already :)
1308 */
1309 dev_WARN(dwc->dev, "Unknown endpoint type %d\n",
1310 usb_endpoint_type(dep->endpoint.desc));
1311 }
1312
1313 /*
1314 * Enable Continue on Short Packet
1315 * when endpoint is not a stream capable
1316 */
1317 if (usb_endpoint_dir_out(dep->endpoint.desc)) {
1318 if (!dep->stream_capable)
1319 trb->ctrl |= DWC3_TRB_CTRL_CSP;
1320
1321 if (short_not_ok)
1322 trb->ctrl |= DWC3_TRB_CTRL_ISP_IMI;
1323 }
1324
1325 /* All TRBs setup for MST must set CSP=1 when LST=0 */
1326 if (dep->stream_capable && DWC3_MST_CAPABLE(&dwc->hwparams))
1327 trb->ctrl |= DWC3_TRB_CTRL_CSP;
1328
1329 if ((!no_interrupt && !chain) || must_interrupt)
1330 trb->ctrl |= DWC3_TRB_CTRL_IOC;
1331
1332 if (chain)
1333 trb->ctrl |= DWC3_TRB_CTRL_CHN;
1334 else if (dep->stream_capable && is_last &&
1335 !DWC3_MST_CAPABLE(&dwc->hwparams))
1336 trb->ctrl |= DWC3_TRB_CTRL_LST;
1337
1338 if (usb_endpoint_xfer_bulk(dep->endpoint.desc) && dep->stream_capable)
1339 trb->ctrl |= DWC3_TRB_CTRL_SID_SOFN(stream_id);
1340
1341 /*
1342 * As per data book 4.2.3.2TRB Control Bit Rules section
1343 *
1344 * The controller autonomously checks the HWO field of a TRB to determine if the
1345 * entire TRB is valid. Therefore, software must ensure that the rest of the TRB
1346 * is valid before setting the HWO field to '1'. In most systems, this means that
1347 * software must update the fourth DWORD of a TRB last.
1348 *
1349 * However there is a possibility of CPU re-ordering here which can cause
1350 * controller to observe the HWO bit set prematurely.
1351 * Add a write memory barrier to prevent CPU re-ordering.
1352 */
1353 wmb();
1354 trb->ctrl |= DWC3_TRB_CTRL_HWO;
1355
1356 dwc3_ep_inc_enq(dep);
1357
1358 trace_dwc3_prepare_trb(dep, trb);
1359}
1360
1361static bool dwc3_needs_extra_trb(struct dwc3_ep *dep, struct dwc3_request *req)
1362{
1363 unsigned int maxp = usb_endpoint_maxp(dep->endpoint.desc);
1364 unsigned int rem = req->request.length % maxp;
1365
1366 if ((req->request.length && req->request.zero && !rem &&
1367 !usb_endpoint_xfer_isoc(dep->endpoint.desc)) ||
1368 (!req->direction && rem))
1369 return true;
1370
1371 return false;
1372}
1373
1374/**
1375 * dwc3_prepare_last_sg - prepare TRBs for the last SG entry
1376 * @dep: The endpoint that the request belongs to
1377 * @req: The request to prepare
1378 * @entry_length: The last SG entry size
1379 * @node: Indicates whether this is not the first entry (for isoc only)
1380 *
1381 * Return the number of TRBs prepared.
1382 */
1383static int dwc3_prepare_last_sg(struct dwc3_ep *dep,
1384 struct dwc3_request *req, unsigned int entry_length,
1385 unsigned int node)
1386{
1387 unsigned int maxp = usb_endpoint_maxp(dep->endpoint.desc);
1388 unsigned int rem = req->request.length % maxp;
1389 unsigned int num_trbs = 1;
1390
1391 if (dwc3_needs_extra_trb(dep, req))
1392 num_trbs++;
1393
1394 if (dwc3_calc_trbs_left(dep) < num_trbs)
1395 return 0;
1396
1397 req->needs_extra_trb = num_trbs > 1;
1398
1399 /* Prepare a normal TRB */
1400 if (req->direction || req->request.length)
1401 dwc3_prepare_one_trb(dep, req, entry_length,
1402 req->needs_extra_trb, node, false, false);
1403
1404 /* Prepare extra TRBs for ZLP and MPS OUT transfer alignment */
1405 if ((!req->direction && !req->request.length) || req->needs_extra_trb)
1406 dwc3_prepare_one_trb(dep, req,
1407 req->direction ? 0 : maxp - rem,
1408 false, 1, true, false);
1409
1410 return num_trbs;
1411}
1412
1413static int dwc3_prepare_trbs_sg(struct dwc3_ep *dep,
1414 struct dwc3_request *req)
1415{
1416 struct scatterlist *sg = req->start_sg;
1417 struct scatterlist *s;
1418 int i;
1419 unsigned int length = req->request.length;
1420 unsigned int remaining = req->request.num_mapped_sgs
1421 - req->num_queued_sgs;
1422 unsigned int num_trbs = req->num_trbs;
1423 bool needs_extra_trb = dwc3_needs_extra_trb(dep, req);
1424
1425 /*
1426 * If we resume preparing the request, then get the remaining length of
1427 * the request and resume where we left off.
1428 */
1429 for_each_sg(req->request.sg, s, req->num_queued_sgs, i)
1430 length -= sg_dma_len(s);
1431
1432 for_each_sg(sg, s, remaining, i) {
1433 unsigned int num_trbs_left = dwc3_calc_trbs_left(dep);
1434 unsigned int trb_length;
1435 bool must_interrupt = false;
1436 bool last_sg = false;
1437
1438 trb_length = min_t(unsigned int, length, sg_dma_len(s));
1439
1440 length -= trb_length;
1441
1442 /*
1443 * IOMMU driver is coalescing the list of sgs which shares a
1444 * page boundary into one and giving it to USB driver. With
1445 * this the number of sgs mapped is not equal to the number of
1446 * sgs passed. So mark the chain bit to false if it isthe last
1447 * mapped sg.
1448 */
1449 if ((i == remaining - 1) || !length)
1450 last_sg = true;
1451
1452 if (!num_trbs_left)
1453 break;
1454
1455 if (last_sg) {
1456 if (!dwc3_prepare_last_sg(dep, req, trb_length, i))
1457 break;
1458 } else {
1459 /*
1460 * Look ahead to check if we have enough TRBs for the
1461 * next SG entry. If not, set interrupt on this TRB to
1462 * resume preparing the next SG entry when more TRBs are
1463 * free.
1464 */
1465 if (num_trbs_left == 1 || (needs_extra_trb &&
1466 num_trbs_left <= 2 &&
1467 sg_dma_len(sg_next(s)) >= length)) {
1468 struct dwc3_request *r;
1469
1470 /* Check if previous requests already set IOC */
1471 list_for_each_entry(r, &dep->started_list, list) {
1472 if (r != req && !r->request.no_interrupt)
1473 break;
1474
1475 if (r == req)
1476 must_interrupt = true;
1477 }
1478 }
1479
1480 dwc3_prepare_one_trb(dep, req, trb_length, 1, i, false,
1481 must_interrupt);
1482 }
1483
1484 /*
1485 * There can be a situation where all sgs in sglist are not
1486 * queued because of insufficient trb number. To handle this
1487 * case, update start_sg to next sg to be queued, so that
1488 * we have free trbs we can continue queuing from where we
1489 * previously stopped
1490 */
1491 if (!last_sg)
1492 req->start_sg = sg_next(s);
1493
1494 req->num_queued_sgs++;
1495 req->num_pending_sgs--;
1496
1497 /*
1498 * The number of pending SG entries may not correspond to the
1499 * number of mapped SG entries. If all the data are queued, then
1500 * don't include unused SG entries.
1501 */
1502 if (length == 0) {
1503 req->num_pending_sgs = 0;
1504 break;
1505 }
1506
1507 if (must_interrupt)
1508 break;
1509 }
1510
1511 return req->num_trbs - num_trbs;
1512}
1513
1514static int dwc3_prepare_trbs_linear(struct dwc3_ep *dep,
1515 struct dwc3_request *req)
1516{
1517 return dwc3_prepare_last_sg(dep, req, req->request.length, 0);
1518}
1519
1520/*
1521 * dwc3_prepare_trbs - setup TRBs from requests
1522 * @dep: endpoint for which requests are being prepared
1523 *
1524 * The function goes through the requests list and sets up TRBs for the
1525 * transfers. The function returns once there are no more TRBs available or
1526 * it runs out of requests.
1527 *
1528 * Returns the number of TRBs prepared or negative errno.
1529 */
1530static int dwc3_prepare_trbs(struct dwc3_ep *dep)
1531{
1532 struct dwc3_request *req, *n;
1533 int ret = 0;
1534
1535 BUILD_BUG_ON_NOT_POWER_OF_2(DWC3_TRB_NUM);
1536
1537 /*
1538 * We can get in a situation where there's a request in the started list
1539 * but there weren't enough TRBs to fully kick it in the first time
1540 * around, so it has been waiting for more TRBs to be freed up.
1541 *
1542 * In that case, we should check if we have a request with pending_sgs
1543 * in the started list and prepare TRBs for that request first,
1544 * otherwise we will prepare TRBs completely out of order and that will
1545 * break things.
1546 */
1547 list_for_each_entry(req, &dep->started_list, list) {
1548 if (req->num_pending_sgs > 0) {
1549 ret = dwc3_prepare_trbs_sg(dep, req);
1550 if (!ret || req->num_pending_sgs)
1551 return ret;
1552 }
1553
1554 if (!dwc3_calc_trbs_left(dep))
1555 return ret;
1556
1557 /*
1558 * Don't prepare beyond a transfer. In DWC_usb32, its transfer
1559 * burst capability may try to read and use TRBs beyond the
1560 * active transfer instead of stopping.
1561 */
1562 if (dep->stream_capable && req->request.is_last &&
1563 !DWC3_MST_CAPABLE(&dep->dwc->hwparams))
1564 return ret;
1565 }
1566
1567 list_for_each_entry_safe(req, n, &dep->pending_list, list) {
1568 struct dwc3 *dwc = dep->dwc;
1569
1570 ret = usb_gadget_map_request_by_dev(dwc->sysdev, &req->request,
1571 dep->direction);
1572 if (ret)
1573 return ret;
1574
1575 req->sg = req->request.sg;
1576 req->start_sg = req->sg;
1577 req->num_queued_sgs = 0;
1578 req->num_pending_sgs = req->request.num_mapped_sgs;
1579
1580 if (req->num_pending_sgs > 0) {
1581 ret = dwc3_prepare_trbs_sg(dep, req);
1582 if (req->num_pending_sgs)
1583 return ret;
1584 } else {
1585 ret = dwc3_prepare_trbs_linear(dep, req);
1586 }
1587
1588 if (!ret || !dwc3_calc_trbs_left(dep))
1589 return ret;
1590
1591 /*
1592 * Don't prepare beyond a transfer. In DWC_usb32, its transfer
1593 * burst capability may try to read and use TRBs beyond the
1594 * active transfer instead of stopping.
1595 */
1596 if (dep->stream_capable && req->request.is_last &&
1597 !DWC3_MST_CAPABLE(&dwc->hwparams))
1598 return ret;
1599 }
1600
1601 return ret;
1602}
1603
1604static void dwc3_gadget_ep_cleanup_cancelled_requests(struct dwc3_ep *dep);
1605
1606static int __dwc3_gadget_kick_transfer(struct dwc3_ep *dep)
1607{
1608 struct dwc3_gadget_ep_cmd_params params;
1609 struct dwc3_request *req;
1610 int starting;
1611 int ret;
1612 u32 cmd;
1613
1614 /*
1615 * Note that it's normal to have no new TRBs prepared (i.e. ret == 0).
1616 * This happens when we need to stop and restart a transfer such as in
1617 * the case of reinitiating a stream or retrying an isoc transfer.
1618 */
1619 ret = dwc3_prepare_trbs(dep);
1620 if (ret < 0)
1621 return ret;
1622
1623 starting = !(dep->flags & DWC3_EP_TRANSFER_STARTED);
1624
1625 /*
1626 * If there's no new TRB prepared and we don't need to restart a
1627 * transfer, there's no need to update the transfer.
1628 */
1629 if (!ret && !starting)
1630 return ret;
1631
1632 req = next_request(&dep->started_list);
1633 if (!req) {
1634 dep->flags |= DWC3_EP_PENDING_REQUEST;
1635 return 0;
1636 }
1637
1638 memset(¶ms, 0, sizeof(params));
1639
1640 if (starting) {
1641 params.param0 = upper_32_bits(req->trb_dma);
1642 params.param1 = lower_32_bits(req->trb_dma);
1643 cmd = DWC3_DEPCMD_STARTTRANSFER;
1644
1645 if (dep->stream_capable)
1646 cmd |= DWC3_DEPCMD_PARAM(req->request.stream_id);
1647
1648 if (usb_endpoint_xfer_isoc(dep->endpoint.desc))
1649 cmd |= DWC3_DEPCMD_PARAM(dep->frame_number);
1650 } else {
1651 cmd = DWC3_DEPCMD_UPDATETRANSFER |
1652 DWC3_DEPCMD_PARAM(dep->resource_index);
1653 }
1654
1655 ret = dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms);
1656 if (ret < 0) {
1657 struct dwc3_request *tmp;
1658
1659 if (ret == -EAGAIN)
1660 return ret;
1661
1662 dwc3_stop_active_transfer(dep, true, true);
1663
1664 list_for_each_entry_safe(req, tmp, &dep->started_list, list)
1665 dwc3_gadget_move_cancelled_request(req, DWC3_REQUEST_STATUS_DEQUEUED);
1666
1667 /* If ep isn't started, then there's no end transfer pending */
1668 if (!(dep->flags & DWC3_EP_END_TRANSFER_PENDING))
1669 dwc3_gadget_ep_cleanup_cancelled_requests(dep);
1670
1671 return ret;
1672 }
1673
1674 if (dep->stream_capable && req->request.is_last &&
1675 !DWC3_MST_CAPABLE(&dep->dwc->hwparams))
1676 dep->flags |= DWC3_EP_WAIT_TRANSFER_COMPLETE;
1677
1678 return 0;
1679}
1680
1681static int __dwc3_gadget_get_frame(struct dwc3 *dwc)
1682{
1683 u32 reg;
1684
1685 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1686 return DWC3_DSTS_SOFFN(reg);
1687}
1688
1689/**
1690 * __dwc3_stop_active_transfer - stop the current active transfer
1691 * @dep: isoc endpoint
1692 * @force: set forcerm bit in the command
1693 * @interrupt: command complete interrupt after End Transfer command
1694 *
1695 * When setting force, the ForceRM bit will be set. In that case
1696 * the controller won't update the TRB progress on command
1697 * completion. It also won't clear the HWO bit in the TRB.
1698 * The command will also not complete immediately in that case.
1699 */
1700static int __dwc3_stop_active_transfer(struct dwc3_ep *dep, bool force, bool interrupt)
1701{
1702 struct dwc3_gadget_ep_cmd_params params;
1703 u32 cmd;
1704 int ret;
1705
1706 cmd = DWC3_DEPCMD_ENDTRANSFER;
1707 cmd |= force ? DWC3_DEPCMD_HIPRI_FORCERM : 0;
1708 cmd |= interrupt ? DWC3_DEPCMD_CMDIOC : 0;
1709 cmd |= DWC3_DEPCMD_PARAM(dep->resource_index);
1710 memset(¶ms, 0, sizeof(params));
1711 ret = dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms);
1712 /*
1713 * If the End Transfer command was timed out while the device is
1714 * not in SETUP phase, it's possible that an incoming Setup packet
1715 * may prevent the command's completion. Let's retry when the
1716 * ep0state returns to EP0_SETUP_PHASE.
1717 */
1718 if (ret == -ETIMEDOUT && dep->dwc->ep0state != EP0_SETUP_PHASE) {
1719 dep->flags |= DWC3_EP_DELAY_STOP;
1720 return 0;
1721 }
1722 WARN_ON_ONCE(ret);
1723 dep->resource_index = 0;
1724
1725 if (!interrupt) {
1726 mdelay(1);
1727 dep->flags &= ~DWC3_EP_TRANSFER_STARTED;
1728 } else if (!ret) {
1729 dep->flags |= DWC3_EP_END_TRANSFER_PENDING;
1730 }
1731
1732 dep->flags &= ~DWC3_EP_DELAY_STOP;
1733 return ret;
1734}
1735
1736/**
1737 * dwc3_gadget_start_isoc_quirk - workaround invalid frame number
1738 * @dep: isoc endpoint
1739 *
1740 * This function tests for the correct combination of BIT[15:14] from the 16-bit
1741 * microframe number reported by the XferNotReady event for the future frame
1742 * number to start the isoc transfer.
1743 *
1744 * In DWC_usb31 version 1.70a-ea06 and prior, for highspeed and fullspeed
1745 * isochronous IN, BIT[15:14] of the 16-bit microframe number reported by the
1746 * XferNotReady event are invalid. The driver uses this number to schedule the
1747 * isochronous transfer and passes it to the START TRANSFER command. Because
1748 * this number is invalid, the command may fail. If BIT[15:14] matches the
1749 * internal 16-bit microframe, the START TRANSFER command will pass and the
1750 * transfer will start at the scheduled time, if it is off by 1, the command
1751 * will still pass, but the transfer will start 2 seconds in the future. For all
1752 * other conditions, the START TRANSFER command will fail with bus-expiry.
1753 *
1754 * In order to workaround this issue, we can test for the correct combination of
1755 * BIT[15:14] by sending START TRANSFER commands with different values of
1756 * BIT[15:14]: 'b00, 'b01, 'b10, and 'b11. Each combination is 2^14 uframe apart
1757 * (or 2 seconds). 4 seconds into the future will result in a bus-expiry status.
1758 * As the result, within the 4 possible combinations for BIT[15:14], there will
1759 * be 2 successful and 2 failure START COMMAND status. One of the 2 successful
1760 * command status will result in a 2-second delay start. The smaller BIT[15:14]
1761 * value is the correct combination.
1762 *
1763 * Since there are only 4 outcomes and the results are ordered, we can simply
1764 * test 2 START TRANSFER commands with BIT[15:14] combinations 'b00 and 'b01 to
1765 * deduce the smaller successful combination.
1766 *
1767 * Let test0 = test status for combination 'b00 and test1 = test status for 'b01
1768 * of BIT[15:14]. The correct combination is as follow:
1769 *
1770 * if test0 fails and test1 passes, BIT[15:14] is 'b01
1771 * if test0 fails and test1 fails, BIT[15:14] is 'b10
1772 * if test0 passes and test1 fails, BIT[15:14] is 'b11
1773 * if test0 passes and test1 passes, BIT[15:14] is 'b00
1774 *
1775 * Synopsys STAR 9001202023: Wrong microframe number for isochronous IN
1776 * endpoints.
1777 */
1778static int dwc3_gadget_start_isoc_quirk(struct dwc3_ep *dep)
1779{
1780 int cmd_status = 0;
1781 bool test0;
1782 bool test1;
1783
1784 while (dep->combo_num < 2) {
1785 struct dwc3_gadget_ep_cmd_params params;
1786 u32 test_frame_number;
1787 u32 cmd;
1788
1789 /*
1790 * Check if we can start isoc transfer on the next interval or
1791 * 4 uframes in the future with BIT[15:14] as dep->combo_num
1792 */
1793 test_frame_number = dep->frame_number & DWC3_FRNUMBER_MASK;
1794 test_frame_number |= dep->combo_num << 14;
1795 test_frame_number += max_t(u32, 4, dep->interval);
1796
1797 params.param0 = upper_32_bits(dep->dwc->bounce_addr);
1798 params.param1 = lower_32_bits(dep->dwc->bounce_addr);
1799
1800 cmd = DWC3_DEPCMD_STARTTRANSFER;
1801 cmd |= DWC3_DEPCMD_PARAM(test_frame_number);
1802 cmd_status = dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms);
1803
1804 /* Redo if some other failure beside bus-expiry is received */
1805 if (cmd_status && cmd_status != -EAGAIN) {
1806 dep->start_cmd_status = 0;
1807 dep->combo_num = 0;
1808 return 0;
1809 }
1810
1811 /* Store the first test status */
1812 if (dep->combo_num == 0)
1813 dep->start_cmd_status = cmd_status;
1814
1815 dep->combo_num++;
1816
1817 /*
1818 * End the transfer if the START_TRANSFER command is successful
1819 * to wait for the next XferNotReady to test the command again
1820 */
1821 if (cmd_status == 0) {
1822 dwc3_stop_active_transfer(dep, true, true);
1823 return 0;
1824 }
1825 }
1826
1827 /* test0 and test1 are both completed at this point */
1828 test0 = (dep->start_cmd_status == 0);
1829 test1 = (cmd_status == 0);
1830
1831 if (!test0 && test1)
1832 dep->combo_num = 1;
1833 else if (!test0 && !test1)
1834 dep->combo_num = 2;
1835 else if (test0 && !test1)
1836 dep->combo_num = 3;
1837 else if (test0 && test1)
1838 dep->combo_num = 0;
1839
1840 dep->frame_number &= DWC3_FRNUMBER_MASK;
1841 dep->frame_number |= dep->combo_num << 14;
1842 dep->frame_number += max_t(u32, 4, dep->interval);
1843
1844 /* Reinitialize test variables */
1845 dep->start_cmd_status = 0;
1846 dep->combo_num = 0;
1847
1848 return __dwc3_gadget_kick_transfer(dep);
1849}
1850
1851static int __dwc3_gadget_start_isoc(struct dwc3_ep *dep)
1852{
1853 const struct usb_endpoint_descriptor *desc = dep->endpoint.desc;
1854 struct dwc3 *dwc = dep->dwc;
1855 int ret;
1856 int i;
1857
1858 if (list_empty(&dep->pending_list) &&
1859 list_empty(&dep->started_list)) {
1860 dep->flags |= DWC3_EP_PENDING_REQUEST;
1861 return -EAGAIN;
1862 }
1863
1864 if (!dwc->dis_start_transfer_quirk &&
1865 (DWC3_VER_IS_PRIOR(DWC31, 170A) ||
1866 DWC3_VER_TYPE_IS_WITHIN(DWC31, 170A, EA01, EA06))) {
1867 if (dwc->gadget->speed <= USB_SPEED_HIGH && dep->direction)
1868 return dwc3_gadget_start_isoc_quirk(dep);
1869 }
1870
1871 if (desc->bInterval <= 14 &&
1872 dwc->gadget->speed >= USB_SPEED_HIGH) {
1873 u32 frame = __dwc3_gadget_get_frame(dwc);
1874 bool rollover = frame <
1875 (dep->frame_number & DWC3_FRNUMBER_MASK);
1876
1877 /*
1878 * frame_number is set from XferNotReady and may be already
1879 * out of date. DSTS only provides the lower 14 bit of the
1880 * current frame number. So add the upper two bits of
1881 * frame_number and handle a possible rollover.
1882 * This will provide the correct frame_number unless more than
1883 * rollover has happened since XferNotReady.
1884 */
1885
1886 dep->frame_number = (dep->frame_number & ~DWC3_FRNUMBER_MASK) |
1887 frame;
1888 if (rollover)
1889 dep->frame_number += BIT(14);
1890 }
1891
1892 for (i = 0; i < DWC3_ISOC_MAX_RETRIES; i++) {
1893 int future_interval = i + 1;
1894
1895 /* Give the controller at least 500us to schedule transfers */
1896 if (desc->bInterval < 3)
1897 future_interval += 3 - desc->bInterval;
1898
1899 dep->frame_number = DWC3_ALIGN_FRAME(dep, future_interval);
1900
1901 ret = __dwc3_gadget_kick_transfer(dep);
1902 if (ret != -EAGAIN)
1903 break;
1904 }
1905
1906 /*
1907 * After a number of unsuccessful start attempts due to bus-expiry
1908 * status, issue END_TRANSFER command and retry on the next XferNotReady
1909 * event.
1910 */
1911 if (ret == -EAGAIN)
1912 ret = __dwc3_stop_active_transfer(dep, false, true);
1913
1914 return ret;
1915}
1916
1917static int __dwc3_gadget_ep_queue(struct dwc3_ep *dep, struct dwc3_request *req)
1918{
1919 struct dwc3 *dwc = dep->dwc;
1920
1921 if (!dep->endpoint.desc || !dwc->pullups_connected || !dwc->connected) {
1922 dev_dbg(dwc->dev, "%s: can't queue to disabled endpoint\n",
1923 dep->name);
1924 return -ESHUTDOWN;
1925 }
1926
1927 if (WARN(req->dep != dep, "request %pK belongs to '%s'\n",
1928 &req->request, req->dep->name))
1929 return -EINVAL;
1930
1931 if (WARN(req->status < DWC3_REQUEST_STATUS_COMPLETED,
1932 "%s: request %pK already in flight\n",
1933 dep->name, &req->request))
1934 return -EINVAL;
1935
1936 pm_runtime_get(dwc->dev);
1937
1938 req->request.actual = 0;
1939 req->request.status = -EINPROGRESS;
1940
1941 trace_dwc3_ep_queue(req);
1942
1943 list_add_tail(&req->list, &dep->pending_list);
1944 req->status = DWC3_REQUEST_STATUS_QUEUED;
1945
1946 if (dep->flags & DWC3_EP_WAIT_TRANSFER_COMPLETE)
1947 return 0;
1948
1949 /*
1950 * Start the transfer only after the END_TRANSFER is completed
1951 * and endpoint STALL is cleared.
1952 */
1953 if ((dep->flags & DWC3_EP_END_TRANSFER_PENDING) ||
1954 (dep->flags & DWC3_EP_WEDGE) ||
1955 (dep->flags & DWC3_EP_DELAY_STOP) ||
1956 (dep->flags & DWC3_EP_STALL)) {
1957 dep->flags |= DWC3_EP_DELAY_START;
1958 return 0;
1959 }
1960
1961 /*
1962 * NOTICE: Isochronous endpoints should NEVER be prestarted. We must
1963 * wait for a XferNotReady event so we will know what's the current
1964 * (micro-)frame number.
1965 *
1966 * Without this trick, we are very, very likely gonna get Bus Expiry
1967 * errors which will force us issue EndTransfer command.
1968 */
1969 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1970 if (!(dep->flags & DWC3_EP_TRANSFER_STARTED)) {
1971 if ((dep->flags & DWC3_EP_PENDING_REQUEST))
1972 return __dwc3_gadget_start_isoc(dep);
1973
1974 return 0;
1975 }
1976 }
1977
1978 __dwc3_gadget_kick_transfer(dep);
1979
1980 return 0;
1981}
1982
1983static int dwc3_gadget_ep_queue(struct usb_ep *ep, struct usb_request *request,
1984 gfp_t gfp_flags)
1985{
1986 struct dwc3_request *req = to_dwc3_request(request);
1987 struct dwc3_ep *dep = to_dwc3_ep(ep);
1988 struct dwc3 *dwc = dep->dwc;
1989
1990 unsigned long flags;
1991
1992 int ret;
1993
1994 spin_lock_irqsave(&dwc->lock, flags);
1995 ret = __dwc3_gadget_ep_queue(dep, req);
1996 spin_unlock_irqrestore(&dwc->lock, flags);
1997
1998 return ret;
1999}
2000
2001static void dwc3_gadget_ep_skip_trbs(struct dwc3_ep *dep, struct dwc3_request *req)
2002{
2003 int i;
2004
2005 /* If req->trb is not set, then the request has not started */
2006 if (!req->trb)
2007 return;
2008
2009 /*
2010 * If request was already started, this means we had to
2011 * stop the transfer. With that we also need to ignore
2012 * all TRBs used by the request, however TRBs can only
2013 * be modified after completion of END_TRANSFER
2014 * command. So what we do here is that we wait for
2015 * END_TRANSFER completion and only after that, we jump
2016 * over TRBs by clearing HWO and incrementing dequeue
2017 * pointer.
2018 */
2019 for (i = 0; i < req->num_trbs; i++) {
2020 struct dwc3_trb *trb;
2021
2022 trb = &dep->trb_pool[dep->trb_dequeue];
2023 trb->ctrl &= ~DWC3_TRB_CTRL_HWO;
2024 dwc3_ep_inc_deq(dep);
2025 }
2026
2027 req->num_trbs = 0;
2028}
2029
2030static void dwc3_gadget_ep_cleanup_cancelled_requests(struct dwc3_ep *dep)
2031{
2032 struct dwc3_request *req;
2033 struct dwc3 *dwc = dep->dwc;
2034
2035 while (!list_empty(&dep->cancelled_list)) {
2036 req = next_request(&dep->cancelled_list);
2037 dwc3_gadget_ep_skip_trbs(dep, req);
2038 switch (req->status) {
2039 case DWC3_REQUEST_STATUS_DISCONNECTED:
2040 dwc3_gadget_giveback(dep, req, -ESHUTDOWN);
2041 break;
2042 case DWC3_REQUEST_STATUS_DEQUEUED:
2043 dwc3_gadget_giveback(dep, req, -ECONNRESET);
2044 break;
2045 case DWC3_REQUEST_STATUS_STALLED:
2046 dwc3_gadget_giveback(dep, req, -EPIPE);
2047 break;
2048 default:
2049 dev_err(dwc->dev, "request cancelled with wrong reason:%d\n", req->status);
2050 dwc3_gadget_giveback(dep, req, -ECONNRESET);
2051 break;
2052 }
2053 /*
2054 * The endpoint is disabled, let the dwc3_remove_requests()
2055 * handle the cleanup.
2056 */
2057 if (!dep->endpoint.desc)
2058 break;
2059 }
2060}
2061
2062static int dwc3_gadget_ep_dequeue(struct usb_ep *ep,
2063 struct usb_request *request)
2064{
2065 struct dwc3_request *req = to_dwc3_request(request);
2066 struct dwc3_request *r = NULL;
2067
2068 struct dwc3_ep *dep = to_dwc3_ep(ep);
2069 struct dwc3 *dwc = dep->dwc;
2070
2071 unsigned long flags;
2072 int ret = 0;
2073
2074 trace_dwc3_ep_dequeue(req);
2075
2076 spin_lock_irqsave(&dwc->lock, flags);
2077
2078 list_for_each_entry(r, &dep->cancelled_list, list) {
2079 if (r == req)
2080 goto out;
2081 }
2082
2083 list_for_each_entry(r, &dep->pending_list, list) {
2084 if (r == req) {
2085 /*
2086 * Explicitly check for EP0/1 as dequeue for those
2087 * EPs need to be handled differently. Control EP
2088 * only deals with one USB req, and giveback will
2089 * occur during dwc3_ep0_stall_and_restart(). EP0
2090 * requests are never added to started_list.
2091 */
2092 if (dep->number > 1)
2093 dwc3_gadget_giveback(dep, req, -ECONNRESET);
2094 else
2095 dwc3_ep0_reset_state(dwc);
2096 goto out;
2097 }
2098 }
2099
2100 list_for_each_entry(r, &dep->started_list, list) {
2101 if (r == req) {
2102 struct dwc3_request *t;
2103
2104 /* wait until it is processed */
2105 dwc3_stop_active_transfer(dep, true, true);
2106
2107 /*
2108 * Remove any started request if the transfer is
2109 * cancelled.
2110 */
2111 list_for_each_entry_safe(r, t, &dep->started_list, list)
2112 dwc3_gadget_move_cancelled_request(r,
2113 DWC3_REQUEST_STATUS_DEQUEUED);
2114
2115 dep->flags &= ~DWC3_EP_WAIT_TRANSFER_COMPLETE;
2116
2117 goto out;
2118 }
2119 }
2120
2121 dev_err(dwc->dev, "request %pK was not queued to %s\n",
2122 request, ep->name);
2123 ret = -EINVAL;
2124out:
2125 spin_unlock_irqrestore(&dwc->lock, flags);
2126
2127 return ret;
2128}
2129
2130int __dwc3_gadget_ep_set_halt(struct dwc3_ep *dep, int value, int protocol)
2131{
2132 struct dwc3_gadget_ep_cmd_params params;
2133 struct dwc3 *dwc = dep->dwc;
2134 struct dwc3_request *req;
2135 struct dwc3_request *tmp;
2136 int ret;
2137
2138 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
2139 dev_err(dwc->dev, "%s is of Isochronous type\n", dep->name);
2140 return -EINVAL;
2141 }
2142
2143 memset(¶ms, 0x00, sizeof(params));
2144
2145 if (value) {
2146 struct dwc3_trb *trb;
2147
2148 unsigned int transfer_in_flight;
2149 unsigned int started;
2150
2151 if (dep->number > 1)
2152 trb = dwc3_ep_prev_trb(dep, dep->trb_enqueue);
2153 else
2154 trb = &dwc->ep0_trb[dep->trb_enqueue];
2155
2156 transfer_in_flight = trb->ctrl & DWC3_TRB_CTRL_HWO;
2157 started = !list_empty(&dep->started_list);
2158
2159 if (!protocol && ((dep->direction && transfer_in_flight) ||
2160 (!dep->direction && started))) {
2161 return -EAGAIN;
2162 }
2163
2164 ret = dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_SETSTALL,
2165 ¶ms);
2166 if (ret)
2167 dev_err(dwc->dev, "failed to set STALL on %s\n",
2168 dep->name);
2169 else
2170 dep->flags |= DWC3_EP_STALL;
2171 } else {
2172 /*
2173 * Don't issue CLEAR_STALL command to control endpoints. The
2174 * controller automatically clears the STALL when it receives
2175 * the SETUP token.
2176 */
2177 if (dep->number <= 1) {
2178 dep->flags &= ~(DWC3_EP_STALL | DWC3_EP_WEDGE);
2179 return 0;
2180 }
2181
2182 dwc3_stop_active_transfer(dep, true, true);
2183
2184 list_for_each_entry_safe(req, tmp, &dep->started_list, list)
2185 dwc3_gadget_move_cancelled_request(req, DWC3_REQUEST_STATUS_STALLED);
2186
2187 if (dep->flags & DWC3_EP_END_TRANSFER_PENDING ||
2188 (dep->flags & DWC3_EP_DELAY_STOP)) {
2189 dep->flags |= DWC3_EP_PENDING_CLEAR_STALL;
2190 if (protocol)
2191 dwc->clear_stall_protocol = dep->number;
2192
2193 return 0;
2194 }
2195
2196 dwc3_gadget_ep_cleanup_cancelled_requests(dep);
2197
2198 ret = dwc3_send_clear_stall_ep_cmd(dep);
2199 if (ret) {
2200 dev_err(dwc->dev, "failed to clear STALL on %s\n",
2201 dep->name);
2202 return ret;
2203 }
2204
2205 dep->flags &= ~(DWC3_EP_STALL | DWC3_EP_WEDGE);
2206
2207 if ((dep->flags & DWC3_EP_DELAY_START) &&
2208 !usb_endpoint_xfer_isoc(dep->endpoint.desc))
2209 __dwc3_gadget_kick_transfer(dep);
2210
2211 dep->flags &= ~DWC3_EP_DELAY_START;
2212 }
2213
2214 return ret;
2215}
2216
2217static int dwc3_gadget_ep_set_halt(struct usb_ep *ep, int value)
2218{
2219 struct dwc3_ep *dep = to_dwc3_ep(ep);
2220 struct dwc3 *dwc = dep->dwc;
2221
2222 unsigned long flags;
2223
2224 int ret;
2225
2226 spin_lock_irqsave(&dwc->lock, flags);
2227 ret = __dwc3_gadget_ep_set_halt(dep, value, false);
2228 spin_unlock_irqrestore(&dwc->lock, flags);
2229
2230 return ret;
2231}
2232
2233static int dwc3_gadget_ep_set_wedge(struct usb_ep *ep)
2234{
2235 struct dwc3_ep *dep = to_dwc3_ep(ep);
2236 struct dwc3 *dwc = dep->dwc;
2237 unsigned long flags;
2238 int ret;
2239
2240 spin_lock_irqsave(&dwc->lock, flags);
2241 dep->flags |= DWC3_EP_WEDGE;
2242
2243 if (dep->number == 0 || dep->number == 1)
2244 ret = __dwc3_gadget_ep0_set_halt(ep, 1);
2245 else
2246 ret = __dwc3_gadget_ep_set_halt(dep, 1, false);
2247 spin_unlock_irqrestore(&dwc->lock, flags);
2248
2249 return ret;
2250}
2251
2252/* -------------------------------------------------------------------------- */
2253
2254static struct usb_endpoint_descriptor dwc3_gadget_ep0_desc = {
2255 .bLength = USB_DT_ENDPOINT_SIZE,
2256 .bDescriptorType = USB_DT_ENDPOINT,
2257 .bmAttributes = USB_ENDPOINT_XFER_CONTROL,
2258};
2259
2260static const struct usb_ep_ops dwc3_gadget_ep0_ops = {
2261 .enable = dwc3_gadget_ep0_enable,
2262 .disable = dwc3_gadget_ep0_disable,
2263 .alloc_request = dwc3_gadget_ep_alloc_request,
2264 .free_request = dwc3_gadget_ep_free_request,
2265 .queue = dwc3_gadget_ep0_queue,
2266 .dequeue = dwc3_gadget_ep_dequeue,
2267 .set_halt = dwc3_gadget_ep0_set_halt,
2268 .set_wedge = dwc3_gadget_ep_set_wedge,
2269};
2270
2271static const struct usb_ep_ops dwc3_gadget_ep_ops = {
2272 .enable = dwc3_gadget_ep_enable,
2273 .disable = dwc3_gadget_ep_disable,
2274 .alloc_request = dwc3_gadget_ep_alloc_request,
2275 .free_request = dwc3_gadget_ep_free_request,
2276 .queue = dwc3_gadget_ep_queue,
2277 .dequeue = dwc3_gadget_ep_dequeue,
2278 .set_halt = dwc3_gadget_ep_set_halt,
2279 .set_wedge = dwc3_gadget_ep_set_wedge,
2280};
2281
2282/* -------------------------------------------------------------------------- */
2283
2284static void dwc3_gadget_enable_linksts_evts(struct dwc3 *dwc, bool set)
2285{
2286 u32 reg;
2287
2288 if (DWC3_VER_IS_PRIOR(DWC3, 250A))
2289 return;
2290
2291 reg = dwc3_readl(dwc->regs, DWC3_DEVTEN);
2292 if (set)
2293 reg |= DWC3_DEVTEN_ULSTCNGEN;
2294 else
2295 reg &= ~DWC3_DEVTEN_ULSTCNGEN;
2296
2297 dwc3_writel(dwc->regs, DWC3_DEVTEN, reg);
2298}
2299
2300static int dwc3_gadget_get_frame(struct usb_gadget *g)
2301{
2302 struct dwc3 *dwc = gadget_to_dwc(g);
2303
2304 return __dwc3_gadget_get_frame(dwc);
2305}
2306
2307static int __dwc3_gadget_wakeup(struct dwc3 *dwc, bool async)
2308{
2309 int retries;
2310
2311 int ret;
2312 u32 reg;
2313
2314 u8 link_state;
2315
2316 /*
2317 * According to the Databook Remote wakeup request should
2318 * be issued only when the device is in early suspend state.
2319 *
2320 * We can check that via USB Link State bits in DSTS register.
2321 */
2322 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
2323
2324 link_state = DWC3_DSTS_USBLNKST(reg);
2325
2326 switch (link_state) {
2327 case DWC3_LINK_STATE_RESET:
2328 case DWC3_LINK_STATE_RX_DET: /* in HS, means Early Suspend */
2329 case DWC3_LINK_STATE_U3: /* in HS, means SUSPEND */
2330 case DWC3_LINK_STATE_U2: /* in HS, means Sleep (L1) */
2331 case DWC3_LINK_STATE_U1:
2332 case DWC3_LINK_STATE_RESUME:
2333 break;
2334 default:
2335 return -EINVAL;
2336 }
2337
2338 if (async)
2339 dwc3_gadget_enable_linksts_evts(dwc, true);
2340
2341 ret = dwc3_gadget_set_link_state(dwc, DWC3_LINK_STATE_RECOV);
2342 if (ret < 0) {
2343 dev_err(dwc->dev, "failed to put link in Recovery\n");
2344 dwc3_gadget_enable_linksts_evts(dwc, false);
2345 return ret;
2346 }
2347
2348 /* Recent versions do this automatically */
2349 if (DWC3_VER_IS_PRIOR(DWC3, 194A)) {
2350 /* write zeroes to Link Change Request */
2351 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2352 reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;
2353 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2354 }
2355
2356 /*
2357 * Since link status change events are enabled we will receive
2358 * an U0 event when wakeup is successful. So bail out.
2359 */
2360 if (async)
2361 return 0;
2362
2363 /* poll until Link State changes to ON */
2364 retries = 20000;
2365
2366 while (retries--) {
2367 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
2368
2369 /* in HS, means ON */
2370 if (DWC3_DSTS_USBLNKST(reg) == DWC3_LINK_STATE_U0)
2371 break;
2372 }
2373
2374 if (DWC3_DSTS_USBLNKST(reg) != DWC3_LINK_STATE_U0) {
2375 dev_err(dwc->dev, "failed to send remote wakeup\n");
2376 return -EINVAL;
2377 }
2378
2379 return 0;
2380}
2381
2382static int dwc3_gadget_wakeup(struct usb_gadget *g)
2383{
2384 struct dwc3 *dwc = gadget_to_dwc(g);
2385 unsigned long flags;
2386 int ret;
2387
2388 if (!dwc->wakeup_configured) {
2389 dev_err(dwc->dev, "remote wakeup not configured\n");
2390 return -EINVAL;
2391 }
2392
2393 spin_lock_irqsave(&dwc->lock, flags);
2394 if (!dwc->gadget->wakeup_armed) {
2395 dev_err(dwc->dev, "not armed for remote wakeup\n");
2396 spin_unlock_irqrestore(&dwc->lock, flags);
2397 return -EINVAL;
2398 }
2399 ret = __dwc3_gadget_wakeup(dwc, true);
2400
2401 spin_unlock_irqrestore(&dwc->lock, flags);
2402
2403 return ret;
2404}
2405
2406static void dwc3_resume_gadget(struct dwc3 *dwc);
2407
2408static int dwc3_gadget_func_wakeup(struct usb_gadget *g, int intf_id)
2409{
2410 struct dwc3 *dwc = gadget_to_dwc(g);
2411 unsigned long flags;
2412 int ret;
2413 int link_state;
2414
2415 if (!dwc->wakeup_configured) {
2416 dev_err(dwc->dev, "remote wakeup not configured\n");
2417 return -EINVAL;
2418 }
2419
2420 spin_lock_irqsave(&dwc->lock, flags);
2421 /*
2422 * If the link is in U3, signal for remote wakeup and wait for the
2423 * link to transition to U0 before sending device notification.
2424 */
2425 link_state = dwc3_gadget_get_link_state(dwc);
2426 if (link_state == DWC3_LINK_STATE_U3) {
2427 ret = __dwc3_gadget_wakeup(dwc, false);
2428 if (ret) {
2429 spin_unlock_irqrestore(&dwc->lock, flags);
2430 return -EINVAL;
2431 }
2432 dwc3_resume_gadget(dwc);
2433 dwc->suspended = false;
2434 dwc->link_state = DWC3_LINK_STATE_U0;
2435 }
2436
2437 ret = dwc3_send_gadget_generic_command(dwc, DWC3_DGCMD_DEV_NOTIFICATION,
2438 DWC3_DGCMDPAR_DN_FUNC_WAKE |
2439 DWC3_DGCMDPAR_INTF_SEL(intf_id));
2440 if (ret)
2441 dev_err(dwc->dev, "function remote wakeup failed, ret:%d\n", ret);
2442
2443 spin_unlock_irqrestore(&dwc->lock, flags);
2444
2445 return ret;
2446}
2447
2448static int dwc3_gadget_set_remote_wakeup(struct usb_gadget *g, int set)
2449{
2450 struct dwc3 *dwc = gadget_to_dwc(g);
2451 unsigned long flags;
2452
2453 spin_lock_irqsave(&dwc->lock, flags);
2454 dwc->wakeup_configured = !!set;
2455 spin_unlock_irqrestore(&dwc->lock, flags);
2456
2457 return 0;
2458}
2459
2460static int dwc3_gadget_set_selfpowered(struct usb_gadget *g,
2461 int is_selfpowered)
2462{
2463 struct dwc3 *dwc = gadget_to_dwc(g);
2464 unsigned long flags;
2465
2466 spin_lock_irqsave(&dwc->lock, flags);
2467 g->is_selfpowered = !!is_selfpowered;
2468 spin_unlock_irqrestore(&dwc->lock, flags);
2469
2470 return 0;
2471}
2472
2473static void dwc3_stop_active_transfers(struct dwc3 *dwc)
2474{
2475 u32 epnum;
2476
2477 for (epnum = 2; epnum < dwc->num_eps; epnum++) {
2478 struct dwc3_ep *dep;
2479
2480 dep = dwc->eps[epnum];
2481 if (!dep)
2482 continue;
2483
2484 dwc3_remove_requests(dwc, dep, -ESHUTDOWN);
2485 }
2486}
2487
2488static void __dwc3_gadget_set_ssp_rate(struct dwc3 *dwc)
2489{
2490 enum usb_ssp_rate ssp_rate = dwc->gadget_ssp_rate;
2491 u32 reg;
2492
2493 if (ssp_rate == USB_SSP_GEN_UNKNOWN)
2494 ssp_rate = dwc->max_ssp_rate;
2495
2496 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2497 reg &= ~DWC3_DCFG_SPEED_MASK;
2498 reg &= ~DWC3_DCFG_NUMLANES(~0);
2499
2500 if (ssp_rate == USB_SSP_GEN_1x2)
2501 reg |= DWC3_DCFG_SUPERSPEED;
2502 else if (dwc->max_ssp_rate != USB_SSP_GEN_1x2)
2503 reg |= DWC3_DCFG_SUPERSPEED_PLUS;
2504
2505 if (ssp_rate != USB_SSP_GEN_2x1 &&
2506 dwc->max_ssp_rate != USB_SSP_GEN_2x1)
2507 reg |= DWC3_DCFG_NUMLANES(1);
2508
2509 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2510}
2511
2512static void __dwc3_gadget_set_speed(struct dwc3 *dwc)
2513{
2514 enum usb_device_speed speed;
2515 u32 reg;
2516
2517 speed = dwc->gadget_max_speed;
2518 if (speed == USB_SPEED_UNKNOWN || speed > dwc->maximum_speed)
2519 speed = dwc->maximum_speed;
2520
2521 if (speed == USB_SPEED_SUPER_PLUS &&
2522 DWC3_IP_IS(DWC32)) {
2523 __dwc3_gadget_set_ssp_rate(dwc);
2524 return;
2525 }
2526
2527 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2528 reg &= ~(DWC3_DCFG_SPEED_MASK);
2529
2530 /*
2531 * WORKAROUND: DWC3 revision < 2.20a have an issue
2532 * which would cause metastability state on Run/Stop
2533 * bit if we try to force the IP to USB2-only mode.
2534 *
2535 * Because of that, we cannot configure the IP to any
2536 * speed other than the SuperSpeed
2537 *
2538 * Refers to:
2539 *
2540 * STAR#9000525659: Clock Domain Crossing on DCTL in
2541 * USB 2.0 Mode
2542 */
2543 if (DWC3_VER_IS_PRIOR(DWC3, 220A) &&
2544 !dwc->dis_metastability_quirk) {
2545 reg |= DWC3_DCFG_SUPERSPEED;
2546 } else {
2547 switch (speed) {
2548 case USB_SPEED_FULL:
2549 reg |= DWC3_DCFG_FULLSPEED;
2550 break;
2551 case USB_SPEED_HIGH:
2552 reg |= DWC3_DCFG_HIGHSPEED;
2553 break;
2554 case USB_SPEED_SUPER:
2555 reg |= DWC3_DCFG_SUPERSPEED;
2556 break;
2557 case USB_SPEED_SUPER_PLUS:
2558 if (DWC3_IP_IS(DWC3))
2559 reg |= DWC3_DCFG_SUPERSPEED;
2560 else
2561 reg |= DWC3_DCFG_SUPERSPEED_PLUS;
2562 break;
2563 default:
2564 dev_err(dwc->dev, "invalid speed (%d)\n", speed);
2565
2566 if (DWC3_IP_IS(DWC3))
2567 reg |= DWC3_DCFG_SUPERSPEED;
2568 else
2569 reg |= DWC3_DCFG_SUPERSPEED_PLUS;
2570 }
2571 }
2572
2573 if (DWC3_IP_IS(DWC32) &&
2574 speed > USB_SPEED_UNKNOWN &&
2575 speed < USB_SPEED_SUPER_PLUS)
2576 reg &= ~DWC3_DCFG_NUMLANES(~0);
2577
2578 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2579}
2580
2581static int dwc3_gadget_run_stop(struct dwc3 *dwc, int is_on)
2582{
2583 u32 reg;
2584 u32 timeout = 2000;
2585
2586 if (pm_runtime_suspended(dwc->dev))
2587 return 0;
2588
2589 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2590 if (is_on) {
2591 if (DWC3_VER_IS_WITHIN(DWC3, ANY, 187A)) {
2592 reg &= ~DWC3_DCTL_TRGTULST_MASK;
2593 reg |= DWC3_DCTL_TRGTULST_RX_DET;
2594 }
2595
2596 if (!DWC3_VER_IS_PRIOR(DWC3, 194A))
2597 reg &= ~DWC3_DCTL_KEEP_CONNECT;
2598 reg |= DWC3_DCTL_RUN_STOP;
2599
2600 __dwc3_gadget_set_speed(dwc);
2601 dwc->pullups_connected = true;
2602 } else {
2603 reg &= ~DWC3_DCTL_RUN_STOP;
2604
2605 dwc->pullups_connected = false;
2606 }
2607
2608 dwc3_gadget_dctl_write_safe(dwc, reg);
2609
2610 do {
2611 usleep_range(1000, 2000);
2612 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
2613 reg &= DWC3_DSTS_DEVCTRLHLT;
2614 } while (--timeout && !(!is_on ^ !reg));
2615
2616 if (!timeout)
2617 return -ETIMEDOUT;
2618
2619 return 0;
2620}
2621
2622static void dwc3_gadget_disable_irq(struct dwc3 *dwc);
2623static void __dwc3_gadget_stop(struct dwc3 *dwc);
2624static int __dwc3_gadget_start(struct dwc3 *dwc);
2625
2626static int dwc3_gadget_soft_disconnect(struct dwc3 *dwc)
2627{
2628 unsigned long flags;
2629 int ret;
2630
2631 spin_lock_irqsave(&dwc->lock, flags);
2632 if (!dwc->pullups_connected) {
2633 spin_unlock_irqrestore(&dwc->lock, flags);
2634 return 0;
2635 }
2636
2637 dwc->connected = false;
2638
2639 /*
2640 * Attempt to end pending SETUP status phase, and not wait for the
2641 * function to do so.
2642 */
2643 if (dwc->delayed_status)
2644 dwc3_ep0_send_delayed_status(dwc);
2645
2646 /*
2647 * In the Synopsys DesignWare Cores USB3 Databook Rev. 3.30a
2648 * Section 4.1.8 Table 4-7, it states that for a device-initiated
2649 * disconnect, the SW needs to ensure that it sends "a DEPENDXFER
2650 * command for any active transfers" before clearing the RunStop
2651 * bit.
2652 */
2653 dwc3_stop_active_transfers(dwc);
2654 spin_unlock_irqrestore(&dwc->lock, flags);
2655
2656 /*
2657 * Per databook, when we want to stop the gadget, if a control transfer
2658 * is still in process, complete it and get the core into setup phase.
2659 * In case the host is unresponsive to a SETUP transaction, forcefully
2660 * stall the transfer, and move back to the SETUP phase, so that any
2661 * pending endxfers can be executed.
2662 */
2663 if (dwc->ep0state != EP0_SETUP_PHASE) {
2664 reinit_completion(&dwc->ep0_in_setup);
2665
2666 ret = wait_for_completion_timeout(&dwc->ep0_in_setup,
2667 msecs_to_jiffies(DWC3_PULL_UP_TIMEOUT));
2668 if (ret == 0) {
2669 dev_warn(dwc->dev, "wait for SETUP phase timed out\n");
2670 spin_lock_irqsave(&dwc->lock, flags);
2671 dwc3_ep0_reset_state(dwc);
2672 spin_unlock_irqrestore(&dwc->lock, flags);
2673 }
2674 }
2675
2676 /*
2677 * Note: if the GEVNTCOUNT indicates events in the event buffer, the
2678 * driver needs to acknowledge them before the controller can halt.
2679 * Simply let the interrupt handler acknowledges and handle the
2680 * remaining event generated by the controller while polling for
2681 * DSTS.DEVCTLHLT.
2682 */
2683 ret = dwc3_gadget_run_stop(dwc, false);
2684
2685 /*
2686 * Stop the gadget after controller is halted, so that if needed, the
2687 * events to update EP0 state can still occur while the run/stop
2688 * routine polls for the halted state. DEVTEN is cleared as part of
2689 * gadget stop.
2690 */
2691 spin_lock_irqsave(&dwc->lock, flags);
2692 __dwc3_gadget_stop(dwc);
2693 spin_unlock_irqrestore(&dwc->lock, flags);
2694
2695 return ret;
2696}
2697
2698static int dwc3_gadget_soft_connect(struct dwc3 *dwc)
2699{
2700 int ret;
2701
2702 /*
2703 * In the Synopsys DWC_usb31 1.90a programming guide section
2704 * 4.1.9, it specifies that for a reconnect after a
2705 * device-initiated disconnect requires a core soft reset
2706 * (DCTL.CSftRst) before enabling the run/stop bit.
2707 */
2708 ret = dwc3_core_soft_reset(dwc);
2709 if (ret)
2710 return ret;
2711
2712 dwc3_event_buffers_setup(dwc);
2713 __dwc3_gadget_start(dwc);
2714 return dwc3_gadget_run_stop(dwc, true);
2715}
2716
2717static int dwc3_gadget_pullup(struct usb_gadget *g, int is_on)
2718{
2719 struct dwc3 *dwc = gadget_to_dwc(g);
2720 int ret;
2721
2722 is_on = !!is_on;
2723
2724 dwc->softconnect = is_on;
2725
2726 /*
2727 * Avoid issuing a runtime resume if the device is already in the
2728 * suspended state during gadget disconnect. DWC3 gadget was already
2729 * halted/stopped during runtime suspend.
2730 */
2731 if (!is_on) {
2732 pm_runtime_barrier(dwc->dev);
2733 if (pm_runtime_suspended(dwc->dev))
2734 return 0;
2735 }
2736
2737 /*
2738 * Check the return value for successful resume, or error. For a
2739 * successful resume, the DWC3 runtime PM resume routine will handle
2740 * the run stop sequence, so avoid duplicate operations here.
2741 */
2742 ret = pm_runtime_get_sync(dwc->dev);
2743 if (!ret || ret < 0) {
2744 pm_runtime_put(dwc->dev);
2745 if (ret < 0)
2746 pm_runtime_set_suspended(dwc->dev);
2747 return ret;
2748 }
2749
2750 if (dwc->pullups_connected == is_on) {
2751 pm_runtime_put(dwc->dev);
2752 return 0;
2753 }
2754
2755 synchronize_irq(dwc->irq_gadget);
2756
2757 if (!is_on)
2758 ret = dwc3_gadget_soft_disconnect(dwc);
2759 else
2760 ret = dwc3_gadget_soft_connect(dwc);
2761
2762 pm_runtime_put(dwc->dev);
2763
2764 return ret;
2765}
2766
2767static void dwc3_gadget_enable_irq(struct dwc3 *dwc)
2768{
2769 u32 reg;
2770
2771 /* Enable all but Start and End of Frame IRQs */
2772 reg = (DWC3_DEVTEN_EVNTOVERFLOWEN |
2773 DWC3_DEVTEN_CMDCMPLTEN |
2774 DWC3_DEVTEN_ERRTICERREN |
2775 DWC3_DEVTEN_WKUPEVTEN |
2776 DWC3_DEVTEN_CONNECTDONEEN |
2777 DWC3_DEVTEN_USBRSTEN |
2778 DWC3_DEVTEN_DISCONNEVTEN);
2779
2780 if (DWC3_VER_IS_PRIOR(DWC3, 250A))
2781 reg |= DWC3_DEVTEN_ULSTCNGEN;
2782
2783 /* On 2.30a and above this bit enables U3/L2-L1 Suspend Events */
2784 if (!DWC3_VER_IS_PRIOR(DWC3, 230A))
2785 reg |= DWC3_DEVTEN_U3L2L1SUSPEN;
2786
2787 dwc3_writel(dwc->regs, DWC3_DEVTEN, reg);
2788}
2789
2790static void dwc3_gadget_disable_irq(struct dwc3 *dwc)
2791{
2792 /* mask all interrupts */
2793 dwc3_writel(dwc->regs, DWC3_DEVTEN, 0x00);
2794}
2795
2796static irqreturn_t dwc3_interrupt(int irq, void *_dwc);
2797static irqreturn_t dwc3_thread_interrupt(int irq, void *_dwc);
2798
2799/**
2800 * dwc3_gadget_setup_nump - calculate and initialize NUMP field of %DWC3_DCFG
2801 * @dwc: pointer to our context structure
2802 *
2803 * The following looks like complex but it's actually very simple. In order to
2804 * calculate the number of packets we can burst at once on OUT transfers, we're
2805 * gonna use RxFIFO size.
2806 *
2807 * To calculate RxFIFO size we need two numbers:
2808 * MDWIDTH = size, in bits, of the internal memory bus
2809 * RAM2_DEPTH = depth, in MDWIDTH, of internal RAM2 (where RxFIFO sits)
2810 *
2811 * Given these two numbers, the formula is simple:
2812 *
2813 * RxFIFO Size = (RAM2_DEPTH * MDWIDTH / 8) - 24 - 16;
2814 *
2815 * 24 bytes is for 3x SETUP packets
2816 * 16 bytes is a clock domain crossing tolerance
2817 *
2818 * Given RxFIFO Size, NUMP = RxFIFOSize / 1024;
2819 */
2820static void dwc3_gadget_setup_nump(struct dwc3 *dwc)
2821{
2822 u32 ram2_depth;
2823 u32 mdwidth;
2824 u32 nump;
2825 u32 reg;
2826
2827 ram2_depth = DWC3_GHWPARAMS7_RAM2_DEPTH(dwc->hwparams.hwparams7);
2828 mdwidth = dwc3_mdwidth(dwc);
2829
2830 nump = ((ram2_depth * mdwidth / 8) - 24 - 16) / 1024;
2831 nump = min_t(u32, nump, 16);
2832
2833 /* update NumP */
2834 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2835 reg &= ~DWC3_DCFG_NUMP_MASK;
2836 reg |= nump << DWC3_DCFG_NUMP_SHIFT;
2837 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2838}
2839
2840static int __dwc3_gadget_start(struct dwc3 *dwc)
2841{
2842 struct dwc3_ep *dep;
2843 int ret = 0;
2844 u32 reg;
2845
2846 /*
2847 * Use IMOD if enabled via dwc->imod_interval. Otherwise, if
2848 * the core supports IMOD, disable it.
2849 */
2850 if (dwc->imod_interval) {
2851 dwc3_writel(dwc->regs, DWC3_DEV_IMOD(0), dwc->imod_interval);
2852 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), DWC3_GEVNTCOUNT_EHB);
2853 } else if (dwc3_has_imod(dwc)) {
2854 dwc3_writel(dwc->regs, DWC3_DEV_IMOD(0), 0);
2855 }
2856
2857 /*
2858 * We are telling dwc3 that we want to use DCFG.NUMP as ACK TP's NUMP
2859 * field instead of letting dwc3 itself calculate that automatically.
2860 *
2861 * This way, we maximize the chances that we'll be able to get several
2862 * bursts of data without going through any sort of endpoint throttling.
2863 */
2864 reg = dwc3_readl(dwc->regs, DWC3_GRXTHRCFG);
2865 if (DWC3_IP_IS(DWC3))
2866 reg &= ~DWC3_GRXTHRCFG_PKTCNTSEL;
2867 else
2868 reg &= ~DWC31_GRXTHRCFG_PKTCNTSEL;
2869
2870 dwc3_writel(dwc->regs, DWC3_GRXTHRCFG, reg);
2871
2872 dwc3_gadget_setup_nump(dwc);
2873
2874 /*
2875 * Currently the controller handles single stream only. So, Ignore
2876 * Packet Pending bit for stream selection and don't search for another
2877 * stream if the host sends Data Packet with PP=0 (for OUT direction) or
2878 * ACK with NumP=0 and PP=0 (for IN direction). This slightly improves
2879 * the stream performance.
2880 */
2881 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2882 reg |= DWC3_DCFG_IGNSTRMPP;
2883 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2884
2885 /* Enable MST by default if the device is capable of MST */
2886 if (DWC3_MST_CAPABLE(&dwc->hwparams)) {
2887 reg = dwc3_readl(dwc->regs, DWC3_DCFG1);
2888 reg &= ~DWC3_DCFG1_DIS_MST_ENH;
2889 dwc3_writel(dwc->regs, DWC3_DCFG1, reg);
2890 }
2891
2892 /* Start with SuperSpeed Default */
2893 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
2894
2895 ret = dwc3_gadget_start_config(dwc, 0);
2896 if (ret) {
2897 dev_err(dwc->dev, "failed to config endpoints\n");
2898 return ret;
2899 }
2900
2901 dep = dwc->eps[0];
2902 dep->flags = 0;
2903 ret = __dwc3_gadget_ep_enable(dep, DWC3_DEPCFG_ACTION_INIT);
2904 if (ret) {
2905 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
2906 goto err0;
2907 }
2908
2909 dep = dwc->eps[1];
2910 dep->flags = 0;
2911 ret = __dwc3_gadget_ep_enable(dep, DWC3_DEPCFG_ACTION_INIT);
2912 if (ret) {
2913 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
2914 goto err1;
2915 }
2916
2917 /* begin to receive SETUP packets */
2918 dwc->ep0state = EP0_SETUP_PHASE;
2919 dwc->ep0_bounced = false;
2920 dwc->link_state = DWC3_LINK_STATE_SS_DIS;
2921 dwc->delayed_status = false;
2922 dwc3_ep0_out_start(dwc);
2923
2924 dwc3_gadget_enable_irq(dwc);
2925 dwc3_enable_susphy(dwc, true);
2926
2927 return 0;
2928
2929err1:
2930 __dwc3_gadget_ep_disable(dwc->eps[0]);
2931
2932err0:
2933 return ret;
2934}
2935
2936static int dwc3_gadget_start(struct usb_gadget *g,
2937 struct usb_gadget_driver *driver)
2938{
2939 struct dwc3 *dwc = gadget_to_dwc(g);
2940 unsigned long flags;
2941 int ret;
2942 int irq;
2943
2944 irq = dwc->irq_gadget;
2945 ret = request_threaded_irq(irq, dwc3_interrupt, dwc3_thread_interrupt,
2946 IRQF_SHARED, "dwc3", dwc->ev_buf);
2947 if (ret) {
2948 dev_err(dwc->dev, "failed to request irq #%d --> %d\n",
2949 irq, ret);
2950 return ret;
2951 }
2952
2953 spin_lock_irqsave(&dwc->lock, flags);
2954 dwc->gadget_driver = driver;
2955 spin_unlock_irqrestore(&dwc->lock, flags);
2956
2957 if (dwc->sys_wakeup)
2958 device_wakeup_enable(dwc->sysdev);
2959
2960 return 0;
2961}
2962
2963static void __dwc3_gadget_stop(struct dwc3 *dwc)
2964{
2965 dwc3_gadget_disable_irq(dwc);
2966 __dwc3_gadget_ep_disable(dwc->eps[0]);
2967 __dwc3_gadget_ep_disable(dwc->eps[1]);
2968}
2969
2970static int dwc3_gadget_stop(struct usb_gadget *g)
2971{
2972 struct dwc3 *dwc = gadget_to_dwc(g);
2973 unsigned long flags;
2974
2975 if (dwc->sys_wakeup)
2976 device_wakeup_disable(dwc->sysdev);
2977
2978 spin_lock_irqsave(&dwc->lock, flags);
2979 dwc->gadget_driver = NULL;
2980 dwc->max_cfg_eps = 0;
2981 spin_unlock_irqrestore(&dwc->lock, flags);
2982
2983 free_irq(dwc->irq_gadget, dwc->ev_buf);
2984
2985 return 0;
2986}
2987
2988static void dwc3_gadget_config_params(struct usb_gadget *g,
2989 struct usb_dcd_config_params *params)
2990{
2991 struct dwc3 *dwc = gadget_to_dwc(g);
2992
2993 params->besl_baseline = USB_DEFAULT_BESL_UNSPECIFIED;
2994 params->besl_deep = USB_DEFAULT_BESL_UNSPECIFIED;
2995
2996 /* Recommended BESL */
2997 if (!dwc->dis_enblslpm_quirk) {
2998 /*
2999 * If the recommended BESL baseline is 0 or if the BESL deep is
3000 * less than 2, Microsoft's Windows 10 host usb stack will issue
3001 * a usb reset immediately after it receives the extended BOS
3002 * descriptor and the enumeration will fail. To maintain
3003 * compatibility with the Windows' usb stack, let's set the
3004 * recommended BESL baseline to 1 and clamp the BESL deep to be
3005 * within 2 to 15.
3006 */
3007 params->besl_baseline = 1;
3008 if (dwc->is_utmi_l1_suspend)
3009 params->besl_deep =
3010 clamp_t(u8, dwc->hird_threshold, 2, 15);
3011 }
3012
3013 /* U1 Device exit Latency */
3014 if (dwc->dis_u1_entry_quirk)
3015 params->bU1devExitLat = 0;
3016 else
3017 params->bU1devExitLat = DWC3_DEFAULT_U1_DEV_EXIT_LAT;
3018
3019 /* U2 Device exit Latency */
3020 if (dwc->dis_u2_entry_quirk)
3021 params->bU2DevExitLat = 0;
3022 else
3023 params->bU2DevExitLat =
3024 cpu_to_le16(DWC3_DEFAULT_U2_DEV_EXIT_LAT);
3025}
3026
3027static void dwc3_gadget_set_speed(struct usb_gadget *g,
3028 enum usb_device_speed speed)
3029{
3030 struct dwc3 *dwc = gadget_to_dwc(g);
3031 unsigned long flags;
3032
3033 spin_lock_irqsave(&dwc->lock, flags);
3034 dwc->gadget_max_speed = speed;
3035 spin_unlock_irqrestore(&dwc->lock, flags);
3036}
3037
3038static void dwc3_gadget_set_ssp_rate(struct usb_gadget *g,
3039 enum usb_ssp_rate rate)
3040{
3041 struct dwc3 *dwc = gadget_to_dwc(g);
3042 unsigned long flags;
3043
3044 spin_lock_irqsave(&dwc->lock, flags);
3045 dwc->gadget_max_speed = USB_SPEED_SUPER_PLUS;
3046 dwc->gadget_ssp_rate = rate;
3047 spin_unlock_irqrestore(&dwc->lock, flags);
3048}
3049
3050static int dwc3_gadget_vbus_draw(struct usb_gadget *g, unsigned int mA)
3051{
3052 struct dwc3 *dwc = gadget_to_dwc(g);
3053 union power_supply_propval val = {0};
3054 int ret;
3055
3056 if (dwc->usb2_phy)
3057 return usb_phy_set_power(dwc->usb2_phy, mA);
3058
3059 if (!dwc->usb_psy)
3060 return -EOPNOTSUPP;
3061
3062 val.intval = 1000 * mA;
3063 ret = power_supply_set_property(dwc->usb_psy, POWER_SUPPLY_PROP_INPUT_CURRENT_LIMIT, &val);
3064
3065 return ret;
3066}
3067
3068/**
3069 * dwc3_gadget_check_config - ensure dwc3 can support the USB configuration
3070 * @g: pointer to the USB gadget
3071 *
3072 * Used to record the maximum number of endpoints being used in a USB composite
3073 * device. (across all configurations) This is to be used in the calculation
3074 * of the TXFIFO sizes when resizing internal memory for individual endpoints.
3075 * It will help ensured that the resizing logic reserves enough space for at
3076 * least one max packet.
3077 */
3078static int dwc3_gadget_check_config(struct usb_gadget *g)
3079{
3080 struct dwc3 *dwc = gadget_to_dwc(g);
3081 struct usb_ep *ep;
3082 int fifo_size = 0;
3083 int ram1_depth;
3084 int ep_num = 0;
3085
3086 if (!dwc->do_fifo_resize)
3087 return 0;
3088
3089 list_for_each_entry(ep, &g->ep_list, ep_list) {
3090 /* Only interested in the IN endpoints */
3091 if (ep->claimed && (ep->address & USB_DIR_IN))
3092 ep_num++;
3093 }
3094
3095 if (ep_num <= dwc->max_cfg_eps)
3096 return 0;
3097
3098 /* Update the max number of eps in the composition */
3099 dwc->max_cfg_eps = ep_num;
3100
3101 fifo_size = dwc3_gadget_calc_tx_fifo_size(dwc, dwc->max_cfg_eps);
3102 /* Based on the equation, increment by one for every ep */
3103 fifo_size += dwc->max_cfg_eps;
3104
3105 /* Check if we can fit a single fifo per endpoint */
3106 ram1_depth = DWC3_RAM1_DEPTH(dwc->hwparams.hwparams7);
3107 if (fifo_size > ram1_depth)
3108 return -ENOMEM;
3109
3110 return 0;
3111}
3112
3113static void dwc3_gadget_async_callbacks(struct usb_gadget *g, bool enable)
3114{
3115 struct dwc3 *dwc = gadget_to_dwc(g);
3116 unsigned long flags;
3117
3118 spin_lock_irqsave(&dwc->lock, flags);
3119 dwc->async_callbacks = enable;
3120 spin_unlock_irqrestore(&dwc->lock, flags);
3121}
3122
3123static const struct usb_gadget_ops dwc3_gadget_ops = {
3124 .get_frame = dwc3_gadget_get_frame,
3125 .wakeup = dwc3_gadget_wakeup,
3126 .func_wakeup = dwc3_gadget_func_wakeup,
3127 .set_remote_wakeup = dwc3_gadget_set_remote_wakeup,
3128 .set_selfpowered = dwc3_gadget_set_selfpowered,
3129 .pullup = dwc3_gadget_pullup,
3130 .udc_start = dwc3_gadget_start,
3131 .udc_stop = dwc3_gadget_stop,
3132 .udc_set_speed = dwc3_gadget_set_speed,
3133 .udc_set_ssp_rate = dwc3_gadget_set_ssp_rate,
3134 .get_config_params = dwc3_gadget_config_params,
3135 .vbus_draw = dwc3_gadget_vbus_draw,
3136 .check_config = dwc3_gadget_check_config,
3137 .udc_async_callbacks = dwc3_gadget_async_callbacks,
3138};
3139
3140/* -------------------------------------------------------------------------- */
3141
3142static int dwc3_gadget_init_control_endpoint(struct dwc3_ep *dep)
3143{
3144 struct dwc3 *dwc = dep->dwc;
3145
3146 usb_ep_set_maxpacket_limit(&dep->endpoint, 512);
3147 dep->endpoint.maxburst = 1;
3148 dep->endpoint.ops = &dwc3_gadget_ep0_ops;
3149 if (!dep->direction)
3150 dwc->gadget->ep0 = &dep->endpoint;
3151
3152 dep->endpoint.caps.type_control = true;
3153
3154 return 0;
3155}
3156
3157static int dwc3_gadget_init_in_endpoint(struct dwc3_ep *dep)
3158{
3159 struct dwc3 *dwc = dep->dwc;
3160 u32 mdwidth;
3161 int size;
3162 int maxpacket;
3163
3164 mdwidth = dwc3_mdwidth(dwc);
3165
3166 /* MDWIDTH is represented in bits, we need it in bytes */
3167 mdwidth /= 8;
3168
3169 size = dwc3_readl(dwc->regs, DWC3_GTXFIFOSIZ(dep->number >> 1));
3170 if (DWC3_IP_IS(DWC3))
3171 size = DWC3_GTXFIFOSIZ_TXFDEP(size);
3172 else
3173 size = DWC31_GTXFIFOSIZ_TXFDEP(size);
3174
3175 /*
3176 * maxpacket size is determined as part of the following, after assuming
3177 * a mult value of one maxpacket:
3178 * DWC3 revision 280A and prior:
3179 * fifo_size = mult * (max_packet / mdwidth) + 1;
3180 * maxpacket = mdwidth * (fifo_size - 1);
3181 *
3182 * DWC3 revision 290A and onwards:
3183 * fifo_size = mult * ((max_packet + mdwidth)/mdwidth + 1) + 1
3184 * maxpacket = mdwidth * ((fifo_size - 1) - 1) - mdwidth;
3185 */
3186 if (DWC3_VER_IS_PRIOR(DWC3, 290A))
3187 maxpacket = mdwidth * (size - 1);
3188 else
3189 maxpacket = mdwidth * ((size - 1) - 1) - mdwidth;
3190
3191 /* Functionally, space for one max packet is sufficient */
3192 size = min_t(int, maxpacket, 1024);
3193 usb_ep_set_maxpacket_limit(&dep->endpoint, size);
3194
3195 dep->endpoint.max_streams = 16;
3196 dep->endpoint.ops = &dwc3_gadget_ep_ops;
3197 list_add_tail(&dep->endpoint.ep_list,
3198 &dwc->gadget->ep_list);
3199 dep->endpoint.caps.type_iso = true;
3200 dep->endpoint.caps.type_bulk = true;
3201 dep->endpoint.caps.type_int = true;
3202
3203 return dwc3_alloc_trb_pool(dep);
3204}
3205
3206static int dwc3_gadget_init_out_endpoint(struct dwc3_ep *dep)
3207{
3208 struct dwc3 *dwc = dep->dwc;
3209 u32 mdwidth;
3210 int size;
3211
3212 mdwidth = dwc3_mdwidth(dwc);
3213
3214 /* MDWIDTH is represented in bits, convert to bytes */
3215 mdwidth /= 8;
3216
3217 /* All OUT endpoints share a single RxFIFO space */
3218 size = dwc3_readl(dwc->regs, DWC3_GRXFIFOSIZ(0));
3219 if (DWC3_IP_IS(DWC3))
3220 size = DWC3_GRXFIFOSIZ_RXFDEP(size);
3221 else
3222 size = DWC31_GRXFIFOSIZ_RXFDEP(size);
3223
3224 /* FIFO depth is in MDWDITH bytes */
3225 size *= mdwidth;
3226
3227 /*
3228 * To meet performance requirement, a minimum recommended RxFIFO size
3229 * is defined as follow:
3230 * RxFIFO size >= (3 x MaxPacketSize) +
3231 * (3 x 8 bytes setup packets size) + (16 bytes clock crossing margin)
3232 *
3233 * Then calculate the max packet limit as below.
3234 */
3235 size -= (3 * 8) + 16;
3236 if (size < 0)
3237 size = 0;
3238 else
3239 size /= 3;
3240
3241 usb_ep_set_maxpacket_limit(&dep->endpoint, size);
3242 dep->endpoint.max_streams = 16;
3243 dep->endpoint.ops = &dwc3_gadget_ep_ops;
3244 list_add_tail(&dep->endpoint.ep_list,
3245 &dwc->gadget->ep_list);
3246 dep->endpoint.caps.type_iso = true;
3247 dep->endpoint.caps.type_bulk = true;
3248 dep->endpoint.caps.type_int = true;
3249
3250 return dwc3_alloc_trb_pool(dep);
3251}
3252
3253static int dwc3_gadget_init_endpoint(struct dwc3 *dwc, u8 epnum)
3254{
3255 struct dwc3_ep *dep;
3256 bool direction = epnum & 1;
3257 int ret;
3258 u8 num = epnum >> 1;
3259
3260 dep = kzalloc(sizeof(*dep), GFP_KERNEL);
3261 if (!dep)
3262 return -ENOMEM;
3263
3264 dep->dwc = dwc;
3265 dep->number = epnum;
3266 dep->direction = direction;
3267 dep->regs = dwc->regs + DWC3_DEP_BASE(epnum);
3268 dwc->eps[epnum] = dep;
3269 dep->combo_num = 0;
3270 dep->start_cmd_status = 0;
3271
3272 snprintf(dep->name, sizeof(dep->name), "ep%u%s", num,
3273 direction ? "in" : "out");
3274
3275 dep->endpoint.name = dep->name;
3276
3277 if (!(dep->number > 1)) {
3278 dep->endpoint.desc = &dwc3_gadget_ep0_desc;
3279 dep->endpoint.comp_desc = NULL;
3280 }
3281
3282 if (num == 0)
3283 ret = dwc3_gadget_init_control_endpoint(dep);
3284 else if (direction)
3285 ret = dwc3_gadget_init_in_endpoint(dep);
3286 else
3287 ret = dwc3_gadget_init_out_endpoint(dep);
3288
3289 if (ret)
3290 return ret;
3291
3292 dep->endpoint.caps.dir_in = direction;
3293 dep->endpoint.caps.dir_out = !direction;
3294
3295 INIT_LIST_HEAD(&dep->pending_list);
3296 INIT_LIST_HEAD(&dep->started_list);
3297 INIT_LIST_HEAD(&dep->cancelled_list);
3298
3299 dwc3_debugfs_create_endpoint_dir(dep);
3300
3301 return 0;
3302}
3303
3304static int dwc3_gadget_init_endpoints(struct dwc3 *dwc, u8 total)
3305{
3306 u8 epnum;
3307
3308 INIT_LIST_HEAD(&dwc->gadget->ep_list);
3309
3310 for (epnum = 0; epnum < total; epnum++) {
3311 int ret;
3312
3313 ret = dwc3_gadget_init_endpoint(dwc, epnum);
3314 if (ret)
3315 return ret;
3316 }
3317
3318 return 0;
3319}
3320
3321static void dwc3_gadget_free_endpoints(struct dwc3 *dwc)
3322{
3323 struct dwc3_ep *dep;
3324 u8 epnum;
3325
3326 for (epnum = 0; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
3327 dep = dwc->eps[epnum];
3328 if (!dep)
3329 continue;
3330 /*
3331 * Physical endpoints 0 and 1 are special; they form the
3332 * bi-directional USB endpoint 0.
3333 *
3334 * For those two physical endpoints, we don't allocate a TRB
3335 * pool nor do we add them the endpoints list. Due to that, we
3336 * shouldn't do these two operations otherwise we would end up
3337 * with all sorts of bugs when removing dwc3.ko.
3338 */
3339 if (epnum != 0 && epnum != 1) {
3340 dwc3_free_trb_pool(dep);
3341 list_del(&dep->endpoint.ep_list);
3342 }
3343
3344 dwc3_debugfs_remove_endpoint_dir(dep);
3345 kfree(dep);
3346 }
3347}
3348
3349/* -------------------------------------------------------------------------- */
3350
3351static int dwc3_gadget_ep_reclaim_completed_trb(struct dwc3_ep *dep,
3352 struct dwc3_request *req, struct dwc3_trb *trb,
3353 const struct dwc3_event_depevt *event, int status, int chain)
3354{
3355 unsigned int count;
3356
3357 dwc3_ep_inc_deq(dep);
3358
3359 trace_dwc3_complete_trb(dep, trb);
3360 req->num_trbs--;
3361
3362 /*
3363 * If we're in the middle of series of chained TRBs and we
3364 * receive a short transfer along the way, DWC3 will skip
3365 * through all TRBs including the last TRB in the chain (the
3366 * where CHN bit is zero. DWC3 will also avoid clearing HWO
3367 * bit and SW has to do it manually.
3368 *
3369 * We're going to do that here to avoid problems of HW trying
3370 * to use bogus TRBs for transfers.
3371 */
3372 if (chain && (trb->ctrl & DWC3_TRB_CTRL_HWO))
3373 trb->ctrl &= ~DWC3_TRB_CTRL_HWO;
3374
3375 /*
3376 * For isochronous transfers, the first TRB in a service interval must
3377 * have the Isoc-First type. Track and report its interval frame number.
3378 */
3379 if (usb_endpoint_xfer_isoc(dep->endpoint.desc) &&
3380 (trb->ctrl & DWC3_TRBCTL_ISOCHRONOUS_FIRST)) {
3381 unsigned int frame_number;
3382
3383 frame_number = DWC3_TRB_CTRL_GET_SID_SOFN(trb->ctrl);
3384 frame_number &= ~(dep->interval - 1);
3385 req->request.frame_number = frame_number;
3386 }
3387
3388 /*
3389 * We use bounce buffer for requests that needs extra TRB or OUT ZLP. If
3390 * this TRB points to the bounce buffer address, it's a MPS alignment
3391 * TRB. Don't add it to req->remaining calculation.
3392 */
3393 if (trb->bpl == lower_32_bits(dep->dwc->bounce_addr) &&
3394 trb->bph == upper_32_bits(dep->dwc->bounce_addr)) {
3395 trb->ctrl &= ~DWC3_TRB_CTRL_HWO;
3396 return 1;
3397 }
3398
3399 count = trb->size & DWC3_TRB_SIZE_MASK;
3400 req->remaining += count;
3401
3402 if ((trb->ctrl & DWC3_TRB_CTRL_HWO) && status != -ESHUTDOWN)
3403 return 1;
3404
3405 if (event->status & DEPEVT_STATUS_SHORT && !chain)
3406 return 1;
3407
3408 if ((trb->ctrl & DWC3_TRB_CTRL_ISP_IMI) &&
3409 DWC3_TRB_SIZE_TRBSTS(trb->size) == DWC3_TRBSTS_MISSED_ISOC)
3410 return 1;
3411
3412 if ((trb->ctrl & DWC3_TRB_CTRL_IOC) ||
3413 (trb->ctrl & DWC3_TRB_CTRL_LST))
3414 return 1;
3415
3416 return 0;
3417}
3418
3419static int dwc3_gadget_ep_reclaim_trb_sg(struct dwc3_ep *dep,
3420 struct dwc3_request *req, const struct dwc3_event_depevt *event,
3421 int status)
3422{
3423 struct dwc3_trb *trb;
3424 struct scatterlist *sg = req->sg;
3425 struct scatterlist *s;
3426 unsigned int num_queued = req->num_queued_sgs;
3427 unsigned int i;
3428 int ret = 0;
3429
3430 for_each_sg(sg, s, num_queued, i) {
3431 trb = &dep->trb_pool[dep->trb_dequeue];
3432
3433 req->sg = sg_next(s);
3434 req->num_queued_sgs--;
3435
3436 ret = dwc3_gadget_ep_reclaim_completed_trb(dep, req,
3437 trb, event, status, true);
3438 if (ret)
3439 break;
3440 }
3441
3442 return ret;
3443}
3444
3445static int dwc3_gadget_ep_reclaim_trb_linear(struct dwc3_ep *dep,
3446 struct dwc3_request *req, const struct dwc3_event_depevt *event,
3447 int status)
3448{
3449 struct dwc3_trb *trb = &dep->trb_pool[dep->trb_dequeue];
3450
3451 return dwc3_gadget_ep_reclaim_completed_trb(dep, req, trb,
3452 event, status, false);
3453}
3454
3455static bool dwc3_gadget_ep_request_completed(struct dwc3_request *req)
3456{
3457 return req->num_pending_sgs == 0 && req->num_queued_sgs == 0;
3458}
3459
3460static int dwc3_gadget_ep_cleanup_completed_request(struct dwc3_ep *dep,
3461 const struct dwc3_event_depevt *event,
3462 struct dwc3_request *req, int status)
3463{
3464 int request_status;
3465 int ret;
3466
3467 if (req->request.num_mapped_sgs)
3468 ret = dwc3_gadget_ep_reclaim_trb_sg(dep, req, event,
3469 status);
3470 else
3471 ret = dwc3_gadget_ep_reclaim_trb_linear(dep, req, event,
3472 status);
3473
3474 req->request.actual = req->request.length - req->remaining;
3475
3476 if (!dwc3_gadget_ep_request_completed(req))
3477 goto out;
3478
3479 if (req->needs_extra_trb) {
3480 ret = dwc3_gadget_ep_reclaim_trb_linear(dep, req, event,
3481 status);
3482 req->needs_extra_trb = false;
3483 }
3484
3485 /*
3486 * The event status only reflects the status of the TRB with IOC set.
3487 * For the requests that don't set interrupt on completion, the driver
3488 * needs to check and return the status of the completed TRBs associated
3489 * with the request. Use the status of the last TRB of the request.
3490 */
3491 if (req->request.no_interrupt) {
3492 struct dwc3_trb *trb;
3493
3494 trb = dwc3_ep_prev_trb(dep, dep->trb_dequeue);
3495 switch (DWC3_TRB_SIZE_TRBSTS(trb->size)) {
3496 case DWC3_TRBSTS_MISSED_ISOC:
3497 /* Isoc endpoint only */
3498 request_status = -EXDEV;
3499 break;
3500 case DWC3_TRB_STS_XFER_IN_PROG:
3501 /* Applicable when End Transfer with ForceRM=0 */
3502 case DWC3_TRBSTS_SETUP_PENDING:
3503 /* Control endpoint only */
3504 case DWC3_TRBSTS_OK:
3505 default:
3506 request_status = 0;
3507 break;
3508 }
3509 } else {
3510 request_status = status;
3511 }
3512
3513 dwc3_gadget_giveback(dep, req, request_status);
3514
3515out:
3516 return ret;
3517}
3518
3519static void dwc3_gadget_ep_cleanup_completed_requests(struct dwc3_ep *dep,
3520 const struct dwc3_event_depevt *event, int status)
3521{
3522 struct dwc3_request *req;
3523
3524 while (!list_empty(&dep->started_list)) {
3525 int ret;
3526
3527 req = next_request(&dep->started_list);
3528 ret = dwc3_gadget_ep_cleanup_completed_request(dep, event,
3529 req, status);
3530 if (ret)
3531 break;
3532 /*
3533 * The endpoint is disabled, let the dwc3_remove_requests()
3534 * handle the cleanup.
3535 */
3536 if (!dep->endpoint.desc)
3537 break;
3538 }
3539}
3540
3541static bool dwc3_gadget_ep_should_continue(struct dwc3_ep *dep)
3542{
3543 struct dwc3_request *req;
3544 struct dwc3 *dwc = dep->dwc;
3545
3546 if (!dep->endpoint.desc || !dwc->pullups_connected ||
3547 !dwc->connected)
3548 return false;
3549
3550 if (!list_empty(&dep->pending_list))
3551 return true;
3552
3553 /*
3554 * We only need to check the first entry of the started list. We can
3555 * assume the completed requests are removed from the started list.
3556 */
3557 req = next_request(&dep->started_list);
3558 if (!req)
3559 return false;
3560
3561 return !dwc3_gadget_ep_request_completed(req);
3562}
3563
3564static void dwc3_gadget_endpoint_frame_from_event(struct dwc3_ep *dep,
3565 const struct dwc3_event_depevt *event)
3566{
3567 dep->frame_number = event->parameters;
3568}
3569
3570static bool dwc3_gadget_endpoint_trbs_complete(struct dwc3_ep *dep,
3571 const struct dwc3_event_depevt *event, int status)
3572{
3573 struct dwc3 *dwc = dep->dwc;
3574 bool no_started_trb = true;
3575
3576 dwc3_gadget_ep_cleanup_completed_requests(dep, event, status);
3577
3578 if (dep->flags & DWC3_EP_END_TRANSFER_PENDING)
3579 goto out;
3580
3581 if (!dep->endpoint.desc)
3582 return no_started_trb;
3583
3584 if (usb_endpoint_xfer_isoc(dep->endpoint.desc) &&
3585 list_empty(&dep->started_list) &&
3586 (list_empty(&dep->pending_list) || status == -EXDEV))
3587 dwc3_stop_active_transfer(dep, true, true);
3588 else if (dwc3_gadget_ep_should_continue(dep))
3589 if (__dwc3_gadget_kick_transfer(dep) == 0)
3590 no_started_trb = false;
3591
3592out:
3593 /*
3594 * WORKAROUND: This is the 2nd half of U1/U2 -> U0 workaround.
3595 * See dwc3_gadget_linksts_change_interrupt() for 1st half.
3596 */
3597 if (DWC3_VER_IS_PRIOR(DWC3, 183A)) {
3598 u32 reg;
3599 int i;
3600
3601 for (i = 0; i < DWC3_ENDPOINTS_NUM; i++) {
3602 dep = dwc->eps[i];
3603
3604 if (!(dep->flags & DWC3_EP_ENABLED))
3605 continue;
3606
3607 if (!list_empty(&dep->started_list))
3608 return no_started_trb;
3609 }
3610
3611 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
3612 reg |= dwc->u1u2;
3613 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
3614
3615 dwc->u1u2 = 0;
3616 }
3617
3618 return no_started_trb;
3619}
3620
3621static void dwc3_gadget_endpoint_transfer_in_progress(struct dwc3_ep *dep,
3622 const struct dwc3_event_depevt *event)
3623{
3624 int status = 0;
3625
3626 if (!dep->endpoint.desc)
3627 return;
3628
3629 if (usb_endpoint_xfer_isoc(dep->endpoint.desc))
3630 dwc3_gadget_endpoint_frame_from_event(dep, event);
3631
3632 if (event->status & DEPEVT_STATUS_BUSERR)
3633 status = -ECONNRESET;
3634
3635 if (event->status & DEPEVT_STATUS_MISSED_ISOC)
3636 status = -EXDEV;
3637
3638 dwc3_gadget_endpoint_trbs_complete(dep, event, status);
3639}
3640
3641static void dwc3_gadget_endpoint_transfer_complete(struct dwc3_ep *dep,
3642 const struct dwc3_event_depevt *event)
3643{
3644 int status = 0;
3645
3646 dep->flags &= ~DWC3_EP_TRANSFER_STARTED;
3647
3648 if (event->status & DEPEVT_STATUS_BUSERR)
3649 status = -ECONNRESET;
3650
3651 if (dwc3_gadget_endpoint_trbs_complete(dep, event, status))
3652 dep->flags &= ~DWC3_EP_WAIT_TRANSFER_COMPLETE;
3653}
3654
3655static void dwc3_gadget_endpoint_transfer_not_ready(struct dwc3_ep *dep,
3656 const struct dwc3_event_depevt *event)
3657{
3658 dwc3_gadget_endpoint_frame_from_event(dep, event);
3659
3660 /*
3661 * The XferNotReady event is generated only once before the endpoint
3662 * starts. It will be generated again when END_TRANSFER command is
3663 * issued. For some controller versions, the XferNotReady event may be
3664 * generated while the END_TRANSFER command is still in process. Ignore
3665 * it and wait for the next XferNotReady event after the command is
3666 * completed.
3667 */
3668 if (dep->flags & DWC3_EP_END_TRANSFER_PENDING)
3669 return;
3670
3671 (void) __dwc3_gadget_start_isoc(dep);
3672}
3673
3674static void dwc3_gadget_endpoint_command_complete(struct dwc3_ep *dep,
3675 const struct dwc3_event_depevt *event)
3676{
3677 u8 cmd = DEPEVT_PARAMETER_CMD(event->parameters);
3678
3679 if (cmd != DWC3_DEPCMD_ENDTRANSFER)
3680 return;
3681
3682 /*
3683 * The END_TRANSFER command will cause the controller to generate a
3684 * NoStream Event, and it's not due to the host DP NoStream rejection.
3685 * Ignore the next NoStream event.
3686 */
3687 if (dep->stream_capable)
3688 dep->flags |= DWC3_EP_IGNORE_NEXT_NOSTREAM;
3689
3690 dep->flags &= ~DWC3_EP_END_TRANSFER_PENDING;
3691 dep->flags &= ~DWC3_EP_TRANSFER_STARTED;
3692 dwc3_gadget_ep_cleanup_cancelled_requests(dep);
3693
3694 if (dep->flags & DWC3_EP_PENDING_CLEAR_STALL) {
3695 struct dwc3 *dwc = dep->dwc;
3696
3697 dep->flags &= ~DWC3_EP_PENDING_CLEAR_STALL;
3698 if (dwc3_send_clear_stall_ep_cmd(dep)) {
3699 struct usb_ep *ep0 = &dwc->eps[0]->endpoint;
3700
3701 dev_err(dwc->dev, "failed to clear STALL on %s\n", dep->name);
3702 if (dwc->delayed_status)
3703 __dwc3_gadget_ep0_set_halt(ep0, 1);
3704 return;
3705 }
3706
3707 dep->flags &= ~(DWC3_EP_STALL | DWC3_EP_WEDGE);
3708 if (dwc->clear_stall_protocol == dep->number)
3709 dwc3_ep0_send_delayed_status(dwc);
3710 }
3711
3712 if ((dep->flags & DWC3_EP_DELAY_START) &&
3713 !usb_endpoint_xfer_isoc(dep->endpoint.desc))
3714 __dwc3_gadget_kick_transfer(dep);
3715
3716 dep->flags &= ~DWC3_EP_DELAY_START;
3717}
3718
3719static void dwc3_gadget_endpoint_stream_event(struct dwc3_ep *dep,
3720 const struct dwc3_event_depevt *event)
3721{
3722 struct dwc3 *dwc = dep->dwc;
3723
3724 if (event->status == DEPEVT_STREAMEVT_FOUND) {
3725 dep->flags |= DWC3_EP_FIRST_STREAM_PRIMED;
3726 goto out;
3727 }
3728
3729 /* Note: NoStream rejection event param value is 0 and not 0xFFFF */
3730 switch (event->parameters) {
3731 case DEPEVT_STREAM_PRIME:
3732 /*
3733 * If the host can properly transition the endpoint state from
3734 * idle to prime after a NoStream rejection, there's no need to
3735 * force restarting the endpoint to reinitiate the stream. To
3736 * simplify the check, assume the host follows the USB spec if
3737 * it primed the endpoint more than once.
3738 */
3739 if (dep->flags & DWC3_EP_FORCE_RESTART_STREAM) {
3740 if (dep->flags & DWC3_EP_FIRST_STREAM_PRIMED)
3741 dep->flags &= ~DWC3_EP_FORCE_RESTART_STREAM;
3742 else
3743 dep->flags |= DWC3_EP_FIRST_STREAM_PRIMED;
3744 }
3745
3746 break;
3747 case DEPEVT_STREAM_NOSTREAM:
3748 if ((dep->flags & DWC3_EP_IGNORE_NEXT_NOSTREAM) ||
3749 !(dep->flags & DWC3_EP_FORCE_RESTART_STREAM) ||
3750 (!DWC3_MST_CAPABLE(&dwc->hwparams) &&
3751 !(dep->flags & DWC3_EP_WAIT_TRANSFER_COMPLETE)))
3752 break;
3753
3754 /*
3755 * If the host rejects a stream due to no active stream, by the
3756 * USB and xHCI spec, the endpoint will be put back to idle
3757 * state. When the host is ready (buffer added/updated), it will
3758 * prime the endpoint to inform the usb device controller. This
3759 * triggers the device controller to issue ERDY to restart the
3760 * stream. However, some hosts don't follow this and keep the
3761 * endpoint in the idle state. No prime will come despite host
3762 * streams are updated, and the device controller will not be
3763 * triggered to generate ERDY to move the next stream data. To
3764 * workaround this and maintain compatibility with various
3765 * hosts, force to reinitiate the stream until the host is ready
3766 * instead of waiting for the host to prime the endpoint.
3767 */
3768 if (DWC3_VER_IS_WITHIN(DWC32, 100A, ANY)) {
3769 unsigned int cmd = DWC3_DGCMD_SET_ENDPOINT_PRIME;
3770
3771 dwc3_send_gadget_generic_command(dwc, cmd, dep->number);
3772 } else {
3773 dep->flags |= DWC3_EP_DELAY_START;
3774 dwc3_stop_active_transfer(dep, true, true);
3775 return;
3776 }
3777 break;
3778 }
3779
3780out:
3781 dep->flags &= ~DWC3_EP_IGNORE_NEXT_NOSTREAM;
3782}
3783
3784static void dwc3_endpoint_interrupt(struct dwc3 *dwc,
3785 const struct dwc3_event_depevt *event)
3786{
3787 struct dwc3_ep *dep;
3788 u8 epnum = event->endpoint_number;
3789
3790 dep = dwc->eps[epnum];
3791
3792 if (!(dep->flags & DWC3_EP_ENABLED)) {
3793 if ((epnum > 1) && !(dep->flags & DWC3_EP_TRANSFER_STARTED))
3794 return;
3795
3796 /* Handle only EPCMDCMPLT when EP disabled */
3797 if ((event->endpoint_event != DWC3_DEPEVT_EPCMDCMPLT) &&
3798 !(epnum <= 1 && event->endpoint_event == DWC3_DEPEVT_XFERCOMPLETE))
3799 return;
3800 }
3801
3802 if (epnum == 0 || epnum == 1) {
3803 dwc3_ep0_interrupt(dwc, event);
3804 return;
3805 }
3806
3807 switch (event->endpoint_event) {
3808 case DWC3_DEPEVT_XFERINPROGRESS:
3809 dwc3_gadget_endpoint_transfer_in_progress(dep, event);
3810 break;
3811 case DWC3_DEPEVT_XFERNOTREADY:
3812 dwc3_gadget_endpoint_transfer_not_ready(dep, event);
3813 break;
3814 case DWC3_DEPEVT_EPCMDCMPLT:
3815 dwc3_gadget_endpoint_command_complete(dep, event);
3816 break;
3817 case DWC3_DEPEVT_XFERCOMPLETE:
3818 dwc3_gadget_endpoint_transfer_complete(dep, event);
3819 break;
3820 case DWC3_DEPEVT_STREAMEVT:
3821 dwc3_gadget_endpoint_stream_event(dep, event);
3822 break;
3823 case DWC3_DEPEVT_RXTXFIFOEVT:
3824 break;
3825 default:
3826 dev_err(dwc->dev, "unknown endpoint event %d\n", event->endpoint_event);
3827 break;
3828 }
3829}
3830
3831static void dwc3_disconnect_gadget(struct dwc3 *dwc)
3832{
3833 if (dwc->async_callbacks && dwc->gadget_driver->disconnect) {
3834 spin_unlock(&dwc->lock);
3835 dwc->gadget_driver->disconnect(dwc->gadget);
3836 spin_lock(&dwc->lock);
3837 }
3838}
3839
3840static void dwc3_suspend_gadget(struct dwc3 *dwc)
3841{
3842 if (dwc->async_callbacks && dwc->gadget_driver->suspend) {
3843 spin_unlock(&dwc->lock);
3844 dwc->gadget_driver->suspend(dwc->gadget);
3845 spin_lock(&dwc->lock);
3846 }
3847}
3848
3849static void dwc3_resume_gadget(struct dwc3 *dwc)
3850{
3851 if (dwc->async_callbacks && dwc->gadget_driver->resume) {
3852 spin_unlock(&dwc->lock);
3853 dwc->gadget_driver->resume(dwc->gadget);
3854 spin_lock(&dwc->lock);
3855 }
3856}
3857
3858static void dwc3_reset_gadget(struct dwc3 *dwc)
3859{
3860 if (!dwc->gadget_driver)
3861 return;
3862
3863 if (dwc->async_callbacks && dwc->gadget->speed != USB_SPEED_UNKNOWN) {
3864 spin_unlock(&dwc->lock);
3865 usb_gadget_udc_reset(dwc->gadget, dwc->gadget_driver);
3866 spin_lock(&dwc->lock);
3867 }
3868}
3869
3870void dwc3_stop_active_transfer(struct dwc3_ep *dep, bool force,
3871 bool interrupt)
3872{
3873 struct dwc3 *dwc = dep->dwc;
3874
3875 /*
3876 * Only issue End Transfer command to the control endpoint of a started
3877 * Data Phase. Typically we should only do so in error cases such as
3878 * invalid/unexpected direction as described in the control transfer
3879 * flow of the programming guide.
3880 */
3881 if (dep->number <= 1 && dwc->ep0state != EP0_DATA_PHASE)
3882 return;
3883
3884 if (interrupt && (dep->flags & DWC3_EP_DELAY_STOP))
3885 return;
3886
3887 if (!(dep->flags & DWC3_EP_TRANSFER_STARTED) ||
3888 (dep->flags & DWC3_EP_END_TRANSFER_PENDING))
3889 return;
3890
3891 /*
3892 * If a Setup packet is received but yet to DMA out, the controller will
3893 * not process the End Transfer command of any endpoint. Polling of its
3894 * DEPCMD.CmdAct may block setting up TRB for Setup packet, causing a
3895 * timeout. Delay issuing the End Transfer command until the Setup TRB is
3896 * prepared.
3897 */
3898 if (dwc->ep0state != EP0_SETUP_PHASE && !dwc->delayed_status) {
3899 dep->flags |= DWC3_EP_DELAY_STOP;
3900 return;
3901 }
3902
3903 /*
3904 * NOTICE: We are violating what the Databook says about the
3905 * EndTransfer command. Ideally we would _always_ wait for the
3906 * EndTransfer Command Completion IRQ, but that's causing too
3907 * much trouble synchronizing between us and gadget driver.
3908 *
3909 * We have discussed this with the IP Provider and it was
3910 * suggested to giveback all requests here.
3911 *
3912 * Note also that a similar handling was tested by Synopsys
3913 * (thanks a lot Paul) and nothing bad has come out of it.
3914 * In short, what we're doing is issuing EndTransfer with
3915 * CMDIOC bit set and delay kicking transfer until the
3916 * EndTransfer command had completed.
3917 *
3918 * As of IP version 3.10a of the DWC_usb3 IP, the controller
3919 * supports a mode to work around the above limitation. The
3920 * software can poll the CMDACT bit in the DEPCMD register
3921 * after issuing a EndTransfer command. This mode is enabled
3922 * by writing GUCTL2[14]. This polling is already done in the
3923 * dwc3_send_gadget_ep_cmd() function so if the mode is
3924 * enabled, the EndTransfer command will have completed upon
3925 * returning from this function.
3926 *
3927 * This mode is NOT available on the DWC_usb31 IP. In this
3928 * case, if the IOC bit is not set, then delay by 1ms
3929 * after issuing the EndTransfer command. This allows for the
3930 * controller to handle the command completely before DWC3
3931 * remove requests attempts to unmap USB request buffers.
3932 */
3933
3934 __dwc3_stop_active_transfer(dep, force, interrupt);
3935}
3936
3937static void dwc3_clear_stall_all_ep(struct dwc3 *dwc)
3938{
3939 u32 epnum;
3940
3941 for (epnum = 1; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
3942 struct dwc3_ep *dep;
3943 int ret;
3944
3945 dep = dwc->eps[epnum];
3946 if (!dep)
3947 continue;
3948
3949 if (!(dep->flags & DWC3_EP_STALL))
3950 continue;
3951
3952 dep->flags &= ~DWC3_EP_STALL;
3953
3954 ret = dwc3_send_clear_stall_ep_cmd(dep);
3955 WARN_ON_ONCE(ret);
3956 }
3957}
3958
3959static void dwc3_gadget_disconnect_interrupt(struct dwc3 *dwc)
3960{
3961 int reg;
3962
3963 dwc->suspended = false;
3964
3965 dwc3_gadget_set_link_state(dwc, DWC3_LINK_STATE_RX_DET);
3966
3967 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
3968 reg &= ~DWC3_DCTL_INITU1ENA;
3969 reg &= ~DWC3_DCTL_INITU2ENA;
3970 dwc3_gadget_dctl_write_safe(dwc, reg);
3971
3972 dwc->connected = false;
3973
3974 dwc3_disconnect_gadget(dwc);
3975
3976 dwc->gadget->speed = USB_SPEED_UNKNOWN;
3977 dwc->setup_packet_pending = false;
3978 dwc->gadget->wakeup_armed = false;
3979 dwc3_gadget_enable_linksts_evts(dwc, false);
3980 usb_gadget_set_state(dwc->gadget, USB_STATE_NOTATTACHED);
3981
3982 dwc3_ep0_reset_state(dwc);
3983
3984 /*
3985 * Request PM idle to address condition where usage count is
3986 * already decremented to zero, but waiting for the disconnect
3987 * interrupt to set dwc->connected to FALSE.
3988 */
3989 pm_request_idle(dwc->dev);
3990}
3991
3992static void dwc3_gadget_reset_interrupt(struct dwc3 *dwc)
3993{
3994 u32 reg;
3995
3996 dwc->suspended = false;
3997
3998 /*
3999 * Ideally, dwc3_reset_gadget() would trigger the function
4000 * drivers to stop any active transfers through ep disable.
4001 * However, for functions which defer ep disable, such as mass
4002 * storage, we will need to rely on the call to stop active
4003 * transfers here, and avoid allowing of request queuing.
4004 */
4005 dwc->connected = false;
4006
4007 /*
4008 * WORKAROUND: DWC3 revisions <1.88a have an issue which
4009 * would cause a missing Disconnect Event if there's a
4010 * pending Setup Packet in the FIFO.
4011 *
4012 * There's no suggested workaround on the official Bug
4013 * report, which states that "unless the driver/application
4014 * is doing any special handling of a disconnect event,
4015 * there is no functional issue".
4016 *
4017 * Unfortunately, it turns out that we _do_ some special
4018 * handling of a disconnect event, namely complete all
4019 * pending transfers, notify gadget driver of the
4020 * disconnection, and so on.
4021 *
4022 * Our suggested workaround is to follow the Disconnect
4023 * Event steps here, instead, based on a setup_packet_pending
4024 * flag. Such flag gets set whenever we have a SETUP_PENDING
4025 * status for EP0 TRBs and gets cleared on XferComplete for the
4026 * same endpoint.
4027 *
4028 * Refers to:
4029 *
4030 * STAR#9000466709: RTL: Device : Disconnect event not
4031 * generated if setup packet pending in FIFO
4032 */
4033 if (DWC3_VER_IS_PRIOR(DWC3, 188A)) {
4034 if (dwc->setup_packet_pending)
4035 dwc3_gadget_disconnect_interrupt(dwc);
4036 }
4037
4038 dwc3_reset_gadget(dwc);
4039
4040 /*
4041 * From SNPS databook section 8.1.2, the EP0 should be in setup
4042 * phase. So ensure that EP0 is in setup phase by issuing a stall
4043 * and restart if EP0 is not in setup phase.
4044 */
4045 dwc3_ep0_reset_state(dwc);
4046
4047 /*
4048 * In the Synopsis DesignWare Cores USB3 Databook Rev. 3.30a
4049 * Section 4.1.2 Table 4-2, it states that during a USB reset, the SW
4050 * needs to ensure that it sends "a DEPENDXFER command for any active
4051 * transfers."
4052 */
4053 dwc3_stop_active_transfers(dwc);
4054 dwc->connected = true;
4055
4056 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
4057 reg &= ~DWC3_DCTL_TSTCTRL_MASK;
4058 dwc3_gadget_dctl_write_safe(dwc, reg);
4059 dwc->test_mode = false;
4060 dwc->gadget->wakeup_armed = false;
4061 dwc3_gadget_enable_linksts_evts(dwc, false);
4062 dwc3_clear_stall_all_ep(dwc);
4063
4064 /* Reset device address to zero */
4065 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
4066 reg &= ~(DWC3_DCFG_DEVADDR_MASK);
4067 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
4068}
4069
4070static void dwc3_gadget_conndone_interrupt(struct dwc3 *dwc)
4071{
4072 struct dwc3_ep *dep;
4073 int ret;
4074 u32 reg;
4075 u8 lanes = 1;
4076 u8 speed;
4077
4078 if (!dwc->softconnect)
4079 return;
4080
4081 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
4082 speed = reg & DWC3_DSTS_CONNECTSPD;
4083 dwc->speed = speed;
4084
4085 if (DWC3_IP_IS(DWC32))
4086 lanes = DWC3_DSTS_CONNLANES(reg) + 1;
4087
4088 dwc->gadget->ssp_rate = USB_SSP_GEN_UNKNOWN;
4089
4090 /*
4091 * RAMClkSel is reset to 0 after USB reset, so it must be reprogrammed
4092 * each time on Connect Done.
4093 *
4094 * Currently we always use the reset value. If any platform
4095 * wants to set this to a different value, we need to add a
4096 * setting and update GCTL.RAMCLKSEL here.
4097 */
4098
4099 switch (speed) {
4100 case DWC3_DSTS_SUPERSPEED_PLUS:
4101 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
4102 dwc->gadget->ep0->maxpacket = 512;
4103 dwc->gadget->speed = USB_SPEED_SUPER_PLUS;
4104
4105 if (lanes > 1)
4106 dwc->gadget->ssp_rate = USB_SSP_GEN_2x2;
4107 else
4108 dwc->gadget->ssp_rate = USB_SSP_GEN_2x1;
4109 break;
4110 case DWC3_DSTS_SUPERSPEED:
4111 /*
4112 * WORKAROUND: DWC3 revisions <1.90a have an issue which
4113 * would cause a missing USB3 Reset event.
4114 *
4115 * In such situations, we should force a USB3 Reset
4116 * event by calling our dwc3_gadget_reset_interrupt()
4117 * routine.
4118 *
4119 * Refers to:
4120 *
4121 * STAR#9000483510: RTL: SS : USB3 reset event may
4122 * not be generated always when the link enters poll
4123 */
4124 if (DWC3_VER_IS_PRIOR(DWC3, 190A))
4125 dwc3_gadget_reset_interrupt(dwc);
4126
4127 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
4128 dwc->gadget->ep0->maxpacket = 512;
4129 dwc->gadget->speed = USB_SPEED_SUPER;
4130
4131 if (lanes > 1) {
4132 dwc->gadget->speed = USB_SPEED_SUPER_PLUS;
4133 dwc->gadget->ssp_rate = USB_SSP_GEN_1x2;
4134 }
4135 break;
4136 case DWC3_DSTS_HIGHSPEED:
4137 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
4138 dwc->gadget->ep0->maxpacket = 64;
4139 dwc->gadget->speed = USB_SPEED_HIGH;
4140 break;
4141 case DWC3_DSTS_FULLSPEED:
4142 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
4143 dwc->gadget->ep0->maxpacket = 64;
4144 dwc->gadget->speed = USB_SPEED_FULL;
4145 break;
4146 }
4147
4148 dwc->eps[1]->endpoint.maxpacket = dwc->gadget->ep0->maxpacket;
4149
4150 /* Enable USB2 LPM Capability */
4151
4152 if (!DWC3_VER_IS_WITHIN(DWC3, ANY, 194A) &&
4153 !dwc->usb2_gadget_lpm_disable &&
4154 (speed != DWC3_DSTS_SUPERSPEED) &&
4155 (speed != DWC3_DSTS_SUPERSPEED_PLUS)) {
4156 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
4157 reg |= DWC3_DCFG_LPM_CAP;
4158 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
4159
4160 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
4161 reg &= ~(DWC3_DCTL_HIRD_THRES_MASK | DWC3_DCTL_L1_HIBER_EN);
4162
4163 reg |= DWC3_DCTL_HIRD_THRES(dwc->hird_threshold |
4164 (dwc->is_utmi_l1_suspend << 4));
4165
4166 /*
4167 * When dwc3 revisions >= 2.40a, LPM Erratum is enabled and
4168 * DCFG.LPMCap is set, core responses with an ACK and the
4169 * BESL value in the LPM token is less than or equal to LPM
4170 * NYET threshold.
4171 */
4172 WARN_ONCE(DWC3_VER_IS_PRIOR(DWC3, 240A) && dwc->has_lpm_erratum,
4173 "LPM Erratum not available on dwc3 revisions < 2.40a\n");
4174
4175 if (dwc->has_lpm_erratum && !DWC3_VER_IS_PRIOR(DWC3, 240A))
4176 reg |= DWC3_DCTL_NYET_THRES(dwc->lpm_nyet_threshold);
4177
4178 dwc3_gadget_dctl_write_safe(dwc, reg);
4179 } else {
4180 if (dwc->usb2_gadget_lpm_disable) {
4181 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
4182 reg &= ~DWC3_DCFG_LPM_CAP;
4183 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
4184 }
4185
4186 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
4187 reg &= ~DWC3_DCTL_HIRD_THRES_MASK;
4188 dwc3_gadget_dctl_write_safe(dwc, reg);
4189 }
4190
4191 dep = dwc->eps[0];
4192 ret = __dwc3_gadget_ep_enable(dep, DWC3_DEPCFG_ACTION_MODIFY);
4193 if (ret) {
4194 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
4195 return;
4196 }
4197
4198 dep = dwc->eps[1];
4199 ret = __dwc3_gadget_ep_enable(dep, DWC3_DEPCFG_ACTION_MODIFY);
4200 if (ret) {
4201 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
4202 return;
4203 }
4204
4205 /*
4206 * Configure PHY via GUSB3PIPECTLn if required.
4207 *
4208 * Update GTXFIFOSIZn
4209 *
4210 * In both cases reset values should be sufficient.
4211 */
4212}
4213
4214static void dwc3_gadget_wakeup_interrupt(struct dwc3 *dwc, unsigned int evtinfo)
4215{
4216 dwc->suspended = false;
4217
4218 /*
4219 * TODO take core out of low power mode when that's
4220 * implemented.
4221 */
4222
4223 if (dwc->async_callbacks && dwc->gadget_driver->resume) {
4224 spin_unlock(&dwc->lock);
4225 dwc->gadget_driver->resume(dwc->gadget);
4226 spin_lock(&dwc->lock);
4227 }
4228
4229 dwc->link_state = evtinfo & DWC3_LINK_STATE_MASK;
4230}
4231
4232static void dwc3_gadget_linksts_change_interrupt(struct dwc3 *dwc,
4233 unsigned int evtinfo)
4234{
4235 enum dwc3_link_state next = evtinfo & DWC3_LINK_STATE_MASK;
4236 unsigned int pwropt;
4237
4238 /*
4239 * WORKAROUND: DWC3 < 2.50a have an issue when configured without
4240 * Hibernation mode enabled which would show up when device detects
4241 * host-initiated U3 exit.
4242 *
4243 * In that case, device will generate a Link State Change Interrupt
4244 * from U3 to RESUME which is only necessary if Hibernation is
4245 * configured in.
4246 *
4247 * There are no functional changes due to such spurious event and we
4248 * just need to ignore it.
4249 *
4250 * Refers to:
4251 *
4252 * STAR#9000570034 RTL: SS Resume event generated in non-Hibernation
4253 * operational mode
4254 */
4255 pwropt = DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1);
4256 if (DWC3_VER_IS_PRIOR(DWC3, 250A) &&
4257 (pwropt != DWC3_GHWPARAMS1_EN_PWROPT_HIB)) {
4258 if ((dwc->link_state == DWC3_LINK_STATE_U3) &&
4259 (next == DWC3_LINK_STATE_RESUME)) {
4260 return;
4261 }
4262 }
4263
4264 /*
4265 * WORKAROUND: DWC3 Revisions <1.83a have an issue which, depending
4266 * on the link partner, the USB session might do multiple entry/exit
4267 * of low power states before a transfer takes place.
4268 *
4269 * Due to this problem, we might experience lower throughput. The
4270 * suggested workaround is to disable DCTL[12:9] bits if we're
4271 * transitioning from U1/U2 to U0 and enable those bits again
4272 * after a transfer completes and there are no pending transfers
4273 * on any of the enabled endpoints.
4274 *
4275 * This is the first half of that workaround.
4276 *
4277 * Refers to:
4278 *
4279 * STAR#9000446952: RTL: Device SS : if U1/U2 ->U0 takes >128us
4280 * core send LGO_Ux entering U0
4281 */
4282 if (DWC3_VER_IS_PRIOR(DWC3, 183A)) {
4283 if (next == DWC3_LINK_STATE_U0) {
4284 u32 u1u2;
4285 u32 reg;
4286
4287 switch (dwc->link_state) {
4288 case DWC3_LINK_STATE_U1:
4289 case DWC3_LINK_STATE_U2:
4290 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
4291 u1u2 = reg & (DWC3_DCTL_INITU2ENA
4292 | DWC3_DCTL_ACCEPTU2ENA
4293 | DWC3_DCTL_INITU1ENA
4294 | DWC3_DCTL_ACCEPTU1ENA);
4295
4296 if (!dwc->u1u2)
4297 dwc->u1u2 = reg & u1u2;
4298
4299 reg &= ~u1u2;
4300
4301 dwc3_gadget_dctl_write_safe(dwc, reg);
4302 break;
4303 default:
4304 /* do nothing */
4305 break;
4306 }
4307 }
4308 }
4309
4310 switch (next) {
4311 case DWC3_LINK_STATE_U0:
4312 if (dwc->gadget->wakeup_armed) {
4313 dwc3_gadget_enable_linksts_evts(dwc, false);
4314 dwc3_resume_gadget(dwc);
4315 dwc->suspended = false;
4316 }
4317 break;
4318 case DWC3_LINK_STATE_U1:
4319 if (dwc->speed == USB_SPEED_SUPER)
4320 dwc3_suspend_gadget(dwc);
4321 break;
4322 case DWC3_LINK_STATE_U2:
4323 case DWC3_LINK_STATE_U3:
4324 dwc3_suspend_gadget(dwc);
4325 break;
4326 case DWC3_LINK_STATE_RESUME:
4327 dwc3_resume_gadget(dwc);
4328 break;
4329 default:
4330 /* do nothing */
4331 break;
4332 }
4333
4334 dwc->link_state = next;
4335}
4336
4337static void dwc3_gadget_suspend_interrupt(struct dwc3 *dwc,
4338 unsigned int evtinfo)
4339{
4340 enum dwc3_link_state next = evtinfo & DWC3_LINK_STATE_MASK;
4341
4342 if (!dwc->suspended && next == DWC3_LINK_STATE_U3) {
4343 dwc->suspended = true;
4344 dwc3_suspend_gadget(dwc);
4345 }
4346
4347 dwc->link_state = next;
4348}
4349
4350static void dwc3_gadget_interrupt(struct dwc3 *dwc,
4351 const struct dwc3_event_devt *event)
4352{
4353 switch (event->type) {
4354 case DWC3_DEVICE_EVENT_DISCONNECT:
4355 dwc3_gadget_disconnect_interrupt(dwc);
4356 break;
4357 case DWC3_DEVICE_EVENT_RESET:
4358 dwc3_gadget_reset_interrupt(dwc);
4359 break;
4360 case DWC3_DEVICE_EVENT_CONNECT_DONE:
4361 dwc3_gadget_conndone_interrupt(dwc);
4362 break;
4363 case DWC3_DEVICE_EVENT_WAKEUP:
4364 dwc3_gadget_wakeup_interrupt(dwc, event->event_info);
4365 break;
4366 case DWC3_DEVICE_EVENT_HIBER_REQ:
4367 dev_WARN_ONCE(dwc->dev, true, "unexpected hibernation event\n");
4368 break;
4369 case DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE:
4370 dwc3_gadget_linksts_change_interrupt(dwc, event->event_info);
4371 break;
4372 case DWC3_DEVICE_EVENT_SUSPEND:
4373 /* It changed to be suspend event for version 2.30a and above */
4374 if (!DWC3_VER_IS_PRIOR(DWC3, 230A))
4375 dwc3_gadget_suspend_interrupt(dwc, event->event_info);
4376 break;
4377 case DWC3_DEVICE_EVENT_SOF:
4378 case DWC3_DEVICE_EVENT_ERRATIC_ERROR:
4379 case DWC3_DEVICE_EVENT_CMD_CMPL:
4380 case DWC3_DEVICE_EVENT_OVERFLOW:
4381 break;
4382 default:
4383 dev_WARN(dwc->dev, "UNKNOWN IRQ %d\n", event->type);
4384 }
4385}
4386
4387static void dwc3_process_event_entry(struct dwc3 *dwc,
4388 const union dwc3_event *event)
4389{
4390 trace_dwc3_event(event->raw, dwc);
4391
4392 if (!event->type.is_devspec)
4393 dwc3_endpoint_interrupt(dwc, &event->depevt);
4394 else if (event->type.type == DWC3_EVENT_TYPE_DEV)
4395 dwc3_gadget_interrupt(dwc, &event->devt);
4396 else
4397 dev_err(dwc->dev, "UNKNOWN IRQ type %d\n", event->raw);
4398}
4399
4400static irqreturn_t dwc3_process_event_buf(struct dwc3_event_buffer *evt)
4401{
4402 struct dwc3 *dwc = evt->dwc;
4403 irqreturn_t ret = IRQ_NONE;
4404 int left;
4405
4406 left = evt->count;
4407
4408 if (!(evt->flags & DWC3_EVENT_PENDING))
4409 return IRQ_NONE;
4410
4411 while (left > 0) {
4412 union dwc3_event event;
4413
4414 event.raw = *(u32 *) (evt->cache + evt->lpos);
4415
4416 dwc3_process_event_entry(dwc, &event);
4417
4418 /*
4419 * FIXME we wrap around correctly to the next entry as
4420 * almost all entries are 4 bytes in size. There is one
4421 * entry which has 12 bytes which is a regular entry
4422 * followed by 8 bytes data. ATM I don't know how
4423 * things are organized if we get next to the a
4424 * boundary so I worry about that once we try to handle
4425 * that.
4426 */
4427 evt->lpos = (evt->lpos + 4) % evt->length;
4428 left -= 4;
4429 }
4430
4431 evt->count = 0;
4432 ret = IRQ_HANDLED;
4433
4434 /* Unmask interrupt */
4435 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0),
4436 DWC3_GEVNTSIZ_SIZE(evt->length));
4437
4438 if (dwc->imod_interval) {
4439 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), DWC3_GEVNTCOUNT_EHB);
4440 dwc3_writel(dwc->regs, DWC3_DEV_IMOD(0), dwc->imod_interval);
4441 }
4442
4443 /* Keep the clearing of DWC3_EVENT_PENDING at the end */
4444 evt->flags &= ~DWC3_EVENT_PENDING;
4445
4446 return ret;
4447}
4448
4449static irqreturn_t dwc3_thread_interrupt(int irq, void *_evt)
4450{
4451 struct dwc3_event_buffer *evt = _evt;
4452 struct dwc3 *dwc = evt->dwc;
4453 unsigned long flags;
4454 irqreturn_t ret = IRQ_NONE;
4455
4456 local_bh_disable();
4457 spin_lock_irqsave(&dwc->lock, flags);
4458 ret = dwc3_process_event_buf(evt);
4459 spin_unlock_irqrestore(&dwc->lock, flags);
4460 local_bh_enable();
4461
4462 return ret;
4463}
4464
4465static irqreturn_t dwc3_check_event_buf(struct dwc3_event_buffer *evt)
4466{
4467 struct dwc3 *dwc = evt->dwc;
4468 u32 amount;
4469 u32 count;
4470
4471 if (pm_runtime_suspended(dwc->dev)) {
4472 dwc->pending_events = true;
4473 /*
4474 * Trigger runtime resume. The get() function will be balanced
4475 * after processing the pending events in dwc3_process_pending
4476 * events().
4477 */
4478 pm_runtime_get(dwc->dev);
4479 disable_irq_nosync(dwc->irq_gadget);
4480 return IRQ_HANDLED;
4481 }
4482
4483 /*
4484 * With PCIe legacy interrupt, test shows that top-half irq handler can
4485 * be called again after HW interrupt deassertion. Check if bottom-half
4486 * irq event handler completes before caching new event to prevent
4487 * losing events.
4488 */
4489 if (evt->flags & DWC3_EVENT_PENDING)
4490 return IRQ_HANDLED;
4491
4492 count = dwc3_readl(dwc->regs, DWC3_GEVNTCOUNT(0));
4493 count &= DWC3_GEVNTCOUNT_MASK;
4494 if (!count)
4495 return IRQ_NONE;
4496
4497 evt->count = count;
4498 evt->flags |= DWC3_EVENT_PENDING;
4499
4500 /* Mask interrupt */
4501 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0),
4502 DWC3_GEVNTSIZ_INTMASK | DWC3_GEVNTSIZ_SIZE(evt->length));
4503
4504 amount = min(count, evt->length - evt->lpos);
4505 memcpy(evt->cache + evt->lpos, evt->buf + evt->lpos, amount);
4506
4507 if (amount < count)
4508 memcpy(evt->cache, evt->buf, count - amount);
4509
4510 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), count);
4511
4512 return IRQ_WAKE_THREAD;
4513}
4514
4515static irqreturn_t dwc3_interrupt(int irq, void *_evt)
4516{
4517 struct dwc3_event_buffer *evt = _evt;
4518
4519 return dwc3_check_event_buf(evt);
4520}
4521
4522static int dwc3_gadget_get_irq(struct dwc3 *dwc)
4523{
4524 struct platform_device *dwc3_pdev = to_platform_device(dwc->dev);
4525 int irq;
4526
4527 irq = platform_get_irq_byname_optional(dwc3_pdev, "peripheral");
4528 if (irq > 0)
4529 goto out;
4530
4531 if (irq == -EPROBE_DEFER)
4532 goto out;
4533
4534 irq = platform_get_irq_byname_optional(dwc3_pdev, "dwc_usb3");
4535 if (irq > 0)
4536 goto out;
4537
4538 if (irq == -EPROBE_DEFER)
4539 goto out;
4540
4541 irq = platform_get_irq(dwc3_pdev, 0);
4542
4543out:
4544 return irq;
4545}
4546
4547static void dwc_gadget_release(struct device *dev)
4548{
4549 struct usb_gadget *gadget = container_of(dev, struct usb_gadget, dev);
4550
4551 kfree(gadget);
4552}
4553
4554/**
4555 * dwc3_gadget_init - initializes gadget related registers
4556 * @dwc: pointer to our controller context structure
4557 *
4558 * Returns 0 on success otherwise negative errno.
4559 */
4560int dwc3_gadget_init(struct dwc3 *dwc)
4561{
4562 int ret;
4563 int irq;
4564 struct device *dev;
4565
4566 irq = dwc3_gadget_get_irq(dwc);
4567 if (irq < 0) {
4568 ret = irq;
4569 goto err0;
4570 }
4571
4572 dwc->irq_gadget = irq;
4573
4574 dwc->ep0_trb = dma_alloc_coherent(dwc->sysdev,
4575 sizeof(*dwc->ep0_trb) * 2,
4576 &dwc->ep0_trb_addr, GFP_KERNEL);
4577 if (!dwc->ep0_trb) {
4578 dev_err(dwc->dev, "failed to allocate ep0 trb\n");
4579 ret = -ENOMEM;
4580 goto err0;
4581 }
4582
4583 dwc->setup_buf = kzalloc(DWC3_EP0_SETUP_SIZE, GFP_KERNEL);
4584 if (!dwc->setup_buf) {
4585 ret = -ENOMEM;
4586 goto err1;
4587 }
4588
4589 dwc->bounce = dma_alloc_coherent(dwc->sysdev, DWC3_BOUNCE_SIZE,
4590 &dwc->bounce_addr, GFP_KERNEL);
4591 if (!dwc->bounce) {
4592 ret = -ENOMEM;
4593 goto err2;
4594 }
4595
4596 init_completion(&dwc->ep0_in_setup);
4597 dwc->gadget = kzalloc(sizeof(struct usb_gadget), GFP_KERNEL);
4598 if (!dwc->gadget) {
4599 ret = -ENOMEM;
4600 goto err3;
4601 }
4602
4603
4604 usb_initialize_gadget(dwc->dev, dwc->gadget, dwc_gadget_release);
4605 dev = &dwc->gadget->dev;
4606 dev->platform_data = dwc;
4607 dwc->gadget->ops = &dwc3_gadget_ops;
4608 dwc->gadget->speed = USB_SPEED_UNKNOWN;
4609 dwc->gadget->ssp_rate = USB_SSP_GEN_UNKNOWN;
4610 dwc->gadget->sg_supported = true;
4611 dwc->gadget->name = "dwc3-gadget";
4612 dwc->gadget->lpm_capable = !dwc->usb2_gadget_lpm_disable;
4613 dwc->gadget->wakeup_capable = true;
4614
4615 /*
4616 * FIXME We might be setting max_speed to <SUPER, however versions
4617 * <2.20a of dwc3 have an issue with metastability (documented
4618 * elsewhere in this driver) which tells us we can't set max speed to
4619 * anything lower than SUPER.
4620 *
4621 * Because gadget.max_speed is only used by composite.c and function
4622 * drivers (i.e. it won't go into dwc3's registers) we are allowing this
4623 * to happen so we avoid sending SuperSpeed Capability descriptor
4624 * together with our BOS descriptor as that could confuse host into
4625 * thinking we can handle super speed.
4626 *
4627 * Note that, in fact, we won't even support GetBOS requests when speed
4628 * is less than super speed because we don't have means, yet, to tell
4629 * composite.c that we are USB 2.0 + LPM ECN.
4630 */
4631 if (DWC3_VER_IS_PRIOR(DWC3, 220A) &&
4632 !dwc->dis_metastability_quirk)
4633 dev_info(dwc->dev, "changing max_speed on rev %08x\n",
4634 dwc->revision);
4635
4636 dwc->gadget->max_speed = dwc->maximum_speed;
4637 dwc->gadget->max_ssp_rate = dwc->max_ssp_rate;
4638
4639 /*
4640 * REVISIT: Here we should clear all pending IRQs to be
4641 * sure we're starting from a well known location.
4642 */
4643
4644 ret = dwc3_gadget_init_endpoints(dwc, dwc->num_eps);
4645 if (ret)
4646 goto err4;
4647
4648 ret = usb_add_gadget(dwc->gadget);
4649 if (ret) {
4650 dev_err(dwc->dev, "failed to add gadget\n");
4651 goto err5;
4652 }
4653
4654 if (DWC3_IP_IS(DWC32) && dwc->maximum_speed == USB_SPEED_SUPER_PLUS)
4655 dwc3_gadget_set_ssp_rate(dwc->gadget, dwc->max_ssp_rate);
4656 else
4657 dwc3_gadget_set_speed(dwc->gadget, dwc->maximum_speed);
4658
4659 /* No system wakeup if no gadget driver bound */
4660 if (dwc->sys_wakeup)
4661 device_wakeup_disable(dwc->sysdev);
4662
4663 return 0;
4664
4665err5:
4666 dwc3_gadget_free_endpoints(dwc);
4667err4:
4668 usb_put_gadget(dwc->gadget);
4669 dwc->gadget = NULL;
4670err3:
4671 dma_free_coherent(dwc->sysdev, DWC3_BOUNCE_SIZE, dwc->bounce,
4672 dwc->bounce_addr);
4673
4674err2:
4675 kfree(dwc->setup_buf);
4676
4677err1:
4678 dma_free_coherent(dwc->sysdev, sizeof(*dwc->ep0_trb) * 2,
4679 dwc->ep0_trb, dwc->ep0_trb_addr);
4680
4681err0:
4682 return ret;
4683}
4684
4685/* -------------------------------------------------------------------------- */
4686
4687void dwc3_gadget_exit(struct dwc3 *dwc)
4688{
4689 if (!dwc->gadget)
4690 return;
4691
4692 dwc3_enable_susphy(dwc, false);
4693 usb_del_gadget(dwc->gadget);
4694 dwc3_gadget_free_endpoints(dwc);
4695 usb_put_gadget(dwc->gadget);
4696 dma_free_coherent(dwc->sysdev, DWC3_BOUNCE_SIZE, dwc->bounce,
4697 dwc->bounce_addr);
4698 kfree(dwc->setup_buf);
4699 dma_free_coherent(dwc->sysdev, sizeof(*dwc->ep0_trb) * 2,
4700 dwc->ep0_trb, dwc->ep0_trb_addr);
4701}
4702
4703int dwc3_gadget_suspend(struct dwc3 *dwc)
4704{
4705 unsigned long flags;
4706 int ret;
4707
4708 ret = dwc3_gadget_soft_disconnect(dwc);
4709 if (ret)
4710 goto err;
4711
4712 spin_lock_irqsave(&dwc->lock, flags);
4713 if (dwc->gadget_driver)
4714 dwc3_disconnect_gadget(dwc);
4715 spin_unlock_irqrestore(&dwc->lock, flags);
4716
4717 return 0;
4718
4719err:
4720 /*
4721 * Attempt to reset the controller's state. Likely no
4722 * communication can be established until the host
4723 * performs a port reset.
4724 */
4725 if (dwc->softconnect)
4726 dwc3_gadget_soft_connect(dwc);
4727
4728 return ret;
4729}
4730
4731int dwc3_gadget_resume(struct dwc3 *dwc)
4732{
4733 if (!dwc->gadget_driver || !dwc->softconnect)
4734 return 0;
4735
4736 return dwc3_gadget_soft_connect(dwc);
4737}
4738
4739void dwc3_gadget_process_pending_events(struct dwc3 *dwc)
4740{
4741 if (dwc->pending_events) {
4742 dwc3_interrupt(dwc->irq_gadget, dwc->ev_buf);
4743 dwc3_thread_interrupt(dwc->irq_gadget, dwc->ev_buf);
4744 pm_runtime_put(dwc->dev);
4745 dwc->pending_events = false;
4746 enable_irq(dwc->irq_gadget);
4747 }
4748}