1// SPDX-License-Identifier: GPL-2.0
   2/* $Id: sungem.c,v 1.44.2.22 2002/03/13 01:18:12 davem Exp $
   3 * sungem.c: Sun GEM ethernet driver.
   4 *
   5 * Copyright (C) 2000, 2001, 2002, 2003 David S. Miller (davem@redhat.com)
   6 *
   7 * Support for Apple GMAC and assorted PHYs, WOL, Power Management
   8 * (C) 2001,2002,2003 Benjamin Herrenscmidt (benh@kernel.crashing.org)
   9 * (C) 2004,2005 Benjamin Herrenscmidt, IBM Corp.
  10 *
  11 * NAPI and NETPOLL support
  12 * (C) 2004 by Eric Lemoine (eric.lemoine@gmail.com)
  13 *
  14 */
  15
  16#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  17
  18#include <linux/module.h>
  19#include <linux/kernel.h>
  20#include <linux/types.h>
  21#include <linux/fcntl.h>
  22#include <linux/interrupt.h>
  23#include <linux/ioport.h>
  24#include <linux/in.h>
  25#include <linux/sched.h>
  26#include <linux/string.h>
  27#include <linux/delay.h>
  28#include <linux/errno.h>
  29#include <linux/pci.h>
  30#include <linux/dma-mapping.h>
  31#include <linux/netdevice.h>
  32#include <linux/etherdevice.h>
  33#include <linux/skbuff.h>
  34#include <linux/mii.h>
  35#include <linux/ethtool.h>
  36#include <linux/crc32.h>
  37#include <linux/random.h>
  38#include <linux/workqueue.h>
  39#include <linux/if_vlan.h>
  40#include <linux/bitops.h>
  41#include <linux/mm.h>
  42#include <linux/gfp.h>
  43#include <linux/of.h>
  44
  45#include <asm/io.h>
  46#include <asm/byteorder.h>
  47#include <linux/uaccess.h>
  48#include <asm/irq.h>
  49
  50#ifdef CONFIG_SPARC
  51#include <asm/idprom.h>
  52#include <asm/prom.h>
  53#endif
  54
  55#ifdef CONFIG_PPC_PMAC
 
 
  56#include <asm/machdep.h>
  57#include <asm/pmac_feature.h>
  58#endif
  59
  60#include <linux/sungem_phy.h>
  61#include "sungem.h"
  62
  63#define STRIP_FCS
 
  64
  65#define DEFAULT_MSG	(NETIF_MSG_DRV		| \
  66			 NETIF_MSG_PROBE	| \
  67			 NETIF_MSG_LINK)
  68
  69#define ADVERTISE_MASK	(SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full | \
  70			 SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full | \
  71			 SUPPORTED_1000baseT_Half | SUPPORTED_1000baseT_Full | \
  72			 SUPPORTED_Pause | SUPPORTED_Autoneg)
  73
  74#define DRV_NAME	"sungem"
  75#define DRV_VERSION	"1.0"
  76#define DRV_AUTHOR	"David S. Miller <davem@redhat.com>"
  77
  78static char version[] =
  79        DRV_NAME ".c:v" DRV_VERSION " " DRV_AUTHOR "\n";
  80
  81MODULE_AUTHOR(DRV_AUTHOR);
  82MODULE_DESCRIPTION("Sun GEM Gbit ethernet driver");
  83MODULE_LICENSE("GPL");
  84
  85#define GEM_MODULE_NAME	"gem"
  86
  87static const struct pci_device_id gem_pci_tbl[] = {
  88	{ PCI_VENDOR_ID_SUN, PCI_DEVICE_ID_SUN_GEM,
  89	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
  90
  91	/* These models only differ from the original GEM in
  92	 * that their tx/rx fifos are of a different size and
  93	 * they only support 10/100 speeds. -DaveM
  94	 *
  95	 * Apple's GMAC does support gigabit on machines with
  96	 * the BCM54xx PHYs. -BenH
  97	 */
  98	{ PCI_VENDOR_ID_SUN, PCI_DEVICE_ID_SUN_RIO_GEM,
  99	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 100	{ PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_UNI_N_GMAC,
 101	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 102	{ PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_UNI_N_GMACP,
 103	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 104	{ PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_UNI_N_GMAC2,
 105	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 106	{ PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_K2_GMAC,
 107	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 108	{ PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_SH_SUNGEM,
 109	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 110	{ PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_IPID2_GMAC,
 111	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 112	{0, }
 113};
 114
 115MODULE_DEVICE_TABLE(pci, gem_pci_tbl);
 116
 117static u16 __sungem_phy_read(struct gem *gp, int phy_addr, int reg)
 118{
 119	u32 cmd;
 120	int limit = 10000;
 121
 122	cmd  = (1 << 30);
 123	cmd |= (2 << 28);
 124	cmd |= (phy_addr << 23) & MIF_FRAME_PHYAD;
 125	cmd |= (reg << 18) & MIF_FRAME_REGAD;
 126	cmd |= (MIF_FRAME_TAMSB);
 127	writel(cmd, gp->regs + MIF_FRAME);
 128
 129	while (--limit) {
 130		cmd = readl(gp->regs + MIF_FRAME);
 131		if (cmd & MIF_FRAME_TALSB)
 132			break;
 133
 134		udelay(10);
 135	}
 136
 137	if (!limit)
 138		cmd = 0xffff;
 139
 140	return cmd & MIF_FRAME_DATA;
 141}
 142
 143static inline int _sungem_phy_read(struct net_device *dev, int mii_id, int reg)
 144{
 145	struct gem *gp = netdev_priv(dev);
 146	return __sungem_phy_read(gp, mii_id, reg);
 147}
 148
 149static inline u16 sungem_phy_read(struct gem *gp, int reg)
 150{
 151	return __sungem_phy_read(gp, gp->mii_phy_addr, reg);
 152}
 153
 154static void __sungem_phy_write(struct gem *gp, int phy_addr, int reg, u16 val)
 155{
 156	u32 cmd;
 157	int limit = 10000;
 158
 159	cmd  = (1 << 30);
 160	cmd |= (1 << 28);
 161	cmd |= (phy_addr << 23) & MIF_FRAME_PHYAD;
 162	cmd |= (reg << 18) & MIF_FRAME_REGAD;
 163	cmd |= (MIF_FRAME_TAMSB);
 164	cmd |= (val & MIF_FRAME_DATA);
 165	writel(cmd, gp->regs + MIF_FRAME);
 166
 167	while (limit--) {
 168		cmd = readl(gp->regs + MIF_FRAME);
 169		if (cmd & MIF_FRAME_TALSB)
 170			break;
 171
 172		udelay(10);
 173	}
 174}
 175
 176static inline void _sungem_phy_write(struct net_device *dev, int mii_id, int reg, int val)
 177{
 178	struct gem *gp = netdev_priv(dev);
 179	__sungem_phy_write(gp, mii_id, reg, val & 0xffff);
 180}
 181
 182static inline void sungem_phy_write(struct gem *gp, int reg, u16 val)
 183{
 184	__sungem_phy_write(gp, gp->mii_phy_addr, reg, val);
 185}
 186
 187static inline void gem_enable_ints(struct gem *gp)
 188{
 189	/* Enable all interrupts but TXDONE */
 190	writel(GREG_STAT_TXDONE, gp->regs + GREG_IMASK);
 191}
 192
 193static inline void gem_disable_ints(struct gem *gp)
 194{
 195	/* Disable all interrupts, including TXDONE */
 196	writel(GREG_STAT_NAPI | GREG_STAT_TXDONE, gp->regs + GREG_IMASK);
 197	(void)readl(gp->regs + GREG_IMASK); /* write posting */
 198}
 199
 200static void gem_get_cell(struct gem *gp)
 201{
 202	BUG_ON(gp->cell_enabled < 0);
 203	gp->cell_enabled++;
 204#ifdef CONFIG_PPC_PMAC
 205	if (gp->cell_enabled == 1) {
 206		mb();
 207		pmac_call_feature(PMAC_FTR_GMAC_ENABLE, gp->of_node, 0, 1);
 208		udelay(10);
 209	}
 210#endif /* CONFIG_PPC_PMAC */
 211}
 212
 213/* Turn off the chip's clock */
 214static void gem_put_cell(struct gem *gp)
 215{
 216	BUG_ON(gp->cell_enabled <= 0);
 217	gp->cell_enabled--;
 218#ifdef CONFIG_PPC_PMAC
 219	if (gp->cell_enabled == 0) {
 220		mb();
 221		pmac_call_feature(PMAC_FTR_GMAC_ENABLE, gp->of_node, 0, 0);
 222		udelay(10);
 223	}
 224#endif /* CONFIG_PPC_PMAC */
 225}
 226
 227static inline void gem_netif_stop(struct gem *gp)
 228{
 229	netif_trans_update(gp->dev);	/* prevent tx timeout */
 230	napi_disable(&gp->napi);
 231	netif_tx_disable(gp->dev);
 232}
 233
 234static inline void gem_netif_start(struct gem *gp)
 235{
 236	/* NOTE: unconditional netif_wake_queue is only
 237	 * appropriate so long as all callers are assured to
 238	 * have free tx slots.
 239	 */
 240	netif_wake_queue(gp->dev);
 241	napi_enable(&gp->napi);
 242}
 243
 244static void gem_schedule_reset(struct gem *gp)
 245{
 246	gp->reset_task_pending = 1;
 247	schedule_work(&gp->reset_task);
 248}
 249
 250static void gem_handle_mif_event(struct gem *gp, u32 reg_val, u32 changed_bits)
 251{
 252	if (netif_msg_intr(gp))
 253		printk(KERN_DEBUG "%s: mif interrupt\n", gp->dev->name);
 254}
 255
 256static int gem_pcs_interrupt(struct net_device *dev, struct gem *gp, u32 gem_status)
 257{
 258	u32 pcs_istat = readl(gp->regs + PCS_ISTAT);
 259	u32 pcs_miistat;
 260
 261	if (netif_msg_intr(gp))
 262		printk(KERN_DEBUG "%s: pcs interrupt, pcs_istat: 0x%x\n",
 263			gp->dev->name, pcs_istat);
 264
 265	if (!(pcs_istat & PCS_ISTAT_LSC)) {
 266		netdev_err(dev, "PCS irq but no link status change???\n");
 267		return 0;
 268	}
 269
 270	/* The link status bit latches on zero, so you must
 271	 * read it twice in such a case to see a transition
 272	 * to the link being up.
 273	 */
 274	pcs_miistat = readl(gp->regs + PCS_MIISTAT);
 275	if (!(pcs_miistat & PCS_MIISTAT_LS))
 276		pcs_miistat |=
 277			(readl(gp->regs + PCS_MIISTAT) &
 278			 PCS_MIISTAT_LS);
 279
 280	if (pcs_miistat & PCS_MIISTAT_ANC) {
 281		/* The remote-fault indication is only valid
 282		 * when autoneg has completed.
 283		 */
 284		if (pcs_miistat & PCS_MIISTAT_RF)
 285			netdev_info(dev, "PCS AutoNEG complete, RemoteFault\n");
 286		else
 287			netdev_info(dev, "PCS AutoNEG complete\n");
 288	}
 289
 290	if (pcs_miistat & PCS_MIISTAT_LS) {
 291		netdev_info(dev, "PCS link is now up\n");
 292		netif_carrier_on(gp->dev);
 293	} else {
 294		netdev_info(dev, "PCS link is now down\n");
 295		netif_carrier_off(gp->dev);
 296		/* If this happens and the link timer is not running,
 297		 * reset so we re-negotiate.
 298		 */
 299		if (!timer_pending(&gp->link_timer))
 300			return 1;
 301	}
 302
 303	return 0;
 304}
 305
 306static int gem_txmac_interrupt(struct net_device *dev, struct gem *gp, u32 gem_status)
 307{
 308	u32 txmac_stat = readl(gp->regs + MAC_TXSTAT);
 309
 310	if (netif_msg_intr(gp))
 311		printk(KERN_DEBUG "%s: txmac interrupt, txmac_stat: 0x%x\n",
 312			gp->dev->name, txmac_stat);
 313
 314	/* Defer timer expiration is quite normal,
 315	 * don't even log the event.
 316	 */
 317	if ((txmac_stat & MAC_TXSTAT_DTE) &&
 318	    !(txmac_stat & ~MAC_TXSTAT_DTE))
 319		return 0;
 320
 321	if (txmac_stat & MAC_TXSTAT_URUN) {
 322		netdev_err(dev, "TX MAC xmit underrun\n");
 323		dev->stats.tx_fifo_errors++;
 324	}
 325
 326	if (txmac_stat & MAC_TXSTAT_MPE) {
 327		netdev_err(dev, "TX MAC max packet size error\n");
 328		dev->stats.tx_errors++;
 329	}
 330
 331	/* The rest are all cases of one of the 16-bit TX
 332	 * counters expiring.
 333	 */
 334	if (txmac_stat & MAC_TXSTAT_NCE)
 335		dev->stats.collisions += 0x10000;
 336
 337	if (txmac_stat & MAC_TXSTAT_ECE) {
 338		dev->stats.tx_aborted_errors += 0x10000;
 339		dev->stats.collisions += 0x10000;
 340	}
 341
 342	if (txmac_stat & MAC_TXSTAT_LCE) {
 343		dev->stats.tx_aborted_errors += 0x10000;
 344		dev->stats.collisions += 0x10000;
 345	}
 346
 347	/* We do not keep track of MAC_TXSTAT_FCE and
 348	 * MAC_TXSTAT_PCE events.
 349	 */
 350	return 0;
 351}
 352
 353/* When we get a RX fifo overflow, the RX unit in GEM is probably hung
 354 * so we do the following.
 355 *
 356 * If any part of the reset goes wrong, we return 1 and that causes the
 357 * whole chip to be reset.
 358 */
 359static int gem_rxmac_reset(struct gem *gp)
 360{
 361	struct net_device *dev = gp->dev;
 362	int limit, i;
 363	u64 desc_dma;
 364	u32 val;
 365
 366	/* First, reset & disable MAC RX. */
 367	writel(MAC_RXRST_CMD, gp->regs + MAC_RXRST);
 368	for (limit = 0; limit < 5000; limit++) {
 369		if (!(readl(gp->regs + MAC_RXRST) & MAC_RXRST_CMD))
 370			break;
 371		udelay(10);
 372	}
 373	if (limit == 5000) {
 374		netdev_err(dev, "RX MAC will not reset, resetting whole chip\n");
 375		return 1;
 376	}
 377
 378	writel(gp->mac_rx_cfg & ~MAC_RXCFG_ENAB,
 379	       gp->regs + MAC_RXCFG);
 380	for (limit = 0; limit < 5000; limit++) {
 381		if (!(readl(gp->regs + MAC_RXCFG) & MAC_RXCFG_ENAB))
 382			break;
 383		udelay(10);
 384	}
 385	if (limit == 5000) {
 386		netdev_err(dev, "RX MAC will not disable, resetting whole chip\n");
 387		return 1;
 388	}
 389
 390	/* Second, disable RX DMA. */
 391	writel(0, gp->regs + RXDMA_CFG);
 392	for (limit = 0; limit < 5000; limit++) {
 393		if (!(readl(gp->regs + RXDMA_CFG) & RXDMA_CFG_ENABLE))
 394			break;
 395		udelay(10);
 396	}
 397	if (limit == 5000) {
 398		netdev_err(dev, "RX DMA will not disable, resetting whole chip\n");
 399		return 1;
 400	}
 401
 402	mdelay(5);
 403
 404	/* Execute RX reset command. */
 405	writel(gp->swrst_base | GREG_SWRST_RXRST,
 406	       gp->regs + GREG_SWRST);
 407	for (limit = 0; limit < 5000; limit++) {
 408		if (!(readl(gp->regs + GREG_SWRST) & GREG_SWRST_RXRST))
 409			break;
 410		udelay(10);
 411	}
 412	if (limit == 5000) {
 413		netdev_err(dev, "RX reset command will not execute, resetting whole chip\n");
 414		return 1;
 415	}
 416
 417	/* Refresh the RX ring. */
 418	for (i = 0; i < RX_RING_SIZE; i++) {
 419		struct gem_rxd *rxd = &gp->init_block->rxd[i];
 420
 421		if (gp->rx_skbs[i] == NULL) {
 422			netdev_err(dev, "Parts of RX ring empty, resetting whole chip\n");
 423			return 1;
 424		}
 425
 426		rxd->status_word = cpu_to_le64(RXDCTRL_FRESH(gp));
 427	}
 428	gp->rx_new = gp->rx_old = 0;
 429
 430	/* Now we must reprogram the rest of RX unit. */
 431	desc_dma = (u64) gp->gblock_dvma;
 432	desc_dma += (INIT_BLOCK_TX_RING_SIZE * sizeof(struct gem_txd));
 433	writel(desc_dma >> 32, gp->regs + RXDMA_DBHI);
 434	writel(desc_dma & 0xffffffff, gp->regs + RXDMA_DBLOW);
 435	writel(RX_RING_SIZE - 4, gp->regs + RXDMA_KICK);
 436	val = (RXDMA_CFG_BASE | (RX_OFFSET << 10) |
 437	       (ETH_HLEN << 13) | RXDMA_CFG_FTHRESH_128);
 438	writel(val, gp->regs + RXDMA_CFG);
 439	if (readl(gp->regs + GREG_BIFCFG) & GREG_BIFCFG_M66EN)
 440		writel(((5 & RXDMA_BLANK_IPKTS) |
 441			((8 << 12) & RXDMA_BLANK_ITIME)),
 442		       gp->regs + RXDMA_BLANK);
 443	else
 444		writel(((5 & RXDMA_BLANK_IPKTS) |
 445			((4 << 12) & RXDMA_BLANK_ITIME)),
 446		       gp->regs + RXDMA_BLANK);
 447	val  = (((gp->rx_pause_off / 64) << 0) & RXDMA_PTHRESH_OFF);
 448	val |= (((gp->rx_pause_on / 64) << 12) & RXDMA_PTHRESH_ON);
 449	writel(val, gp->regs + RXDMA_PTHRESH);
 450	val = readl(gp->regs + RXDMA_CFG);
 451	writel(val | RXDMA_CFG_ENABLE, gp->regs + RXDMA_CFG);
 452	writel(MAC_RXSTAT_RCV, gp->regs + MAC_RXMASK);
 453	val = readl(gp->regs + MAC_RXCFG);
 454	writel(val | MAC_RXCFG_ENAB, gp->regs + MAC_RXCFG);
 455
 456	return 0;
 457}
 458
 459static int gem_rxmac_interrupt(struct net_device *dev, struct gem *gp, u32 gem_status)
 460{
 461	u32 rxmac_stat = readl(gp->regs + MAC_RXSTAT);
 462	int ret = 0;
 463
 464	if (netif_msg_intr(gp))
 465		printk(KERN_DEBUG "%s: rxmac interrupt, rxmac_stat: 0x%x\n",
 466			gp->dev->name, rxmac_stat);
 467
 468	if (rxmac_stat & MAC_RXSTAT_OFLW) {
 469		u32 smac = readl(gp->regs + MAC_SMACHINE);
 470
 471		netdev_err(dev, "RX MAC fifo overflow smac[%08x]\n", smac);
 472		dev->stats.rx_over_errors++;
 473		dev->stats.rx_fifo_errors++;
 474
 475		ret = gem_rxmac_reset(gp);
 476	}
 477
 478	if (rxmac_stat & MAC_RXSTAT_ACE)
 479		dev->stats.rx_frame_errors += 0x10000;
 480
 481	if (rxmac_stat & MAC_RXSTAT_CCE)
 482		dev->stats.rx_crc_errors += 0x10000;
 483
 484	if (rxmac_stat & MAC_RXSTAT_LCE)
 485		dev->stats.rx_length_errors += 0x10000;
 486
 487	/* We do not track MAC_RXSTAT_FCE and MAC_RXSTAT_VCE
 488	 * events.
 489	 */
 490	return ret;
 491}
 492
 493static int gem_mac_interrupt(struct net_device *dev, struct gem *gp, u32 gem_status)
 494{
 495	u32 mac_cstat = readl(gp->regs + MAC_CSTAT);
 496
 497	if (netif_msg_intr(gp))
 498		printk(KERN_DEBUG "%s: mac interrupt, mac_cstat: 0x%x\n",
 499			gp->dev->name, mac_cstat);
 500
 501	/* This interrupt is just for pause frame and pause
 502	 * tracking.  It is useful for diagnostics and debug
 503	 * but probably by default we will mask these events.
 504	 */
 505	if (mac_cstat & MAC_CSTAT_PS)
 506		gp->pause_entered++;
 507
 508	if (mac_cstat & MAC_CSTAT_PRCV)
 509		gp->pause_last_time_recvd = (mac_cstat >> 16);
 510
 511	return 0;
 512}
 513
 514static int gem_mif_interrupt(struct net_device *dev, struct gem *gp, u32 gem_status)
 515{
 516	u32 mif_status = readl(gp->regs + MIF_STATUS);
 517	u32 reg_val, changed_bits;
 518
 519	reg_val = (mif_status & MIF_STATUS_DATA) >> 16;
 520	changed_bits = (mif_status & MIF_STATUS_STAT);
 521
 522	gem_handle_mif_event(gp, reg_val, changed_bits);
 523
 524	return 0;
 525}
 526
 527static int gem_pci_interrupt(struct net_device *dev, struct gem *gp, u32 gem_status)
 528{
 529	u32 pci_estat = readl(gp->regs + GREG_PCIESTAT);
 530
 531	if (gp->pdev->vendor == PCI_VENDOR_ID_SUN &&
 532	    gp->pdev->device == PCI_DEVICE_ID_SUN_GEM) {
 533		netdev_err(dev, "PCI error [%04x]", pci_estat);
 534
 535		if (pci_estat & GREG_PCIESTAT_BADACK)
 536			pr_cont(" <No ACK64# during ABS64 cycle>");
 537		if (pci_estat & GREG_PCIESTAT_DTRTO)
 538			pr_cont(" <Delayed transaction timeout>");
 539		if (pci_estat & GREG_PCIESTAT_OTHER)
 540			pr_cont(" <other>");
 541		pr_cont("\n");
 542	} else {
 543		pci_estat |= GREG_PCIESTAT_OTHER;
 544		netdev_err(dev, "PCI error\n");
 545	}
 546
 547	if (pci_estat & GREG_PCIESTAT_OTHER) {
 548		int pci_errs;
 549
 550		/* Interrogate PCI config space for the
 551		 * true cause.
 552		 */
 553		pci_errs = pci_status_get_and_clear_errors(gp->pdev);
 554		netdev_err(dev, "PCI status errors[%04x]\n", pci_errs);
 555		if (pci_errs & PCI_STATUS_PARITY)
 
 
 556			netdev_err(dev, "PCI parity error detected\n");
 557		if (pci_errs & PCI_STATUS_SIG_TARGET_ABORT)
 558			netdev_err(dev, "PCI target abort\n");
 559		if (pci_errs & PCI_STATUS_REC_TARGET_ABORT)
 560			netdev_err(dev, "PCI master acks target abort\n");
 561		if (pci_errs & PCI_STATUS_REC_MASTER_ABORT)
 562			netdev_err(dev, "PCI master abort\n");
 563		if (pci_errs & PCI_STATUS_SIG_SYSTEM_ERROR)
 564			netdev_err(dev, "PCI system error SERR#\n");
 565		if (pci_errs & PCI_STATUS_DETECTED_PARITY)
 566			netdev_err(dev, "PCI parity error\n");
 
 
 
 
 
 
 
 
 
 
 567	}
 568
 569	/* For all PCI errors, we should reset the chip. */
 570	return 1;
 571}
 572
 573/* All non-normal interrupt conditions get serviced here.
 574 * Returns non-zero if we should just exit the interrupt
 575 * handler right now (ie. if we reset the card which invalidates
 576 * all of the other original irq status bits).
 577 */
 578static int gem_abnormal_irq(struct net_device *dev, struct gem *gp, u32 gem_status)
 579{
 580	if (gem_status & GREG_STAT_RXNOBUF) {
 581		/* Frame arrived, no free RX buffers available. */
 582		if (netif_msg_rx_err(gp))
 583			printk(KERN_DEBUG "%s: no buffer for rx frame\n",
 584				gp->dev->name);
 585		dev->stats.rx_dropped++;
 586	}
 587
 588	if (gem_status & GREG_STAT_RXTAGERR) {
 589		/* corrupt RX tag framing */
 590		if (netif_msg_rx_err(gp))
 591			printk(KERN_DEBUG "%s: corrupt rx tag framing\n",
 592				gp->dev->name);
 593		dev->stats.rx_errors++;
 594
 595		return 1;
 596	}
 597
 598	if (gem_status & GREG_STAT_PCS) {
 599		if (gem_pcs_interrupt(dev, gp, gem_status))
 600			return 1;
 601	}
 602
 603	if (gem_status & GREG_STAT_TXMAC) {
 604		if (gem_txmac_interrupt(dev, gp, gem_status))
 605			return 1;
 606	}
 607
 608	if (gem_status & GREG_STAT_RXMAC) {
 609		if (gem_rxmac_interrupt(dev, gp, gem_status))
 610			return 1;
 611	}
 612
 613	if (gem_status & GREG_STAT_MAC) {
 614		if (gem_mac_interrupt(dev, gp, gem_status))
 615			return 1;
 616	}
 617
 618	if (gem_status & GREG_STAT_MIF) {
 619		if (gem_mif_interrupt(dev, gp, gem_status))
 620			return 1;
 621	}
 622
 623	if (gem_status & GREG_STAT_PCIERR) {
 624		if (gem_pci_interrupt(dev, gp, gem_status))
 625			return 1;
 626	}
 627
 628	return 0;
 629}
 630
 631static __inline__ void gem_tx(struct net_device *dev, struct gem *gp, u32 gem_status)
 632{
 633	int entry, limit;
 634
 635	entry = gp->tx_old;
 636	limit = ((gem_status & GREG_STAT_TXNR) >> GREG_STAT_TXNR_SHIFT);
 637	while (entry != limit) {
 638		struct sk_buff *skb;
 639		struct gem_txd *txd;
 640		dma_addr_t dma_addr;
 641		u32 dma_len;
 642		int frag;
 643
 644		if (netif_msg_tx_done(gp))
 645			printk(KERN_DEBUG "%s: tx done, slot %d\n",
 646				gp->dev->name, entry);
 647		skb = gp->tx_skbs[entry];
 648		if (skb_shinfo(skb)->nr_frags) {
 649			int last = entry + skb_shinfo(skb)->nr_frags;
 650			int walk = entry;
 651			int incomplete = 0;
 652
 653			last &= (TX_RING_SIZE - 1);
 654			for (;;) {
 655				walk = NEXT_TX(walk);
 656				if (walk == limit)
 657					incomplete = 1;
 658				if (walk == last)
 659					break;
 660			}
 661			if (incomplete)
 662				break;
 663		}
 664		gp->tx_skbs[entry] = NULL;
 665		dev->stats.tx_bytes += skb->len;
 666
 667		for (frag = 0; frag <= skb_shinfo(skb)->nr_frags; frag++) {
 668			txd = &gp->init_block->txd[entry];
 669
 670			dma_addr = le64_to_cpu(txd->buffer);
 671			dma_len = le64_to_cpu(txd->control_word) & TXDCTRL_BUFSZ;
 672
 673			dma_unmap_page(&gp->pdev->dev, dma_addr, dma_len,
 674				       DMA_TO_DEVICE);
 675			entry = NEXT_TX(entry);
 676		}
 677
 678		dev->stats.tx_packets++;
 679		dev_consume_skb_any(skb);
 680	}
 681	gp->tx_old = entry;
 682
 683	/* Need to make the tx_old update visible to gem_start_xmit()
 684	 * before checking for netif_queue_stopped().  Without the
 685	 * memory barrier, there is a small possibility that gem_start_xmit()
 686	 * will miss it and cause the queue to be stopped forever.
 687	 */
 688	smp_mb();
 689
 690	if (unlikely(netif_queue_stopped(dev) &&
 691		     TX_BUFFS_AVAIL(gp) > (MAX_SKB_FRAGS + 1))) {
 692		struct netdev_queue *txq = netdev_get_tx_queue(dev, 0);
 693
 694		__netif_tx_lock(txq, smp_processor_id());
 695		if (netif_queue_stopped(dev) &&
 696		    TX_BUFFS_AVAIL(gp) > (MAX_SKB_FRAGS + 1))
 697			netif_wake_queue(dev);
 698		__netif_tx_unlock(txq);
 699	}
 700}
 701
 702static __inline__ void gem_post_rxds(struct gem *gp, int limit)
 703{
 704	int cluster_start, curr, count, kick;
 705
 706	cluster_start = curr = (gp->rx_new & ~(4 - 1));
 707	count = 0;
 708	kick = -1;
 709	dma_wmb();
 710	while (curr != limit) {
 711		curr = NEXT_RX(curr);
 712		if (++count == 4) {
 713			struct gem_rxd *rxd =
 714				&gp->init_block->rxd[cluster_start];
 715			for (;;) {
 716				rxd->status_word = cpu_to_le64(RXDCTRL_FRESH(gp));
 717				rxd++;
 718				cluster_start = NEXT_RX(cluster_start);
 719				if (cluster_start == curr)
 720					break;
 721			}
 722			kick = curr;
 723			count = 0;
 724		}
 725	}
 726	if (kick >= 0) {
 727		mb();
 728		writel(kick, gp->regs + RXDMA_KICK);
 729	}
 730}
 731
 732#define ALIGNED_RX_SKB_ADDR(addr) \
 733        ((((unsigned long)(addr) + (64UL - 1UL)) & ~(64UL - 1UL)) - (unsigned long)(addr))
 734static __inline__ struct sk_buff *gem_alloc_skb(struct net_device *dev, int size,
 735						gfp_t gfp_flags)
 736{
 737	struct sk_buff *skb = alloc_skb(size + 64, gfp_flags);
 738
 739	if (likely(skb)) {
 740		unsigned long offset = ALIGNED_RX_SKB_ADDR(skb->data);
 741		skb_reserve(skb, offset);
 742	}
 743	return skb;
 744}
 745
 746static int gem_rx(struct gem *gp, int work_to_do)
 747{
 748	struct net_device *dev = gp->dev;
 749	int entry, drops, work_done = 0;
 750	u32 done;
 
 751
 752	if (netif_msg_rx_status(gp))
 753		printk(KERN_DEBUG "%s: rx interrupt, done: %d, rx_new: %d\n",
 754			gp->dev->name, readl(gp->regs + RXDMA_DONE), gp->rx_new);
 755
 756	entry = gp->rx_new;
 757	drops = 0;
 758	done = readl(gp->regs + RXDMA_DONE);
 759	for (;;) {
 760		struct gem_rxd *rxd = &gp->init_block->rxd[entry];
 761		struct sk_buff *skb;
 762		u64 status = le64_to_cpu(rxd->status_word);
 763		dma_addr_t dma_addr;
 764		int len;
 765
 766		if ((status & RXDCTRL_OWN) != 0)
 767			break;
 768
 769		if (work_done >= RX_RING_SIZE || work_done >= work_to_do)
 770			break;
 771
 772		/* When writing back RX descriptor, GEM writes status
 773		 * then buffer address, possibly in separate transactions.
 774		 * If we don't wait for the chip to write both, we could
 775		 * post a new buffer to this descriptor then have GEM spam
 776		 * on the buffer address.  We sync on the RX completion
 777		 * register to prevent this from happening.
 778		 */
 779		if (entry == done) {
 780			done = readl(gp->regs + RXDMA_DONE);
 781			if (entry == done)
 782				break;
 783		}
 784
 785		/* We can now account for the work we're about to do */
 786		work_done++;
 787
 788		skb = gp->rx_skbs[entry];
 789
 790		len = (status & RXDCTRL_BUFSZ) >> 16;
 791		if ((len < ETH_ZLEN) || (status & RXDCTRL_BAD)) {
 792			dev->stats.rx_errors++;
 793			if (len < ETH_ZLEN)
 794				dev->stats.rx_length_errors++;
 795			if (len & RXDCTRL_BAD)
 796				dev->stats.rx_crc_errors++;
 797
 798			/* We'll just return it to GEM. */
 799		drop_it:
 800			dev->stats.rx_dropped++;
 801			goto next;
 802		}
 803
 804		dma_addr = le64_to_cpu(rxd->buffer);
 805		if (len > RX_COPY_THRESHOLD) {
 806			struct sk_buff *new_skb;
 807
 808			new_skb = gem_alloc_skb(dev, RX_BUF_ALLOC_SIZE(gp), GFP_ATOMIC);
 809			if (new_skb == NULL) {
 810				drops++;
 811				goto drop_it;
 812			}
 813			dma_unmap_page(&gp->pdev->dev, dma_addr,
 814				       RX_BUF_ALLOC_SIZE(gp), DMA_FROM_DEVICE);
 
 815			gp->rx_skbs[entry] = new_skb;
 816			skb_put(new_skb, (gp->rx_buf_sz + RX_OFFSET));
 817			rxd->buffer = cpu_to_le64(dma_map_page(&gp->pdev->dev,
 818							       virt_to_page(new_skb->data),
 819							       offset_in_page(new_skb->data),
 820							       RX_BUF_ALLOC_SIZE(gp),
 821							       DMA_FROM_DEVICE));
 822			skb_reserve(new_skb, RX_OFFSET);
 823
 824			/* Trim the original skb for the netif. */
 825			skb_trim(skb, len);
 826		} else {
 827			struct sk_buff *copy_skb = netdev_alloc_skb(dev, len + 2);
 828
 829			if (copy_skb == NULL) {
 830				drops++;
 831				goto drop_it;
 832			}
 833
 834			skb_reserve(copy_skb, 2);
 835			skb_put(copy_skb, len);
 836			dma_sync_single_for_cpu(&gp->pdev->dev, dma_addr, len,
 837						DMA_FROM_DEVICE);
 838			skb_copy_from_linear_data(skb, copy_skb->data, len);
 839			dma_sync_single_for_device(&gp->pdev->dev, dma_addr,
 840						   len, DMA_FROM_DEVICE);
 841
 842			/* We'll reuse the original ring buffer. */
 843			skb = copy_skb;
 844		}
 845
 846		if (likely(dev->features & NETIF_F_RXCSUM)) {
 847			__sum16 csum;
 848
 849			csum = (__force __sum16)htons((status & RXDCTRL_TCPCSUM) ^ 0xffff);
 850			skb->csum = csum_unfold(csum);
 851			skb->ip_summed = CHECKSUM_COMPLETE;
 852		}
 853		skb->protocol = eth_type_trans(skb, gp->dev);
 854
 855		napi_gro_receive(&gp->napi, skb);
 856
 857		dev->stats.rx_packets++;
 858		dev->stats.rx_bytes += len;
 859
 860	next:
 861		entry = NEXT_RX(entry);
 862	}
 863
 864	gem_post_rxds(gp, entry);
 865
 866	gp->rx_new = entry;
 867
 868	if (drops)
 869		netdev_info(gp->dev, "Memory squeeze, deferring packet\n");
 870
 871	return work_done;
 872}
 873
 874static int gem_poll(struct napi_struct *napi, int budget)
 875{
 876	struct gem *gp = container_of(napi, struct gem, napi);
 877	struct net_device *dev = gp->dev;
 878	int work_done;
 879
 880	work_done = 0;
 881	do {
 882		/* Handle anomalies */
 883		if (unlikely(gp->status & GREG_STAT_ABNORMAL)) {
 884			struct netdev_queue *txq = netdev_get_tx_queue(dev, 0);
 885			int reset;
 886
 887			/* We run the abnormal interrupt handling code with
 888			 * the Tx lock. It only resets the Rx portion of the
 889			 * chip, but we need to guard it against DMA being
 890			 * restarted by the link poll timer
 891			 */
 892			__netif_tx_lock(txq, smp_processor_id());
 893			reset = gem_abnormal_irq(dev, gp, gp->status);
 894			__netif_tx_unlock(txq);
 895			if (reset) {
 896				gem_schedule_reset(gp);
 897				napi_complete(napi);
 898				return work_done;
 899			}
 900		}
 901
 902		/* Run TX completion thread */
 903		gem_tx(dev, gp, gp->status);
 904
 905		/* Run RX thread. We don't use any locking here,
 906		 * code willing to do bad things - like cleaning the
 907		 * rx ring - must call napi_disable(), which
 908		 * schedule_timeout()'s if polling is already disabled.
 909		 */
 910		work_done += gem_rx(gp, budget - work_done);
 911
 912		if (work_done >= budget)
 913			return work_done;
 914
 915		gp->status = readl(gp->regs + GREG_STAT);
 916	} while (gp->status & GREG_STAT_NAPI);
 917
 918	napi_complete_done(napi, work_done);
 919	gem_enable_ints(gp);
 920
 921	return work_done;
 922}
 923
 924static irqreturn_t gem_interrupt(int irq, void *dev_id)
 925{
 926	struct net_device *dev = dev_id;
 927	struct gem *gp = netdev_priv(dev);
 928
 929	if (napi_schedule_prep(&gp->napi)) {
 930		u32 gem_status = readl(gp->regs + GREG_STAT);
 931
 932		if (unlikely(gem_status == 0)) {
 933			napi_enable(&gp->napi);
 934			return IRQ_NONE;
 935		}
 936		if (netif_msg_intr(gp))
 937			printk(KERN_DEBUG "%s: gem_interrupt() gem_status: 0x%x\n",
 938			       gp->dev->name, gem_status);
 939
 940		gp->status = gem_status;
 941		gem_disable_ints(gp);
 942		__napi_schedule(&gp->napi);
 943	}
 944
 945	/* If polling was disabled at the time we received that
 946	 * interrupt, we may return IRQ_HANDLED here while we
 947	 * should return IRQ_NONE. No big deal...
 948	 */
 949	return IRQ_HANDLED;
 950}
 951
 952static void gem_tx_timeout(struct net_device *dev, unsigned int txqueue)
 
 
 
 
 
 
 
 
 
 
 
 953{
 954	struct gem *gp = netdev_priv(dev);
 955
 956	netdev_err(dev, "transmit timed out, resetting\n");
 957
 958	netdev_err(dev, "TX_STATE[%08x:%08x:%08x]\n",
 959		   readl(gp->regs + TXDMA_CFG),
 960		   readl(gp->regs + MAC_TXSTAT),
 961		   readl(gp->regs + MAC_TXCFG));
 962	netdev_err(dev, "RX_STATE[%08x:%08x:%08x]\n",
 963		   readl(gp->regs + RXDMA_CFG),
 964		   readl(gp->regs + MAC_RXSTAT),
 965		   readl(gp->regs + MAC_RXCFG));
 966
 967	gem_schedule_reset(gp);
 968}
 969
 970static __inline__ int gem_intme(int entry)
 971{
 972	/* Algorithm: IRQ every 1/2 of descriptors. */
 973	if (!(entry & ((TX_RING_SIZE>>1)-1)))
 974		return 1;
 975
 976	return 0;
 977}
 978
 979static netdev_tx_t gem_start_xmit(struct sk_buff *skb,
 980				  struct net_device *dev)
 981{
 982	struct gem *gp = netdev_priv(dev);
 983	int entry;
 984	u64 ctrl;
 985
 986	ctrl = 0;
 987	if (skb->ip_summed == CHECKSUM_PARTIAL) {
 988		const u64 csum_start_off = skb_checksum_start_offset(skb);
 989		const u64 csum_stuff_off = csum_start_off + skb->csum_offset;
 990
 991		ctrl = (TXDCTRL_CENAB |
 992			(csum_start_off << 15) |
 993			(csum_stuff_off << 21));
 994	}
 995
 996	if (unlikely(TX_BUFFS_AVAIL(gp) <= (skb_shinfo(skb)->nr_frags + 1))) {
 997		/* This is a hard error, log it. */
 998		if (!netif_queue_stopped(dev)) {
 999			netif_stop_queue(dev);
1000			netdev_err(dev, "BUG! Tx Ring full when queue awake!\n");
1001		}
1002		return NETDEV_TX_BUSY;
1003	}
1004
1005	entry = gp->tx_new;
1006	gp->tx_skbs[entry] = skb;
1007
1008	if (skb_shinfo(skb)->nr_frags == 0) {
1009		struct gem_txd *txd = &gp->init_block->txd[entry];
1010		dma_addr_t mapping;
1011		u32 len;
1012
1013		len = skb->len;
1014		mapping = dma_map_page(&gp->pdev->dev,
1015				       virt_to_page(skb->data),
1016				       offset_in_page(skb->data),
1017				       len, DMA_TO_DEVICE);
1018		ctrl |= TXDCTRL_SOF | TXDCTRL_EOF | len;
1019		if (gem_intme(entry))
1020			ctrl |= TXDCTRL_INTME;
1021		txd->buffer = cpu_to_le64(mapping);
1022		dma_wmb();
1023		txd->control_word = cpu_to_le64(ctrl);
1024		entry = NEXT_TX(entry);
1025	} else {
1026		struct gem_txd *txd;
1027		u32 first_len;
1028		u64 intme;
1029		dma_addr_t first_mapping;
1030		int frag, first_entry = entry;
1031
1032		intme = 0;
1033		if (gem_intme(entry))
1034			intme |= TXDCTRL_INTME;
1035
1036		/* We must give this initial chunk to the device last.
1037		 * Otherwise we could race with the device.
1038		 */
1039		first_len = skb_headlen(skb);
1040		first_mapping = dma_map_page(&gp->pdev->dev,
1041					     virt_to_page(skb->data),
1042					     offset_in_page(skb->data),
1043					     first_len, DMA_TO_DEVICE);
1044		entry = NEXT_TX(entry);
1045
1046		for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) {
1047			const skb_frag_t *this_frag = &skb_shinfo(skb)->frags[frag];
1048			u32 len;
1049			dma_addr_t mapping;
1050			u64 this_ctrl;
1051
1052			len = skb_frag_size(this_frag);
1053			mapping = skb_frag_dma_map(&gp->pdev->dev, this_frag,
1054						   0, len, DMA_TO_DEVICE);
1055			this_ctrl = ctrl;
1056			if (frag == skb_shinfo(skb)->nr_frags - 1)
1057				this_ctrl |= TXDCTRL_EOF;
1058
1059			txd = &gp->init_block->txd[entry];
1060			txd->buffer = cpu_to_le64(mapping);
1061			dma_wmb();
1062			txd->control_word = cpu_to_le64(this_ctrl | len);
1063
1064			if (gem_intme(entry))
1065				intme |= TXDCTRL_INTME;
1066
1067			entry = NEXT_TX(entry);
1068		}
1069		txd = &gp->init_block->txd[first_entry];
1070		txd->buffer = cpu_to_le64(first_mapping);
1071		dma_wmb();
1072		txd->control_word =
1073			cpu_to_le64(ctrl | TXDCTRL_SOF | intme | first_len);
1074	}
1075
1076	gp->tx_new = entry;
1077	if (unlikely(TX_BUFFS_AVAIL(gp) <= (MAX_SKB_FRAGS + 1))) {
1078		netif_stop_queue(dev);
1079
1080		/* netif_stop_queue() must be done before checking
1081		 * tx index in TX_BUFFS_AVAIL() below, because
1082		 * in gem_tx(), we update tx_old before checking for
1083		 * netif_queue_stopped().
1084		 */
1085		smp_mb();
1086		if (TX_BUFFS_AVAIL(gp) > (MAX_SKB_FRAGS + 1))
1087			netif_wake_queue(dev);
1088	}
1089	if (netif_msg_tx_queued(gp))
1090		printk(KERN_DEBUG "%s: tx queued, slot %d, skblen %d\n",
1091		       dev->name, entry, skb->len);
1092	mb();
1093	writel(gp->tx_new, gp->regs + TXDMA_KICK);
1094
1095	return NETDEV_TX_OK;
1096}
1097
1098static void gem_pcs_reset(struct gem *gp)
1099{
1100	int limit;
1101	u32 val;
1102
1103	/* Reset PCS unit. */
1104	val = readl(gp->regs + PCS_MIICTRL);
1105	val |= PCS_MIICTRL_RST;
1106	writel(val, gp->regs + PCS_MIICTRL);
1107
1108	limit = 32;
1109	while (readl(gp->regs + PCS_MIICTRL) & PCS_MIICTRL_RST) {
1110		udelay(100);
1111		if (limit-- <= 0)
1112			break;
1113	}
1114	if (limit < 0)
1115		netdev_warn(gp->dev, "PCS reset bit would not clear\n");
1116}
1117
1118static void gem_pcs_reinit_adv(struct gem *gp)
1119{
1120	u32 val;
1121
1122	/* Make sure PCS is disabled while changing advertisement
1123	 * configuration.
1124	 */
1125	val = readl(gp->regs + PCS_CFG);
1126	val &= ~(PCS_CFG_ENABLE | PCS_CFG_TO);
1127	writel(val, gp->regs + PCS_CFG);
1128
1129	/* Advertise all capabilities except asymmetric
1130	 * pause.
1131	 */
1132	val = readl(gp->regs + PCS_MIIADV);
1133	val |= (PCS_MIIADV_FD | PCS_MIIADV_HD |
1134		PCS_MIIADV_SP | PCS_MIIADV_AP);
1135	writel(val, gp->regs + PCS_MIIADV);
1136
1137	/* Enable and restart auto-negotiation, disable wrapback/loopback,
1138	 * and re-enable PCS.
1139	 */
1140	val = readl(gp->regs + PCS_MIICTRL);
1141	val |= (PCS_MIICTRL_RAN | PCS_MIICTRL_ANE);
1142	val &= ~PCS_MIICTRL_WB;
1143	writel(val, gp->regs + PCS_MIICTRL);
1144
1145	val = readl(gp->regs + PCS_CFG);
1146	val |= PCS_CFG_ENABLE;
1147	writel(val, gp->regs + PCS_CFG);
1148
1149	/* Make sure serialink loopback is off.  The meaning
1150	 * of this bit is logically inverted based upon whether
1151	 * you are in Serialink or SERDES mode.
1152	 */
1153	val = readl(gp->regs + PCS_SCTRL);
1154	if (gp->phy_type == phy_serialink)
1155		val &= ~PCS_SCTRL_LOOP;
1156	else
1157		val |= PCS_SCTRL_LOOP;
1158	writel(val, gp->regs + PCS_SCTRL);
1159}
1160
1161#define STOP_TRIES 32
1162
1163static void gem_reset(struct gem *gp)
1164{
1165	int limit;
1166	u32 val;
1167
1168	/* Make sure we won't get any more interrupts */
1169	writel(0xffffffff, gp->regs + GREG_IMASK);
1170
1171	/* Reset the chip */
1172	writel(gp->swrst_base | GREG_SWRST_TXRST | GREG_SWRST_RXRST,
1173	       gp->regs + GREG_SWRST);
1174
1175	limit = STOP_TRIES;
1176
1177	do {
1178		udelay(20);
1179		val = readl(gp->regs + GREG_SWRST);
1180		if (limit-- <= 0)
1181			break;
1182	} while (val & (GREG_SWRST_TXRST | GREG_SWRST_RXRST));
1183
1184	if (limit < 0)
1185		netdev_err(gp->dev, "SW reset is ghetto\n");
1186
1187	if (gp->phy_type == phy_serialink || gp->phy_type == phy_serdes)
1188		gem_pcs_reinit_adv(gp);
1189}
1190
1191static void gem_start_dma(struct gem *gp)
1192{
1193	u32 val;
1194
1195	/* We are ready to rock, turn everything on. */
1196	val = readl(gp->regs + TXDMA_CFG);
1197	writel(val | TXDMA_CFG_ENABLE, gp->regs + TXDMA_CFG);
1198	val = readl(gp->regs + RXDMA_CFG);
1199	writel(val | RXDMA_CFG_ENABLE, gp->regs + RXDMA_CFG);
1200	val = readl(gp->regs + MAC_TXCFG);
1201	writel(val | MAC_TXCFG_ENAB, gp->regs + MAC_TXCFG);
1202	val = readl(gp->regs + MAC_RXCFG);
1203	writel(val | MAC_RXCFG_ENAB, gp->regs + MAC_RXCFG);
1204
1205	(void) readl(gp->regs + MAC_RXCFG);
1206	udelay(100);
1207
1208	gem_enable_ints(gp);
1209
1210	writel(RX_RING_SIZE - 4, gp->regs + RXDMA_KICK);
1211}
1212
1213/* DMA won't be actually stopped before about 4ms tho ...
1214 */
1215static void gem_stop_dma(struct gem *gp)
1216{
1217	u32 val;
1218
1219	/* We are done rocking, turn everything off. */
1220	val = readl(gp->regs + TXDMA_CFG);
1221	writel(val & ~TXDMA_CFG_ENABLE, gp->regs + TXDMA_CFG);
1222	val = readl(gp->regs + RXDMA_CFG);
1223	writel(val & ~RXDMA_CFG_ENABLE, gp->regs + RXDMA_CFG);
1224	val = readl(gp->regs + MAC_TXCFG);
1225	writel(val & ~MAC_TXCFG_ENAB, gp->regs + MAC_TXCFG);
1226	val = readl(gp->regs + MAC_RXCFG);
1227	writel(val & ~MAC_RXCFG_ENAB, gp->regs + MAC_RXCFG);
1228
1229	(void) readl(gp->regs + MAC_RXCFG);
1230
1231	/* Need to wait a bit ... done by the caller */
1232}
1233
1234
1235// XXX dbl check what that function should do when called on PCS PHY
1236static void gem_begin_auto_negotiation(struct gem *gp,
1237				       const struct ethtool_link_ksettings *ep)
1238{
1239	u32 advertise, features;
1240	int autoneg;
1241	int speed;
1242	int duplex;
1243	u32 advertising;
1244
1245	if (ep)
1246		ethtool_convert_link_mode_to_legacy_u32(
1247			&advertising, ep->link_modes.advertising);
1248
1249	if (gp->phy_type != phy_mii_mdio0 &&
1250	    gp->phy_type != phy_mii_mdio1)
1251		goto non_mii;
1252
1253	/* Setup advertise */
1254	if (found_mii_phy(gp))
1255		features = gp->phy_mii.def->features;
1256	else
1257		features = 0;
1258
1259	advertise = features & ADVERTISE_MASK;
1260	if (gp->phy_mii.advertising != 0)
1261		advertise &= gp->phy_mii.advertising;
1262
1263	autoneg = gp->want_autoneg;
1264	speed = gp->phy_mii.speed;
1265	duplex = gp->phy_mii.duplex;
1266
1267	/* Setup link parameters */
1268	if (!ep)
1269		goto start_aneg;
1270	if (ep->base.autoneg == AUTONEG_ENABLE) {
1271		advertise = advertising;
1272		autoneg = 1;
1273	} else {
1274		autoneg = 0;
1275		speed = ep->base.speed;
1276		duplex = ep->base.duplex;
1277	}
1278
1279start_aneg:
1280	/* Sanitize settings based on PHY capabilities */
1281	if ((features & SUPPORTED_Autoneg) == 0)
1282		autoneg = 0;
1283	if (speed == SPEED_1000 &&
1284	    !(features & (SUPPORTED_1000baseT_Half | SUPPORTED_1000baseT_Full)))
1285		speed = SPEED_100;
1286	if (speed == SPEED_100 &&
1287	    !(features & (SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full)))
1288		speed = SPEED_10;
1289	if (duplex == DUPLEX_FULL &&
1290	    !(features & (SUPPORTED_1000baseT_Full |
1291	    		  SUPPORTED_100baseT_Full |
1292	    		  SUPPORTED_10baseT_Full)))
1293	    	duplex = DUPLEX_HALF;
1294	if (speed == 0)
1295		speed = SPEED_10;
1296
1297	/* If we are asleep, we don't try to actually setup the PHY, we
1298	 * just store the settings
1299	 */
1300	if (!netif_device_present(gp->dev)) {
1301		gp->phy_mii.autoneg = gp->want_autoneg = autoneg;
1302		gp->phy_mii.speed = speed;
1303		gp->phy_mii.duplex = duplex;
1304		return;
1305	}
1306
1307	/* Configure PHY & start aneg */
1308	gp->want_autoneg = autoneg;
1309	if (autoneg) {
1310		if (found_mii_phy(gp))
1311			gp->phy_mii.def->ops->setup_aneg(&gp->phy_mii, advertise);
1312		gp->lstate = link_aneg;
1313	} else {
1314		if (found_mii_phy(gp))
1315			gp->phy_mii.def->ops->setup_forced(&gp->phy_mii, speed, duplex);
1316		gp->lstate = link_force_ok;
1317	}
1318
1319non_mii:
1320	gp->timer_ticks = 0;
1321	mod_timer(&gp->link_timer, jiffies + ((12 * HZ) / 10));
1322}
1323
1324/* A link-up condition has occurred, initialize and enable the
1325 * rest of the chip.
1326 */
1327static int gem_set_link_modes(struct gem *gp)
1328{
1329	struct netdev_queue *txq = netdev_get_tx_queue(gp->dev, 0);
1330	int full_duplex, speed, pause;
1331	u32 val;
1332
1333	full_duplex = 0;
1334	speed = SPEED_10;
1335	pause = 0;
1336
1337	if (found_mii_phy(gp)) {
1338	    	if (gp->phy_mii.def->ops->read_link(&gp->phy_mii))
1339	    		return 1;
1340		full_duplex = (gp->phy_mii.duplex == DUPLEX_FULL);
1341		speed = gp->phy_mii.speed;
1342		pause = gp->phy_mii.pause;
1343	} else if (gp->phy_type == phy_serialink ||
1344	    	   gp->phy_type == phy_serdes) {
1345		u32 pcs_lpa = readl(gp->regs + PCS_MIILP);
1346
1347		if ((pcs_lpa & PCS_MIIADV_FD) || gp->phy_type == phy_serdes)
1348			full_duplex = 1;
1349		speed = SPEED_1000;
1350	}
1351
1352	netif_info(gp, link, gp->dev, "Link is up at %d Mbps, %s-duplex\n",
1353		   speed, (full_duplex ? "full" : "half"));
1354
1355
1356	/* We take the tx queue lock to avoid collisions between
1357	 * this code, the tx path and the NAPI-driven error path
1358	 */
1359	__netif_tx_lock(txq, smp_processor_id());
1360
1361	val = (MAC_TXCFG_EIPG0 | MAC_TXCFG_NGU);
1362	if (full_duplex) {
1363		val |= (MAC_TXCFG_ICS | MAC_TXCFG_ICOLL);
1364	} else {
1365		/* MAC_TXCFG_NBO must be zero. */
1366	}
1367	writel(val, gp->regs + MAC_TXCFG);
1368
1369	val = (MAC_XIFCFG_OE | MAC_XIFCFG_LLED);
1370	if (!full_duplex &&
1371	    (gp->phy_type == phy_mii_mdio0 ||
1372	     gp->phy_type == phy_mii_mdio1)) {
1373		val |= MAC_XIFCFG_DISE;
1374	} else if (full_duplex) {
1375		val |= MAC_XIFCFG_FLED;
1376	}
1377
1378	if (speed == SPEED_1000)
1379		val |= (MAC_XIFCFG_GMII);
1380
1381	writel(val, gp->regs + MAC_XIFCFG);
1382
1383	/* If gigabit and half-duplex, enable carrier extension
1384	 * mode.  Else, disable it.
1385	 */
1386	if (speed == SPEED_1000 && !full_duplex) {
1387		val = readl(gp->regs + MAC_TXCFG);
1388		writel(val | MAC_TXCFG_TCE, gp->regs + MAC_TXCFG);
1389
1390		val = readl(gp->regs + MAC_RXCFG);
1391		writel(val | MAC_RXCFG_RCE, gp->regs + MAC_RXCFG);
1392	} else {
1393		val = readl(gp->regs + MAC_TXCFG);
1394		writel(val & ~MAC_TXCFG_TCE, gp->regs + MAC_TXCFG);
1395
1396		val = readl(gp->regs + MAC_RXCFG);
1397		writel(val & ~MAC_RXCFG_RCE, gp->regs + MAC_RXCFG);
1398	}
1399
1400	if (gp->phy_type == phy_serialink ||
1401	    gp->phy_type == phy_serdes) {
1402		u32 pcs_lpa = readl(gp->regs + PCS_MIILP);
1403
1404		if (pcs_lpa & (PCS_MIIADV_SP | PCS_MIIADV_AP))
1405			pause = 1;
1406	}
1407
1408	if (!full_duplex)
1409		writel(512, gp->regs + MAC_STIME);
1410	else
1411		writel(64, gp->regs + MAC_STIME);
1412	val = readl(gp->regs + MAC_MCCFG);
1413	if (pause)
1414		val |= (MAC_MCCFG_SPE | MAC_MCCFG_RPE);
1415	else
1416		val &= ~(MAC_MCCFG_SPE | MAC_MCCFG_RPE);
1417	writel(val, gp->regs + MAC_MCCFG);
1418
1419	gem_start_dma(gp);
1420
1421	__netif_tx_unlock(txq);
1422
1423	if (netif_msg_link(gp)) {
1424		if (pause) {
1425			netdev_info(gp->dev,
1426				    "Pause is enabled (rxfifo: %d off: %d on: %d)\n",
1427				    gp->rx_fifo_sz,
1428				    gp->rx_pause_off,
1429				    gp->rx_pause_on);
1430		} else {
1431			netdev_info(gp->dev, "Pause is disabled\n");
1432		}
1433	}
1434
1435	return 0;
1436}
1437
1438static int gem_mdio_link_not_up(struct gem *gp)
1439{
1440	switch (gp->lstate) {
1441	case link_force_ret:
1442		netif_info(gp, link, gp->dev,
1443			   "Autoneg failed again, keeping forced mode\n");
1444		gp->phy_mii.def->ops->setup_forced(&gp->phy_mii,
1445			gp->last_forced_speed, DUPLEX_HALF);
1446		gp->timer_ticks = 5;
1447		gp->lstate = link_force_ok;
1448		return 0;
1449	case link_aneg:
1450		/* We try forced modes after a failed aneg only on PHYs that don't
1451		 * have "magic_aneg" bit set, which means they internally do the
1452		 * while forced-mode thingy. On these, we just restart aneg
1453		 */
1454		if (gp->phy_mii.def->magic_aneg)
1455			return 1;
1456		netif_info(gp, link, gp->dev, "switching to forced 100bt\n");
1457		/* Try forced modes. */
1458		gp->phy_mii.def->ops->setup_forced(&gp->phy_mii, SPEED_100,
1459			DUPLEX_HALF);
1460		gp->timer_ticks = 5;
1461		gp->lstate = link_force_try;
1462		return 0;
1463	case link_force_try:
1464		/* Downgrade from 100 to 10 Mbps if necessary.
1465		 * If already at 10Mbps, warn user about the
1466		 * situation every 10 ticks.
1467		 */
1468		if (gp->phy_mii.speed == SPEED_100) {
1469			gp->phy_mii.def->ops->setup_forced(&gp->phy_mii, SPEED_10,
1470				DUPLEX_HALF);
1471			gp->timer_ticks = 5;
1472			netif_info(gp, link, gp->dev,
1473				   "switching to forced 10bt\n");
1474			return 0;
1475		} else
1476			return 1;
1477	default:
1478		return 0;
1479	}
1480}
1481
1482static void gem_link_timer(struct timer_list *t)
1483{
1484	struct gem *gp = from_timer(gp, t, link_timer);
1485	struct net_device *dev = gp->dev;
1486	int restart_aneg = 0;
1487
1488	/* There's no point doing anything if we're going to be reset */
1489	if (gp->reset_task_pending)
1490		return;
1491
1492	if (gp->phy_type == phy_serialink ||
1493	    gp->phy_type == phy_serdes) {
1494		u32 val = readl(gp->regs + PCS_MIISTAT);
1495
1496		if (!(val & PCS_MIISTAT_LS))
1497			val = readl(gp->regs + PCS_MIISTAT);
1498
1499		if ((val & PCS_MIISTAT_LS) != 0) {
1500			if (gp->lstate == link_up)
1501				goto restart;
1502
1503			gp->lstate = link_up;
1504			netif_carrier_on(dev);
1505			(void)gem_set_link_modes(gp);
1506		}
1507		goto restart;
1508	}
1509	if (found_mii_phy(gp) && gp->phy_mii.def->ops->poll_link(&gp->phy_mii)) {
1510		/* Ok, here we got a link. If we had it due to a forced
1511		 * fallback, and we were configured for autoneg, we do
1512		 * retry a short autoneg pass. If you know your hub is
1513		 * broken, use ethtool ;)
1514		 */
1515		if (gp->lstate == link_force_try && gp->want_autoneg) {
1516			gp->lstate = link_force_ret;
1517			gp->last_forced_speed = gp->phy_mii.speed;
1518			gp->timer_ticks = 5;
1519			if (netif_msg_link(gp))
1520				netdev_info(dev,
1521					    "Got link after fallback, retrying autoneg once...\n");
1522			gp->phy_mii.def->ops->setup_aneg(&gp->phy_mii, gp->phy_mii.advertising);
1523		} else if (gp->lstate != link_up) {
1524			gp->lstate = link_up;
1525			netif_carrier_on(dev);
1526			if (gem_set_link_modes(gp))
1527				restart_aneg = 1;
1528		}
1529	} else {
1530		/* If the link was previously up, we restart the
1531		 * whole process
1532		 */
1533		if (gp->lstate == link_up) {
1534			gp->lstate = link_down;
1535			netif_info(gp, link, dev, "Link down\n");
1536			netif_carrier_off(dev);
1537			gem_schedule_reset(gp);
1538			/* The reset task will restart the timer */
1539			return;
1540		} else if (++gp->timer_ticks > 10) {
1541			if (found_mii_phy(gp))
1542				restart_aneg = gem_mdio_link_not_up(gp);
1543			else
1544				restart_aneg = 1;
1545		}
1546	}
1547	if (restart_aneg) {
1548		gem_begin_auto_negotiation(gp, NULL);
1549		return;
1550	}
1551restart:
1552	mod_timer(&gp->link_timer, jiffies + ((12 * HZ) / 10));
1553}
1554
1555static void gem_clean_rings(struct gem *gp)
1556{
1557	struct gem_init_block *gb = gp->init_block;
1558	struct sk_buff *skb;
1559	int i;
1560	dma_addr_t dma_addr;
1561
1562	for (i = 0; i < RX_RING_SIZE; i++) {
1563		struct gem_rxd *rxd;
1564
1565		rxd = &gb->rxd[i];
1566		if (gp->rx_skbs[i] != NULL) {
1567			skb = gp->rx_skbs[i];
1568			dma_addr = le64_to_cpu(rxd->buffer);
1569			dma_unmap_page(&gp->pdev->dev, dma_addr,
1570				       RX_BUF_ALLOC_SIZE(gp),
1571				       DMA_FROM_DEVICE);
1572			dev_kfree_skb_any(skb);
1573			gp->rx_skbs[i] = NULL;
1574		}
1575		rxd->status_word = 0;
1576		dma_wmb();
1577		rxd->buffer = 0;
1578	}
1579
1580	for (i = 0; i < TX_RING_SIZE; i++) {
1581		if (gp->tx_skbs[i] != NULL) {
1582			struct gem_txd *txd;
1583			int frag;
1584
1585			skb = gp->tx_skbs[i];
1586			gp->tx_skbs[i] = NULL;
1587
1588			for (frag = 0; frag <= skb_shinfo(skb)->nr_frags; frag++) {
1589				int ent = i & (TX_RING_SIZE - 1);
1590
1591				txd = &gb->txd[ent];
1592				dma_addr = le64_to_cpu(txd->buffer);
1593				dma_unmap_page(&gp->pdev->dev, dma_addr,
1594					       le64_to_cpu(txd->control_word) &
1595					       TXDCTRL_BUFSZ, DMA_TO_DEVICE);
1596
1597				if (frag != skb_shinfo(skb)->nr_frags)
1598					i++;
1599			}
1600			dev_kfree_skb_any(skb);
1601		}
1602	}
1603}
1604
1605static void gem_init_rings(struct gem *gp)
1606{
1607	struct gem_init_block *gb = gp->init_block;
1608	struct net_device *dev = gp->dev;
1609	int i;
1610	dma_addr_t dma_addr;
1611
1612	gp->rx_new = gp->rx_old = gp->tx_new = gp->tx_old = 0;
1613
1614	gem_clean_rings(gp);
1615
1616	gp->rx_buf_sz = max(dev->mtu + ETH_HLEN + VLAN_HLEN,
1617			    (unsigned)VLAN_ETH_FRAME_LEN);
1618
1619	for (i = 0; i < RX_RING_SIZE; i++) {
1620		struct sk_buff *skb;
1621		struct gem_rxd *rxd = &gb->rxd[i];
1622
1623		skb = gem_alloc_skb(dev, RX_BUF_ALLOC_SIZE(gp), GFP_KERNEL);
1624		if (!skb) {
1625			rxd->buffer = 0;
1626			rxd->status_word = 0;
1627			continue;
1628		}
1629
1630		gp->rx_skbs[i] = skb;
1631		skb_put(skb, (gp->rx_buf_sz + RX_OFFSET));
1632		dma_addr = dma_map_page(&gp->pdev->dev,
1633					virt_to_page(skb->data),
1634					offset_in_page(skb->data),
1635					RX_BUF_ALLOC_SIZE(gp),
1636					DMA_FROM_DEVICE);
1637		rxd->buffer = cpu_to_le64(dma_addr);
1638		dma_wmb();
1639		rxd->status_word = cpu_to_le64(RXDCTRL_FRESH(gp));
1640		skb_reserve(skb, RX_OFFSET);
1641	}
1642
1643	for (i = 0; i < TX_RING_SIZE; i++) {
1644		struct gem_txd *txd = &gb->txd[i];
1645
1646		txd->control_word = 0;
1647		dma_wmb();
1648		txd->buffer = 0;
1649	}
1650	wmb();
1651}
1652
1653/* Init PHY interface and start link poll state machine */
1654static void gem_init_phy(struct gem *gp)
1655{
1656	u32 mifcfg;
1657
1658	/* Revert MIF CFG setting done on stop_phy */
1659	mifcfg = readl(gp->regs + MIF_CFG);
1660	mifcfg &= ~MIF_CFG_BBMODE;
1661	writel(mifcfg, gp->regs + MIF_CFG);
1662
1663	if (gp->pdev->vendor == PCI_VENDOR_ID_APPLE) {
1664		int i;
1665
1666		/* Those delays sucks, the HW seems to love them though, I'll
1667		 * seriously consider breaking some locks here to be able
1668		 * to schedule instead
1669		 */
1670		for (i = 0; i < 3; i++) {
1671#ifdef CONFIG_PPC_PMAC
1672			pmac_call_feature(PMAC_FTR_GMAC_PHY_RESET, gp->of_node, 0, 0);
1673			msleep(20);
1674#endif
1675			/* Some PHYs used by apple have problem getting back to us,
1676			 * we do an additional reset here
1677			 */
1678			sungem_phy_write(gp, MII_BMCR, BMCR_RESET);
1679			msleep(20);
1680			if (sungem_phy_read(gp, MII_BMCR) != 0xffff)
1681				break;
1682			if (i == 2)
1683				netdev_warn(gp->dev, "GMAC PHY not responding !\n");
1684		}
1685	}
1686
1687	if (gp->pdev->vendor == PCI_VENDOR_ID_SUN &&
1688	    gp->pdev->device == PCI_DEVICE_ID_SUN_GEM) {
1689		u32 val;
1690
1691		/* Init datapath mode register. */
1692		if (gp->phy_type == phy_mii_mdio0 ||
1693		    gp->phy_type == phy_mii_mdio1) {
1694			val = PCS_DMODE_MGM;
1695		} else if (gp->phy_type == phy_serialink) {
1696			val = PCS_DMODE_SM | PCS_DMODE_GMOE;
1697		} else {
1698			val = PCS_DMODE_ESM;
1699		}
1700
1701		writel(val, gp->regs + PCS_DMODE);
1702	}
1703
1704	if (gp->phy_type == phy_mii_mdio0 ||
1705	    gp->phy_type == phy_mii_mdio1) {
1706		/* Reset and detect MII PHY */
1707		sungem_phy_probe(&gp->phy_mii, gp->mii_phy_addr);
1708
1709		/* Init PHY */
1710		if (gp->phy_mii.def && gp->phy_mii.def->ops->init)
1711			gp->phy_mii.def->ops->init(&gp->phy_mii);
1712	} else {
1713		gem_pcs_reset(gp);
1714		gem_pcs_reinit_adv(gp);
1715	}
1716
1717	/* Default aneg parameters */
1718	gp->timer_ticks = 0;
1719	gp->lstate = link_down;
1720	netif_carrier_off(gp->dev);
1721
1722	/* Print things out */
1723	if (gp->phy_type == phy_mii_mdio0 ||
1724	    gp->phy_type == phy_mii_mdio1)
1725		netdev_info(gp->dev, "Found %s PHY\n",
1726			    gp->phy_mii.def ? gp->phy_mii.def->name : "no");
1727
1728	gem_begin_auto_negotiation(gp, NULL);
1729}
1730
1731static void gem_init_dma(struct gem *gp)
1732{
1733	u64 desc_dma = (u64) gp->gblock_dvma;
1734	u32 val;
1735
1736	val = (TXDMA_CFG_BASE | (0x7ff << 10) | TXDMA_CFG_PMODE);
1737	writel(val, gp->regs + TXDMA_CFG);
1738
1739	writel(desc_dma >> 32, gp->regs + TXDMA_DBHI);
1740	writel(desc_dma & 0xffffffff, gp->regs + TXDMA_DBLOW);
1741	desc_dma += (INIT_BLOCK_TX_RING_SIZE * sizeof(struct gem_txd));
1742
1743	writel(0, gp->regs + TXDMA_KICK);
1744
1745	val = (RXDMA_CFG_BASE | (RX_OFFSET << 10) |
1746	       (ETH_HLEN << 13) | RXDMA_CFG_FTHRESH_128);
1747	writel(val, gp->regs + RXDMA_CFG);
1748
1749	writel(desc_dma >> 32, gp->regs + RXDMA_DBHI);
1750	writel(desc_dma & 0xffffffff, gp->regs + RXDMA_DBLOW);
1751
1752	writel(RX_RING_SIZE - 4, gp->regs + RXDMA_KICK);
1753
1754	val  = (((gp->rx_pause_off / 64) << 0) & RXDMA_PTHRESH_OFF);
1755	val |= (((gp->rx_pause_on / 64) << 12) & RXDMA_PTHRESH_ON);
1756	writel(val, gp->regs + RXDMA_PTHRESH);
1757
1758	if (readl(gp->regs + GREG_BIFCFG) & GREG_BIFCFG_M66EN)
1759		writel(((5 & RXDMA_BLANK_IPKTS) |
1760			((8 << 12) & RXDMA_BLANK_ITIME)),
1761		       gp->regs + RXDMA_BLANK);
1762	else
1763		writel(((5 & RXDMA_BLANK_IPKTS) |
1764			((4 << 12) & RXDMA_BLANK_ITIME)),
1765		       gp->regs + RXDMA_BLANK);
1766}
1767
1768static u32 gem_setup_multicast(struct gem *gp)
1769{
1770	u32 rxcfg = 0;
1771	int i;
1772
1773	if ((gp->dev->flags & IFF_ALLMULTI) ||
1774	    (netdev_mc_count(gp->dev) > 256)) {
1775	    	for (i=0; i<16; i++)
1776			writel(0xffff, gp->regs + MAC_HASH0 + (i << 2));
1777		rxcfg |= MAC_RXCFG_HFE;
1778	} else if (gp->dev->flags & IFF_PROMISC) {
1779		rxcfg |= MAC_RXCFG_PROM;
1780	} else {
1781		u16 hash_table[16];
1782		u32 crc;
1783		struct netdev_hw_addr *ha;
1784		int i;
1785
1786		memset(hash_table, 0, sizeof(hash_table));
1787		netdev_for_each_mc_addr(ha, gp->dev) {
1788			crc = ether_crc_le(6, ha->addr);
1789			crc >>= 24;
1790			hash_table[crc >> 4] |= 1 << (15 - (crc & 0xf));
1791		}
1792	    	for (i=0; i<16; i++)
1793			writel(hash_table[i], gp->regs + MAC_HASH0 + (i << 2));
1794		rxcfg |= MAC_RXCFG_HFE;
1795	}
1796
1797	return rxcfg;
1798}
1799
1800static void gem_init_mac(struct gem *gp)
1801{
1802	const unsigned char *e = &gp->dev->dev_addr[0];
1803
1804	writel(0x1bf0, gp->regs + MAC_SNDPAUSE);
1805
1806	writel(0x00, gp->regs + MAC_IPG0);
1807	writel(0x08, gp->regs + MAC_IPG1);
1808	writel(0x04, gp->regs + MAC_IPG2);
1809	writel(0x40, gp->regs + MAC_STIME);
1810	writel(0x40, gp->regs + MAC_MINFSZ);
1811
1812	/* Ethernet payload + header + FCS + optional VLAN tag. */
1813	writel(0x20000000 | (gp->rx_buf_sz + 4), gp->regs + MAC_MAXFSZ);
1814
1815	writel(0x07, gp->regs + MAC_PASIZE);
1816	writel(0x04, gp->regs + MAC_JAMSIZE);
1817	writel(0x10, gp->regs + MAC_ATTLIM);
1818	writel(0x8808, gp->regs + MAC_MCTYPE);
1819
1820	writel((e[5] | (e[4] << 8)) & 0x3ff, gp->regs + MAC_RANDSEED);
1821
1822	writel((e[4] << 8) | e[5], gp->regs + MAC_ADDR0);
1823	writel((e[2] << 8) | e[3], gp->regs + MAC_ADDR1);
1824	writel((e[0] << 8) | e[1], gp->regs + MAC_ADDR2);
1825
1826	writel(0, gp->regs + MAC_ADDR3);
1827	writel(0, gp->regs + MAC_ADDR4);
1828	writel(0, gp->regs + MAC_ADDR5);
1829
1830	writel(0x0001, gp->regs + MAC_ADDR6);
1831	writel(0xc200, gp->regs + MAC_ADDR7);
1832	writel(0x0180, gp->regs + MAC_ADDR8);
1833
1834	writel(0, gp->regs + MAC_AFILT0);
1835	writel(0, gp->regs + MAC_AFILT1);
1836	writel(0, gp->regs + MAC_AFILT2);
1837	writel(0, gp->regs + MAC_AF21MSK);
1838	writel(0, gp->regs + MAC_AF0MSK);
1839
1840	gp->mac_rx_cfg = gem_setup_multicast(gp);
1841#ifdef STRIP_FCS
1842	gp->mac_rx_cfg |= MAC_RXCFG_SFCS;
1843#endif
1844	writel(0, gp->regs + MAC_NCOLL);
1845	writel(0, gp->regs + MAC_FASUCC);
1846	writel(0, gp->regs + MAC_ECOLL);
1847	writel(0, gp->regs + MAC_LCOLL);
1848	writel(0, gp->regs + MAC_DTIMER);
1849	writel(0, gp->regs + MAC_PATMPS);
1850	writel(0, gp->regs + MAC_RFCTR);
1851	writel(0, gp->regs + MAC_LERR);
1852	writel(0, gp->regs + MAC_AERR);
1853	writel(0, gp->regs + MAC_FCSERR);
1854	writel(0, gp->regs + MAC_RXCVERR);
1855
1856	/* Clear RX/TX/MAC/XIF config, we will set these up and enable
1857	 * them once a link is established.
1858	 */
1859	writel(0, gp->regs + MAC_TXCFG);
1860	writel(gp->mac_rx_cfg, gp->regs + MAC_RXCFG);
1861	writel(0, gp->regs + MAC_MCCFG);
1862	writel(0, gp->regs + MAC_XIFCFG);
1863
1864	/* Setup MAC interrupts.  We want to get all of the interesting
1865	 * counter expiration events, but we do not want to hear about
1866	 * normal rx/tx as the DMA engine tells us that.
1867	 */
1868	writel(MAC_TXSTAT_XMIT, gp->regs + MAC_TXMASK);
1869	writel(MAC_RXSTAT_RCV, gp->regs + MAC_RXMASK);
1870
1871	/* Don't enable even the PAUSE interrupts for now, we
1872	 * make no use of those events other than to record them.
1873	 */
1874	writel(0xffffffff, gp->regs + MAC_MCMASK);
1875
1876	/* Don't enable GEM's WOL in normal operations
1877	 */
1878	if (gp->has_wol)
1879		writel(0, gp->regs + WOL_WAKECSR);
1880}
1881
1882static void gem_init_pause_thresholds(struct gem *gp)
1883{
1884	u32 cfg;
1885
1886	/* Calculate pause thresholds.  Setting the OFF threshold to the
1887	 * full RX fifo size effectively disables PAUSE generation which
1888	 * is what we do for 10/100 only GEMs which have FIFOs too small
1889	 * to make real gains from PAUSE.
1890	 */
1891	if (gp->rx_fifo_sz <= (2 * 1024)) {
1892		gp->rx_pause_off = gp->rx_pause_on = gp->rx_fifo_sz;
1893	} else {
1894		int max_frame = (gp->rx_buf_sz + 4 + 64) & ~63;
1895		int off = (gp->rx_fifo_sz - (max_frame * 2));
1896		int on = off - max_frame;
1897
1898		gp->rx_pause_off = off;
1899		gp->rx_pause_on = on;
1900	}
1901
1902
1903	/* Configure the chip "burst" DMA mode & enable some
1904	 * HW bug fixes on Apple version
1905	 */
1906	cfg  = 0;
1907	if (gp->pdev->vendor == PCI_VENDOR_ID_APPLE)
1908		cfg |= GREG_CFG_RONPAULBIT | GREG_CFG_ENBUG2FIX;
1909#if !defined(CONFIG_SPARC64) && !defined(CONFIG_ALPHA)
1910	cfg |= GREG_CFG_IBURST;
1911#endif
1912	cfg |= ((31 << 1) & GREG_CFG_TXDMALIM);
1913	cfg |= ((31 << 6) & GREG_CFG_RXDMALIM);
1914	writel(cfg, gp->regs + GREG_CFG);
1915
1916	/* If Infinite Burst didn't stick, then use different
1917	 * thresholds (and Apple bug fixes don't exist)
1918	 */
1919	if (!(readl(gp->regs + GREG_CFG) & GREG_CFG_IBURST)) {
1920		cfg = ((2 << 1) & GREG_CFG_TXDMALIM);
1921		cfg |= ((8 << 6) & GREG_CFG_RXDMALIM);
1922		writel(cfg, gp->regs + GREG_CFG);
1923	}
1924}
1925
1926static int gem_check_invariants(struct gem *gp)
1927{
1928	struct pci_dev *pdev = gp->pdev;
1929	u32 mif_cfg;
1930
1931	/* On Apple's sungem, we can't rely on registers as the chip
1932	 * was been powered down by the firmware. The PHY is looked
1933	 * up later on.
1934	 */
1935	if (pdev->vendor == PCI_VENDOR_ID_APPLE) {
1936		gp->phy_type = phy_mii_mdio0;
1937		gp->tx_fifo_sz = readl(gp->regs + TXDMA_FSZ) * 64;
1938		gp->rx_fifo_sz = readl(gp->regs + RXDMA_FSZ) * 64;
1939		gp->swrst_base = 0;
1940
1941		mif_cfg = readl(gp->regs + MIF_CFG);
1942		mif_cfg &= ~(MIF_CFG_PSELECT|MIF_CFG_POLL|MIF_CFG_BBMODE|MIF_CFG_MDI1);
1943		mif_cfg |= MIF_CFG_MDI0;
1944		writel(mif_cfg, gp->regs + MIF_CFG);
1945		writel(PCS_DMODE_MGM, gp->regs + PCS_DMODE);
1946		writel(MAC_XIFCFG_OE, gp->regs + MAC_XIFCFG);
1947
1948		/* We hard-code the PHY address so we can properly bring it out of
1949		 * reset later on, we can't really probe it at this point, though
1950		 * that isn't an issue.
1951		 */
1952		if (gp->pdev->device == PCI_DEVICE_ID_APPLE_K2_GMAC)
1953			gp->mii_phy_addr = 1;
1954		else
1955			gp->mii_phy_addr = 0;
1956
1957		return 0;
1958	}
1959
1960	mif_cfg = readl(gp->regs + MIF_CFG);
1961
1962	if (pdev->vendor == PCI_VENDOR_ID_SUN &&
1963	    pdev->device == PCI_DEVICE_ID_SUN_RIO_GEM) {
1964		/* One of the MII PHYs _must_ be present
1965		 * as this chip has no gigabit PHY.
1966		 */
1967		if ((mif_cfg & (MIF_CFG_MDI0 | MIF_CFG_MDI1)) == 0) {
1968			pr_err("RIO GEM lacks MII phy, mif_cfg[%08x]\n",
1969			       mif_cfg);
1970			return -1;
1971		}
1972	}
1973
1974	/* Determine initial PHY interface type guess.  MDIO1 is the
1975	 * external PHY and thus takes precedence over MDIO0.
1976	 */
1977
1978	if (mif_cfg & MIF_CFG_MDI1) {
1979		gp->phy_type = phy_mii_mdio1;
1980		mif_cfg |= MIF_CFG_PSELECT;
1981		writel(mif_cfg, gp->regs + MIF_CFG);
1982	} else if (mif_cfg & MIF_CFG_MDI0) {
1983		gp->phy_type = phy_mii_mdio0;
1984		mif_cfg &= ~MIF_CFG_PSELECT;
1985		writel(mif_cfg, gp->regs + MIF_CFG);
1986	} else {
1987#ifdef CONFIG_SPARC
1988		const char *p;
1989
1990		p = of_get_property(gp->of_node, "shared-pins", NULL);
1991		if (p && !strcmp(p, "serdes"))
1992			gp->phy_type = phy_serdes;
1993		else
1994#endif
1995			gp->phy_type = phy_serialink;
1996	}
1997	if (gp->phy_type == phy_mii_mdio1 ||
1998	    gp->phy_type == phy_mii_mdio0) {
1999		int i;
2000
2001		for (i = 0; i < 32; i++) {
2002			gp->mii_phy_addr = i;
2003			if (sungem_phy_read(gp, MII_BMCR) != 0xffff)
2004				break;
2005		}
2006		if (i == 32) {
2007			if (pdev->device != PCI_DEVICE_ID_SUN_GEM) {
2008				pr_err("RIO MII phy will not respond\n");
2009				return -1;
2010			}
2011			gp->phy_type = phy_serdes;
2012		}
2013	}
2014
2015	/* Fetch the FIFO configurations now too. */
2016	gp->tx_fifo_sz = readl(gp->regs + TXDMA_FSZ) * 64;
2017	gp->rx_fifo_sz = readl(gp->regs + RXDMA_FSZ) * 64;
2018
2019	if (pdev->vendor == PCI_VENDOR_ID_SUN) {
2020		if (pdev->device == PCI_DEVICE_ID_SUN_GEM) {
2021			if (gp->tx_fifo_sz != (9 * 1024) ||
2022			    gp->rx_fifo_sz != (20 * 1024)) {
2023				pr_err("GEM has bogus fifo sizes tx(%d) rx(%d)\n",
2024				       gp->tx_fifo_sz, gp->rx_fifo_sz);
2025				return -1;
2026			}
2027			gp->swrst_base = 0;
2028		} else {
2029			if (gp->tx_fifo_sz != (2 * 1024) ||
2030			    gp->rx_fifo_sz != (2 * 1024)) {
2031				pr_err("RIO GEM has bogus fifo sizes tx(%d) rx(%d)\n",
2032				       gp->tx_fifo_sz, gp->rx_fifo_sz);
2033				return -1;
2034			}
2035			gp->swrst_base = (64 / 4) << GREG_SWRST_CACHE_SHIFT;
2036		}
2037	}
2038
2039	return 0;
2040}
2041
2042static void gem_reinit_chip(struct gem *gp)
2043{
2044	/* Reset the chip */
2045	gem_reset(gp);
2046
2047	/* Make sure ints are disabled */
2048	gem_disable_ints(gp);
2049
2050	/* Allocate & setup ring buffers */
2051	gem_init_rings(gp);
2052
2053	/* Configure pause thresholds */
2054	gem_init_pause_thresholds(gp);
2055
2056	/* Init DMA & MAC engines */
2057	gem_init_dma(gp);
2058	gem_init_mac(gp);
2059}
2060
2061
2062static void gem_stop_phy(struct gem *gp, int wol)
2063{
2064	u32 mifcfg;
2065
2066	/* Let the chip settle down a bit, it seems that helps
2067	 * for sleep mode on some models
2068	 */
2069	msleep(10);
2070
2071	/* Make sure we aren't polling PHY status change. We
2072	 * don't currently use that feature though
2073	 */
2074	mifcfg = readl(gp->regs + MIF_CFG);
2075	mifcfg &= ~MIF_CFG_POLL;
2076	writel(mifcfg, gp->regs + MIF_CFG);
2077
2078	if (wol && gp->has_wol) {
2079		const unsigned char *e = &gp->dev->dev_addr[0];
2080		u32 csr;
2081
2082		/* Setup wake-on-lan for MAGIC packet */
2083		writel(MAC_RXCFG_HFE | MAC_RXCFG_SFCS | MAC_RXCFG_ENAB,
2084		       gp->regs + MAC_RXCFG);
2085		writel((e[4] << 8) | e[5], gp->regs + WOL_MATCH0);
2086		writel((e[2] << 8) | e[3], gp->regs + WOL_MATCH1);
2087		writel((e[0] << 8) | e[1], gp->regs + WOL_MATCH2);
2088
2089		writel(WOL_MCOUNT_N | WOL_MCOUNT_M, gp->regs + WOL_MCOUNT);
2090		csr = WOL_WAKECSR_ENABLE;
2091		if ((readl(gp->regs + MAC_XIFCFG) & MAC_XIFCFG_GMII) == 0)
2092			csr |= WOL_WAKECSR_MII;
2093		writel(csr, gp->regs + WOL_WAKECSR);
2094	} else {
2095		writel(0, gp->regs + MAC_RXCFG);
2096		(void)readl(gp->regs + MAC_RXCFG);
2097		/* Machine sleep will die in strange ways if we
2098		 * dont wait a bit here, looks like the chip takes
2099		 * some time to really shut down
2100		 */
2101		msleep(10);
2102	}
2103
2104	writel(0, gp->regs + MAC_TXCFG);
2105	writel(0, gp->regs + MAC_XIFCFG);
2106	writel(0, gp->regs + TXDMA_CFG);
2107	writel(0, gp->regs + RXDMA_CFG);
2108
2109	if (!wol) {
2110		gem_reset(gp);
2111		writel(MAC_TXRST_CMD, gp->regs + MAC_TXRST);
2112		writel(MAC_RXRST_CMD, gp->regs + MAC_RXRST);
2113
2114		if (found_mii_phy(gp) && gp->phy_mii.def->ops->suspend)
2115			gp->phy_mii.def->ops->suspend(&gp->phy_mii);
2116
2117		/* According to Apple, we must set the MDIO pins to this begnign
2118		 * state or we may 1) eat more current, 2) damage some PHYs
2119		 */
2120		writel(mifcfg | MIF_CFG_BBMODE, gp->regs + MIF_CFG);
2121		writel(0, gp->regs + MIF_BBCLK);
2122		writel(0, gp->regs + MIF_BBDATA);
2123		writel(0, gp->regs + MIF_BBOENAB);
2124		writel(MAC_XIFCFG_GMII | MAC_XIFCFG_LBCK, gp->regs + MAC_XIFCFG);
2125		(void) readl(gp->regs + MAC_XIFCFG);
2126	}
2127}
2128
2129static int gem_do_start(struct net_device *dev)
2130{
2131	struct gem *gp = netdev_priv(dev);
2132	int rc;
2133
 
 
 
 
 
 
 
 
 
 
 
 
 
 
2134	pci_set_master(gp->pdev);
2135
2136	/* Init & setup chip hardware */
2137	gem_reinit_chip(gp);
2138
2139	/* An interrupt might come in handy */
2140	rc = request_irq(gp->pdev->irq, gem_interrupt,
2141			 IRQF_SHARED, dev->name, (void *)dev);
2142	if (rc) {
2143		netdev_err(dev, "failed to request irq !\n");
2144
2145		gem_reset(gp);
2146		gem_clean_rings(gp);
2147		gem_put_cell(gp);
2148		return rc;
2149	}
2150
2151	/* Mark us as attached again if we come from resume(), this has
2152	 * no effect if we weren't detached and needs to be done now.
2153	 */
2154	netif_device_attach(dev);
2155
2156	/* Restart NAPI & queues */
2157	gem_netif_start(gp);
2158
2159	/* Detect & init PHY, start autoneg etc... this will
2160	 * eventually result in starting DMA operations when
2161	 * the link is up
2162	 */
2163	gem_init_phy(gp);
2164
2165	return 0;
2166}
2167
2168static void gem_do_stop(struct net_device *dev, int wol)
2169{
2170	struct gem *gp = netdev_priv(dev);
2171
2172	/* Stop NAPI and stop tx queue */
2173	gem_netif_stop(gp);
2174
2175	/* Make sure ints are disabled. We don't care about
2176	 * synchronizing as NAPI is disabled, thus a stray
2177	 * interrupt will do nothing bad (our irq handler
2178	 * just schedules NAPI)
2179	 */
2180	gem_disable_ints(gp);
2181
2182	/* Stop the link timer */
2183	del_timer_sync(&gp->link_timer);
2184
2185	/* We cannot cancel the reset task while holding the
2186	 * rtnl lock, we'd get an A->B / B->A deadlock stituation
2187	 * if we did. This is not an issue however as the reset
2188	 * task is synchronized vs. us (rtnl_lock) and will do
2189	 * nothing if the device is down or suspended. We do
2190	 * still clear reset_task_pending to avoid a spurrious
2191	 * reset later on in case we do resume before it gets
2192	 * scheduled.
2193	 */
2194	gp->reset_task_pending = 0;
2195
2196	/* If we are going to sleep with WOL */
2197	gem_stop_dma(gp);
2198	msleep(10);
2199	if (!wol)
2200		gem_reset(gp);
2201	msleep(10);
2202
2203	/* Get rid of rings */
2204	gem_clean_rings(gp);
2205
2206	/* No irq needed anymore */
2207	free_irq(gp->pdev->irq, (void *) dev);
2208
2209	/* Shut the PHY down eventually and setup WOL */
2210	gem_stop_phy(gp, wol);
 
 
 
 
 
 
 
2211}
2212
2213static void gem_reset_task(struct work_struct *work)
2214{
2215	struct gem *gp = container_of(work, struct gem, reset_task);
2216
2217	/* Lock out the network stack (essentially shield ourselves
2218	 * against a racing open, close, control call, or suspend
2219	 */
2220	rtnl_lock();
2221
2222	/* Skip the reset task if suspended or closed, or if it's
2223	 * been cancelled by gem_do_stop (see comment there)
2224	 */
2225	if (!netif_device_present(gp->dev) ||
2226	    !netif_running(gp->dev) ||
2227	    !gp->reset_task_pending) {
2228		rtnl_unlock();
2229		return;
2230	}
2231
2232	/* Stop the link timer */
2233	del_timer_sync(&gp->link_timer);
2234
2235	/* Stop NAPI and tx */
2236	gem_netif_stop(gp);
2237
2238	/* Reset the chip & rings */
2239	gem_reinit_chip(gp);
2240	if (gp->lstate == link_up)
2241		gem_set_link_modes(gp);
2242
2243	/* Restart NAPI and Tx */
2244	gem_netif_start(gp);
2245
2246	/* We are back ! */
2247	gp->reset_task_pending = 0;
2248
2249	/* If the link is not up, restart autoneg, else restart the
2250	 * polling timer
2251	 */
2252	if (gp->lstate != link_up)
2253		gem_begin_auto_negotiation(gp, NULL);
2254	else
2255		mod_timer(&gp->link_timer, jiffies + ((12 * HZ) / 10));
2256
2257	rtnl_unlock();
2258}
2259
2260static int gem_open(struct net_device *dev)
2261{
2262	struct gem *gp = netdev_priv(dev);
2263	int rc;
2264
2265	/* We allow open while suspended, we just do nothing,
2266	 * the chip will be initialized in resume()
2267	 */
2268	if (netif_device_present(dev)) {
2269		/* Enable the cell */
2270		gem_get_cell(gp);
2271
2272		/* Make sure PCI access and bus master are enabled */
2273		rc = pci_enable_device(gp->pdev);
2274		if (rc) {
2275			netdev_err(dev, "Failed to enable chip on PCI bus !\n");
2276
2277			/* Put cell and forget it for now, it will be considered
2278			 *as still asleep, a new sleep cycle may bring it back
2279			 */
2280			gem_put_cell(gp);
2281			return -ENXIO;
2282		}
2283		return gem_do_start(dev);
2284	}
2285
2286	return 0;
2287}
2288
2289static int gem_close(struct net_device *dev)
2290{
2291	struct gem *gp = netdev_priv(dev);
2292
2293	if (netif_device_present(dev)) {
2294		gem_do_stop(dev, 0);
2295
2296		/* Make sure bus master is disabled */
2297		pci_disable_device(gp->pdev);
2298
2299		/* Cell not needed neither if no WOL */
2300		if (!gp->asleep_wol)
2301			gem_put_cell(gp);
2302	}
2303	return 0;
2304}
2305
2306static int __maybe_unused gem_suspend(struct device *dev_d)
 
2307{
2308	struct net_device *dev = dev_get_drvdata(dev_d);
2309	struct gem *gp = netdev_priv(dev);
2310
2311	/* Lock the network stack first to avoid racing with open/close,
2312	 * reset task and setting calls
2313	 */
2314	rtnl_lock();
2315
2316	/* Not running, mark ourselves non-present, no need for
2317	 * a lock here
2318	 */
2319	if (!netif_running(dev)) {
2320		netif_device_detach(dev);
2321		rtnl_unlock();
2322		return 0;
2323	}
2324	netdev_info(dev, "suspending, WakeOnLan %s\n",
2325		    (gp->wake_on_lan && netif_running(dev)) ?
2326		    "enabled" : "disabled");
2327
2328	/* Tell the network stack we're gone. gem_do_stop() below will
2329	 * synchronize with TX, stop NAPI etc...
2330	 */
2331	netif_device_detach(dev);
2332
2333	/* Switch off chip, remember WOL setting */
2334	gp->asleep_wol = !!gp->wake_on_lan;
2335	gem_do_stop(dev, gp->asleep_wol);
2336
2337	/* Cell not needed neither if no WOL */
2338	if (!gp->asleep_wol)
2339		gem_put_cell(gp);
2340
2341	/* Unlock the network stack */
2342	rtnl_unlock();
2343
2344	return 0;
2345}
2346
2347static int __maybe_unused gem_resume(struct device *dev_d)
2348{
2349	struct net_device *dev = dev_get_drvdata(dev_d);
2350	struct gem *gp = netdev_priv(dev);
2351
2352	/* See locking comment in gem_suspend */
2353	rtnl_lock();
2354
2355	/* Not running, mark ourselves present, no need for
2356	 * a lock here
2357	 */
2358	if (!netif_running(dev)) {
2359		netif_device_attach(dev);
2360		rtnl_unlock();
2361		return 0;
2362	}
2363
2364	/* Enable the cell */
2365	gem_get_cell(gp);
2366
2367	/* Restart chip. If that fails there isn't much we can do, we
2368	 * leave things stopped.
2369	 */
2370	gem_do_start(dev);
2371
2372	/* If we had WOL enabled, the cell clock was never turned off during
2373	 * sleep, so we end up beeing unbalanced. Fix that here
2374	 */
2375	if (gp->asleep_wol)
2376		gem_put_cell(gp);
2377
2378	/* Unlock the network stack */
2379	rtnl_unlock();
2380
2381	return 0;
2382}
 
2383
2384static struct net_device_stats *gem_get_stats(struct net_device *dev)
2385{
2386	struct gem *gp = netdev_priv(dev);
2387
2388	/* I have seen this being called while the PM was in progress,
2389	 * so we shield against this. Let's also not poke at registers
2390	 * while the reset task is going on.
2391	 *
2392	 * TODO: Move stats collection elsewhere (link timer ?) and
2393	 * make this a nop to avoid all those synchro issues
2394	 */
2395	if (!netif_device_present(dev) || !netif_running(dev))
2396		goto bail;
2397
2398	/* Better safe than sorry... */
2399	if (WARN_ON(!gp->cell_enabled))
2400		goto bail;
2401
2402	dev->stats.rx_crc_errors += readl(gp->regs + MAC_FCSERR);
2403	writel(0, gp->regs + MAC_FCSERR);
2404
2405	dev->stats.rx_frame_errors += readl(gp->regs + MAC_AERR);
2406	writel(0, gp->regs + MAC_AERR);
2407
2408	dev->stats.rx_length_errors += readl(gp->regs + MAC_LERR);
2409	writel(0, gp->regs + MAC_LERR);
2410
2411	dev->stats.tx_aborted_errors += readl(gp->regs + MAC_ECOLL);
2412	dev->stats.collisions +=
2413		(readl(gp->regs + MAC_ECOLL) + readl(gp->regs + MAC_LCOLL));
2414	writel(0, gp->regs + MAC_ECOLL);
2415	writel(0, gp->regs + MAC_LCOLL);
2416 bail:
2417	return &dev->stats;
2418}
2419
2420static int gem_set_mac_address(struct net_device *dev, void *addr)
2421{
2422	struct sockaddr *macaddr = (struct sockaddr *) addr;
2423	const unsigned char *e = &dev->dev_addr[0];
2424	struct gem *gp = netdev_priv(dev);
 
2425
2426	if (!is_valid_ether_addr(macaddr->sa_data))
2427		return -EADDRNOTAVAIL;
2428
2429	eth_hw_addr_set(dev, macaddr->sa_data);
2430
2431	/* We'll just catch it later when the device is up'd or resumed */
2432	if (!netif_running(dev) || !netif_device_present(dev))
2433		return 0;
2434
2435	/* Better safe than sorry... */
2436	if (WARN_ON(!gp->cell_enabled))
2437		return 0;
2438
2439	writel((e[4] << 8) | e[5], gp->regs + MAC_ADDR0);
2440	writel((e[2] << 8) | e[3], gp->regs + MAC_ADDR1);
2441	writel((e[0] << 8) | e[1], gp->regs + MAC_ADDR2);
2442
2443	return 0;
2444}
2445
2446static void gem_set_multicast(struct net_device *dev)
2447{
2448	struct gem *gp = netdev_priv(dev);
2449	u32 rxcfg, rxcfg_new;
2450	int limit = 10000;
2451
2452	if (!netif_running(dev) || !netif_device_present(dev))
2453		return;
2454
2455	/* Better safe than sorry... */
2456	if (gp->reset_task_pending || WARN_ON(!gp->cell_enabled))
2457		return;
2458
2459	rxcfg = readl(gp->regs + MAC_RXCFG);
2460	rxcfg_new = gem_setup_multicast(gp);
2461#ifdef STRIP_FCS
2462	rxcfg_new |= MAC_RXCFG_SFCS;
2463#endif
2464	gp->mac_rx_cfg = rxcfg_new;
2465
2466	writel(rxcfg & ~MAC_RXCFG_ENAB, gp->regs + MAC_RXCFG);
2467	while (readl(gp->regs + MAC_RXCFG) & MAC_RXCFG_ENAB) {
2468		if (!limit--)
2469			break;
2470		udelay(10);
2471	}
2472
2473	rxcfg &= ~(MAC_RXCFG_PROM | MAC_RXCFG_HFE);
2474	rxcfg |= rxcfg_new;
2475
2476	writel(rxcfg, gp->regs + MAC_RXCFG);
2477}
2478
2479/* Jumbo-grams don't seem to work :-( */
2480#define GEM_MIN_MTU	ETH_MIN_MTU
2481#if 1
2482#define GEM_MAX_MTU	ETH_DATA_LEN
2483#else
2484#define GEM_MAX_MTU	9000
2485#endif
2486
2487static int gem_change_mtu(struct net_device *dev, int new_mtu)
2488{
2489	struct gem *gp = netdev_priv(dev);
2490
2491	WRITE_ONCE(dev->mtu, new_mtu);
 
 
 
2492
2493	/* We'll just catch it later when the device is up'd or resumed */
2494	if (!netif_running(dev) || !netif_device_present(dev))
2495		return 0;
2496
2497	/* Better safe than sorry... */
2498	if (WARN_ON(!gp->cell_enabled))
2499		return 0;
2500
2501	gem_netif_stop(gp);
2502	gem_reinit_chip(gp);
2503	if (gp->lstate == link_up)
2504		gem_set_link_modes(gp);
2505	gem_netif_start(gp);
2506
2507	return 0;
2508}
2509
2510static void gem_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
2511{
2512	struct gem *gp = netdev_priv(dev);
2513
2514	strscpy(info->driver, DRV_NAME, sizeof(info->driver));
2515	strscpy(info->version, DRV_VERSION, sizeof(info->version));
2516	strscpy(info->bus_info, pci_name(gp->pdev), sizeof(info->bus_info));
2517}
2518
2519static int gem_get_link_ksettings(struct net_device *dev,
2520				  struct ethtool_link_ksettings *cmd)
2521{
2522	struct gem *gp = netdev_priv(dev);
2523	u32 supported, advertising;
2524
2525	if (gp->phy_type == phy_mii_mdio0 ||
2526	    gp->phy_type == phy_mii_mdio1) {
2527		if (gp->phy_mii.def)
2528			supported = gp->phy_mii.def->features;
2529		else
2530			supported = (SUPPORTED_10baseT_Half |
2531					  SUPPORTED_10baseT_Full);
2532
2533		/* XXX hardcoded stuff for now */
2534		cmd->base.port = PORT_MII;
2535		cmd->base.phy_address = 0; /* XXX fixed PHYAD */
 
2536
2537		/* Return current PHY settings */
2538		cmd->base.autoneg = gp->want_autoneg;
2539		cmd->base.speed = gp->phy_mii.speed;
2540		cmd->base.duplex = gp->phy_mii.duplex;
2541		advertising = gp->phy_mii.advertising;
2542
2543		/* If we started with a forced mode, we don't have a default
2544		 * advertise set, we need to return something sensible so
2545		 * userland can re-enable autoneg properly.
2546		 */
2547		if (advertising == 0)
2548			advertising = supported;
2549	} else { // XXX PCS ?
2550		supported =
2551			(SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full |
2552			 SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full |
2553			 SUPPORTED_Autoneg);
2554		advertising = supported;
2555		cmd->base.speed = 0;
2556		cmd->base.duplex = 0;
2557		cmd->base.port = 0;
2558		cmd->base.phy_address = 0;
2559		cmd->base.autoneg = 0;
2560
2561		/* serdes means usually a Fibre connector, with most fixed */
2562		if (gp->phy_type == phy_serdes) {
2563			cmd->base.port = PORT_FIBRE;
2564			supported = (SUPPORTED_1000baseT_Half |
2565				SUPPORTED_1000baseT_Full |
2566				SUPPORTED_FIBRE | SUPPORTED_Autoneg |
2567				SUPPORTED_Pause | SUPPORTED_Asym_Pause);
2568			advertising = supported;
 
2569			if (gp->lstate == link_up)
2570				cmd->base.speed = SPEED_1000;
2571			cmd->base.duplex = DUPLEX_FULL;
2572			cmd->base.autoneg = 1;
2573		}
2574	}
2575
2576	ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.supported,
2577						supported);
2578	ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.advertising,
2579						advertising);
2580
2581	return 0;
2582}
2583
2584static int gem_set_link_ksettings(struct net_device *dev,
2585				  const struct ethtool_link_ksettings *cmd)
2586{
2587	struct gem *gp = netdev_priv(dev);
2588	u32 speed = cmd->base.speed;
2589	u32 advertising;
2590
2591	ethtool_convert_link_mode_to_legacy_u32(&advertising,
2592						cmd->link_modes.advertising);
2593
2594	/* Verify the settings we care about. */
2595	if (cmd->base.autoneg != AUTONEG_ENABLE &&
2596	    cmd->base.autoneg != AUTONEG_DISABLE)
2597		return -EINVAL;
2598
2599	if (cmd->base.autoneg == AUTONEG_ENABLE &&
2600	    advertising == 0)
2601		return -EINVAL;
2602
2603	if (cmd->base.autoneg == AUTONEG_DISABLE &&
2604	    ((speed != SPEED_1000 &&
2605	      speed != SPEED_100 &&
2606	      speed != SPEED_10) ||
2607	     (cmd->base.duplex != DUPLEX_HALF &&
2608	      cmd->base.duplex != DUPLEX_FULL)))
2609		return -EINVAL;
2610
2611	/* Apply settings and restart link process. */
2612	if (netif_device_present(gp->dev)) {
2613		del_timer_sync(&gp->link_timer);
2614		gem_begin_auto_negotiation(gp, cmd);
2615	}
2616
2617	return 0;
2618}
2619
2620static int gem_nway_reset(struct net_device *dev)
2621{
2622	struct gem *gp = netdev_priv(dev);
2623
2624	if (!gp->want_autoneg)
2625		return -EINVAL;
2626
2627	/* Restart link process  */
2628	if (netif_device_present(gp->dev)) {
2629		del_timer_sync(&gp->link_timer);
2630		gem_begin_auto_negotiation(gp, NULL);
2631	}
2632
2633	return 0;
2634}
2635
2636static u32 gem_get_msglevel(struct net_device *dev)
2637{
2638	struct gem *gp = netdev_priv(dev);
2639	return gp->msg_enable;
2640}
2641
2642static void gem_set_msglevel(struct net_device *dev, u32 value)
2643{
2644	struct gem *gp = netdev_priv(dev);
2645	gp->msg_enable = value;
2646}
2647
2648
2649/* Add more when I understand how to program the chip */
2650/* like WAKE_UCAST | WAKE_MCAST | WAKE_BCAST */
2651
2652#define WOL_SUPPORTED_MASK	(WAKE_MAGIC)
2653
2654static void gem_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2655{
2656	struct gem *gp = netdev_priv(dev);
2657
2658	/* Add more when I understand how to program the chip */
2659	if (gp->has_wol) {
2660		wol->supported = WOL_SUPPORTED_MASK;
2661		wol->wolopts = gp->wake_on_lan;
2662	} else {
2663		wol->supported = 0;
2664		wol->wolopts = 0;
2665	}
2666}
2667
2668static int gem_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2669{
2670	struct gem *gp = netdev_priv(dev);
2671
2672	if (!gp->has_wol)
2673		return -EOPNOTSUPP;
2674	gp->wake_on_lan = wol->wolopts & WOL_SUPPORTED_MASK;
2675	return 0;
2676}
2677
2678static const struct ethtool_ops gem_ethtool_ops = {
2679	.get_drvinfo		= gem_get_drvinfo,
2680	.get_link		= ethtool_op_get_link,
 
 
2681	.nway_reset		= gem_nway_reset,
2682	.get_msglevel		= gem_get_msglevel,
2683	.set_msglevel		= gem_set_msglevel,
2684	.get_wol		= gem_get_wol,
2685	.set_wol		= gem_set_wol,
2686	.get_link_ksettings	= gem_get_link_ksettings,
2687	.set_link_ksettings	= gem_set_link_ksettings,
2688};
2689
2690static int gem_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2691{
2692	struct gem *gp = netdev_priv(dev);
2693	struct mii_ioctl_data *data = if_mii(ifr);
2694	int rc = -EOPNOTSUPP;
2695
2696	/* For SIOCGMIIREG and SIOCSMIIREG the core checks for us that
2697	 * netif_device_present() is true and holds rtnl_lock for us
2698	 * so we have nothing to worry about
2699	 */
2700
2701	switch (cmd) {
2702	case SIOCGMIIPHY:		/* Get address of MII PHY in use. */
2703		data->phy_id = gp->mii_phy_addr;
2704		fallthrough;
2705
2706	case SIOCGMIIREG:		/* Read MII PHY register. */
2707		data->val_out = __sungem_phy_read(gp, data->phy_id & 0x1f,
2708					   data->reg_num & 0x1f);
2709		rc = 0;
2710		break;
2711
2712	case SIOCSMIIREG:		/* Write MII PHY register. */
2713		__sungem_phy_write(gp, data->phy_id & 0x1f, data->reg_num & 0x1f,
2714			    data->val_in);
2715		rc = 0;
2716		break;
2717	}
2718	return rc;
2719}
2720
2721#if (!defined(CONFIG_SPARC) && !defined(CONFIG_PPC_PMAC))
2722/* Fetch MAC address from vital product data of PCI ROM. */
2723static int find_eth_addr_in_vpd(void __iomem *rom_base, int len, unsigned char *dev_addr)
2724{
2725	int this_offset;
2726
2727	for (this_offset = 0x20; this_offset < len; this_offset++) {
2728		void __iomem *p = rom_base + this_offset;
2729		int i;
2730
2731		if (readb(p + 0) != 0x90 ||
2732		    readb(p + 1) != 0x00 ||
2733		    readb(p + 2) != 0x09 ||
2734		    readb(p + 3) != 0x4e ||
2735		    readb(p + 4) != 0x41 ||
2736		    readb(p + 5) != 0x06)
2737			continue;
2738
2739		this_offset += 6;
2740		p += 6;
2741
2742		for (i = 0; i < 6; i++)
2743			dev_addr[i] = readb(p + i);
2744		return 1;
2745	}
2746	return 0;
2747}
2748
2749static void get_gem_mac_nonobp(struct pci_dev *pdev, unsigned char *dev_addr)
2750{
2751	size_t size;
2752	void __iomem *p = pci_map_rom(pdev, &size);
2753
2754	if (p) {
2755		int found;
2756
2757		found = readb(p) == 0x55 &&
2758			readb(p + 1) == 0xaa &&
2759			find_eth_addr_in_vpd(p, (64 * 1024), dev_addr);
2760		pci_unmap_rom(pdev, p);
2761		if (found)
2762			return;
2763	}
2764
2765	/* Sun MAC prefix then 3 random bytes. */
2766	dev_addr[0] = 0x08;
2767	dev_addr[1] = 0x00;
2768	dev_addr[2] = 0x20;
2769	get_random_bytes(dev_addr + 3, 3);
2770}
2771#endif /* not Sparc and not PPC */
2772
2773static int gem_get_device_address(struct gem *gp)
2774{
2775#if defined(CONFIG_SPARC) || defined(CONFIG_PPC_PMAC)
2776	struct net_device *dev = gp->dev;
2777	const unsigned char *addr;
2778
2779	addr = of_get_property(gp->of_node, "local-mac-address", NULL);
2780	if (addr == NULL) {
2781#ifdef CONFIG_SPARC
2782		addr = idprom->id_ethaddr;
2783#else
2784		printk("\n");
2785		pr_err("%s: can't get mac-address\n", dev->name);
2786		return -1;
2787#endif
2788	}
2789	eth_hw_addr_set(dev, addr);
2790#else
2791	u8 addr[ETH_ALEN];
2792
2793	get_gem_mac_nonobp(gp->pdev, addr);
2794	eth_hw_addr_set(gp->dev, addr);
2795#endif
2796	return 0;
2797}
2798
2799static void gem_remove_one(struct pci_dev *pdev)
2800{
2801	struct net_device *dev = pci_get_drvdata(pdev);
2802
2803	if (dev) {
2804		struct gem *gp = netdev_priv(dev);
2805
2806		unregister_netdev(dev);
2807
2808		/* Ensure reset task is truly gone */
2809		cancel_work_sync(&gp->reset_task);
2810
2811		/* Free resources */
2812		dma_free_coherent(&pdev->dev, sizeof(struct gem_init_block),
2813				  gp->init_block, gp->gblock_dvma);
 
 
2814		iounmap(gp->regs);
2815		pci_release_regions(pdev);
2816		free_netdev(dev);
2817	}
2818}
2819
2820static const struct net_device_ops gem_netdev_ops = {
2821	.ndo_open		= gem_open,
2822	.ndo_stop		= gem_close,
2823	.ndo_start_xmit		= gem_start_xmit,
2824	.ndo_get_stats		= gem_get_stats,
2825	.ndo_set_rx_mode	= gem_set_multicast,
2826	.ndo_eth_ioctl		= gem_ioctl,
2827	.ndo_tx_timeout		= gem_tx_timeout,
2828	.ndo_change_mtu		= gem_change_mtu,
2829	.ndo_validate_addr	= eth_validate_addr,
2830	.ndo_set_mac_address    = gem_set_mac_address,
 
 
 
2831};
2832
2833static int gem_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
2834{
2835	unsigned long gemreg_base, gemreg_len;
2836	struct net_device *dev;
2837	struct gem *gp;
2838	int err, pci_using_dac;
2839
2840	printk_once(KERN_INFO "%s", version);
2841
2842	/* Apple gmac note: during probe, the chip is powered up by
2843	 * the arch code to allow the code below to work (and to let
2844	 * the chip be probed on the config space. It won't stay powered
2845	 * up until the interface is brought up however, so we can't rely
2846	 * on register configuration done at this point.
2847	 */
2848	err = pci_enable_device(pdev);
2849	if (err) {
2850		pr_err("Cannot enable MMIO operation, aborting\n");
2851		return err;
2852	}
2853	pci_set_master(pdev);
2854
2855	/* Configure DMA attributes. */
2856
2857	/* All of the GEM documentation states that 64-bit DMA addressing
2858	 * is fully supported and should work just fine.  However the
2859	 * front end for RIO based GEMs is different and only supports
2860	 * 32-bit addressing.
2861	 *
2862	 * For now we assume the various PPC GEMs are 32-bit only as well.
2863	 */
2864	if (pdev->vendor == PCI_VENDOR_ID_SUN &&
2865	    pdev->device == PCI_DEVICE_ID_SUN_GEM &&
2866	    !dma_set_mask(&pdev->dev, DMA_BIT_MASK(64))) {
2867		pci_using_dac = 1;
2868	} else {
2869		err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
2870		if (err) {
2871			pr_err("No usable DMA configuration, aborting\n");
2872			goto err_disable_device;
2873		}
2874		pci_using_dac = 0;
2875	}
2876
2877	gemreg_base = pci_resource_start(pdev, 0);
2878	gemreg_len = pci_resource_len(pdev, 0);
2879
2880	if ((pci_resource_flags(pdev, 0) & IORESOURCE_IO) != 0) {
2881		pr_err("Cannot find proper PCI device base address, aborting\n");
2882		err = -ENODEV;
2883		goto err_disable_device;
2884	}
2885
2886	dev = alloc_etherdev(sizeof(*gp));
2887	if (!dev) {
2888		err = -ENOMEM;
2889		goto err_disable_device;
2890	}
2891	SET_NETDEV_DEV(dev, &pdev->dev);
2892
2893	gp = netdev_priv(dev);
2894
2895	err = pci_request_regions(pdev, DRV_NAME);
2896	if (err) {
2897		pr_err("Cannot obtain PCI resources, aborting\n");
2898		goto err_out_free_netdev;
2899	}
2900
2901	gp->pdev = pdev;
2902	gp->dev = dev;
2903
2904	gp->msg_enable = DEFAULT_MSG;
2905
2906	timer_setup(&gp->link_timer, gem_link_timer, 0);
 
 
2907
2908	INIT_WORK(&gp->reset_task, gem_reset_task);
2909
2910	gp->lstate = link_down;
2911	gp->timer_ticks = 0;
2912	netif_carrier_off(dev);
2913
2914	gp->regs = ioremap(gemreg_base, gemreg_len);
2915	if (!gp->regs) {
2916		pr_err("Cannot map device registers, aborting\n");
2917		err = -EIO;
2918		goto err_out_free_res;
2919	}
2920
2921	/* On Apple, we want a reference to the Open Firmware device-tree
2922	 * node. We use it for clock control.
2923	 */
2924#if defined(CONFIG_PPC_PMAC) || defined(CONFIG_SPARC)
2925	gp->of_node = pci_device_to_OF_node(pdev);
2926#endif
2927
2928	/* Only Apple version supports WOL afaik */
2929	if (pdev->vendor == PCI_VENDOR_ID_APPLE)
2930		gp->has_wol = 1;
2931
2932	/* Make sure cell is enabled */
2933	gem_get_cell(gp);
2934
2935	/* Make sure everything is stopped and in init state */
2936	gem_reset(gp);
2937
2938	/* Fill up the mii_phy structure (even if we won't use it) */
2939	gp->phy_mii.dev = dev;
2940	gp->phy_mii.mdio_read = _sungem_phy_read;
2941	gp->phy_mii.mdio_write = _sungem_phy_write;
2942#ifdef CONFIG_PPC_PMAC
2943	gp->phy_mii.platform_data = gp->of_node;
2944#endif
2945	/* By default, we start with autoneg */
2946	gp->want_autoneg = 1;
2947
2948	/* Check fifo sizes, PHY type, etc... */
2949	if (gem_check_invariants(gp)) {
2950		err = -ENODEV;
2951		goto err_out_iounmap;
2952	}
2953
2954	/* It is guaranteed that the returned buffer will be at least
2955	 * PAGE_SIZE aligned.
2956	 */
2957	gp->init_block = dma_alloc_coherent(&pdev->dev, sizeof(struct gem_init_block),
2958					    &gp->gblock_dvma, GFP_KERNEL);
 
2959	if (!gp->init_block) {
2960		pr_err("Cannot allocate init block, aborting\n");
2961		err = -ENOMEM;
2962		goto err_out_iounmap;
2963	}
2964
2965	err = gem_get_device_address(gp);
2966	if (err)
2967		goto err_out_free_consistent;
2968
2969	dev->netdev_ops = &gem_netdev_ops;
2970	netif_napi_add(dev, &gp->napi, gem_poll);
2971	dev->ethtool_ops = &gem_ethtool_ops;
2972	dev->watchdog_timeo = 5 * HZ;
2973	dev->dma = 0;
2974
2975	/* Set that now, in case PM kicks in now */
2976	pci_set_drvdata(pdev, dev);
2977
2978	/* We can do scatter/gather and HW checksum */
2979	dev->hw_features = NETIF_F_SG | NETIF_F_HW_CSUM | NETIF_F_RXCSUM;
2980	dev->features = dev->hw_features;
2981	if (pci_using_dac)
2982		dev->features |= NETIF_F_HIGHDMA;
2983
2984	/* MTU range: 68 - 1500 (Jumbo mode is broken) */
2985	dev->min_mtu = GEM_MIN_MTU;
2986	dev->max_mtu = GEM_MAX_MTU;
2987
2988	/* Register with kernel */
2989	if (register_netdev(dev)) {
2990		pr_err("Cannot register net device, aborting\n");
2991		err = -ENOMEM;
2992		goto err_out_free_consistent;
2993	}
2994
2995	/* Undo the get_cell with appropriate locking (we could use
2996	 * ndo_init/uninit but that would be even more clumsy imho)
2997	 */
2998	rtnl_lock();
2999	gem_put_cell(gp);
3000	rtnl_unlock();
3001
3002	netdev_info(dev, "Sun GEM (PCI) 10/100/1000BaseT Ethernet %pM\n",
3003		    dev->dev_addr);
3004	return 0;
3005
3006err_out_free_consistent:
3007	gem_remove_one(pdev);
3008err_out_iounmap:
3009	gem_put_cell(gp);
3010	iounmap(gp->regs);
3011
3012err_out_free_res:
3013	pci_release_regions(pdev);
3014
3015err_out_free_netdev:
3016	free_netdev(dev);
3017err_disable_device:
3018	pci_disable_device(pdev);
3019	return err;
3020
3021}
3022
3023static SIMPLE_DEV_PM_OPS(gem_pm_ops, gem_suspend, gem_resume);
3024
3025static struct pci_driver gem_driver = {
3026	.name		= GEM_MODULE_NAME,
3027	.id_table	= gem_pci_tbl,
3028	.probe		= gem_init_one,
3029	.remove		= gem_remove_one,
3030	.driver.pm	= &gem_pm_ops,
 
 
 
3031};
3032
3033module_pci_driver(gem_driver);