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1// SPDX-License-Identifier: GPL-2.0
2/* $Id: sungem.c,v 1.44.2.22 2002/03/13 01:18:12 davem Exp $
3 * sungem.c: Sun GEM ethernet driver.
4 *
5 * Copyright (C) 2000, 2001, 2002, 2003 David S. Miller (davem@redhat.com)
6 *
7 * Support for Apple GMAC and assorted PHYs, WOL, Power Management
8 * (C) 2001,2002,2003 Benjamin Herrenscmidt (benh@kernel.crashing.org)
9 * (C) 2004,2005 Benjamin Herrenscmidt, IBM Corp.
10 *
11 * NAPI and NETPOLL support
12 * (C) 2004 by Eric Lemoine (eric.lemoine@gmail.com)
13 *
14 */
15
16#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
17
18#include <linux/module.h>
19#include <linux/kernel.h>
20#include <linux/types.h>
21#include <linux/fcntl.h>
22#include <linux/interrupt.h>
23#include <linux/ioport.h>
24#include <linux/in.h>
25#include <linux/sched.h>
26#include <linux/string.h>
27#include <linux/delay.h>
28#include <linux/errno.h>
29#include <linux/pci.h>
30#include <linux/dma-mapping.h>
31#include <linux/netdevice.h>
32#include <linux/etherdevice.h>
33#include <linux/skbuff.h>
34#include <linux/mii.h>
35#include <linux/ethtool.h>
36#include <linux/crc32.h>
37#include <linux/random.h>
38#include <linux/workqueue.h>
39#include <linux/if_vlan.h>
40#include <linux/bitops.h>
41#include <linux/mm.h>
42#include <linux/gfp.h>
43#include <linux/of.h>
44
45#include <asm/io.h>
46#include <asm/byteorder.h>
47#include <linux/uaccess.h>
48#include <asm/irq.h>
49
50#ifdef CONFIG_SPARC
51#include <asm/idprom.h>
52#include <asm/prom.h>
53#endif
54
55#ifdef CONFIG_PPC_PMAC
56#include <asm/machdep.h>
57#include <asm/pmac_feature.h>
58#endif
59
60#include <linux/sungem_phy.h>
61#include "sungem.h"
62
63#define STRIP_FCS
64
65#define DEFAULT_MSG (NETIF_MSG_DRV | \
66 NETIF_MSG_PROBE | \
67 NETIF_MSG_LINK)
68
69#define ADVERTISE_MASK (SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full | \
70 SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full | \
71 SUPPORTED_1000baseT_Half | SUPPORTED_1000baseT_Full | \
72 SUPPORTED_Pause | SUPPORTED_Autoneg)
73
74#define DRV_NAME "sungem"
75#define DRV_VERSION "1.0"
76#define DRV_AUTHOR "David S. Miller <davem@redhat.com>"
77
78static char version[] =
79 DRV_NAME ".c:v" DRV_VERSION " " DRV_AUTHOR "\n";
80
81MODULE_AUTHOR(DRV_AUTHOR);
82MODULE_DESCRIPTION("Sun GEM Gbit ethernet driver");
83MODULE_LICENSE("GPL");
84
85#define GEM_MODULE_NAME "gem"
86
87static const struct pci_device_id gem_pci_tbl[] = {
88 { PCI_VENDOR_ID_SUN, PCI_DEVICE_ID_SUN_GEM,
89 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
90
91 /* These models only differ from the original GEM in
92 * that their tx/rx fifos are of a different size and
93 * they only support 10/100 speeds. -DaveM
94 *
95 * Apple's GMAC does support gigabit on machines with
96 * the BCM54xx PHYs. -BenH
97 */
98 { PCI_VENDOR_ID_SUN, PCI_DEVICE_ID_SUN_RIO_GEM,
99 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
100 { PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_UNI_N_GMAC,
101 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
102 { PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_UNI_N_GMACP,
103 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
104 { PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_UNI_N_GMAC2,
105 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
106 { PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_K2_GMAC,
107 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
108 { PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_SH_SUNGEM,
109 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
110 { PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_IPID2_GMAC,
111 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
112 {0, }
113};
114
115MODULE_DEVICE_TABLE(pci, gem_pci_tbl);
116
117static u16 __sungem_phy_read(struct gem *gp, int phy_addr, int reg)
118{
119 u32 cmd;
120 int limit = 10000;
121
122 cmd = (1 << 30);
123 cmd |= (2 << 28);
124 cmd |= (phy_addr << 23) & MIF_FRAME_PHYAD;
125 cmd |= (reg << 18) & MIF_FRAME_REGAD;
126 cmd |= (MIF_FRAME_TAMSB);
127 writel(cmd, gp->regs + MIF_FRAME);
128
129 while (--limit) {
130 cmd = readl(gp->regs + MIF_FRAME);
131 if (cmd & MIF_FRAME_TALSB)
132 break;
133
134 udelay(10);
135 }
136
137 if (!limit)
138 cmd = 0xffff;
139
140 return cmd & MIF_FRAME_DATA;
141}
142
143static inline int _sungem_phy_read(struct net_device *dev, int mii_id, int reg)
144{
145 struct gem *gp = netdev_priv(dev);
146 return __sungem_phy_read(gp, mii_id, reg);
147}
148
149static inline u16 sungem_phy_read(struct gem *gp, int reg)
150{
151 return __sungem_phy_read(gp, gp->mii_phy_addr, reg);
152}
153
154static void __sungem_phy_write(struct gem *gp, int phy_addr, int reg, u16 val)
155{
156 u32 cmd;
157 int limit = 10000;
158
159 cmd = (1 << 30);
160 cmd |= (1 << 28);
161 cmd |= (phy_addr << 23) & MIF_FRAME_PHYAD;
162 cmd |= (reg << 18) & MIF_FRAME_REGAD;
163 cmd |= (MIF_FRAME_TAMSB);
164 cmd |= (val & MIF_FRAME_DATA);
165 writel(cmd, gp->regs + MIF_FRAME);
166
167 while (limit--) {
168 cmd = readl(gp->regs + MIF_FRAME);
169 if (cmd & MIF_FRAME_TALSB)
170 break;
171
172 udelay(10);
173 }
174}
175
176static inline void _sungem_phy_write(struct net_device *dev, int mii_id, int reg, int val)
177{
178 struct gem *gp = netdev_priv(dev);
179 __sungem_phy_write(gp, mii_id, reg, val & 0xffff);
180}
181
182static inline void sungem_phy_write(struct gem *gp, int reg, u16 val)
183{
184 __sungem_phy_write(gp, gp->mii_phy_addr, reg, val);
185}
186
187static inline void gem_enable_ints(struct gem *gp)
188{
189 /* Enable all interrupts but TXDONE */
190 writel(GREG_STAT_TXDONE, gp->regs + GREG_IMASK);
191}
192
193static inline void gem_disable_ints(struct gem *gp)
194{
195 /* Disable all interrupts, including TXDONE */
196 writel(GREG_STAT_NAPI | GREG_STAT_TXDONE, gp->regs + GREG_IMASK);
197 (void)readl(gp->regs + GREG_IMASK); /* write posting */
198}
199
200static void gem_get_cell(struct gem *gp)
201{
202 BUG_ON(gp->cell_enabled < 0);
203 gp->cell_enabled++;
204#ifdef CONFIG_PPC_PMAC
205 if (gp->cell_enabled == 1) {
206 mb();
207 pmac_call_feature(PMAC_FTR_GMAC_ENABLE, gp->of_node, 0, 1);
208 udelay(10);
209 }
210#endif /* CONFIG_PPC_PMAC */
211}
212
213/* Turn off the chip's clock */
214static void gem_put_cell(struct gem *gp)
215{
216 BUG_ON(gp->cell_enabled <= 0);
217 gp->cell_enabled--;
218#ifdef CONFIG_PPC_PMAC
219 if (gp->cell_enabled == 0) {
220 mb();
221 pmac_call_feature(PMAC_FTR_GMAC_ENABLE, gp->of_node, 0, 0);
222 udelay(10);
223 }
224#endif /* CONFIG_PPC_PMAC */
225}
226
227static inline void gem_netif_stop(struct gem *gp)
228{
229 netif_trans_update(gp->dev); /* prevent tx timeout */
230 napi_disable(&gp->napi);
231 netif_tx_disable(gp->dev);
232}
233
234static inline void gem_netif_start(struct gem *gp)
235{
236 /* NOTE: unconditional netif_wake_queue is only
237 * appropriate so long as all callers are assured to
238 * have free tx slots.
239 */
240 netif_wake_queue(gp->dev);
241 napi_enable(&gp->napi);
242}
243
244static void gem_schedule_reset(struct gem *gp)
245{
246 gp->reset_task_pending = 1;
247 schedule_work(&gp->reset_task);
248}
249
250static void gem_handle_mif_event(struct gem *gp, u32 reg_val, u32 changed_bits)
251{
252 if (netif_msg_intr(gp))
253 printk(KERN_DEBUG "%s: mif interrupt\n", gp->dev->name);
254}
255
256static int gem_pcs_interrupt(struct net_device *dev, struct gem *gp, u32 gem_status)
257{
258 u32 pcs_istat = readl(gp->regs + PCS_ISTAT);
259 u32 pcs_miistat;
260
261 if (netif_msg_intr(gp))
262 printk(KERN_DEBUG "%s: pcs interrupt, pcs_istat: 0x%x\n",
263 gp->dev->name, pcs_istat);
264
265 if (!(pcs_istat & PCS_ISTAT_LSC)) {
266 netdev_err(dev, "PCS irq but no link status change???\n");
267 return 0;
268 }
269
270 /* The link status bit latches on zero, so you must
271 * read it twice in such a case to see a transition
272 * to the link being up.
273 */
274 pcs_miistat = readl(gp->regs + PCS_MIISTAT);
275 if (!(pcs_miistat & PCS_MIISTAT_LS))
276 pcs_miistat |=
277 (readl(gp->regs + PCS_MIISTAT) &
278 PCS_MIISTAT_LS);
279
280 if (pcs_miistat & PCS_MIISTAT_ANC) {
281 /* The remote-fault indication is only valid
282 * when autoneg has completed.
283 */
284 if (pcs_miistat & PCS_MIISTAT_RF)
285 netdev_info(dev, "PCS AutoNEG complete, RemoteFault\n");
286 else
287 netdev_info(dev, "PCS AutoNEG complete\n");
288 }
289
290 if (pcs_miistat & PCS_MIISTAT_LS) {
291 netdev_info(dev, "PCS link is now up\n");
292 netif_carrier_on(gp->dev);
293 } else {
294 netdev_info(dev, "PCS link is now down\n");
295 netif_carrier_off(gp->dev);
296 /* If this happens and the link timer is not running,
297 * reset so we re-negotiate.
298 */
299 if (!timer_pending(&gp->link_timer))
300 return 1;
301 }
302
303 return 0;
304}
305
306static int gem_txmac_interrupt(struct net_device *dev, struct gem *gp, u32 gem_status)
307{
308 u32 txmac_stat = readl(gp->regs + MAC_TXSTAT);
309
310 if (netif_msg_intr(gp))
311 printk(KERN_DEBUG "%s: txmac interrupt, txmac_stat: 0x%x\n",
312 gp->dev->name, txmac_stat);
313
314 /* Defer timer expiration is quite normal,
315 * don't even log the event.
316 */
317 if ((txmac_stat & MAC_TXSTAT_DTE) &&
318 !(txmac_stat & ~MAC_TXSTAT_DTE))
319 return 0;
320
321 if (txmac_stat & MAC_TXSTAT_URUN) {
322 netdev_err(dev, "TX MAC xmit underrun\n");
323 dev->stats.tx_fifo_errors++;
324 }
325
326 if (txmac_stat & MAC_TXSTAT_MPE) {
327 netdev_err(dev, "TX MAC max packet size error\n");
328 dev->stats.tx_errors++;
329 }
330
331 /* The rest are all cases of one of the 16-bit TX
332 * counters expiring.
333 */
334 if (txmac_stat & MAC_TXSTAT_NCE)
335 dev->stats.collisions += 0x10000;
336
337 if (txmac_stat & MAC_TXSTAT_ECE) {
338 dev->stats.tx_aborted_errors += 0x10000;
339 dev->stats.collisions += 0x10000;
340 }
341
342 if (txmac_stat & MAC_TXSTAT_LCE) {
343 dev->stats.tx_aborted_errors += 0x10000;
344 dev->stats.collisions += 0x10000;
345 }
346
347 /* We do not keep track of MAC_TXSTAT_FCE and
348 * MAC_TXSTAT_PCE events.
349 */
350 return 0;
351}
352
353/* When we get a RX fifo overflow, the RX unit in GEM is probably hung
354 * so we do the following.
355 *
356 * If any part of the reset goes wrong, we return 1 and that causes the
357 * whole chip to be reset.
358 */
359static int gem_rxmac_reset(struct gem *gp)
360{
361 struct net_device *dev = gp->dev;
362 int limit, i;
363 u64 desc_dma;
364 u32 val;
365
366 /* First, reset & disable MAC RX. */
367 writel(MAC_RXRST_CMD, gp->regs + MAC_RXRST);
368 for (limit = 0; limit < 5000; limit++) {
369 if (!(readl(gp->regs + MAC_RXRST) & MAC_RXRST_CMD))
370 break;
371 udelay(10);
372 }
373 if (limit == 5000) {
374 netdev_err(dev, "RX MAC will not reset, resetting whole chip\n");
375 return 1;
376 }
377
378 writel(gp->mac_rx_cfg & ~MAC_RXCFG_ENAB,
379 gp->regs + MAC_RXCFG);
380 for (limit = 0; limit < 5000; limit++) {
381 if (!(readl(gp->regs + MAC_RXCFG) & MAC_RXCFG_ENAB))
382 break;
383 udelay(10);
384 }
385 if (limit == 5000) {
386 netdev_err(dev, "RX MAC will not disable, resetting whole chip\n");
387 return 1;
388 }
389
390 /* Second, disable RX DMA. */
391 writel(0, gp->regs + RXDMA_CFG);
392 for (limit = 0; limit < 5000; limit++) {
393 if (!(readl(gp->regs + RXDMA_CFG) & RXDMA_CFG_ENABLE))
394 break;
395 udelay(10);
396 }
397 if (limit == 5000) {
398 netdev_err(dev, "RX DMA will not disable, resetting whole chip\n");
399 return 1;
400 }
401
402 mdelay(5);
403
404 /* Execute RX reset command. */
405 writel(gp->swrst_base | GREG_SWRST_RXRST,
406 gp->regs + GREG_SWRST);
407 for (limit = 0; limit < 5000; limit++) {
408 if (!(readl(gp->regs + GREG_SWRST) & GREG_SWRST_RXRST))
409 break;
410 udelay(10);
411 }
412 if (limit == 5000) {
413 netdev_err(dev, "RX reset command will not execute, resetting whole chip\n");
414 return 1;
415 }
416
417 /* Refresh the RX ring. */
418 for (i = 0; i < RX_RING_SIZE; i++) {
419 struct gem_rxd *rxd = &gp->init_block->rxd[i];
420
421 if (gp->rx_skbs[i] == NULL) {
422 netdev_err(dev, "Parts of RX ring empty, resetting whole chip\n");
423 return 1;
424 }
425
426 rxd->status_word = cpu_to_le64(RXDCTRL_FRESH(gp));
427 }
428 gp->rx_new = gp->rx_old = 0;
429
430 /* Now we must reprogram the rest of RX unit. */
431 desc_dma = (u64) gp->gblock_dvma;
432 desc_dma += (INIT_BLOCK_TX_RING_SIZE * sizeof(struct gem_txd));
433 writel(desc_dma >> 32, gp->regs + RXDMA_DBHI);
434 writel(desc_dma & 0xffffffff, gp->regs + RXDMA_DBLOW);
435 writel(RX_RING_SIZE - 4, gp->regs + RXDMA_KICK);
436 val = (RXDMA_CFG_BASE | (RX_OFFSET << 10) |
437 (ETH_HLEN << 13) | RXDMA_CFG_FTHRESH_128);
438 writel(val, gp->regs + RXDMA_CFG);
439 if (readl(gp->regs + GREG_BIFCFG) & GREG_BIFCFG_M66EN)
440 writel(((5 & RXDMA_BLANK_IPKTS) |
441 ((8 << 12) & RXDMA_BLANK_ITIME)),
442 gp->regs + RXDMA_BLANK);
443 else
444 writel(((5 & RXDMA_BLANK_IPKTS) |
445 ((4 << 12) & RXDMA_BLANK_ITIME)),
446 gp->regs + RXDMA_BLANK);
447 val = (((gp->rx_pause_off / 64) << 0) & RXDMA_PTHRESH_OFF);
448 val |= (((gp->rx_pause_on / 64) << 12) & RXDMA_PTHRESH_ON);
449 writel(val, gp->regs + RXDMA_PTHRESH);
450 val = readl(gp->regs + RXDMA_CFG);
451 writel(val | RXDMA_CFG_ENABLE, gp->regs + RXDMA_CFG);
452 writel(MAC_RXSTAT_RCV, gp->regs + MAC_RXMASK);
453 val = readl(gp->regs + MAC_RXCFG);
454 writel(val | MAC_RXCFG_ENAB, gp->regs + MAC_RXCFG);
455
456 return 0;
457}
458
459static int gem_rxmac_interrupt(struct net_device *dev, struct gem *gp, u32 gem_status)
460{
461 u32 rxmac_stat = readl(gp->regs + MAC_RXSTAT);
462 int ret = 0;
463
464 if (netif_msg_intr(gp))
465 printk(KERN_DEBUG "%s: rxmac interrupt, rxmac_stat: 0x%x\n",
466 gp->dev->name, rxmac_stat);
467
468 if (rxmac_stat & MAC_RXSTAT_OFLW) {
469 u32 smac = readl(gp->regs + MAC_SMACHINE);
470
471 netdev_err(dev, "RX MAC fifo overflow smac[%08x]\n", smac);
472 dev->stats.rx_over_errors++;
473 dev->stats.rx_fifo_errors++;
474
475 ret = gem_rxmac_reset(gp);
476 }
477
478 if (rxmac_stat & MAC_RXSTAT_ACE)
479 dev->stats.rx_frame_errors += 0x10000;
480
481 if (rxmac_stat & MAC_RXSTAT_CCE)
482 dev->stats.rx_crc_errors += 0x10000;
483
484 if (rxmac_stat & MAC_RXSTAT_LCE)
485 dev->stats.rx_length_errors += 0x10000;
486
487 /* We do not track MAC_RXSTAT_FCE and MAC_RXSTAT_VCE
488 * events.
489 */
490 return ret;
491}
492
493static int gem_mac_interrupt(struct net_device *dev, struct gem *gp, u32 gem_status)
494{
495 u32 mac_cstat = readl(gp->regs + MAC_CSTAT);
496
497 if (netif_msg_intr(gp))
498 printk(KERN_DEBUG "%s: mac interrupt, mac_cstat: 0x%x\n",
499 gp->dev->name, mac_cstat);
500
501 /* This interrupt is just for pause frame and pause
502 * tracking. It is useful for diagnostics and debug
503 * but probably by default we will mask these events.
504 */
505 if (mac_cstat & MAC_CSTAT_PS)
506 gp->pause_entered++;
507
508 if (mac_cstat & MAC_CSTAT_PRCV)
509 gp->pause_last_time_recvd = (mac_cstat >> 16);
510
511 return 0;
512}
513
514static int gem_mif_interrupt(struct net_device *dev, struct gem *gp, u32 gem_status)
515{
516 u32 mif_status = readl(gp->regs + MIF_STATUS);
517 u32 reg_val, changed_bits;
518
519 reg_val = (mif_status & MIF_STATUS_DATA) >> 16;
520 changed_bits = (mif_status & MIF_STATUS_STAT);
521
522 gem_handle_mif_event(gp, reg_val, changed_bits);
523
524 return 0;
525}
526
527static int gem_pci_interrupt(struct net_device *dev, struct gem *gp, u32 gem_status)
528{
529 u32 pci_estat = readl(gp->regs + GREG_PCIESTAT);
530
531 if (gp->pdev->vendor == PCI_VENDOR_ID_SUN &&
532 gp->pdev->device == PCI_DEVICE_ID_SUN_GEM) {
533 netdev_err(dev, "PCI error [%04x]", pci_estat);
534
535 if (pci_estat & GREG_PCIESTAT_BADACK)
536 pr_cont(" <No ACK64# during ABS64 cycle>");
537 if (pci_estat & GREG_PCIESTAT_DTRTO)
538 pr_cont(" <Delayed transaction timeout>");
539 if (pci_estat & GREG_PCIESTAT_OTHER)
540 pr_cont(" <other>");
541 pr_cont("\n");
542 } else {
543 pci_estat |= GREG_PCIESTAT_OTHER;
544 netdev_err(dev, "PCI error\n");
545 }
546
547 if (pci_estat & GREG_PCIESTAT_OTHER) {
548 int pci_errs;
549
550 /* Interrogate PCI config space for the
551 * true cause.
552 */
553 pci_errs = pci_status_get_and_clear_errors(gp->pdev);
554 netdev_err(dev, "PCI status errors[%04x]\n", pci_errs);
555 if (pci_errs & PCI_STATUS_PARITY)
556 netdev_err(dev, "PCI parity error detected\n");
557 if (pci_errs & PCI_STATUS_SIG_TARGET_ABORT)
558 netdev_err(dev, "PCI target abort\n");
559 if (pci_errs & PCI_STATUS_REC_TARGET_ABORT)
560 netdev_err(dev, "PCI master acks target abort\n");
561 if (pci_errs & PCI_STATUS_REC_MASTER_ABORT)
562 netdev_err(dev, "PCI master abort\n");
563 if (pci_errs & PCI_STATUS_SIG_SYSTEM_ERROR)
564 netdev_err(dev, "PCI system error SERR#\n");
565 if (pci_errs & PCI_STATUS_DETECTED_PARITY)
566 netdev_err(dev, "PCI parity error\n");
567 }
568
569 /* For all PCI errors, we should reset the chip. */
570 return 1;
571}
572
573/* All non-normal interrupt conditions get serviced here.
574 * Returns non-zero if we should just exit the interrupt
575 * handler right now (ie. if we reset the card which invalidates
576 * all of the other original irq status bits).
577 */
578static int gem_abnormal_irq(struct net_device *dev, struct gem *gp, u32 gem_status)
579{
580 if (gem_status & GREG_STAT_RXNOBUF) {
581 /* Frame arrived, no free RX buffers available. */
582 if (netif_msg_rx_err(gp))
583 printk(KERN_DEBUG "%s: no buffer for rx frame\n",
584 gp->dev->name);
585 dev->stats.rx_dropped++;
586 }
587
588 if (gem_status & GREG_STAT_RXTAGERR) {
589 /* corrupt RX tag framing */
590 if (netif_msg_rx_err(gp))
591 printk(KERN_DEBUG "%s: corrupt rx tag framing\n",
592 gp->dev->name);
593 dev->stats.rx_errors++;
594
595 return 1;
596 }
597
598 if (gem_status & GREG_STAT_PCS) {
599 if (gem_pcs_interrupt(dev, gp, gem_status))
600 return 1;
601 }
602
603 if (gem_status & GREG_STAT_TXMAC) {
604 if (gem_txmac_interrupt(dev, gp, gem_status))
605 return 1;
606 }
607
608 if (gem_status & GREG_STAT_RXMAC) {
609 if (gem_rxmac_interrupt(dev, gp, gem_status))
610 return 1;
611 }
612
613 if (gem_status & GREG_STAT_MAC) {
614 if (gem_mac_interrupt(dev, gp, gem_status))
615 return 1;
616 }
617
618 if (gem_status & GREG_STAT_MIF) {
619 if (gem_mif_interrupt(dev, gp, gem_status))
620 return 1;
621 }
622
623 if (gem_status & GREG_STAT_PCIERR) {
624 if (gem_pci_interrupt(dev, gp, gem_status))
625 return 1;
626 }
627
628 return 0;
629}
630
631static __inline__ void gem_tx(struct net_device *dev, struct gem *gp, u32 gem_status)
632{
633 int entry, limit;
634
635 entry = gp->tx_old;
636 limit = ((gem_status & GREG_STAT_TXNR) >> GREG_STAT_TXNR_SHIFT);
637 while (entry != limit) {
638 struct sk_buff *skb;
639 struct gem_txd *txd;
640 dma_addr_t dma_addr;
641 u32 dma_len;
642 int frag;
643
644 if (netif_msg_tx_done(gp))
645 printk(KERN_DEBUG "%s: tx done, slot %d\n",
646 gp->dev->name, entry);
647 skb = gp->tx_skbs[entry];
648 if (skb_shinfo(skb)->nr_frags) {
649 int last = entry + skb_shinfo(skb)->nr_frags;
650 int walk = entry;
651 int incomplete = 0;
652
653 last &= (TX_RING_SIZE - 1);
654 for (;;) {
655 walk = NEXT_TX(walk);
656 if (walk == limit)
657 incomplete = 1;
658 if (walk == last)
659 break;
660 }
661 if (incomplete)
662 break;
663 }
664 gp->tx_skbs[entry] = NULL;
665 dev->stats.tx_bytes += skb->len;
666
667 for (frag = 0; frag <= skb_shinfo(skb)->nr_frags; frag++) {
668 txd = &gp->init_block->txd[entry];
669
670 dma_addr = le64_to_cpu(txd->buffer);
671 dma_len = le64_to_cpu(txd->control_word) & TXDCTRL_BUFSZ;
672
673 dma_unmap_page(&gp->pdev->dev, dma_addr, dma_len,
674 DMA_TO_DEVICE);
675 entry = NEXT_TX(entry);
676 }
677
678 dev->stats.tx_packets++;
679 dev_consume_skb_any(skb);
680 }
681 gp->tx_old = entry;
682
683 /* Need to make the tx_old update visible to gem_start_xmit()
684 * before checking for netif_queue_stopped(). Without the
685 * memory barrier, there is a small possibility that gem_start_xmit()
686 * will miss it and cause the queue to be stopped forever.
687 */
688 smp_mb();
689
690 if (unlikely(netif_queue_stopped(dev) &&
691 TX_BUFFS_AVAIL(gp) > (MAX_SKB_FRAGS + 1))) {
692 struct netdev_queue *txq = netdev_get_tx_queue(dev, 0);
693
694 __netif_tx_lock(txq, smp_processor_id());
695 if (netif_queue_stopped(dev) &&
696 TX_BUFFS_AVAIL(gp) > (MAX_SKB_FRAGS + 1))
697 netif_wake_queue(dev);
698 __netif_tx_unlock(txq);
699 }
700}
701
702static __inline__ void gem_post_rxds(struct gem *gp, int limit)
703{
704 int cluster_start, curr, count, kick;
705
706 cluster_start = curr = (gp->rx_new & ~(4 - 1));
707 count = 0;
708 kick = -1;
709 dma_wmb();
710 while (curr != limit) {
711 curr = NEXT_RX(curr);
712 if (++count == 4) {
713 struct gem_rxd *rxd =
714 &gp->init_block->rxd[cluster_start];
715 for (;;) {
716 rxd->status_word = cpu_to_le64(RXDCTRL_FRESH(gp));
717 rxd++;
718 cluster_start = NEXT_RX(cluster_start);
719 if (cluster_start == curr)
720 break;
721 }
722 kick = curr;
723 count = 0;
724 }
725 }
726 if (kick >= 0) {
727 mb();
728 writel(kick, gp->regs + RXDMA_KICK);
729 }
730}
731
732#define ALIGNED_RX_SKB_ADDR(addr) \
733 ((((unsigned long)(addr) + (64UL - 1UL)) & ~(64UL - 1UL)) - (unsigned long)(addr))
734static __inline__ struct sk_buff *gem_alloc_skb(struct net_device *dev, int size,
735 gfp_t gfp_flags)
736{
737 struct sk_buff *skb = alloc_skb(size + 64, gfp_flags);
738
739 if (likely(skb)) {
740 unsigned long offset = ALIGNED_RX_SKB_ADDR(skb->data);
741 skb_reserve(skb, offset);
742 }
743 return skb;
744}
745
746static int gem_rx(struct gem *gp, int work_to_do)
747{
748 struct net_device *dev = gp->dev;
749 int entry, drops, work_done = 0;
750 u32 done;
751
752 if (netif_msg_rx_status(gp))
753 printk(KERN_DEBUG "%s: rx interrupt, done: %d, rx_new: %d\n",
754 gp->dev->name, readl(gp->regs + RXDMA_DONE), gp->rx_new);
755
756 entry = gp->rx_new;
757 drops = 0;
758 done = readl(gp->regs + RXDMA_DONE);
759 for (;;) {
760 struct gem_rxd *rxd = &gp->init_block->rxd[entry];
761 struct sk_buff *skb;
762 u64 status = le64_to_cpu(rxd->status_word);
763 dma_addr_t dma_addr;
764 int len;
765
766 if ((status & RXDCTRL_OWN) != 0)
767 break;
768
769 if (work_done >= RX_RING_SIZE || work_done >= work_to_do)
770 break;
771
772 /* When writing back RX descriptor, GEM writes status
773 * then buffer address, possibly in separate transactions.
774 * If we don't wait for the chip to write both, we could
775 * post a new buffer to this descriptor then have GEM spam
776 * on the buffer address. We sync on the RX completion
777 * register to prevent this from happening.
778 */
779 if (entry == done) {
780 done = readl(gp->regs + RXDMA_DONE);
781 if (entry == done)
782 break;
783 }
784
785 /* We can now account for the work we're about to do */
786 work_done++;
787
788 skb = gp->rx_skbs[entry];
789
790 len = (status & RXDCTRL_BUFSZ) >> 16;
791 if ((len < ETH_ZLEN) || (status & RXDCTRL_BAD)) {
792 dev->stats.rx_errors++;
793 if (len < ETH_ZLEN)
794 dev->stats.rx_length_errors++;
795 if (len & RXDCTRL_BAD)
796 dev->stats.rx_crc_errors++;
797
798 /* We'll just return it to GEM. */
799 drop_it:
800 dev->stats.rx_dropped++;
801 goto next;
802 }
803
804 dma_addr = le64_to_cpu(rxd->buffer);
805 if (len > RX_COPY_THRESHOLD) {
806 struct sk_buff *new_skb;
807
808 new_skb = gem_alloc_skb(dev, RX_BUF_ALLOC_SIZE(gp), GFP_ATOMIC);
809 if (new_skb == NULL) {
810 drops++;
811 goto drop_it;
812 }
813 dma_unmap_page(&gp->pdev->dev, dma_addr,
814 RX_BUF_ALLOC_SIZE(gp), DMA_FROM_DEVICE);
815 gp->rx_skbs[entry] = new_skb;
816 skb_put(new_skb, (gp->rx_buf_sz + RX_OFFSET));
817 rxd->buffer = cpu_to_le64(dma_map_page(&gp->pdev->dev,
818 virt_to_page(new_skb->data),
819 offset_in_page(new_skb->data),
820 RX_BUF_ALLOC_SIZE(gp),
821 DMA_FROM_DEVICE));
822 skb_reserve(new_skb, RX_OFFSET);
823
824 /* Trim the original skb for the netif. */
825 skb_trim(skb, len);
826 } else {
827 struct sk_buff *copy_skb = netdev_alloc_skb(dev, len + 2);
828
829 if (copy_skb == NULL) {
830 drops++;
831 goto drop_it;
832 }
833
834 skb_reserve(copy_skb, 2);
835 skb_put(copy_skb, len);
836 dma_sync_single_for_cpu(&gp->pdev->dev, dma_addr, len,
837 DMA_FROM_DEVICE);
838 skb_copy_from_linear_data(skb, copy_skb->data, len);
839 dma_sync_single_for_device(&gp->pdev->dev, dma_addr,
840 len, DMA_FROM_DEVICE);
841
842 /* We'll reuse the original ring buffer. */
843 skb = copy_skb;
844 }
845
846 if (likely(dev->features & NETIF_F_RXCSUM)) {
847 __sum16 csum;
848
849 csum = (__force __sum16)htons((status & RXDCTRL_TCPCSUM) ^ 0xffff);
850 skb->csum = csum_unfold(csum);
851 skb->ip_summed = CHECKSUM_COMPLETE;
852 }
853 skb->protocol = eth_type_trans(skb, gp->dev);
854
855 napi_gro_receive(&gp->napi, skb);
856
857 dev->stats.rx_packets++;
858 dev->stats.rx_bytes += len;
859
860 next:
861 entry = NEXT_RX(entry);
862 }
863
864 gem_post_rxds(gp, entry);
865
866 gp->rx_new = entry;
867
868 if (drops)
869 netdev_info(gp->dev, "Memory squeeze, deferring packet\n");
870
871 return work_done;
872}
873
874static int gem_poll(struct napi_struct *napi, int budget)
875{
876 struct gem *gp = container_of(napi, struct gem, napi);
877 struct net_device *dev = gp->dev;
878 int work_done;
879
880 work_done = 0;
881 do {
882 /* Handle anomalies */
883 if (unlikely(gp->status & GREG_STAT_ABNORMAL)) {
884 struct netdev_queue *txq = netdev_get_tx_queue(dev, 0);
885 int reset;
886
887 /* We run the abnormal interrupt handling code with
888 * the Tx lock. It only resets the Rx portion of the
889 * chip, but we need to guard it against DMA being
890 * restarted by the link poll timer
891 */
892 __netif_tx_lock(txq, smp_processor_id());
893 reset = gem_abnormal_irq(dev, gp, gp->status);
894 __netif_tx_unlock(txq);
895 if (reset) {
896 gem_schedule_reset(gp);
897 napi_complete(napi);
898 return work_done;
899 }
900 }
901
902 /* Run TX completion thread */
903 gem_tx(dev, gp, gp->status);
904
905 /* Run RX thread. We don't use any locking here,
906 * code willing to do bad things - like cleaning the
907 * rx ring - must call napi_disable(), which
908 * schedule_timeout()'s if polling is already disabled.
909 */
910 work_done += gem_rx(gp, budget - work_done);
911
912 if (work_done >= budget)
913 return work_done;
914
915 gp->status = readl(gp->regs + GREG_STAT);
916 } while (gp->status & GREG_STAT_NAPI);
917
918 napi_complete_done(napi, work_done);
919 gem_enable_ints(gp);
920
921 return work_done;
922}
923
924static irqreturn_t gem_interrupt(int irq, void *dev_id)
925{
926 struct net_device *dev = dev_id;
927 struct gem *gp = netdev_priv(dev);
928
929 if (napi_schedule_prep(&gp->napi)) {
930 u32 gem_status = readl(gp->regs + GREG_STAT);
931
932 if (unlikely(gem_status == 0)) {
933 napi_enable(&gp->napi);
934 return IRQ_NONE;
935 }
936 if (netif_msg_intr(gp))
937 printk(KERN_DEBUG "%s: gem_interrupt() gem_status: 0x%x\n",
938 gp->dev->name, gem_status);
939
940 gp->status = gem_status;
941 gem_disable_ints(gp);
942 __napi_schedule(&gp->napi);
943 }
944
945 /* If polling was disabled at the time we received that
946 * interrupt, we may return IRQ_HANDLED here while we
947 * should return IRQ_NONE. No big deal...
948 */
949 return IRQ_HANDLED;
950}
951
952static void gem_tx_timeout(struct net_device *dev, unsigned int txqueue)
953{
954 struct gem *gp = netdev_priv(dev);
955
956 netdev_err(dev, "transmit timed out, resetting\n");
957
958 netdev_err(dev, "TX_STATE[%08x:%08x:%08x]\n",
959 readl(gp->regs + TXDMA_CFG),
960 readl(gp->regs + MAC_TXSTAT),
961 readl(gp->regs + MAC_TXCFG));
962 netdev_err(dev, "RX_STATE[%08x:%08x:%08x]\n",
963 readl(gp->regs + RXDMA_CFG),
964 readl(gp->regs + MAC_RXSTAT),
965 readl(gp->regs + MAC_RXCFG));
966
967 gem_schedule_reset(gp);
968}
969
970static __inline__ int gem_intme(int entry)
971{
972 /* Algorithm: IRQ every 1/2 of descriptors. */
973 if (!(entry & ((TX_RING_SIZE>>1)-1)))
974 return 1;
975
976 return 0;
977}
978
979static netdev_tx_t gem_start_xmit(struct sk_buff *skb,
980 struct net_device *dev)
981{
982 struct gem *gp = netdev_priv(dev);
983 int entry;
984 u64 ctrl;
985
986 ctrl = 0;
987 if (skb->ip_summed == CHECKSUM_PARTIAL) {
988 const u64 csum_start_off = skb_checksum_start_offset(skb);
989 const u64 csum_stuff_off = csum_start_off + skb->csum_offset;
990
991 ctrl = (TXDCTRL_CENAB |
992 (csum_start_off << 15) |
993 (csum_stuff_off << 21));
994 }
995
996 if (unlikely(TX_BUFFS_AVAIL(gp) <= (skb_shinfo(skb)->nr_frags + 1))) {
997 /* This is a hard error, log it. */
998 if (!netif_queue_stopped(dev)) {
999 netif_stop_queue(dev);
1000 netdev_err(dev, "BUG! Tx Ring full when queue awake!\n");
1001 }
1002 return NETDEV_TX_BUSY;
1003 }
1004
1005 entry = gp->tx_new;
1006 gp->tx_skbs[entry] = skb;
1007
1008 if (skb_shinfo(skb)->nr_frags == 0) {
1009 struct gem_txd *txd = &gp->init_block->txd[entry];
1010 dma_addr_t mapping;
1011 u32 len;
1012
1013 len = skb->len;
1014 mapping = dma_map_page(&gp->pdev->dev,
1015 virt_to_page(skb->data),
1016 offset_in_page(skb->data),
1017 len, DMA_TO_DEVICE);
1018 ctrl |= TXDCTRL_SOF | TXDCTRL_EOF | len;
1019 if (gem_intme(entry))
1020 ctrl |= TXDCTRL_INTME;
1021 txd->buffer = cpu_to_le64(mapping);
1022 dma_wmb();
1023 txd->control_word = cpu_to_le64(ctrl);
1024 entry = NEXT_TX(entry);
1025 } else {
1026 struct gem_txd *txd;
1027 u32 first_len;
1028 u64 intme;
1029 dma_addr_t first_mapping;
1030 int frag, first_entry = entry;
1031
1032 intme = 0;
1033 if (gem_intme(entry))
1034 intme |= TXDCTRL_INTME;
1035
1036 /* We must give this initial chunk to the device last.
1037 * Otherwise we could race with the device.
1038 */
1039 first_len = skb_headlen(skb);
1040 first_mapping = dma_map_page(&gp->pdev->dev,
1041 virt_to_page(skb->data),
1042 offset_in_page(skb->data),
1043 first_len, DMA_TO_DEVICE);
1044 entry = NEXT_TX(entry);
1045
1046 for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) {
1047 const skb_frag_t *this_frag = &skb_shinfo(skb)->frags[frag];
1048 u32 len;
1049 dma_addr_t mapping;
1050 u64 this_ctrl;
1051
1052 len = skb_frag_size(this_frag);
1053 mapping = skb_frag_dma_map(&gp->pdev->dev, this_frag,
1054 0, len, DMA_TO_DEVICE);
1055 this_ctrl = ctrl;
1056 if (frag == skb_shinfo(skb)->nr_frags - 1)
1057 this_ctrl |= TXDCTRL_EOF;
1058
1059 txd = &gp->init_block->txd[entry];
1060 txd->buffer = cpu_to_le64(mapping);
1061 dma_wmb();
1062 txd->control_word = cpu_to_le64(this_ctrl | len);
1063
1064 if (gem_intme(entry))
1065 intme |= TXDCTRL_INTME;
1066
1067 entry = NEXT_TX(entry);
1068 }
1069 txd = &gp->init_block->txd[first_entry];
1070 txd->buffer = cpu_to_le64(first_mapping);
1071 dma_wmb();
1072 txd->control_word =
1073 cpu_to_le64(ctrl | TXDCTRL_SOF | intme | first_len);
1074 }
1075
1076 gp->tx_new = entry;
1077 if (unlikely(TX_BUFFS_AVAIL(gp) <= (MAX_SKB_FRAGS + 1))) {
1078 netif_stop_queue(dev);
1079
1080 /* netif_stop_queue() must be done before checking
1081 * tx index in TX_BUFFS_AVAIL() below, because
1082 * in gem_tx(), we update tx_old before checking for
1083 * netif_queue_stopped().
1084 */
1085 smp_mb();
1086 if (TX_BUFFS_AVAIL(gp) > (MAX_SKB_FRAGS + 1))
1087 netif_wake_queue(dev);
1088 }
1089 if (netif_msg_tx_queued(gp))
1090 printk(KERN_DEBUG "%s: tx queued, slot %d, skblen %d\n",
1091 dev->name, entry, skb->len);
1092 mb();
1093 writel(gp->tx_new, gp->regs + TXDMA_KICK);
1094
1095 return NETDEV_TX_OK;
1096}
1097
1098static void gem_pcs_reset(struct gem *gp)
1099{
1100 int limit;
1101 u32 val;
1102
1103 /* Reset PCS unit. */
1104 val = readl(gp->regs + PCS_MIICTRL);
1105 val |= PCS_MIICTRL_RST;
1106 writel(val, gp->regs + PCS_MIICTRL);
1107
1108 limit = 32;
1109 while (readl(gp->regs + PCS_MIICTRL) & PCS_MIICTRL_RST) {
1110 udelay(100);
1111 if (limit-- <= 0)
1112 break;
1113 }
1114 if (limit < 0)
1115 netdev_warn(gp->dev, "PCS reset bit would not clear\n");
1116}
1117
1118static void gem_pcs_reinit_adv(struct gem *gp)
1119{
1120 u32 val;
1121
1122 /* Make sure PCS is disabled while changing advertisement
1123 * configuration.
1124 */
1125 val = readl(gp->regs + PCS_CFG);
1126 val &= ~(PCS_CFG_ENABLE | PCS_CFG_TO);
1127 writel(val, gp->regs + PCS_CFG);
1128
1129 /* Advertise all capabilities except asymmetric
1130 * pause.
1131 */
1132 val = readl(gp->regs + PCS_MIIADV);
1133 val |= (PCS_MIIADV_FD | PCS_MIIADV_HD |
1134 PCS_MIIADV_SP | PCS_MIIADV_AP);
1135 writel(val, gp->regs + PCS_MIIADV);
1136
1137 /* Enable and restart auto-negotiation, disable wrapback/loopback,
1138 * and re-enable PCS.
1139 */
1140 val = readl(gp->regs + PCS_MIICTRL);
1141 val |= (PCS_MIICTRL_RAN | PCS_MIICTRL_ANE);
1142 val &= ~PCS_MIICTRL_WB;
1143 writel(val, gp->regs + PCS_MIICTRL);
1144
1145 val = readl(gp->regs + PCS_CFG);
1146 val |= PCS_CFG_ENABLE;
1147 writel(val, gp->regs + PCS_CFG);
1148
1149 /* Make sure serialink loopback is off. The meaning
1150 * of this bit is logically inverted based upon whether
1151 * you are in Serialink or SERDES mode.
1152 */
1153 val = readl(gp->regs + PCS_SCTRL);
1154 if (gp->phy_type == phy_serialink)
1155 val &= ~PCS_SCTRL_LOOP;
1156 else
1157 val |= PCS_SCTRL_LOOP;
1158 writel(val, gp->regs + PCS_SCTRL);
1159}
1160
1161#define STOP_TRIES 32
1162
1163static void gem_reset(struct gem *gp)
1164{
1165 int limit;
1166 u32 val;
1167
1168 /* Make sure we won't get any more interrupts */
1169 writel(0xffffffff, gp->regs + GREG_IMASK);
1170
1171 /* Reset the chip */
1172 writel(gp->swrst_base | GREG_SWRST_TXRST | GREG_SWRST_RXRST,
1173 gp->regs + GREG_SWRST);
1174
1175 limit = STOP_TRIES;
1176
1177 do {
1178 udelay(20);
1179 val = readl(gp->regs + GREG_SWRST);
1180 if (limit-- <= 0)
1181 break;
1182 } while (val & (GREG_SWRST_TXRST | GREG_SWRST_RXRST));
1183
1184 if (limit < 0)
1185 netdev_err(gp->dev, "SW reset is ghetto\n");
1186
1187 if (gp->phy_type == phy_serialink || gp->phy_type == phy_serdes)
1188 gem_pcs_reinit_adv(gp);
1189}
1190
1191static void gem_start_dma(struct gem *gp)
1192{
1193 u32 val;
1194
1195 /* We are ready to rock, turn everything on. */
1196 val = readl(gp->regs + TXDMA_CFG);
1197 writel(val | TXDMA_CFG_ENABLE, gp->regs + TXDMA_CFG);
1198 val = readl(gp->regs + RXDMA_CFG);
1199 writel(val | RXDMA_CFG_ENABLE, gp->regs + RXDMA_CFG);
1200 val = readl(gp->regs + MAC_TXCFG);
1201 writel(val | MAC_TXCFG_ENAB, gp->regs + MAC_TXCFG);
1202 val = readl(gp->regs + MAC_RXCFG);
1203 writel(val | MAC_RXCFG_ENAB, gp->regs + MAC_RXCFG);
1204
1205 (void) readl(gp->regs + MAC_RXCFG);
1206 udelay(100);
1207
1208 gem_enable_ints(gp);
1209
1210 writel(RX_RING_SIZE - 4, gp->regs + RXDMA_KICK);
1211}
1212
1213/* DMA won't be actually stopped before about 4ms tho ...
1214 */
1215static void gem_stop_dma(struct gem *gp)
1216{
1217 u32 val;
1218
1219 /* We are done rocking, turn everything off. */
1220 val = readl(gp->regs + TXDMA_CFG);
1221 writel(val & ~TXDMA_CFG_ENABLE, gp->regs + TXDMA_CFG);
1222 val = readl(gp->regs + RXDMA_CFG);
1223 writel(val & ~RXDMA_CFG_ENABLE, gp->regs + RXDMA_CFG);
1224 val = readl(gp->regs + MAC_TXCFG);
1225 writel(val & ~MAC_TXCFG_ENAB, gp->regs + MAC_TXCFG);
1226 val = readl(gp->regs + MAC_RXCFG);
1227 writel(val & ~MAC_RXCFG_ENAB, gp->regs + MAC_RXCFG);
1228
1229 (void) readl(gp->regs + MAC_RXCFG);
1230
1231 /* Need to wait a bit ... done by the caller */
1232}
1233
1234
1235// XXX dbl check what that function should do when called on PCS PHY
1236static void gem_begin_auto_negotiation(struct gem *gp,
1237 const struct ethtool_link_ksettings *ep)
1238{
1239 u32 advertise, features;
1240 int autoneg;
1241 int speed;
1242 int duplex;
1243 u32 advertising;
1244
1245 if (ep)
1246 ethtool_convert_link_mode_to_legacy_u32(
1247 &advertising, ep->link_modes.advertising);
1248
1249 if (gp->phy_type != phy_mii_mdio0 &&
1250 gp->phy_type != phy_mii_mdio1)
1251 goto non_mii;
1252
1253 /* Setup advertise */
1254 if (found_mii_phy(gp))
1255 features = gp->phy_mii.def->features;
1256 else
1257 features = 0;
1258
1259 advertise = features & ADVERTISE_MASK;
1260 if (gp->phy_mii.advertising != 0)
1261 advertise &= gp->phy_mii.advertising;
1262
1263 autoneg = gp->want_autoneg;
1264 speed = gp->phy_mii.speed;
1265 duplex = gp->phy_mii.duplex;
1266
1267 /* Setup link parameters */
1268 if (!ep)
1269 goto start_aneg;
1270 if (ep->base.autoneg == AUTONEG_ENABLE) {
1271 advertise = advertising;
1272 autoneg = 1;
1273 } else {
1274 autoneg = 0;
1275 speed = ep->base.speed;
1276 duplex = ep->base.duplex;
1277 }
1278
1279start_aneg:
1280 /* Sanitize settings based on PHY capabilities */
1281 if ((features & SUPPORTED_Autoneg) == 0)
1282 autoneg = 0;
1283 if (speed == SPEED_1000 &&
1284 !(features & (SUPPORTED_1000baseT_Half | SUPPORTED_1000baseT_Full)))
1285 speed = SPEED_100;
1286 if (speed == SPEED_100 &&
1287 !(features & (SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full)))
1288 speed = SPEED_10;
1289 if (duplex == DUPLEX_FULL &&
1290 !(features & (SUPPORTED_1000baseT_Full |
1291 SUPPORTED_100baseT_Full |
1292 SUPPORTED_10baseT_Full)))
1293 duplex = DUPLEX_HALF;
1294 if (speed == 0)
1295 speed = SPEED_10;
1296
1297 /* If we are asleep, we don't try to actually setup the PHY, we
1298 * just store the settings
1299 */
1300 if (!netif_device_present(gp->dev)) {
1301 gp->phy_mii.autoneg = gp->want_autoneg = autoneg;
1302 gp->phy_mii.speed = speed;
1303 gp->phy_mii.duplex = duplex;
1304 return;
1305 }
1306
1307 /* Configure PHY & start aneg */
1308 gp->want_autoneg = autoneg;
1309 if (autoneg) {
1310 if (found_mii_phy(gp))
1311 gp->phy_mii.def->ops->setup_aneg(&gp->phy_mii, advertise);
1312 gp->lstate = link_aneg;
1313 } else {
1314 if (found_mii_phy(gp))
1315 gp->phy_mii.def->ops->setup_forced(&gp->phy_mii, speed, duplex);
1316 gp->lstate = link_force_ok;
1317 }
1318
1319non_mii:
1320 gp->timer_ticks = 0;
1321 mod_timer(&gp->link_timer, jiffies + ((12 * HZ) / 10));
1322}
1323
1324/* A link-up condition has occurred, initialize and enable the
1325 * rest of the chip.
1326 */
1327static int gem_set_link_modes(struct gem *gp)
1328{
1329 struct netdev_queue *txq = netdev_get_tx_queue(gp->dev, 0);
1330 int full_duplex, speed, pause;
1331 u32 val;
1332
1333 full_duplex = 0;
1334 speed = SPEED_10;
1335 pause = 0;
1336
1337 if (found_mii_phy(gp)) {
1338 if (gp->phy_mii.def->ops->read_link(&gp->phy_mii))
1339 return 1;
1340 full_duplex = (gp->phy_mii.duplex == DUPLEX_FULL);
1341 speed = gp->phy_mii.speed;
1342 pause = gp->phy_mii.pause;
1343 } else if (gp->phy_type == phy_serialink ||
1344 gp->phy_type == phy_serdes) {
1345 u32 pcs_lpa = readl(gp->regs + PCS_MIILP);
1346
1347 if ((pcs_lpa & PCS_MIIADV_FD) || gp->phy_type == phy_serdes)
1348 full_duplex = 1;
1349 speed = SPEED_1000;
1350 }
1351
1352 netif_info(gp, link, gp->dev, "Link is up at %d Mbps, %s-duplex\n",
1353 speed, (full_duplex ? "full" : "half"));
1354
1355
1356 /* We take the tx queue lock to avoid collisions between
1357 * this code, the tx path and the NAPI-driven error path
1358 */
1359 __netif_tx_lock(txq, smp_processor_id());
1360
1361 val = (MAC_TXCFG_EIPG0 | MAC_TXCFG_NGU);
1362 if (full_duplex) {
1363 val |= (MAC_TXCFG_ICS | MAC_TXCFG_ICOLL);
1364 } else {
1365 /* MAC_TXCFG_NBO must be zero. */
1366 }
1367 writel(val, gp->regs + MAC_TXCFG);
1368
1369 val = (MAC_XIFCFG_OE | MAC_XIFCFG_LLED);
1370 if (!full_duplex &&
1371 (gp->phy_type == phy_mii_mdio0 ||
1372 gp->phy_type == phy_mii_mdio1)) {
1373 val |= MAC_XIFCFG_DISE;
1374 } else if (full_duplex) {
1375 val |= MAC_XIFCFG_FLED;
1376 }
1377
1378 if (speed == SPEED_1000)
1379 val |= (MAC_XIFCFG_GMII);
1380
1381 writel(val, gp->regs + MAC_XIFCFG);
1382
1383 /* If gigabit and half-duplex, enable carrier extension
1384 * mode. Else, disable it.
1385 */
1386 if (speed == SPEED_1000 && !full_duplex) {
1387 val = readl(gp->regs + MAC_TXCFG);
1388 writel(val | MAC_TXCFG_TCE, gp->regs + MAC_TXCFG);
1389
1390 val = readl(gp->regs + MAC_RXCFG);
1391 writel(val | MAC_RXCFG_RCE, gp->regs + MAC_RXCFG);
1392 } else {
1393 val = readl(gp->regs + MAC_TXCFG);
1394 writel(val & ~MAC_TXCFG_TCE, gp->regs + MAC_TXCFG);
1395
1396 val = readl(gp->regs + MAC_RXCFG);
1397 writel(val & ~MAC_RXCFG_RCE, gp->regs + MAC_RXCFG);
1398 }
1399
1400 if (gp->phy_type == phy_serialink ||
1401 gp->phy_type == phy_serdes) {
1402 u32 pcs_lpa = readl(gp->regs + PCS_MIILP);
1403
1404 if (pcs_lpa & (PCS_MIIADV_SP | PCS_MIIADV_AP))
1405 pause = 1;
1406 }
1407
1408 if (!full_duplex)
1409 writel(512, gp->regs + MAC_STIME);
1410 else
1411 writel(64, gp->regs + MAC_STIME);
1412 val = readl(gp->regs + MAC_MCCFG);
1413 if (pause)
1414 val |= (MAC_MCCFG_SPE | MAC_MCCFG_RPE);
1415 else
1416 val &= ~(MAC_MCCFG_SPE | MAC_MCCFG_RPE);
1417 writel(val, gp->regs + MAC_MCCFG);
1418
1419 gem_start_dma(gp);
1420
1421 __netif_tx_unlock(txq);
1422
1423 if (netif_msg_link(gp)) {
1424 if (pause) {
1425 netdev_info(gp->dev,
1426 "Pause is enabled (rxfifo: %d off: %d on: %d)\n",
1427 gp->rx_fifo_sz,
1428 gp->rx_pause_off,
1429 gp->rx_pause_on);
1430 } else {
1431 netdev_info(gp->dev, "Pause is disabled\n");
1432 }
1433 }
1434
1435 return 0;
1436}
1437
1438static int gem_mdio_link_not_up(struct gem *gp)
1439{
1440 switch (gp->lstate) {
1441 case link_force_ret:
1442 netif_info(gp, link, gp->dev,
1443 "Autoneg failed again, keeping forced mode\n");
1444 gp->phy_mii.def->ops->setup_forced(&gp->phy_mii,
1445 gp->last_forced_speed, DUPLEX_HALF);
1446 gp->timer_ticks = 5;
1447 gp->lstate = link_force_ok;
1448 return 0;
1449 case link_aneg:
1450 /* We try forced modes after a failed aneg only on PHYs that don't
1451 * have "magic_aneg" bit set, which means they internally do the
1452 * while forced-mode thingy. On these, we just restart aneg
1453 */
1454 if (gp->phy_mii.def->magic_aneg)
1455 return 1;
1456 netif_info(gp, link, gp->dev, "switching to forced 100bt\n");
1457 /* Try forced modes. */
1458 gp->phy_mii.def->ops->setup_forced(&gp->phy_mii, SPEED_100,
1459 DUPLEX_HALF);
1460 gp->timer_ticks = 5;
1461 gp->lstate = link_force_try;
1462 return 0;
1463 case link_force_try:
1464 /* Downgrade from 100 to 10 Mbps if necessary.
1465 * If already at 10Mbps, warn user about the
1466 * situation every 10 ticks.
1467 */
1468 if (gp->phy_mii.speed == SPEED_100) {
1469 gp->phy_mii.def->ops->setup_forced(&gp->phy_mii, SPEED_10,
1470 DUPLEX_HALF);
1471 gp->timer_ticks = 5;
1472 netif_info(gp, link, gp->dev,
1473 "switching to forced 10bt\n");
1474 return 0;
1475 } else
1476 return 1;
1477 default:
1478 return 0;
1479 }
1480}
1481
1482static void gem_link_timer(struct timer_list *t)
1483{
1484 struct gem *gp = from_timer(gp, t, link_timer);
1485 struct net_device *dev = gp->dev;
1486 int restart_aneg = 0;
1487
1488 /* There's no point doing anything if we're going to be reset */
1489 if (gp->reset_task_pending)
1490 return;
1491
1492 if (gp->phy_type == phy_serialink ||
1493 gp->phy_type == phy_serdes) {
1494 u32 val = readl(gp->regs + PCS_MIISTAT);
1495
1496 if (!(val & PCS_MIISTAT_LS))
1497 val = readl(gp->regs + PCS_MIISTAT);
1498
1499 if ((val & PCS_MIISTAT_LS) != 0) {
1500 if (gp->lstate == link_up)
1501 goto restart;
1502
1503 gp->lstate = link_up;
1504 netif_carrier_on(dev);
1505 (void)gem_set_link_modes(gp);
1506 }
1507 goto restart;
1508 }
1509 if (found_mii_phy(gp) && gp->phy_mii.def->ops->poll_link(&gp->phy_mii)) {
1510 /* Ok, here we got a link. If we had it due to a forced
1511 * fallback, and we were configured for autoneg, we do
1512 * retry a short autoneg pass. If you know your hub is
1513 * broken, use ethtool ;)
1514 */
1515 if (gp->lstate == link_force_try && gp->want_autoneg) {
1516 gp->lstate = link_force_ret;
1517 gp->last_forced_speed = gp->phy_mii.speed;
1518 gp->timer_ticks = 5;
1519 if (netif_msg_link(gp))
1520 netdev_info(dev,
1521 "Got link after fallback, retrying autoneg once...\n");
1522 gp->phy_mii.def->ops->setup_aneg(&gp->phy_mii, gp->phy_mii.advertising);
1523 } else if (gp->lstate != link_up) {
1524 gp->lstate = link_up;
1525 netif_carrier_on(dev);
1526 if (gem_set_link_modes(gp))
1527 restart_aneg = 1;
1528 }
1529 } else {
1530 /* If the link was previously up, we restart the
1531 * whole process
1532 */
1533 if (gp->lstate == link_up) {
1534 gp->lstate = link_down;
1535 netif_info(gp, link, dev, "Link down\n");
1536 netif_carrier_off(dev);
1537 gem_schedule_reset(gp);
1538 /* The reset task will restart the timer */
1539 return;
1540 } else if (++gp->timer_ticks > 10) {
1541 if (found_mii_phy(gp))
1542 restart_aneg = gem_mdio_link_not_up(gp);
1543 else
1544 restart_aneg = 1;
1545 }
1546 }
1547 if (restart_aneg) {
1548 gem_begin_auto_negotiation(gp, NULL);
1549 return;
1550 }
1551restart:
1552 mod_timer(&gp->link_timer, jiffies + ((12 * HZ) / 10));
1553}
1554
1555static void gem_clean_rings(struct gem *gp)
1556{
1557 struct gem_init_block *gb = gp->init_block;
1558 struct sk_buff *skb;
1559 int i;
1560 dma_addr_t dma_addr;
1561
1562 for (i = 0; i < RX_RING_SIZE; i++) {
1563 struct gem_rxd *rxd;
1564
1565 rxd = &gb->rxd[i];
1566 if (gp->rx_skbs[i] != NULL) {
1567 skb = gp->rx_skbs[i];
1568 dma_addr = le64_to_cpu(rxd->buffer);
1569 dma_unmap_page(&gp->pdev->dev, dma_addr,
1570 RX_BUF_ALLOC_SIZE(gp),
1571 DMA_FROM_DEVICE);
1572 dev_kfree_skb_any(skb);
1573 gp->rx_skbs[i] = NULL;
1574 }
1575 rxd->status_word = 0;
1576 dma_wmb();
1577 rxd->buffer = 0;
1578 }
1579
1580 for (i = 0; i < TX_RING_SIZE; i++) {
1581 if (gp->tx_skbs[i] != NULL) {
1582 struct gem_txd *txd;
1583 int frag;
1584
1585 skb = gp->tx_skbs[i];
1586 gp->tx_skbs[i] = NULL;
1587
1588 for (frag = 0; frag <= skb_shinfo(skb)->nr_frags; frag++) {
1589 int ent = i & (TX_RING_SIZE - 1);
1590
1591 txd = &gb->txd[ent];
1592 dma_addr = le64_to_cpu(txd->buffer);
1593 dma_unmap_page(&gp->pdev->dev, dma_addr,
1594 le64_to_cpu(txd->control_word) &
1595 TXDCTRL_BUFSZ, DMA_TO_DEVICE);
1596
1597 if (frag != skb_shinfo(skb)->nr_frags)
1598 i++;
1599 }
1600 dev_kfree_skb_any(skb);
1601 }
1602 }
1603}
1604
1605static void gem_init_rings(struct gem *gp)
1606{
1607 struct gem_init_block *gb = gp->init_block;
1608 struct net_device *dev = gp->dev;
1609 int i;
1610 dma_addr_t dma_addr;
1611
1612 gp->rx_new = gp->rx_old = gp->tx_new = gp->tx_old = 0;
1613
1614 gem_clean_rings(gp);
1615
1616 gp->rx_buf_sz = max(dev->mtu + ETH_HLEN + VLAN_HLEN,
1617 (unsigned)VLAN_ETH_FRAME_LEN);
1618
1619 for (i = 0; i < RX_RING_SIZE; i++) {
1620 struct sk_buff *skb;
1621 struct gem_rxd *rxd = &gb->rxd[i];
1622
1623 skb = gem_alloc_skb(dev, RX_BUF_ALLOC_SIZE(gp), GFP_KERNEL);
1624 if (!skb) {
1625 rxd->buffer = 0;
1626 rxd->status_word = 0;
1627 continue;
1628 }
1629
1630 gp->rx_skbs[i] = skb;
1631 skb_put(skb, (gp->rx_buf_sz + RX_OFFSET));
1632 dma_addr = dma_map_page(&gp->pdev->dev,
1633 virt_to_page(skb->data),
1634 offset_in_page(skb->data),
1635 RX_BUF_ALLOC_SIZE(gp),
1636 DMA_FROM_DEVICE);
1637 rxd->buffer = cpu_to_le64(dma_addr);
1638 dma_wmb();
1639 rxd->status_word = cpu_to_le64(RXDCTRL_FRESH(gp));
1640 skb_reserve(skb, RX_OFFSET);
1641 }
1642
1643 for (i = 0; i < TX_RING_SIZE; i++) {
1644 struct gem_txd *txd = &gb->txd[i];
1645
1646 txd->control_word = 0;
1647 dma_wmb();
1648 txd->buffer = 0;
1649 }
1650 wmb();
1651}
1652
1653/* Init PHY interface and start link poll state machine */
1654static void gem_init_phy(struct gem *gp)
1655{
1656 u32 mifcfg;
1657
1658 /* Revert MIF CFG setting done on stop_phy */
1659 mifcfg = readl(gp->regs + MIF_CFG);
1660 mifcfg &= ~MIF_CFG_BBMODE;
1661 writel(mifcfg, gp->regs + MIF_CFG);
1662
1663 if (gp->pdev->vendor == PCI_VENDOR_ID_APPLE) {
1664 int i;
1665
1666 /* Those delays sucks, the HW seems to love them though, I'll
1667 * seriously consider breaking some locks here to be able
1668 * to schedule instead
1669 */
1670 for (i = 0; i < 3; i++) {
1671#ifdef CONFIG_PPC_PMAC
1672 pmac_call_feature(PMAC_FTR_GMAC_PHY_RESET, gp->of_node, 0, 0);
1673 msleep(20);
1674#endif
1675 /* Some PHYs used by apple have problem getting back to us,
1676 * we do an additional reset here
1677 */
1678 sungem_phy_write(gp, MII_BMCR, BMCR_RESET);
1679 msleep(20);
1680 if (sungem_phy_read(gp, MII_BMCR) != 0xffff)
1681 break;
1682 if (i == 2)
1683 netdev_warn(gp->dev, "GMAC PHY not responding !\n");
1684 }
1685 }
1686
1687 if (gp->pdev->vendor == PCI_VENDOR_ID_SUN &&
1688 gp->pdev->device == PCI_DEVICE_ID_SUN_GEM) {
1689 u32 val;
1690
1691 /* Init datapath mode register. */
1692 if (gp->phy_type == phy_mii_mdio0 ||
1693 gp->phy_type == phy_mii_mdio1) {
1694 val = PCS_DMODE_MGM;
1695 } else if (gp->phy_type == phy_serialink) {
1696 val = PCS_DMODE_SM | PCS_DMODE_GMOE;
1697 } else {
1698 val = PCS_DMODE_ESM;
1699 }
1700
1701 writel(val, gp->regs + PCS_DMODE);
1702 }
1703
1704 if (gp->phy_type == phy_mii_mdio0 ||
1705 gp->phy_type == phy_mii_mdio1) {
1706 /* Reset and detect MII PHY */
1707 sungem_phy_probe(&gp->phy_mii, gp->mii_phy_addr);
1708
1709 /* Init PHY */
1710 if (gp->phy_mii.def && gp->phy_mii.def->ops->init)
1711 gp->phy_mii.def->ops->init(&gp->phy_mii);
1712 } else {
1713 gem_pcs_reset(gp);
1714 gem_pcs_reinit_adv(gp);
1715 }
1716
1717 /* Default aneg parameters */
1718 gp->timer_ticks = 0;
1719 gp->lstate = link_down;
1720 netif_carrier_off(gp->dev);
1721
1722 /* Print things out */
1723 if (gp->phy_type == phy_mii_mdio0 ||
1724 gp->phy_type == phy_mii_mdio1)
1725 netdev_info(gp->dev, "Found %s PHY\n",
1726 gp->phy_mii.def ? gp->phy_mii.def->name : "no");
1727
1728 gem_begin_auto_negotiation(gp, NULL);
1729}
1730
1731static void gem_init_dma(struct gem *gp)
1732{
1733 u64 desc_dma = (u64) gp->gblock_dvma;
1734 u32 val;
1735
1736 val = (TXDMA_CFG_BASE | (0x7ff << 10) | TXDMA_CFG_PMODE);
1737 writel(val, gp->regs + TXDMA_CFG);
1738
1739 writel(desc_dma >> 32, gp->regs + TXDMA_DBHI);
1740 writel(desc_dma & 0xffffffff, gp->regs + TXDMA_DBLOW);
1741 desc_dma += (INIT_BLOCK_TX_RING_SIZE * sizeof(struct gem_txd));
1742
1743 writel(0, gp->regs + TXDMA_KICK);
1744
1745 val = (RXDMA_CFG_BASE | (RX_OFFSET << 10) |
1746 (ETH_HLEN << 13) | RXDMA_CFG_FTHRESH_128);
1747 writel(val, gp->regs + RXDMA_CFG);
1748
1749 writel(desc_dma >> 32, gp->regs + RXDMA_DBHI);
1750 writel(desc_dma & 0xffffffff, gp->regs + RXDMA_DBLOW);
1751
1752 writel(RX_RING_SIZE - 4, gp->regs + RXDMA_KICK);
1753
1754 val = (((gp->rx_pause_off / 64) << 0) & RXDMA_PTHRESH_OFF);
1755 val |= (((gp->rx_pause_on / 64) << 12) & RXDMA_PTHRESH_ON);
1756 writel(val, gp->regs + RXDMA_PTHRESH);
1757
1758 if (readl(gp->regs + GREG_BIFCFG) & GREG_BIFCFG_M66EN)
1759 writel(((5 & RXDMA_BLANK_IPKTS) |
1760 ((8 << 12) & RXDMA_BLANK_ITIME)),
1761 gp->regs + RXDMA_BLANK);
1762 else
1763 writel(((5 & RXDMA_BLANK_IPKTS) |
1764 ((4 << 12) & RXDMA_BLANK_ITIME)),
1765 gp->regs + RXDMA_BLANK);
1766}
1767
1768static u32 gem_setup_multicast(struct gem *gp)
1769{
1770 u32 rxcfg = 0;
1771 int i;
1772
1773 if ((gp->dev->flags & IFF_ALLMULTI) ||
1774 (netdev_mc_count(gp->dev) > 256)) {
1775 for (i=0; i<16; i++)
1776 writel(0xffff, gp->regs + MAC_HASH0 + (i << 2));
1777 rxcfg |= MAC_RXCFG_HFE;
1778 } else if (gp->dev->flags & IFF_PROMISC) {
1779 rxcfg |= MAC_RXCFG_PROM;
1780 } else {
1781 u16 hash_table[16];
1782 u32 crc;
1783 struct netdev_hw_addr *ha;
1784 int i;
1785
1786 memset(hash_table, 0, sizeof(hash_table));
1787 netdev_for_each_mc_addr(ha, gp->dev) {
1788 crc = ether_crc_le(6, ha->addr);
1789 crc >>= 24;
1790 hash_table[crc >> 4] |= 1 << (15 - (crc & 0xf));
1791 }
1792 for (i=0; i<16; i++)
1793 writel(hash_table[i], gp->regs + MAC_HASH0 + (i << 2));
1794 rxcfg |= MAC_RXCFG_HFE;
1795 }
1796
1797 return rxcfg;
1798}
1799
1800static void gem_init_mac(struct gem *gp)
1801{
1802 const unsigned char *e = &gp->dev->dev_addr[0];
1803
1804 writel(0x1bf0, gp->regs + MAC_SNDPAUSE);
1805
1806 writel(0x00, gp->regs + MAC_IPG0);
1807 writel(0x08, gp->regs + MAC_IPG1);
1808 writel(0x04, gp->regs + MAC_IPG2);
1809 writel(0x40, gp->regs + MAC_STIME);
1810 writel(0x40, gp->regs + MAC_MINFSZ);
1811
1812 /* Ethernet payload + header + FCS + optional VLAN tag. */
1813 writel(0x20000000 | (gp->rx_buf_sz + 4), gp->regs + MAC_MAXFSZ);
1814
1815 writel(0x07, gp->regs + MAC_PASIZE);
1816 writel(0x04, gp->regs + MAC_JAMSIZE);
1817 writel(0x10, gp->regs + MAC_ATTLIM);
1818 writel(0x8808, gp->regs + MAC_MCTYPE);
1819
1820 writel((e[5] | (e[4] << 8)) & 0x3ff, gp->regs + MAC_RANDSEED);
1821
1822 writel((e[4] << 8) | e[5], gp->regs + MAC_ADDR0);
1823 writel((e[2] << 8) | e[3], gp->regs + MAC_ADDR1);
1824 writel((e[0] << 8) | e[1], gp->regs + MAC_ADDR2);
1825
1826 writel(0, gp->regs + MAC_ADDR3);
1827 writel(0, gp->regs + MAC_ADDR4);
1828 writel(0, gp->regs + MAC_ADDR5);
1829
1830 writel(0x0001, gp->regs + MAC_ADDR6);
1831 writel(0xc200, gp->regs + MAC_ADDR7);
1832 writel(0x0180, gp->regs + MAC_ADDR8);
1833
1834 writel(0, gp->regs + MAC_AFILT0);
1835 writel(0, gp->regs + MAC_AFILT1);
1836 writel(0, gp->regs + MAC_AFILT2);
1837 writel(0, gp->regs + MAC_AF21MSK);
1838 writel(0, gp->regs + MAC_AF0MSK);
1839
1840 gp->mac_rx_cfg = gem_setup_multicast(gp);
1841#ifdef STRIP_FCS
1842 gp->mac_rx_cfg |= MAC_RXCFG_SFCS;
1843#endif
1844 writel(0, gp->regs + MAC_NCOLL);
1845 writel(0, gp->regs + MAC_FASUCC);
1846 writel(0, gp->regs + MAC_ECOLL);
1847 writel(0, gp->regs + MAC_LCOLL);
1848 writel(0, gp->regs + MAC_DTIMER);
1849 writel(0, gp->regs + MAC_PATMPS);
1850 writel(0, gp->regs + MAC_RFCTR);
1851 writel(0, gp->regs + MAC_LERR);
1852 writel(0, gp->regs + MAC_AERR);
1853 writel(0, gp->regs + MAC_FCSERR);
1854 writel(0, gp->regs + MAC_RXCVERR);
1855
1856 /* Clear RX/TX/MAC/XIF config, we will set these up and enable
1857 * them once a link is established.
1858 */
1859 writel(0, gp->regs + MAC_TXCFG);
1860 writel(gp->mac_rx_cfg, gp->regs + MAC_RXCFG);
1861 writel(0, gp->regs + MAC_MCCFG);
1862 writel(0, gp->regs + MAC_XIFCFG);
1863
1864 /* Setup MAC interrupts. We want to get all of the interesting
1865 * counter expiration events, but we do not want to hear about
1866 * normal rx/tx as the DMA engine tells us that.
1867 */
1868 writel(MAC_TXSTAT_XMIT, gp->regs + MAC_TXMASK);
1869 writel(MAC_RXSTAT_RCV, gp->regs + MAC_RXMASK);
1870
1871 /* Don't enable even the PAUSE interrupts for now, we
1872 * make no use of those events other than to record them.
1873 */
1874 writel(0xffffffff, gp->regs + MAC_MCMASK);
1875
1876 /* Don't enable GEM's WOL in normal operations
1877 */
1878 if (gp->has_wol)
1879 writel(0, gp->regs + WOL_WAKECSR);
1880}
1881
1882static void gem_init_pause_thresholds(struct gem *gp)
1883{
1884 u32 cfg;
1885
1886 /* Calculate pause thresholds. Setting the OFF threshold to the
1887 * full RX fifo size effectively disables PAUSE generation which
1888 * is what we do for 10/100 only GEMs which have FIFOs too small
1889 * to make real gains from PAUSE.
1890 */
1891 if (gp->rx_fifo_sz <= (2 * 1024)) {
1892 gp->rx_pause_off = gp->rx_pause_on = gp->rx_fifo_sz;
1893 } else {
1894 int max_frame = (gp->rx_buf_sz + 4 + 64) & ~63;
1895 int off = (gp->rx_fifo_sz - (max_frame * 2));
1896 int on = off - max_frame;
1897
1898 gp->rx_pause_off = off;
1899 gp->rx_pause_on = on;
1900 }
1901
1902
1903 /* Configure the chip "burst" DMA mode & enable some
1904 * HW bug fixes on Apple version
1905 */
1906 cfg = 0;
1907 if (gp->pdev->vendor == PCI_VENDOR_ID_APPLE)
1908 cfg |= GREG_CFG_RONPAULBIT | GREG_CFG_ENBUG2FIX;
1909#if !defined(CONFIG_SPARC64) && !defined(CONFIG_ALPHA)
1910 cfg |= GREG_CFG_IBURST;
1911#endif
1912 cfg |= ((31 << 1) & GREG_CFG_TXDMALIM);
1913 cfg |= ((31 << 6) & GREG_CFG_RXDMALIM);
1914 writel(cfg, gp->regs + GREG_CFG);
1915
1916 /* If Infinite Burst didn't stick, then use different
1917 * thresholds (and Apple bug fixes don't exist)
1918 */
1919 if (!(readl(gp->regs + GREG_CFG) & GREG_CFG_IBURST)) {
1920 cfg = ((2 << 1) & GREG_CFG_TXDMALIM);
1921 cfg |= ((8 << 6) & GREG_CFG_RXDMALIM);
1922 writel(cfg, gp->regs + GREG_CFG);
1923 }
1924}
1925
1926static int gem_check_invariants(struct gem *gp)
1927{
1928 struct pci_dev *pdev = gp->pdev;
1929 u32 mif_cfg;
1930
1931 /* On Apple's sungem, we can't rely on registers as the chip
1932 * was been powered down by the firmware. The PHY is looked
1933 * up later on.
1934 */
1935 if (pdev->vendor == PCI_VENDOR_ID_APPLE) {
1936 gp->phy_type = phy_mii_mdio0;
1937 gp->tx_fifo_sz = readl(gp->regs + TXDMA_FSZ) * 64;
1938 gp->rx_fifo_sz = readl(gp->regs + RXDMA_FSZ) * 64;
1939 gp->swrst_base = 0;
1940
1941 mif_cfg = readl(gp->regs + MIF_CFG);
1942 mif_cfg &= ~(MIF_CFG_PSELECT|MIF_CFG_POLL|MIF_CFG_BBMODE|MIF_CFG_MDI1);
1943 mif_cfg |= MIF_CFG_MDI0;
1944 writel(mif_cfg, gp->regs + MIF_CFG);
1945 writel(PCS_DMODE_MGM, gp->regs + PCS_DMODE);
1946 writel(MAC_XIFCFG_OE, gp->regs + MAC_XIFCFG);
1947
1948 /* We hard-code the PHY address so we can properly bring it out of
1949 * reset later on, we can't really probe it at this point, though
1950 * that isn't an issue.
1951 */
1952 if (gp->pdev->device == PCI_DEVICE_ID_APPLE_K2_GMAC)
1953 gp->mii_phy_addr = 1;
1954 else
1955 gp->mii_phy_addr = 0;
1956
1957 return 0;
1958 }
1959
1960 mif_cfg = readl(gp->regs + MIF_CFG);
1961
1962 if (pdev->vendor == PCI_VENDOR_ID_SUN &&
1963 pdev->device == PCI_DEVICE_ID_SUN_RIO_GEM) {
1964 /* One of the MII PHYs _must_ be present
1965 * as this chip has no gigabit PHY.
1966 */
1967 if ((mif_cfg & (MIF_CFG_MDI0 | MIF_CFG_MDI1)) == 0) {
1968 pr_err("RIO GEM lacks MII phy, mif_cfg[%08x]\n",
1969 mif_cfg);
1970 return -1;
1971 }
1972 }
1973
1974 /* Determine initial PHY interface type guess. MDIO1 is the
1975 * external PHY and thus takes precedence over MDIO0.
1976 */
1977
1978 if (mif_cfg & MIF_CFG_MDI1) {
1979 gp->phy_type = phy_mii_mdio1;
1980 mif_cfg |= MIF_CFG_PSELECT;
1981 writel(mif_cfg, gp->regs + MIF_CFG);
1982 } else if (mif_cfg & MIF_CFG_MDI0) {
1983 gp->phy_type = phy_mii_mdio0;
1984 mif_cfg &= ~MIF_CFG_PSELECT;
1985 writel(mif_cfg, gp->regs + MIF_CFG);
1986 } else {
1987#ifdef CONFIG_SPARC
1988 const char *p;
1989
1990 p = of_get_property(gp->of_node, "shared-pins", NULL);
1991 if (p && !strcmp(p, "serdes"))
1992 gp->phy_type = phy_serdes;
1993 else
1994#endif
1995 gp->phy_type = phy_serialink;
1996 }
1997 if (gp->phy_type == phy_mii_mdio1 ||
1998 gp->phy_type == phy_mii_mdio0) {
1999 int i;
2000
2001 for (i = 0; i < 32; i++) {
2002 gp->mii_phy_addr = i;
2003 if (sungem_phy_read(gp, MII_BMCR) != 0xffff)
2004 break;
2005 }
2006 if (i == 32) {
2007 if (pdev->device != PCI_DEVICE_ID_SUN_GEM) {
2008 pr_err("RIO MII phy will not respond\n");
2009 return -1;
2010 }
2011 gp->phy_type = phy_serdes;
2012 }
2013 }
2014
2015 /* Fetch the FIFO configurations now too. */
2016 gp->tx_fifo_sz = readl(gp->regs + TXDMA_FSZ) * 64;
2017 gp->rx_fifo_sz = readl(gp->regs + RXDMA_FSZ) * 64;
2018
2019 if (pdev->vendor == PCI_VENDOR_ID_SUN) {
2020 if (pdev->device == PCI_DEVICE_ID_SUN_GEM) {
2021 if (gp->tx_fifo_sz != (9 * 1024) ||
2022 gp->rx_fifo_sz != (20 * 1024)) {
2023 pr_err("GEM has bogus fifo sizes tx(%d) rx(%d)\n",
2024 gp->tx_fifo_sz, gp->rx_fifo_sz);
2025 return -1;
2026 }
2027 gp->swrst_base = 0;
2028 } else {
2029 if (gp->tx_fifo_sz != (2 * 1024) ||
2030 gp->rx_fifo_sz != (2 * 1024)) {
2031 pr_err("RIO GEM has bogus fifo sizes tx(%d) rx(%d)\n",
2032 gp->tx_fifo_sz, gp->rx_fifo_sz);
2033 return -1;
2034 }
2035 gp->swrst_base = (64 / 4) << GREG_SWRST_CACHE_SHIFT;
2036 }
2037 }
2038
2039 return 0;
2040}
2041
2042static void gem_reinit_chip(struct gem *gp)
2043{
2044 /* Reset the chip */
2045 gem_reset(gp);
2046
2047 /* Make sure ints are disabled */
2048 gem_disable_ints(gp);
2049
2050 /* Allocate & setup ring buffers */
2051 gem_init_rings(gp);
2052
2053 /* Configure pause thresholds */
2054 gem_init_pause_thresholds(gp);
2055
2056 /* Init DMA & MAC engines */
2057 gem_init_dma(gp);
2058 gem_init_mac(gp);
2059}
2060
2061
2062static void gem_stop_phy(struct gem *gp, int wol)
2063{
2064 u32 mifcfg;
2065
2066 /* Let the chip settle down a bit, it seems that helps
2067 * for sleep mode on some models
2068 */
2069 msleep(10);
2070
2071 /* Make sure we aren't polling PHY status change. We
2072 * don't currently use that feature though
2073 */
2074 mifcfg = readl(gp->regs + MIF_CFG);
2075 mifcfg &= ~MIF_CFG_POLL;
2076 writel(mifcfg, gp->regs + MIF_CFG);
2077
2078 if (wol && gp->has_wol) {
2079 const unsigned char *e = &gp->dev->dev_addr[0];
2080 u32 csr;
2081
2082 /* Setup wake-on-lan for MAGIC packet */
2083 writel(MAC_RXCFG_HFE | MAC_RXCFG_SFCS | MAC_RXCFG_ENAB,
2084 gp->regs + MAC_RXCFG);
2085 writel((e[4] << 8) | e[5], gp->regs + WOL_MATCH0);
2086 writel((e[2] << 8) | e[3], gp->regs + WOL_MATCH1);
2087 writel((e[0] << 8) | e[1], gp->regs + WOL_MATCH2);
2088
2089 writel(WOL_MCOUNT_N | WOL_MCOUNT_M, gp->regs + WOL_MCOUNT);
2090 csr = WOL_WAKECSR_ENABLE;
2091 if ((readl(gp->regs + MAC_XIFCFG) & MAC_XIFCFG_GMII) == 0)
2092 csr |= WOL_WAKECSR_MII;
2093 writel(csr, gp->regs + WOL_WAKECSR);
2094 } else {
2095 writel(0, gp->regs + MAC_RXCFG);
2096 (void)readl(gp->regs + MAC_RXCFG);
2097 /* Machine sleep will die in strange ways if we
2098 * dont wait a bit here, looks like the chip takes
2099 * some time to really shut down
2100 */
2101 msleep(10);
2102 }
2103
2104 writel(0, gp->regs + MAC_TXCFG);
2105 writel(0, gp->regs + MAC_XIFCFG);
2106 writel(0, gp->regs + TXDMA_CFG);
2107 writel(0, gp->regs + RXDMA_CFG);
2108
2109 if (!wol) {
2110 gem_reset(gp);
2111 writel(MAC_TXRST_CMD, gp->regs + MAC_TXRST);
2112 writel(MAC_RXRST_CMD, gp->regs + MAC_RXRST);
2113
2114 if (found_mii_phy(gp) && gp->phy_mii.def->ops->suspend)
2115 gp->phy_mii.def->ops->suspend(&gp->phy_mii);
2116
2117 /* According to Apple, we must set the MDIO pins to this begnign
2118 * state or we may 1) eat more current, 2) damage some PHYs
2119 */
2120 writel(mifcfg | MIF_CFG_BBMODE, gp->regs + MIF_CFG);
2121 writel(0, gp->regs + MIF_BBCLK);
2122 writel(0, gp->regs + MIF_BBDATA);
2123 writel(0, gp->regs + MIF_BBOENAB);
2124 writel(MAC_XIFCFG_GMII | MAC_XIFCFG_LBCK, gp->regs + MAC_XIFCFG);
2125 (void) readl(gp->regs + MAC_XIFCFG);
2126 }
2127}
2128
2129static int gem_do_start(struct net_device *dev)
2130{
2131 struct gem *gp = netdev_priv(dev);
2132 int rc;
2133
2134 pci_set_master(gp->pdev);
2135
2136 /* Init & setup chip hardware */
2137 gem_reinit_chip(gp);
2138
2139 /* An interrupt might come in handy */
2140 rc = request_irq(gp->pdev->irq, gem_interrupt,
2141 IRQF_SHARED, dev->name, (void *)dev);
2142 if (rc) {
2143 netdev_err(dev, "failed to request irq !\n");
2144
2145 gem_reset(gp);
2146 gem_clean_rings(gp);
2147 gem_put_cell(gp);
2148 return rc;
2149 }
2150
2151 /* Mark us as attached again if we come from resume(), this has
2152 * no effect if we weren't detached and needs to be done now.
2153 */
2154 netif_device_attach(dev);
2155
2156 /* Restart NAPI & queues */
2157 gem_netif_start(gp);
2158
2159 /* Detect & init PHY, start autoneg etc... this will
2160 * eventually result in starting DMA operations when
2161 * the link is up
2162 */
2163 gem_init_phy(gp);
2164
2165 return 0;
2166}
2167
2168static void gem_do_stop(struct net_device *dev, int wol)
2169{
2170 struct gem *gp = netdev_priv(dev);
2171
2172 /* Stop NAPI and stop tx queue */
2173 gem_netif_stop(gp);
2174
2175 /* Make sure ints are disabled. We don't care about
2176 * synchronizing as NAPI is disabled, thus a stray
2177 * interrupt will do nothing bad (our irq handler
2178 * just schedules NAPI)
2179 */
2180 gem_disable_ints(gp);
2181
2182 /* Stop the link timer */
2183 del_timer_sync(&gp->link_timer);
2184
2185 /* We cannot cancel the reset task while holding the
2186 * rtnl lock, we'd get an A->B / B->A deadlock stituation
2187 * if we did. This is not an issue however as the reset
2188 * task is synchronized vs. us (rtnl_lock) and will do
2189 * nothing if the device is down or suspended. We do
2190 * still clear reset_task_pending to avoid a spurrious
2191 * reset later on in case we do resume before it gets
2192 * scheduled.
2193 */
2194 gp->reset_task_pending = 0;
2195
2196 /* If we are going to sleep with WOL */
2197 gem_stop_dma(gp);
2198 msleep(10);
2199 if (!wol)
2200 gem_reset(gp);
2201 msleep(10);
2202
2203 /* Get rid of rings */
2204 gem_clean_rings(gp);
2205
2206 /* No irq needed anymore */
2207 free_irq(gp->pdev->irq, (void *) dev);
2208
2209 /* Shut the PHY down eventually and setup WOL */
2210 gem_stop_phy(gp, wol);
2211}
2212
2213static void gem_reset_task(struct work_struct *work)
2214{
2215 struct gem *gp = container_of(work, struct gem, reset_task);
2216
2217 /* Lock out the network stack (essentially shield ourselves
2218 * against a racing open, close, control call, or suspend
2219 */
2220 rtnl_lock();
2221
2222 /* Skip the reset task if suspended or closed, or if it's
2223 * been cancelled by gem_do_stop (see comment there)
2224 */
2225 if (!netif_device_present(gp->dev) ||
2226 !netif_running(gp->dev) ||
2227 !gp->reset_task_pending) {
2228 rtnl_unlock();
2229 return;
2230 }
2231
2232 /* Stop the link timer */
2233 del_timer_sync(&gp->link_timer);
2234
2235 /* Stop NAPI and tx */
2236 gem_netif_stop(gp);
2237
2238 /* Reset the chip & rings */
2239 gem_reinit_chip(gp);
2240 if (gp->lstate == link_up)
2241 gem_set_link_modes(gp);
2242
2243 /* Restart NAPI and Tx */
2244 gem_netif_start(gp);
2245
2246 /* We are back ! */
2247 gp->reset_task_pending = 0;
2248
2249 /* If the link is not up, restart autoneg, else restart the
2250 * polling timer
2251 */
2252 if (gp->lstate != link_up)
2253 gem_begin_auto_negotiation(gp, NULL);
2254 else
2255 mod_timer(&gp->link_timer, jiffies + ((12 * HZ) / 10));
2256
2257 rtnl_unlock();
2258}
2259
2260static int gem_open(struct net_device *dev)
2261{
2262 struct gem *gp = netdev_priv(dev);
2263 int rc;
2264
2265 /* We allow open while suspended, we just do nothing,
2266 * the chip will be initialized in resume()
2267 */
2268 if (netif_device_present(dev)) {
2269 /* Enable the cell */
2270 gem_get_cell(gp);
2271
2272 /* Make sure PCI access and bus master are enabled */
2273 rc = pci_enable_device(gp->pdev);
2274 if (rc) {
2275 netdev_err(dev, "Failed to enable chip on PCI bus !\n");
2276
2277 /* Put cell and forget it for now, it will be considered
2278 *as still asleep, a new sleep cycle may bring it back
2279 */
2280 gem_put_cell(gp);
2281 return -ENXIO;
2282 }
2283 return gem_do_start(dev);
2284 }
2285
2286 return 0;
2287}
2288
2289static int gem_close(struct net_device *dev)
2290{
2291 struct gem *gp = netdev_priv(dev);
2292
2293 if (netif_device_present(dev)) {
2294 gem_do_stop(dev, 0);
2295
2296 /* Make sure bus master is disabled */
2297 pci_disable_device(gp->pdev);
2298
2299 /* Cell not needed neither if no WOL */
2300 if (!gp->asleep_wol)
2301 gem_put_cell(gp);
2302 }
2303 return 0;
2304}
2305
2306static int __maybe_unused gem_suspend(struct device *dev_d)
2307{
2308 struct net_device *dev = dev_get_drvdata(dev_d);
2309 struct gem *gp = netdev_priv(dev);
2310
2311 /* Lock the network stack first to avoid racing with open/close,
2312 * reset task and setting calls
2313 */
2314 rtnl_lock();
2315
2316 /* Not running, mark ourselves non-present, no need for
2317 * a lock here
2318 */
2319 if (!netif_running(dev)) {
2320 netif_device_detach(dev);
2321 rtnl_unlock();
2322 return 0;
2323 }
2324 netdev_info(dev, "suspending, WakeOnLan %s\n",
2325 (gp->wake_on_lan && netif_running(dev)) ?
2326 "enabled" : "disabled");
2327
2328 /* Tell the network stack we're gone. gem_do_stop() below will
2329 * synchronize with TX, stop NAPI etc...
2330 */
2331 netif_device_detach(dev);
2332
2333 /* Switch off chip, remember WOL setting */
2334 gp->asleep_wol = !!gp->wake_on_lan;
2335 gem_do_stop(dev, gp->asleep_wol);
2336
2337 /* Cell not needed neither if no WOL */
2338 if (!gp->asleep_wol)
2339 gem_put_cell(gp);
2340
2341 /* Unlock the network stack */
2342 rtnl_unlock();
2343
2344 return 0;
2345}
2346
2347static int __maybe_unused gem_resume(struct device *dev_d)
2348{
2349 struct net_device *dev = dev_get_drvdata(dev_d);
2350 struct gem *gp = netdev_priv(dev);
2351
2352 /* See locking comment in gem_suspend */
2353 rtnl_lock();
2354
2355 /* Not running, mark ourselves present, no need for
2356 * a lock here
2357 */
2358 if (!netif_running(dev)) {
2359 netif_device_attach(dev);
2360 rtnl_unlock();
2361 return 0;
2362 }
2363
2364 /* Enable the cell */
2365 gem_get_cell(gp);
2366
2367 /* Restart chip. If that fails there isn't much we can do, we
2368 * leave things stopped.
2369 */
2370 gem_do_start(dev);
2371
2372 /* If we had WOL enabled, the cell clock was never turned off during
2373 * sleep, so we end up beeing unbalanced. Fix that here
2374 */
2375 if (gp->asleep_wol)
2376 gem_put_cell(gp);
2377
2378 /* Unlock the network stack */
2379 rtnl_unlock();
2380
2381 return 0;
2382}
2383
2384static struct net_device_stats *gem_get_stats(struct net_device *dev)
2385{
2386 struct gem *gp = netdev_priv(dev);
2387
2388 /* I have seen this being called while the PM was in progress,
2389 * so we shield against this. Let's also not poke at registers
2390 * while the reset task is going on.
2391 *
2392 * TODO: Move stats collection elsewhere (link timer ?) and
2393 * make this a nop to avoid all those synchro issues
2394 */
2395 if (!netif_device_present(dev) || !netif_running(dev))
2396 goto bail;
2397
2398 /* Better safe than sorry... */
2399 if (WARN_ON(!gp->cell_enabled))
2400 goto bail;
2401
2402 dev->stats.rx_crc_errors += readl(gp->regs + MAC_FCSERR);
2403 writel(0, gp->regs + MAC_FCSERR);
2404
2405 dev->stats.rx_frame_errors += readl(gp->regs + MAC_AERR);
2406 writel(0, gp->regs + MAC_AERR);
2407
2408 dev->stats.rx_length_errors += readl(gp->regs + MAC_LERR);
2409 writel(0, gp->regs + MAC_LERR);
2410
2411 dev->stats.tx_aborted_errors += readl(gp->regs + MAC_ECOLL);
2412 dev->stats.collisions +=
2413 (readl(gp->regs + MAC_ECOLL) + readl(gp->regs + MAC_LCOLL));
2414 writel(0, gp->regs + MAC_ECOLL);
2415 writel(0, gp->regs + MAC_LCOLL);
2416 bail:
2417 return &dev->stats;
2418}
2419
2420static int gem_set_mac_address(struct net_device *dev, void *addr)
2421{
2422 struct sockaddr *macaddr = (struct sockaddr *) addr;
2423 const unsigned char *e = &dev->dev_addr[0];
2424 struct gem *gp = netdev_priv(dev);
2425
2426 if (!is_valid_ether_addr(macaddr->sa_data))
2427 return -EADDRNOTAVAIL;
2428
2429 eth_hw_addr_set(dev, macaddr->sa_data);
2430
2431 /* We'll just catch it later when the device is up'd or resumed */
2432 if (!netif_running(dev) || !netif_device_present(dev))
2433 return 0;
2434
2435 /* Better safe than sorry... */
2436 if (WARN_ON(!gp->cell_enabled))
2437 return 0;
2438
2439 writel((e[4] << 8) | e[5], gp->regs + MAC_ADDR0);
2440 writel((e[2] << 8) | e[3], gp->regs + MAC_ADDR1);
2441 writel((e[0] << 8) | e[1], gp->regs + MAC_ADDR2);
2442
2443 return 0;
2444}
2445
2446static void gem_set_multicast(struct net_device *dev)
2447{
2448 struct gem *gp = netdev_priv(dev);
2449 u32 rxcfg, rxcfg_new;
2450 int limit = 10000;
2451
2452 if (!netif_running(dev) || !netif_device_present(dev))
2453 return;
2454
2455 /* Better safe than sorry... */
2456 if (gp->reset_task_pending || WARN_ON(!gp->cell_enabled))
2457 return;
2458
2459 rxcfg = readl(gp->regs + MAC_RXCFG);
2460 rxcfg_new = gem_setup_multicast(gp);
2461#ifdef STRIP_FCS
2462 rxcfg_new |= MAC_RXCFG_SFCS;
2463#endif
2464 gp->mac_rx_cfg = rxcfg_new;
2465
2466 writel(rxcfg & ~MAC_RXCFG_ENAB, gp->regs + MAC_RXCFG);
2467 while (readl(gp->regs + MAC_RXCFG) & MAC_RXCFG_ENAB) {
2468 if (!limit--)
2469 break;
2470 udelay(10);
2471 }
2472
2473 rxcfg &= ~(MAC_RXCFG_PROM | MAC_RXCFG_HFE);
2474 rxcfg |= rxcfg_new;
2475
2476 writel(rxcfg, gp->regs + MAC_RXCFG);
2477}
2478
2479/* Jumbo-grams don't seem to work :-( */
2480#define GEM_MIN_MTU ETH_MIN_MTU
2481#if 1
2482#define GEM_MAX_MTU ETH_DATA_LEN
2483#else
2484#define GEM_MAX_MTU 9000
2485#endif
2486
2487static int gem_change_mtu(struct net_device *dev, int new_mtu)
2488{
2489 struct gem *gp = netdev_priv(dev);
2490
2491 WRITE_ONCE(dev->mtu, new_mtu);
2492
2493 /* We'll just catch it later when the device is up'd or resumed */
2494 if (!netif_running(dev) || !netif_device_present(dev))
2495 return 0;
2496
2497 /* Better safe than sorry... */
2498 if (WARN_ON(!gp->cell_enabled))
2499 return 0;
2500
2501 gem_netif_stop(gp);
2502 gem_reinit_chip(gp);
2503 if (gp->lstate == link_up)
2504 gem_set_link_modes(gp);
2505 gem_netif_start(gp);
2506
2507 return 0;
2508}
2509
2510static void gem_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
2511{
2512 struct gem *gp = netdev_priv(dev);
2513
2514 strscpy(info->driver, DRV_NAME, sizeof(info->driver));
2515 strscpy(info->version, DRV_VERSION, sizeof(info->version));
2516 strscpy(info->bus_info, pci_name(gp->pdev), sizeof(info->bus_info));
2517}
2518
2519static int gem_get_link_ksettings(struct net_device *dev,
2520 struct ethtool_link_ksettings *cmd)
2521{
2522 struct gem *gp = netdev_priv(dev);
2523 u32 supported, advertising;
2524
2525 if (gp->phy_type == phy_mii_mdio0 ||
2526 gp->phy_type == phy_mii_mdio1) {
2527 if (gp->phy_mii.def)
2528 supported = gp->phy_mii.def->features;
2529 else
2530 supported = (SUPPORTED_10baseT_Half |
2531 SUPPORTED_10baseT_Full);
2532
2533 /* XXX hardcoded stuff for now */
2534 cmd->base.port = PORT_MII;
2535 cmd->base.phy_address = 0; /* XXX fixed PHYAD */
2536
2537 /* Return current PHY settings */
2538 cmd->base.autoneg = gp->want_autoneg;
2539 cmd->base.speed = gp->phy_mii.speed;
2540 cmd->base.duplex = gp->phy_mii.duplex;
2541 advertising = gp->phy_mii.advertising;
2542
2543 /* If we started with a forced mode, we don't have a default
2544 * advertise set, we need to return something sensible so
2545 * userland can re-enable autoneg properly.
2546 */
2547 if (advertising == 0)
2548 advertising = supported;
2549 } else { // XXX PCS ?
2550 supported =
2551 (SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full |
2552 SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full |
2553 SUPPORTED_Autoneg);
2554 advertising = supported;
2555 cmd->base.speed = 0;
2556 cmd->base.duplex = 0;
2557 cmd->base.port = 0;
2558 cmd->base.phy_address = 0;
2559 cmd->base.autoneg = 0;
2560
2561 /* serdes means usually a Fibre connector, with most fixed */
2562 if (gp->phy_type == phy_serdes) {
2563 cmd->base.port = PORT_FIBRE;
2564 supported = (SUPPORTED_1000baseT_Half |
2565 SUPPORTED_1000baseT_Full |
2566 SUPPORTED_FIBRE | SUPPORTED_Autoneg |
2567 SUPPORTED_Pause | SUPPORTED_Asym_Pause);
2568 advertising = supported;
2569 if (gp->lstate == link_up)
2570 cmd->base.speed = SPEED_1000;
2571 cmd->base.duplex = DUPLEX_FULL;
2572 cmd->base.autoneg = 1;
2573 }
2574 }
2575
2576 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.supported,
2577 supported);
2578 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.advertising,
2579 advertising);
2580
2581 return 0;
2582}
2583
2584static int gem_set_link_ksettings(struct net_device *dev,
2585 const struct ethtool_link_ksettings *cmd)
2586{
2587 struct gem *gp = netdev_priv(dev);
2588 u32 speed = cmd->base.speed;
2589 u32 advertising;
2590
2591 ethtool_convert_link_mode_to_legacy_u32(&advertising,
2592 cmd->link_modes.advertising);
2593
2594 /* Verify the settings we care about. */
2595 if (cmd->base.autoneg != AUTONEG_ENABLE &&
2596 cmd->base.autoneg != AUTONEG_DISABLE)
2597 return -EINVAL;
2598
2599 if (cmd->base.autoneg == AUTONEG_ENABLE &&
2600 advertising == 0)
2601 return -EINVAL;
2602
2603 if (cmd->base.autoneg == AUTONEG_DISABLE &&
2604 ((speed != SPEED_1000 &&
2605 speed != SPEED_100 &&
2606 speed != SPEED_10) ||
2607 (cmd->base.duplex != DUPLEX_HALF &&
2608 cmd->base.duplex != DUPLEX_FULL)))
2609 return -EINVAL;
2610
2611 /* Apply settings and restart link process. */
2612 if (netif_device_present(gp->dev)) {
2613 del_timer_sync(&gp->link_timer);
2614 gem_begin_auto_negotiation(gp, cmd);
2615 }
2616
2617 return 0;
2618}
2619
2620static int gem_nway_reset(struct net_device *dev)
2621{
2622 struct gem *gp = netdev_priv(dev);
2623
2624 if (!gp->want_autoneg)
2625 return -EINVAL;
2626
2627 /* Restart link process */
2628 if (netif_device_present(gp->dev)) {
2629 del_timer_sync(&gp->link_timer);
2630 gem_begin_auto_negotiation(gp, NULL);
2631 }
2632
2633 return 0;
2634}
2635
2636static u32 gem_get_msglevel(struct net_device *dev)
2637{
2638 struct gem *gp = netdev_priv(dev);
2639 return gp->msg_enable;
2640}
2641
2642static void gem_set_msglevel(struct net_device *dev, u32 value)
2643{
2644 struct gem *gp = netdev_priv(dev);
2645 gp->msg_enable = value;
2646}
2647
2648
2649/* Add more when I understand how to program the chip */
2650/* like WAKE_UCAST | WAKE_MCAST | WAKE_BCAST */
2651
2652#define WOL_SUPPORTED_MASK (WAKE_MAGIC)
2653
2654static void gem_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2655{
2656 struct gem *gp = netdev_priv(dev);
2657
2658 /* Add more when I understand how to program the chip */
2659 if (gp->has_wol) {
2660 wol->supported = WOL_SUPPORTED_MASK;
2661 wol->wolopts = gp->wake_on_lan;
2662 } else {
2663 wol->supported = 0;
2664 wol->wolopts = 0;
2665 }
2666}
2667
2668static int gem_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2669{
2670 struct gem *gp = netdev_priv(dev);
2671
2672 if (!gp->has_wol)
2673 return -EOPNOTSUPP;
2674 gp->wake_on_lan = wol->wolopts & WOL_SUPPORTED_MASK;
2675 return 0;
2676}
2677
2678static const struct ethtool_ops gem_ethtool_ops = {
2679 .get_drvinfo = gem_get_drvinfo,
2680 .get_link = ethtool_op_get_link,
2681 .nway_reset = gem_nway_reset,
2682 .get_msglevel = gem_get_msglevel,
2683 .set_msglevel = gem_set_msglevel,
2684 .get_wol = gem_get_wol,
2685 .set_wol = gem_set_wol,
2686 .get_link_ksettings = gem_get_link_ksettings,
2687 .set_link_ksettings = gem_set_link_ksettings,
2688};
2689
2690static int gem_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2691{
2692 struct gem *gp = netdev_priv(dev);
2693 struct mii_ioctl_data *data = if_mii(ifr);
2694 int rc = -EOPNOTSUPP;
2695
2696 /* For SIOCGMIIREG and SIOCSMIIREG the core checks for us that
2697 * netif_device_present() is true and holds rtnl_lock for us
2698 * so we have nothing to worry about
2699 */
2700
2701 switch (cmd) {
2702 case SIOCGMIIPHY: /* Get address of MII PHY in use. */
2703 data->phy_id = gp->mii_phy_addr;
2704 fallthrough;
2705
2706 case SIOCGMIIREG: /* Read MII PHY register. */
2707 data->val_out = __sungem_phy_read(gp, data->phy_id & 0x1f,
2708 data->reg_num & 0x1f);
2709 rc = 0;
2710 break;
2711
2712 case SIOCSMIIREG: /* Write MII PHY register. */
2713 __sungem_phy_write(gp, data->phy_id & 0x1f, data->reg_num & 0x1f,
2714 data->val_in);
2715 rc = 0;
2716 break;
2717 }
2718 return rc;
2719}
2720
2721#if (!defined(CONFIG_SPARC) && !defined(CONFIG_PPC_PMAC))
2722/* Fetch MAC address from vital product data of PCI ROM. */
2723static int find_eth_addr_in_vpd(void __iomem *rom_base, int len, unsigned char *dev_addr)
2724{
2725 int this_offset;
2726
2727 for (this_offset = 0x20; this_offset < len; this_offset++) {
2728 void __iomem *p = rom_base + this_offset;
2729 int i;
2730
2731 if (readb(p + 0) != 0x90 ||
2732 readb(p + 1) != 0x00 ||
2733 readb(p + 2) != 0x09 ||
2734 readb(p + 3) != 0x4e ||
2735 readb(p + 4) != 0x41 ||
2736 readb(p + 5) != 0x06)
2737 continue;
2738
2739 this_offset += 6;
2740 p += 6;
2741
2742 for (i = 0; i < 6; i++)
2743 dev_addr[i] = readb(p + i);
2744 return 1;
2745 }
2746 return 0;
2747}
2748
2749static void get_gem_mac_nonobp(struct pci_dev *pdev, unsigned char *dev_addr)
2750{
2751 size_t size;
2752 void __iomem *p = pci_map_rom(pdev, &size);
2753
2754 if (p) {
2755 int found;
2756
2757 found = readb(p) == 0x55 &&
2758 readb(p + 1) == 0xaa &&
2759 find_eth_addr_in_vpd(p, (64 * 1024), dev_addr);
2760 pci_unmap_rom(pdev, p);
2761 if (found)
2762 return;
2763 }
2764
2765 /* Sun MAC prefix then 3 random bytes. */
2766 dev_addr[0] = 0x08;
2767 dev_addr[1] = 0x00;
2768 dev_addr[2] = 0x20;
2769 get_random_bytes(dev_addr + 3, 3);
2770}
2771#endif /* not Sparc and not PPC */
2772
2773static int gem_get_device_address(struct gem *gp)
2774{
2775#if defined(CONFIG_SPARC) || defined(CONFIG_PPC_PMAC)
2776 struct net_device *dev = gp->dev;
2777 const unsigned char *addr;
2778
2779 addr = of_get_property(gp->of_node, "local-mac-address", NULL);
2780 if (addr == NULL) {
2781#ifdef CONFIG_SPARC
2782 addr = idprom->id_ethaddr;
2783#else
2784 printk("\n");
2785 pr_err("%s: can't get mac-address\n", dev->name);
2786 return -1;
2787#endif
2788 }
2789 eth_hw_addr_set(dev, addr);
2790#else
2791 u8 addr[ETH_ALEN];
2792
2793 get_gem_mac_nonobp(gp->pdev, addr);
2794 eth_hw_addr_set(gp->dev, addr);
2795#endif
2796 return 0;
2797}
2798
2799static void gem_remove_one(struct pci_dev *pdev)
2800{
2801 struct net_device *dev = pci_get_drvdata(pdev);
2802
2803 if (dev) {
2804 struct gem *gp = netdev_priv(dev);
2805
2806 unregister_netdev(dev);
2807
2808 /* Ensure reset task is truly gone */
2809 cancel_work_sync(&gp->reset_task);
2810
2811 /* Free resources */
2812 dma_free_coherent(&pdev->dev, sizeof(struct gem_init_block),
2813 gp->init_block, gp->gblock_dvma);
2814 iounmap(gp->regs);
2815 pci_release_regions(pdev);
2816 free_netdev(dev);
2817 }
2818}
2819
2820static const struct net_device_ops gem_netdev_ops = {
2821 .ndo_open = gem_open,
2822 .ndo_stop = gem_close,
2823 .ndo_start_xmit = gem_start_xmit,
2824 .ndo_get_stats = gem_get_stats,
2825 .ndo_set_rx_mode = gem_set_multicast,
2826 .ndo_eth_ioctl = gem_ioctl,
2827 .ndo_tx_timeout = gem_tx_timeout,
2828 .ndo_change_mtu = gem_change_mtu,
2829 .ndo_validate_addr = eth_validate_addr,
2830 .ndo_set_mac_address = gem_set_mac_address,
2831};
2832
2833static int gem_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
2834{
2835 unsigned long gemreg_base, gemreg_len;
2836 struct net_device *dev;
2837 struct gem *gp;
2838 int err, pci_using_dac;
2839
2840 printk_once(KERN_INFO "%s", version);
2841
2842 /* Apple gmac note: during probe, the chip is powered up by
2843 * the arch code to allow the code below to work (and to let
2844 * the chip be probed on the config space. It won't stay powered
2845 * up until the interface is brought up however, so we can't rely
2846 * on register configuration done at this point.
2847 */
2848 err = pci_enable_device(pdev);
2849 if (err) {
2850 pr_err("Cannot enable MMIO operation, aborting\n");
2851 return err;
2852 }
2853 pci_set_master(pdev);
2854
2855 /* Configure DMA attributes. */
2856
2857 /* All of the GEM documentation states that 64-bit DMA addressing
2858 * is fully supported and should work just fine. However the
2859 * front end for RIO based GEMs is different and only supports
2860 * 32-bit addressing.
2861 *
2862 * For now we assume the various PPC GEMs are 32-bit only as well.
2863 */
2864 if (pdev->vendor == PCI_VENDOR_ID_SUN &&
2865 pdev->device == PCI_DEVICE_ID_SUN_GEM &&
2866 !dma_set_mask(&pdev->dev, DMA_BIT_MASK(64))) {
2867 pci_using_dac = 1;
2868 } else {
2869 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
2870 if (err) {
2871 pr_err("No usable DMA configuration, aborting\n");
2872 goto err_disable_device;
2873 }
2874 pci_using_dac = 0;
2875 }
2876
2877 gemreg_base = pci_resource_start(pdev, 0);
2878 gemreg_len = pci_resource_len(pdev, 0);
2879
2880 if ((pci_resource_flags(pdev, 0) & IORESOURCE_IO) != 0) {
2881 pr_err("Cannot find proper PCI device base address, aborting\n");
2882 err = -ENODEV;
2883 goto err_disable_device;
2884 }
2885
2886 dev = alloc_etherdev(sizeof(*gp));
2887 if (!dev) {
2888 err = -ENOMEM;
2889 goto err_disable_device;
2890 }
2891 SET_NETDEV_DEV(dev, &pdev->dev);
2892
2893 gp = netdev_priv(dev);
2894
2895 err = pci_request_regions(pdev, DRV_NAME);
2896 if (err) {
2897 pr_err("Cannot obtain PCI resources, aborting\n");
2898 goto err_out_free_netdev;
2899 }
2900
2901 gp->pdev = pdev;
2902 gp->dev = dev;
2903
2904 gp->msg_enable = DEFAULT_MSG;
2905
2906 timer_setup(&gp->link_timer, gem_link_timer, 0);
2907
2908 INIT_WORK(&gp->reset_task, gem_reset_task);
2909
2910 gp->lstate = link_down;
2911 gp->timer_ticks = 0;
2912 netif_carrier_off(dev);
2913
2914 gp->regs = ioremap(gemreg_base, gemreg_len);
2915 if (!gp->regs) {
2916 pr_err("Cannot map device registers, aborting\n");
2917 err = -EIO;
2918 goto err_out_free_res;
2919 }
2920
2921 /* On Apple, we want a reference to the Open Firmware device-tree
2922 * node. We use it for clock control.
2923 */
2924#if defined(CONFIG_PPC_PMAC) || defined(CONFIG_SPARC)
2925 gp->of_node = pci_device_to_OF_node(pdev);
2926#endif
2927
2928 /* Only Apple version supports WOL afaik */
2929 if (pdev->vendor == PCI_VENDOR_ID_APPLE)
2930 gp->has_wol = 1;
2931
2932 /* Make sure cell is enabled */
2933 gem_get_cell(gp);
2934
2935 /* Make sure everything is stopped and in init state */
2936 gem_reset(gp);
2937
2938 /* Fill up the mii_phy structure (even if we won't use it) */
2939 gp->phy_mii.dev = dev;
2940 gp->phy_mii.mdio_read = _sungem_phy_read;
2941 gp->phy_mii.mdio_write = _sungem_phy_write;
2942#ifdef CONFIG_PPC_PMAC
2943 gp->phy_mii.platform_data = gp->of_node;
2944#endif
2945 /* By default, we start with autoneg */
2946 gp->want_autoneg = 1;
2947
2948 /* Check fifo sizes, PHY type, etc... */
2949 if (gem_check_invariants(gp)) {
2950 err = -ENODEV;
2951 goto err_out_iounmap;
2952 }
2953
2954 /* It is guaranteed that the returned buffer will be at least
2955 * PAGE_SIZE aligned.
2956 */
2957 gp->init_block = dma_alloc_coherent(&pdev->dev, sizeof(struct gem_init_block),
2958 &gp->gblock_dvma, GFP_KERNEL);
2959 if (!gp->init_block) {
2960 pr_err("Cannot allocate init block, aborting\n");
2961 err = -ENOMEM;
2962 goto err_out_iounmap;
2963 }
2964
2965 err = gem_get_device_address(gp);
2966 if (err)
2967 goto err_out_free_consistent;
2968
2969 dev->netdev_ops = &gem_netdev_ops;
2970 netif_napi_add(dev, &gp->napi, gem_poll);
2971 dev->ethtool_ops = &gem_ethtool_ops;
2972 dev->watchdog_timeo = 5 * HZ;
2973 dev->dma = 0;
2974
2975 /* Set that now, in case PM kicks in now */
2976 pci_set_drvdata(pdev, dev);
2977
2978 /* We can do scatter/gather and HW checksum */
2979 dev->hw_features = NETIF_F_SG | NETIF_F_HW_CSUM | NETIF_F_RXCSUM;
2980 dev->features = dev->hw_features;
2981 if (pci_using_dac)
2982 dev->features |= NETIF_F_HIGHDMA;
2983
2984 /* MTU range: 68 - 1500 (Jumbo mode is broken) */
2985 dev->min_mtu = GEM_MIN_MTU;
2986 dev->max_mtu = GEM_MAX_MTU;
2987
2988 /* Register with kernel */
2989 if (register_netdev(dev)) {
2990 pr_err("Cannot register net device, aborting\n");
2991 err = -ENOMEM;
2992 goto err_out_free_consistent;
2993 }
2994
2995 /* Undo the get_cell with appropriate locking (we could use
2996 * ndo_init/uninit but that would be even more clumsy imho)
2997 */
2998 rtnl_lock();
2999 gem_put_cell(gp);
3000 rtnl_unlock();
3001
3002 netdev_info(dev, "Sun GEM (PCI) 10/100/1000BaseT Ethernet %pM\n",
3003 dev->dev_addr);
3004 return 0;
3005
3006err_out_free_consistent:
3007 gem_remove_one(pdev);
3008err_out_iounmap:
3009 gem_put_cell(gp);
3010 iounmap(gp->regs);
3011
3012err_out_free_res:
3013 pci_release_regions(pdev);
3014
3015err_out_free_netdev:
3016 free_netdev(dev);
3017err_disable_device:
3018 pci_disable_device(pdev);
3019 return err;
3020
3021}
3022
3023static SIMPLE_DEV_PM_OPS(gem_pm_ops, gem_suspend, gem_resume);
3024
3025static struct pci_driver gem_driver = {
3026 .name = GEM_MODULE_NAME,
3027 .id_table = gem_pci_tbl,
3028 .probe = gem_init_one,
3029 .remove = gem_remove_one,
3030 .driver.pm = &gem_pm_ops,
3031};
3032
3033module_pci_driver(gem_driver);
1// SPDX-License-Identifier: GPL-2.0
2/* $Id: sungem.c,v 1.44.2.22 2002/03/13 01:18:12 davem Exp $
3 * sungem.c: Sun GEM ethernet driver.
4 *
5 * Copyright (C) 2000, 2001, 2002, 2003 David S. Miller (davem@redhat.com)
6 *
7 * Support for Apple GMAC and assorted PHYs, WOL, Power Management
8 * (C) 2001,2002,2003 Benjamin Herrenscmidt (benh@kernel.crashing.org)
9 * (C) 2004,2005 Benjamin Herrenscmidt, IBM Corp.
10 *
11 * NAPI and NETPOLL support
12 * (C) 2004 by Eric Lemoine (eric.lemoine@gmail.com)
13 *
14 */
15
16#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
17
18#include <linux/module.h>
19#include <linux/kernel.h>
20#include <linux/types.h>
21#include <linux/fcntl.h>
22#include <linux/interrupt.h>
23#include <linux/ioport.h>
24#include <linux/in.h>
25#include <linux/sched.h>
26#include <linux/string.h>
27#include <linux/delay.h>
28#include <linux/errno.h>
29#include <linux/pci.h>
30#include <linux/dma-mapping.h>
31#include <linux/netdevice.h>
32#include <linux/etherdevice.h>
33#include <linux/skbuff.h>
34#include <linux/mii.h>
35#include <linux/ethtool.h>
36#include <linux/crc32.h>
37#include <linux/random.h>
38#include <linux/workqueue.h>
39#include <linux/if_vlan.h>
40#include <linux/bitops.h>
41#include <linux/mm.h>
42#include <linux/gfp.h>
43
44#include <asm/io.h>
45#include <asm/byteorder.h>
46#include <linux/uaccess.h>
47#include <asm/irq.h>
48
49#ifdef CONFIG_SPARC
50#include <asm/idprom.h>
51#include <asm/prom.h>
52#endif
53
54#ifdef CONFIG_PPC_PMAC
55#include <asm/prom.h>
56#include <asm/machdep.h>
57#include <asm/pmac_feature.h>
58#endif
59
60#include <linux/sungem_phy.h>
61#include "sungem.h"
62
63/* Stripping FCS is causing problems, disabled for now */
64#undef STRIP_FCS
65
66#define DEFAULT_MSG (NETIF_MSG_DRV | \
67 NETIF_MSG_PROBE | \
68 NETIF_MSG_LINK)
69
70#define ADVERTISE_MASK (SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full | \
71 SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full | \
72 SUPPORTED_1000baseT_Half | SUPPORTED_1000baseT_Full | \
73 SUPPORTED_Pause | SUPPORTED_Autoneg)
74
75#define DRV_NAME "sungem"
76#define DRV_VERSION "1.0"
77#define DRV_AUTHOR "David S. Miller <davem@redhat.com>"
78
79static char version[] =
80 DRV_NAME ".c:v" DRV_VERSION " " DRV_AUTHOR "\n";
81
82MODULE_AUTHOR(DRV_AUTHOR);
83MODULE_DESCRIPTION("Sun GEM Gbit ethernet driver");
84MODULE_LICENSE("GPL");
85
86#define GEM_MODULE_NAME "gem"
87
88static const struct pci_device_id gem_pci_tbl[] = {
89 { PCI_VENDOR_ID_SUN, PCI_DEVICE_ID_SUN_GEM,
90 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
91
92 /* These models only differ from the original GEM in
93 * that their tx/rx fifos are of a different size and
94 * they only support 10/100 speeds. -DaveM
95 *
96 * Apple's GMAC does support gigabit on machines with
97 * the BCM54xx PHYs. -BenH
98 */
99 { PCI_VENDOR_ID_SUN, PCI_DEVICE_ID_SUN_RIO_GEM,
100 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
101 { PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_UNI_N_GMAC,
102 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
103 { PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_UNI_N_GMACP,
104 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
105 { PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_UNI_N_GMAC2,
106 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
107 { PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_K2_GMAC,
108 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
109 { PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_SH_SUNGEM,
110 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
111 { PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_IPID2_GMAC,
112 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
113 {0, }
114};
115
116MODULE_DEVICE_TABLE(pci, gem_pci_tbl);
117
118static u16 __sungem_phy_read(struct gem *gp, int phy_addr, int reg)
119{
120 u32 cmd;
121 int limit = 10000;
122
123 cmd = (1 << 30);
124 cmd |= (2 << 28);
125 cmd |= (phy_addr << 23) & MIF_FRAME_PHYAD;
126 cmd |= (reg << 18) & MIF_FRAME_REGAD;
127 cmd |= (MIF_FRAME_TAMSB);
128 writel(cmd, gp->regs + MIF_FRAME);
129
130 while (--limit) {
131 cmd = readl(gp->regs + MIF_FRAME);
132 if (cmd & MIF_FRAME_TALSB)
133 break;
134
135 udelay(10);
136 }
137
138 if (!limit)
139 cmd = 0xffff;
140
141 return cmd & MIF_FRAME_DATA;
142}
143
144static inline int _sungem_phy_read(struct net_device *dev, int mii_id, int reg)
145{
146 struct gem *gp = netdev_priv(dev);
147 return __sungem_phy_read(gp, mii_id, reg);
148}
149
150static inline u16 sungem_phy_read(struct gem *gp, int reg)
151{
152 return __sungem_phy_read(gp, gp->mii_phy_addr, reg);
153}
154
155static void __sungem_phy_write(struct gem *gp, int phy_addr, int reg, u16 val)
156{
157 u32 cmd;
158 int limit = 10000;
159
160 cmd = (1 << 30);
161 cmd |= (1 << 28);
162 cmd |= (phy_addr << 23) & MIF_FRAME_PHYAD;
163 cmd |= (reg << 18) & MIF_FRAME_REGAD;
164 cmd |= (MIF_FRAME_TAMSB);
165 cmd |= (val & MIF_FRAME_DATA);
166 writel(cmd, gp->regs + MIF_FRAME);
167
168 while (limit--) {
169 cmd = readl(gp->regs + MIF_FRAME);
170 if (cmd & MIF_FRAME_TALSB)
171 break;
172
173 udelay(10);
174 }
175}
176
177static inline void _sungem_phy_write(struct net_device *dev, int mii_id, int reg, int val)
178{
179 struct gem *gp = netdev_priv(dev);
180 __sungem_phy_write(gp, mii_id, reg, val & 0xffff);
181}
182
183static inline void sungem_phy_write(struct gem *gp, int reg, u16 val)
184{
185 __sungem_phy_write(gp, gp->mii_phy_addr, reg, val);
186}
187
188static inline void gem_enable_ints(struct gem *gp)
189{
190 /* Enable all interrupts but TXDONE */
191 writel(GREG_STAT_TXDONE, gp->regs + GREG_IMASK);
192}
193
194static inline void gem_disable_ints(struct gem *gp)
195{
196 /* Disable all interrupts, including TXDONE */
197 writel(GREG_STAT_NAPI | GREG_STAT_TXDONE, gp->regs + GREG_IMASK);
198 (void)readl(gp->regs + GREG_IMASK); /* write posting */
199}
200
201static void gem_get_cell(struct gem *gp)
202{
203 BUG_ON(gp->cell_enabled < 0);
204 gp->cell_enabled++;
205#ifdef CONFIG_PPC_PMAC
206 if (gp->cell_enabled == 1) {
207 mb();
208 pmac_call_feature(PMAC_FTR_GMAC_ENABLE, gp->of_node, 0, 1);
209 udelay(10);
210 }
211#endif /* CONFIG_PPC_PMAC */
212}
213
214/* Turn off the chip's clock */
215static void gem_put_cell(struct gem *gp)
216{
217 BUG_ON(gp->cell_enabled <= 0);
218 gp->cell_enabled--;
219#ifdef CONFIG_PPC_PMAC
220 if (gp->cell_enabled == 0) {
221 mb();
222 pmac_call_feature(PMAC_FTR_GMAC_ENABLE, gp->of_node, 0, 0);
223 udelay(10);
224 }
225#endif /* CONFIG_PPC_PMAC */
226}
227
228static inline void gem_netif_stop(struct gem *gp)
229{
230 netif_trans_update(gp->dev); /* prevent tx timeout */
231 napi_disable(&gp->napi);
232 netif_tx_disable(gp->dev);
233}
234
235static inline void gem_netif_start(struct gem *gp)
236{
237 /* NOTE: unconditional netif_wake_queue is only
238 * appropriate so long as all callers are assured to
239 * have free tx slots.
240 */
241 netif_wake_queue(gp->dev);
242 napi_enable(&gp->napi);
243}
244
245static void gem_schedule_reset(struct gem *gp)
246{
247 gp->reset_task_pending = 1;
248 schedule_work(&gp->reset_task);
249}
250
251static void gem_handle_mif_event(struct gem *gp, u32 reg_val, u32 changed_bits)
252{
253 if (netif_msg_intr(gp))
254 printk(KERN_DEBUG "%s: mif interrupt\n", gp->dev->name);
255}
256
257static int gem_pcs_interrupt(struct net_device *dev, struct gem *gp, u32 gem_status)
258{
259 u32 pcs_istat = readl(gp->regs + PCS_ISTAT);
260 u32 pcs_miistat;
261
262 if (netif_msg_intr(gp))
263 printk(KERN_DEBUG "%s: pcs interrupt, pcs_istat: 0x%x\n",
264 gp->dev->name, pcs_istat);
265
266 if (!(pcs_istat & PCS_ISTAT_LSC)) {
267 netdev_err(dev, "PCS irq but no link status change???\n");
268 return 0;
269 }
270
271 /* The link status bit latches on zero, so you must
272 * read it twice in such a case to see a transition
273 * to the link being up.
274 */
275 pcs_miistat = readl(gp->regs + PCS_MIISTAT);
276 if (!(pcs_miistat & PCS_MIISTAT_LS))
277 pcs_miistat |=
278 (readl(gp->regs + PCS_MIISTAT) &
279 PCS_MIISTAT_LS);
280
281 if (pcs_miistat & PCS_MIISTAT_ANC) {
282 /* The remote-fault indication is only valid
283 * when autoneg has completed.
284 */
285 if (pcs_miistat & PCS_MIISTAT_RF)
286 netdev_info(dev, "PCS AutoNEG complete, RemoteFault\n");
287 else
288 netdev_info(dev, "PCS AutoNEG complete\n");
289 }
290
291 if (pcs_miistat & PCS_MIISTAT_LS) {
292 netdev_info(dev, "PCS link is now up\n");
293 netif_carrier_on(gp->dev);
294 } else {
295 netdev_info(dev, "PCS link is now down\n");
296 netif_carrier_off(gp->dev);
297 /* If this happens and the link timer is not running,
298 * reset so we re-negotiate.
299 */
300 if (!timer_pending(&gp->link_timer))
301 return 1;
302 }
303
304 return 0;
305}
306
307static int gem_txmac_interrupt(struct net_device *dev, struct gem *gp, u32 gem_status)
308{
309 u32 txmac_stat = readl(gp->regs + MAC_TXSTAT);
310
311 if (netif_msg_intr(gp))
312 printk(KERN_DEBUG "%s: txmac interrupt, txmac_stat: 0x%x\n",
313 gp->dev->name, txmac_stat);
314
315 /* Defer timer expiration is quite normal,
316 * don't even log the event.
317 */
318 if ((txmac_stat & MAC_TXSTAT_DTE) &&
319 !(txmac_stat & ~MAC_TXSTAT_DTE))
320 return 0;
321
322 if (txmac_stat & MAC_TXSTAT_URUN) {
323 netdev_err(dev, "TX MAC xmit underrun\n");
324 dev->stats.tx_fifo_errors++;
325 }
326
327 if (txmac_stat & MAC_TXSTAT_MPE) {
328 netdev_err(dev, "TX MAC max packet size error\n");
329 dev->stats.tx_errors++;
330 }
331
332 /* The rest are all cases of one of the 16-bit TX
333 * counters expiring.
334 */
335 if (txmac_stat & MAC_TXSTAT_NCE)
336 dev->stats.collisions += 0x10000;
337
338 if (txmac_stat & MAC_TXSTAT_ECE) {
339 dev->stats.tx_aborted_errors += 0x10000;
340 dev->stats.collisions += 0x10000;
341 }
342
343 if (txmac_stat & MAC_TXSTAT_LCE) {
344 dev->stats.tx_aborted_errors += 0x10000;
345 dev->stats.collisions += 0x10000;
346 }
347
348 /* We do not keep track of MAC_TXSTAT_FCE and
349 * MAC_TXSTAT_PCE events.
350 */
351 return 0;
352}
353
354/* When we get a RX fifo overflow, the RX unit in GEM is probably hung
355 * so we do the following.
356 *
357 * If any part of the reset goes wrong, we return 1 and that causes the
358 * whole chip to be reset.
359 */
360static int gem_rxmac_reset(struct gem *gp)
361{
362 struct net_device *dev = gp->dev;
363 int limit, i;
364 u64 desc_dma;
365 u32 val;
366
367 /* First, reset & disable MAC RX. */
368 writel(MAC_RXRST_CMD, gp->regs + MAC_RXRST);
369 for (limit = 0; limit < 5000; limit++) {
370 if (!(readl(gp->regs + MAC_RXRST) & MAC_RXRST_CMD))
371 break;
372 udelay(10);
373 }
374 if (limit == 5000) {
375 netdev_err(dev, "RX MAC will not reset, resetting whole chip\n");
376 return 1;
377 }
378
379 writel(gp->mac_rx_cfg & ~MAC_RXCFG_ENAB,
380 gp->regs + MAC_RXCFG);
381 for (limit = 0; limit < 5000; limit++) {
382 if (!(readl(gp->regs + MAC_RXCFG) & MAC_RXCFG_ENAB))
383 break;
384 udelay(10);
385 }
386 if (limit == 5000) {
387 netdev_err(dev, "RX MAC will not disable, resetting whole chip\n");
388 return 1;
389 }
390
391 /* Second, disable RX DMA. */
392 writel(0, gp->regs + RXDMA_CFG);
393 for (limit = 0; limit < 5000; limit++) {
394 if (!(readl(gp->regs + RXDMA_CFG) & RXDMA_CFG_ENABLE))
395 break;
396 udelay(10);
397 }
398 if (limit == 5000) {
399 netdev_err(dev, "RX DMA will not disable, resetting whole chip\n");
400 return 1;
401 }
402
403 mdelay(5);
404
405 /* Execute RX reset command. */
406 writel(gp->swrst_base | GREG_SWRST_RXRST,
407 gp->regs + GREG_SWRST);
408 for (limit = 0; limit < 5000; limit++) {
409 if (!(readl(gp->regs + GREG_SWRST) & GREG_SWRST_RXRST))
410 break;
411 udelay(10);
412 }
413 if (limit == 5000) {
414 netdev_err(dev, "RX reset command will not execute, resetting whole chip\n");
415 return 1;
416 }
417
418 /* Refresh the RX ring. */
419 for (i = 0; i < RX_RING_SIZE; i++) {
420 struct gem_rxd *rxd = &gp->init_block->rxd[i];
421
422 if (gp->rx_skbs[i] == NULL) {
423 netdev_err(dev, "Parts of RX ring empty, resetting whole chip\n");
424 return 1;
425 }
426
427 rxd->status_word = cpu_to_le64(RXDCTRL_FRESH(gp));
428 }
429 gp->rx_new = gp->rx_old = 0;
430
431 /* Now we must reprogram the rest of RX unit. */
432 desc_dma = (u64) gp->gblock_dvma;
433 desc_dma += (INIT_BLOCK_TX_RING_SIZE * sizeof(struct gem_txd));
434 writel(desc_dma >> 32, gp->regs + RXDMA_DBHI);
435 writel(desc_dma & 0xffffffff, gp->regs + RXDMA_DBLOW);
436 writel(RX_RING_SIZE - 4, gp->regs + RXDMA_KICK);
437 val = (RXDMA_CFG_BASE | (RX_OFFSET << 10) |
438 ((14 / 2) << 13) | RXDMA_CFG_FTHRESH_128);
439 writel(val, gp->regs + RXDMA_CFG);
440 if (readl(gp->regs + GREG_BIFCFG) & GREG_BIFCFG_M66EN)
441 writel(((5 & RXDMA_BLANK_IPKTS) |
442 ((8 << 12) & RXDMA_BLANK_ITIME)),
443 gp->regs + RXDMA_BLANK);
444 else
445 writel(((5 & RXDMA_BLANK_IPKTS) |
446 ((4 << 12) & RXDMA_BLANK_ITIME)),
447 gp->regs + RXDMA_BLANK);
448 val = (((gp->rx_pause_off / 64) << 0) & RXDMA_PTHRESH_OFF);
449 val |= (((gp->rx_pause_on / 64) << 12) & RXDMA_PTHRESH_ON);
450 writel(val, gp->regs + RXDMA_PTHRESH);
451 val = readl(gp->regs + RXDMA_CFG);
452 writel(val | RXDMA_CFG_ENABLE, gp->regs + RXDMA_CFG);
453 writel(MAC_RXSTAT_RCV, gp->regs + MAC_RXMASK);
454 val = readl(gp->regs + MAC_RXCFG);
455 writel(val | MAC_RXCFG_ENAB, gp->regs + MAC_RXCFG);
456
457 return 0;
458}
459
460static int gem_rxmac_interrupt(struct net_device *dev, struct gem *gp, u32 gem_status)
461{
462 u32 rxmac_stat = readl(gp->regs + MAC_RXSTAT);
463 int ret = 0;
464
465 if (netif_msg_intr(gp))
466 printk(KERN_DEBUG "%s: rxmac interrupt, rxmac_stat: 0x%x\n",
467 gp->dev->name, rxmac_stat);
468
469 if (rxmac_stat & MAC_RXSTAT_OFLW) {
470 u32 smac = readl(gp->regs + MAC_SMACHINE);
471
472 netdev_err(dev, "RX MAC fifo overflow smac[%08x]\n", smac);
473 dev->stats.rx_over_errors++;
474 dev->stats.rx_fifo_errors++;
475
476 ret = gem_rxmac_reset(gp);
477 }
478
479 if (rxmac_stat & MAC_RXSTAT_ACE)
480 dev->stats.rx_frame_errors += 0x10000;
481
482 if (rxmac_stat & MAC_RXSTAT_CCE)
483 dev->stats.rx_crc_errors += 0x10000;
484
485 if (rxmac_stat & MAC_RXSTAT_LCE)
486 dev->stats.rx_length_errors += 0x10000;
487
488 /* We do not track MAC_RXSTAT_FCE and MAC_RXSTAT_VCE
489 * events.
490 */
491 return ret;
492}
493
494static int gem_mac_interrupt(struct net_device *dev, struct gem *gp, u32 gem_status)
495{
496 u32 mac_cstat = readl(gp->regs + MAC_CSTAT);
497
498 if (netif_msg_intr(gp))
499 printk(KERN_DEBUG "%s: mac interrupt, mac_cstat: 0x%x\n",
500 gp->dev->name, mac_cstat);
501
502 /* This interrupt is just for pause frame and pause
503 * tracking. It is useful for diagnostics and debug
504 * but probably by default we will mask these events.
505 */
506 if (mac_cstat & MAC_CSTAT_PS)
507 gp->pause_entered++;
508
509 if (mac_cstat & MAC_CSTAT_PRCV)
510 gp->pause_last_time_recvd = (mac_cstat >> 16);
511
512 return 0;
513}
514
515static int gem_mif_interrupt(struct net_device *dev, struct gem *gp, u32 gem_status)
516{
517 u32 mif_status = readl(gp->regs + MIF_STATUS);
518 u32 reg_val, changed_bits;
519
520 reg_val = (mif_status & MIF_STATUS_DATA) >> 16;
521 changed_bits = (mif_status & MIF_STATUS_STAT);
522
523 gem_handle_mif_event(gp, reg_val, changed_bits);
524
525 return 0;
526}
527
528static int gem_pci_interrupt(struct net_device *dev, struct gem *gp, u32 gem_status)
529{
530 u32 pci_estat = readl(gp->regs + GREG_PCIESTAT);
531
532 if (gp->pdev->vendor == PCI_VENDOR_ID_SUN &&
533 gp->pdev->device == PCI_DEVICE_ID_SUN_GEM) {
534 netdev_err(dev, "PCI error [%04x]", pci_estat);
535
536 if (pci_estat & GREG_PCIESTAT_BADACK)
537 pr_cont(" <No ACK64# during ABS64 cycle>");
538 if (pci_estat & GREG_PCIESTAT_DTRTO)
539 pr_cont(" <Delayed transaction timeout>");
540 if (pci_estat & GREG_PCIESTAT_OTHER)
541 pr_cont(" <other>");
542 pr_cont("\n");
543 } else {
544 pci_estat |= GREG_PCIESTAT_OTHER;
545 netdev_err(dev, "PCI error\n");
546 }
547
548 if (pci_estat & GREG_PCIESTAT_OTHER) {
549 u16 pci_cfg_stat;
550
551 /* Interrogate PCI config space for the
552 * true cause.
553 */
554 pci_read_config_word(gp->pdev, PCI_STATUS,
555 &pci_cfg_stat);
556 netdev_err(dev, "Read PCI cfg space status [%04x]\n",
557 pci_cfg_stat);
558 if (pci_cfg_stat & PCI_STATUS_PARITY)
559 netdev_err(dev, "PCI parity error detected\n");
560 if (pci_cfg_stat & PCI_STATUS_SIG_TARGET_ABORT)
561 netdev_err(dev, "PCI target abort\n");
562 if (pci_cfg_stat & PCI_STATUS_REC_TARGET_ABORT)
563 netdev_err(dev, "PCI master acks target abort\n");
564 if (pci_cfg_stat & PCI_STATUS_REC_MASTER_ABORT)
565 netdev_err(dev, "PCI master abort\n");
566 if (pci_cfg_stat & PCI_STATUS_SIG_SYSTEM_ERROR)
567 netdev_err(dev, "PCI system error SERR#\n");
568 if (pci_cfg_stat & PCI_STATUS_DETECTED_PARITY)
569 netdev_err(dev, "PCI parity error\n");
570
571 /* Write the error bits back to clear them. */
572 pci_cfg_stat &= (PCI_STATUS_PARITY |
573 PCI_STATUS_SIG_TARGET_ABORT |
574 PCI_STATUS_REC_TARGET_ABORT |
575 PCI_STATUS_REC_MASTER_ABORT |
576 PCI_STATUS_SIG_SYSTEM_ERROR |
577 PCI_STATUS_DETECTED_PARITY);
578 pci_write_config_word(gp->pdev,
579 PCI_STATUS, pci_cfg_stat);
580 }
581
582 /* For all PCI errors, we should reset the chip. */
583 return 1;
584}
585
586/* All non-normal interrupt conditions get serviced here.
587 * Returns non-zero if we should just exit the interrupt
588 * handler right now (ie. if we reset the card which invalidates
589 * all of the other original irq status bits).
590 */
591static int gem_abnormal_irq(struct net_device *dev, struct gem *gp, u32 gem_status)
592{
593 if (gem_status & GREG_STAT_RXNOBUF) {
594 /* Frame arrived, no free RX buffers available. */
595 if (netif_msg_rx_err(gp))
596 printk(KERN_DEBUG "%s: no buffer for rx frame\n",
597 gp->dev->name);
598 dev->stats.rx_dropped++;
599 }
600
601 if (gem_status & GREG_STAT_RXTAGERR) {
602 /* corrupt RX tag framing */
603 if (netif_msg_rx_err(gp))
604 printk(KERN_DEBUG "%s: corrupt rx tag framing\n",
605 gp->dev->name);
606 dev->stats.rx_errors++;
607
608 return 1;
609 }
610
611 if (gem_status & GREG_STAT_PCS) {
612 if (gem_pcs_interrupt(dev, gp, gem_status))
613 return 1;
614 }
615
616 if (gem_status & GREG_STAT_TXMAC) {
617 if (gem_txmac_interrupt(dev, gp, gem_status))
618 return 1;
619 }
620
621 if (gem_status & GREG_STAT_RXMAC) {
622 if (gem_rxmac_interrupt(dev, gp, gem_status))
623 return 1;
624 }
625
626 if (gem_status & GREG_STAT_MAC) {
627 if (gem_mac_interrupt(dev, gp, gem_status))
628 return 1;
629 }
630
631 if (gem_status & GREG_STAT_MIF) {
632 if (gem_mif_interrupt(dev, gp, gem_status))
633 return 1;
634 }
635
636 if (gem_status & GREG_STAT_PCIERR) {
637 if (gem_pci_interrupt(dev, gp, gem_status))
638 return 1;
639 }
640
641 return 0;
642}
643
644static __inline__ void gem_tx(struct net_device *dev, struct gem *gp, u32 gem_status)
645{
646 int entry, limit;
647
648 entry = gp->tx_old;
649 limit = ((gem_status & GREG_STAT_TXNR) >> GREG_STAT_TXNR_SHIFT);
650 while (entry != limit) {
651 struct sk_buff *skb;
652 struct gem_txd *txd;
653 dma_addr_t dma_addr;
654 u32 dma_len;
655 int frag;
656
657 if (netif_msg_tx_done(gp))
658 printk(KERN_DEBUG "%s: tx done, slot %d\n",
659 gp->dev->name, entry);
660 skb = gp->tx_skbs[entry];
661 if (skb_shinfo(skb)->nr_frags) {
662 int last = entry + skb_shinfo(skb)->nr_frags;
663 int walk = entry;
664 int incomplete = 0;
665
666 last &= (TX_RING_SIZE - 1);
667 for (;;) {
668 walk = NEXT_TX(walk);
669 if (walk == limit)
670 incomplete = 1;
671 if (walk == last)
672 break;
673 }
674 if (incomplete)
675 break;
676 }
677 gp->tx_skbs[entry] = NULL;
678 dev->stats.tx_bytes += skb->len;
679
680 for (frag = 0; frag <= skb_shinfo(skb)->nr_frags; frag++) {
681 txd = &gp->init_block->txd[entry];
682
683 dma_addr = le64_to_cpu(txd->buffer);
684 dma_len = le64_to_cpu(txd->control_word) & TXDCTRL_BUFSZ;
685
686 pci_unmap_page(gp->pdev, dma_addr, dma_len, PCI_DMA_TODEVICE);
687 entry = NEXT_TX(entry);
688 }
689
690 dev->stats.tx_packets++;
691 dev_consume_skb_any(skb);
692 }
693 gp->tx_old = entry;
694
695 /* Need to make the tx_old update visible to gem_start_xmit()
696 * before checking for netif_queue_stopped(). Without the
697 * memory barrier, there is a small possibility that gem_start_xmit()
698 * will miss it and cause the queue to be stopped forever.
699 */
700 smp_mb();
701
702 if (unlikely(netif_queue_stopped(dev) &&
703 TX_BUFFS_AVAIL(gp) > (MAX_SKB_FRAGS + 1))) {
704 struct netdev_queue *txq = netdev_get_tx_queue(dev, 0);
705
706 __netif_tx_lock(txq, smp_processor_id());
707 if (netif_queue_stopped(dev) &&
708 TX_BUFFS_AVAIL(gp) > (MAX_SKB_FRAGS + 1))
709 netif_wake_queue(dev);
710 __netif_tx_unlock(txq);
711 }
712}
713
714static __inline__ void gem_post_rxds(struct gem *gp, int limit)
715{
716 int cluster_start, curr, count, kick;
717
718 cluster_start = curr = (gp->rx_new & ~(4 - 1));
719 count = 0;
720 kick = -1;
721 dma_wmb();
722 while (curr != limit) {
723 curr = NEXT_RX(curr);
724 if (++count == 4) {
725 struct gem_rxd *rxd =
726 &gp->init_block->rxd[cluster_start];
727 for (;;) {
728 rxd->status_word = cpu_to_le64(RXDCTRL_FRESH(gp));
729 rxd++;
730 cluster_start = NEXT_RX(cluster_start);
731 if (cluster_start == curr)
732 break;
733 }
734 kick = curr;
735 count = 0;
736 }
737 }
738 if (kick >= 0) {
739 mb();
740 writel(kick, gp->regs + RXDMA_KICK);
741 }
742}
743
744#define ALIGNED_RX_SKB_ADDR(addr) \
745 ((((unsigned long)(addr) + (64UL - 1UL)) & ~(64UL - 1UL)) - (unsigned long)(addr))
746static __inline__ struct sk_buff *gem_alloc_skb(struct net_device *dev, int size,
747 gfp_t gfp_flags)
748{
749 struct sk_buff *skb = alloc_skb(size + 64, gfp_flags);
750
751 if (likely(skb)) {
752 unsigned long offset = ALIGNED_RX_SKB_ADDR(skb->data);
753 skb_reserve(skb, offset);
754 }
755 return skb;
756}
757
758static int gem_rx(struct gem *gp, int work_to_do)
759{
760 struct net_device *dev = gp->dev;
761 int entry, drops, work_done = 0;
762 u32 done;
763 __sum16 csum;
764
765 if (netif_msg_rx_status(gp))
766 printk(KERN_DEBUG "%s: rx interrupt, done: %d, rx_new: %d\n",
767 gp->dev->name, readl(gp->regs + RXDMA_DONE), gp->rx_new);
768
769 entry = gp->rx_new;
770 drops = 0;
771 done = readl(gp->regs + RXDMA_DONE);
772 for (;;) {
773 struct gem_rxd *rxd = &gp->init_block->rxd[entry];
774 struct sk_buff *skb;
775 u64 status = le64_to_cpu(rxd->status_word);
776 dma_addr_t dma_addr;
777 int len;
778
779 if ((status & RXDCTRL_OWN) != 0)
780 break;
781
782 if (work_done >= RX_RING_SIZE || work_done >= work_to_do)
783 break;
784
785 /* When writing back RX descriptor, GEM writes status
786 * then buffer address, possibly in separate transactions.
787 * If we don't wait for the chip to write both, we could
788 * post a new buffer to this descriptor then have GEM spam
789 * on the buffer address. We sync on the RX completion
790 * register to prevent this from happening.
791 */
792 if (entry == done) {
793 done = readl(gp->regs + RXDMA_DONE);
794 if (entry == done)
795 break;
796 }
797
798 /* We can now account for the work we're about to do */
799 work_done++;
800
801 skb = gp->rx_skbs[entry];
802
803 len = (status & RXDCTRL_BUFSZ) >> 16;
804 if ((len < ETH_ZLEN) || (status & RXDCTRL_BAD)) {
805 dev->stats.rx_errors++;
806 if (len < ETH_ZLEN)
807 dev->stats.rx_length_errors++;
808 if (len & RXDCTRL_BAD)
809 dev->stats.rx_crc_errors++;
810
811 /* We'll just return it to GEM. */
812 drop_it:
813 dev->stats.rx_dropped++;
814 goto next;
815 }
816
817 dma_addr = le64_to_cpu(rxd->buffer);
818 if (len > RX_COPY_THRESHOLD) {
819 struct sk_buff *new_skb;
820
821 new_skb = gem_alloc_skb(dev, RX_BUF_ALLOC_SIZE(gp), GFP_ATOMIC);
822 if (new_skb == NULL) {
823 drops++;
824 goto drop_it;
825 }
826 pci_unmap_page(gp->pdev, dma_addr,
827 RX_BUF_ALLOC_SIZE(gp),
828 PCI_DMA_FROMDEVICE);
829 gp->rx_skbs[entry] = new_skb;
830 skb_put(new_skb, (gp->rx_buf_sz + RX_OFFSET));
831 rxd->buffer = cpu_to_le64(pci_map_page(gp->pdev,
832 virt_to_page(new_skb->data),
833 offset_in_page(new_skb->data),
834 RX_BUF_ALLOC_SIZE(gp),
835 PCI_DMA_FROMDEVICE));
836 skb_reserve(new_skb, RX_OFFSET);
837
838 /* Trim the original skb for the netif. */
839 skb_trim(skb, len);
840 } else {
841 struct sk_buff *copy_skb = netdev_alloc_skb(dev, len + 2);
842
843 if (copy_skb == NULL) {
844 drops++;
845 goto drop_it;
846 }
847
848 skb_reserve(copy_skb, 2);
849 skb_put(copy_skb, len);
850 pci_dma_sync_single_for_cpu(gp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
851 skb_copy_from_linear_data(skb, copy_skb->data, len);
852 pci_dma_sync_single_for_device(gp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
853
854 /* We'll reuse the original ring buffer. */
855 skb = copy_skb;
856 }
857
858 csum = (__force __sum16)htons((status & RXDCTRL_TCPCSUM) ^ 0xffff);
859 skb->csum = csum_unfold(csum);
860 skb->ip_summed = CHECKSUM_COMPLETE;
861 skb->protocol = eth_type_trans(skb, gp->dev);
862
863 napi_gro_receive(&gp->napi, skb);
864
865 dev->stats.rx_packets++;
866 dev->stats.rx_bytes += len;
867
868 next:
869 entry = NEXT_RX(entry);
870 }
871
872 gem_post_rxds(gp, entry);
873
874 gp->rx_new = entry;
875
876 if (drops)
877 netdev_info(gp->dev, "Memory squeeze, deferring packet\n");
878
879 return work_done;
880}
881
882static int gem_poll(struct napi_struct *napi, int budget)
883{
884 struct gem *gp = container_of(napi, struct gem, napi);
885 struct net_device *dev = gp->dev;
886 int work_done;
887
888 work_done = 0;
889 do {
890 /* Handle anomalies */
891 if (unlikely(gp->status & GREG_STAT_ABNORMAL)) {
892 struct netdev_queue *txq = netdev_get_tx_queue(dev, 0);
893 int reset;
894
895 /* We run the abnormal interrupt handling code with
896 * the Tx lock. It only resets the Rx portion of the
897 * chip, but we need to guard it against DMA being
898 * restarted by the link poll timer
899 */
900 __netif_tx_lock(txq, smp_processor_id());
901 reset = gem_abnormal_irq(dev, gp, gp->status);
902 __netif_tx_unlock(txq);
903 if (reset) {
904 gem_schedule_reset(gp);
905 napi_complete(napi);
906 return work_done;
907 }
908 }
909
910 /* Run TX completion thread */
911 gem_tx(dev, gp, gp->status);
912
913 /* Run RX thread. We don't use any locking here,
914 * code willing to do bad things - like cleaning the
915 * rx ring - must call napi_disable(), which
916 * schedule_timeout()'s if polling is already disabled.
917 */
918 work_done += gem_rx(gp, budget - work_done);
919
920 if (work_done >= budget)
921 return work_done;
922
923 gp->status = readl(gp->regs + GREG_STAT);
924 } while (gp->status & GREG_STAT_NAPI);
925
926 napi_complete_done(napi, work_done);
927 gem_enable_ints(gp);
928
929 return work_done;
930}
931
932static irqreturn_t gem_interrupt(int irq, void *dev_id)
933{
934 struct net_device *dev = dev_id;
935 struct gem *gp = netdev_priv(dev);
936
937 if (napi_schedule_prep(&gp->napi)) {
938 u32 gem_status = readl(gp->regs + GREG_STAT);
939
940 if (unlikely(gem_status == 0)) {
941 napi_enable(&gp->napi);
942 return IRQ_NONE;
943 }
944 if (netif_msg_intr(gp))
945 printk(KERN_DEBUG "%s: gem_interrupt() gem_status: 0x%x\n",
946 gp->dev->name, gem_status);
947
948 gp->status = gem_status;
949 gem_disable_ints(gp);
950 __napi_schedule(&gp->napi);
951 }
952
953 /* If polling was disabled at the time we received that
954 * interrupt, we may return IRQ_HANDLED here while we
955 * should return IRQ_NONE. No big deal...
956 */
957 return IRQ_HANDLED;
958}
959
960#ifdef CONFIG_NET_POLL_CONTROLLER
961static void gem_poll_controller(struct net_device *dev)
962{
963 struct gem *gp = netdev_priv(dev);
964
965 disable_irq(gp->pdev->irq);
966 gem_interrupt(gp->pdev->irq, dev);
967 enable_irq(gp->pdev->irq);
968}
969#endif
970
971static void gem_tx_timeout(struct net_device *dev)
972{
973 struct gem *gp = netdev_priv(dev);
974
975 netdev_err(dev, "transmit timed out, resetting\n");
976
977 netdev_err(dev, "TX_STATE[%08x:%08x:%08x]\n",
978 readl(gp->regs + TXDMA_CFG),
979 readl(gp->regs + MAC_TXSTAT),
980 readl(gp->regs + MAC_TXCFG));
981 netdev_err(dev, "RX_STATE[%08x:%08x:%08x]\n",
982 readl(gp->regs + RXDMA_CFG),
983 readl(gp->regs + MAC_RXSTAT),
984 readl(gp->regs + MAC_RXCFG));
985
986 gem_schedule_reset(gp);
987}
988
989static __inline__ int gem_intme(int entry)
990{
991 /* Algorithm: IRQ every 1/2 of descriptors. */
992 if (!(entry & ((TX_RING_SIZE>>1)-1)))
993 return 1;
994
995 return 0;
996}
997
998static netdev_tx_t gem_start_xmit(struct sk_buff *skb,
999 struct net_device *dev)
1000{
1001 struct gem *gp = netdev_priv(dev);
1002 int entry;
1003 u64 ctrl;
1004
1005 ctrl = 0;
1006 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1007 const u64 csum_start_off = skb_checksum_start_offset(skb);
1008 const u64 csum_stuff_off = csum_start_off + skb->csum_offset;
1009
1010 ctrl = (TXDCTRL_CENAB |
1011 (csum_start_off << 15) |
1012 (csum_stuff_off << 21));
1013 }
1014
1015 if (unlikely(TX_BUFFS_AVAIL(gp) <= (skb_shinfo(skb)->nr_frags + 1))) {
1016 /* This is a hard error, log it. */
1017 if (!netif_queue_stopped(dev)) {
1018 netif_stop_queue(dev);
1019 netdev_err(dev, "BUG! Tx Ring full when queue awake!\n");
1020 }
1021 return NETDEV_TX_BUSY;
1022 }
1023
1024 entry = gp->tx_new;
1025 gp->tx_skbs[entry] = skb;
1026
1027 if (skb_shinfo(skb)->nr_frags == 0) {
1028 struct gem_txd *txd = &gp->init_block->txd[entry];
1029 dma_addr_t mapping;
1030 u32 len;
1031
1032 len = skb->len;
1033 mapping = pci_map_page(gp->pdev,
1034 virt_to_page(skb->data),
1035 offset_in_page(skb->data),
1036 len, PCI_DMA_TODEVICE);
1037 ctrl |= TXDCTRL_SOF | TXDCTRL_EOF | len;
1038 if (gem_intme(entry))
1039 ctrl |= TXDCTRL_INTME;
1040 txd->buffer = cpu_to_le64(mapping);
1041 dma_wmb();
1042 txd->control_word = cpu_to_le64(ctrl);
1043 entry = NEXT_TX(entry);
1044 } else {
1045 struct gem_txd *txd;
1046 u32 first_len;
1047 u64 intme;
1048 dma_addr_t first_mapping;
1049 int frag, first_entry = entry;
1050
1051 intme = 0;
1052 if (gem_intme(entry))
1053 intme |= TXDCTRL_INTME;
1054
1055 /* We must give this initial chunk to the device last.
1056 * Otherwise we could race with the device.
1057 */
1058 first_len = skb_headlen(skb);
1059 first_mapping = pci_map_page(gp->pdev, virt_to_page(skb->data),
1060 offset_in_page(skb->data),
1061 first_len, PCI_DMA_TODEVICE);
1062 entry = NEXT_TX(entry);
1063
1064 for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) {
1065 const skb_frag_t *this_frag = &skb_shinfo(skb)->frags[frag];
1066 u32 len;
1067 dma_addr_t mapping;
1068 u64 this_ctrl;
1069
1070 len = skb_frag_size(this_frag);
1071 mapping = skb_frag_dma_map(&gp->pdev->dev, this_frag,
1072 0, len, DMA_TO_DEVICE);
1073 this_ctrl = ctrl;
1074 if (frag == skb_shinfo(skb)->nr_frags - 1)
1075 this_ctrl |= TXDCTRL_EOF;
1076
1077 txd = &gp->init_block->txd[entry];
1078 txd->buffer = cpu_to_le64(mapping);
1079 dma_wmb();
1080 txd->control_word = cpu_to_le64(this_ctrl | len);
1081
1082 if (gem_intme(entry))
1083 intme |= TXDCTRL_INTME;
1084
1085 entry = NEXT_TX(entry);
1086 }
1087 txd = &gp->init_block->txd[first_entry];
1088 txd->buffer = cpu_to_le64(first_mapping);
1089 dma_wmb();
1090 txd->control_word =
1091 cpu_to_le64(ctrl | TXDCTRL_SOF | intme | first_len);
1092 }
1093
1094 gp->tx_new = entry;
1095 if (unlikely(TX_BUFFS_AVAIL(gp) <= (MAX_SKB_FRAGS + 1))) {
1096 netif_stop_queue(dev);
1097
1098 /* netif_stop_queue() must be done before checking
1099 * checking tx index in TX_BUFFS_AVAIL() below, because
1100 * in gem_tx(), we update tx_old before checking for
1101 * netif_queue_stopped().
1102 */
1103 smp_mb();
1104 if (TX_BUFFS_AVAIL(gp) > (MAX_SKB_FRAGS + 1))
1105 netif_wake_queue(dev);
1106 }
1107 if (netif_msg_tx_queued(gp))
1108 printk(KERN_DEBUG "%s: tx queued, slot %d, skblen %d\n",
1109 dev->name, entry, skb->len);
1110 mb();
1111 writel(gp->tx_new, gp->regs + TXDMA_KICK);
1112
1113 return NETDEV_TX_OK;
1114}
1115
1116static void gem_pcs_reset(struct gem *gp)
1117{
1118 int limit;
1119 u32 val;
1120
1121 /* Reset PCS unit. */
1122 val = readl(gp->regs + PCS_MIICTRL);
1123 val |= PCS_MIICTRL_RST;
1124 writel(val, gp->regs + PCS_MIICTRL);
1125
1126 limit = 32;
1127 while (readl(gp->regs + PCS_MIICTRL) & PCS_MIICTRL_RST) {
1128 udelay(100);
1129 if (limit-- <= 0)
1130 break;
1131 }
1132 if (limit < 0)
1133 netdev_warn(gp->dev, "PCS reset bit would not clear\n");
1134}
1135
1136static void gem_pcs_reinit_adv(struct gem *gp)
1137{
1138 u32 val;
1139
1140 /* Make sure PCS is disabled while changing advertisement
1141 * configuration.
1142 */
1143 val = readl(gp->regs + PCS_CFG);
1144 val &= ~(PCS_CFG_ENABLE | PCS_CFG_TO);
1145 writel(val, gp->regs + PCS_CFG);
1146
1147 /* Advertise all capabilities except asymmetric
1148 * pause.
1149 */
1150 val = readl(gp->regs + PCS_MIIADV);
1151 val |= (PCS_MIIADV_FD | PCS_MIIADV_HD |
1152 PCS_MIIADV_SP | PCS_MIIADV_AP);
1153 writel(val, gp->regs + PCS_MIIADV);
1154
1155 /* Enable and restart auto-negotiation, disable wrapback/loopback,
1156 * and re-enable PCS.
1157 */
1158 val = readl(gp->regs + PCS_MIICTRL);
1159 val |= (PCS_MIICTRL_RAN | PCS_MIICTRL_ANE);
1160 val &= ~PCS_MIICTRL_WB;
1161 writel(val, gp->regs + PCS_MIICTRL);
1162
1163 val = readl(gp->regs + PCS_CFG);
1164 val |= PCS_CFG_ENABLE;
1165 writel(val, gp->regs + PCS_CFG);
1166
1167 /* Make sure serialink loopback is off. The meaning
1168 * of this bit is logically inverted based upon whether
1169 * you are in Serialink or SERDES mode.
1170 */
1171 val = readl(gp->regs + PCS_SCTRL);
1172 if (gp->phy_type == phy_serialink)
1173 val &= ~PCS_SCTRL_LOOP;
1174 else
1175 val |= PCS_SCTRL_LOOP;
1176 writel(val, gp->regs + PCS_SCTRL);
1177}
1178
1179#define STOP_TRIES 32
1180
1181static void gem_reset(struct gem *gp)
1182{
1183 int limit;
1184 u32 val;
1185
1186 /* Make sure we won't get any more interrupts */
1187 writel(0xffffffff, gp->regs + GREG_IMASK);
1188
1189 /* Reset the chip */
1190 writel(gp->swrst_base | GREG_SWRST_TXRST | GREG_SWRST_RXRST,
1191 gp->regs + GREG_SWRST);
1192
1193 limit = STOP_TRIES;
1194
1195 do {
1196 udelay(20);
1197 val = readl(gp->regs + GREG_SWRST);
1198 if (limit-- <= 0)
1199 break;
1200 } while (val & (GREG_SWRST_TXRST | GREG_SWRST_RXRST));
1201
1202 if (limit < 0)
1203 netdev_err(gp->dev, "SW reset is ghetto\n");
1204
1205 if (gp->phy_type == phy_serialink || gp->phy_type == phy_serdes)
1206 gem_pcs_reinit_adv(gp);
1207}
1208
1209static void gem_start_dma(struct gem *gp)
1210{
1211 u32 val;
1212
1213 /* We are ready to rock, turn everything on. */
1214 val = readl(gp->regs + TXDMA_CFG);
1215 writel(val | TXDMA_CFG_ENABLE, gp->regs + TXDMA_CFG);
1216 val = readl(gp->regs + RXDMA_CFG);
1217 writel(val | RXDMA_CFG_ENABLE, gp->regs + RXDMA_CFG);
1218 val = readl(gp->regs + MAC_TXCFG);
1219 writel(val | MAC_TXCFG_ENAB, gp->regs + MAC_TXCFG);
1220 val = readl(gp->regs + MAC_RXCFG);
1221 writel(val | MAC_RXCFG_ENAB, gp->regs + MAC_RXCFG);
1222
1223 (void) readl(gp->regs + MAC_RXCFG);
1224 udelay(100);
1225
1226 gem_enable_ints(gp);
1227
1228 writel(RX_RING_SIZE - 4, gp->regs + RXDMA_KICK);
1229}
1230
1231/* DMA won't be actually stopped before about 4ms tho ...
1232 */
1233static void gem_stop_dma(struct gem *gp)
1234{
1235 u32 val;
1236
1237 /* We are done rocking, turn everything off. */
1238 val = readl(gp->regs + TXDMA_CFG);
1239 writel(val & ~TXDMA_CFG_ENABLE, gp->regs + TXDMA_CFG);
1240 val = readl(gp->regs + RXDMA_CFG);
1241 writel(val & ~RXDMA_CFG_ENABLE, gp->regs + RXDMA_CFG);
1242 val = readl(gp->regs + MAC_TXCFG);
1243 writel(val & ~MAC_TXCFG_ENAB, gp->regs + MAC_TXCFG);
1244 val = readl(gp->regs + MAC_RXCFG);
1245 writel(val & ~MAC_RXCFG_ENAB, gp->regs + MAC_RXCFG);
1246
1247 (void) readl(gp->regs + MAC_RXCFG);
1248
1249 /* Need to wait a bit ... done by the caller */
1250}
1251
1252
1253// XXX dbl check what that function should do when called on PCS PHY
1254static void gem_begin_auto_negotiation(struct gem *gp,
1255 const struct ethtool_link_ksettings *ep)
1256{
1257 u32 advertise, features;
1258 int autoneg;
1259 int speed;
1260 int duplex;
1261 u32 advertising;
1262
1263 if (ep)
1264 ethtool_convert_link_mode_to_legacy_u32(
1265 &advertising, ep->link_modes.advertising);
1266
1267 if (gp->phy_type != phy_mii_mdio0 &&
1268 gp->phy_type != phy_mii_mdio1)
1269 goto non_mii;
1270
1271 /* Setup advertise */
1272 if (found_mii_phy(gp))
1273 features = gp->phy_mii.def->features;
1274 else
1275 features = 0;
1276
1277 advertise = features & ADVERTISE_MASK;
1278 if (gp->phy_mii.advertising != 0)
1279 advertise &= gp->phy_mii.advertising;
1280
1281 autoneg = gp->want_autoneg;
1282 speed = gp->phy_mii.speed;
1283 duplex = gp->phy_mii.duplex;
1284
1285 /* Setup link parameters */
1286 if (!ep)
1287 goto start_aneg;
1288 if (ep->base.autoneg == AUTONEG_ENABLE) {
1289 advertise = advertising;
1290 autoneg = 1;
1291 } else {
1292 autoneg = 0;
1293 speed = ep->base.speed;
1294 duplex = ep->base.duplex;
1295 }
1296
1297start_aneg:
1298 /* Sanitize settings based on PHY capabilities */
1299 if ((features & SUPPORTED_Autoneg) == 0)
1300 autoneg = 0;
1301 if (speed == SPEED_1000 &&
1302 !(features & (SUPPORTED_1000baseT_Half | SUPPORTED_1000baseT_Full)))
1303 speed = SPEED_100;
1304 if (speed == SPEED_100 &&
1305 !(features & (SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full)))
1306 speed = SPEED_10;
1307 if (duplex == DUPLEX_FULL &&
1308 !(features & (SUPPORTED_1000baseT_Full |
1309 SUPPORTED_100baseT_Full |
1310 SUPPORTED_10baseT_Full)))
1311 duplex = DUPLEX_HALF;
1312 if (speed == 0)
1313 speed = SPEED_10;
1314
1315 /* If we are asleep, we don't try to actually setup the PHY, we
1316 * just store the settings
1317 */
1318 if (!netif_device_present(gp->dev)) {
1319 gp->phy_mii.autoneg = gp->want_autoneg = autoneg;
1320 gp->phy_mii.speed = speed;
1321 gp->phy_mii.duplex = duplex;
1322 return;
1323 }
1324
1325 /* Configure PHY & start aneg */
1326 gp->want_autoneg = autoneg;
1327 if (autoneg) {
1328 if (found_mii_phy(gp))
1329 gp->phy_mii.def->ops->setup_aneg(&gp->phy_mii, advertise);
1330 gp->lstate = link_aneg;
1331 } else {
1332 if (found_mii_phy(gp))
1333 gp->phy_mii.def->ops->setup_forced(&gp->phy_mii, speed, duplex);
1334 gp->lstate = link_force_ok;
1335 }
1336
1337non_mii:
1338 gp->timer_ticks = 0;
1339 mod_timer(&gp->link_timer, jiffies + ((12 * HZ) / 10));
1340}
1341
1342/* A link-up condition has occurred, initialize and enable the
1343 * rest of the chip.
1344 */
1345static int gem_set_link_modes(struct gem *gp)
1346{
1347 struct netdev_queue *txq = netdev_get_tx_queue(gp->dev, 0);
1348 int full_duplex, speed, pause;
1349 u32 val;
1350
1351 full_duplex = 0;
1352 speed = SPEED_10;
1353 pause = 0;
1354
1355 if (found_mii_phy(gp)) {
1356 if (gp->phy_mii.def->ops->read_link(&gp->phy_mii))
1357 return 1;
1358 full_duplex = (gp->phy_mii.duplex == DUPLEX_FULL);
1359 speed = gp->phy_mii.speed;
1360 pause = gp->phy_mii.pause;
1361 } else if (gp->phy_type == phy_serialink ||
1362 gp->phy_type == phy_serdes) {
1363 u32 pcs_lpa = readl(gp->regs + PCS_MIILP);
1364
1365 if ((pcs_lpa & PCS_MIIADV_FD) || gp->phy_type == phy_serdes)
1366 full_duplex = 1;
1367 speed = SPEED_1000;
1368 }
1369
1370 netif_info(gp, link, gp->dev, "Link is up at %d Mbps, %s-duplex\n",
1371 speed, (full_duplex ? "full" : "half"));
1372
1373
1374 /* We take the tx queue lock to avoid collisions between
1375 * this code, the tx path and the NAPI-driven error path
1376 */
1377 __netif_tx_lock(txq, smp_processor_id());
1378
1379 val = (MAC_TXCFG_EIPG0 | MAC_TXCFG_NGU);
1380 if (full_duplex) {
1381 val |= (MAC_TXCFG_ICS | MAC_TXCFG_ICOLL);
1382 } else {
1383 /* MAC_TXCFG_NBO must be zero. */
1384 }
1385 writel(val, gp->regs + MAC_TXCFG);
1386
1387 val = (MAC_XIFCFG_OE | MAC_XIFCFG_LLED);
1388 if (!full_duplex &&
1389 (gp->phy_type == phy_mii_mdio0 ||
1390 gp->phy_type == phy_mii_mdio1)) {
1391 val |= MAC_XIFCFG_DISE;
1392 } else if (full_duplex) {
1393 val |= MAC_XIFCFG_FLED;
1394 }
1395
1396 if (speed == SPEED_1000)
1397 val |= (MAC_XIFCFG_GMII);
1398
1399 writel(val, gp->regs + MAC_XIFCFG);
1400
1401 /* If gigabit and half-duplex, enable carrier extension
1402 * mode. Else, disable it.
1403 */
1404 if (speed == SPEED_1000 && !full_duplex) {
1405 val = readl(gp->regs + MAC_TXCFG);
1406 writel(val | MAC_TXCFG_TCE, gp->regs + MAC_TXCFG);
1407
1408 val = readl(gp->regs + MAC_RXCFG);
1409 writel(val | MAC_RXCFG_RCE, gp->regs + MAC_RXCFG);
1410 } else {
1411 val = readl(gp->regs + MAC_TXCFG);
1412 writel(val & ~MAC_TXCFG_TCE, gp->regs + MAC_TXCFG);
1413
1414 val = readl(gp->regs + MAC_RXCFG);
1415 writel(val & ~MAC_RXCFG_RCE, gp->regs + MAC_RXCFG);
1416 }
1417
1418 if (gp->phy_type == phy_serialink ||
1419 gp->phy_type == phy_serdes) {
1420 u32 pcs_lpa = readl(gp->regs + PCS_MIILP);
1421
1422 if (pcs_lpa & (PCS_MIIADV_SP | PCS_MIIADV_AP))
1423 pause = 1;
1424 }
1425
1426 if (!full_duplex)
1427 writel(512, gp->regs + MAC_STIME);
1428 else
1429 writel(64, gp->regs + MAC_STIME);
1430 val = readl(gp->regs + MAC_MCCFG);
1431 if (pause)
1432 val |= (MAC_MCCFG_SPE | MAC_MCCFG_RPE);
1433 else
1434 val &= ~(MAC_MCCFG_SPE | MAC_MCCFG_RPE);
1435 writel(val, gp->regs + MAC_MCCFG);
1436
1437 gem_start_dma(gp);
1438
1439 __netif_tx_unlock(txq);
1440
1441 if (netif_msg_link(gp)) {
1442 if (pause) {
1443 netdev_info(gp->dev,
1444 "Pause is enabled (rxfifo: %d off: %d on: %d)\n",
1445 gp->rx_fifo_sz,
1446 gp->rx_pause_off,
1447 gp->rx_pause_on);
1448 } else {
1449 netdev_info(gp->dev, "Pause is disabled\n");
1450 }
1451 }
1452
1453 return 0;
1454}
1455
1456static int gem_mdio_link_not_up(struct gem *gp)
1457{
1458 switch (gp->lstate) {
1459 case link_force_ret:
1460 netif_info(gp, link, gp->dev,
1461 "Autoneg failed again, keeping forced mode\n");
1462 gp->phy_mii.def->ops->setup_forced(&gp->phy_mii,
1463 gp->last_forced_speed, DUPLEX_HALF);
1464 gp->timer_ticks = 5;
1465 gp->lstate = link_force_ok;
1466 return 0;
1467 case link_aneg:
1468 /* We try forced modes after a failed aneg only on PHYs that don't
1469 * have "magic_aneg" bit set, which means they internally do the
1470 * while forced-mode thingy. On these, we just restart aneg
1471 */
1472 if (gp->phy_mii.def->magic_aneg)
1473 return 1;
1474 netif_info(gp, link, gp->dev, "switching to forced 100bt\n");
1475 /* Try forced modes. */
1476 gp->phy_mii.def->ops->setup_forced(&gp->phy_mii, SPEED_100,
1477 DUPLEX_HALF);
1478 gp->timer_ticks = 5;
1479 gp->lstate = link_force_try;
1480 return 0;
1481 case link_force_try:
1482 /* Downgrade from 100 to 10 Mbps if necessary.
1483 * If already at 10Mbps, warn user about the
1484 * situation every 10 ticks.
1485 */
1486 if (gp->phy_mii.speed == SPEED_100) {
1487 gp->phy_mii.def->ops->setup_forced(&gp->phy_mii, SPEED_10,
1488 DUPLEX_HALF);
1489 gp->timer_ticks = 5;
1490 netif_info(gp, link, gp->dev,
1491 "switching to forced 10bt\n");
1492 return 0;
1493 } else
1494 return 1;
1495 default:
1496 return 0;
1497 }
1498}
1499
1500static void gem_link_timer(struct timer_list *t)
1501{
1502 struct gem *gp = from_timer(gp, t, link_timer);
1503 struct net_device *dev = gp->dev;
1504 int restart_aneg = 0;
1505
1506 /* There's no point doing anything if we're going to be reset */
1507 if (gp->reset_task_pending)
1508 return;
1509
1510 if (gp->phy_type == phy_serialink ||
1511 gp->phy_type == phy_serdes) {
1512 u32 val = readl(gp->regs + PCS_MIISTAT);
1513
1514 if (!(val & PCS_MIISTAT_LS))
1515 val = readl(gp->regs + PCS_MIISTAT);
1516
1517 if ((val & PCS_MIISTAT_LS) != 0) {
1518 if (gp->lstate == link_up)
1519 goto restart;
1520
1521 gp->lstate = link_up;
1522 netif_carrier_on(dev);
1523 (void)gem_set_link_modes(gp);
1524 }
1525 goto restart;
1526 }
1527 if (found_mii_phy(gp) && gp->phy_mii.def->ops->poll_link(&gp->phy_mii)) {
1528 /* Ok, here we got a link. If we had it due to a forced
1529 * fallback, and we were configured for autoneg, we do
1530 * retry a short autoneg pass. If you know your hub is
1531 * broken, use ethtool ;)
1532 */
1533 if (gp->lstate == link_force_try && gp->want_autoneg) {
1534 gp->lstate = link_force_ret;
1535 gp->last_forced_speed = gp->phy_mii.speed;
1536 gp->timer_ticks = 5;
1537 if (netif_msg_link(gp))
1538 netdev_info(dev,
1539 "Got link after fallback, retrying autoneg once...\n");
1540 gp->phy_mii.def->ops->setup_aneg(&gp->phy_mii, gp->phy_mii.advertising);
1541 } else if (gp->lstate != link_up) {
1542 gp->lstate = link_up;
1543 netif_carrier_on(dev);
1544 if (gem_set_link_modes(gp))
1545 restart_aneg = 1;
1546 }
1547 } else {
1548 /* If the link was previously up, we restart the
1549 * whole process
1550 */
1551 if (gp->lstate == link_up) {
1552 gp->lstate = link_down;
1553 netif_info(gp, link, dev, "Link down\n");
1554 netif_carrier_off(dev);
1555 gem_schedule_reset(gp);
1556 /* The reset task will restart the timer */
1557 return;
1558 } else if (++gp->timer_ticks > 10) {
1559 if (found_mii_phy(gp))
1560 restart_aneg = gem_mdio_link_not_up(gp);
1561 else
1562 restart_aneg = 1;
1563 }
1564 }
1565 if (restart_aneg) {
1566 gem_begin_auto_negotiation(gp, NULL);
1567 return;
1568 }
1569restart:
1570 mod_timer(&gp->link_timer, jiffies + ((12 * HZ) / 10));
1571}
1572
1573static void gem_clean_rings(struct gem *gp)
1574{
1575 struct gem_init_block *gb = gp->init_block;
1576 struct sk_buff *skb;
1577 int i;
1578 dma_addr_t dma_addr;
1579
1580 for (i = 0; i < RX_RING_SIZE; i++) {
1581 struct gem_rxd *rxd;
1582
1583 rxd = &gb->rxd[i];
1584 if (gp->rx_skbs[i] != NULL) {
1585 skb = gp->rx_skbs[i];
1586 dma_addr = le64_to_cpu(rxd->buffer);
1587 pci_unmap_page(gp->pdev, dma_addr,
1588 RX_BUF_ALLOC_SIZE(gp),
1589 PCI_DMA_FROMDEVICE);
1590 dev_kfree_skb_any(skb);
1591 gp->rx_skbs[i] = NULL;
1592 }
1593 rxd->status_word = 0;
1594 dma_wmb();
1595 rxd->buffer = 0;
1596 }
1597
1598 for (i = 0; i < TX_RING_SIZE; i++) {
1599 if (gp->tx_skbs[i] != NULL) {
1600 struct gem_txd *txd;
1601 int frag;
1602
1603 skb = gp->tx_skbs[i];
1604 gp->tx_skbs[i] = NULL;
1605
1606 for (frag = 0; frag <= skb_shinfo(skb)->nr_frags; frag++) {
1607 int ent = i & (TX_RING_SIZE - 1);
1608
1609 txd = &gb->txd[ent];
1610 dma_addr = le64_to_cpu(txd->buffer);
1611 pci_unmap_page(gp->pdev, dma_addr,
1612 le64_to_cpu(txd->control_word) &
1613 TXDCTRL_BUFSZ, PCI_DMA_TODEVICE);
1614
1615 if (frag != skb_shinfo(skb)->nr_frags)
1616 i++;
1617 }
1618 dev_kfree_skb_any(skb);
1619 }
1620 }
1621}
1622
1623static void gem_init_rings(struct gem *gp)
1624{
1625 struct gem_init_block *gb = gp->init_block;
1626 struct net_device *dev = gp->dev;
1627 int i;
1628 dma_addr_t dma_addr;
1629
1630 gp->rx_new = gp->rx_old = gp->tx_new = gp->tx_old = 0;
1631
1632 gem_clean_rings(gp);
1633
1634 gp->rx_buf_sz = max(dev->mtu + ETH_HLEN + VLAN_HLEN,
1635 (unsigned)VLAN_ETH_FRAME_LEN);
1636
1637 for (i = 0; i < RX_RING_SIZE; i++) {
1638 struct sk_buff *skb;
1639 struct gem_rxd *rxd = &gb->rxd[i];
1640
1641 skb = gem_alloc_skb(dev, RX_BUF_ALLOC_SIZE(gp), GFP_KERNEL);
1642 if (!skb) {
1643 rxd->buffer = 0;
1644 rxd->status_word = 0;
1645 continue;
1646 }
1647
1648 gp->rx_skbs[i] = skb;
1649 skb_put(skb, (gp->rx_buf_sz + RX_OFFSET));
1650 dma_addr = pci_map_page(gp->pdev,
1651 virt_to_page(skb->data),
1652 offset_in_page(skb->data),
1653 RX_BUF_ALLOC_SIZE(gp),
1654 PCI_DMA_FROMDEVICE);
1655 rxd->buffer = cpu_to_le64(dma_addr);
1656 dma_wmb();
1657 rxd->status_word = cpu_to_le64(RXDCTRL_FRESH(gp));
1658 skb_reserve(skb, RX_OFFSET);
1659 }
1660
1661 for (i = 0; i < TX_RING_SIZE; i++) {
1662 struct gem_txd *txd = &gb->txd[i];
1663
1664 txd->control_word = 0;
1665 dma_wmb();
1666 txd->buffer = 0;
1667 }
1668 wmb();
1669}
1670
1671/* Init PHY interface and start link poll state machine */
1672static void gem_init_phy(struct gem *gp)
1673{
1674 u32 mifcfg;
1675
1676 /* Revert MIF CFG setting done on stop_phy */
1677 mifcfg = readl(gp->regs + MIF_CFG);
1678 mifcfg &= ~MIF_CFG_BBMODE;
1679 writel(mifcfg, gp->regs + MIF_CFG);
1680
1681 if (gp->pdev->vendor == PCI_VENDOR_ID_APPLE) {
1682 int i;
1683
1684 /* Those delay sucks, the HW seem to love them though, I'll
1685 * serisouly consider breaking some locks here to be able
1686 * to schedule instead
1687 */
1688 for (i = 0; i < 3; i++) {
1689#ifdef CONFIG_PPC_PMAC
1690 pmac_call_feature(PMAC_FTR_GMAC_PHY_RESET, gp->of_node, 0, 0);
1691 msleep(20);
1692#endif
1693 /* Some PHYs used by apple have problem getting back to us,
1694 * we do an additional reset here
1695 */
1696 sungem_phy_write(gp, MII_BMCR, BMCR_RESET);
1697 msleep(20);
1698 if (sungem_phy_read(gp, MII_BMCR) != 0xffff)
1699 break;
1700 if (i == 2)
1701 netdev_warn(gp->dev, "GMAC PHY not responding !\n");
1702 }
1703 }
1704
1705 if (gp->pdev->vendor == PCI_VENDOR_ID_SUN &&
1706 gp->pdev->device == PCI_DEVICE_ID_SUN_GEM) {
1707 u32 val;
1708
1709 /* Init datapath mode register. */
1710 if (gp->phy_type == phy_mii_mdio0 ||
1711 gp->phy_type == phy_mii_mdio1) {
1712 val = PCS_DMODE_MGM;
1713 } else if (gp->phy_type == phy_serialink) {
1714 val = PCS_DMODE_SM | PCS_DMODE_GMOE;
1715 } else {
1716 val = PCS_DMODE_ESM;
1717 }
1718
1719 writel(val, gp->regs + PCS_DMODE);
1720 }
1721
1722 if (gp->phy_type == phy_mii_mdio0 ||
1723 gp->phy_type == phy_mii_mdio1) {
1724 /* Reset and detect MII PHY */
1725 sungem_phy_probe(&gp->phy_mii, gp->mii_phy_addr);
1726
1727 /* Init PHY */
1728 if (gp->phy_mii.def && gp->phy_mii.def->ops->init)
1729 gp->phy_mii.def->ops->init(&gp->phy_mii);
1730 } else {
1731 gem_pcs_reset(gp);
1732 gem_pcs_reinit_adv(gp);
1733 }
1734
1735 /* Default aneg parameters */
1736 gp->timer_ticks = 0;
1737 gp->lstate = link_down;
1738 netif_carrier_off(gp->dev);
1739
1740 /* Print things out */
1741 if (gp->phy_type == phy_mii_mdio0 ||
1742 gp->phy_type == phy_mii_mdio1)
1743 netdev_info(gp->dev, "Found %s PHY\n",
1744 gp->phy_mii.def ? gp->phy_mii.def->name : "no");
1745
1746 gem_begin_auto_negotiation(gp, NULL);
1747}
1748
1749static void gem_init_dma(struct gem *gp)
1750{
1751 u64 desc_dma = (u64) gp->gblock_dvma;
1752 u32 val;
1753
1754 val = (TXDMA_CFG_BASE | (0x7ff << 10) | TXDMA_CFG_PMODE);
1755 writel(val, gp->regs + TXDMA_CFG);
1756
1757 writel(desc_dma >> 32, gp->regs + TXDMA_DBHI);
1758 writel(desc_dma & 0xffffffff, gp->regs + TXDMA_DBLOW);
1759 desc_dma += (INIT_BLOCK_TX_RING_SIZE * sizeof(struct gem_txd));
1760
1761 writel(0, gp->regs + TXDMA_KICK);
1762
1763 val = (RXDMA_CFG_BASE | (RX_OFFSET << 10) |
1764 ((14 / 2) << 13) | RXDMA_CFG_FTHRESH_128);
1765 writel(val, gp->regs + RXDMA_CFG);
1766
1767 writel(desc_dma >> 32, gp->regs + RXDMA_DBHI);
1768 writel(desc_dma & 0xffffffff, gp->regs + RXDMA_DBLOW);
1769
1770 writel(RX_RING_SIZE - 4, gp->regs + RXDMA_KICK);
1771
1772 val = (((gp->rx_pause_off / 64) << 0) & RXDMA_PTHRESH_OFF);
1773 val |= (((gp->rx_pause_on / 64) << 12) & RXDMA_PTHRESH_ON);
1774 writel(val, gp->regs + RXDMA_PTHRESH);
1775
1776 if (readl(gp->regs + GREG_BIFCFG) & GREG_BIFCFG_M66EN)
1777 writel(((5 & RXDMA_BLANK_IPKTS) |
1778 ((8 << 12) & RXDMA_BLANK_ITIME)),
1779 gp->regs + RXDMA_BLANK);
1780 else
1781 writel(((5 & RXDMA_BLANK_IPKTS) |
1782 ((4 << 12) & RXDMA_BLANK_ITIME)),
1783 gp->regs + RXDMA_BLANK);
1784}
1785
1786static u32 gem_setup_multicast(struct gem *gp)
1787{
1788 u32 rxcfg = 0;
1789 int i;
1790
1791 if ((gp->dev->flags & IFF_ALLMULTI) ||
1792 (netdev_mc_count(gp->dev) > 256)) {
1793 for (i=0; i<16; i++)
1794 writel(0xffff, gp->regs + MAC_HASH0 + (i << 2));
1795 rxcfg |= MAC_RXCFG_HFE;
1796 } else if (gp->dev->flags & IFF_PROMISC) {
1797 rxcfg |= MAC_RXCFG_PROM;
1798 } else {
1799 u16 hash_table[16];
1800 u32 crc;
1801 struct netdev_hw_addr *ha;
1802 int i;
1803
1804 memset(hash_table, 0, sizeof(hash_table));
1805 netdev_for_each_mc_addr(ha, gp->dev) {
1806 crc = ether_crc_le(6, ha->addr);
1807 crc >>= 24;
1808 hash_table[crc >> 4] |= 1 << (15 - (crc & 0xf));
1809 }
1810 for (i=0; i<16; i++)
1811 writel(hash_table[i], gp->regs + MAC_HASH0 + (i << 2));
1812 rxcfg |= MAC_RXCFG_HFE;
1813 }
1814
1815 return rxcfg;
1816}
1817
1818static void gem_init_mac(struct gem *gp)
1819{
1820 unsigned char *e = &gp->dev->dev_addr[0];
1821
1822 writel(0x1bf0, gp->regs + MAC_SNDPAUSE);
1823
1824 writel(0x00, gp->regs + MAC_IPG0);
1825 writel(0x08, gp->regs + MAC_IPG1);
1826 writel(0x04, gp->regs + MAC_IPG2);
1827 writel(0x40, gp->regs + MAC_STIME);
1828 writel(0x40, gp->regs + MAC_MINFSZ);
1829
1830 /* Ethernet payload + header + FCS + optional VLAN tag. */
1831 writel(0x20000000 | (gp->rx_buf_sz + 4), gp->regs + MAC_MAXFSZ);
1832
1833 writel(0x07, gp->regs + MAC_PASIZE);
1834 writel(0x04, gp->regs + MAC_JAMSIZE);
1835 writel(0x10, gp->regs + MAC_ATTLIM);
1836 writel(0x8808, gp->regs + MAC_MCTYPE);
1837
1838 writel((e[5] | (e[4] << 8)) & 0x3ff, gp->regs + MAC_RANDSEED);
1839
1840 writel((e[4] << 8) | e[5], gp->regs + MAC_ADDR0);
1841 writel((e[2] << 8) | e[3], gp->regs + MAC_ADDR1);
1842 writel((e[0] << 8) | e[1], gp->regs + MAC_ADDR2);
1843
1844 writel(0, gp->regs + MAC_ADDR3);
1845 writel(0, gp->regs + MAC_ADDR4);
1846 writel(0, gp->regs + MAC_ADDR5);
1847
1848 writel(0x0001, gp->regs + MAC_ADDR6);
1849 writel(0xc200, gp->regs + MAC_ADDR7);
1850 writel(0x0180, gp->regs + MAC_ADDR8);
1851
1852 writel(0, gp->regs + MAC_AFILT0);
1853 writel(0, gp->regs + MAC_AFILT1);
1854 writel(0, gp->regs + MAC_AFILT2);
1855 writel(0, gp->regs + MAC_AF21MSK);
1856 writel(0, gp->regs + MAC_AF0MSK);
1857
1858 gp->mac_rx_cfg = gem_setup_multicast(gp);
1859#ifdef STRIP_FCS
1860 gp->mac_rx_cfg |= MAC_RXCFG_SFCS;
1861#endif
1862 writel(0, gp->regs + MAC_NCOLL);
1863 writel(0, gp->regs + MAC_FASUCC);
1864 writel(0, gp->regs + MAC_ECOLL);
1865 writel(0, gp->regs + MAC_LCOLL);
1866 writel(0, gp->regs + MAC_DTIMER);
1867 writel(0, gp->regs + MAC_PATMPS);
1868 writel(0, gp->regs + MAC_RFCTR);
1869 writel(0, gp->regs + MAC_LERR);
1870 writel(0, gp->regs + MAC_AERR);
1871 writel(0, gp->regs + MAC_FCSERR);
1872 writel(0, gp->regs + MAC_RXCVERR);
1873
1874 /* Clear RX/TX/MAC/XIF config, we will set these up and enable
1875 * them once a link is established.
1876 */
1877 writel(0, gp->regs + MAC_TXCFG);
1878 writel(gp->mac_rx_cfg, gp->regs + MAC_RXCFG);
1879 writel(0, gp->regs + MAC_MCCFG);
1880 writel(0, gp->regs + MAC_XIFCFG);
1881
1882 /* Setup MAC interrupts. We want to get all of the interesting
1883 * counter expiration events, but we do not want to hear about
1884 * normal rx/tx as the DMA engine tells us that.
1885 */
1886 writel(MAC_TXSTAT_XMIT, gp->regs + MAC_TXMASK);
1887 writel(MAC_RXSTAT_RCV, gp->regs + MAC_RXMASK);
1888
1889 /* Don't enable even the PAUSE interrupts for now, we
1890 * make no use of those events other than to record them.
1891 */
1892 writel(0xffffffff, gp->regs + MAC_MCMASK);
1893
1894 /* Don't enable GEM's WOL in normal operations
1895 */
1896 if (gp->has_wol)
1897 writel(0, gp->regs + WOL_WAKECSR);
1898}
1899
1900static void gem_init_pause_thresholds(struct gem *gp)
1901{
1902 u32 cfg;
1903
1904 /* Calculate pause thresholds. Setting the OFF threshold to the
1905 * full RX fifo size effectively disables PAUSE generation which
1906 * is what we do for 10/100 only GEMs which have FIFOs too small
1907 * to make real gains from PAUSE.
1908 */
1909 if (gp->rx_fifo_sz <= (2 * 1024)) {
1910 gp->rx_pause_off = gp->rx_pause_on = gp->rx_fifo_sz;
1911 } else {
1912 int max_frame = (gp->rx_buf_sz + 4 + 64) & ~63;
1913 int off = (gp->rx_fifo_sz - (max_frame * 2));
1914 int on = off - max_frame;
1915
1916 gp->rx_pause_off = off;
1917 gp->rx_pause_on = on;
1918 }
1919
1920
1921 /* Configure the chip "burst" DMA mode & enable some
1922 * HW bug fixes on Apple version
1923 */
1924 cfg = 0;
1925 if (gp->pdev->vendor == PCI_VENDOR_ID_APPLE)
1926 cfg |= GREG_CFG_RONPAULBIT | GREG_CFG_ENBUG2FIX;
1927#if !defined(CONFIG_SPARC64) && !defined(CONFIG_ALPHA)
1928 cfg |= GREG_CFG_IBURST;
1929#endif
1930 cfg |= ((31 << 1) & GREG_CFG_TXDMALIM);
1931 cfg |= ((31 << 6) & GREG_CFG_RXDMALIM);
1932 writel(cfg, gp->regs + GREG_CFG);
1933
1934 /* If Infinite Burst didn't stick, then use different
1935 * thresholds (and Apple bug fixes don't exist)
1936 */
1937 if (!(readl(gp->regs + GREG_CFG) & GREG_CFG_IBURST)) {
1938 cfg = ((2 << 1) & GREG_CFG_TXDMALIM);
1939 cfg |= ((8 << 6) & GREG_CFG_RXDMALIM);
1940 writel(cfg, gp->regs + GREG_CFG);
1941 }
1942}
1943
1944static int gem_check_invariants(struct gem *gp)
1945{
1946 struct pci_dev *pdev = gp->pdev;
1947 u32 mif_cfg;
1948
1949 /* On Apple's sungem, we can't rely on registers as the chip
1950 * was been powered down by the firmware. The PHY is looked
1951 * up later on.
1952 */
1953 if (pdev->vendor == PCI_VENDOR_ID_APPLE) {
1954 gp->phy_type = phy_mii_mdio0;
1955 gp->tx_fifo_sz = readl(gp->regs + TXDMA_FSZ) * 64;
1956 gp->rx_fifo_sz = readl(gp->regs + RXDMA_FSZ) * 64;
1957 gp->swrst_base = 0;
1958
1959 mif_cfg = readl(gp->regs + MIF_CFG);
1960 mif_cfg &= ~(MIF_CFG_PSELECT|MIF_CFG_POLL|MIF_CFG_BBMODE|MIF_CFG_MDI1);
1961 mif_cfg |= MIF_CFG_MDI0;
1962 writel(mif_cfg, gp->regs + MIF_CFG);
1963 writel(PCS_DMODE_MGM, gp->regs + PCS_DMODE);
1964 writel(MAC_XIFCFG_OE, gp->regs + MAC_XIFCFG);
1965
1966 /* We hard-code the PHY address so we can properly bring it out of
1967 * reset later on, we can't really probe it at this point, though
1968 * that isn't an issue.
1969 */
1970 if (gp->pdev->device == PCI_DEVICE_ID_APPLE_K2_GMAC)
1971 gp->mii_phy_addr = 1;
1972 else
1973 gp->mii_phy_addr = 0;
1974
1975 return 0;
1976 }
1977
1978 mif_cfg = readl(gp->regs + MIF_CFG);
1979
1980 if (pdev->vendor == PCI_VENDOR_ID_SUN &&
1981 pdev->device == PCI_DEVICE_ID_SUN_RIO_GEM) {
1982 /* One of the MII PHYs _must_ be present
1983 * as this chip has no gigabit PHY.
1984 */
1985 if ((mif_cfg & (MIF_CFG_MDI0 | MIF_CFG_MDI1)) == 0) {
1986 pr_err("RIO GEM lacks MII phy, mif_cfg[%08x]\n",
1987 mif_cfg);
1988 return -1;
1989 }
1990 }
1991
1992 /* Determine initial PHY interface type guess. MDIO1 is the
1993 * external PHY and thus takes precedence over MDIO0.
1994 */
1995
1996 if (mif_cfg & MIF_CFG_MDI1) {
1997 gp->phy_type = phy_mii_mdio1;
1998 mif_cfg |= MIF_CFG_PSELECT;
1999 writel(mif_cfg, gp->regs + MIF_CFG);
2000 } else if (mif_cfg & MIF_CFG_MDI0) {
2001 gp->phy_type = phy_mii_mdio0;
2002 mif_cfg &= ~MIF_CFG_PSELECT;
2003 writel(mif_cfg, gp->regs + MIF_CFG);
2004 } else {
2005#ifdef CONFIG_SPARC
2006 const char *p;
2007
2008 p = of_get_property(gp->of_node, "shared-pins", NULL);
2009 if (p && !strcmp(p, "serdes"))
2010 gp->phy_type = phy_serdes;
2011 else
2012#endif
2013 gp->phy_type = phy_serialink;
2014 }
2015 if (gp->phy_type == phy_mii_mdio1 ||
2016 gp->phy_type == phy_mii_mdio0) {
2017 int i;
2018
2019 for (i = 0; i < 32; i++) {
2020 gp->mii_phy_addr = i;
2021 if (sungem_phy_read(gp, MII_BMCR) != 0xffff)
2022 break;
2023 }
2024 if (i == 32) {
2025 if (pdev->device != PCI_DEVICE_ID_SUN_GEM) {
2026 pr_err("RIO MII phy will not respond\n");
2027 return -1;
2028 }
2029 gp->phy_type = phy_serdes;
2030 }
2031 }
2032
2033 /* Fetch the FIFO configurations now too. */
2034 gp->tx_fifo_sz = readl(gp->regs + TXDMA_FSZ) * 64;
2035 gp->rx_fifo_sz = readl(gp->regs + RXDMA_FSZ) * 64;
2036
2037 if (pdev->vendor == PCI_VENDOR_ID_SUN) {
2038 if (pdev->device == PCI_DEVICE_ID_SUN_GEM) {
2039 if (gp->tx_fifo_sz != (9 * 1024) ||
2040 gp->rx_fifo_sz != (20 * 1024)) {
2041 pr_err("GEM has bogus fifo sizes tx(%d) rx(%d)\n",
2042 gp->tx_fifo_sz, gp->rx_fifo_sz);
2043 return -1;
2044 }
2045 gp->swrst_base = 0;
2046 } else {
2047 if (gp->tx_fifo_sz != (2 * 1024) ||
2048 gp->rx_fifo_sz != (2 * 1024)) {
2049 pr_err("RIO GEM has bogus fifo sizes tx(%d) rx(%d)\n",
2050 gp->tx_fifo_sz, gp->rx_fifo_sz);
2051 return -1;
2052 }
2053 gp->swrst_base = (64 / 4) << GREG_SWRST_CACHE_SHIFT;
2054 }
2055 }
2056
2057 return 0;
2058}
2059
2060static void gem_reinit_chip(struct gem *gp)
2061{
2062 /* Reset the chip */
2063 gem_reset(gp);
2064
2065 /* Make sure ints are disabled */
2066 gem_disable_ints(gp);
2067
2068 /* Allocate & setup ring buffers */
2069 gem_init_rings(gp);
2070
2071 /* Configure pause thresholds */
2072 gem_init_pause_thresholds(gp);
2073
2074 /* Init DMA & MAC engines */
2075 gem_init_dma(gp);
2076 gem_init_mac(gp);
2077}
2078
2079
2080static void gem_stop_phy(struct gem *gp, int wol)
2081{
2082 u32 mifcfg;
2083
2084 /* Let the chip settle down a bit, it seems that helps
2085 * for sleep mode on some models
2086 */
2087 msleep(10);
2088
2089 /* Make sure we aren't polling PHY status change. We
2090 * don't currently use that feature though
2091 */
2092 mifcfg = readl(gp->regs + MIF_CFG);
2093 mifcfg &= ~MIF_CFG_POLL;
2094 writel(mifcfg, gp->regs + MIF_CFG);
2095
2096 if (wol && gp->has_wol) {
2097 unsigned char *e = &gp->dev->dev_addr[0];
2098 u32 csr;
2099
2100 /* Setup wake-on-lan for MAGIC packet */
2101 writel(MAC_RXCFG_HFE | MAC_RXCFG_SFCS | MAC_RXCFG_ENAB,
2102 gp->regs + MAC_RXCFG);
2103 writel((e[4] << 8) | e[5], gp->regs + WOL_MATCH0);
2104 writel((e[2] << 8) | e[3], gp->regs + WOL_MATCH1);
2105 writel((e[0] << 8) | e[1], gp->regs + WOL_MATCH2);
2106
2107 writel(WOL_MCOUNT_N | WOL_MCOUNT_M, gp->regs + WOL_MCOUNT);
2108 csr = WOL_WAKECSR_ENABLE;
2109 if ((readl(gp->regs + MAC_XIFCFG) & MAC_XIFCFG_GMII) == 0)
2110 csr |= WOL_WAKECSR_MII;
2111 writel(csr, gp->regs + WOL_WAKECSR);
2112 } else {
2113 writel(0, gp->regs + MAC_RXCFG);
2114 (void)readl(gp->regs + MAC_RXCFG);
2115 /* Machine sleep will die in strange ways if we
2116 * dont wait a bit here, looks like the chip takes
2117 * some time to really shut down
2118 */
2119 msleep(10);
2120 }
2121
2122 writel(0, gp->regs + MAC_TXCFG);
2123 writel(0, gp->regs + MAC_XIFCFG);
2124 writel(0, gp->regs + TXDMA_CFG);
2125 writel(0, gp->regs + RXDMA_CFG);
2126
2127 if (!wol) {
2128 gem_reset(gp);
2129 writel(MAC_TXRST_CMD, gp->regs + MAC_TXRST);
2130 writel(MAC_RXRST_CMD, gp->regs + MAC_RXRST);
2131
2132 if (found_mii_phy(gp) && gp->phy_mii.def->ops->suspend)
2133 gp->phy_mii.def->ops->suspend(&gp->phy_mii);
2134
2135 /* According to Apple, we must set the MDIO pins to this begnign
2136 * state or we may 1) eat more current, 2) damage some PHYs
2137 */
2138 writel(mifcfg | MIF_CFG_BBMODE, gp->regs + MIF_CFG);
2139 writel(0, gp->regs + MIF_BBCLK);
2140 writel(0, gp->regs + MIF_BBDATA);
2141 writel(0, gp->regs + MIF_BBOENAB);
2142 writel(MAC_XIFCFG_GMII | MAC_XIFCFG_LBCK, gp->regs + MAC_XIFCFG);
2143 (void) readl(gp->regs + MAC_XIFCFG);
2144 }
2145}
2146
2147static int gem_do_start(struct net_device *dev)
2148{
2149 struct gem *gp = netdev_priv(dev);
2150 int rc;
2151
2152 /* Enable the cell */
2153 gem_get_cell(gp);
2154
2155 /* Make sure PCI access and bus master are enabled */
2156 rc = pci_enable_device(gp->pdev);
2157 if (rc) {
2158 netdev_err(dev, "Failed to enable chip on PCI bus !\n");
2159
2160 /* Put cell and forget it for now, it will be considered as
2161 * still asleep, a new sleep cycle may bring it back
2162 */
2163 gem_put_cell(gp);
2164 return -ENXIO;
2165 }
2166 pci_set_master(gp->pdev);
2167
2168 /* Init & setup chip hardware */
2169 gem_reinit_chip(gp);
2170
2171 /* An interrupt might come in handy */
2172 rc = request_irq(gp->pdev->irq, gem_interrupt,
2173 IRQF_SHARED, dev->name, (void *)dev);
2174 if (rc) {
2175 netdev_err(dev, "failed to request irq !\n");
2176
2177 gem_reset(gp);
2178 gem_clean_rings(gp);
2179 gem_put_cell(gp);
2180 return rc;
2181 }
2182
2183 /* Mark us as attached again if we come from resume(), this has
2184 * no effect if we weren't detached and needs to be done now.
2185 */
2186 netif_device_attach(dev);
2187
2188 /* Restart NAPI & queues */
2189 gem_netif_start(gp);
2190
2191 /* Detect & init PHY, start autoneg etc... this will
2192 * eventually result in starting DMA operations when
2193 * the link is up
2194 */
2195 gem_init_phy(gp);
2196
2197 return 0;
2198}
2199
2200static void gem_do_stop(struct net_device *dev, int wol)
2201{
2202 struct gem *gp = netdev_priv(dev);
2203
2204 /* Stop NAPI and stop tx queue */
2205 gem_netif_stop(gp);
2206
2207 /* Make sure ints are disabled. We don't care about
2208 * synchronizing as NAPI is disabled, thus a stray
2209 * interrupt will do nothing bad (our irq handler
2210 * just schedules NAPI)
2211 */
2212 gem_disable_ints(gp);
2213
2214 /* Stop the link timer */
2215 del_timer_sync(&gp->link_timer);
2216
2217 /* We cannot cancel the reset task while holding the
2218 * rtnl lock, we'd get an A->B / B->A deadlock stituation
2219 * if we did. This is not an issue however as the reset
2220 * task is synchronized vs. us (rtnl_lock) and will do
2221 * nothing if the device is down or suspended. We do
2222 * still clear reset_task_pending to avoid a spurrious
2223 * reset later on in case we do resume before it gets
2224 * scheduled.
2225 */
2226 gp->reset_task_pending = 0;
2227
2228 /* If we are going to sleep with WOL */
2229 gem_stop_dma(gp);
2230 msleep(10);
2231 if (!wol)
2232 gem_reset(gp);
2233 msleep(10);
2234
2235 /* Get rid of rings */
2236 gem_clean_rings(gp);
2237
2238 /* No irq needed anymore */
2239 free_irq(gp->pdev->irq, (void *) dev);
2240
2241 /* Shut the PHY down eventually and setup WOL */
2242 gem_stop_phy(gp, wol);
2243
2244 /* Make sure bus master is disabled */
2245 pci_disable_device(gp->pdev);
2246
2247 /* Cell not needed neither if no WOL */
2248 if (!wol)
2249 gem_put_cell(gp);
2250}
2251
2252static void gem_reset_task(struct work_struct *work)
2253{
2254 struct gem *gp = container_of(work, struct gem, reset_task);
2255
2256 /* Lock out the network stack (essentially shield ourselves
2257 * against a racing open, close, control call, or suspend
2258 */
2259 rtnl_lock();
2260
2261 /* Skip the reset task if suspended or closed, or if it's
2262 * been cancelled by gem_do_stop (see comment there)
2263 */
2264 if (!netif_device_present(gp->dev) ||
2265 !netif_running(gp->dev) ||
2266 !gp->reset_task_pending) {
2267 rtnl_unlock();
2268 return;
2269 }
2270
2271 /* Stop the link timer */
2272 del_timer_sync(&gp->link_timer);
2273
2274 /* Stop NAPI and tx */
2275 gem_netif_stop(gp);
2276
2277 /* Reset the chip & rings */
2278 gem_reinit_chip(gp);
2279 if (gp->lstate == link_up)
2280 gem_set_link_modes(gp);
2281
2282 /* Restart NAPI and Tx */
2283 gem_netif_start(gp);
2284
2285 /* We are back ! */
2286 gp->reset_task_pending = 0;
2287
2288 /* If the link is not up, restart autoneg, else restart the
2289 * polling timer
2290 */
2291 if (gp->lstate != link_up)
2292 gem_begin_auto_negotiation(gp, NULL);
2293 else
2294 mod_timer(&gp->link_timer, jiffies + ((12 * HZ) / 10));
2295
2296 rtnl_unlock();
2297}
2298
2299static int gem_open(struct net_device *dev)
2300{
2301 /* We allow open while suspended, we just do nothing,
2302 * the chip will be initialized in resume()
2303 */
2304 if (netif_device_present(dev))
2305 return gem_do_start(dev);
2306 return 0;
2307}
2308
2309static int gem_close(struct net_device *dev)
2310{
2311 if (netif_device_present(dev))
2312 gem_do_stop(dev, 0);
2313
2314 return 0;
2315}
2316
2317#ifdef CONFIG_PM
2318static int gem_suspend(struct pci_dev *pdev, pm_message_t state)
2319{
2320 struct net_device *dev = pci_get_drvdata(pdev);
2321 struct gem *gp = netdev_priv(dev);
2322
2323 /* Lock the network stack first to avoid racing with open/close,
2324 * reset task and setting calls
2325 */
2326 rtnl_lock();
2327
2328 /* Not running, mark ourselves non-present, no need for
2329 * a lock here
2330 */
2331 if (!netif_running(dev)) {
2332 netif_device_detach(dev);
2333 rtnl_unlock();
2334 return 0;
2335 }
2336 netdev_info(dev, "suspending, WakeOnLan %s\n",
2337 (gp->wake_on_lan && netif_running(dev)) ?
2338 "enabled" : "disabled");
2339
2340 /* Tell the network stack we're gone. gem_do_stop() below will
2341 * synchronize with TX, stop NAPI etc...
2342 */
2343 netif_device_detach(dev);
2344
2345 /* Switch off chip, remember WOL setting */
2346 gp->asleep_wol = !!gp->wake_on_lan;
2347 gem_do_stop(dev, gp->asleep_wol);
2348
2349 /* Unlock the network stack */
2350 rtnl_unlock();
2351
2352 return 0;
2353}
2354
2355static int gem_resume(struct pci_dev *pdev)
2356{
2357 struct net_device *dev = pci_get_drvdata(pdev);
2358 struct gem *gp = netdev_priv(dev);
2359
2360 /* See locking comment in gem_suspend */
2361 rtnl_lock();
2362
2363 /* Not running, mark ourselves present, no need for
2364 * a lock here
2365 */
2366 if (!netif_running(dev)) {
2367 netif_device_attach(dev);
2368 rtnl_unlock();
2369 return 0;
2370 }
2371
2372 /* Restart chip. If that fails there isn't much we can do, we
2373 * leave things stopped.
2374 */
2375 gem_do_start(dev);
2376
2377 /* If we had WOL enabled, the cell clock was never turned off during
2378 * sleep, so we end up beeing unbalanced. Fix that here
2379 */
2380 if (gp->asleep_wol)
2381 gem_put_cell(gp);
2382
2383 /* Unlock the network stack */
2384 rtnl_unlock();
2385
2386 return 0;
2387}
2388#endif /* CONFIG_PM */
2389
2390static struct net_device_stats *gem_get_stats(struct net_device *dev)
2391{
2392 struct gem *gp = netdev_priv(dev);
2393
2394 /* I have seen this being called while the PM was in progress,
2395 * so we shield against this. Let's also not poke at registers
2396 * while the reset task is going on.
2397 *
2398 * TODO: Move stats collection elsewhere (link timer ?) and
2399 * make this a nop to avoid all those synchro issues
2400 */
2401 if (!netif_device_present(dev) || !netif_running(dev))
2402 goto bail;
2403
2404 /* Better safe than sorry... */
2405 if (WARN_ON(!gp->cell_enabled))
2406 goto bail;
2407
2408 dev->stats.rx_crc_errors += readl(gp->regs + MAC_FCSERR);
2409 writel(0, gp->regs + MAC_FCSERR);
2410
2411 dev->stats.rx_frame_errors += readl(gp->regs + MAC_AERR);
2412 writel(0, gp->regs + MAC_AERR);
2413
2414 dev->stats.rx_length_errors += readl(gp->regs + MAC_LERR);
2415 writel(0, gp->regs + MAC_LERR);
2416
2417 dev->stats.tx_aborted_errors += readl(gp->regs + MAC_ECOLL);
2418 dev->stats.collisions +=
2419 (readl(gp->regs + MAC_ECOLL) + readl(gp->regs + MAC_LCOLL));
2420 writel(0, gp->regs + MAC_ECOLL);
2421 writel(0, gp->regs + MAC_LCOLL);
2422 bail:
2423 return &dev->stats;
2424}
2425
2426static int gem_set_mac_address(struct net_device *dev, void *addr)
2427{
2428 struct sockaddr *macaddr = (struct sockaddr *) addr;
2429 struct gem *gp = netdev_priv(dev);
2430 unsigned char *e = &dev->dev_addr[0];
2431
2432 if (!is_valid_ether_addr(macaddr->sa_data))
2433 return -EADDRNOTAVAIL;
2434
2435 memcpy(dev->dev_addr, macaddr->sa_data, dev->addr_len);
2436
2437 /* We'll just catch it later when the device is up'd or resumed */
2438 if (!netif_running(dev) || !netif_device_present(dev))
2439 return 0;
2440
2441 /* Better safe than sorry... */
2442 if (WARN_ON(!gp->cell_enabled))
2443 return 0;
2444
2445 writel((e[4] << 8) | e[5], gp->regs + MAC_ADDR0);
2446 writel((e[2] << 8) | e[3], gp->regs + MAC_ADDR1);
2447 writel((e[0] << 8) | e[1], gp->regs + MAC_ADDR2);
2448
2449 return 0;
2450}
2451
2452static void gem_set_multicast(struct net_device *dev)
2453{
2454 struct gem *gp = netdev_priv(dev);
2455 u32 rxcfg, rxcfg_new;
2456 int limit = 10000;
2457
2458 if (!netif_running(dev) || !netif_device_present(dev))
2459 return;
2460
2461 /* Better safe than sorry... */
2462 if (gp->reset_task_pending || WARN_ON(!gp->cell_enabled))
2463 return;
2464
2465 rxcfg = readl(gp->regs + MAC_RXCFG);
2466 rxcfg_new = gem_setup_multicast(gp);
2467#ifdef STRIP_FCS
2468 rxcfg_new |= MAC_RXCFG_SFCS;
2469#endif
2470 gp->mac_rx_cfg = rxcfg_new;
2471
2472 writel(rxcfg & ~MAC_RXCFG_ENAB, gp->regs + MAC_RXCFG);
2473 while (readl(gp->regs + MAC_RXCFG) & MAC_RXCFG_ENAB) {
2474 if (!limit--)
2475 break;
2476 udelay(10);
2477 }
2478
2479 rxcfg &= ~(MAC_RXCFG_PROM | MAC_RXCFG_HFE);
2480 rxcfg |= rxcfg_new;
2481
2482 writel(rxcfg, gp->regs + MAC_RXCFG);
2483}
2484
2485/* Jumbo-grams don't seem to work :-( */
2486#define GEM_MIN_MTU ETH_MIN_MTU
2487#if 1
2488#define GEM_MAX_MTU ETH_DATA_LEN
2489#else
2490#define GEM_MAX_MTU 9000
2491#endif
2492
2493static int gem_change_mtu(struct net_device *dev, int new_mtu)
2494{
2495 struct gem *gp = netdev_priv(dev);
2496
2497 dev->mtu = new_mtu;
2498
2499 /* We'll just catch it later when the device is up'd or resumed */
2500 if (!netif_running(dev) || !netif_device_present(dev))
2501 return 0;
2502
2503 /* Better safe than sorry... */
2504 if (WARN_ON(!gp->cell_enabled))
2505 return 0;
2506
2507 gem_netif_stop(gp);
2508 gem_reinit_chip(gp);
2509 if (gp->lstate == link_up)
2510 gem_set_link_modes(gp);
2511 gem_netif_start(gp);
2512
2513 return 0;
2514}
2515
2516static void gem_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
2517{
2518 struct gem *gp = netdev_priv(dev);
2519
2520 strlcpy(info->driver, DRV_NAME, sizeof(info->driver));
2521 strlcpy(info->version, DRV_VERSION, sizeof(info->version));
2522 strlcpy(info->bus_info, pci_name(gp->pdev), sizeof(info->bus_info));
2523}
2524
2525static int gem_get_link_ksettings(struct net_device *dev,
2526 struct ethtool_link_ksettings *cmd)
2527{
2528 struct gem *gp = netdev_priv(dev);
2529 u32 supported, advertising;
2530
2531 if (gp->phy_type == phy_mii_mdio0 ||
2532 gp->phy_type == phy_mii_mdio1) {
2533 if (gp->phy_mii.def)
2534 supported = gp->phy_mii.def->features;
2535 else
2536 supported = (SUPPORTED_10baseT_Half |
2537 SUPPORTED_10baseT_Full);
2538
2539 /* XXX hardcoded stuff for now */
2540 cmd->base.port = PORT_MII;
2541 cmd->base.phy_address = 0; /* XXX fixed PHYAD */
2542
2543 /* Return current PHY settings */
2544 cmd->base.autoneg = gp->want_autoneg;
2545 cmd->base.speed = gp->phy_mii.speed;
2546 cmd->base.duplex = gp->phy_mii.duplex;
2547 advertising = gp->phy_mii.advertising;
2548
2549 /* If we started with a forced mode, we don't have a default
2550 * advertise set, we need to return something sensible so
2551 * userland can re-enable autoneg properly.
2552 */
2553 if (advertising == 0)
2554 advertising = supported;
2555 } else { // XXX PCS ?
2556 supported =
2557 (SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full |
2558 SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full |
2559 SUPPORTED_Autoneg);
2560 advertising = supported;
2561 cmd->base.speed = 0;
2562 cmd->base.duplex = 0;
2563 cmd->base.port = 0;
2564 cmd->base.phy_address = 0;
2565 cmd->base.autoneg = 0;
2566
2567 /* serdes means usually a Fibre connector, with most fixed */
2568 if (gp->phy_type == phy_serdes) {
2569 cmd->base.port = PORT_FIBRE;
2570 supported = (SUPPORTED_1000baseT_Half |
2571 SUPPORTED_1000baseT_Full |
2572 SUPPORTED_FIBRE | SUPPORTED_Autoneg |
2573 SUPPORTED_Pause | SUPPORTED_Asym_Pause);
2574 advertising = supported;
2575 if (gp->lstate == link_up)
2576 cmd->base.speed = SPEED_1000;
2577 cmd->base.duplex = DUPLEX_FULL;
2578 cmd->base.autoneg = 1;
2579 }
2580 }
2581
2582 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.supported,
2583 supported);
2584 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.advertising,
2585 advertising);
2586
2587 return 0;
2588}
2589
2590static int gem_set_link_ksettings(struct net_device *dev,
2591 const struct ethtool_link_ksettings *cmd)
2592{
2593 struct gem *gp = netdev_priv(dev);
2594 u32 speed = cmd->base.speed;
2595 u32 advertising;
2596
2597 ethtool_convert_link_mode_to_legacy_u32(&advertising,
2598 cmd->link_modes.advertising);
2599
2600 /* Verify the settings we care about. */
2601 if (cmd->base.autoneg != AUTONEG_ENABLE &&
2602 cmd->base.autoneg != AUTONEG_DISABLE)
2603 return -EINVAL;
2604
2605 if (cmd->base.autoneg == AUTONEG_ENABLE &&
2606 advertising == 0)
2607 return -EINVAL;
2608
2609 if (cmd->base.autoneg == AUTONEG_DISABLE &&
2610 ((speed != SPEED_1000 &&
2611 speed != SPEED_100 &&
2612 speed != SPEED_10) ||
2613 (cmd->base.duplex != DUPLEX_HALF &&
2614 cmd->base.duplex != DUPLEX_FULL)))
2615 return -EINVAL;
2616
2617 /* Apply settings and restart link process. */
2618 if (netif_device_present(gp->dev)) {
2619 del_timer_sync(&gp->link_timer);
2620 gem_begin_auto_negotiation(gp, cmd);
2621 }
2622
2623 return 0;
2624}
2625
2626static int gem_nway_reset(struct net_device *dev)
2627{
2628 struct gem *gp = netdev_priv(dev);
2629
2630 if (!gp->want_autoneg)
2631 return -EINVAL;
2632
2633 /* Restart link process */
2634 if (netif_device_present(gp->dev)) {
2635 del_timer_sync(&gp->link_timer);
2636 gem_begin_auto_negotiation(gp, NULL);
2637 }
2638
2639 return 0;
2640}
2641
2642static u32 gem_get_msglevel(struct net_device *dev)
2643{
2644 struct gem *gp = netdev_priv(dev);
2645 return gp->msg_enable;
2646}
2647
2648static void gem_set_msglevel(struct net_device *dev, u32 value)
2649{
2650 struct gem *gp = netdev_priv(dev);
2651 gp->msg_enable = value;
2652}
2653
2654
2655/* Add more when I understand how to program the chip */
2656/* like WAKE_UCAST | WAKE_MCAST | WAKE_BCAST */
2657
2658#define WOL_SUPPORTED_MASK (WAKE_MAGIC)
2659
2660static void gem_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2661{
2662 struct gem *gp = netdev_priv(dev);
2663
2664 /* Add more when I understand how to program the chip */
2665 if (gp->has_wol) {
2666 wol->supported = WOL_SUPPORTED_MASK;
2667 wol->wolopts = gp->wake_on_lan;
2668 } else {
2669 wol->supported = 0;
2670 wol->wolopts = 0;
2671 }
2672}
2673
2674static int gem_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2675{
2676 struct gem *gp = netdev_priv(dev);
2677
2678 if (!gp->has_wol)
2679 return -EOPNOTSUPP;
2680 gp->wake_on_lan = wol->wolopts & WOL_SUPPORTED_MASK;
2681 return 0;
2682}
2683
2684static const struct ethtool_ops gem_ethtool_ops = {
2685 .get_drvinfo = gem_get_drvinfo,
2686 .get_link = ethtool_op_get_link,
2687 .nway_reset = gem_nway_reset,
2688 .get_msglevel = gem_get_msglevel,
2689 .set_msglevel = gem_set_msglevel,
2690 .get_wol = gem_get_wol,
2691 .set_wol = gem_set_wol,
2692 .get_link_ksettings = gem_get_link_ksettings,
2693 .set_link_ksettings = gem_set_link_ksettings,
2694};
2695
2696static int gem_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2697{
2698 struct gem *gp = netdev_priv(dev);
2699 struct mii_ioctl_data *data = if_mii(ifr);
2700 int rc = -EOPNOTSUPP;
2701
2702 /* For SIOCGMIIREG and SIOCSMIIREG the core checks for us that
2703 * netif_device_present() is true and holds rtnl_lock for us
2704 * so we have nothing to worry about
2705 */
2706
2707 switch (cmd) {
2708 case SIOCGMIIPHY: /* Get address of MII PHY in use. */
2709 data->phy_id = gp->mii_phy_addr;
2710 /* Fallthrough... */
2711
2712 case SIOCGMIIREG: /* Read MII PHY register. */
2713 data->val_out = __sungem_phy_read(gp, data->phy_id & 0x1f,
2714 data->reg_num & 0x1f);
2715 rc = 0;
2716 break;
2717
2718 case SIOCSMIIREG: /* Write MII PHY register. */
2719 __sungem_phy_write(gp, data->phy_id & 0x1f, data->reg_num & 0x1f,
2720 data->val_in);
2721 rc = 0;
2722 break;
2723 }
2724 return rc;
2725}
2726
2727#if (!defined(CONFIG_SPARC) && !defined(CONFIG_PPC_PMAC))
2728/* Fetch MAC address from vital product data of PCI ROM. */
2729static int find_eth_addr_in_vpd(void __iomem *rom_base, int len, unsigned char *dev_addr)
2730{
2731 int this_offset;
2732
2733 for (this_offset = 0x20; this_offset < len; this_offset++) {
2734 void __iomem *p = rom_base + this_offset;
2735 int i;
2736
2737 if (readb(p + 0) != 0x90 ||
2738 readb(p + 1) != 0x00 ||
2739 readb(p + 2) != 0x09 ||
2740 readb(p + 3) != 0x4e ||
2741 readb(p + 4) != 0x41 ||
2742 readb(p + 5) != 0x06)
2743 continue;
2744
2745 this_offset += 6;
2746 p += 6;
2747
2748 for (i = 0; i < 6; i++)
2749 dev_addr[i] = readb(p + i);
2750 return 1;
2751 }
2752 return 0;
2753}
2754
2755static void get_gem_mac_nonobp(struct pci_dev *pdev, unsigned char *dev_addr)
2756{
2757 size_t size;
2758 void __iomem *p = pci_map_rom(pdev, &size);
2759
2760 if (p) {
2761 int found;
2762
2763 found = readb(p) == 0x55 &&
2764 readb(p + 1) == 0xaa &&
2765 find_eth_addr_in_vpd(p, (64 * 1024), dev_addr);
2766 pci_unmap_rom(pdev, p);
2767 if (found)
2768 return;
2769 }
2770
2771 /* Sun MAC prefix then 3 random bytes. */
2772 dev_addr[0] = 0x08;
2773 dev_addr[1] = 0x00;
2774 dev_addr[2] = 0x20;
2775 get_random_bytes(dev_addr + 3, 3);
2776}
2777#endif /* not Sparc and not PPC */
2778
2779static int gem_get_device_address(struct gem *gp)
2780{
2781#if defined(CONFIG_SPARC) || defined(CONFIG_PPC_PMAC)
2782 struct net_device *dev = gp->dev;
2783 const unsigned char *addr;
2784
2785 addr = of_get_property(gp->of_node, "local-mac-address", NULL);
2786 if (addr == NULL) {
2787#ifdef CONFIG_SPARC
2788 addr = idprom->id_ethaddr;
2789#else
2790 printk("\n");
2791 pr_err("%s: can't get mac-address\n", dev->name);
2792 return -1;
2793#endif
2794 }
2795 memcpy(dev->dev_addr, addr, ETH_ALEN);
2796#else
2797 get_gem_mac_nonobp(gp->pdev, gp->dev->dev_addr);
2798#endif
2799 return 0;
2800}
2801
2802static void gem_remove_one(struct pci_dev *pdev)
2803{
2804 struct net_device *dev = pci_get_drvdata(pdev);
2805
2806 if (dev) {
2807 struct gem *gp = netdev_priv(dev);
2808
2809 unregister_netdev(dev);
2810
2811 /* Ensure reset task is truly gone */
2812 cancel_work_sync(&gp->reset_task);
2813
2814 /* Free resources */
2815 pci_free_consistent(pdev,
2816 sizeof(struct gem_init_block),
2817 gp->init_block,
2818 gp->gblock_dvma);
2819 iounmap(gp->regs);
2820 pci_release_regions(pdev);
2821 free_netdev(dev);
2822 }
2823}
2824
2825static const struct net_device_ops gem_netdev_ops = {
2826 .ndo_open = gem_open,
2827 .ndo_stop = gem_close,
2828 .ndo_start_xmit = gem_start_xmit,
2829 .ndo_get_stats = gem_get_stats,
2830 .ndo_set_rx_mode = gem_set_multicast,
2831 .ndo_do_ioctl = gem_ioctl,
2832 .ndo_tx_timeout = gem_tx_timeout,
2833 .ndo_change_mtu = gem_change_mtu,
2834 .ndo_validate_addr = eth_validate_addr,
2835 .ndo_set_mac_address = gem_set_mac_address,
2836#ifdef CONFIG_NET_POLL_CONTROLLER
2837 .ndo_poll_controller = gem_poll_controller,
2838#endif
2839};
2840
2841static int gem_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
2842{
2843 unsigned long gemreg_base, gemreg_len;
2844 struct net_device *dev;
2845 struct gem *gp;
2846 int err, pci_using_dac;
2847
2848 printk_once(KERN_INFO "%s", version);
2849
2850 /* Apple gmac note: during probe, the chip is powered up by
2851 * the arch code to allow the code below to work (and to let
2852 * the chip be probed on the config space. It won't stay powered
2853 * up until the interface is brought up however, so we can't rely
2854 * on register configuration done at this point.
2855 */
2856 err = pci_enable_device(pdev);
2857 if (err) {
2858 pr_err("Cannot enable MMIO operation, aborting\n");
2859 return err;
2860 }
2861 pci_set_master(pdev);
2862
2863 /* Configure DMA attributes. */
2864
2865 /* All of the GEM documentation states that 64-bit DMA addressing
2866 * is fully supported and should work just fine. However the
2867 * front end for RIO based GEMs is different and only supports
2868 * 32-bit addressing.
2869 *
2870 * For now we assume the various PPC GEMs are 32-bit only as well.
2871 */
2872 if (pdev->vendor == PCI_VENDOR_ID_SUN &&
2873 pdev->device == PCI_DEVICE_ID_SUN_GEM &&
2874 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
2875 pci_using_dac = 1;
2876 } else {
2877 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
2878 if (err) {
2879 pr_err("No usable DMA configuration, aborting\n");
2880 goto err_disable_device;
2881 }
2882 pci_using_dac = 0;
2883 }
2884
2885 gemreg_base = pci_resource_start(pdev, 0);
2886 gemreg_len = pci_resource_len(pdev, 0);
2887
2888 if ((pci_resource_flags(pdev, 0) & IORESOURCE_IO) != 0) {
2889 pr_err("Cannot find proper PCI device base address, aborting\n");
2890 err = -ENODEV;
2891 goto err_disable_device;
2892 }
2893
2894 dev = alloc_etherdev(sizeof(*gp));
2895 if (!dev) {
2896 err = -ENOMEM;
2897 goto err_disable_device;
2898 }
2899 SET_NETDEV_DEV(dev, &pdev->dev);
2900
2901 gp = netdev_priv(dev);
2902
2903 err = pci_request_regions(pdev, DRV_NAME);
2904 if (err) {
2905 pr_err("Cannot obtain PCI resources, aborting\n");
2906 goto err_out_free_netdev;
2907 }
2908
2909 gp->pdev = pdev;
2910 gp->dev = dev;
2911
2912 gp->msg_enable = DEFAULT_MSG;
2913
2914 timer_setup(&gp->link_timer, gem_link_timer, 0);
2915
2916 INIT_WORK(&gp->reset_task, gem_reset_task);
2917
2918 gp->lstate = link_down;
2919 gp->timer_ticks = 0;
2920 netif_carrier_off(dev);
2921
2922 gp->regs = ioremap(gemreg_base, gemreg_len);
2923 if (!gp->regs) {
2924 pr_err("Cannot map device registers, aborting\n");
2925 err = -EIO;
2926 goto err_out_free_res;
2927 }
2928
2929 /* On Apple, we want a reference to the Open Firmware device-tree
2930 * node. We use it for clock control.
2931 */
2932#if defined(CONFIG_PPC_PMAC) || defined(CONFIG_SPARC)
2933 gp->of_node = pci_device_to_OF_node(pdev);
2934#endif
2935
2936 /* Only Apple version supports WOL afaik */
2937 if (pdev->vendor == PCI_VENDOR_ID_APPLE)
2938 gp->has_wol = 1;
2939
2940 /* Make sure cell is enabled */
2941 gem_get_cell(gp);
2942
2943 /* Make sure everything is stopped and in init state */
2944 gem_reset(gp);
2945
2946 /* Fill up the mii_phy structure (even if we won't use it) */
2947 gp->phy_mii.dev = dev;
2948 gp->phy_mii.mdio_read = _sungem_phy_read;
2949 gp->phy_mii.mdio_write = _sungem_phy_write;
2950#ifdef CONFIG_PPC_PMAC
2951 gp->phy_mii.platform_data = gp->of_node;
2952#endif
2953 /* By default, we start with autoneg */
2954 gp->want_autoneg = 1;
2955
2956 /* Check fifo sizes, PHY type, etc... */
2957 if (gem_check_invariants(gp)) {
2958 err = -ENODEV;
2959 goto err_out_iounmap;
2960 }
2961
2962 /* It is guaranteed that the returned buffer will be at least
2963 * PAGE_SIZE aligned.
2964 */
2965 gp->init_block = (struct gem_init_block *)
2966 pci_alloc_consistent(pdev, sizeof(struct gem_init_block),
2967 &gp->gblock_dvma);
2968 if (!gp->init_block) {
2969 pr_err("Cannot allocate init block, aborting\n");
2970 err = -ENOMEM;
2971 goto err_out_iounmap;
2972 }
2973
2974 err = gem_get_device_address(gp);
2975 if (err)
2976 goto err_out_free_consistent;
2977
2978 dev->netdev_ops = &gem_netdev_ops;
2979 netif_napi_add(dev, &gp->napi, gem_poll, 64);
2980 dev->ethtool_ops = &gem_ethtool_ops;
2981 dev->watchdog_timeo = 5 * HZ;
2982 dev->dma = 0;
2983
2984 /* Set that now, in case PM kicks in now */
2985 pci_set_drvdata(pdev, dev);
2986
2987 /* We can do scatter/gather and HW checksum */
2988 dev->hw_features = NETIF_F_SG | NETIF_F_HW_CSUM;
2989 dev->features |= dev->hw_features | NETIF_F_RXCSUM;
2990 if (pci_using_dac)
2991 dev->features |= NETIF_F_HIGHDMA;
2992
2993 /* MTU range: 68 - 1500 (Jumbo mode is broken) */
2994 dev->min_mtu = GEM_MIN_MTU;
2995 dev->max_mtu = GEM_MAX_MTU;
2996
2997 /* Register with kernel */
2998 if (register_netdev(dev)) {
2999 pr_err("Cannot register net device, aborting\n");
3000 err = -ENOMEM;
3001 goto err_out_free_consistent;
3002 }
3003
3004 /* Undo the get_cell with appropriate locking (we could use
3005 * ndo_init/uninit but that would be even more clumsy imho)
3006 */
3007 rtnl_lock();
3008 gem_put_cell(gp);
3009 rtnl_unlock();
3010
3011 netdev_info(dev, "Sun GEM (PCI) 10/100/1000BaseT Ethernet %pM\n",
3012 dev->dev_addr);
3013 return 0;
3014
3015err_out_free_consistent:
3016 gem_remove_one(pdev);
3017err_out_iounmap:
3018 gem_put_cell(gp);
3019 iounmap(gp->regs);
3020
3021err_out_free_res:
3022 pci_release_regions(pdev);
3023
3024err_out_free_netdev:
3025 free_netdev(dev);
3026err_disable_device:
3027 pci_disable_device(pdev);
3028 return err;
3029
3030}
3031
3032
3033static struct pci_driver gem_driver = {
3034 .name = GEM_MODULE_NAME,
3035 .id_table = gem_pci_tbl,
3036 .probe = gem_init_one,
3037 .remove = gem_remove_one,
3038#ifdef CONFIG_PM
3039 .suspend = gem_suspend,
3040 .resume = gem_resume,
3041#endif /* CONFIG_PM */
3042};
3043
3044module_pci_driver(gem_driver);