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1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Fast Ethernet Controller (FEC) driver for Motorola MPC8xx.
4 * Copyright (c) 1997 Dan Malek (dmalek@jlc.net)
5 *
6 * Right now, I am very wasteful with the buffers. I allocate memory
7 * pages and then divide them into 2K frame buffers. This way I know I
8 * have buffers large enough to hold one frame within one buffer descriptor.
9 * Once I get this working, I will use 64 or 128 byte CPM buffers, which
10 * will be much more memory efficient and will easily handle lots of
11 * small packets.
12 *
13 * Much better multiple PHY support by Magnus Damm.
14 * Copyright (c) 2000 Ericsson Radio Systems AB.
15 *
16 * Support for FEC controller of ColdFire processors.
17 * Copyright (c) 2001-2005 Greg Ungerer (gerg@snapgear.com)
18 *
19 * Bug fixes and cleanup by Philippe De Muyter (phdm@macqel.be)
20 * Copyright (c) 2004-2006 Macq Electronique SA.
21 *
22 * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
23 */
24
25#include <linux/module.h>
26#include <linux/kernel.h>
27#include <linux/string.h>
28#include <linux/pm_runtime.h>
29#include <linux/ptrace.h>
30#include <linux/errno.h>
31#include <linux/ioport.h>
32#include <linux/slab.h>
33#include <linux/interrupt.h>
34#include <linux/delay.h>
35#include <linux/netdevice.h>
36#include <linux/etherdevice.h>
37#include <linux/skbuff.h>
38#include <linux/in.h>
39#include <linux/ip.h>
40#include <net/ip.h>
41#include <net/page_pool/helpers.h>
42#include <net/selftests.h>
43#include <net/tso.h>
44#include <linux/tcp.h>
45#include <linux/udp.h>
46#include <linux/icmp.h>
47#include <linux/spinlock.h>
48#include <linux/workqueue.h>
49#include <linux/bitops.h>
50#include <linux/io.h>
51#include <linux/irq.h>
52#include <linux/clk.h>
53#include <linux/crc32.h>
54#include <linux/platform_device.h>
55#include <linux/property.h>
56#include <linux/mdio.h>
57#include <linux/phy.h>
58#include <linux/fec.h>
59#include <linux/of.h>
60#include <linux/of_mdio.h>
61#include <linux/of_net.h>
62#include <linux/regulator/consumer.h>
63#include <linux/if_vlan.h>
64#include <linux/pinctrl/consumer.h>
65#include <linux/gpio/consumer.h>
66#include <linux/prefetch.h>
67#include <linux/mfd/syscon.h>
68#include <linux/regmap.h>
69#include <soc/imx/cpuidle.h>
70#include <linux/filter.h>
71#include <linux/bpf.h>
72#include <linux/bpf_trace.h>
73
74#include <asm/cacheflush.h>
75
76#include "fec.h"
77
78static void set_multicast_list(struct net_device *ndev);
79static void fec_enet_itr_coal_set(struct net_device *ndev);
80static int fec_enet_xdp_tx_xmit(struct fec_enet_private *fep,
81 int cpu, struct xdp_buff *xdp,
82 u32 dma_sync_len);
83
84#define DRIVER_NAME "fec"
85
86static const u16 fec_enet_vlan_pri_to_queue[8] = {0, 0, 1, 1, 1, 2, 2, 2};
87
88#define FEC_ENET_RSEM_V 0x84
89#define FEC_ENET_RSFL_V 16
90#define FEC_ENET_RAEM_V 0x8
91#define FEC_ENET_RAFL_V 0x8
92#define FEC_ENET_OPD_V 0xFFF0
93#define FEC_MDIO_PM_TIMEOUT 100 /* ms */
94
95#define FEC_ENET_XDP_PASS 0
96#define FEC_ENET_XDP_CONSUMED BIT(0)
97#define FEC_ENET_XDP_TX BIT(1)
98#define FEC_ENET_XDP_REDIR BIT(2)
99
100struct fec_devinfo {
101 u32 quirks;
102};
103
104static const struct fec_devinfo fec_imx25_info = {
105 .quirks = FEC_QUIRK_USE_GASKET | FEC_QUIRK_MIB_CLEAR |
106 FEC_QUIRK_HAS_FRREG | FEC_QUIRK_HAS_MDIO_C45,
107};
108
109static const struct fec_devinfo fec_imx27_info = {
110 .quirks = FEC_QUIRK_MIB_CLEAR | FEC_QUIRK_HAS_FRREG |
111 FEC_QUIRK_HAS_MDIO_C45,
112};
113
114static const struct fec_devinfo fec_imx28_info = {
115 .quirks = FEC_QUIRK_ENET_MAC | FEC_QUIRK_SWAP_FRAME |
116 FEC_QUIRK_SINGLE_MDIO | FEC_QUIRK_HAS_RACC |
117 FEC_QUIRK_HAS_FRREG | FEC_QUIRK_CLEAR_SETUP_MII |
118 FEC_QUIRK_NO_HARD_RESET | FEC_QUIRK_HAS_MDIO_C45,
119};
120
121static const struct fec_devinfo fec_imx6q_info = {
122 .quirks = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT |
123 FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM |
124 FEC_QUIRK_HAS_VLAN | FEC_QUIRK_ERR006358 |
125 FEC_QUIRK_HAS_RACC | FEC_QUIRK_CLEAR_SETUP_MII |
126 FEC_QUIRK_HAS_PMQOS | FEC_QUIRK_HAS_MDIO_C45,
127};
128
129static const struct fec_devinfo fec_mvf600_info = {
130 .quirks = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_RACC |
131 FEC_QUIRK_HAS_MDIO_C45,
132};
133
134static const struct fec_devinfo fec_imx6x_info = {
135 .quirks = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT |
136 FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM |
137 FEC_QUIRK_HAS_VLAN | FEC_QUIRK_HAS_AVB |
138 FEC_QUIRK_ERR007885 | FEC_QUIRK_BUG_CAPTURE |
139 FEC_QUIRK_HAS_RACC | FEC_QUIRK_HAS_COALESCE |
140 FEC_QUIRK_CLEAR_SETUP_MII | FEC_QUIRK_HAS_MULTI_QUEUES |
141 FEC_QUIRK_HAS_MDIO_C45,
142};
143
144static const struct fec_devinfo fec_imx6ul_info = {
145 .quirks = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT |
146 FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM |
147 FEC_QUIRK_HAS_VLAN | FEC_QUIRK_ERR007885 |
148 FEC_QUIRK_BUG_CAPTURE | FEC_QUIRK_HAS_RACC |
149 FEC_QUIRK_HAS_COALESCE | FEC_QUIRK_CLEAR_SETUP_MII |
150 FEC_QUIRK_HAS_MDIO_C45,
151};
152
153static const struct fec_devinfo fec_imx8mq_info = {
154 .quirks = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT |
155 FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM |
156 FEC_QUIRK_HAS_VLAN | FEC_QUIRK_HAS_AVB |
157 FEC_QUIRK_ERR007885 | FEC_QUIRK_BUG_CAPTURE |
158 FEC_QUIRK_HAS_RACC | FEC_QUIRK_HAS_COALESCE |
159 FEC_QUIRK_CLEAR_SETUP_MII | FEC_QUIRK_HAS_MULTI_QUEUES |
160 FEC_QUIRK_HAS_EEE | FEC_QUIRK_WAKEUP_FROM_INT2 |
161 FEC_QUIRK_HAS_MDIO_C45,
162};
163
164static const struct fec_devinfo fec_imx8qm_info = {
165 .quirks = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT |
166 FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM |
167 FEC_QUIRK_HAS_VLAN | FEC_QUIRK_HAS_AVB |
168 FEC_QUIRK_ERR007885 | FEC_QUIRK_BUG_CAPTURE |
169 FEC_QUIRK_HAS_RACC | FEC_QUIRK_HAS_COALESCE |
170 FEC_QUIRK_CLEAR_SETUP_MII | FEC_QUIRK_HAS_MULTI_QUEUES |
171 FEC_QUIRK_DELAYED_CLKS_SUPPORT | FEC_QUIRK_HAS_MDIO_C45,
172};
173
174static const struct fec_devinfo fec_s32v234_info = {
175 .quirks = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT |
176 FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM |
177 FEC_QUIRK_HAS_VLAN | FEC_QUIRK_HAS_AVB |
178 FEC_QUIRK_ERR007885 | FEC_QUIRK_BUG_CAPTURE |
179 FEC_QUIRK_HAS_MDIO_C45,
180};
181
182static struct platform_device_id fec_devtype[] = {
183 {
184 /* keep it for coldfire */
185 .name = DRIVER_NAME,
186 .driver_data = 0,
187 }, {
188 /* sentinel */
189 }
190};
191MODULE_DEVICE_TABLE(platform, fec_devtype);
192
193static const struct of_device_id fec_dt_ids[] = {
194 { .compatible = "fsl,imx25-fec", .data = &fec_imx25_info, },
195 { .compatible = "fsl,imx27-fec", .data = &fec_imx27_info, },
196 { .compatible = "fsl,imx28-fec", .data = &fec_imx28_info, },
197 { .compatible = "fsl,imx6q-fec", .data = &fec_imx6q_info, },
198 { .compatible = "fsl,mvf600-fec", .data = &fec_mvf600_info, },
199 { .compatible = "fsl,imx6sx-fec", .data = &fec_imx6x_info, },
200 { .compatible = "fsl,imx6ul-fec", .data = &fec_imx6ul_info, },
201 { .compatible = "fsl,imx8mq-fec", .data = &fec_imx8mq_info, },
202 { .compatible = "fsl,imx8qm-fec", .data = &fec_imx8qm_info, },
203 { .compatible = "fsl,s32v234-fec", .data = &fec_s32v234_info, },
204 { /* sentinel */ }
205};
206MODULE_DEVICE_TABLE(of, fec_dt_ids);
207
208static unsigned char macaddr[ETH_ALEN];
209module_param_array(macaddr, byte, NULL, 0);
210MODULE_PARM_DESC(macaddr, "FEC Ethernet MAC address");
211
212#if defined(CONFIG_M5272)
213/*
214 * Some hardware gets it MAC address out of local flash memory.
215 * if this is non-zero then assume it is the address to get MAC from.
216 */
217#if defined(CONFIG_NETtel)
218#define FEC_FLASHMAC 0xf0006006
219#elif defined(CONFIG_GILBARCONAP) || defined(CONFIG_SCALES)
220#define FEC_FLASHMAC 0xf0006000
221#elif defined(CONFIG_CANCam)
222#define FEC_FLASHMAC 0xf0020000
223#elif defined (CONFIG_M5272C3)
224#define FEC_FLASHMAC (0xffe04000 + 4)
225#elif defined(CONFIG_MOD5272)
226#define FEC_FLASHMAC 0xffc0406b
227#else
228#define FEC_FLASHMAC 0
229#endif
230#endif /* CONFIG_M5272 */
231
232/* The FEC stores dest/src/type/vlan, data, and checksum for receive packets.
233 *
234 * 2048 byte skbufs are allocated. However, alignment requirements
235 * varies between FEC variants. Worst case is 64, so round down by 64.
236 */
237#define PKT_MAXBUF_SIZE (round_down(2048 - 64, 64))
238#define PKT_MINBUF_SIZE 64
239
240/* FEC receive acceleration */
241#define FEC_RACC_IPDIS BIT(1)
242#define FEC_RACC_PRODIS BIT(2)
243#define FEC_RACC_SHIFT16 BIT(7)
244#define FEC_RACC_OPTIONS (FEC_RACC_IPDIS | FEC_RACC_PRODIS)
245
246/* MIB Control Register */
247#define FEC_MIB_CTRLSTAT_DISABLE BIT(31)
248
249/*
250 * The 5270/5271/5280/5282/532x RX control register also contains maximum frame
251 * size bits. Other FEC hardware does not, so we need to take that into
252 * account when setting it.
253 */
254#if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
255 defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_ARM) || \
256 defined(CONFIG_ARM64)
257#define OPT_FRAME_SIZE (PKT_MAXBUF_SIZE << 16)
258#else
259#define OPT_FRAME_SIZE 0
260#endif
261
262/* FEC MII MMFR bits definition */
263#define FEC_MMFR_ST (1 << 30)
264#define FEC_MMFR_ST_C45 (0)
265#define FEC_MMFR_OP_READ (2 << 28)
266#define FEC_MMFR_OP_READ_C45 (3 << 28)
267#define FEC_MMFR_OP_WRITE (1 << 28)
268#define FEC_MMFR_OP_ADDR_WRITE (0)
269#define FEC_MMFR_PA(v) ((v & 0x1f) << 23)
270#define FEC_MMFR_RA(v) ((v & 0x1f) << 18)
271#define FEC_MMFR_TA (2 << 16)
272#define FEC_MMFR_DATA(v) (v & 0xffff)
273/* FEC ECR bits definition */
274#define FEC_ECR_RESET BIT(0)
275#define FEC_ECR_ETHEREN BIT(1)
276#define FEC_ECR_MAGICEN BIT(2)
277#define FEC_ECR_SLEEP BIT(3)
278#define FEC_ECR_EN1588 BIT(4)
279#define FEC_ECR_BYTESWP BIT(8)
280/* FEC RCR bits definition */
281#define FEC_RCR_LOOP BIT(0)
282#define FEC_RCR_HALFDPX BIT(1)
283#define FEC_RCR_MII BIT(2)
284#define FEC_RCR_PROMISC BIT(3)
285#define FEC_RCR_BC_REJ BIT(4)
286#define FEC_RCR_FLOWCTL BIT(5)
287#define FEC_RCR_RMII BIT(8)
288#define FEC_RCR_10BASET BIT(9)
289/* TX WMARK bits */
290#define FEC_TXWMRK_STRFWD BIT(8)
291
292#define FEC_MII_TIMEOUT 30000 /* us */
293
294/* Transmitter timeout */
295#define TX_TIMEOUT (2 * HZ)
296
297#define FEC_PAUSE_FLAG_AUTONEG 0x1
298#define FEC_PAUSE_FLAG_ENABLE 0x2
299#define FEC_WOL_HAS_MAGIC_PACKET (0x1 << 0)
300#define FEC_WOL_FLAG_ENABLE (0x1 << 1)
301#define FEC_WOL_FLAG_SLEEP_ON (0x1 << 2)
302
303/* Max number of allowed TCP segments for software TSO */
304#define FEC_MAX_TSO_SEGS 100
305#define FEC_MAX_SKB_DESCS (FEC_MAX_TSO_SEGS * 2 + MAX_SKB_FRAGS)
306
307#define IS_TSO_HEADER(txq, addr) \
308 ((addr >= txq->tso_hdrs_dma) && \
309 (addr < txq->tso_hdrs_dma + txq->bd.ring_size * TSO_HEADER_SIZE))
310
311static int mii_cnt;
312
313static struct bufdesc *fec_enet_get_nextdesc(struct bufdesc *bdp,
314 struct bufdesc_prop *bd)
315{
316 return (bdp >= bd->last) ? bd->base
317 : (struct bufdesc *)(((void *)bdp) + bd->dsize);
318}
319
320static struct bufdesc *fec_enet_get_prevdesc(struct bufdesc *bdp,
321 struct bufdesc_prop *bd)
322{
323 return (bdp <= bd->base) ? bd->last
324 : (struct bufdesc *)(((void *)bdp) - bd->dsize);
325}
326
327static int fec_enet_get_bd_index(struct bufdesc *bdp,
328 struct bufdesc_prop *bd)
329{
330 return ((const char *)bdp - (const char *)bd->base) >> bd->dsize_log2;
331}
332
333static int fec_enet_get_free_txdesc_num(struct fec_enet_priv_tx_q *txq)
334{
335 int entries;
336
337 entries = (((const char *)txq->dirty_tx -
338 (const char *)txq->bd.cur) >> txq->bd.dsize_log2) - 1;
339
340 return entries >= 0 ? entries : entries + txq->bd.ring_size;
341}
342
343static void swap_buffer(void *bufaddr, int len)
344{
345 int i;
346 unsigned int *buf = bufaddr;
347
348 for (i = 0; i < len; i += 4, buf++)
349 swab32s(buf);
350}
351
352static void fec_dump(struct net_device *ndev)
353{
354 struct fec_enet_private *fep = netdev_priv(ndev);
355 struct bufdesc *bdp;
356 struct fec_enet_priv_tx_q *txq;
357 int index = 0;
358
359 netdev_info(ndev, "TX ring dump\n");
360 pr_info("Nr SC addr len SKB\n");
361
362 txq = fep->tx_queue[0];
363 bdp = txq->bd.base;
364
365 do {
366 pr_info("%3u %c%c 0x%04x 0x%08x %4u %p\n",
367 index,
368 bdp == txq->bd.cur ? 'S' : ' ',
369 bdp == txq->dirty_tx ? 'H' : ' ',
370 fec16_to_cpu(bdp->cbd_sc),
371 fec32_to_cpu(bdp->cbd_bufaddr),
372 fec16_to_cpu(bdp->cbd_datlen),
373 txq->tx_buf[index].buf_p);
374 bdp = fec_enet_get_nextdesc(bdp, &txq->bd);
375 index++;
376 } while (bdp != txq->bd.base);
377}
378
379/*
380 * Coldfire does not support DMA coherent allocations, and has historically used
381 * a band-aid with a manual flush in fec_enet_rx_queue.
382 */
383#if defined(CONFIG_COLDFIRE) && !defined(CONFIG_COLDFIRE_COHERENT_DMA)
384static void *fec_dma_alloc(struct device *dev, size_t size, dma_addr_t *handle,
385 gfp_t gfp)
386{
387 return dma_alloc_noncoherent(dev, size, handle, DMA_BIDIRECTIONAL, gfp);
388}
389
390static void fec_dma_free(struct device *dev, size_t size, void *cpu_addr,
391 dma_addr_t handle)
392{
393 dma_free_noncoherent(dev, size, cpu_addr, handle, DMA_BIDIRECTIONAL);
394}
395#else /* !CONFIG_COLDFIRE || CONFIG_COLDFIRE_COHERENT_DMA */
396static void *fec_dma_alloc(struct device *dev, size_t size, dma_addr_t *handle,
397 gfp_t gfp)
398{
399 return dma_alloc_coherent(dev, size, handle, gfp);
400}
401
402static void fec_dma_free(struct device *dev, size_t size, void *cpu_addr,
403 dma_addr_t handle)
404{
405 dma_free_coherent(dev, size, cpu_addr, handle);
406}
407#endif /* !CONFIG_COLDFIRE || CONFIG_COLDFIRE_COHERENT_DMA */
408
409struct fec_dma_devres {
410 size_t size;
411 void *vaddr;
412 dma_addr_t dma_handle;
413};
414
415static void fec_dmam_release(struct device *dev, void *res)
416{
417 struct fec_dma_devres *this = res;
418
419 fec_dma_free(dev, this->size, this->vaddr, this->dma_handle);
420}
421
422static void *fec_dmam_alloc(struct device *dev, size_t size, dma_addr_t *handle,
423 gfp_t gfp)
424{
425 struct fec_dma_devres *dr;
426 void *vaddr;
427
428 dr = devres_alloc(fec_dmam_release, sizeof(*dr), gfp);
429 if (!dr)
430 return NULL;
431 vaddr = fec_dma_alloc(dev, size, handle, gfp);
432 if (!vaddr) {
433 devres_free(dr);
434 return NULL;
435 }
436 dr->vaddr = vaddr;
437 dr->dma_handle = *handle;
438 dr->size = size;
439 devres_add(dev, dr);
440 return vaddr;
441}
442
443static inline bool is_ipv4_pkt(struct sk_buff *skb)
444{
445 return skb->protocol == htons(ETH_P_IP) && ip_hdr(skb)->version == 4;
446}
447
448static int
449fec_enet_clear_csum(struct sk_buff *skb, struct net_device *ndev)
450{
451 /* Only run for packets requiring a checksum. */
452 if (skb->ip_summed != CHECKSUM_PARTIAL)
453 return 0;
454
455 if (unlikely(skb_cow_head(skb, 0)))
456 return -1;
457
458 if (is_ipv4_pkt(skb))
459 ip_hdr(skb)->check = 0;
460 *(__sum16 *)(skb->head + skb->csum_start + skb->csum_offset) = 0;
461
462 return 0;
463}
464
465static int
466fec_enet_create_page_pool(struct fec_enet_private *fep,
467 struct fec_enet_priv_rx_q *rxq, int size)
468{
469 struct bpf_prog *xdp_prog = READ_ONCE(fep->xdp_prog);
470 struct page_pool_params pp_params = {
471 .order = 0,
472 .flags = PP_FLAG_DMA_MAP | PP_FLAG_DMA_SYNC_DEV,
473 .pool_size = size,
474 .nid = dev_to_node(&fep->pdev->dev),
475 .dev = &fep->pdev->dev,
476 .dma_dir = xdp_prog ? DMA_BIDIRECTIONAL : DMA_FROM_DEVICE,
477 .offset = FEC_ENET_XDP_HEADROOM,
478 .max_len = FEC_ENET_RX_FRSIZE,
479 };
480 int err;
481
482 rxq->page_pool = page_pool_create(&pp_params);
483 if (IS_ERR(rxq->page_pool)) {
484 err = PTR_ERR(rxq->page_pool);
485 rxq->page_pool = NULL;
486 return err;
487 }
488
489 err = xdp_rxq_info_reg(&rxq->xdp_rxq, fep->netdev, rxq->id, 0);
490 if (err < 0)
491 goto err_free_pp;
492
493 err = xdp_rxq_info_reg_mem_model(&rxq->xdp_rxq, MEM_TYPE_PAGE_POOL,
494 rxq->page_pool);
495 if (err)
496 goto err_unregister_rxq;
497
498 return 0;
499
500err_unregister_rxq:
501 xdp_rxq_info_unreg(&rxq->xdp_rxq);
502err_free_pp:
503 page_pool_destroy(rxq->page_pool);
504 rxq->page_pool = NULL;
505 return err;
506}
507
508static struct bufdesc *
509fec_enet_txq_submit_frag_skb(struct fec_enet_priv_tx_q *txq,
510 struct sk_buff *skb,
511 struct net_device *ndev)
512{
513 struct fec_enet_private *fep = netdev_priv(ndev);
514 struct bufdesc *bdp = txq->bd.cur;
515 struct bufdesc_ex *ebdp;
516 int nr_frags = skb_shinfo(skb)->nr_frags;
517 int frag, frag_len;
518 unsigned short status;
519 unsigned int estatus = 0;
520 skb_frag_t *this_frag;
521 unsigned int index;
522 void *bufaddr;
523 dma_addr_t addr;
524 int i;
525
526 for (frag = 0; frag < nr_frags; frag++) {
527 this_frag = &skb_shinfo(skb)->frags[frag];
528 bdp = fec_enet_get_nextdesc(bdp, &txq->bd);
529 ebdp = (struct bufdesc_ex *)bdp;
530
531 status = fec16_to_cpu(bdp->cbd_sc);
532 status &= ~BD_ENET_TX_STATS;
533 status |= (BD_ENET_TX_TC | BD_ENET_TX_READY);
534 frag_len = skb_frag_size(&skb_shinfo(skb)->frags[frag]);
535
536 /* Handle the last BD specially */
537 if (frag == nr_frags - 1) {
538 status |= (BD_ENET_TX_INTR | BD_ENET_TX_LAST);
539 if (fep->bufdesc_ex) {
540 estatus |= BD_ENET_TX_INT;
541 if (unlikely(skb_shinfo(skb)->tx_flags &
542 SKBTX_HW_TSTAMP && fep->hwts_tx_en))
543 estatus |= BD_ENET_TX_TS;
544 }
545 }
546
547 if (fep->bufdesc_ex) {
548 if (fep->quirks & FEC_QUIRK_HAS_AVB)
549 estatus |= FEC_TX_BD_FTYPE(txq->bd.qid);
550 if (skb->ip_summed == CHECKSUM_PARTIAL)
551 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS;
552
553 ebdp->cbd_bdu = 0;
554 ebdp->cbd_esc = cpu_to_fec32(estatus);
555 }
556
557 bufaddr = skb_frag_address(this_frag);
558
559 index = fec_enet_get_bd_index(bdp, &txq->bd);
560 if (((unsigned long) bufaddr) & fep->tx_align ||
561 fep->quirks & FEC_QUIRK_SWAP_FRAME) {
562 memcpy(txq->tx_bounce[index], bufaddr, frag_len);
563 bufaddr = txq->tx_bounce[index];
564
565 if (fep->quirks & FEC_QUIRK_SWAP_FRAME)
566 swap_buffer(bufaddr, frag_len);
567 }
568
569 addr = dma_map_single(&fep->pdev->dev, bufaddr, frag_len,
570 DMA_TO_DEVICE);
571 if (dma_mapping_error(&fep->pdev->dev, addr)) {
572 if (net_ratelimit())
573 netdev_err(ndev, "Tx DMA memory map failed\n");
574 goto dma_mapping_error;
575 }
576
577 bdp->cbd_bufaddr = cpu_to_fec32(addr);
578 bdp->cbd_datlen = cpu_to_fec16(frag_len);
579 /* Make sure the updates to rest of the descriptor are
580 * performed before transferring ownership.
581 */
582 wmb();
583 bdp->cbd_sc = cpu_to_fec16(status);
584 }
585
586 return bdp;
587dma_mapping_error:
588 bdp = txq->bd.cur;
589 for (i = 0; i < frag; i++) {
590 bdp = fec_enet_get_nextdesc(bdp, &txq->bd);
591 dma_unmap_single(&fep->pdev->dev, fec32_to_cpu(bdp->cbd_bufaddr),
592 fec16_to_cpu(bdp->cbd_datlen), DMA_TO_DEVICE);
593 }
594 return ERR_PTR(-ENOMEM);
595}
596
597static int fec_enet_txq_submit_skb(struct fec_enet_priv_tx_q *txq,
598 struct sk_buff *skb, struct net_device *ndev)
599{
600 struct fec_enet_private *fep = netdev_priv(ndev);
601 int nr_frags = skb_shinfo(skb)->nr_frags;
602 struct bufdesc *bdp, *last_bdp;
603 void *bufaddr;
604 dma_addr_t addr;
605 unsigned short status;
606 unsigned short buflen;
607 unsigned int estatus = 0;
608 unsigned int index;
609 int entries_free;
610
611 entries_free = fec_enet_get_free_txdesc_num(txq);
612 if (entries_free < MAX_SKB_FRAGS + 1) {
613 dev_kfree_skb_any(skb);
614 if (net_ratelimit())
615 netdev_err(ndev, "NOT enough BD for SG!\n");
616 return NETDEV_TX_OK;
617 }
618
619 /* Protocol checksum off-load for TCP and UDP. */
620 if (fec_enet_clear_csum(skb, ndev)) {
621 dev_kfree_skb_any(skb);
622 return NETDEV_TX_OK;
623 }
624
625 /* Fill in a Tx ring entry */
626 bdp = txq->bd.cur;
627 last_bdp = bdp;
628 status = fec16_to_cpu(bdp->cbd_sc);
629 status &= ~BD_ENET_TX_STATS;
630
631 /* Set buffer length and buffer pointer */
632 bufaddr = skb->data;
633 buflen = skb_headlen(skb);
634
635 index = fec_enet_get_bd_index(bdp, &txq->bd);
636 if (((unsigned long) bufaddr) & fep->tx_align ||
637 fep->quirks & FEC_QUIRK_SWAP_FRAME) {
638 memcpy(txq->tx_bounce[index], skb->data, buflen);
639 bufaddr = txq->tx_bounce[index];
640
641 if (fep->quirks & FEC_QUIRK_SWAP_FRAME)
642 swap_buffer(bufaddr, buflen);
643 }
644
645 /* Push the data cache so the CPM does not get stale memory data. */
646 addr = dma_map_single(&fep->pdev->dev, bufaddr, buflen, DMA_TO_DEVICE);
647 if (dma_mapping_error(&fep->pdev->dev, addr)) {
648 dev_kfree_skb_any(skb);
649 if (net_ratelimit())
650 netdev_err(ndev, "Tx DMA memory map failed\n");
651 return NETDEV_TX_OK;
652 }
653
654 if (nr_frags) {
655 last_bdp = fec_enet_txq_submit_frag_skb(txq, skb, ndev);
656 if (IS_ERR(last_bdp)) {
657 dma_unmap_single(&fep->pdev->dev, addr,
658 buflen, DMA_TO_DEVICE);
659 dev_kfree_skb_any(skb);
660 return NETDEV_TX_OK;
661 }
662 } else {
663 status |= (BD_ENET_TX_INTR | BD_ENET_TX_LAST);
664 if (fep->bufdesc_ex) {
665 estatus = BD_ENET_TX_INT;
666 if (unlikely(skb_shinfo(skb)->tx_flags &
667 SKBTX_HW_TSTAMP && fep->hwts_tx_en))
668 estatus |= BD_ENET_TX_TS;
669 }
670 }
671 bdp->cbd_bufaddr = cpu_to_fec32(addr);
672 bdp->cbd_datlen = cpu_to_fec16(buflen);
673
674 if (fep->bufdesc_ex) {
675
676 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
677
678 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP &&
679 fep->hwts_tx_en))
680 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
681
682 if (fep->quirks & FEC_QUIRK_HAS_AVB)
683 estatus |= FEC_TX_BD_FTYPE(txq->bd.qid);
684
685 if (skb->ip_summed == CHECKSUM_PARTIAL)
686 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS;
687
688 ebdp->cbd_bdu = 0;
689 ebdp->cbd_esc = cpu_to_fec32(estatus);
690 }
691
692 index = fec_enet_get_bd_index(last_bdp, &txq->bd);
693 /* Save skb pointer */
694 txq->tx_buf[index].buf_p = skb;
695
696 /* Make sure the updates to rest of the descriptor are performed before
697 * transferring ownership.
698 */
699 wmb();
700
701 /* Send it on its way. Tell FEC it's ready, interrupt when done,
702 * it's the last BD of the frame, and to put the CRC on the end.
703 */
704 status |= (BD_ENET_TX_READY | BD_ENET_TX_TC);
705 bdp->cbd_sc = cpu_to_fec16(status);
706
707 /* If this was the last BD in the ring, start at the beginning again. */
708 bdp = fec_enet_get_nextdesc(last_bdp, &txq->bd);
709
710 skb_tx_timestamp(skb);
711
712 /* Make sure the update to bdp is performed before txq->bd.cur. */
713 wmb();
714 txq->bd.cur = bdp;
715
716 /* Trigger transmission start */
717 writel(0, txq->bd.reg_desc_active);
718
719 return 0;
720}
721
722static int
723fec_enet_txq_put_data_tso(struct fec_enet_priv_tx_q *txq, struct sk_buff *skb,
724 struct net_device *ndev,
725 struct bufdesc *bdp, int index, char *data,
726 int size, bool last_tcp, bool is_last)
727{
728 struct fec_enet_private *fep = netdev_priv(ndev);
729 struct bufdesc_ex *ebdp = container_of(bdp, struct bufdesc_ex, desc);
730 unsigned short status;
731 unsigned int estatus = 0;
732 dma_addr_t addr;
733
734 status = fec16_to_cpu(bdp->cbd_sc);
735 status &= ~BD_ENET_TX_STATS;
736
737 status |= (BD_ENET_TX_TC | BD_ENET_TX_READY);
738
739 if (((unsigned long) data) & fep->tx_align ||
740 fep->quirks & FEC_QUIRK_SWAP_FRAME) {
741 memcpy(txq->tx_bounce[index], data, size);
742 data = txq->tx_bounce[index];
743
744 if (fep->quirks & FEC_QUIRK_SWAP_FRAME)
745 swap_buffer(data, size);
746 }
747
748 addr = dma_map_single(&fep->pdev->dev, data, size, DMA_TO_DEVICE);
749 if (dma_mapping_error(&fep->pdev->dev, addr)) {
750 dev_kfree_skb_any(skb);
751 if (net_ratelimit())
752 netdev_err(ndev, "Tx DMA memory map failed\n");
753 return NETDEV_TX_OK;
754 }
755
756 bdp->cbd_datlen = cpu_to_fec16(size);
757 bdp->cbd_bufaddr = cpu_to_fec32(addr);
758
759 if (fep->bufdesc_ex) {
760 if (fep->quirks & FEC_QUIRK_HAS_AVB)
761 estatus |= FEC_TX_BD_FTYPE(txq->bd.qid);
762 if (skb->ip_summed == CHECKSUM_PARTIAL)
763 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS;
764 ebdp->cbd_bdu = 0;
765 ebdp->cbd_esc = cpu_to_fec32(estatus);
766 }
767
768 /* Handle the last BD specially */
769 if (last_tcp)
770 status |= (BD_ENET_TX_LAST | BD_ENET_TX_TC);
771 if (is_last) {
772 status |= BD_ENET_TX_INTR;
773 if (fep->bufdesc_ex)
774 ebdp->cbd_esc |= cpu_to_fec32(BD_ENET_TX_INT);
775 }
776
777 bdp->cbd_sc = cpu_to_fec16(status);
778
779 return 0;
780}
781
782static int
783fec_enet_txq_put_hdr_tso(struct fec_enet_priv_tx_q *txq,
784 struct sk_buff *skb, struct net_device *ndev,
785 struct bufdesc *bdp, int index)
786{
787 struct fec_enet_private *fep = netdev_priv(ndev);
788 int hdr_len = skb_tcp_all_headers(skb);
789 struct bufdesc_ex *ebdp = container_of(bdp, struct bufdesc_ex, desc);
790 void *bufaddr;
791 unsigned long dmabuf;
792 unsigned short status;
793 unsigned int estatus = 0;
794
795 status = fec16_to_cpu(bdp->cbd_sc);
796 status &= ~BD_ENET_TX_STATS;
797 status |= (BD_ENET_TX_TC | BD_ENET_TX_READY);
798
799 bufaddr = txq->tso_hdrs + index * TSO_HEADER_SIZE;
800 dmabuf = txq->tso_hdrs_dma + index * TSO_HEADER_SIZE;
801 if (((unsigned long)bufaddr) & fep->tx_align ||
802 fep->quirks & FEC_QUIRK_SWAP_FRAME) {
803 memcpy(txq->tx_bounce[index], skb->data, hdr_len);
804 bufaddr = txq->tx_bounce[index];
805
806 if (fep->quirks & FEC_QUIRK_SWAP_FRAME)
807 swap_buffer(bufaddr, hdr_len);
808
809 dmabuf = dma_map_single(&fep->pdev->dev, bufaddr,
810 hdr_len, DMA_TO_DEVICE);
811 if (dma_mapping_error(&fep->pdev->dev, dmabuf)) {
812 dev_kfree_skb_any(skb);
813 if (net_ratelimit())
814 netdev_err(ndev, "Tx DMA memory map failed\n");
815 return NETDEV_TX_OK;
816 }
817 }
818
819 bdp->cbd_bufaddr = cpu_to_fec32(dmabuf);
820 bdp->cbd_datlen = cpu_to_fec16(hdr_len);
821
822 if (fep->bufdesc_ex) {
823 if (fep->quirks & FEC_QUIRK_HAS_AVB)
824 estatus |= FEC_TX_BD_FTYPE(txq->bd.qid);
825 if (skb->ip_summed == CHECKSUM_PARTIAL)
826 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS;
827 ebdp->cbd_bdu = 0;
828 ebdp->cbd_esc = cpu_to_fec32(estatus);
829 }
830
831 bdp->cbd_sc = cpu_to_fec16(status);
832
833 return 0;
834}
835
836static int fec_enet_txq_submit_tso(struct fec_enet_priv_tx_q *txq,
837 struct sk_buff *skb,
838 struct net_device *ndev)
839{
840 struct fec_enet_private *fep = netdev_priv(ndev);
841 int hdr_len, total_len, data_left;
842 struct bufdesc *bdp = txq->bd.cur;
843 struct bufdesc *tmp_bdp;
844 struct bufdesc_ex *ebdp;
845 struct tso_t tso;
846 unsigned int index = 0;
847 int ret;
848
849 if (tso_count_descs(skb) >= fec_enet_get_free_txdesc_num(txq)) {
850 dev_kfree_skb_any(skb);
851 if (net_ratelimit())
852 netdev_err(ndev, "NOT enough BD for TSO!\n");
853 return NETDEV_TX_OK;
854 }
855
856 /* Protocol checksum off-load for TCP and UDP. */
857 if (fec_enet_clear_csum(skb, ndev)) {
858 dev_kfree_skb_any(skb);
859 return NETDEV_TX_OK;
860 }
861
862 /* Initialize the TSO handler, and prepare the first payload */
863 hdr_len = tso_start(skb, &tso);
864
865 total_len = skb->len - hdr_len;
866 while (total_len > 0) {
867 char *hdr;
868
869 index = fec_enet_get_bd_index(bdp, &txq->bd);
870 data_left = min_t(int, skb_shinfo(skb)->gso_size, total_len);
871 total_len -= data_left;
872
873 /* prepare packet headers: MAC + IP + TCP */
874 hdr = txq->tso_hdrs + index * TSO_HEADER_SIZE;
875 tso_build_hdr(skb, hdr, &tso, data_left, total_len == 0);
876 ret = fec_enet_txq_put_hdr_tso(txq, skb, ndev, bdp, index);
877 if (ret)
878 goto err_release;
879
880 while (data_left > 0) {
881 int size;
882
883 size = min_t(int, tso.size, data_left);
884 bdp = fec_enet_get_nextdesc(bdp, &txq->bd);
885 index = fec_enet_get_bd_index(bdp, &txq->bd);
886 ret = fec_enet_txq_put_data_tso(txq, skb, ndev,
887 bdp, index,
888 tso.data, size,
889 size == data_left,
890 total_len == 0);
891 if (ret)
892 goto err_release;
893
894 data_left -= size;
895 tso_build_data(skb, &tso, size);
896 }
897
898 bdp = fec_enet_get_nextdesc(bdp, &txq->bd);
899 }
900
901 /* Save skb pointer */
902 txq->tx_buf[index].buf_p = skb;
903
904 skb_tx_timestamp(skb);
905 txq->bd.cur = bdp;
906
907 /* Trigger transmission start */
908 if (!(fep->quirks & FEC_QUIRK_ERR007885) ||
909 !readl(txq->bd.reg_desc_active) ||
910 !readl(txq->bd.reg_desc_active) ||
911 !readl(txq->bd.reg_desc_active) ||
912 !readl(txq->bd.reg_desc_active))
913 writel(0, txq->bd.reg_desc_active);
914
915 return 0;
916
917err_release:
918 /* Release all used data descriptors for TSO */
919 tmp_bdp = txq->bd.cur;
920
921 while (tmp_bdp != bdp) {
922 /* Unmap data buffers */
923 if (tmp_bdp->cbd_bufaddr &&
924 !IS_TSO_HEADER(txq, fec32_to_cpu(tmp_bdp->cbd_bufaddr)))
925 dma_unmap_single(&fep->pdev->dev,
926 fec32_to_cpu(tmp_bdp->cbd_bufaddr),
927 fec16_to_cpu(tmp_bdp->cbd_datlen),
928 DMA_TO_DEVICE);
929
930 /* Clear standard buffer descriptor fields */
931 tmp_bdp->cbd_sc = 0;
932 tmp_bdp->cbd_datlen = 0;
933 tmp_bdp->cbd_bufaddr = 0;
934
935 /* Handle extended descriptor if enabled */
936 if (fep->bufdesc_ex) {
937 ebdp = (struct bufdesc_ex *)tmp_bdp;
938 ebdp->cbd_esc = 0;
939 }
940
941 tmp_bdp = fec_enet_get_nextdesc(tmp_bdp, &txq->bd);
942 }
943
944 dev_kfree_skb_any(skb);
945
946 return ret;
947}
948
949static netdev_tx_t
950fec_enet_start_xmit(struct sk_buff *skb, struct net_device *ndev)
951{
952 struct fec_enet_private *fep = netdev_priv(ndev);
953 int entries_free;
954 unsigned short queue;
955 struct fec_enet_priv_tx_q *txq;
956 struct netdev_queue *nq;
957 int ret;
958
959 queue = skb_get_queue_mapping(skb);
960 txq = fep->tx_queue[queue];
961 nq = netdev_get_tx_queue(ndev, queue);
962
963 if (skb_is_gso(skb))
964 ret = fec_enet_txq_submit_tso(txq, skb, ndev);
965 else
966 ret = fec_enet_txq_submit_skb(txq, skb, ndev);
967 if (ret)
968 return ret;
969
970 entries_free = fec_enet_get_free_txdesc_num(txq);
971 if (entries_free <= txq->tx_stop_threshold)
972 netif_tx_stop_queue(nq);
973
974 return NETDEV_TX_OK;
975}
976
977/* Init RX & TX buffer descriptors
978 */
979static void fec_enet_bd_init(struct net_device *dev)
980{
981 struct fec_enet_private *fep = netdev_priv(dev);
982 struct fec_enet_priv_tx_q *txq;
983 struct fec_enet_priv_rx_q *rxq;
984 struct bufdesc *bdp;
985 unsigned int i;
986 unsigned int q;
987
988 for (q = 0; q < fep->num_rx_queues; q++) {
989 /* Initialize the receive buffer descriptors. */
990 rxq = fep->rx_queue[q];
991 bdp = rxq->bd.base;
992
993 for (i = 0; i < rxq->bd.ring_size; i++) {
994
995 /* Initialize the BD for every fragment in the page. */
996 if (bdp->cbd_bufaddr)
997 bdp->cbd_sc = cpu_to_fec16(BD_ENET_RX_EMPTY);
998 else
999 bdp->cbd_sc = cpu_to_fec16(0);
1000 bdp = fec_enet_get_nextdesc(bdp, &rxq->bd);
1001 }
1002
1003 /* Set the last buffer to wrap */
1004 bdp = fec_enet_get_prevdesc(bdp, &rxq->bd);
1005 bdp->cbd_sc |= cpu_to_fec16(BD_SC_WRAP);
1006
1007 rxq->bd.cur = rxq->bd.base;
1008 }
1009
1010 for (q = 0; q < fep->num_tx_queues; q++) {
1011 /* ...and the same for transmit */
1012 txq = fep->tx_queue[q];
1013 bdp = txq->bd.base;
1014 txq->bd.cur = bdp;
1015
1016 for (i = 0; i < txq->bd.ring_size; i++) {
1017 /* Initialize the BD for every fragment in the page. */
1018 bdp->cbd_sc = cpu_to_fec16(0);
1019 if (txq->tx_buf[i].type == FEC_TXBUF_T_SKB) {
1020 if (bdp->cbd_bufaddr &&
1021 !IS_TSO_HEADER(txq, fec32_to_cpu(bdp->cbd_bufaddr)))
1022 dma_unmap_single(&fep->pdev->dev,
1023 fec32_to_cpu(bdp->cbd_bufaddr),
1024 fec16_to_cpu(bdp->cbd_datlen),
1025 DMA_TO_DEVICE);
1026 if (txq->tx_buf[i].buf_p)
1027 dev_kfree_skb_any(txq->tx_buf[i].buf_p);
1028 } else if (txq->tx_buf[i].type == FEC_TXBUF_T_XDP_NDO) {
1029 if (bdp->cbd_bufaddr)
1030 dma_unmap_single(&fep->pdev->dev,
1031 fec32_to_cpu(bdp->cbd_bufaddr),
1032 fec16_to_cpu(bdp->cbd_datlen),
1033 DMA_TO_DEVICE);
1034
1035 if (txq->tx_buf[i].buf_p)
1036 xdp_return_frame(txq->tx_buf[i].buf_p);
1037 } else {
1038 struct page *page = txq->tx_buf[i].buf_p;
1039
1040 if (page)
1041 page_pool_put_page(page->pp, page, 0, false);
1042 }
1043
1044 txq->tx_buf[i].buf_p = NULL;
1045 /* restore default tx buffer type: FEC_TXBUF_T_SKB */
1046 txq->tx_buf[i].type = FEC_TXBUF_T_SKB;
1047 bdp->cbd_bufaddr = cpu_to_fec32(0);
1048 bdp = fec_enet_get_nextdesc(bdp, &txq->bd);
1049 }
1050
1051 /* Set the last buffer to wrap */
1052 bdp = fec_enet_get_prevdesc(bdp, &txq->bd);
1053 bdp->cbd_sc |= cpu_to_fec16(BD_SC_WRAP);
1054 txq->dirty_tx = bdp;
1055 }
1056}
1057
1058static void fec_enet_active_rxring(struct net_device *ndev)
1059{
1060 struct fec_enet_private *fep = netdev_priv(ndev);
1061 int i;
1062
1063 for (i = 0; i < fep->num_rx_queues; i++)
1064 writel(0, fep->rx_queue[i]->bd.reg_desc_active);
1065}
1066
1067static void fec_enet_enable_ring(struct net_device *ndev)
1068{
1069 struct fec_enet_private *fep = netdev_priv(ndev);
1070 struct fec_enet_priv_tx_q *txq;
1071 struct fec_enet_priv_rx_q *rxq;
1072 int i;
1073
1074 for (i = 0; i < fep->num_rx_queues; i++) {
1075 rxq = fep->rx_queue[i];
1076 writel(rxq->bd.dma, fep->hwp + FEC_R_DES_START(i));
1077 writel(PKT_MAXBUF_SIZE, fep->hwp + FEC_R_BUFF_SIZE(i));
1078
1079 /* enable DMA1/2 */
1080 if (i)
1081 writel(RCMR_MATCHEN | RCMR_CMP(i),
1082 fep->hwp + FEC_RCMR(i));
1083 }
1084
1085 for (i = 0; i < fep->num_tx_queues; i++) {
1086 txq = fep->tx_queue[i];
1087 writel(txq->bd.dma, fep->hwp + FEC_X_DES_START(i));
1088
1089 /* enable DMA1/2 */
1090 if (i)
1091 writel(DMA_CLASS_EN | IDLE_SLOPE(i),
1092 fep->hwp + FEC_DMA_CFG(i));
1093 }
1094}
1095
1096/*
1097 * This function is called to start or restart the FEC during a link
1098 * change, transmit timeout, or to reconfigure the FEC. The network
1099 * packet processing for this device must be stopped before this call.
1100 */
1101static void
1102fec_restart(struct net_device *ndev)
1103{
1104 struct fec_enet_private *fep = netdev_priv(ndev);
1105 u32 temp_mac[2];
1106 u32 rcntl = OPT_FRAME_SIZE | 0x04;
1107 u32 ecntl = FEC_ECR_ETHEREN;
1108
1109 if (fep->bufdesc_ex)
1110 fec_ptp_save_state(fep);
1111
1112 /* Whack a reset. We should wait for this.
1113 * For i.MX6SX SOC, enet use AXI bus, we use disable MAC
1114 * instead of reset MAC itself.
1115 */
1116 if (fep->quirks & FEC_QUIRK_HAS_MULTI_QUEUES ||
1117 ((fep->quirks & FEC_QUIRK_NO_HARD_RESET) && fep->link)) {
1118 writel(0, fep->hwp + FEC_ECNTRL);
1119 } else {
1120 writel(1, fep->hwp + FEC_ECNTRL);
1121 udelay(10);
1122 }
1123
1124 /*
1125 * enet-mac reset will reset mac address registers too,
1126 * so need to reconfigure it.
1127 */
1128 memcpy(&temp_mac, ndev->dev_addr, ETH_ALEN);
1129 writel((__force u32)cpu_to_be32(temp_mac[0]),
1130 fep->hwp + FEC_ADDR_LOW);
1131 writel((__force u32)cpu_to_be32(temp_mac[1]),
1132 fep->hwp + FEC_ADDR_HIGH);
1133
1134 /* Clear any outstanding interrupt, except MDIO. */
1135 writel((0xffffffff & ~FEC_ENET_MII), fep->hwp + FEC_IEVENT);
1136
1137 fec_enet_bd_init(ndev);
1138
1139 fec_enet_enable_ring(ndev);
1140
1141 /* Enable MII mode */
1142 if (fep->full_duplex == DUPLEX_FULL) {
1143 /* FD enable */
1144 writel(0x04, fep->hwp + FEC_X_CNTRL);
1145 } else {
1146 /* No Rcv on Xmit */
1147 rcntl |= 0x02;
1148 writel(0x0, fep->hwp + FEC_X_CNTRL);
1149 }
1150
1151 /* Set MII speed */
1152 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
1153
1154#if !defined(CONFIG_M5272)
1155 if (fep->quirks & FEC_QUIRK_HAS_RACC) {
1156 u32 val = readl(fep->hwp + FEC_RACC);
1157
1158 /* align IP header */
1159 val |= FEC_RACC_SHIFT16;
1160 if (fep->csum_flags & FLAG_RX_CSUM_ENABLED)
1161 /* set RX checksum */
1162 val |= FEC_RACC_OPTIONS;
1163 else
1164 val &= ~FEC_RACC_OPTIONS;
1165 writel(val, fep->hwp + FEC_RACC);
1166 writel(PKT_MAXBUF_SIZE, fep->hwp + FEC_FTRL);
1167 }
1168#endif
1169
1170 /*
1171 * The phy interface and speed need to get configured
1172 * differently on enet-mac.
1173 */
1174 if (fep->quirks & FEC_QUIRK_ENET_MAC) {
1175 /* Enable flow control and length check */
1176 rcntl |= 0x40000000 | 0x00000020;
1177
1178 /* RGMII, RMII or MII */
1179 if (fep->phy_interface == PHY_INTERFACE_MODE_RGMII ||
1180 fep->phy_interface == PHY_INTERFACE_MODE_RGMII_ID ||
1181 fep->phy_interface == PHY_INTERFACE_MODE_RGMII_RXID ||
1182 fep->phy_interface == PHY_INTERFACE_MODE_RGMII_TXID)
1183 rcntl |= (1 << 6);
1184 else if (fep->phy_interface == PHY_INTERFACE_MODE_RMII)
1185 rcntl |= FEC_RCR_RMII;
1186 else
1187 rcntl &= ~FEC_RCR_RMII;
1188
1189 /* 1G, 100M or 10M */
1190 if (ndev->phydev) {
1191 if (ndev->phydev->speed == SPEED_1000)
1192 ecntl |= (1 << 5);
1193 else if (ndev->phydev->speed == SPEED_100)
1194 rcntl &= ~FEC_RCR_10BASET;
1195 else
1196 rcntl |= FEC_RCR_10BASET;
1197 }
1198 } else {
1199#ifdef FEC_MIIGSK_ENR
1200 if (fep->quirks & FEC_QUIRK_USE_GASKET) {
1201 u32 cfgr;
1202 /* disable the gasket and wait */
1203 writel(0, fep->hwp + FEC_MIIGSK_ENR);
1204 while (readl(fep->hwp + FEC_MIIGSK_ENR) & 4)
1205 udelay(1);
1206
1207 /*
1208 * configure the gasket:
1209 * RMII, 50 MHz, no loopback, no echo
1210 * MII, 25 MHz, no loopback, no echo
1211 */
1212 cfgr = (fep->phy_interface == PHY_INTERFACE_MODE_RMII)
1213 ? BM_MIIGSK_CFGR_RMII : BM_MIIGSK_CFGR_MII;
1214 if (ndev->phydev && ndev->phydev->speed == SPEED_10)
1215 cfgr |= BM_MIIGSK_CFGR_FRCONT_10M;
1216 writel(cfgr, fep->hwp + FEC_MIIGSK_CFGR);
1217
1218 /* re-enable the gasket */
1219 writel(2, fep->hwp + FEC_MIIGSK_ENR);
1220 }
1221#endif
1222 }
1223
1224#if !defined(CONFIG_M5272)
1225 /* enable pause frame*/
1226 if ((fep->pause_flag & FEC_PAUSE_FLAG_ENABLE) ||
1227 ((fep->pause_flag & FEC_PAUSE_FLAG_AUTONEG) &&
1228 ndev->phydev && ndev->phydev->pause)) {
1229 rcntl |= FEC_RCR_FLOWCTL;
1230
1231 /* set FIFO threshold parameter to reduce overrun */
1232 writel(FEC_ENET_RSEM_V, fep->hwp + FEC_R_FIFO_RSEM);
1233 writel(FEC_ENET_RSFL_V, fep->hwp + FEC_R_FIFO_RSFL);
1234 writel(FEC_ENET_RAEM_V, fep->hwp + FEC_R_FIFO_RAEM);
1235 writel(FEC_ENET_RAFL_V, fep->hwp + FEC_R_FIFO_RAFL);
1236
1237 /* OPD */
1238 writel(FEC_ENET_OPD_V, fep->hwp + FEC_OPD);
1239 } else {
1240 rcntl &= ~FEC_RCR_FLOWCTL;
1241 }
1242#endif /* !defined(CONFIG_M5272) */
1243
1244 writel(rcntl, fep->hwp + FEC_R_CNTRL);
1245
1246 /* Setup multicast filter. */
1247 set_multicast_list(ndev);
1248#ifndef CONFIG_M5272
1249 writel(0, fep->hwp + FEC_HASH_TABLE_HIGH);
1250 writel(0, fep->hwp + FEC_HASH_TABLE_LOW);
1251#endif
1252
1253 if (fep->quirks & FEC_QUIRK_ENET_MAC) {
1254 /* enable ENET endian swap */
1255 ecntl |= FEC_ECR_BYTESWP;
1256 /* enable ENET store and forward mode */
1257 writel(FEC_TXWMRK_STRFWD, fep->hwp + FEC_X_WMRK);
1258 }
1259
1260 if (fep->bufdesc_ex)
1261 ecntl |= FEC_ECR_EN1588;
1262
1263 if (fep->quirks & FEC_QUIRK_DELAYED_CLKS_SUPPORT &&
1264 fep->rgmii_txc_dly)
1265 ecntl |= FEC_ENET_TXC_DLY;
1266 if (fep->quirks & FEC_QUIRK_DELAYED_CLKS_SUPPORT &&
1267 fep->rgmii_rxc_dly)
1268 ecntl |= FEC_ENET_RXC_DLY;
1269
1270#ifndef CONFIG_M5272
1271 /* Enable the MIB statistic event counters */
1272 writel(0 << 31, fep->hwp + FEC_MIB_CTRLSTAT);
1273#endif
1274
1275 /* And last, enable the transmit and receive processing */
1276 writel(ecntl, fep->hwp + FEC_ECNTRL);
1277 fec_enet_active_rxring(ndev);
1278
1279 if (fep->bufdesc_ex) {
1280 fec_ptp_start_cyclecounter(ndev);
1281 fec_ptp_restore_state(fep);
1282 }
1283
1284 /* Enable interrupts we wish to service */
1285 if (fep->link)
1286 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK);
1287 else
1288 writel(0, fep->hwp + FEC_IMASK);
1289
1290 /* Init the interrupt coalescing */
1291 if (fep->quirks & FEC_QUIRK_HAS_COALESCE)
1292 fec_enet_itr_coal_set(ndev);
1293}
1294
1295static int fec_enet_ipc_handle_init(struct fec_enet_private *fep)
1296{
1297 if (!(of_machine_is_compatible("fsl,imx8qm") ||
1298 of_machine_is_compatible("fsl,imx8qxp") ||
1299 of_machine_is_compatible("fsl,imx8dxl")))
1300 return 0;
1301
1302 return imx_scu_get_handle(&fep->ipc_handle);
1303}
1304
1305static void fec_enet_ipg_stop_set(struct fec_enet_private *fep, bool enabled)
1306{
1307 struct device_node *np = fep->pdev->dev.of_node;
1308 u32 rsrc_id, val;
1309 int idx;
1310
1311 if (!np || !fep->ipc_handle)
1312 return;
1313
1314 idx = of_alias_get_id(np, "ethernet");
1315 if (idx < 0)
1316 idx = 0;
1317 rsrc_id = idx ? IMX_SC_R_ENET_1 : IMX_SC_R_ENET_0;
1318
1319 val = enabled ? 1 : 0;
1320 imx_sc_misc_set_control(fep->ipc_handle, rsrc_id, IMX_SC_C_IPG_STOP, val);
1321}
1322
1323static void fec_enet_stop_mode(struct fec_enet_private *fep, bool enabled)
1324{
1325 struct fec_platform_data *pdata = fep->pdev->dev.platform_data;
1326 struct fec_stop_mode_gpr *stop_gpr = &fep->stop_gpr;
1327
1328 if (stop_gpr->gpr) {
1329 if (enabled)
1330 regmap_update_bits(stop_gpr->gpr, stop_gpr->reg,
1331 BIT(stop_gpr->bit),
1332 BIT(stop_gpr->bit));
1333 else
1334 regmap_update_bits(stop_gpr->gpr, stop_gpr->reg,
1335 BIT(stop_gpr->bit), 0);
1336 } else if (pdata && pdata->sleep_mode_enable) {
1337 pdata->sleep_mode_enable(enabled);
1338 } else {
1339 fec_enet_ipg_stop_set(fep, enabled);
1340 }
1341}
1342
1343static void fec_irqs_disable(struct net_device *ndev)
1344{
1345 struct fec_enet_private *fep = netdev_priv(ndev);
1346
1347 writel(0, fep->hwp + FEC_IMASK);
1348}
1349
1350static void fec_irqs_disable_except_wakeup(struct net_device *ndev)
1351{
1352 struct fec_enet_private *fep = netdev_priv(ndev);
1353
1354 writel(0, fep->hwp + FEC_IMASK);
1355 writel(FEC_ENET_WAKEUP, fep->hwp + FEC_IMASK);
1356}
1357
1358static void
1359fec_stop(struct net_device *ndev)
1360{
1361 struct fec_enet_private *fep = netdev_priv(ndev);
1362 u32 rmii_mode = readl(fep->hwp + FEC_R_CNTRL) & FEC_RCR_RMII;
1363 u32 val;
1364
1365 /* We cannot expect a graceful transmit stop without link !!! */
1366 if (fep->link) {
1367 writel(1, fep->hwp + FEC_X_CNTRL); /* Graceful transmit stop */
1368 udelay(10);
1369 if (!(readl(fep->hwp + FEC_IEVENT) & FEC_ENET_GRA))
1370 netdev_err(ndev, "Graceful transmit stop did not complete!\n");
1371 }
1372
1373 if (fep->bufdesc_ex)
1374 fec_ptp_save_state(fep);
1375
1376 /* Whack a reset. We should wait for this.
1377 * For i.MX6SX SOC, enet use AXI bus, we use disable MAC
1378 * instead of reset MAC itself.
1379 */
1380 if (!(fep->wol_flag & FEC_WOL_FLAG_SLEEP_ON)) {
1381 if (fep->quirks & FEC_QUIRK_HAS_MULTI_QUEUES) {
1382 writel(0, fep->hwp + FEC_ECNTRL);
1383 } else {
1384 writel(FEC_ECR_RESET, fep->hwp + FEC_ECNTRL);
1385 udelay(10);
1386 }
1387 } else {
1388 val = readl(fep->hwp + FEC_ECNTRL);
1389 val |= (FEC_ECR_MAGICEN | FEC_ECR_SLEEP);
1390 writel(val, fep->hwp + FEC_ECNTRL);
1391 }
1392 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
1393 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK);
1394
1395 /* We have to keep ENET enabled to have MII interrupt stay working */
1396 if (fep->quirks & FEC_QUIRK_ENET_MAC &&
1397 !(fep->wol_flag & FEC_WOL_FLAG_SLEEP_ON)) {
1398 writel(FEC_ECR_ETHEREN, fep->hwp + FEC_ECNTRL);
1399 writel(rmii_mode, fep->hwp + FEC_R_CNTRL);
1400 }
1401
1402 if (fep->bufdesc_ex) {
1403 val = readl(fep->hwp + FEC_ECNTRL);
1404 val |= FEC_ECR_EN1588;
1405 writel(val, fep->hwp + FEC_ECNTRL);
1406
1407 fec_ptp_start_cyclecounter(ndev);
1408 fec_ptp_restore_state(fep);
1409 }
1410}
1411
1412static void
1413fec_timeout(struct net_device *ndev, unsigned int txqueue)
1414{
1415 struct fec_enet_private *fep = netdev_priv(ndev);
1416
1417 fec_dump(ndev);
1418
1419 ndev->stats.tx_errors++;
1420
1421 schedule_work(&fep->tx_timeout_work);
1422}
1423
1424static void fec_enet_timeout_work(struct work_struct *work)
1425{
1426 struct fec_enet_private *fep =
1427 container_of(work, struct fec_enet_private, tx_timeout_work);
1428 struct net_device *ndev = fep->netdev;
1429
1430 rtnl_lock();
1431 if (netif_device_present(ndev) || netif_running(ndev)) {
1432 napi_disable(&fep->napi);
1433 netif_tx_lock_bh(ndev);
1434 fec_restart(ndev);
1435 netif_tx_wake_all_queues(ndev);
1436 netif_tx_unlock_bh(ndev);
1437 napi_enable(&fep->napi);
1438 }
1439 rtnl_unlock();
1440}
1441
1442static void
1443fec_enet_hwtstamp(struct fec_enet_private *fep, unsigned ts,
1444 struct skb_shared_hwtstamps *hwtstamps)
1445{
1446 unsigned long flags;
1447 u64 ns;
1448
1449 spin_lock_irqsave(&fep->tmreg_lock, flags);
1450 ns = timecounter_cyc2time(&fep->tc, ts);
1451 spin_unlock_irqrestore(&fep->tmreg_lock, flags);
1452
1453 memset(hwtstamps, 0, sizeof(*hwtstamps));
1454 hwtstamps->hwtstamp = ns_to_ktime(ns);
1455}
1456
1457static void
1458fec_enet_tx_queue(struct net_device *ndev, u16 queue_id, int budget)
1459{
1460 struct fec_enet_private *fep;
1461 struct xdp_frame *xdpf;
1462 struct bufdesc *bdp;
1463 unsigned short status;
1464 struct sk_buff *skb;
1465 struct fec_enet_priv_tx_q *txq;
1466 struct netdev_queue *nq;
1467 int index = 0;
1468 int entries_free;
1469 struct page *page;
1470 int frame_len;
1471
1472 fep = netdev_priv(ndev);
1473
1474 txq = fep->tx_queue[queue_id];
1475 /* get next bdp of dirty_tx */
1476 nq = netdev_get_tx_queue(ndev, queue_id);
1477 bdp = txq->dirty_tx;
1478
1479 /* get next bdp of dirty_tx */
1480 bdp = fec_enet_get_nextdesc(bdp, &txq->bd);
1481
1482 while (bdp != READ_ONCE(txq->bd.cur)) {
1483 /* Order the load of bd.cur and cbd_sc */
1484 rmb();
1485 status = fec16_to_cpu(READ_ONCE(bdp->cbd_sc));
1486 if (status & BD_ENET_TX_READY)
1487 break;
1488
1489 index = fec_enet_get_bd_index(bdp, &txq->bd);
1490
1491 if (txq->tx_buf[index].type == FEC_TXBUF_T_SKB) {
1492 skb = txq->tx_buf[index].buf_p;
1493 if (bdp->cbd_bufaddr &&
1494 !IS_TSO_HEADER(txq, fec32_to_cpu(bdp->cbd_bufaddr)))
1495 dma_unmap_single(&fep->pdev->dev,
1496 fec32_to_cpu(bdp->cbd_bufaddr),
1497 fec16_to_cpu(bdp->cbd_datlen),
1498 DMA_TO_DEVICE);
1499 bdp->cbd_bufaddr = cpu_to_fec32(0);
1500 if (!skb)
1501 goto tx_buf_done;
1502 } else {
1503 /* Tx processing cannot call any XDP (or page pool) APIs if
1504 * the "budget" is 0. Because NAPI is called with budget of
1505 * 0 (such as netpoll) indicates we may be in an IRQ context,
1506 * however, we can't use the page pool from IRQ context.
1507 */
1508 if (unlikely(!budget))
1509 break;
1510
1511 if (txq->tx_buf[index].type == FEC_TXBUF_T_XDP_NDO) {
1512 xdpf = txq->tx_buf[index].buf_p;
1513 if (bdp->cbd_bufaddr)
1514 dma_unmap_single(&fep->pdev->dev,
1515 fec32_to_cpu(bdp->cbd_bufaddr),
1516 fec16_to_cpu(bdp->cbd_datlen),
1517 DMA_TO_DEVICE);
1518 } else {
1519 page = txq->tx_buf[index].buf_p;
1520 }
1521
1522 bdp->cbd_bufaddr = cpu_to_fec32(0);
1523 if (unlikely(!txq->tx_buf[index].buf_p)) {
1524 txq->tx_buf[index].type = FEC_TXBUF_T_SKB;
1525 goto tx_buf_done;
1526 }
1527
1528 frame_len = fec16_to_cpu(bdp->cbd_datlen);
1529 }
1530
1531 /* Check for errors. */
1532 if (status & (BD_ENET_TX_HB | BD_ENET_TX_LC |
1533 BD_ENET_TX_RL | BD_ENET_TX_UN |
1534 BD_ENET_TX_CSL)) {
1535 ndev->stats.tx_errors++;
1536 if (status & BD_ENET_TX_HB) /* No heartbeat */
1537 ndev->stats.tx_heartbeat_errors++;
1538 if (status & BD_ENET_TX_LC) /* Late collision */
1539 ndev->stats.tx_window_errors++;
1540 if (status & BD_ENET_TX_RL) /* Retrans limit */
1541 ndev->stats.tx_aborted_errors++;
1542 if (status & BD_ENET_TX_UN) /* Underrun */
1543 ndev->stats.tx_fifo_errors++;
1544 if (status & BD_ENET_TX_CSL) /* Carrier lost */
1545 ndev->stats.tx_carrier_errors++;
1546 } else {
1547 ndev->stats.tx_packets++;
1548
1549 if (txq->tx_buf[index].type == FEC_TXBUF_T_SKB)
1550 ndev->stats.tx_bytes += skb->len;
1551 else
1552 ndev->stats.tx_bytes += frame_len;
1553 }
1554
1555 /* Deferred means some collisions occurred during transmit,
1556 * but we eventually sent the packet OK.
1557 */
1558 if (status & BD_ENET_TX_DEF)
1559 ndev->stats.collisions++;
1560
1561 if (txq->tx_buf[index].type == FEC_TXBUF_T_SKB) {
1562 /* NOTE: SKBTX_IN_PROGRESS being set does not imply it's we who
1563 * are to time stamp the packet, so we still need to check time
1564 * stamping enabled flag.
1565 */
1566 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS &&
1567 fep->hwts_tx_en) && fep->bufdesc_ex) {
1568 struct skb_shared_hwtstamps shhwtstamps;
1569 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
1570
1571 fec_enet_hwtstamp(fep, fec32_to_cpu(ebdp->ts), &shhwtstamps);
1572 skb_tstamp_tx(skb, &shhwtstamps);
1573 }
1574
1575 /* Free the sk buffer associated with this last transmit */
1576 napi_consume_skb(skb, budget);
1577 } else if (txq->tx_buf[index].type == FEC_TXBUF_T_XDP_NDO) {
1578 xdp_return_frame_rx_napi(xdpf);
1579 } else { /* recycle pages of XDP_TX frames */
1580 /* The dma_sync_size = 0 as XDP_TX has already synced DMA for_device */
1581 page_pool_put_page(page->pp, page, 0, true);
1582 }
1583
1584 txq->tx_buf[index].buf_p = NULL;
1585 /* restore default tx buffer type: FEC_TXBUF_T_SKB */
1586 txq->tx_buf[index].type = FEC_TXBUF_T_SKB;
1587
1588tx_buf_done:
1589 /* Make sure the update to bdp and tx_buf are performed
1590 * before dirty_tx
1591 */
1592 wmb();
1593 txq->dirty_tx = bdp;
1594
1595 /* Update pointer to next buffer descriptor to be transmitted */
1596 bdp = fec_enet_get_nextdesc(bdp, &txq->bd);
1597
1598 /* Since we have freed up a buffer, the ring is no longer full
1599 */
1600 if (netif_tx_queue_stopped(nq)) {
1601 entries_free = fec_enet_get_free_txdesc_num(txq);
1602 if (entries_free >= txq->tx_wake_threshold)
1603 netif_tx_wake_queue(nq);
1604 }
1605 }
1606
1607 /* ERR006358: Keep the transmitter going */
1608 if (bdp != txq->bd.cur &&
1609 readl(txq->bd.reg_desc_active) == 0)
1610 writel(0, txq->bd.reg_desc_active);
1611}
1612
1613static void fec_enet_tx(struct net_device *ndev, int budget)
1614{
1615 struct fec_enet_private *fep = netdev_priv(ndev);
1616 int i;
1617
1618 /* Make sure that AVB queues are processed first. */
1619 for (i = fep->num_tx_queues - 1; i >= 0; i--)
1620 fec_enet_tx_queue(ndev, i, budget);
1621}
1622
1623static int fec_enet_update_cbd(struct fec_enet_priv_rx_q *rxq,
1624 struct bufdesc *bdp, int index)
1625{
1626 struct page *new_page;
1627 dma_addr_t phys_addr;
1628
1629 new_page = page_pool_dev_alloc_pages(rxq->page_pool);
1630 if (unlikely(!new_page))
1631 return -ENOMEM;
1632
1633 rxq->rx_skb_info[index].page = new_page;
1634 rxq->rx_skb_info[index].offset = FEC_ENET_XDP_HEADROOM;
1635 phys_addr = page_pool_get_dma_addr(new_page) + FEC_ENET_XDP_HEADROOM;
1636 bdp->cbd_bufaddr = cpu_to_fec32(phys_addr);
1637
1638 return 0;
1639}
1640
1641static u32
1642fec_enet_run_xdp(struct fec_enet_private *fep, struct bpf_prog *prog,
1643 struct xdp_buff *xdp, struct fec_enet_priv_rx_q *rxq, int cpu)
1644{
1645 unsigned int sync, len = xdp->data_end - xdp->data;
1646 u32 ret = FEC_ENET_XDP_PASS;
1647 struct page *page;
1648 int err;
1649 u32 act;
1650
1651 act = bpf_prog_run_xdp(prog, xdp);
1652
1653 /* Due xdp_adjust_tail and xdp_adjust_head: DMA sync for_device cover
1654 * max len CPU touch
1655 */
1656 sync = xdp->data_end - xdp->data;
1657 sync = max(sync, len);
1658
1659 switch (act) {
1660 case XDP_PASS:
1661 rxq->stats[RX_XDP_PASS]++;
1662 ret = FEC_ENET_XDP_PASS;
1663 break;
1664
1665 case XDP_REDIRECT:
1666 rxq->stats[RX_XDP_REDIRECT]++;
1667 err = xdp_do_redirect(fep->netdev, xdp, prog);
1668 if (unlikely(err))
1669 goto xdp_err;
1670
1671 ret = FEC_ENET_XDP_REDIR;
1672 break;
1673
1674 case XDP_TX:
1675 rxq->stats[RX_XDP_TX]++;
1676 err = fec_enet_xdp_tx_xmit(fep, cpu, xdp, sync);
1677 if (unlikely(err)) {
1678 rxq->stats[RX_XDP_TX_ERRORS]++;
1679 goto xdp_err;
1680 }
1681
1682 ret = FEC_ENET_XDP_TX;
1683 break;
1684
1685 default:
1686 bpf_warn_invalid_xdp_action(fep->netdev, prog, act);
1687 fallthrough;
1688
1689 case XDP_ABORTED:
1690 fallthrough; /* handle aborts by dropping packet */
1691
1692 case XDP_DROP:
1693 rxq->stats[RX_XDP_DROP]++;
1694xdp_err:
1695 ret = FEC_ENET_XDP_CONSUMED;
1696 page = virt_to_head_page(xdp->data);
1697 page_pool_put_page(rxq->page_pool, page, sync, true);
1698 if (act != XDP_DROP)
1699 trace_xdp_exception(fep->netdev, prog, act);
1700 break;
1701 }
1702
1703 return ret;
1704}
1705
1706/* During a receive, the bd_rx.cur points to the current incoming buffer.
1707 * When we update through the ring, if the next incoming buffer has
1708 * not been given to the system, we just set the empty indicator,
1709 * effectively tossing the packet.
1710 */
1711static int
1712fec_enet_rx_queue(struct net_device *ndev, int budget, u16 queue_id)
1713{
1714 struct fec_enet_private *fep = netdev_priv(ndev);
1715 struct fec_enet_priv_rx_q *rxq;
1716 struct bufdesc *bdp;
1717 unsigned short status;
1718 struct sk_buff *skb;
1719 ushort pkt_len;
1720 __u8 *data;
1721 int pkt_received = 0;
1722 struct bufdesc_ex *ebdp = NULL;
1723 bool vlan_packet_rcvd = false;
1724 u16 vlan_tag;
1725 int index = 0;
1726 bool need_swap = fep->quirks & FEC_QUIRK_SWAP_FRAME;
1727 struct bpf_prog *xdp_prog = READ_ONCE(fep->xdp_prog);
1728 u32 ret, xdp_result = FEC_ENET_XDP_PASS;
1729 u32 data_start = FEC_ENET_XDP_HEADROOM;
1730 int cpu = smp_processor_id();
1731 struct xdp_buff xdp;
1732 struct page *page;
1733 __fec32 cbd_bufaddr;
1734 u32 sub_len = 4;
1735
1736#if !defined(CONFIG_M5272)
1737 /*If it has the FEC_QUIRK_HAS_RACC quirk property, the bit of
1738 * FEC_RACC_SHIFT16 is set by default in the probe function.
1739 */
1740 if (fep->quirks & FEC_QUIRK_HAS_RACC) {
1741 data_start += 2;
1742 sub_len += 2;
1743 }
1744#endif
1745
1746#if defined(CONFIG_COLDFIRE) && !defined(CONFIG_COLDFIRE_COHERENT_DMA)
1747 /*
1748 * Hacky flush of all caches instead of using the DMA API for the TSO
1749 * headers.
1750 */
1751 flush_cache_all();
1752#endif
1753 rxq = fep->rx_queue[queue_id];
1754
1755 /* First, grab all of the stats for the incoming packet.
1756 * These get messed up if we get called due to a busy condition.
1757 */
1758 bdp = rxq->bd.cur;
1759 xdp_init_buff(&xdp, PAGE_SIZE, &rxq->xdp_rxq);
1760
1761 while (!((status = fec16_to_cpu(bdp->cbd_sc)) & BD_ENET_RX_EMPTY)) {
1762
1763 if (pkt_received >= budget)
1764 break;
1765 pkt_received++;
1766
1767 writel(FEC_ENET_RXF_GET(queue_id), fep->hwp + FEC_IEVENT);
1768
1769 /* Check for errors. */
1770 status ^= BD_ENET_RX_LAST;
1771 if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH | BD_ENET_RX_NO |
1772 BD_ENET_RX_CR | BD_ENET_RX_OV | BD_ENET_RX_LAST |
1773 BD_ENET_RX_CL)) {
1774 ndev->stats.rx_errors++;
1775 if (status & BD_ENET_RX_OV) {
1776 /* FIFO overrun */
1777 ndev->stats.rx_fifo_errors++;
1778 goto rx_processing_done;
1779 }
1780 if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH
1781 | BD_ENET_RX_LAST)) {
1782 /* Frame too long or too short. */
1783 ndev->stats.rx_length_errors++;
1784 if (status & BD_ENET_RX_LAST)
1785 netdev_err(ndev, "rcv is not +last\n");
1786 }
1787 if (status & BD_ENET_RX_CR) /* CRC Error */
1788 ndev->stats.rx_crc_errors++;
1789 /* Report late collisions as a frame error. */
1790 if (status & (BD_ENET_RX_NO | BD_ENET_RX_CL))
1791 ndev->stats.rx_frame_errors++;
1792 goto rx_processing_done;
1793 }
1794
1795 /* Process the incoming frame. */
1796 ndev->stats.rx_packets++;
1797 pkt_len = fec16_to_cpu(bdp->cbd_datlen);
1798 ndev->stats.rx_bytes += pkt_len;
1799
1800 index = fec_enet_get_bd_index(bdp, &rxq->bd);
1801 page = rxq->rx_skb_info[index].page;
1802 cbd_bufaddr = bdp->cbd_bufaddr;
1803 if (fec_enet_update_cbd(rxq, bdp, index)) {
1804 ndev->stats.rx_dropped++;
1805 goto rx_processing_done;
1806 }
1807
1808 dma_sync_single_for_cpu(&fep->pdev->dev,
1809 fec32_to_cpu(cbd_bufaddr),
1810 pkt_len,
1811 DMA_FROM_DEVICE);
1812 prefetch(page_address(page));
1813
1814 if (xdp_prog) {
1815 xdp_buff_clear_frags_flag(&xdp);
1816 /* subtract 16bit shift and FCS */
1817 xdp_prepare_buff(&xdp, page_address(page),
1818 data_start, pkt_len - sub_len, false);
1819 ret = fec_enet_run_xdp(fep, xdp_prog, &xdp, rxq, cpu);
1820 xdp_result |= ret;
1821 if (ret != FEC_ENET_XDP_PASS)
1822 goto rx_processing_done;
1823 }
1824
1825 /* The packet length includes FCS, but we don't want to
1826 * include that when passing upstream as it messes up
1827 * bridging applications.
1828 */
1829 skb = build_skb(page_address(page), PAGE_SIZE);
1830 if (unlikely(!skb)) {
1831 page_pool_recycle_direct(rxq->page_pool, page);
1832 ndev->stats.rx_dropped++;
1833
1834 netdev_err_once(ndev, "build_skb failed!\n");
1835 goto rx_processing_done;
1836 }
1837
1838 skb_reserve(skb, data_start);
1839 skb_put(skb, pkt_len - sub_len);
1840 skb_mark_for_recycle(skb);
1841
1842 if (unlikely(need_swap)) {
1843 data = page_address(page) + FEC_ENET_XDP_HEADROOM;
1844 swap_buffer(data, pkt_len);
1845 }
1846 data = skb->data;
1847
1848 /* Extract the enhanced buffer descriptor */
1849 ebdp = NULL;
1850 if (fep->bufdesc_ex)
1851 ebdp = (struct bufdesc_ex *)bdp;
1852
1853 /* If this is a VLAN packet remove the VLAN Tag */
1854 vlan_packet_rcvd = false;
1855 if ((ndev->features & NETIF_F_HW_VLAN_CTAG_RX) &&
1856 fep->bufdesc_ex &&
1857 (ebdp->cbd_esc & cpu_to_fec32(BD_ENET_RX_VLAN))) {
1858 /* Push and remove the vlan tag */
1859 struct vlan_hdr *vlan_header =
1860 (struct vlan_hdr *) (data + ETH_HLEN);
1861 vlan_tag = ntohs(vlan_header->h_vlan_TCI);
1862
1863 vlan_packet_rcvd = true;
1864
1865 memmove(skb->data + VLAN_HLEN, data, ETH_ALEN * 2);
1866 skb_pull(skb, VLAN_HLEN);
1867 }
1868
1869 skb->protocol = eth_type_trans(skb, ndev);
1870
1871 /* Get receive timestamp from the skb */
1872 if (fep->hwts_rx_en && fep->bufdesc_ex)
1873 fec_enet_hwtstamp(fep, fec32_to_cpu(ebdp->ts),
1874 skb_hwtstamps(skb));
1875
1876 if (fep->bufdesc_ex &&
1877 (fep->csum_flags & FLAG_RX_CSUM_ENABLED)) {
1878 if (!(ebdp->cbd_esc & cpu_to_fec32(FLAG_RX_CSUM_ERROR))) {
1879 /* don't check it */
1880 skb->ip_summed = CHECKSUM_UNNECESSARY;
1881 } else {
1882 skb_checksum_none_assert(skb);
1883 }
1884 }
1885
1886 /* Handle received VLAN packets */
1887 if (vlan_packet_rcvd)
1888 __vlan_hwaccel_put_tag(skb,
1889 htons(ETH_P_8021Q),
1890 vlan_tag);
1891
1892 skb_record_rx_queue(skb, queue_id);
1893 napi_gro_receive(&fep->napi, skb);
1894
1895rx_processing_done:
1896 /* Clear the status flags for this buffer */
1897 status &= ~BD_ENET_RX_STATS;
1898
1899 /* Mark the buffer empty */
1900 status |= BD_ENET_RX_EMPTY;
1901
1902 if (fep->bufdesc_ex) {
1903 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
1904
1905 ebdp->cbd_esc = cpu_to_fec32(BD_ENET_RX_INT);
1906 ebdp->cbd_prot = 0;
1907 ebdp->cbd_bdu = 0;
1908 }
1909 /* Make sure the updates to rest of the descriptor are
1910 * performed before transferring ownership.
1911 */
1912 wmb();
1913 bdp->cbd_sc = cpu_to_fec16(status);
1914
1915 /* Update BD pointer to next entry */
1916 bdp = fec_enet_get_nextdesc(bdp, &rxq->bd);
1917
1918 /* Doing this here will keep the FEC running while we process
1919 * incoming frames. On a heavily loaded network, we should be
1920 * able to keep up at the expense of system resources.
1921 */
1922 writel(0, rxq->bd.reg_desc_active);
1923 }
1924 rxq->bd.cur = bdp;
1925
1926 if (xdp_result & FEC_ENET_XDP_REDIR)
1927 xdp_do_flush();
1928
1929 return pkt_received;
1930}
1931
1932static int fec_enet_rx(struct net_device *ndev, int budget)
1933{
1934 struct fec_enet_private *fep = netdev_priv(ndev);
1935 int i, done = 0;
1936
1937 /* Make sure that AVB queues are processed first. */
1938 for (i = fep->num_rx_queues - 1; i >= 0; i--)
1939 done += fec_enet_rx_queue(ndev, budget - done, i);
1940
1941 return done;
1942}
1943
1944static bool fec_enet_collect_events(struct fec_enet_private *fep)
1945{
1946 uint int_events;
1947
1948 int_events = readl(fep->hwp + FEC_IEVENT);
1949
1950 /* Don't clear MDIO events, we poll for those */
1951 int_events &= ~FEC_ENET_MII;
1952
1953 writel(int_events, fep->hwp + FEC_IEVENT);
1954
1955 return int_events != 0;
1956}
1957
1958static irqreturn_t
1959fec_enet_interrupt(int irq, void *dev_id)
1960{
1961 struct net_device *ndev = dev_id;
1962 struct fec_enet_private *fep = netdev_priv(ndev);
1963 irqreturn_t ret = IRQ_NONE;
1964
1965 if (fec_enet_collect_events(fep) && fep->link) {
1966 ret = IRQ_HANDLED;
1967
1968 if (napi_schedule_prep(&fep->napi)) {
1969 /* Disable interrupts */
1970 writel(0, fep->hwp + FEC_IMASK);
1971 __napi_schedule(&fep->napi);
1972 }
1973 }
1974
1975 return ret;
1976}
1977
1978static int fec_enet_rx_napi(struct napi_struct *napi, int budget)
1979{
1980 struct net_device *ndev = napi->dev;
1981 struct fec_enet_private *fep = netdev_priv(ndev);
1982 int done = 0;
1983
1984 do {
1985 done += fec_enet_rx(ndev, budget - done);
1986 fec_enet_tx(ndev, budget);
1987 } while ((done < budget) && fec_enet_collect_events(fep));
1988
1989 if (done < budget) {
1990 napi_complete_done(napi, done);
1991 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK);
1992 }
1993
1994 return done;
1995}
1996
1997/* ------------------------------------------------------------------------- */
1998static int fec_get_mac(struct net_device *ndev)
1999{
2000 struct fec_enet_private *fep = netdev_priv(ndev);
2001 unsigned char *iap, tmpaddr[ETH_ALEN];
2002 int ret;
2003
2004 /*
2005 * try to get mac address in following order:
2006 *
2007 * 1) module parameter via kernel command line in form
2008 * fec.macaddr=0x00,0x04,0x9f,0x01,0x30,0xe0
2009 */
2010 iap = macaddr;
2011
2012 /*
2013 * 2) from device tree data
2014 */
2015 if (!is_valid_ether_addr(iap)) {
2016 struct device_node *np = fep->pdev->dev.of_node;
2017 if (np) {
2018 ret = of_get_mac_address(np, tmpaddr);
2019 if (!ret)
2020 iap = tmpaddr;
2021 else if (ret == -EPROBE_DEFER)
2022 return ret;
2023 }
2024 }
2025
2026 /*
2027 * 3) from flash or fuse (via platform data)
2028 */
2029 if (!is_valid_ether_addr(iap)) {
2030#ifdef CONFIG_M5272
2031 if (FEC_FLASHMAC)
2032 iap = (unsigned char *)FEC_FLASHMAC;
2033#else
2034 struct fec_platform_data *pdata = dev_get_platdata(&fep->pdev->dev);
2035
2036 if (pdata)
2037 iap = (unsigned char *)&pdata->mac;
2038#endif
2039 }
2040
2041 /*
2042 * 4) FEC mac registers set by bootloader
2043 */
2044 if (!is_valid_ether_addr(iap)) {
2045 *((__be32 *) &tmpaddr[0]) =
2046 cpu_to_be32(readl(fep->hwp + FEC_ADDR_LOW));
2047 *((__be16 *) &tmpaddr[4]) =
2048 cpu_to_be16(readl(fep->hwp + FEC_ADDR_HIGH) >> 16);
2049 iap = &tmpaddr[0];
2050 }
2051
2052 /*
2053 * 5) random mac address
2054 */
2055 if (!is_valid_ether_addr(iap)) {
2056 /* Report it and use a random ethernet address instead */
2057 dev_err(&fep->pdev->dev, "Invalid MAC address: %pM\n", iap);
2058 eth_hw_addr_random(ndev);
2059 dev_info(&fep->pdev->dev, "Using random MAC address: %pM\n",
2060 ndev->dev_addr);
2061 return 0;
2062 }
2063
2064 /* Adjust MAC if using macaddr */
2065 eth_hw_addr_gen(ndev, iap, iap == macaddr ? fep->dev_id : 0);
2066
2067 return 0;
2068}
2069
2070/* ------------------------------------------------------------------------- */
2071
2072/*
2073 * Phy section
2074 */
2075
2076/* LPI Sleep Ts count base on tx clk (clk_ref).
2077 * The lpi sleep cnt value = X us / (cycle_ns).
2078 */
2079static int fec_enet_us_to_tx_cycle(struct net_device *ndev, int us)
2080{
2081 struct fec_enet_private *fep = netdev_priv(ndev);
2082
2083 return us * (fep->clk_ref_rate / 1000) / 1000;
2084}
2085
2086static int fec_enet_eee_mode_set(struct net_device *ndev, bool enable)
2087{
2088 struct fec_enet_private *fep = netdev_priv(ndev);
2089 struct ethtool_keee *p = &fep->eee;
2090 unsigned int sleep_cycle, wake_cycle;
2091
2092 if (enable) {
2093 sleep_cycle = fec_enet_us_to_tx_cycle(ndev, p->tx_lpi_timer);
2094 wake_cycle = sleep_cycle;
2095 } else {
2096 sleep_cycle = 0;
2097 wake_cycle = 0;
2098 }
2099
2100 writel(sleep_cycle, fep->hwp + FEC_LPI_SLEEP);
2101 writel(wake_cycle, fep->hwp + FEC_LPI_WAKE);
2102
2103 return 0;
2104}
2105
2106static void fec_enet_adjust_link(struct net_device *ndev)
2107{
2108 struct fec_enet_private *fep = netdev_priv(ndev);
2109 struct phy_device *phy_dev = ndev->phydev;
2110 int status_change = 0;
2111
2112 /*
2113 * If the netdev is down, or is going down, we're not interested
2114 * in link state events, so just mark our idea of the link as down
2115 * and ignore the event.
2116 */
2117 if (!netif_running(ndev) || !netif_device_present(ndev)) {
2118 fep->link = 0;
2119 } else if (phy_dev->link) {
2120 if (!fep->link) {
2121 fep->link = phy_dev->link;
2122 status_change = 1;
2123 }
2124
2125 if (fep->full_duplex != phy_dev->duplex) {
2126 fep->full_duplex = phy_dev->duplex;
2127 status_change = 1;
2128 }
2129
2130 if (phy_dev->speed != fep->speed) {
2131 fep->speed = phy_dev->speed;
2132 status_change = 1;
2133 }
2134
2135 /* if any of the above changed restart the FEC */
2136 if (status_change) {
2137 netif_stop_queue(ndev);
2138 napi_disable(&fep->napi);
2139 netif_tx_lock_bh(ndev);
2140 fec_restart(ndev);
2141 netif_tx_wake_all_queues(ndev);
2142 netif_tx_unlock_bh(ndev);
2143 napi_enable(&fep->napi);
2144 }
2145 if (fep->quirks & FEC_QUIRK_HAS_EEE)
2146 fec_enet_eee_mode_set(ndev, phy_dev->enable_tx_lpi);
2147 } else {
2148 if (fep->link) {
2149 netif_stop_queue(ndev);
2150 napi_disable(&fep->napi);
2151 netif_tx_lock_bh(ndev);
2152 fec_stop(ndev);
2153 netif_tx_unlock_bh(ndev);
2154 napi_enable(&fep->napi);
2155 fep->link = phy_dev->link;
2156 status_change = 1;
2157 }
2158 }
2159
2160 if (status_change)
2161 phy_print_status(phy_dev);
2162}
2163
2164static int fec_enet_mdio_wait(struct fec_enet_private *fep)
2165{
2166 uint ievent;
2167 int ret;
2168
2169 ret = readl_poll_timeout_atomic(fep->hwp + FEC_IEVENT, ievent,
2170 ievent & FEC_ENET_MII, 2, 30000);
2171
2172 if (!ret)
2173 writel(FEC_ENET_MII, fep->hwp + FEC_IEVENT);
2174
2175 return ret;
2176}
2177
2178static int fec_enet_mdio_read_c22(struct mii_bus *bus, int mii_id, int regnum)
2179{
2180 struct fec_enet_private *fep = bus->priv;
2181 struct device *dev = &fep->pdev->dev;
2182 int ret = 0, frame_start, frame_addr, frame_op;
2183
2184 ret = pm_runtime_resume_and_get(dev);
2185 if (ret < 0)
2186 return ret;
2187
2188 /* C22 read */
2189 frame_op = FEC_MMFR_OP_READ;
2190 frame_start = FEC_MMFR_ST;
2191 frame_addr = regnum;
2192
2193 /* start a read op */
2194 writel(frame_start | frame_op |
2195 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(frame_addr) |
2196 FEC_MMFR_TA, fep->hwp + FEC_MII_DATA);
2197
2198 /* wait for end of transfer */
2199 ret = fec_enet_mdio_wait(fep);
2200 if (ret) {
2201 netdev_err(fep->netdev, "MDIO read timeout\n");
2202 goto out;
2203 }
2204
2205 ret = FEC_MMFR_DATA(readl(fep->hwp + FEC_MII_DATA));
2206
2207out:
2208 pm_runtime_mark_last_busy(dev);
2209 pm_runtime_put_autosuspend(dev);
2210
2211 return ret;
2212}
2213
2214static int fec_enet_mdio_read_c45(struct mii_bus *bus, int mii_id,
2215 int devad, int regnum)
2216{
2217 struct fec_enet_private *fep = bus->priv;
2218 struct device *dev = &fep->pdev->dev;
2219 int ret = 0, frame_start, frame_op;
2220
2221 ret = pm_runtime_resume_and_get(dev);
2222 if (ret < 0)
2223 return ret;
2224
2225 frame_start = FEC_MMFR_ST_C45;
2226
2227 /* write address */
2228 writel(frame_start | FEC_MMFR_OP_ADDR_WRITE |
2229 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(devad) |
2230 FEC_MMFR_TA | (regnum & 0xFFFF),
2231 fep->hwp + FEC_MII_DATA);
2232
2233 /* wait for end of transfer */
2234 ret = fec_enet_mdio_wait(fep);
2235 if (ret) {
2236 netdev_err(fep->netdev, "MDIO address write timeout\n");
2237 goto out;
2238 }
2239
2240 frame_op = FEC_MMFR_OP_READ_C45;
2241
2242 /* start a read op */
2243 writel(frame_start | frame_op |
2244 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(devad) |
2245 FEC_MMFR_TA, fep->hwp + FEC_MII_DATA);
2246
2247 /* wait for end of transfer */
2248 ret = fec_enet_mdio_wait(fep);
2249 if (ret) {
2250 netdev_err(fep->netdev, "MDIO read timeout\n");
2251 goto out;
2252 }
2253
2254 ret = FEC_MMFR_DATA(readl(fep->hwp + FEC_MII_DATA));
2255
2256out:
2257 pm_runtime_mark_last_busy(dev);
2258 pm_runtime_put_autosuspend(dev);
2259
2260 return ret;
2261}
2262
2263static int fec_enet_mdio_write_c22(struct mii_bus *bus, int mii_id, int regnum,
2264 u16 value)
2265{
2266 struct fec_enet_private *fep = bus->priv;
2267 struct device *dev = &fep->pdev->dev;
2268 int ret, frame_start, frame_addr;
2269
2270 ret = pm_runtime_resume_and_get(dev);
2271 if (ret < 0)
2272 return ret;
2273
2274 /* C22 write */
2275 frame_start = FEC_MMFR_ST;
2276 frame_addr = regnum;
2277
2278 /* start a write op */
2279 writel(frame_start | FEC_MMFR_OP_WRITE |
2280 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(frame_addr) |
2281 FEC_MMFR_TA | FEC_MMFR_DATA(value),
2282 fep->hwp + FEC_MII_DATA);
2283
2284 /* wait for end of transfer */
2285 ret = fec_enet_mdio_wait(fep);
2286 if (ret)
2287 netdev_err(fep->netdev, "MDIO write timeout\n");
2288
2289 pm_runtime_mark_last_busy(dev);
2290 pm_runtime_put_autosuspend(dev);
2291
2292 return ret;
2293}
2294
2295static int fec_enet_mdio_write_c45(struct mii_bus *bus, int mii_id,
2296 int devad, int regnum, u16 value)
2297{
2298 struct fec_enet_private *fep = bus->priv;
2299 struct device *dev = &fep->pdev->dev;
2300 int ret, frame_start;
2301
2302 ret = pm_runtime_resume_and_get(dev);
2303 if (ret < 0)
2304 return ret;
2305
2306 frame_start = FEC_MMFR_ST_C45;
2307
2308 /* write address */
2309 writel(frame_start | FEC_MMFR_OP_ADDR_WRITE |
2310 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(devad) |
2311 FEC_MMFR_TA | (regnum & 0xFFFF),
2312 fep->hwp + FEC_MII_DATA);
2313
2314 /* wait for end of transfer */
2315 ret = fec_enet_mdio_wait(fep);
2316 if (ret) {
2317 netdev_err(fep->netdev, "MDIO address write timeout\n");
2318 goto out;
2319 }
2320
2321 /* start a write op */
2322 writel(frame_start | FEC_MMFR_OP_WRITE |
2323 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(devad) |
2324 FEC_MMFR_TA | FEC_MMFR_DATA(value),
2325 fep->hwp + FEC_MII_DATA);
2326
2327 /* wait for end of transfer */
2328 ret = fec_enet_mdio_wait(fep);
2329 if (ret)
2330 netdev_err(fep->netdev, "MDIO write timeout\n");
2331
2332out:
2333 pm_runtime_mark_last_busy(dev);
2334 pm_runtime_put_autosuspend(dev);
2335
2336 return ret;
2337}
2338
2339static void fec_enet_phy_reset_after_clk_enable(struct net_device *ndev)
2340{
2341 struct fec_enet_private *fep = netdev_priv(ndev);
2342 struct phy_device *phy_dev = ndev->phydev;
2343
2344 if (phy_dev) {
2345 phy_reset_after_clk_enable(phy_dev);
2346 } else if (fep->phy_node) {
2347 /*
2348 * If the PHY still is not bound to the MAC, but there is
2349 * OF PHY node and a matching PHY device instance already,
2350 * use the OF PHY node to obtain the PHY device instance,
2351 * and then use that PHY device instance when triggering
2352 * the PHY reset.
2353 */
2354 phy_dev = of_phy_find_device(fep->phy_node);
2355 phy_reset_after_clk_enable(phy_dev);
2356 put_device(&phy_dev->mdio.dev);
2357 }
2358}
2359
2360static int fec_enet_clk_enable(struct net_device *ndev, bool enable)
2361{
2362 struct fec_enet_private *fep = netdev_priv(ndev);
2363 int ret;
2364
2365 if (enable) {
2366 ret = clk_prepare_enable(fep->clk_enet_out);
2367 if (ret)
2368 return ret;
2369
2370 if (fep->clk_ptp) {
2371 mutex_lock(&fep->ptp_clk_mutex);
2372 ret = clk_prepare_enable(fep->clk_ptp);
2373 if (ret) {
2374 mutex_unlock(&fep->ptp_clk_mutex);
2375 goto failed_clk_ptp;
2376 } else {
2377 fep->ptp_clk_on = true;
2378 }
2379 mutex_unlock(&fep->ptp_clk_mutex);
2380 }
2381
2382 ret = clk_prepare_enable(fep->clk_ref);
2383 if (ret)
2384 goto failed_clk_ref;
2385
2386 ret = clk_prepare_enable(fep->clk_2x_txclk);
2387 if (ret)
2388 goto failed_clk_2x_txclk;
2389
2390 fec_enet_phy_reset_after_clk_enable(ndev);
2391 } else {
2392 clk_disable_unprepare(fep->clk_enet_out);
2393 if (fep->clk_ptp) {
2394 mutex_lock(&fep->ptp_clk_mutex);
2395 clk_disable_unprepare(fep->clk_ptp);
2396 fep->ptp_clk_on = false;
2397 mutex_unlock(&fep->ptp_clk_mutex);
2398 }
2399 clk_disable_unprepare(fep->clk_ref);
2400 clk_disable_unprepare(fep->clk_2x_txclk);
2401 }
2402
2403 return 0;
2404
2405failed_clk_2x_txclk:
2406 if (fep->clk_ref)
2407 clk_disable_unprepare(fep->clk_ref);
2408failed_clk_ref:
2409 if (fep->clk_ptp) {
2410 mutex_lock(&fep->ptp_clk_mutex);
2411 clk_disable_unprepare(fep->clk_ptp);
2412 fep->ptp_clk_on = false;
2413 mutex_unlock(&fep->ptp_clk_mutex);
2414 }
2415failed_clk_ptp:
2416 clk_disable_unprepare(fep->clk_enet_out);
2417
2418 return ret;
2419}
2420
2421static int fec_enet_parse_rgmii_delay(struct fec_enet_private *fep,
2422 struct device_node *np)
2423{
2424 u32 rgmii_tx_delay, rgmii_rx_delay;
2425
2426 /* For rgmii tx internal delay, valid values are 0ps and 2000ps */
2427 if (!of_property_read_u32(np, "tx-internal-delay-ps", &rgmii_tx_delay)) {
2428 if (rgmii_tx_delay != 0 && rgmii_tx_delay != 2000) {
2429 dev_err(&fep->pdev->dev, "The only allowed RGMII TX delay values are: 0ps, 2000ps");
2430 return -EINVAL;
2431 } else if (rgmii_tx_delay == 2000) {
2432 fep->rgmii_txc_dly = true;
2433 }
2434 }
2435
2436 /* For rgmii rx internal delay, valid values are 0ps and 2000ps */
2437 if (!of_property_read_u32(np, "rx-internal-delay-ps", &rgmii_rx_delay)) {
2438 if (rgmii_rx_delay != 0 && rgmii_rx_delay != 2000) {
2439 dev_err(&fep->pdev->dev, "The only allowed RGMII RX delay values are: 0ps, 2000ps");
2440 return -EINVAL;
2441 } else if (rgmii_rx_delay == 2000) {
2442 fep->rgmii_rxc_dly = true;
2443 }
2444 }
2445
2446 return 0;
2447}
2448
2449static int fec_enet_mii_probe(struct net_device *ndev)
2450{
2451 struct fec_enet_private *fep = netdev_priv(ndev);
2452 struct phy_device *phy_dev = NULL;
2453 char mdio_bus_id[MII_BUS_ID_SIZE];
2454 char phy_name[MII_BUS_ID_SIZE + 3];
2455 int phy_id;
2456 int dev_id = fep->dev_id;
2457
2458 if (fep->phy_node) {
2459 phy_dev = of_phy_connect(ndev, fep->phy_node,
2460 &fec_enet_adjust_link, 0,
2461 fep->phy_interface);
2462 if (!phy_dev) {
2463 netdev_err(ndev, "Unable to connect to phy\n");
2464 return -ENODEV;
2465 }
2466 } else {
2467 /* check for attached phy */
2468 for (phy_id = 0; (phy_id < PHY_MAX_ADDR); phy_id++) {
2469 if (!mdiobus_is_registered_device(fep->mii_bus, phy_id))
2470 continue;
2471 if (dev_id--)
2472 continue;
2473 strscpy(mdio_bus_id, fep->mii_bus->id, MII_BUS_ID_SIZE);
2474 break;
2475 }
2476
2477 if (phy_id >= PHY_MAX_ADDR) {
2478 netdev_info(ndev, "no PHY, assuming direct connection to switch\n");
2479 strscpy(mdio_bus_id, "fixed-0", MII_BUS_ID_SIZE);
2480 phy_id = 0;
2481 }
2482
2483 snprintf(phy_name, sizeof(phy_name),
2484 PHY_ID_FMT, mdio_bus_id, phy_id);
2485 phy_dev = phy_connect(ndev, phy_name, &fec_enet_adjust_link,
2486 fep->phy_interface);
2487 }
2488
2489 if (IS_ERR(phy_dev)) {
2490 netdev_err(ndev, "could not attach to PHY\n");
2491 return PTR_ERR(phy_dev);
2492 }
2493
2494 /* mask with MAC supported features */
2495 if (fep->quirks & FEC_QUIRK_HAS_GBIT) {
2496 phy_set_max_speed(phy_dev, 1000);
2497 phy_remove_link_mode(phy_dev,
2498 ETHTOOL_LINK_MODE_1000baseT_Half_BIT);
2499#if !defined(CONFIG_M5272)
2500 phy_support_sym_pause(phy_dev);
2501#endif
2502 }
2503 else
2504 phy_set_max_speed(phy_dev, 100);
2505
2506 if (fep->quirks & FEC_QUIRK_HAS_EEE)
2507 phy_support_eee(phy_dev);
2508
2509 fep->link = 0;
2510 fep->full_duplex = 0;
2511
2512 phy_attached_info(phy_dev);
2513
2514 return 0;
2515}
2516
2517static int fec_enet_mii_init(struct platform_device *pdev)
2518{
2519 static struct mii_bus *fec0_mii_bus;
2520 struct net_device *ndev = platform_get_drvdata(pdev);
2521 struct fec_enet_private *fep = netdev_priv(ndev);
2522 bool suppress_preamble = false;
2523 struct phy_device *phydev;
2524 struct device_node *node;
2525 int err = -ENXIO;
2526 u32 mii_speed, holdtime;
2527 u32 bus_freq;
2528 int addr;
2529
2530 /*
2531 * The i.MX28 dual fec interfaces are not equal.
2532 * Here are the differences:
2533 *
2534 * - fec0 supports MII & RMII modes while fec1 only supports RMII
2535 * - fec0 acts as the 1588 time master while fec1 is slave
2536 * - external phys can only be configured by fec0
2537 *
2538 * That is to say fec1 can not work independently. It only works
2539 * when fec0 is working. The reason behind this design is that the
2540 * second interface is added primarily for Switch mode.
2541 *
2542 * Because of the last point above, both phys are attached on fec0
2543 * mdio interface in board design, and need to be configured by
2544 * fec0 mii_bus.
2545 */
2546 if ((fep->quirks & FEC_QUIRK_SINGLE_MDIO) && fep->dev_id > 0) {
2547 /* fec1 uses fec0 mii_bus */
2548 if (mii_cnt && fec0_mii_bus) {
2549 fep->mii_bus = fec0_mii_bus;
2550 mii_cnt++;
2551 return 0;
2552 }
2553 return -ENOENT;
2554 }
2555
2556 bus_freq = 2500000; /* 2.5MHz by default */
2557 node = of_get_child_by_name(pdev->dev.of_node, "mdio");
2558 if (node) {
2559 of_property_read_u32(node, "clock-frequency", &bus_freq);
2560 suppress_preamble = of_property_read_bool(node,
2561 "suppress-preamble");
2562 }
2563
2564 /*
2565 * Set MII speed (= clk_get_rate() / 2 * phy_speed)
2566 *
2567 * The formula for FEC MDC is 'ref_freq / (MII_SPEED x 2)' while
2568 * for ENET-MAC is 'ref_freq / ((MII_SPEED + 1) x 2)'. The i.MX28
2569 * Reference Manual has an error on this, and gets fixed on i.MX6Q
2570 * document.
2571 */
2572 mii_speed = DIV_ROUND_UP(clk_get_rate(fep->clk_ipg), bus_freq * 2);
2573 if (fep->quirks & FEC_QUIRK_ENET_MAC)
2574 mii_speed--;
2575 if (mii_speed > 63) {
2576 dev_err(&pdev->dev,
2577 "fec clock (%lu) too fast to get right mii speed\n",
2578 clk_get_rate(fep->clk_ipg));
2579 err = -EINVAL;
2580 goto err_out;
2581 }
2582
2583 /*
2584 * The i.MX28 and i.MX6 types have another filed in the MSCR (aka
2585 * MII_SPEED) register that defines the MDIO output hold time. Earlier
2586 * versions are RAZ there, so just ignore the difference and write the
2587 * register always.
2588 * The minimal hold time according to IEE802.3 (clause 22) is 10 ns.
2589 * HOLDTIME + 1 is the number of clk cycles the fec is holding the
2590 * output.
2591 * The HOLDTIME bitfield takes values between 0 and 7 (inclusive).
2592 * Given that ceil(clkrate / 5000000) <= 64, the calculation for
2593 * holdtime cannot result in a value greater than 3.
2594 */
2595 holdtime = DIV_ROUND_UP(clk_get_rate(fep->clk_ipg), 100000000) - 1;
2596
2597 fep->phy_speed = mii_speed << 1 | holdtime << 8;
2598
2599 if (suppress_preamble)
2600 fep->phy_speed |= BIT(7);
2601
2602 if (fep->quirks & FEC_QUIRK_CLEAR_SETUP_MII) {
2603 /* Clear MMFR to avoid to generate MII event by writing MSCR.
2604 * MII event generation condition:
2605 * - writing MSCR:
2606 * - mmfr[31:0]_not_zero & mscr[7:0]_is_zero &
2607 * mscr_reg_data_in[7:0] != 0
2608 * - writing MMFR:
2609 * - mscr[7:0]_not_zero
2610 */
2611 writel(0, fep->hwp + FEC_MII_DATA);
2612 }
2613
2614 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
2615
2616 /* Clear any pending transaction complete indication */
2617 writel(FEC_ENET_MII, fep->hwp + FEC_IEVENT);
2618
2619 fep->mii_bus = mdiobus_alloc();
2620 if (fep->mii_bus == NULL) {
2621 err = -ENOMEM;
2622 goto err_out;
2623 }
2624
2625 fep->mii_bus->name = "fec_enet_mii_bus";
2626 fep->mii_bus->read = fec_enet_mdio_read_c22;
2627 fep->mii_bus->write = fec_enet_mdio_write_c22;
2628 if (fep->quirks & FEC_QUIRK_HAS_MDIO_C45) {
2629 fep->mii_bus->read_c45 = fec_enet_mdio_read_c45;
2630 fep->mii_bus->write_c45 = fec_enet_mdio_write_c45;
2631 }
2632 snprintf(fep->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
2633 pdev->name, fep->dev_id + 1);
2634 fep->mii_bus->priv = fep;
2635 fep->mii_bus->parent = &pdev->dev;
2636
2637 err = of_mdiobus_register(fep->mii_bus, node);
2638 if (err)
2639 goto err_out_free_mdiobus;
2640 of_node_put(node);
2641
2642 /* find all the PHY devices on the bus and set mac_managed_pm to true */
2643 for (addr = 0; addr < PHY_MAX_ADDR; addr++) {
2644 phydev = mdiobus_get_phy(fep->mii_bus, addr);
2645 if (phydev)
2646 phydev->mac_managed_pm = true;
2647 }
2648
2649 mii_cnt++;
2650
2651 /* save fec0 mii_bus */
2652 if (fep->quirks & FEC_QUIRK_SINGLE_MDIO)
2653 fec0_mii_bus = fep->mii_bus;
2654
2655 return 0;
2656
2657err_out_free_mdiobus:
2658 mdiobus_free(fep->mii_bus);
2659err_out:
2660 of_node_put(node);
2661 return err;
2662}
2663
2664static void fec_enet_mii_remove(struct fec_enet_private *fep)
2665{
2666 if (--mii_cnt == 0) {
2667 mdiobus_unregister(fep->mii_bus);
2668 mdiobus_free(fep->mii_bus);
2669 }
2670}
2671
2672static void fec_enet_get_drvinfo(struct net_device *ndev,
2673 struct ethtool_drvinfo *info)
2674{
2675 struct fec_enet_private *fep = netdev_priv(ndev);
2676
2677 strscpy(info->driver, fep->pdev->dev.driver->name,
2678 sizeof(info->driver));
2679 strscpy(info->bus_info, dev_name(&ndev->dev), sizeof(info->bus_info));
2680}
2681
2682static int fec_enet_get_regs_len(struct net_device *ndev)
2683{
2684 struct fec_enet_private *fep = netdev_priv(ndev);
2685 struct resource *r;
2686 int s = 0;
2687
2688 r = platform_get_resource(fep->pdev, IORESOURCE_MEM, 0);
2689 if (r)
2690 s = resource_size(r);
2691
2692 return s;
2693}
2694
2695/* List of registers that can be safety be read to dump them with ethtool */
2696#if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
2697 defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_ARM) || \
2698 defined(CONFIG_ARM64) || defined(CONFIG_COMPILE_TEST)
2699static __u32 fec_enet_register_version = 2;
2700static u32 fec_enet_register_offset[] = {
2701 FEC_IEVENT, FEC_IMASK, FEC_R_DES_ACTIVE_0, FEC_X_DES_ACTIVE_0,
2702 FEC_ECNTRL, FEC_MII_DATA, FEC_MII_SPEED, FEC_MIB_CTRLSTAT, FEC_R_CNTRL,
2703 FEC_X_CNTRL, FEC_ADDR_LOW, FEC_ADDR_HIGH, FEC_OPD, FEC_TXIC0, FEC_TXIC1,
2704 FEC_TXIC2, FEC_RXIC0, FEC_RXIC1, FEC_RXIC2, FEC_HASH_TABLE_HIGH,
2705 FEC_HASH_TABLE_LOW, FEC_GRP_HASH_TABLE_HIGH, FEC_GRP_HASH_TABLE_LOW,
2706 FEC_X_WMRK, FEC_R_BOUND, FEC_R_FSTART, FEC_R_DES_START_1,
2707 FEC_X_DES_START_1, FEC_R_BUFF_SIZE_1, FEC_R_DES_START_2,
2708 FEC_X_DES_START_2, FEC_R_BUFF_SIZE_2, FEC_R_DES_START_0,
2709 FEC_X_DES_START_0, FEC_R_BUFF_SIZE_0, FEC_R_FIFO_RSFL, FEC_R_FIFO_RSEM,
2710 FEC_R_FIFO_RAEM, FEC_R_FIFO_RAFL, FEC_RACC, FEC_RCMR_1, FEC_RCMR_2,
2711 FEC_DMA_CFG_1, FEC_DMA_CFG_2, FEC_R_DES_ACTIVE_1, FEC_X_DES_ACTIVE_1,
2712 FEC_R_DES_ACTIVE_2, FEC_X_DES_ACTIVE_2, FEC_QOS_SCHEME,
2713 RMON_T_DROP, RMON_T_PACKETS, RMON_T_BC_PKT, RMON_T_MC_PKT,
2714 RMON_T_CRC_ALIGN, RMON_T_UNDERSIZE, RMON_T_OVERSIZE, RMON_T_FRAG,
2715 RMON_T_JAB, RMON_T_COL, RMON_T_P64, RMON_T_P65TO127, RMON_T_P128TO255,
2716 RMON_T_P256TO511, RMON_T_P512TO1023, RMON_T_P1024TO2047,
2717 RMON_T_P_GTE2048, RMON_T_OCTETS,
2718 IEEE_T_DROP, IEEE_T_FRAME_OK, IEEE_T_1COL, IEEE_T_MCOL, IEEE_T_DEF,
2719 IEEE_T_LCOL, IEEE_T_EXCOL, IEEE_T_MACERR, IEEE_T_CSERR, IEEE_T_SQE,
2720 IEEE_T_FDXFC, IEEE_T_OCTETS_OK,
2721 RMON_R_PACKETS, RMON_R_BC_PKT, RMON_R_MC_PKT, RMON_R_CRC_ALIGN,
2722 RMON_R_UNDERSIZE, RMON_R_OVERSIZE, RMON_R_FRAG, RMON_R_JAB,
2723 RMON_R_RESVD_O, RMON_R_P64, RMON_R_P65TO127, RMON_R_P128TO255,
2724 RMON_R_P256TO511, RMON_R_P512TO1023, RMON_R_P1024TO2047,
2725 RMON_R_P_GTE2048, RMON_R_OCTETS,
2726 IEEE_R_DROP, IEEE_R_FRAME_OK, IEEE_R_CRC, IEEE_R_ALIGN, IEEE_R_MACERR,
2727 IEEE_R_FDXFC, IEEE_R_OCTETS_OK
2728};
2729/* for i.MX6ul */
2730static u32 fec_enet_register_offset_6ul[] = {
2731 FEC_IEVENT, FEC_IMASK, FEC_R_DES_ACTIVE_0, FEC_X_DES_ACTIVE_0,
2732 FEC_ECNTRL, FEC_MII_DATA, FEC_MII_SPEED, FEC_MIB_CTRLSTAT, FEC_R_CNTRL,
2733 FEC_X_CNTRL, FEC_ADDR_LOW, FEC_ADDR_HIGH, FEC_OPD, FEC_TXIC0, FEC_RXIC0,
2734 FEC_HASH_TABLE_HIGH, FEC_HASH_TABLE_LOW, FEC_GRP_HASH_TABLE_HIGH,
2735 FEC_GRP_HASH_TABLE_LOW, FEC_X_WMRK, FEC_R_DES_START_0,
2736 FEC_X_DES_START_0, FEC_R_BUFF_SIZE_0, FEC_R_FIFO_RSFL, FEC_R_FIFO_RSEM,
2737 FEC_R_FIFO_RAEM, FEC_R_FIFO_RAFL, FEC_RACC,
2738 RMON_T_DROP, RMON_T_PACKETS, RMON_T_BC_PKT, RMON_T_MC_PKT,
2739 RMON_T_CRC_ALIGN, RMON_T_UNDERSIZE, RMON_T_OVERSIZE, RMON_T_FRAG,
2740 RMON_T_JAB, RMON_T_COL, RMON_T_P64, RMON_T_P65TO127, RMON_T_P128TO255,
2741 RMON_T_P256TO511, RMON_T_P512TO1023, RMON_T_P1024TO2047,
2742 RMON_T_P_GTE2048, RMON_T_OCTETS,
2743 IEEE_T_DROP, IEEE_T_FRAME_OK, IEEE_T_1COL, IEEE_T_MCOL, IEEE_T_DEF,
2744 IEEE_T_LCOL, IEEE_T_EXCOL, IEEE_T_MACERR, IEEE_T_CSERR, IEEE_T_SQE,
2745 IEEE_T_FDXFC, IEEE_T_OCTETS_OK,
2746 RMON_R_PACKETS, RMON_R_BC_PKT, RMON_R_MC_PKT, RMON_R_CRC_ALIGN,
2747 RMON_R_UNDERSIZE, RMON_R_OVERSIZE, RMON_R_FRAG, RMON_R_JAB,
2748 RMON_R_RESVD_O, RMON_R_P64, RMON_R_P65TO127, RMON_R_P128TO255,
2749 RMON_R_P256TO511, RMON_R_P512TO1023, RMON_R_P1024TO2047,
2750 RMON_R_P_GTE2048, RMON_R_OCTETS,
2751 IEEE_R_DROP, IEEE_R_FRAME_OK, IEEE_R_CRC, IEEE_R_ALIGN, IEEE_R_MACERR,
2752 IEEE_R_FDXFC, IEEE_R_OCTETS_OK
2753};
2754#else
2755static __u32 fec_enet_register_version = 1;
2756static u32 fec_enet_register_offset[] = {
2757 FEC_ECNTRL, FEC_IEVENT, FEC_IMASK, FEC_IVEC, FEC_R_DES_ACTIVE_0,
2758 FEC_R_DES_ACTIVE_1, FEC_R_DES_ACTIVE_2, FEC_X_DES_ACTIVE_0,
2759 FEC_X_DES_ACTIVE_1, FEC_X_DES_ACTIVE_2, FEC_MII_DATA, FEC_MII_SPEED,
2760 FEC_R_BOUND, FEC_R_FSTART, FEC_X_WMRK, FEC_X_FSTART, FEC_R_CNTRL,
2761 FEC_MAX_FRM_LEN, FEC_X_CNTRL, FEC_ADDR_LOW, FEC_ADDR_HIGH,
2762 FEC_GRP_HASH_TABLE_HIGH, FEC_GRP_HASH_TABLE_LOW, FEC_R_DES_START_0,
2763 FEC_R_DES_START_1, FEC_R_DES_START_2, FEC_X_DES_START_0,
2764 FEC_X_DES_START_1, FEC_X_DES_START_2, FEC_R_BUFF_SIZE_0,
2765 FEC_R_BUFF_SIZE_1, FEC_R_BUFF_SIZE_2
2766};
2767#endif
2768
2769static void fec_enet_get_regs(struct net_device *ndev,
2770 struct ethtool_regs *regs, void *regbuf)
2771{
2772 struct fec_enet_private *fep = netdev_priv(ndev);
2773 u32 __iomem *theregs = (u32 __iomem *)fep->hwp;
2774 struct device *dev = &fep->pdev->dev;
2775 u32 *buf = (u32 *)regbuf;
2776 u32 i, off;
2777 int ret;
2778#if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
2779 defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_ARM) || \
2780 defined(CONFIG_ARM64) || defined(CONFIG_COMPILE_TEST)
2781 u32 *reg_list;
2782 u32 reg_cnt;
2783
2784 if (!of_machine_is_compatible("fsl,imx6ul")) {
2785 reg_list = fec_enet_register_offset;
2786 reg_cnt = ARRAY_SIZE(fec_enet_register_offset);
2787 } else {
2788 reg_list = fec_enet_register_offset_6ul;
2789 reg_cnt = ARRAY_SIZE(fec_enet_register_offset_6ul);
2790 }
2791#else
2792 /* coldfire */
2793 static u32 *reg_list = fec_enet_register_offset;
2794 static const u32 reg_cnt = ARRAY_SIZE(fec_enet_register_offset);
2795#endif
2796 ret = pm_runtime_resume_and_get(dev);
2797 if (ret < 0)
2798 return;
2799
2800 regs->version = fec_enet_register_version;
2801
2802 memset(buf, 0, regs->len);
2803
2804 for (i = 0; i < reg_cnt; i++) {
2805 off = reg_list[i];
2806
2807 if ((off == FEC_R_BOUND || off == FEC_R_FSTART) &&
2808 !(fep->quirks & FEC_QUIRK_HAS_FRREG))
2809 continue;
2810
2811 off >>= 2;
2812 buf[off] = readl(&theregs[off]);
2813 }
2814
2815 pm_runtime_mark_last_busy(dev);
2816 pm_runtime_put_autosuspend(dev);
2817}
2818
2819static int fec_enet_get_ts_info(struct net_device *ndev,
2820 struct kernel_ethtool_ts_info *info)
2821{
2822 struct fec_enet_private *fep = netdev_priv(ndev);
2823
2824 if (fep->bufdesc_ex) {
2825
2826 info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE |
2827 SOF_TIMESTAMPING_TX_HARDWARE |
2828 SOF_TIMESTAMPING_RX_HARDWARE |
2829 SOF_TIMESTAMPING_RAW_HARDWARE;
2830 if (fep->ptp_clock)
2831 info->phc_index = ptp_clock_index(fep->ptp_clock);
2832
2833 info->tx_types = (1 << HWTSTAMP_TX_OFF) |
2834 (1 << HWTSTAMP_TX_ON);
2835
2836 info->rx_filters = (1 << HWTSTAMP_FILTER_NONE) |
2837 (1 << HWTSTAMP_FILTER_ALL);
2838 return 0;
2839 } else {
2840 return ethtool_op_get_ts_info(ndev, info);
2841 }
2842}
2843
2844#if !defined(CONFIG_M5272)
2845
2846static void fec_enet_get_pauseparam(struct net_device *ndev,
2847 struct ethtool_pauseparam *pause)
2848{
2849 struct fec_enet_private *fep = netdev_priv(ndev);
2850
2851 pause->autoneg = (fep->pause_flag & FEC_PAUSE_FLAG_AUTONEG) != 0;
2852 pause->tx_pause = (fep->pause_flag & FEC_PAUSE_FLAG_ENABLE) != 0;
2853 pause->rx_pause = pause->tx_pause;
2854}
2855
2856static int fec_enet_set_pauseparam(struct net_device *ndev,
2857 struct ethtool_pauseparam *pause)
2858{
2859 struct fec_enet_private *fep = netdev_priv(ndev);
2860
2861 if (!ndev->phydev)
2862 return -ENODEV;
2863
2864 if (pause->tx_pause != pause->rx_pause) {
2865 netdev_info(ndev,
2866 "hardware only support enable/disable both tx and rx");
2867 return -EINVAL;
2868 }
2869
2870 fep->pause_flag = 0;
2871
2872 /* tx pause must be same as rx pause */
2873 fep->pause_flag |= pause->rx_pause ? FEC_PAUSE_FLAG_ENABLE : 0;
2874 fep->pause_flag |= pause->autoneg ? FEC_PAUSE_FLAG_AUTONEG : 0;
2875
2876 phy_set_sym_pause(ndev->phydev, pause->rx_pause, pause->tx_pause,
2877 pause->autoneg);
2878
2879 if (pause->autoneg) {
2880 if (netif_running(ndev))
2881 fec_stop(ndev);
2882 phy_start_aneg(ndev->phydev);
2883 }
2884 if (netif_running(ndev)) {
2885 napi_disable(&fep->napi);
2886 netif_tx_lock_bh(ndev);
2887 fec_restart(ndev);
2888 netif_tx_wake_all_queues(ndev);
2889 netif_tx_unlock_bh(ndev);
2890 napi_enable(&fep->napi);
2891 }
2892
2893 return 0;
2894}
2895
2896static const struct fec_stat {
2897 char name[ETH_GSTRING_LEN];
2898 u16 offset;
2899} fec_stats[] = {
2900 /* RMON TX */
2901 { "tx_dropped", RMON_T_DROP },
2902 { "tx_packets", RMON_T_PACKETS },
2903 { "tx_broadcast", RMON_T_BC_PKT },
2904 { "tx_multicast", RMON_T_MC_PKT },
2905 { "tx_crc_errors", RMON_T_CRC_ALIGN },
2906 { "tx_undersize", RMON_T_UNDERSIZE },
2907 { "tx_oversize", RMON_T_OVERSIZE },
2908 { "tx_fragment", RMON_T_FRAG },
2909 { "tx_jabber", RMON_T_JAB },
2910 { "tx_collision", RMON_T_COL },
2911 { "tx_64byte", RMON_T_P64 },
2912 { "tx_65to127byte", RMON_T_P65TO127 },
2913 { "tx_128to255byte", RMON_T_P128TO255 },
2914 { "tx_256to511byte", RMON_T_P256TO511 },
2915 { "tx_512to1023byte", RMON_T_P512TO1023 },
2916 { "tx_1024to2047byte", RMON_T_P1024TO2047 },
2917 { "tx_GTE2048byte", RMON_T_P_GTE2048 },
2918 { "tx_octets", RMON_T_OCTETS },
2919
2920 /* IEEE TX */
2921 { "IEEE_tx_drop", IEEE_T_DROP },
2922 { "IEEE_tx_frame_ok", IEEE_T_FRAME_OK },
2923 { "IEEE_tx_1col", IEEE_T_1COL },
2924 { "IEEE_tx_mcol", IEEE_T_MCOL },
2925 { "IEEE_tx_def", IEEE_T_DEF },
2926 { "IEEE_tx_lcol", IEEE_T_LCOL },
2927 { "IEEE_tx_excol", IEEE_T_EXCOL },
2928 { "IEEE_tx_macerr", IEEE_T_MACERR },
2929 { "IEEE_tx_cserr", IEEE_T_CSERR },
2930 { "IEEE_tx_sqe", IEEE_T_SQE },
2931 { "IEEE_tx_fdxfc", IEEE_T_FDXFC },
2932 { "IEEE_tx_octets_ok", IEEE_T_OCTETS_OK },
2933
2934 /* RMON RX */
2935 { "rx_packets", RMON_R_PACKETS },
2936 { "rx_broadcast", RMON_R_BC_PKT },
2937 { "rx_multicast", RMON_R_MC_PKT },
2938 { "rx_crc_errors", RMON_R_CRC_ALIGN },
2939 { "rx_undersize", RMON_R_UNDERSIZE },
2940 { "rx_oversize", RMON_R_OVERSIZE },
2941 { "rx_fragment", RMON_R_FRAG },
2942 { "rx_jabber", RMON_R_JAB },
2943 { "rx_64byte", RMON_R_P64 },
2944 { "rx_65to127byte", RMON_R_P65TO127 },
2945 { "rx_128to255byte", RMON_R_P128TO255 },
2946 { "rx_256to511byte", RMON_R_P256TO511 },
2947 { "rx_512to1023byte", RMON_R_P512TO1023 },
2948 { "rx_1024to2047byte", RMON_R_P1024TO2047 },
2949 { "rx_GTE2048byte", RMON_R_P_GTE2048 },
2950 { "rx_octets", RMON_R_OCTETS },
2951
2952 /* IEEE RX */
2953 { "IEEE_rx_drop", IEEE_R_DROP },
2954 { "IEEE_rx_frame_ok", IEEE_R_FRAME_OK },
2955 { "IEEE_rx_crc", IEEE_R_CRC },
2956 { "IEEE_rx_align", IEEE_R_ALIGN },
2957 { "IEEE_rx_macerr", IEEE_R_MACERR },
2958 { "IEEE_rx_fdxfc", IEEE_R_FDXFC },
2959 { "IEEE_rx_octets_ok", IEEE_R_OCTETS_OK },
2960};
2961
2962#define FEC_STATS_SIZE (ARRAY_SIZE(fec_stats) * sizeof(u64))
2963
2964static const char *fec_xdp_stat_strs[XDP_STATS_TOTAL] = {
2965 "rx_xdp_redirect", /* RX_XDP_REDIRECT = 0, */
2966 "rx_xdp_pass", /* RX_XDP_PASS, */
2967 "rx_xdp_drop", /* RX_XDP_DROP, */
2968 "rx_xdp_tx", /* RX_XDP_TX, */
2969 "rx_xdp_tx_errors", /* RX_XDP_TX_ERRORS, */
2970 "tx_xdp_xmit", /* TX_XDP_XMIT, */
2971 "tx_xdp_xmit_errors", /* TX_XDP_XMIT_ERRORS, */
2972};
2973
2974static void fec_enet_update_ethtool_stats(struct net_device *dev)
2975{
2976 struct fec_enet_private *fep = netdev_priv(dev);
2977 int i;
2978
2979 for (i = 0; i < ARRAY_SIZE(fec_stats); i++)
2980 fep->ethtool_stats[i] = readl(fep->hwp + fec_stats[i].offset);
2981}
2982
2983static void fec_enet_get_xdp_stats(struct fec_enet_private *fep, u64 *data)
2984{
2985 u64 xdp_stats[XDP_STATS_TOTAL] = { 0 };
2986 struct fec_enet_priv_rx_q *rxq;
2987 int i, j;
2988
2989 for (i = fep->num_rx_queues - 1; i >= 0; i--) {
2990 rxq = fep->rx_queue[i];
2991
2992 for (j = 0; j < XDP_STATS_TOTAL; j++)
2993 xdp_stats[j] += rxq->stats[j];
2994 }
2995
2996 memcpy(data, xdp_stats, sizeof(xdp_stats));
2997}
2998
2999static void fec_enet_page_pool_stats(struct fec_enet_private *fep, u64 *data)
3000{
3001#ifdef CONFIG_PAGE_POOL_STATS
3002 struct page_pool_stats stats = {};
3003 struct fec_enet_priv_rx_q *rxq;
3004 int i;
3005
3006 for (i = fep->num_rx_queues - 1; i >= 0; i--) {
3007 rxq = fep->rx_queue[i];
3008
3009 if (!rxq->page_pool)
3010 continue;
3011
3012 page_pool_get_stats(rxq->page_pool, &stats);
3013 }
3014
3015 page_pool_ethtool_stats_get(data, &stats);
3016#endif
3017}
3018
3019static void fec_enet_get_ethtool_stats(struct net_device *dev,
3020 struct ethtool_stats *stats, u64 *data)
3021{
3022 struct fec_enet_private *fep = netdev_priv(dev);
3023
3024 if (netif_running(dev))
3025 fec_enet_update_ethtool_stats(dev);
3026
3027 memcpy(data, fep->ethtool_stats, FEC_STATS_SIZE);
3028 data += FEC_STATS_SIZE / sizeof(u64);
3029
3030 fec_enet_get_xdp_stats(fep, data);
3031 data += XDP_STATS_TOTAL;
3032
3033 fec_enet_page_pool_stats(fep, data);
3034}
3035
3036static void fec_enet_get_strings(struct net_device *netdev,
3037 u32 stringset, u8 *data)
3038{
3039 int i;
3040 switch (stringset) {
3041 case ETH_SS_STATS:
3042 for (i = 0; i < ARRAY_SIZE(fec_stats); i++) {
3043 ethtool_puts(&data, fec_stats[i].name);
3044 }
3045 for (i = 0; i < ARRAY_SIZE(fec_xdp_stat_strs); i++) {
3046 ethtool_puts(&data, fec_xdp_stat_strs[i]);
3047 }
3048 page_pool_ethtool_stats_get_strings(data);
3049
3050 break;
3051 case ETH_SS_TEST:
3052 net_selftest_get_strings(data);
3053 break;
3054 }
3055}
3056
3057static int fec_enet_get_sset_count(struct net_device *dev, int sset)
3058{
3059 int count;
3060
3061 switch (sset) {
3062 case ETH_SS_STATS:
3063 count = ARRAY_SIZE(fec_stats) + XDP_STATS_TOTAL;
3064 count += page_pool_ethtool_stats_get_count();
3065 return count;
3066
3067 case ETH_SS_TEST:
3068 return net_selftest_get_count();
3069 default:
3070 return -EOPNOTSUPP;
3071 }
3072}
3073
3074static void fec_enet_clear_ethtool_stats(struct net_device *dev)
3075{
3076 struct fec_enet_private *fep = netdev_priv(dev);
3077 struct fec_enet_priv_rx_q *rxq;
3078 int i, j;
3079
3080 /* Disable MIB statistics counters */
3081 writel(FEC_MIB_CTRLSTAT_DISABLE, fep->hwp + FEC_MIB_CTRLSTAT);
3082
3083 for (i = 0; i < ARRAY_SIZE(fec_stats); i++)
3084 writel(0, fep->hwp + fec_stats[i].offset);
3085
3086 for (i = fep->num_rx_queues - 1; i >= 0; i--) {
3087 rxq = fep->rx_queue[i];
3088 for (j = 0; j < XDP_STATS_TOTAL; j++)
3089 rxq->stats[j] = 0;
3090 }
3091
3092 /* Don't disable MIB statistics counters */
3093 writel(0, fep->hwp + FEC_MIB_CTRLSTAT);
3094}
3095
3096#else /* !defined(CONFIG_M5272) */
3097#define FEC_STATS_SIZE 0
3098static inline void fec_enet_update_ethtool_stats(struct net_device *dev)
3099{
3100}
3101
3102static inline void fec_enet_clear_ethtool_stats(struct net_device *dev)
3103{
3104}
3105#endif /* !defined(CONFIG_M5272) */
3106
3107/* ITR clock source is enet system clock (clk_ahb).
3108 * TCTT unit is cycle_ns * 64 cycle
3109 * So, the ICTT value = X us / (cycle_ns * 64)
3110 */
3111static int fec_enet_us_to_itr_clock(struct net_device *ndev, int us)
3112{
3113 struct fec_enet_private *fep = netdev_priv(ndev);
3114
3115 return us * (fep->itr_clk_rate / 64000) / 1000;
3116}
3117
3118/* Set threshold for interrupt coalescing */
3119static void fec_enet_itr_coal_set(struct net_device *ndev)
3120{
3121 struct fec_enet_private *fep = netdev_priv(ndev);
3122 int rx_itr, tx_itr;
3123
3124 /* Must be greater than zero to avoid unpredictable behavior */
3125 if (!fep->rx_time_itr || !fep->rx_pkts_itr ||
3126 !fep->tx_time_itr || !fep->tx_pkts_itr)
3127 return;
3128
3129 /* Select enet system clock as Interrupt Coalescing
3130 * timer Clock Source
3131 */
3132 rx_itr = FEC_ITR_CLK_SEL;
3133 tx_itr = FEC_ITR_CLK_SEL;
3134
3135 /* set ICFT and ICTT */
3136 rx_itr |= FEC_ITR_ICFT(fep->rx_pkts_itr);
3137 rx_itr |= FEC_ITR_ICTT(fec_enet_us_to_itr_clock(ndev, fep->rx_time_itr));
3138 tx_itr |= FEC_ITR_ICFT(fep->tx_pkts_itr);
3139 tx_itr |= FEC_ITR_ICTT(fec_enet_us_to_itr_clock(ndev, fep->tx_time_itr));
3140
3141 rx_itr |= FEC_ITR_EN;
3142 tx_itr |= FEC_ITR_EN;
3143
3144 writel(tx_itr, fep->hwp + FEC_TXIC0);
3145 writel(rx_itr, fep->hwp + FEC_RXIC0);
3146 if (fep->quirks & FEC_QUIRK_HAS_MULTI_QUEUES) {
3147 writel(tx_itr, fep->hwp + FEC_TXIC1);
3148 writel(rx_itr, fep->hwp + FEC_RXIC1);
3149 writel(tx_itr, fep->hwp + FEC_TXIC2);
3150 writel(rx_itr, fep->hwp + FEC_RXIC2);
3151 }
3152}
3153
3154static int fec_enet_get_coalesce(struct net_device *ndev,
3155 struct ethtool_coalesce *ec,
3156 struct kernel_ethtool_coalesce *kernel_coal,
3157 struct netlink_ext_ack *extack)
3158{
3159 struct fec_enet_private *fep = netdev_priv(ndev);
3160
3161 if (!(fep->quirks & FEC_QUIRK_HAS_COALESCE))
3162 return -EOPNOTSUPP;
3163
3164 ec->rx_coalesce_usecs = fep->rx_time_itr;
3165 ec->rx_max_coalesced_frames = fep->rx_pkts_itr;
3166
3167 ec->tx_coalesce_usecs = fep->tx_time_itr;
3168 ec->tx_max_coalesced_frames = fep->tx_pkts_itr;
3169
3170 return 0;
3171}
3172
3173static int fec_enet_set_coalesce(struct net_device *ndev,
3174 struct ethtool_coalesce *ec,
3175 struct kernel_ethtool_coalesce *kernel_coal,
3176 struct netlink_ext_ack *extack)
3177{
3178 struct fec_enet_private *fep = netdev_priv(ndev);
3179 struct device *dev = &fep->pdev->dev;
3180 unsigned int cycle;
3181
3182 if (!(fep->quirks & FEC_QUIRK_HAS_COALESCE))
3183 return -EOPNOTSUPP;
3184
3185 if (ec->rx_max_coalesced_frames > 255) {
3186 dev_err(dev, "Rx coalesced frames exceed hardware limitation\n");
3187 return -EINVAL;
3188 }
3189
3190 if (ec->tx_max_coalesced_frames > 255) {
3191 dev_err(dev, "Tx coalesced frame exceed hardware limitation\n");
3192 return -EINVAL;
3193 }
3194
3195 cycle = fec_enet_us_to_itr_clock(ndev, ec->rx_coalesce_usecs);
3196 if (cycle > 0xFFFF) {
3197 dev_err(dev, "Rx coalesced usec exceed hardware limitation\n");
3198 return -EINVAL;
3199 }
3200
3201 cycle = fec_enet_us_to_itr_clock(ndev, ec->tx_coalesce_usecs);
3202 if (cycle > 0xFFFF) {
3203 dev_err(dev, "Tx coalesced usec exceed hardware limitation\n");
3204 return -EINVAL;
3205 }
3206
3207 fep->rx_time_itr = ec->rx_coalesce_usecs;
3208 fep->rx_pkts_itr = ec->rx_max_coalesced_frames;
3209
3210 fep->tx_time_itr = ec->tx_coalesce_usecs;
3211 fep->tx_pkts_itr = ec->tx_max_coalesced_frames;
3212
3213 fec_enet_itr_coal_set(ndev);
3214
3215 return 0;
3216}
3217
3218static int
3219fec_enet_get_eee(struct net_device *ndev, struct ethtool_keee *edata)
3220{
3221 struct fec_enet_private *fep = netdev_priv(ndev);
3222 struct ethtool_keee *p = &fep->eee;
3223
3224 if (!(fep->quirks & FEC_QUIRK_HAS_EEE))
3225 return -EOPNOTSUPP;
3226
3227 if (!netif_running(ndev))
3228 return -ENETDOWN;
3229
3230 edata->tx_lpi_timer = p->tx_lpi_timer;
3231
3232 return phy_ethtool_get_eee(ndev->phydev, edata);
3233}
3234
3235static int
3236fec_enet_set_eee(struct net_device *ndev, struct ethtool_keee *edata)
3237{
3238 struct fec_enet_private *fep = netdev_priv(ndev);
3239 struct ethtool_keee *p = &fep->eee;
3240
3241 if (!(fep->quirks & FEC_QUIRK_HAS_EEE))
3242 return -EOPNOTSUPP;
3243
3244 if (!netif_running(ndev))
3245 return -ENETDOWN;
3246
3247 p->tx_lpi_timer = edata->tx_lpi_timer;
3248
3249 return phy_ethtool_set_eee(ndev->phydev, edata);
3250}
3251
3252static void
3253fec_enet_get_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
3254{
3255 struct fec_enet_private *fep = netdev_priv(ndev);
3256
3257 if (fep->wol_flag & FEC_WOL_HAS_MAGIC_PACKET) {
3258 wol->supported = WAKE_MAGIC;
3259 wol->wolopts = fep->wol_flag & FEC_WOL_FLAG_ENABLE ? WAKE_MAGIC : 0;
3260 } else {
3261 wol->supported = wol->wolopts = 0;
3262 }
3263}
3264
3265static int
3266fec_enet_set_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
3267{
3268 struct fec_enet_private *fep = netdev_priv(ndev);
3269
3270 if (!(fep->wol_flag & FEC_WOL_HAS_MAGIC_PACKET))
3271 return -EINVAL;
3272
3273 if (wol->wolopts & ~WAKE_MAGIC)
3274 return -EINVAL;
3275
3276 device_set_wakeup_enable(&ndev->dev, wol->wolopts & WAKE_MAGIC);
3277 if (device_may_wakeup(&ndev->dev))
3278 fep->wol_flag |= FEC_WOL_FLAG_ENABLE;
3279 else
3280 fep->wol_flag &= (~FEC_WOL_FLAG_ENABLE);
3281
3282 return 0;
3283}
3284
3285static const struct ethtool_ops fec_enet_ethtool_ops = {
3286 .supported_coalesce_params = ETHTOOL_COALESCE_USECS |
3287 ETHTOOL_COALESCE_MAX_FRAMES,
3288 .get_drvinfo = fec_enet_get_drvinfo,
3289 .get_regs_len = fec_enet_get_regs_len,
3290 .get_regs = fec_enet_get_regs,
3291 .nway_reset = phy_ethtool_nway_reset,
3292 .get_link = ethtool_op_get_link,
3293 .get_coalesce = fec_enet_get_coalesce,
3294 .set_coalesce = fec_enet_set_coalesce,
3295#ifndef CONFIG_M5272
3296 .get_pauseparam = fec_enet_get_pauseparam,
3297 .set_pauseparam = fec_enet_set_pauseparam,
3298 .get_strings = fec_enet_get_strings,
3299 .get_ethtool_stats = fec_enet_get_ethtool_stats,
3300 .get_sset_count = fec_enet_get_sset_count,
3301#endif
3302 .get_ts_info = fec_enet_get_ts_info,
3303 .get_wol = fec_enet_get_wol,
3304 .set_wol = fec_enet_set_wol,
3305 .get_eee = fec_enet_get_eee,
3306 .set_eee = fec_enet_set_eee,
3307 .get_link_ksettings = phy_ethtool_get_link_ksettings,
3308 .set_link_ksettings = phy_ethtool_set_link_ksettings,
3309 .self_test = net_selftest,
3310};
3311
3312static void fec_enet_free_buffers(struct net_device *ndev)
3313{
3314 struct fec_enet_private *fep = netdev_priv(ndev);
3315 unsigned int i;
3316 struct fec_enet_priv_tx_q *txq;
3317 struct fec_enet_priv_rx_q *rxq;
3318 unsigned int q;
3319
3320 for (q = 0; q < fep->num_rx_queues; q++) {
3321 rxq = fep->rx_queue[q];
3322 for (i = 0; i < rxq->bd.ring_size; i++)
3323 page_pool_put_full_page(rxq->page_pool, rxq->rx_skb_info[i].page, false);
3324
3325 for (i = 0; i < XDP_STATS_TOTAL; i++)
3326 rxq->stats[i] = 0;
3327
3328 if (xdp_rxq_info_is_reg(&rxq->xdp_rxq))
3329 xdp_rxq_info_unreg(&rxq->xdp_rxq);
3330 page_pool_destroy(rxq->page_pool);
3331 rxq->page_pool = NULL;
3332 }
3333
3334 for (q = 0; q < fep->num_tx_queues; q++) {
3335 txq = fep->tx_queue[q];
3336 for (i = 0; i < txq->bd.ring_size; i++) {
3337 kfree(txq->tx_bounce[i]);
3338 txq->tx_bounce[i] = NULL;
3339
3340 if (!txq->tx_buf[i].buf_p) {
3341 txq->tx_buf[i].type = FEC_TXBUF_T_SKB;
3342 continue;
3343 }
3344
3345 if (txq->tx_buf[i].type == FEC_TXBUF_T_SKB) {
3346 dev_kfree_skb(txq->tx_buf[i].buf_p);
3347 } else if (txq->tx_buf[i].type == FEC_TXBUF_T_XDP_NDO) {
3348 xdp_return_frame(txq->tx_buf[i].buf_p);
3349 } else {
3350 struct page *page = txq->tx_buf[i].buf_p;
3351
3352 page_pool_put_page(page->pp, page, 0, false);
3353 }
3354
3355 txq->tx_buf[i].buf_p = NULL;
3356 txq->tx_buf[i].type = FEC_TXBUF_T_SKB;
3357 }
3358 }
3359}
3360
3361static void fec_enet_free_queue(struct net_device *ndev)
3362{
3363 struct fec_enet_private *fep = netdev_priv(ndev);
3364 int i;
3365 struct fec_enet_priv_tx_q *txq;
3366
3367 for (i = 0; i < fep->num_tx_queues; i++)
3368 if (fep->tx_queue[i] && fep->tx_queue[i]->tso_hdrs) {
3369 txq = fep->tx_queue[i];
3370 fec_dma_free(&fep->pdev->dev,
3371 txq->bd.ring_size * TSO_HEADER_SIZE,
3372 txq->tso_hdrs, txq->tso_hdrs_dma);
3373 }
3374
3375 for (i = 0; i < fep->num_rx_queues; i++)
3376 kfree(fep->rx_queue[i]);
3377 for (i = 0; i < fep->num_tx_queues; i++)
3378 kfree(fep->tx_queue[i]);
3379}
3380
3381static int fec_enet_alloc_queue(struct net_device *ndev)
3382{
3383 struct fec_enet_private *fep = netdev_priv(ndev);
3384 int i;
3385 int ret = 0;
3386 struct fec_enet_priv_tx_q *txq;
3387
3388 for (i = 0; i < fep->num_tx_queues; i++) {
3389 txq = kzalloc(sizeof(*txq), GFP_KERNEL);
3390 if (!txq) {
3391 ret = -ENOMEM;
3392 goto alloc_failed;
3393 }
3394
3395 fep->tx_queue[i] = txq;
3396 txq->bd.ring_size = TX_RING_SIZE;
3397 fep->total_tx_ring_size += fep->tx_queue[i]->bd.ring_size;
3398
3399 txq->tx_stop_threshold = FEC_MAX_SKB_DESCS;
3400 txq->tx_wake_threshold = FEC_MAX_SKB_DESCS + 2 * MAX_SKB_FRAGS;
3401
3402 txq->tso_hdrs = fec_dma_alloc(&fep->pdev->dev,
3403 txq->bd.ring_size * TSO_HEADER_SIZE,
3404 &txq->tso_hdrs_dma, GFP_KERNEL);
3405 if (!txq->tso_hdrs) {
3406 ret = -ENOMEM;
3407 goto alloc_failed;
3408 }
3409 }
3410
3411 for (i = 0; i < fep->num_rx_queues; i++) {
3412 fep->rx_queue[i] = kzalloc(sizeof(*fep->rx_queue[i]),
3413 GFP_KERNEL);
3414 if (!fep->rx_queue[i]) {
3415 ret = -ENOMEM;
3416 goto alloc_failed;
3417 }
3418
3419 fep->rx_queue[i]->bd.ring_size = RX_RING_SIZE;
3420 fep->total_rx_ring_size += fep->rx_queue[i]->bd.ring_size;
3421 }
3422 return ret;
3423
3424alloc_failed:
3425 fec_enet_free_queue(ndev);
3426 return ret;
3427}
3428
3429static int
3430fec_enet_alloc_rxq_buffers(struct net_device *ndev, unsigned int queue)
3431{
3432 struct fec_enet_private *fep = netdev_priv(ndev);
3433 struct fec_enet_priv_rx_q *rxq;
3434 dma_addr_t phys_addr;
3435 struct bufdesc *bdp;
3436 struct page *page;
3437 int i, err;
3438
3439 rxq = fep->rx_queue[queue];
3440 bdp = rxq->bd.base;
3441
3442 err = fec_enet_create_page_pool(fep, rxq, rxq->bd.ring_size);
3443 if (err < 0) {
3444 netdev_err(ndev, "%s failed queue %d (%d)\n", __func__, queue, err);
3445 return err;
3446 }
3447
3448 for (i = 0; i < rxq->bd.ring_size; i++) {
3449 page = page_pool_dev_alloc_pages(rxq->page_pool);
3450 if (!page)
3451 goto err_alloc;
3452
3453 phys_addr = page_pool_get_dma_addr(page) + FEC_ENET_XDP_HEADROOM;
3454 bdp->cbd_bufaddr = cpu_to_fec32(phys_addr);
3455
3456 rxq->rx_skb_info[i].page = page;
3457 rxq->rx_skb_info[i].offset = FEC_ENET_XDP_HEADROOM;
3458 bdp->cbd_sc = cpu_to_fec16(BD_ENET_RX_EMPTY);
3459
3460 if (fep->bufdesc_ex) {
3461 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
3462 ebdp->cbd_esc = cpu_to_fec32(BD_ENET_RX_INT);
3463 }
3464
3465 bdp = fec_enet_get_nextdesc(bdp, &rxq->bd);
3466 }
3467
3468 /* Set the last buffer to wrap. */
3469 bdp = fec_enet_get_prevdesc(bdp, &rxq->bd);
3470 bdp->cbd_sc |= cpu_to_fec16(BD_SC_WRAP);
3471 return 0;
3472
3473 err_alloc:
3474 fec_enet_free_buffers(ndev);
3475 return -ENOMEM;
3476}
3477
3478static int
3479fec_enet_alloc_txq_buffers(struct net_device *ndev, unsigned int queue)
3480{
3481 struct fec_enet_private *fep = netdev_priv(ndev);
3482 unsigned int i;
3483 struct bufdesc *bdp;
3484 struct fec_enet_priv_tx_q *txq;
3485
3486 txq = fep->tx_queue[queue];
3487 bdp = txq->bd.base;
3488 for (i = 0; i < txq->bd.ring_size; i++) {
3489 txq->tx_bounce[i] = kmalloc(FEC_ENET_TX_FRSIZE, GFP_KERNEL);
3490 if (!txq->tx_bounce[i])
3491 goto err_alloc;
3492
3493 bdp->cbd_sc = cpu_to_fec16(0);
3494 bdp->cbd_bufaddr = cpu_to_fec32(0);
3495
3496 if (fep->bufdesc_ex) {
3497 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
3498 ebdp->cbd_esc = cpu_to_fec32(BD_ENET_TX_INT);
3499 }
3500
3501 bdp = fec_enet_get_nextdesc(bdp, &txq->bd);
3502 }
3503
3504 /* Set the last buffer to wrap. */
3505 bdp = fec_enet_get_prevdesc(bdp, &txq->bd);
3506 bdp->cbd_sc |= cpu_to_fec16(BD_SC_WRAP);
3507
3508 return 0;
3509
3510 err_alloc:
3511 fec_enet_free_buffers(ndev);
3512 return -ENOMEM;
3513}
3514
3515static int fec_enet_alloc_buffers(struct net_device *ndev)
3516{
3517 struct fec_enet_private *fep = netdev_priv(ndev);
3518 unsigned int i;
3519
3520 for (i = 0; i < fep->num_rx_queues; i++)
3521 if (fec_enet_alloc_rxq_buffers(ndev, i))
3522 return -ENOMEM;
3523
3524 for (i = 0; i < fep->num_tx_queues; i++)
3525 if (fec_enet_alloc_txq_buffers(ndev, i))
3526 return -ENOMEM;
3527 return 0;
3528}
3529
3530static int
3531fec_enet_open(struct net_device *ndev)
3532{
3533 struct fec_enet_private *fep = netdev_priv(ndev);
3534 int ret;
3535 bool reset_again;
3536
3537 ret = pm_runtime_resume_and_get(&fep->pdev->dev);
3538 if (ret < 0)
3539 return ret;
3540
3541 pinctrl_pm_select_default_state(&fep->pdev->dev);
3542 ret = fec_enet_clk_enable(ndev, true);
3543 if (ret)
3544 goto clk_enable;
3545
3546 /* During the first fec_enet_open call the PHY isn't probed at this
3547 * point. Therefore the phy_reset_after_clk_enable() call within
3548 * fec_enet_clk_enable() fails. As we need this reset in order to be
3549 * sure the PHY is working correctly we check if we need to reset again
3550 * later when the PHY is probed
3551 */
3552 if (ndev->phydev && ndev->phydev->drv)
3553 reset_again = false;
3554 else
3555 reset_again = true;
3556
3557 /* I should reset the ring buffers here, but I don't yet know
3558 * a simple way to do that.
3559 */
3560
3561 ret = fec_enet_alloc_buffers(ndev);
3562 if (ret)
3563 goto err_enet_alloc;
3564
3565 /* Init MAC prior to mii bus probe */
3566 fec_restart(ndev);
3567
3568 /* Call phy_reset_after_clk_enable() again if it failed during
3569 * phy_reset_after_clk_enable() before because the PHY wasn't probed.
3570 */
3571 if (reset_again)
3572 fec_enet_phy_reset_after_clk_enable(ndev);
3573
3574 /* Probe and connect to PHY when open the interface */
3575 ret = fec_enet_mii_probe(ndev);
3576 if (ret)
3577 goto err_enet_mii_probe;
3578
3579 if (fep->quirks & FEC_QUIRK_ERR006687)
3580 imx6q_cpuidle_fec_irqs_used();
3581
3582 if (fep->quirks & FEC_QUIRK_HAS_PMQOS)
3583 cpu_latency_qos_add_request(&fep->pm_qos_req, 0);
3584
3585 napi_enable(&fep->napi);
3586 phy_start(ndev->phydev);
3587 netif_tx_start_all_queues(ndev);
3588
3589 device_set_wakeup_enable(&ndev->dev, fep->wol_flag &
3590 FEC_WOL_FLAG_ENABLE);
3591
3592 return 0;
3593
3594err_enet_mii_probe:
3595 fec_enet_free_buffers(ndev);
3596err_enet_alloc:
3597 fec_enet_clk_enable(ndev, false);
3598clk_enable:
3599 pm_runtime_mark_last_busy(&fep->pdev->dev);
3600 pm_runtime_put_autosuspend(&fep->pdev->dev);
3601 pinctrl_pm_select_sleep_state(&fep->pdev->dev);
3602 return ret;
3603}
3604
3605static int
3606fec_enet_close(struct net_device *ndev)
3607{
3608 struct fec_enet_private *fep = netdev_priv(ndev);
3609
3610 phy_stop(ndev->phydev);
3611
3612 if (netif_device_present(ndev)) {
3613 napi_disable(&fep->napi);
3614 netif_tx_disable(ndev);
3615 fec_stop(ndev);
3616 }
3617
3618 phy_disconnect(ndev->phydev);
3619
3620 if (fep->quirks & FEC_QUIRK_ERR006687)
3621 imx6q_cpuidle_fec_irqs_unused();
3622
3623 fec_enet_update_ethtool_stats(ndev);
3624
3625 fec_enet_clk_enable(ndev, false);
3626 if (fep->quirks & FEC_QUIRK_HAS_PMQOS)
3627 cpu_latency_qos_remove_request(&fep->pm_qos_req);
3628
3629 pinctrl_pm_select_sleep_state(&fep->pdev->dev);
3630 pm_runtime_mark_last_busy(&fep->pdev->dev);
3631 pm_runtime_put_autosuspend(&fep->pdev->dev);
3632
3633 fec_enet_free_buffers(ndev);
3634
3635 return 0;
3636}
3637
3638/* Set or clear the multicast filter for this adaptor.
3639 * Skeleton taken from sunlance driver.
3640 * The CPM Ethernet implementation allows Multicast as well as individual
3641 * MAC address filtering. Some of the drivers check to make sure it is
3642 * a group multicast address, and discard those that are not. I guess I
3643 * will do the same for now, but just remove the test if you want
3644 * individual filtering as well (do the upper net layers want or support
3645 * this kind of feature?).
3646 */
3647
3648#define FEC_HASH_BITS 6 /* #bits in hash */
3649
3650static void set_multicast_list(struct net_device *ndev)
3651{
3652 struct fec_enet_private *fep = netdev_priv(ndev);
3653 struct netdev_hw_addr *ha;
3654 unsigned int crc, tmp;
3655 unsigned char hash;
3656 unsigned int hash_high = 0, hash_low = 0;
3657
3658 if (ndev->flags & IFF_PROMISC) {
3659 tmp = readl(fep->hwp + FEC_R_CNTRL);
3660 tmp |= 0x8;
3661 writel(tmp, fep->hwp + FEC_R_CNTRL);
3662 return;
3663 }
3664
3665 tmp = readl(fep->hwp + FEC_R_CNTRL);
3666 tmp &= ~0x8;
3667 writel(tmp, fep->hwp + FEC_R_CNTRL);
3668
3669 if (ndev->flags & IFF_ALLMULTI) {
3670 /* Catch all multicast addresses, so set the
3671 * filter to all 1's
3672 */
3673 writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
3674 writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
3675
3676 return;
3677 }
3678
3679 /* Add the addresses in hash register */
3680 netdev_for_each_mc_addr(ha, ndev) {
3681 /* calculate crc32 value of mac address */
3682 crc = ether_crc_le(ndev->addr_len, ha->addr);
3683
3684 /* only upper 6 bits (FEC_HASH_BITS) are used
3685 * which point to specific bit in the hash registers
3686 */
3687 hash = (crc >> (32 - FEC_HASH_BITS)) & 0x3f;
3688
3689 if (hash > 31)
3690 hash_high |= 1 << (hash - 32);
3691 else
3692 hash_low |= 1 << hash;
3693 }
3694
3695 writel(hash_high, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
3696 writel(hash_low, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
3697}
3698
3699/* Set a MAC change in hardware. */
3700static int
3701fec_set_mac_address(struct net_device *ndev, void *p)
3702{
3703 struct fec_enet_private *fep = netdev_priv(ndev);
3704 struct sockaddr *addr = p;
3705
3706 if (addr) {
3707 if (!is_valid_ether_addr(addr->sa_data))
3708 return -EADDRNOTAVAIL;
3709 eth_hw_addr_set(ndev, addr->sa_data);
3710 }
3711
3712 /* Add netif status check here to avoid system hang in below case:
3713 * ifconfig ethx down; ifconfig ethx hw ether xx:xx:xx:xx:xx:xx;
3714 * After ethx down, fec all clocks are gated off and then register
3715 * access causes system hang.
3716 */
3717 if (!netif_running(ndev))
3718 return 0;
3719
3720 writel(ndev->dev_addr[3] | (ndev->dev_addr[2] << 8) |
3721 (ndev->dev_addr[1] << 16) | (ndev->dev_addr[0] << 24),
3722 fep->hwp + FEC_ADDR_LOW);
3723 writel((ndev->dev_addr[5] << 16) | (ndev->dev_addr[4] << 24),
3724 fep->hwp + FEC_ADDR_HIGH);
3725 return 0;
3726}
3727
3728static inline void fec_enet_set_netdev_features(struct net_device *netdev,
3729 netdev_features_t features)
3730{
3731 struct fec_enet_private *fep = netdev_priv(netdev);
3732 netdev_features_t changed = features ^ netdev->features;
3733
3734 netdev->features = features;
3735
3736 /* Receive checksum has been changed */
3737 if (changed & NETIF_F_RXCSUM) {
3738 if (features & NETIF_F_RXCSUM)
3739 fep->csum_flags |= FLAG_RX_CSUM_ENABLED;
3740 else
3741 fep->csum_flags &= ~FLAG_RX_CSUM_ENABLED;
3742 }
3743}
3744
3745static int fec_set_features(struct net_device *netdev,
3746 netdev_features_t features)
3747{
3748 struct fec_enet_private *fep = netdev_priv(netdev);
3749 netdev_features_t changed = features ^ netdev->features;
3750
3751 if (netif_running(netdev) && changed & NETIF_F_RXCSUM) {
3752 napi_disable(&fep->napi);
3753 netif_tx_lock_bh(netdev);
3754 fec_stop(netdev);
3755 fec_enet_set_netdev_features(netdev, features);
3756 fec_restart(netdev);
3757 netif_tx_wake_all_queues(netdev);
3758 netif_tx_unlock_bh(netdev);
3759 napi_enable(&fep->napi);
3760 } else {
3761 fec_enet_set_netdev_features(netdev, features);
3762 }
3763
3764 return 0;
3765}
3766
3767static u16 fec_enet_select_queue(struct net_device *ndev, struct sk_buff *skb,
3768 struct net_device *sb_dev)
3769{
3770 struct fec_enet_private *fep = netdev_priv(ndev);
3771 u16 vlan_tag = 0;
3772
3773 if (!(fep->quirks & FEC_QUIRK_HAS_AVB))
3774 return netdev_pick_tx(ndev, skb, NULL);
3775
3776 /* VLAN is present in the payload.*/
3777 if (eth_type_vlan(skb->protocol)) {
3778 struct vlan_ethhdr *vhdr = skb_vlan_eth_hdr(skb);
3779
3780 vlan_tag = ntohs(vhdr->h_vlan_TCI);
3781 /* VLAN is present in the skb but not yet pushed in the payload.*/
3782 } else if (skb_vlan_tag_present(skb)) {
3783 vlan_tag = skb->vlan_tci;
3784 } else {
3785 return vlan_tag;
3786 }
3787
3788 return fec_enet_vlan_pri_to_queue[vlan_tag >> 13];
3789}
3790
3791static int fec_enet_bpf(struct net_device *dev, struct netdev_bpf *bpf)
3792{
3793 struct fec_enet_private *fep = netdev_priv(dev);
3794 bool is_run = netif_running(dev);
3795 struct bpf_prog *old_prog;
3796
3797 switch (bpf->command) {
3798 case XDP_SETUP_PROG:
3799 /* No need to support the SoCs that require to
3800 * do the frame swap because the performance wouldn't be
3801 * better than the skb mode.
3802 */
3803 if (fep->quirks & FEC_QUIRK_SWAP_FRAME)
3804 return -EOPNOTSUPP;
3805
3806 if (!bpf->prog)
3807 xdp_features_clear_redirect_target(dev);
3808
3809 if (is_run) {
3810 napi_disable(&fep->napi);
3811 netif_tx_disable(dev);
3812 }
3813
3814 old_prog = xchg(&fep->xdp_prog, bpf->prog);
3815 if (old_prog)
3816 bpf_prog_put(old_prog);
3817
3818 fec_restart(dev);
3819
3820 if (is_run) {
3821 napi_enable(&fep->napi);
3822 netif_tx_start_all_queues(dev);
3823 }
3824
3825 if (bpf->prog)
3826 xdp_features_set_redirect_target(dev, false);
3827
3828 return 0;
3829
3830 case XDP_SETUP_XSK_POOL:
3831 return -EOPNOTSUPP;
3832
3833 default:
3834 return -EOPNOTSUPP;
3835 }
3836}
3837
3838static int
3839fec_enet_xdp_get_tx_queue(struct fec_enet_private *fep, int index)
3840{
3841 if (unlikely(index < 0))
3842 return 0;
3843
3844 return (index % fep->num_tx_queues);
3845}
3846
3847static int fec_enet_txq_xmit_frame(struct fec_enet_private *fep,
3848 struct fec_enet_priv_tx_q *txq,
3849 void *frame, u32 dma_sync_len,
3850 bool ndo_xmit)
3851{
3852 unsigned int index, status, estatus;
3853 struct bufdesc *bdp;
3854 dma_addr_t dma_addr;
3855 int entries_free;
3856 u16 frame_len;
3857
3858 entries_free = fec_enet_get_free_txdesc_num(txq);
3859 if (entries_free < MAX_SKB_FRAGS + 1) {
3860 netdev_err_once(fep->netdev, "NOT enough BD for SG!\n");
3861 return -EBUSY;
3862 }
3863
3864 /* Fill in a Tx ring entry */
3865 bdp = txq->bd.cur;
3866 status = fec16_to_cpu(bdp->cbd_sc);
3867 status &= ~BD_ENET_TX_STATS;
3868
3869 index = fec_enet_get_bd_index(bdp, &txq->bd);
3870
3871 if (ndo_xmit) {
3872 struct xdp_frame *xdpf = frame;
3873
3874 dma_addr = dma_map_single(&fep->pdev->dev, xdpf->data,
3875 xdpf->len, DMA_TO_DEVICE);
3876 if (dma_mapping_error(&fep->pdev->dev, dma_addr))
3877 return -ENOMEM;
3878
3879 frame_len = xdpf->len;
3880 txq->tx_buf[index].buf_p = xdpf;
3881 txq->tx_buf[index].type = FEC_TXBUF_T_XDP_NDO;
3882 } else {
3883 struct xdp_buff *xdpb = frame;
3884 struct page *page;
3885
3886 page = virt_to_page(xdpb->data);
3887 dma_addr = page_pool_get_dma_addr(page) +
3888 (xdpb->data - xdpb->data_hard_start);
3889 dma_sync_single_for_device(&fep->pdev->dev, dma_addr,
3890 dma_sync_len, DMA_BIDIRECTIONAL);
3891 frame_len = xdpb->data_end - xdpb->data;
3892 txq->tx_buf[index].buf_p = page;
3893 txq->tx_buf[index].type = FEC_TXBUF_T_XDP_TX;
3894 }
3895
3896 status |= (BD_ENET_TX_INTR | BD_ENET_TX_LAST);
3897 if (fep->bufdesc_ex)
3898 estatus = BD_ENET_TX_INT;
3899
3900 bdp->cbd_bufaddr = cpu_to_fec32(dma_addr);
3901 bdp->cbd_datlen = cpu_to_fec16(frame_len);
3902
3903 if (fep->bufdesc_ex) {
3904 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
3905
3906 if (fep->quirks & FEC_QUIRK_HAS_AVB)
3907 estatus |= FEC_TX_BD_FTYPE(txq->bd.qid);
3908
3909 ebdp->cbd_bdu = 0;
3910 ebdp->cbd_esc = cpu_to_fec32(estatus);
3911 }
3912
3913 /* Make sure the updates to rest of the descriptor are performed before
3914 * transferring ownership.
3915 */
3916 dma_wmb();
3917
3918 /* Send it on its way. Tell FEC it's ready, interrupt when done,
3919 * it's the last BD of the frame, and to put the CRC on the end.
3920 */
3921 status |= (BD_ENET_TX_READY | BD_ENET_TX_TC);
3922 bdp->cbd_sc = cpu_to_fec16(status);
3923
3924 /* If this was the last BD in the ring, start at the beginning again. */
3925 bdp = fec_enet_get_nextdesc(bdp, &txq->bd);
3926
3927 /* Make sure the update to bdp are performed before txq->bd.cur. */
3928 dma_wmb();
3929
3930 txq->bd.cur = bdp;
3931
3932 /* Trigger transmission start */
3933 writel(0, txq->bd.reg_desc_active);
3934
3935 return 0;
3936}
3937
3938static int fec_enet_xdp_tx_xmit(struct fec_enet_private *fep,
3939 int cpu, struct xdp_buff *xdp,
3940 u32 dma_sync_len)
3941{
3942 struct fec_enet_priv_tx_q *txq;
3943 struct netdev_queue *nq;
3944 int queue, ret;
3945
3946 queue = fec_enet_xdp_get_tx_queue(fep, cpu);
3947 txq = fep->tx_queue[queue];
3948 nq = netdev_get_tx_queue(fep->netdev, queue);
3949
3950 __netif_tx_lock(nq, cpu);
3951
3952 /* Avoid tx timeout as XDP shares the queue with kernel stack */
3953 txq_trans_cond_update(nq);
3954 ret = fec_enet_txq_xmit_frame(fep, txq, xdp, dma_sync_len, false);
3955
3956 __netif_tx_unlock(nq);
3957
3958 return ret;
3959}
3960
3961static int fec_enet_xdp_xmit(struct net_device *dev,
3962 int num_frames,
3963 struct xdp_frame **frames,
3964 u32 flags)
3965{
3966 struct fec_enet_private *fep = netdev_priv(dev);
3967 struct fec_enet_priv_tx_q *txq;
3968 int cpu = smp_processor_id();
3969 unsigned int sent_frames = 0;
3970 struct netdev_queue *nq;
3971 unsigned int queue;
3972 int i;
3973
3974 queue = fec_enet_xdp_get_tx_queue(fep, cpu);
3975 txq = fep->tx_queue[queue];
3976 nq = netdev_get_tx_queue(fep->netdev, queue);
3977
3978 __netif_tx_lock(nq, cpu);
3979
3980 /* Avoid tx timeout as XDP shares the queue with kernel stack */
3981 txq_trans_cond_update(nq);
3982 for (i = 0; i < num_frames; i++) {
3983 if (fec_enet_txq_xmit_frame(fep, txq, frames[i], 0, true) < 0)
3984 break;
3985 sent_frames++;
3986 }
3987
3988 __netif_tx_unlock(nq);
3989
3990 return sent_frames;
3991}
3992
3993static int fec_hwtstamp_get(struct net_device *ndev,
3994 struct kernel_hwtstamp_config *config)
3995{
3996 struct fec_enet_private *fep = netdev_priv(ndev);
3997
3998 if (!netif_running(ndev))
3999 return -EINVAL;
4000
4001 if (!fep->bufdesc_ex)
4002 return -EOPNOTSUPP;
4003
4004 fec_ptp_get(ndev, config);
4005
4006 return 0;
4007}
4008
4009static int fec_hwtstamp_set(struct net_device *ndev,
4010 struct kernel_hwtstamp_config *config,
4011 struct netlink_ext_ack *extack)
4012{
4013 struct fec_enet_private *fep = netdev_priv(ndev);
4014
4015 if (!netif_running(ndev))
4016 return -EINVAL;
4017
4018 if (!fep->bufdesc_ex)
4019 return -EOPNOTSUPP;
4020
4021 return fec_ptp_set(ndev, config, extack);
4022}
4023
4024static const struct net_device_ops fec_netdev_ops = {
4025 .ndo_open = fec_enet_open,
4026 .ndo_stop = fec_enet_close,
4027 .ndo_start_xmit = fec_enet_start_xmit,
4028 .ndo_select_queue = fec_enet_select_queue,
4029 .ndo_set_rx_mode = set_multicast_list,
4030 .ndo_validate_addr = eth_validate_addr,
4031 .ndo_tx_timeout = fec_timeout,
4032 .ndo_set_mac_address = fec_set_mac_address,
4033 .ndo_eth_ioctl = phy_do_ioctl_running,
4034 .ndo_set_features = fec_set_features,
4035 .ndo_bpf = fec_enet_bpf,
4036 .ndo_xdp_xmit = fec_enet_xdp_xmit,
4037 .ndo_hwtstamp_get = fec_hwtstamp_get,
4038 .ndo_hwtstamp_set = fec_hwtstamp_set,
4039};
4040
4041static const unsigned short offset_des_active_rxq[] = {
4042 FEC_R_DES_ACTIVE_0, FEC_R_DES_ACTIVE_1, FEC_R_DES_ACTIVE_2
4043};
4044
4045static const unsigned short offset_des_active_txq[] = {
4046 FEC_X_DES_ACTIVE_0, FEC_X_DES_ACTIVE_1, FEC_X_DES_ACTIVE_2
4047};
4048
4049 /*
4050 * XXX: We need to clean up on failure exits here.
4051 *
4052 */
4053static int fec_enet_init(struct net_device *ndev)
4054{
4055 struct fec_enet_private *fep = netdev_priv(ndev);
4056 struct bufdesc *cbd_base;
4057 dma_addr_t bd_dma;
4058 int bd_size;
4059 unsigned int i;
4060 unsigned dsize = fep->bufdesc_ex ? sizeof(struct bufdesc_ex) :
4061 sizeof(struct bufdesc);
4062 unsigned dsize_log2 = __fls(dsize);
4063 int ret;
4064
4065 WARN_ON(dsize != (1 << dsize_log2));
4066#if defined(CONFIG_ARM) || defined(CONFIG_ARM64)
4067 fep->rx_align = 0xf;
4068 fep->tx_align = 0xf;
4069#else
4070 fep->rx_align = 0x3;
4071 fep->tx_align = 0x3;
4072#endif
4073 fep->rx_pkts_itr = FEC_ITR_ICFT_DEFAULT;
4074 fep->tx_pkts_itr = FEC_ITR_ICFT_DEFAULT;
4075 fep->rx_time_itr = FEC_ITR_ICTT_DEFAULT;
4076 fep->tx_time_itr = FEC_ITR_ICTT_DEFAULT;
4077
4078 /* Check mask of the streaming and coherent API */
4079 ret = dma_set_mask_and_coherent(&fep->pdev->dev, DMA_BIT_MASK(32));
4080 if (ret < 0) {
4081 dev_warn(&fep->pdev->dev, "No suitable DMA available\n");
4082 return ret;
4083 }
4084
4085 ret = fec_enet_alloc_queue(ndev);
4086 if (ret)
4087 return ret;
4088
4089 bd_size = (fep->total_tx_ring_size + fep->total_rx_ring_size) * dsize;
4090
4091 /* Allocate memory for buffer descriptors. */
4092 cbd_base = fec_dmam_alloc(&fep->pdev->dev, bd_size, &bd_dma,
4093 GFP_KERNEL);
4094 if (!cbd_base) {
4095 ret = -ENOMEM;
4096 goto free_queue_mem;
4097 }
4098
4099 /* Get the Ethernet address */
4100 ret = fec_get_mac(ndev);
4101 if (ret)
4102 goto free_queue_mem;
4103
4104 /* Set receive and transmit descriptor base. */
4105 for (i = 0; i < fep->num_rx_queues; i++) {
4106 struct fec_enet_priv_rx_q *rxq = fep->rx_queue[i];
4107 unsigned size = dsize * rxq->bd.ring_size;
4108
4109 rxq->bd.qid = i;
4110 rxq->bd.base = cbd_base;
4111 rxq->bd.cur = cbd_base;
4112 rxq->bd.dma = bd_dma;
4113 rxq->bd.dsize = dsize;
4114 rxq->bd.dsize_log2 = dsize_log2;
4115 rxq->bd.reg_desc_active = fep->hwp + offset_des_active_rxq[i];
4116 bd_dma += size;
4117 cbd_base = (struct bufdesc *)(((void *)cbd_base) + size);
4118 rxq->bd.last = (struct bufdesc *)(((void *)cbd_base) - dsize);
4119 }
4120
4121 for (i = 0; i < fep->num_tx_queues; i++) {
4122 struct fec_enet_priv_tx_q *txq = fep->tx_queue[i];
4123 unsigned size = dsize * txq->bd.ring_size;
4124
4125 txq->bd.qid = i;
4126 txq->bd.base = cbd_base;
4127 txq->bd.cur = cbd_base;
4128 txq->bd.dma = bd_dma;
4129 txq->bd.dsize = dsize;
4130 txq->bd.dsize_log2 = dsize_log2;
4131 txq->bd.reg_desc_active = fep->hwp + offset_des_active_txq[i];
4132 bd_dma += size;
4133 cbd_base = (struct bufdesc *)(((void *)cbd_base) + size);
4134 txq->bd.last = (struct bufdesc *)(((void *)cbd_base) - dsize);
4135 }
4136
4137
4138 /* The FEC Ethernet specific entries in the device structure */
4139 ndev->watchdog_timeo = TX_TIMEOUT;
4140 ndev->netdev_ops = &fec_netdev_ops;
4141 ndev->ethtool_ops = &fec_enet_ethtool_ops;
4142
4143 writel(FEC_RX_DISABLED_IMASK, fep->hwp + FEC_IMASK);
4144 netif_napi_add(ndev, &fep->napi, fec_enet_rx_napi);
4145
4146 if (fep->quirks & FEC_QUIRK_HAS_VLAN)
4147 /* enable hw VLAN support */
4148 ndev->features |= NETIF_F_HW_VLAN_CTAG_RX;
4149
4150 if (fep->quirks & FEC_QUIRK_HAS_CSUM) {
4151 netif_set_tso_max_segs(ndev, FEC_MAX_TSO_SEGS);
4152
4153 /* enable hw accelerator */
4154 ndev->features |= (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM
4155 | NETIF_F_RXCSUM | NETIF_F_SG | NETIF_F_TSO);
4156 fep->csum_flags |= FLAG_RX_CSUM_ENABLED;
4157 }
4158
4159 if (fep->quirks & FEC_QUIRK_HAS_MULTI_QUEUES) {
4160 fep->tx_align = 0;
4161 fep->rx_align = 0x3f;
4162 }
4163
4164 ndev->hw_features = ndev->features;
4165
4166 if (!(fep->quirks & FEC_QUIRK_SWAP_FRAME))
4167 ndev->xdp_features = NETDEV_XDP_ACT_BASIC |
4168 NETDEV_XDP_ACT_REDIRECT;
4169
4170 fec_restart(ndev);
4171
4172 if (fep->quirks & FEC_QUIRK_MIB_CLEAR)
4173 fec_enet_clear_ethtool_stats(ndev);
4174 else
4175 fec_enet_update_ethtool_stats(ndev);
4176
4177 return 0;
4178
4179free_queue_mem:
4180 fec_enet_free_queue(ndev);
4181 return ret;
4182}
4183
4184static void fec_enet_deinit(struct net_device *ndev)
4185{
4186 struct fec_enet_private *fep = netdev_priv(ndev);
4187
4188 netif_napi_del(&fep->napi);
4189 fec_enet_free_queue(ndev);
4190}
4191
4192#ifdef CONFIG_OF
4193static int fec_reset_phy(struct platform_device *pdev)
4194{
4195 struct gpio_desc *phy_reset;
4196 int msec = 1, phy_post_delay = 0;
4197 struct device_node *np = pdev->dev.of_node;
4198 int err;
4199
4200 if (!np)
4201 return 0;
4202
4203 err = of_property_read_u32(np, "phy-reset-duration", &msec);
4204 /* A sane reset duration should not be longer than 1s */
4205 if (!err && msec > 1000)
4206 msec = 1;
4207
4208 err = of_property_read_u32(np, "phy-reset-post-delay", &phy_post_delay);
4209 /* valid reset duration should be less than 1s */
4210 if (!err && phy_post_delay > 1000)
4211 return -EINVAL;
4212
4213 phy_reset = devm_gpiod_get_optional(&pdev->dev, "phy-reset",
4214 GPIOD_OUT_HIGH);
4215 if (IS_ERR(phy_reset))
4216 return dev_err_probe(&pdev->dev, PTR_ERR(phy_reset),
4217 "failed to get phy-reset-gpios\n");
4218
4219 if (!phy_reset)
4220 return 0;
4221
4222 if (msec > 20)
4223 msleep(msec);
4224 else
4225 usleep_range(msec * 1000, msec * 1000 + 1000);
4226
4227 gpiod_set_value_cansleep(phy_reset, 0);
4228
4229 if (!phy_post_delay)
4230 return 0;
4231
4232 if (phy_post_delay > 20)
4233 msleep(phy_post_delay);
4234 else
4235 usleep_range(phy_post_delay * 1000,
4236 phy_post_delay * 1000 + 1000);
4237
4238 return 0;
4239}
4240#else /* CONFIG_OF */
4241static int fec_reset_phy(struct platform_device *pdev)
4242{
4243 /*
4244 * In case of platform probe, the reset has been done
4245 * by machine code.
4246 */
4247 return 0;
4248}
4249#endif /* CONFIG_OF */
4250
4251static void
4252fec_enet_get_queue_num(struct platform_device *pdev, int *num_tx, int *num_rx)
4253{
4254 struct device_node *np = pdev->dev.of_node;
4255
4256 *num_tx = *num_rx = 1;
4257
4258 if (!np || !of_device_is_available(np))
4259 return;
4260
4261 /* parse the num of tx and rx queues */
4262 of_property_read_u32(np, "fsl,num-tx-queues", num_tx);
4263
4264 of_property_read_u32(np, "fsl,num-rx-queues", num_rx);
4265
4266 if (*num_tx < 1 || *num_tx > FEC_ENET_MAX_TX_QS) {
4267 dev_warn(&pdev->dev, "Invalid num_tx(=%d), fall back to 1\n",
4268 *num_tx);
4269 *num_tx = 1;
4270 return;
4271 }
4272
4273 if (*num_rx < 1 || *num_rx > FEC_ENET_MAX_RX_QS) {
4274 dev_warn(&pdev->dev, "Invalid num_rx(=%d), fall back to 1\n",
4275 *num_rx);
4276 *num_rx = 1;
4277 return;
4278 }
4279
4280}
4281
4282static int fec_enet_get_irq_cnt(struct platform_device *pdev)
4283{
4284 int irq_cnt = platform_irq_count(pdev);
4285
4286 if (irq_cnt > FEC_IRQ_NUM)
4287 irq_cnt = FEC_IRQ_NUM; /* last for pps */
4288 else if (irq_cnt == 2)
4289 irq_cnt = 1; /* last for pps */
4290 else if (irq_cnt <= 0)
4291 irq_cnt = 1; /* At least 1 irq is needed */
4292 return irq_cnt;
4293}
4294
4295static void fec_enet_get_wakeup_irq(struct platform_device *pdev)
4296{
4297 struct net_device *ndev = platform_get_drvdata(pdev);
4298 struct fec_enet_private *fep = netdev_priv(ndev);
4299
4300 if (fep->quirks & FEC_QUIRK_WAKEUP_FROM_INT2)
4301 fep->wake_irq = fep->irq[2];
4302 else
4303 fep->wake_irq = fep->irq[0];
4304}
4305
4306static int fec_enet_init_stop_mode(struct fec_enet_private *fep,
4307 struct device_node *np)
4308{
4309 struct device_node *gpr_np;
4310 u32 out_val[3];
4311 int ret = 0;
4312
4313 gpr_np = of_parse_phandle(np, "fsl,stop-mode", 0);
4314 if (!gpr_np)
4315 return 0;
4316
4317 ret = of_property_read_u32_array(np, "fsl,stop-mode", out_val,
4318 ARRAY_SIZE(out_val));
4319 if (ret) {
4320 dev_dbg(&fep->pdev->dev, "no stop mode property\n");
4321 goto out;
4322 }
4323
4324 fep->stop_gpr.gpr = syscon_node_to_regmap(gpr_np);
4325 if (IS_ERR(fep->stop_gpr.gpr)) {
4326 dev_err(&fep->pdev->dev, "could not find gpr regmap\n");
4327 ret = PTR_ERR(fep->stop_gpr.gpr);
4328 fep->stop_gpr.gpr = NULL;
4329 goto out;
4330 }
4331
4332 fep->stop_gpr.reg = out_val[1];
4333 fep->stop_gpr.bit = out_val[2];
4334
4335out:
4336 of_node_put(gpr_np);
4337
4338 return ret;
4339}
4340
4341static int
4342fec_probe(struct platform_device *pdev)
4343{
4344 struct fec_enet_private *fep;
4345 struct fec_platform_data *pdata;
4346 phy_interface_t interface;
4347 struct net_device *ndev;
4348 int i, irq, ret = 0;
4349 static int dev_id;
4350 struct device_node *np = pdev->dev.of_node, *phy_node;
4351 int num_tx_qs;
4352 int num_rx_qs;
4353 char irq_name[8];
4354 int irq_cnt;
4355 const struct fec_devinfo *dev_info;
4356
4357 fec_enet_get_queue_num(pdev, &num_tx_qs, &num_rx_qs);
4358
4359 /* Init network device */
4360 ndev = alloc_etherdev_mqs(sizeof(struct fec_enet_private) +
4361 FEC_STATS_SIZE, num_tx_qs, num_rx_qs);
4362 if (!ndev)
4363 return -ENOMEM;
4364
4365 SET_NETDEV_DEV(ndev, &pdev->dev);
4366
4367 /* setup board info structure */
4368 fep = netdev_priv(ndev);
4369
4370 dev_info = device_get_match_data(&pdev->dev);
4371 if (!dev_info)
4372 dev_info = (const struct fec_devinfo *)pdev->id_entry->driver_data;
4373 if (dev_info)
4374 fep->quirks = dev_info->quirks;
4375
4376 fep->netdev = ndev;
4377 fep->num_rx_queues = num_rx_qs;
4378 fep->num_tx_queues = num_tx_qs;
4379
4380#if !defined(CONFIG_M5272)
4381 /* default enable pause frame auto negotiation */
4382 if (fep->quirks & FEC_QUIRK_HAS_GBIT)
4383 fep->pause_flag |= FEC_PAUSE_FLAG_AUTONEG;
4384#endif
4385
4386 /* Select default pin state */
4387 pinctrl_pm_select_default_state(&pdev->dev);
4388
4389 fep->hwp = devm_platform_ioremap_resource(pdev, 0);
4390 if (IS_ERR(fep->hwp)) {
4391 ret = PTR_ERR(fep->hwp);
4392 goto failed_ioremap;
4393 }
4394
4395 fep->pdev = pdev;
4396 fep->dev_id = dev_id++;
4397
4398 platform_set_drvdata(pdev, ndev);
4399
4400 if ((of_machine_is_compatible("fsl,imx6q") ||
4401 of_machine_is_compatible("fsl,imx6dl")) &&
4402 !of_property_read_bool(np, "fsl,err006687-workaround-present"))
4403 fep->quirks |= FEC_QUIRK_ERR006687;
4404
4405 ret = fec_enet_ipc_handle_init(fep);
4406 if (ret)
4407 goto failed_ipc_init;
4408
4409 if (of_property_read_bool(np, "fsl,magic-packet"))
4410 fep->wol_flag |= FEC_WOL_HAS_MAGIC_PACKET;
4411
4412 ret = fec_enet_init_stop_mode(fep, np);
4413 if (ret)
4414 goto failed_stop_mode;
4415
4416 phy_node = of_parse_phandle(np, "phy-handle", 0);
4417 if (!phy_node && of_phy_is_fixed_link(np)) {
4418 ret = of_phy_register_fixed_link(np);
4419 if (ret < 0) {
4420 dev_err(&pdev->dev,
4421 "broken fixed-link specification\n");
4422 goto failed_phy;
4423 }
4424 phy_node = of_node_get(np);
4425 }
4426 fep->phy_node = phy_node;
4427
4428 ret = of_get_phy_mode(pdev->dev.of_node, &interface);
4429 if (ret) {
4430 pdata = dev_get_platdata(&pdev->dev);
4431 if (pdata)
4432 fep->phy_interface = pdata->phy;
4433 else
4434 fep->phy_interface = PHY_INTERFACE_MODE_MII;
4435 } else {
4436 fep->phy_interface = interface;
4437 }
4438
4439 ret = fec_enet_parse_rgmii_delay(fep, np);
4440 if (ret)
4441 goto failed_rgmii_delay;
4442
4443 fep->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
4444 if (IS_ERR(fep->clk_ipg)) {
4445 ret = PTR_ERR(fep->clk_ipg);
4446 goto failed_clk;
4447 }
4448
4449 fep->clk_ahb = devm_clk_get(&pdev->dev, "ahb");
4450 if (IS_ERR(fep->clk_ahb)) {
4451 ret = PTR_ERR(fep->clk_ahb);
4452 goto failed_clk;
4453 }
4454
4455 fep->itr_clk_rate = clk_get_rate(fep->clk_ahb);
4456
4457 /* enet_out is optional, depends on board */
4458 fep->clk_enet_out = devm_clk_get_optional(&pdev->dev, "enet_out");
4459 if (IS_ERR(fep->clk_enet_out)) {
4460 ret = PTR_ERR(fep->clk_enet_out);
4461 goto failed_clk;
4462 }
4463
4464 fep->ptp_clk_on = false;
4465 mutex_init(&fep->ptp_clk_mutex);
4466
4467 /* clk_ref is optional, depends on board */
4468 fep->clk_ref = devm_clk_get_optional(&pdev->dev, "enet_clk_ref");
4469 if (IS_ERR(fep->clk_ref)) {
4470 ret = PTR_ERR(fep->clk_ref);
4471 goto failed_clk;
4472 }
4473 fep->clk_ref_rate = clk_get_rate(fep->clk_ref);
4474
4475 /* clk_2x_txclk is optional, depends on board */
4476 if (fep->rgmii_txc_dly || fep->rgmii_rxc_dly) {
4477 fep->clk_2x_txclk = devm_clk_get(&pdev->dev, "enet_2x_txclk");
4478 if (IS_ERR(fep->clk_2x_txclk))
4479 fep->clk_2x_txclk = NULL;
4480 }
4481
4482 fep->bufdesc_ex = fep->quirks & FEC_QUIRK_HAS_BUFDESC_EX;
4483 fep->clk_ptp = devm_clk_get(&pdev->dev, "ptp");
4484 if (IS_ERR(fep->clk_ptp)) {
4485 fep->clk_ptp = NULL;
4486 fep->bufdesc_ex = false;
4487 }
4488
4489 ret = fec_enet_clk_enable(ndev, true);
4490 if (ret)
4491 goto failed_clk;
4492
4493 ret = clk_prepare_enable(fep->clk_ipg);
4494 if (ret)
4495 goto failed_clk_ipg;
4496 ret = clk_prepare_enable(fep->clk_ahb);
4497 if (ret)
4498 goto failed_clk_ahb;
4499
4500 fep->reg_phy = devm_regulator_get_optional(&pdev->dev, "phy");
4501 if (!IS_ERR(fep->reg_phy)) {
4502 ret = regulator_enable(fep->reg_phy);
4503 if (ret) {
4504 dev_err(&pdev->dev,
4505 "Failed to enable phy regulator: %d\n", ret);
4506 goto failed_regulator;
4507 }
4508 } else {
4509 if (PTR_ERR(fep->reg_phy) == -EPROBE_DEFER) {
4510 ret = -EPROBE_DEFER;
4511 goto failed_regulator;
4512 }
4513 fep->reg_phy = NULL;
4514 }
4515
4516 pm_runtime_set_autosuspend_delay(&pdev->dev, FEC_MDIO_PM_TIMEOUT);
4517 pm_runtime_use_autosuspend(&pdev->dev);
4518 pm_runtime_get_noresume(&pdev->dev);
4519 pm_runtime_set_active(&pdev->dev);
4520 pm_runtime_enable(&pdev->dev);
4521
4522 ret = fec_reset_phy(pdev);
4523 if (ret)
4524 goto failed_reset;
4525
4526 irq_cnt = fec_enet_get_irq_cnt(pdev);
4527 if (fep->bufdesc_ex)
4528 fec_ptp_init(pdev, irq_cnt);
4529
4530 ret = fec_enet_init(ndev);
4531 if (ret)
4532 goto failed_init;
4533
4534 for (i = 0; i < irq_cnt; i++) {
4535 snprintf(irq_name, sizeof(irq_name), "int%d", i);
4536 irq = platform_get_irq_byname_optional(pdev, irq_name);
4537 if (irq < 0)
4538 irq = platform_get_irq(pdev, i);
4539 if (irq < 0) {
4540 ret = irq;
4541 goto failed_irq;
4542 }
4543 ret = devm_request_irq(&pdev->dev, irq, fec_enet_interrupt,
4544 0, pdev->name, ndev);
4545 if (ret)
4546 goto failed_irq;
4547
4548 fep->irq[i] = irq;
4549 }
4550
4551 /* Decide which interrupt line is wakeup capable */
4552 fec_enet_get_wakeup_irq(pdev);
4553
4554 ret = fec_enet_mii_init(pdev);
4555 if (ret)
4556 goto failed_mii_init;
4557
4558 /* Carrier starts down, phylib will bring it up */
4559 netif_carrier_off(ndev);
4560 fec_enet_clk_enable(ndev, false);
4561 pinctrl_pm_select_sleep_state(&pdev->dev);
4562
4563 ndev->max_mtu = PKT_MAXBUF_SIZE - ETH_HLEN - ETH_FCS_LEN;
4564
4565 ret = register_netdev(ndev);
4566 if (ret)
4567 goto failed_register;
4568
4569 device_init_wakeup(&ndev->dev, fep->wol_flag &
4570 FEC_WOL_HAS_MAGIC_PACKET);
4571
4572 if (fep->bufdesc_ex && fep->ptp_clock)
4573 netdev_info(ndev, "registered PHC device %d\n", fep->dev_id);
4574
4575 INIT_WORK(&fep->tx_timeout_work, fec_enet_timeout_work);
4576
4577 pm_runtime_mark_last_busy(&pdev->dev);
4578 pm_runtime_put_autosuspend(&pdev->dev);
4579
4580 return 0;
4581
4582failed_register:
4583 fec_enet_mii_remove(fep);
4584failed_mii_init:
4585failed_irq:
4586 fec_enet_deinit(ndev);
4587failed_init:
4588 fec_ptp_stop(pdev);
4589failed_reset:
4590 pm_runtime_put_noidle(&pdev->dev);
4591 pm_runtime_disable(&pdev->dev);
4592 if (fep->reg_phy)
4593 regulator_disable(fep->reg_phy);
4594failed_regulator:
4595 clk_disable_unprepare(fep->clk_ahb);
4596failed_clk_ahb:
4597 clk_disable_unprepare(fep->clk_ipg);
4598failed_clk_ipg:
4599 fec_enet_clk_enable(ndev, false);
4600failed_clk:
4601failed_rgmii_delay:
4602 if (of_phy_is_fixed_link(np))
4603 of_phy_deregister_fixed_link(np);
4604 of_node_put(phy_node);
4605failed_stop_mode:
4606failed_ipc_init:
4607failed_phy:
4608 dev_id--;
4609failed_ioremap:
4610 free_netdev(ndev);
4611
4612 return ret;
4613}
4614
4615static void
4616fec_drv_remove(struct platform_device *pdev)
4617{
4618 struct net_device *ndev = platform_get_drvdata(pdev);
4619 struct fec_enet_private *fep = netdev_priv(ndev);
4620 struct device_node *np = pdev->dev.of_node;
4621 int ret;
4622
4623 ret = pm_runtime_get_sync(&pdev->dev);
4624 if (ret < 0)
4625 dev_err(&pdev->dev,
4626 "Failed to resume device in remove callback (%pe)\n",
4627 ERR_PTR(ret));
4628
4629 cancel_work_sync(&fep->tx_timeout_work);
4630 fec_ptp_stop(pdev);
4631 unregister_netdev(ndev);
4632 fec_enet_mii_remove(fep);
4633 if (fep->reg_phy)
4634 regulator_disable(fep->reg_phy);
4635
4636 if (of_phy_is_fixed_link(np))
4637 of_phy_deregister_fixed_link(np);
4638 of_node_put(fep->phy_node);
4639
4640 /* After pm_runtime_get_sync() failed, the clks are still off, so skip
4641 * disabling them again.
4642 */
4643 if (ret >= 0) {
4644 clk_disable_unprepare(fep->clk_ahb);
4645 clk_disable_unprepare(fep->clk_ipg);
4646 }
4647 pm_runtime_put_noidle(&pdev->dev);
4648 pm_runtime_disable(&pdev->dev);
4649
4650 fec_enet_deinit(ndev);
4651 free_netdev(ndev);
4652}
4653
4654static int fec_suspend(struct device *dev)
4655{
4656 struct net_device *ndev = dev_get_drvdata(dev);
4657 struct fec_enet_private *fep = netdev_priv(ndev);
4658 int ret;
4659
4660 rtnl_lock();
4661 if (netif_running(ndev)) {
4662 if (fep->wol_flag & FEC_WOL_FLAG_ENABLE)
4663 fep->wol_flag |= FEC_WOL_FLAG_SLEEP_ON;
4664 phy_stop(ndev->phydev);
4665 napi_disable(&fep->napi);
4666 netif_tx_lock_bh(ndev);
4667 netif_device_detach(ndev);
4668 netif_tx_unlock_bh(ndev);
4669 fec_stop(ndev);
4670 if (!(fep->wol_flag & FEC_WOL_FLAG_ENABLE)) {
4671 fec_irqs_disable(ndev);
4672 pinctrl_pm_select_sleep_state(&fep->pdev->dev);
4673 } else {
4674 fec_irqs_disable_except_wakeup(ndev);
4675 if (fep->wake_irq > 0) {
4676 disable_irq(fep->wake_irq);
4677 enable_irq_wake(fep->wake_irq);
4678 }
4679 fec_enet_stop_mode(fep, true);
4680 }
4681 /* It's safe to disable clocks since interrupts are masked */
4682 fec_enet_clk_enable(ndev, false);
4683
4684 fep->rpm_active = !pm_runtime_status_suspended(dev);
4685 if (fep->rpm_active) {
4686 ret = pm_runtime_force_suspend(dev);
4687 if (ret < 0) {
4688 rtnl_unlock();
4689 return ret;
4690 }
4691 }
4692 }
4693 rtnl_unlock();
4694
4695 if (fep->reg_phy && !(fep->wol_flag & FEC_WOL_FLAG_ENABLE))
4696 regulator_disable(fep->reg_phy);
4697
4698 /* SOC supply clock to phy, when clock is disabled, phy link down
4699 * SOC control phy regulator, when regulator is disabled, phy link down
4700 */
4701 if (fep->clk_enet_out || fep->reg_phy)
4702 fep->link = 0;
4703
4704 return 0;
4705}
4706
4707static int fec_resume(struct device *dev)
4708{
4709 struct net_device *ndev = dev_get_drvdata(dev);
4710 struct fec_enet_private *fep = netdev_priv(ndev);
4711 int ret;
4712 int val;
4713
4714 if (fep->reg_phy && !(fep->wol_flag & FEC_WOL_FLAG_ENABLE)) {
4715 ret = regulator_enable(fep->reg_phy);
4716 if (ret)
4717 return ret;
4718 }
4719
4720 rtnl_lock();
4721 if (netif_running(ndev)) {
4722 if (fep->rpm_active)
4723 pm_runtime_force_resume(dev);
4724
4725 ret = fec_enet_clk_enable(ndev, true);
4726 if (ret) {
4727 rtnl_unlock();
4728 goto failed_clk;
4729 }
4730 if (fep->wol_flag & FEC_WOL_FLAG_ENABLE) {
4731 fec_enet_stop_mode(fep, false);
4732 if (fep->wake_irq) {
4733 disable_irq_wake(fep->wake_irq);
4734 enable_irq(fep->wake_irq);
4735 }
4736
4737 val = readl(fep->hwp + FEC_ECNTRL);
4738 val &= ~(FEC_ECR_MAGICEN | FEC_ECR_SLEEP);
4739 writel(val, fep->hwp + FEC_ECNTRL);
4740 fep->wol_flag &= ~FEC_WOL_FLAG_SLEEP_ON;
4741 } else {
4742 pinctrl_pm_select_default_state(&fep->pdev->dev);
4743 }
4744 fec_restart(ndev);
4745 netif_tx_lock_bh(ndev);
4746 netif_device_attach(ndev);
4747 netif_tx_unlock_bh(ndev);
4748 napi_enable(&fep->napi);
4749 phy_init_hw(ndev->phydev);
4750 phy_start(ndev->phydev);
4751 }
4752 rtnl_unlock();
4753
4754 return 0;
4755
4756failed_clk:
4757 if (fep->reg_phy)
4758 regulator_disable(fep->reg_phy);
4759 return ret;
4760}
4761
4762static int fec_runtime_suspend(struct device *dev)
4763{
4764 struct net_device *ndev = dev_get_drvdata(dev);
4765 struct fec_enet_private *fep = netdev_priv(ndev);
4766
4767 clk_disable_unprepare(fep->clk_ahb);
4768 clk_disable_unprepare(fep->clk_ipg);
4769
4770 return 0;
4771}
4772
4773static int fec_runtime_resume(struct device *dev)
4774{
4775 struct net_device *ndev = dev_get_drvdata(dev);
4776 struct fec_enet_private *fep = netdev_priv(ndev);
4777 int ret;
4778
4779 ret = clk_prepare_enable(fep->clk_ahb);
4780 if (ret)
4781 return ret;
4782 ret = clk_prepare_enable(fep->clk_ipg);
4783 if (ret)
4784 goto failed_clk_ipg;
4785
4786 return 0;
4787
4788failed_clk_ipg:
4789 clk_disable_unprepare(fep->clk_ahb);
4790 return ret;
4791}
4792
4793static const struct dev_pm_ops fec_pm_ops = {
4794 SYSTEM_SLEEP_PM_OPS(fec_suspend, fec_resume)
4795 RUNTIME_PM_OPS(fec_runtime_suspend, fec_runtime_resume, NULL)
4796};
4797
4798static struct platform_driver fec_driver = {
4799 .driver = {
4800 .name = DRIVER_NAME,
4801 .pm = pm_ptr(&fec_pm_ops),
4802 .of_match_table = fec_dt_ids,
4803 .suppress_bind_attrs = true,
4804 },
4805 .id_table = fec_devtype,
4806 .probe = fec_probe,
4807 .remove = fec_drv_remove,
4808};
4809
4810module_platform_driver(fec_driver);
4811
4812MODULE_DESCRIPTION("NXP Fast Ethernet Controller (FEC) driver");
4813MODULE_LICENSE("GPL");
1/*
2 * Fast Ethernet Controller (FEC) driver for Motorola MPC8xx.
3 * Copyright (c) 1997 Dan Malek (dmalek@jlc.net)
4 *
5 * Right now, I am very wasteful with the buffers. I allocate memory
6 * pages and then divide them into 2K frame buffers. This way I know I
7 * have buffers large enough to hold one frame within one buffer descriptor.
8 * Once I get this working, I will use 64 or 128 byte CPM buffers, which
9 * will be much more memory efficient and will easily handle lots of
10 * small packets.
11 *
12 * Much better multiple PHY support by Magnus Damm.
13 * Copyright (c) 2000 Ericsson Radio Systems AB.
14 *
15 * Support for FEC controller of ColdFire processors.
16 * Copyright (c) 2001-2005 Greg Ungerer (gerg@snapgear.com)
17 *
18 * Bug fixes and cleanup by Philippe De Muyter (phdm@macqel.be)
19 * Copyright (c) 2004-2006 Macq Electronique SA.
20 *
21 * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
22 */
23
24#include <linux/module.h>
25#include <linux/kernel.h>
26#include <linux/string.h>
27#include <linux/ptrace.h>
28#include <linux/errno.h>
29#include <linux/ioport.h>
30#include <linux/slab.h>
31#include <linux/interrupt.h>
32#include <linux/delay.h>
33#include <linux/netdevice.h>
34#include <linux/etherdevice.h>
35#include <linux/skbuff.h>
36#include <linux/in.h>
37#include <linux/ip.h>
38#include <net/ip.h>
39#include <linux/tcp.h>
40#include <linux/udp.h>
41#include <linux/icmp.h>
42#include <linux/spinlock.h>
43#include <linux/workqueue.h>
44#include <linux/bitops.h>
45#include <linux/io.h>
46#include <linux/irq.h>
47#include <linux/clk.h>
48#include <linux/platform_device.h>
49#include <linux/phy.h>
50#include <linux/fec.h>
51#include <linux/of.h>
52#include <linux/of_device.h>
53#include <linux/of_gpio.h>
54#include <linux/of_net.h>
55#include <linux/regulator/consumer.h>
56#include <linux/if_vlan.h>
57
58#include <asm/cacheflush.h>
59
60#include "fec.h"
61
62static void set_multicast_list(struct net_device *ndev);
63
64#if defined(CONFIG_ARM)
65#define FEC_ALIGNMENT 0xf
66#else
67#define FEC_ALIGNMENT 0x3
68#endif
69
70#define DRIVER_NAME "fec"
71
72/* Pause frame feild and FIFO threshold */
73#define FEC_ENET_FCE (1 << 5)
74#define FEC_ENET_RSEM_V 0x84
75#define FEC_ENET_RSFL_V 16
76#define FEC_ENET_RAEM_V 0x8
77#define FEC_ENET_RAFL_V 0x8
78#define FEC_ENET_OPD_V 0xFFF0
79
80/* Controller is ENET-MAC */
81#define FEC_QUIRK_ENET_MAC (1 << 0)
82/* Controller needs driver to swap frame */
83#define FEC_QUIRK_SWAP_FRAME (1 << 1)
84/* Controller uses gasket */
85#define FEC_QUIRK_USE_GASKET (1 << 2)
86/* Controller has GBIT support */
87#define FEC_QUIRK_HAS_GBIT (1 << 3)
88/* Controller has extend desc buffer */
89#define FEC_QUIRK_HAS_BUFDESC_EX (1 << 4)
90/* Controller has hardware checksum support */
91#define FEC_QUIRK_HAS_CSUM (1 << 5)
92/* Controller has hardware vlan support */
93#define FEC_QUIRK_HAS_VLAN (1 << 6)
94/* ENET IP errata ERR006358
95 *
96 * If the ready bit in the transmit buffer descriptor (TxBD[R]) is previously
97 * detected as not set during a prior frame transmission, then the
98 * ENET_TDAR[TDAR] bit is cleared at a later time, even if additional TxBDs
99 * were added to the ring and the ENET_TDAR[TDAR] bit is set. This results in
100 * frames not being transmitted until there is a 0-to-1 transition on
101 * ENET_TDAR[TDAR].
102 */
103#define FEC_QUIRK_ERR006358 (1 << 7)
104
105static struct platform_device_id fec_devtype[] = {
106 {
107 /* keep it for coldfire */
108 .name = DRIVER_NAME,
109 .driver_data = 0,
110 }, {
111 .name = "imx25-fec",
112 .driver_data = FEC_QUIRK_USE_GASKET,
113 }, {
114 .name = "imx27-fec",
115 .driver_data = 0,
116 }, {
117 .name = "imx28-fec",
118 .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_SWAP_FRAME,
119 }, {
120 .name = "imx6q-fec",
121 .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT |
122 FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM |
123 FEC_QUIRK_HAS_VLAN | FEC_QUIRK_ERR006358,
124 }, {
125 .name = "mvf600-fec",
126 .driver_data = FEC_QUIRK_ENET_MAC,
127 }, {
128 /* sentinel */
129 }
130};
131MODULE_DEVICE_TABLE(platform, fec_devtype);
132
133enum imx_fec_type {
134 IMX25_FEC = 1, /* runs on i.mx25/50/53 */
135 IMX27_FEC, /* runs on i.mx27/35/51 */
136 IMX28_FEC,
137 IMX6Q_FEC,
138 MVF600_FEC,
139};
140
141static const struct of_device_id fec_dt_ids[] = {
142 { .compatible = "fsl,imx25-fec", .data = &fec_devtype[IMX25_FEC], },
143 { .compatible = "fsl,imx27-fec", .data = &fec_devtype[IMX27_FEC], },
144 { .compatible = "fsl,imx28-fec", .data = &fec_devtype[IMX28_FEC], },
145 { .compatible = "fsl,imx6q-fec", .data = &fec_devtype[IMX6Q_FEC], },
146 { .compatible = "fsl,mvf600-fec", .data = &fec_devtype[MVF600_FEC], },
147 { /* sentinel */ }
148};
149MODULE_DEVICE_TABLE(of, fec_dt_ids);
150
151static unsigned char macaddr[ETH_ALEN];
152module_param_array(macaddr, byte, NULL, 0);
153MODULE_PARM_DESC(macaddr, "FEC Ethernet MAC address");
154
155#if defined(CONFIG_M5272)
156/*
157 * Some hardware gets it MAC address out of local flash memory.
158 * if this is non-zero then assume it is the address to get MAC from.
159 */
160#if defined(CONFIG_NETtel)
161#define FEC_FLASHMAC 0xf0006006
162#elif defined(CONFIG_GILBARCONAP) || defined(CONFIG_SCALES)
163#define FEC_FLASHMAC 0xf0006000
164#elif defined(CONFIG_CANCam)
165#define FEC_FLASHMAC 0xf0020000
166#elif defined (CONFIG_M5272C3)
167#define FEC_FLASHMAC (0xffe04000 + 4)
168#elif defined(CONFIG_MOD5272)
169#define FEC_FLASHMAC 0xffc0406b
170#else
171#define FEC_FLASHMAC 0
172#endif
173#endif /* CONFIG_M5272 */
174
175#if (((RX_RING_SIZE + TX_RING_SIZE) * 32) > PAGE_SIZE)
176#error "FEC: descriptor ring size constants too large"
177#endif
178
179/* Interrupt events/masks. */
180#define FEC_ENET_HBERR ((uint)0x80000000) /* Heartbeat error */
181#define FEC_ENET_BABR ((uint)0x40000000) /* Babbling receiver */
182#define FEC_ENET_BABT ((uint)0x20000000) /* Babbling transmitter */
183#define FEC_ENET_GRA ((uint)0x10000000) /* Graceful stop complete */
184#define FEC_ENET_TXF ((uint)0x08000000) /* Full frame transmitted */
185#define FEC_ENET_TXB ((uint)0x04000000) /* A buffer was transmitted */
186#define FEC_ENET_RXF ((uint)0x02000000) /* Full frame received */
187#define FEC_ENET_RXB ((uint)0x01000000) /* A buffer was received */
188#define FEC_ENET_MII ((uint)0x00800000) /* MII interrupt */
189#define FEC_ENET_EBERR ((uint)0x00400000) /* SDMA bus error */
190
191#define FEC_DEFAULT_IMASK (FEC_ENET_TXF | FEC_ENET_RXF | FEC_ENET_MII)
192#define FEC_RX_DISABLED_IMASK (FEC_DEFAULT_IMASK & (~FEC_ENET_RXF))
193
194/* The FEC stores dest/src/type/vlan, data, and checksum for receive packets.
195 */
196#define PKT_MAXBUF_SIZE 1522
197#define PKT_MINBUF_SIZE 64
198#define PKT_MAXBLR_SIZE 1536
199
200/* FEC receive acceleration */
201#define FEC_RACC_IPDIS (1 << 1)
202#define FEC_RACC_PRODIS (1 << 2)
203#define FEC_RACC_OPTIONS (FEC_RACC_IPDIS | FEC_RACC_PRODIS)
204
205/*
206 * The 5270/5271/5280/5282/532x RX control register also contains maximum frame
207 * size bits. Other FEC hardware does not, so we need to take that into
208 * account when setting it.
209 */
210#if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
211 defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_ARM)
212#define OPT_FRAME_SIZE (PKT_MAXBUF_SIZE << 16)
213#else
214#define OPT_FRAME_SIZE 0
215#endif
216
217/* FEC MII MMFR bits definition */
218#define FEC_MMFR_ST (1 << 30)
219#define FEC_MMFR_OP_READ (2 << 28)
220#define FEC_MMFR_OP_WRITE (1 << 28)
221#define FEC_MMFR_PA(v) ((v & 0x1f) << 23)
222#define FEC_MMFR_RA(v) ((v & 0x1f) << 18)
223#define FEC_MMFR_TA (2 << 16)
224#define FEC_MMFR_DATA(v) (v & 0xffff)
225
226#define FEC_MII_TIMEOUT 30000 /* us */
227
228/* Transmitter timeout */
229#define TX_TIMEOUT (2 * HZ)
230
231#define FEC_PAUSE_FLAG_AUTONEG 0x1
232#define FEC_PAUSE_FLAG_ENABLE 0x2
233
234static int mii_cnt;
235
236static inline
237struct bufdesc *fec_enet_get_nextdesc(struct bufdesc *bdp, struct fec_enet_private *fep)
238{
239 struct bufdesc *new_bd = bdp + 1;
240 struct bufdesc_ex *ex_new_bd = (struct bufdesc_ex *)bdp + 1;
241 struct bufdesc_ex *ex_base;
242 struct bufdesc *base;
243 int ring_size;
244
245 if (bdp >= fep->tx_bd_base) {
246 base = fep->tx_bd_base;
247 ring_size = fep->tx_ring_size;
248 ex_base = (struct bufdesc_ex *)fep->tx_bd_base;
249 } else {
250 base = fep->rx_bd_base;
251 ring_size = fep->rx_ring_size;
252 ex_base = (struct bufdesc_ex *)fep->rx_bd_base;
253 }
254
255 if (fep->bufdesc_ex)
256 return (struct bufdesc *)((ex_new_bd >= (ex_base + ring_size)) ?
257 ex_base : ex_new_bd);
258 else
259 return (new_bd >= (base + ring_size)) ?
260 base : new_bd;
261}
262
263static inline
264struct bufdesc *fec_enet_get_prevdesc(struct bufdesc *bdp, struct fec_enet_private *fep)
265{
266 struct bufdesc *new_bd = bdp - 1;
267 struct bufdesc_ex *ex_new_bd = (struct bufdesc_ex *)bdp - 1;
268 struct bufdesc_ex *ex_base;
269 struct bufdesc *base;
270 int ring_size;
271
272 if (bdp >= fep->tx_bd_base) {
273 base = fep->tx_bd_base;
274 ring_size = fep->tx_ring_size;
275 ex_base = (struct bufdesc_ex *)fep->tx_bd_base;
276 } else {
277 base = fep->rx_bd_base;
278 ring_size = fep->rx_ring_size;
279 ex_base = (struct bufdesc_ex *)fep->rx_bd_base;
280 }
281
282 if (fep->bufdesc_ex)
283 return (struct bufdesc *)((ex_new_bd < ex_base) ?
284 (ex_new_bd + ring_size) : ex_new_bd);
285 else
286 return (new_bd < base) ? (new_bd + ring_size) : new_bd;
287}
288
289static void *swap_buffer(void *bufaddr, int len)
290{
291 int i;
292 unsigned int *buf = bufaddr;
293
294 for (i = 0; i < DIV_ROUND_UP(len, 4); i++, buf++)
295 *buf = cpu_to_be32(*buf);
296
297 return bufaddr;
298}
299
300static int
301fec_enet_clear_csum(struct sk_buff *skb, struct net_device *ndev)
302{
303 /* Only run for packets requiring a checksum. */
304 if (skb->ip_summed != CHECKSUM_PARTIAL)
305 return 0;
306
307 if (unlikely(skb_cow_head(skb, 0)))
308 return -1;
309
310 *(__sum16 *)(skb->head + skb->csum_start + skb->csum_offset) = 0;
311
312 return 0;
313}
314
315static netdev_tx_t
316fec_enet_start_xmit(struct sk_buff *skb, struct net_device *ndev)
317{
318 struct fec_enet_private *fep = netdev_priv(ndev);
319 const struct platform_device_id *id_entry =
320 platform_get_device_id(fep->pdev);
321 struct bufdesc *bdp, *bdp_pre;
322 void *bufaddr;
323 unsigned short status;
324 unsigned int index;
325
326 /* Fill in a Tx ring entry */
327 bdp = fep->cur_tx;
328
329 status = bdp->cbd_sc;
330
331 if (status & BD_ENET_TX_READY) {
332 /* Ooops. All transmit buffers are full. Bail out.
333 * This should not happen, since ndev->tbusy should be set.
334 */
335 netdev_err(ndev, "tx queue full!\n");
336 return NETDEV_TX_BUSY;
337 }
338
339 /* Protocol checksum off-load for TCP and UDP. */
340 if (fec_enet_clear_csum(skb, ndev)) {
341 dev_kfree_skb_any(skb);
342 return NETDEV_TX_OK;
343 }
344
345 /* Clear all of the status flags */
346 status &= ~BD_ENET_TX_STATS;
347
348 /* Set buffer length and buffer pointer */
349 bufaddr = skb->data;
350 bdp->cbd_datlen = skb->len;
351
352 /*
353 * On some FEC implementations data must be aligned on
354 * 4-byte boundaries. Use bounce buffers to copy data
355 * and get it aligned. Ugh.
356 */
357 if (fep->bufdesc_ex)
358 index = (struct bufdesc_ex *)bdp -
359 (struct bufdesc_ex *)fep->tx_bd_base;
360 else
361 index = bdp - fep->tx_bd_base;
362
363 if (((unsigned long) bufaddr) & FEC_ALIGNMENT) {
364 memcpy(fep->tx_bounce[index], skb->data, skb->len);
365 bufaddr = fep->tx_bounce[index];
366 }
367
368 /*
369 * Some design made an incorrect assumption on endian mode of
370 * the system that it's running on. As the result, driver has to
371 * swap every frame going to and coming from the controller.
372 */
373 if (id_entry->driver_data & FEC_QUIRK_SWAP_FRAME)
374 swap_buffer(bufaddr, skb->len);
375
376 /* Save skb pointer */
377 fep->tx_skbuff[index] = skb;
378
379 /* Push the data cache so the CPM does not get stale memory
380 * data.
381 */
382 bdp->cbd_bufaddr = dma_map_single(&fep->pdev->dev, bufaddr,
383 skb->len, DMA_TO_DEVICE);
384 if (dma_mapping_error(&fep->pdev->dev, bdp->cbd_bufaddr)) {
385 bdp->cbd_bufaddr = 0;
386 fep->tx_skbuff[index] = NULL;
387 dev_kfree_skb_any(skb);
388 if (net_ratelimit())
389 netdev_err(ndev, "Tx DMA memory map failed\n");
390 return NETDEV_TX_OK;
391 }
392
393 if (fep->bufdesc_ex) {
394
395 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
396 ebdp->cbd_bdu = 0;
397 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP &&
398 fep->hwts_tx_en)) {
399 ebdp->cbd_esc = (BD_ENET_TX_TS | BD_ENET_TX_INT);
400 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
401 } else {
402 ebdp->cbd_esc = BD_ENET_TX_INT;
403
404 /* Enable protocol checksum flags
405 * We do not bother with the IP Checksum bits as they
406 * are done by the kernel
407 */
408 if (skb->ip_summed == CHECKSUM_PARTIAL)
409 ebdp->cbd_esc |= BD_ENET_TX_PINS;
410 }
411 }
412
413 /* Send it on its way. Tell FEC it's ready, interrupt when done,
414 * it's the last BD of the frame, and to put the CRC on the end.
415 */
416 status |= (BD_ENET_TX_READY | BD_ENET_TX_INTR
417 | BD_ENET_TX_LAST | BD_ENET_TX_TC);
418 bdp->cbd_sc = status;
419
420 bdp_pre = fec_enet_get_prevdesc(bdp, fep);
421 if ((id_entry->driver_data & FEC_QUIRK_ERR006358) &&
422 !(bdp_pre->cbd_sc & BD_ENET_TX_READY)) {
423 fep->delay_work.trig_tx = true;
424 schedule_delayed_work(&(fep->delay_work.delay_work),
425 msecs_to_jiffies(1));
426 }
427
428 /* If this was the last BD in the ring, start at the beginning again. */
429 bdp = fec_enet_get_nextdesc(bdp, fep);
430
431 skb_tx_timestamp(skb);
432
433 fep->cur_tx = bdp;
434
435 if (fep->cur_tx == fep->dirty_tx)
436 netif_stop_queue(ndev);
437
438 /* Trigger transmission start */
439 writel(0, fep->hwp + FEC_X_DES_ACTIVE);
440
441 return NETDEV_TX_OK;
442}
443
444/* Init RX & TX buffer descriptors
445 */
446static void fec_enet_bd_init(struct net_device *dev)
447{
448 struct fec_enet_private *fep = netdev_priv(dev);
449 struct bufdesc *bdp;
450 unsigned int i;
451
452 /* Initialize the receive buffer descriptors. */
453 bdp = fep->rx_bd_base;
454 for (i = 0; i < fep->rx_ring_size; i++) {
455
456 /* Initialize the BD for every fragment in the page. */
457 if (bdp->cbd_bufaddr)
458 bdp->cbd_sc = BD_ENET_RX_EMPTY;
459 else
460 bdp->cbd_sc = 0;
461 bdp = fec_enet_get_nextdesc(bdp, fep);
462 }
463
464 /* Set the last buffer to wrap */
465 bdp = fec_enet_get_prevdesc(bdp, fep);
466 bdp->cbd_sc |= BD_SC_WRAP;
467
468 fep->cur_rx = fep->rx_bd_base;
469
470 /* ...and the same for transmit */
471 bdp = fep->tx_bd_base;
472 fep->cur_tx = bdp;
473 for (i = 0; i < fep->tx_ring_size; i++) {
474
475 /* Initialize the BD for every fragment in the page. */
476 bdp->cbd_sc = 0;
477 if (bdp->cbd_bufaddr && fep->tx_skbuff[i]) {
478 dev_kfree_skb_any(fep->tx_skbuff[i]);
479 fep->tx_skbuff[i] = NULL;
480 }
481 bdp->cbd_bufaddr = 0;
482 bdp = fec_enet_get_nextdesc(bdp, fep);
483 }
484
485 /* Set the last buffer to wrap */
486 bdp = fec_enet_get_prevdesc(bdp, fep);
487 bdp->cbd_sc |= BD_SC_WRAP;
488 fep->dirty_tx = bdp;
489}
490
491/* This function is called to start or restart the FEC during a link
492 * change. This only happens when switching between half and full
493 * duplex.
494 */
495static void
496fec_restart(struct net_device *ndev, int duplex)
497{
498 struct fec_enet_private *fep = netdev_priv(ndev);
499 const struct platform_device_id *id_entry =
500 platform_get_device_id(fep->pdev);
501 int i;
502 u32 val;
503 u32 temp_mac[2];
504 u32 rcntl = OPT_FRAME_SIZE | 0x04;
505 u32 ecntl = 0x2; /* ETHEREN */
506
507 if (netif_running(ndev)) {
508 netif_device_detach(ndev);
509 napi_disable(&fep->napi);
510 netif_stop_queue(ndev);
511 netif_tx_lock_bh(ndev);
512 }
513
514 /* Whack a reset. We should wait for this. */
515 writel(1, fep->hwp + FEC_ECNTRL);
516 udelay(10);
517
518 /*
519 * enet-mac reset will reset mac address registers too,
520 * so need to reconfigure it.
521 */
522 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) {
523 memcpy(&temp_mac, ndev->dev_addr, ETH_ALEN);
524 writel(cpu_to_be32(temp_mac[0]), fep->hwp + FEC_ADDR_LOW);
525 writel(cpu_to_be32(temp_mac[1]), fep->hwp + FEC_ADDR_HIGH);
526 }
527
528 /* Clear any outstanding interrupt. */
529 writel(0xffc00000, fep->hwp + FEC_IEVENT);
530
531 /* Set maximum receive buffer size. */
532 writel(PKT_MAXBLR_SIZE, fep->hwp + FEC_R_BUFF_SIZE);
533
534 fec_enet_bd_init(ndev);
535
536 /* Set receive and transmit descriptor base. */
537 writel(fep->bd_dma, fep->hwp + FEC_R_DES_START);
538 if (fep->bufdesc_ex)
539 writel((unsigned long)fep->bd_dma + sizeof(struct bufdesc_ex)
540 * fep->rx_ring_size, fep->hwp + FEC_X_DES_START);
541 else
542 writel((unsigned long)fep->bd_dma + sizeof(struct bufdesc)
543 * fep->rx_ring_size, fep->hwp + FEC_X_DES_START);
544
545
546 for (i = 0; i <= TX_RING_MOD_MASK; i++) {
547 if (fep->tx_skbuff[i]) {
548 dev_kfree_skb_any(fep->tx_skbuff[i]);
549 fep->tx_skbuff[i] = NULL;
550 }
551 }
552
553 /* Enable MII mode */
554 if (duplex) {
555 /* FD enable */
556 writel(0x04, fep->hwp + FEC_X_CNTRL);
557 } else {
558 /* No Rcv on Xmit */
559 rcntl |= 0x02;
560 writel(0x0, fep->hwp + FEC_X_CNTRL);
561 }
562
563 fep->full_duplex = duplex;
564
565 /* Set MII speed */
566 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
567
568#if !defined(CONFIG_M5272)
569 /* set RX checksum */
570 val = readl(fep->hwp + FEC_RACC);
571 if (fep->csum_flags & FLAG_RX_CSUM_ENABLED)
572 val |= FEC_RACC_OPTIONS;
573 else
574 val &= ~FEC_RACC_OPTIONS;
575 writel(val, fep->hwp + FEC_RACC);
576#endif
577
578 /*
579 * The phy interface and speed need to get configured
580 * differently on enet-mac.
581 */
582 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) {
583 /* Enable flow control and length check */
584 rcntl |= 0x40000000 | 0x00000020;
585
586 /* RGMII, RMII or MII */
587 if (fep->phy_interface == PHY_INTERFACE_MODE_RGMII)
588 rcntl |= (1 << 6);
589 else if (fep->phy_interface == PHY_INTERFACE_MODE_RMII)
590 rcntl |= (1 << 8);
591 else
592 rcntl &= ~(1 << 8);
593
594 /* 1G, 100M or 10M */
595 if (fep->phy_dev) {
596 if (fep->phy_dev->speed == SPEED_1000)
597 ecntl |= (1 << 5);
598 else if (fep->phy_dev->speed == SPEED_100)
599 rcntl &= ~(1 << 9);
600 else
601 rcntl |= (1 << 9);
602 }
603 } else {
604#ifdef FEC_MIIGSK_ENR
605 if (id_entry->driver_data & FEC_QUIRK_USE_GASKET) {
606 u32 cfgr;
607 /* disable the gasket and wait */
608 writel(0, fep->hwp + FEC_MIIGSK_ENR);
609 while (readl(fep->hwp + FEC_MIIGSK_ENR) & 4)
610 udelay(1);
611
612 /*
613 * configure the gasket:
614 * RMII, 50 MHz, no loopback, no echo
615 * MII, 25 MHz, no loopback, no echo
616 */
617 cfgr = (fep->phy_interface == PHY_INTERFACE_MODE_RMII)
618 ? BM_MIIGSK_CFGR_RMII : BM_MIIGSK_CFGR_MII;
619 if (fep->phy_dev && fep->phy_dev->speed == SPEED_10)
620 cfgr |= BM_MIIGSK_CFGR_FRCONT_10M;
621 writel(cfgr, fep->hwp + FEC_MIIGSK_CFGR);
622
623 /* re-enable the gasket */
624 writel(2, fep->hwp + FEC_MIIGSK_ENR);
625 }
626#endif
627 }
628
629#if !defined(CONFIG_M5272)
630 /* enable pause frame*/
631 if ((fep->pause_flag & FEC_PAUSE_FLAG_ENABLE) ||
632 ((fep->pause_flag & FEC_PAUSE_FLAG_AUTONEG) &&
633 fep->phy_dev && fep->phy_dev->pause)) {
634 rcntl |= FEC_ENET_FCE;
635
636 /* set FIFO threshold parameter to reduce overrun */
637 writel(FEC_ENET_RSEM_V, fep->hwp + FEC_R_FIFO_RSEM);
638 writel(FEC_ENET_RSFL_V, fep->hwp + FEC_R_FIFO_RSFL);
639 writel(FEC_ENET_RAEM_V, fep->hwp + FEC_R_FIFO_RAEM);
640 writel(FEC_ENET_RAFL_V, fep->hwp + FEC_R_FIFO_RAFL);
641
642 /* OPD */
643 writel(FEC_ENET_OPD_V, fep->hwp + FEC_OPD);
644 } else {
645 rcntl &= ~FEC_ENET_FCE;
646 }
647#endif /* !defined(CONFIG_M5272) */
648
649 writel(rcntl, fep->hwp + FEC_R_CNTRL);
650
651 /* Setup multicast filter. */
652 set_multicast_list(ndev);
653#ifndef CONFIG_M5272
654 writel(0, fep->hwp + FEC_HASH_TABLE_HIGH);
655 writel(0, fep->hwp + FEC_HASH_TABLE_LOW);
656#endif
657
658 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) {
659 /* enable ENET endian swap */
660 ecntl |= (1 << 8);
661 /* enable ENET store and forward mode */
662 writel(1 << 8, fep->hwp + FEC_X_WMRK);
663 }
664
665 if (fep->bufdesc_ex)
666 ecntl |= (1 << 4);
667
668#ifndef CONFIG_M5272
669 /* Enable the MIB statistic event counters */
670 writel(0 << 31, fep->hwp + FEC_MIB_CTRLSTAT);
671#endif
672
673 /* And last, enable the transmit and receive processing */
674 writel(ecntl, fep->hwp + FEC_ECNTRL);
675 writel(0, fep->hwp + FEC_R_DES_ACTIVE);
676
677 if (fep->bufdesc_ex)
678 fec_ptp_start_cyclecounter(ndev);
679
680 /* Enable interrupts we wish to service */
681 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK);
682
683 if (netif_running(ndev)) {
684 netif_tx_unlock_bh(ndev);
685 netif_wake_queue(ndev);
686 napi_enable(&fep->napi);
687 netif_device_attach(ndev);
688 }
689}
690
691static void
692fec_stop(struct net_device *ndev)
693{
694 struct fec_enet_private *fep = netdev_priv(ndev);
695 const struct platform_device_id *id_entry =
696 platform_get_device_id(fep->pdev);
697 u32 rmii_mode = readl(fep->hwp + FEC_R_CNTRL) & (1 << 8);
698
699 /* We cannot expect a graceful transmit stop without link !!! */
700 if (fep->link) {
701 writel(1, fep->hwp + FEC_X_CNTRL); /* Graceful transmit stop */
702 udelay(10);
703 if (!(readl(fep->hwp + FEC_IEVENT) & FEC_ENET_GRA))
704 netdev_err(ndev, "Graceful transmit stop did not complete!\n");
705 }
706
707 /* Whack a reset. We should wait for this. */
708 writel(1, fep->hwp + FEC_ECNTRL);
709 udelay(10);
710 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
711 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK);
712
713 /* We have to keep ENET enabled to have MII interrupt stay working */
714 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) {
715 writel(2, fep->hwp + FEC_ECNTRL);
716 writel(rmii_mode, fep->hwp + FEC_R_CNTRL);
717 }
718}
719
720
721static void
722fec_timeout(struct net_device *ndev)
723{
724 struct fec_enet_private *fep = netdev_priv(ndev);
725
726 ndev->stats.tx_errors++;
727
728 fep->delay_work.timeout = true;
729 schedule_delayed_work(&(fep->delay_work.delay_work), 0);
730}
731
732static void fec_enet_work(struct work_struct *work)
733{
734 struct fec_enet_private *fep =
735 container_of(work,
736 struct fec_enet_private,
737 delay_work.delay_work.work);
738
739 if (fep->delay_work.timeout) {
740 fep->delay_work.timeout = false;
741 fec_restart(fep->netdev, fep->full_duplex);
742 netif_wake_queue(fep->netdev);
743 }
744
745 if (fep->delay_work.trig_tx) {
746 fep->delay_work.trig_tx = false;
747 writel(0, fep->hwp + FEC_X_DES_ACTIVE);
748 }
749}
750
751static void
752fec_enet_tx(struct net_device *ndev)
753{
754 struct fec_enet_private *fep;
755 struct bufdesc *bdp;
756 unsigned short status;
757 struct sk_buff *skb;
758 int index = 0;
759
760 fep = netdev_priv(ndev);
761 bdp = fep->dirty_tx;
762
763 /* get next bdp of dirty_tx */
764 bdp = fec_enet_get_nextdesc(bdp, fep);
765
766 while (((status = bdp->cbd_sc) & BD_ENET_TX_READY) == 0) {
767
768 /* current queue is empty */
769 if (bdp == fep->cur_tx)
770 break;
771
772 if (fep->bufdesc_ex)
773 index = (struct bufdesc_ex *)bdp -
774 (struct bufdesc_ex *)fep->tx_bd_base;
775 else
776 index = bdp - fep->tx_bd_base;
777
778 skb = fep->tx_skbuff[index];
779 dma_unmap_single(&fep->pdev->dev, bdp->cbd_bufaddr, skb->len,
780 DMA_TO_DEVICE);
781 bdp->cbd_bufaddr = 0;
782
783 /* Check for errors. */
784 if (status & (BD_ENET_TX_HB | BD_ENET_TX_LC |
785 BD_ENET_TX_RL | BD_ENET_TX_UN |
786 BD_ENET_TX_CSL)) {
787 ndev->stats.tx_errors++;
788 if (status & BD_ENET_TX_HB) /* No heartbeat */
789 ndev->stats.tx_heartbeat_errors++;
790 if (status & BD_ENET_TX_LC) /* Late collision */
791 ndev->stats.tx_window_errors++;
792 if (status & BD_ENET_TX_RL) /* Retrans limit */
793 ndev->stats.tx_aborted_errors++;
794 if (status & BD_ENET_TX_UN) /* Underrun */
795 ndev->stats.tx_fifo_errors++;
796 if (status & BD_ENET_TX_CSL) /* Carrier lost */
797 ndev->stats.tx_carrier_errors++;
798 } else {
799 ndev->stats.tx_packets++;
800 ndev->stats.tx_bytes += bdp->cbd_datlen;
801 }
802
803 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS) &&
804 fep->bufdesc_ex) {
805 struct skb_shared_hwtstamps shhwtstamps;
806 unsigned long flags;
807 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
808
809 memset(&shhwtstamps, 0, sizeof(shhwtstamps));
810 spin_lock_irqsave(&fep->tmreg_lock, flags);
811 shhwtstamps.hwtstamp = ns_to_ktime(
812 timecounter_cyc2time(&fep->tc, ebdp->ts));
813 spin_unlock_irqrestore(&fep->tmreg_lock, flags);
814 skb_tstamp_tx(skb, &shhwtstamps);
815 }
816
817 if (status & BD_ENET_TX_READY)
818 netdev_err(ndev, "HEY! Enet xmit interrupt and TX_READY\n");
819
820 /* Deferred means some collisions occurred during transmit,
821 * but we eventually sent the packet OK.
822 */
823 if (status & BD_ENET_TX_DEF)
824 ndev->stats.collisions++;
825
826 /* Free the sk buffer associated with this last transmit */
827 dev_kfree_skb_any(skb);
828 fep->tx_skbuff[index] = NULL;
829
830 fep->dirty_tx = bdp;
831
832 /* Update pointer to next buffer descriptor to be transmitted */
833 bdp = fec_enet_get_nextdesc(bdp, fep);
834
835 /* Since we have freed up a buffer, the ring is no longer full
836 */
837 if (fep->dirty_tx != fep->cur_tx) {
838 if (netif_queue_stopped(ndev))
839 netif_wake_queue(ndev);
840 }
841 }
842 return;
843}
844
845
846/* During a receive, the cur_rx points to the current incoming buffer.
847 * When we update through the ring, if the next incoming buffer has
848 * not been given to the system, we just set the empty indicator,
849 * effectively tossing the packet.
850 */
851static int
852fec_enet_rx(struct net_device *ndev, int budget)
853{
854 struct fec_enet_private *fep = netdev_priv(ndev);
855 const struct platform_device_id *id_entry =
856 platform_get_device_id(fep->pdev);
857 struct bufdesc *bdp;
858 unsigned short status;
859 struct sk_buff *skb;
860 ushort pkt_len;
861 __u8 *data;
862 int pkt_received = 0;
863 struct bufdesc_ex *ebdp = NULL;
864 bool vlan_packet_rcvd = false;
865 u16 vlan_tag;
866 int index = 0;
867
868#ifdef CONFIG_M532x
869 flush_cache_all();
870#endif
871
872 /* First, grab all of the stats for the incoming packet.
873 * These get messed up if we get called due to a busy condition.
874 */
875 bdp = fep->cur_rx;
876
877 while (!((status = bdp->cbd_sc) & BD_ENET_RX_EMPTY)) {
878
879 if (pkt_received >= budget)
880 break;
881 pkt_received++;
882
883 /* Since we have allocated space to hold a complete frame,
884 * the last indicator should be set.
885 */
886 if ((status & BD_ENET_RX_LAST) == 0)
887 netdev_err(ndev, "rcv is not +last\n");
888
889 if (!fep->opened)
890 goto rx_processing_done;
891
892 /* Check for errors. */
893 if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH | BD_ENET_RX_NO |
894 BD_ENET_RX_CR | BD_ENET_RX_OV)) {
895 ndev->stats.rx_errors++;
896 if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH)) {
897 /* Frame too long or too short. */
898 ndev->stats.rx_length_errors++;
899 }
900 if (status & BD_ENET_RX_NO) /* Frame alignment */
901 ndev->stats.rx_frame_errors++;
902 if (status & BD_ENET_RX_CR) /* CRC Error */
903 ndev->stats.rx_crc_errors++;
904 if (status & BD_ENET_RX_OV) /* FIFO overrun */
905 ndev->stats.rx_fifo_errors++;
906 }
907
908 /* Report late collisions as a frame error.
909 * On this error, the BD is closed, but we don't know what we
910 * have in the buffer. So, just drop this frame on the floor.
911 */
912 if (status & BD_ENET_RX_CL) {
913 ndev->stats.rx_errors++;
914 ndev->stats.rx_frame_errors++;
915 goto rx_processing_done;
916 }
917
918 /* Process the incoming frame. */
919 ndev->stats.rx_packets++;
920 pkt_len = bdp->cbd_datlen;
921 ndev->stats.rx_bytes += pkt_len;
922
923 if (fep->bufdesc_ex)
924 index = (struct bufdesc_ex *)bdp -
925 (struct bufdesc_ex *)fep->rx_bd_base;
926 else
927 index = bdp - fep->rx_bd_base;
928 data = fep->rx_skbuff[index]->data;
929 dma_sync_single_for_cpu(&fep->pdev->dev, bdp->cbd_bufaddr,
930 FEC_ENET_RX_FRSIZE, DMA_FROM_DEVICE);
931
932 if (id_entry->driver_data & FEC_QUIRK_SWAP_FRAME)
933 swap_buffer(data, pkt_len);
934
935 /* Extract the enhanced buffer descriptor */
936 ebdp = NULL;
937 if (fep->bufdesc_ex)
938 ebdp = (struct bufdesc_ex *)bdp;
939
940 /* If this is a VLAN packet remove the VLAN Tag */
941 vlan_packet_rcvd = false;
942 if ((ndev->features & NETIF_F_HW_VLAN_CTAG_RX) &&
943 fep->bufdesc_ex && (ebdp->cbd_esc & BD_ENET_RX_VLAN)) {
944 /* Push and remove the vlan tag */
945 struct vlan_hdr *vlan_header =
946 (struct vlan_hdr *) (data + ETH_HLEN);
947 vlan_tag = ntohs(vlan_header->h_vlan_TCI);
948 pkt_len -= VLAN_HLEN;
949
950 vlan_packet_rcvd = true;
951 }
952
953 /* This does 16 byte alignment, exactly what we need.
954 * The packet length includes FCS, but we don't want to
955 * include that when passing upstream as it messes up
956 * bridging applications.
957 */
958 skb = netdev_alloc_skb(ndev, pkt_len - 4 + NET_IP_ALIGN);
959
960 if (unlikely(!skb)) {
961 ndev->stats.rx_dropped++;
962 } else {
963 int payload_offset = (2 * ETH_ALEN);
964 skb_reserve(skb, NET_IP_ALIGN);
965 skb_put(skb, pkt_len - 4); /* Make room */
966
967 /* Extract the frame data without the VLAN header. */
968 skb_copy_to_linear_data(skb, data, (2 * ETH_ALEN));
969 if (vlan_packet_rcvd)
970 payload_offset = (2 * ETH_ALEN) + VLAN_HLEN;
971 skb_copy_to_linear_data_offset(skb, (2 * ETH_ALEN),
972 data + payload_offset,
973 pkt_len - 4 - (2 * ETH_ALEN));
974
975 skb->protocol = eth_type_trans(skb, ndev);
976
977 /* Get receive timestamp from the skb */
978 if (fep->hwts_rx_en && fep->bufdesc_ex) {
979 struct skb_shared_hwtstamps *shhwtstamps =
980 skb_hwtstamps(skb);
981 unsigned long flags;
982
983 memset(shhwtstamps, 0, sizeof(*shhwtstamps));
984
985 spin_lock_irqsave(&fep->tmreg_lock, flags);
986 shhwtstamps->hwtstamp = ns_to_ktime(
987 timecounter_cyc2time(&fep->tc, ebdp->ts));
988 spin_unlock_irqrestore(&fep->tmreg_lock, flags);
989 }
990
991 if (fep->bufdesc_ex &&
992 (fep->csum_flags & FLAG_RX_CSUM_ENABLED)) {
993 if (!(ebdp->cbd_esc & FLAG_RX_CSUM_ERROR)) {
994 /* don't check it */
995 skb->ip_summed = CHECKSUM_UNNECESSARY;
996 } else {
997 skb_checksum_none_assert(skb);
998 }
999 }
1000
1001 /* Handle received VLAN packets */
1002 if (vlan_packet_rcvd)
1003 __vlan_hwaccel_put_tag(skb,
1004 htons(ETH_P_8021Q),
1005 vlan_tag);
1006
1007 napi_gro_receive(&fep->napi, skb);
1008 }
1009
1010 dma_sync_single_for_device(&fep->pdev->dev, bdp->cbd_bufaddr,
1011 FEC_ENET_RX_FRSIZE, DMA_FROM_DEVICE);
1012rx_processing_done:
1013 /* Clear the status flags for this buffer */
1014 status &= ~BD_ENET_RX_STATS;
1015
1016 /* Mark the buffer empty */
1017 status |= BD_ENET_RX_EMPTY;
1018 bdp->cbd_sc = status;
1019
1020 if (fep->bufdesc_ex) {
1021 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
1022
1023 ebdp->cbd_esc = BD_ENET_RX_INT;
1024 ebdp->cbd_prot = 0;
1025 ebdp->cbd_bdu = 0;
1026 }
1027
1028 /* Update BD pointer to next entry */
1029 bdp = fec_enet_get_nextdesc(bdp, fep);
1030
1031 /* Doing this here will keep the FEC running while we process
1032 * incoming frames. On a heavily loaded network, we should be
1033 * able to keep up at the expense of system resources.
1034 */
1035 writel(0, fep->hwp + FEC_R_DES_ACTIVE);
1036 }
1037 fep->cur_rx = bdp;
1038
1039 return pkt_received;
1040}
1041
1042static irqreturn_t
1043fec_enet_interrupt(int irq, void *dev_id)
1044{
1045 struct net_device *ndev = dev_id;
1046 struct fec_enet_private *fep = netdev_priv(ndev);
1047 uint int_events;
1048 irqreturn_t ret = IRQ_NONE;
1049
1050 do {
1051 int_events = readl(fep->hwp + FEC_IEVENT);
1052 writel(int_events, fep->hwp + FEC_IEVENT);
1053
1054 if (int_events & (FEC_ENET_RXF | FEC_ENET_TXF)) {
1055 ret = IRQ_HANDLED;
1056
1057 /* Disable the RX interrupt */
1058 if (napi_schedule_prep(&fep->napi)) {
1059 writel(FEC_RX_DISABLED_IMASK,
1060 fep->hwp + FEC_IMASK);
1061 __napi_schedule(&fep->napi);
1062 }
1063 }
1064
1065 if (int_events & FEC_ENET_MII) {
1066 ret = IRQ_HANDLED;
1067 complete(&fep->mdio_done);
1068 }
1069 } while (int_events);
1070
1071 return ret;
1072}
1073
1074static int fec_enet_rx_napi(struct napi_struct *napi, int budget)
1075{
1076 struct net_device *ndev = napi->dev;
1077 int pkts = fec_enet_rx(ndev, budget);
1078 struct fec_enet_private *fep = netdev_priv(ndev);
1079
1080 fec_enet_tx(ndev);
1081
1082 if (pkts < budget) {
1083 napi_complete(napi);
1084 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK);
1085 }
1086 return pkts;
1087}
1088
1089/* ------------------------------------------------------------------------- */
1090static void fec_get_mac(struct net_device *ndev)
1091{
1092 struct fec_enet_private *fep = netdev_priv(ndev);
1093 struct fec_platform_data *pdata = dev_get_platdata(&fep->pdev->dev);
1094 unsigned char *iap, tmpaddr[ETH_ALEN];
1095
1096 /*
1097 * try to get mac address in following order:
1098 *
1099 * 1) module parameter via kernel command line in form
1100 * fec.macaddr=0x00,0x04,0x9f,0x01,0x30,0xe0
1101 */
1102 iap = macaddr;
1103
1104 /*
1105 * 2) from device tree data
1106 */
1107 if (!is_valid_ether_addr(iap)) {
1108 struct device_node *np = fep->pdev->dev.of_node;
1109 if (np) {
1110 const char *mac = of_get_mac_address(np);
1111 if (mac)
1112 iap = (unsigned char *) mac;
1113 }
1114 }
1115
1116 /*
1117 * 3) from flash or fuse (via platform data)
1118 */
1119 if (!is_valid_ether_addr(iap)) {
1120#ifdef CONFIG_M5272
1121 if (FEC_FLASHMAC)
1122 iap = (unsigned char *)FEC_FLASHMAC;
1123#else
1124 if (pdata)
1125 iap = (unsigned char *)&pdata->mac;
1126#endif
1127 }
1128
1129 /*
1130 * 4) FEC mac registers set by bootloader
1131 */
1132 if (!is_valid_ether_addr(iap)) {
1133 *((__be32 *) &tmpaddr[0]) =
1134 cpu_to_be32(readl(fep->hwp + FEC_ADDR_LOW));
1135 *((__be16 *) &tmpaddr[4]) =
1136 cpu_to_be16(readl(fep->hwp + FEC_ADDR_HIGH) >> 16);
1137 iap = &tmpaddr[0];
1138 }
1139
1140 /*
1141 * 5) random mac address
1142 */
1143 if (!is_valid_ether_addr(iap)) {
1144 /* Report it and use a random ethernet address instead */
1145 netdev_err(ndev, "Invalid MAC address: %pM\n", iap);
1146 eth_hw_addr_random(ndev);
1147 netdev_info(ndev, "Using random MAC address: %pM\n",
1148 ndev->dev_addr);
1149 return;
1150 }
1151
1152 memcpy(ndev->dev_addr, iap, ETH_ALEN);
1153
1154 /* Adjust MAC if using macaddr */
1155 if (iap == macaddr)
1156 ndev->dev_addr[ETH_ALEN-1] = macaddr[ETH_ALEN-1] + fep->dev_id;
1157}
1158
1159/* ------------------------------------------------------------------------- */
1160
1161/*
1162 * Phy section
1163 */
1164static void fec_enet_adjust_link(struct net_device *ndev)
1165{
1166 struct fec_enet_private *fep = netdev_priv(ndev);
1167 struct phy_device *phy_dev = fep->phy_dev;
1168 int status_change = 0;
1169
1170 /* Prevent a state halted on mii error */
1171 if (fep->mii_timeout && phy_dev->state == PHY_HALTED) {
1172 phy_dev->state = PHY_RESUMING;
1173 return;
1174 }
1175
1176 if (phy_dev->link) {
1177 if (!fep->link) {
1178 fep->link = phy_dev->link;
1179 status_change = 1;
1180 }
1181
1182 if (fep->full_duplex != phy_dev->duplex)
1183 status_change = 1;
1184
1185 if (phy_dev->speed != fep->speed) {
1186 fep->speed = phy_dev->speed;
1187 status_change = 1;
1188 }
1189
1190 /* if any of the above changed restart the FEC */
1191 if (status_change)
1192 fec_restart(ndev, phy_dev->duplex);
1193 } else {
1194 if (fep->link) {
1195 fec_stop(ndev);
1196 fep->link = phy_dev->link;
1197 status_change = 1;
1198 }
1199 }
1200
1201 if (status_change)
1202 phy_print_status(phy_dev);
1203}
1204
1205static int fec_enet_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
1206{
1207 struct fec_enet_private *fep = bus->priv;
1208 unsigned long time_left;
1209
1210 fep->mii_timeout = 0;
1211 init_completion(&fep->mdio_done);
1212
1213 /* start a read op */
1214 writel(FEC_MMFR_ST | FEC_MMFR_OP_READ |
1215 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(regnum) |
1216 FEC_MMFR_TA, fep->hwp + FEC_MII_DATA);
1217
1218 /* wait for end of transfer */
1219 time_left = wait_for_completion_timeout(&fep->mdio_done,
1220 usecs_to_jiffies(FEC_MII_TIMEOUT));
1221 if (time_left == 0) {
1222 fep->mii_timeout = 1;
1223 netdev_err(fep->netdev, "MDIO read timeout\n");
1224 return -ETIMEDOUT;
1225 }
1226
1227 /* return value */
1228 return FEC_MMFR_DATA(readl(fep->hwp + FEC_MII_DATA));
1229}
1230
1231static int fec_enet_mdio_write(struct mii_bus *bus, int mii_id, int regnum,
1232 u16 value)
1233{
1234 struct fec_enet_private *fep = bus->priv;
1235 unsigned long time_left;
1236
1237 fep->mii_timeout = 0;
1238 init_completion(&fep->mdio_done);
1239
1240 /* start a write op */
1241 writel(FEC_MMFR_ST | FEC_MMFR_OP_WRITE |
1242 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(regnum) |
1243 FEC_MMFR_TA | FEC_MMFR_DATA(value),
1244 fep->hwp + FEC_MII_DATA);
1245
1246 /* wait for end of transfer */
1247 time_left = wait_for_completion_timeout(&fep->mdio_done,
1248 usecs_to_jiffies(FEC_MII_TIMEOUT));
1249 if (time_left == 0) {
1250 fep->mii_timeout = 1;
1251 netdev_err(fep->netdev, "MDIO write timeout\n");
1252 return -ETIMEDOUT;
1253 }
1254
1255 return 0;
1256}
1257
1258static int fec_enet_mii_probe(struct net_device *ndev)
1259{
1260 struct fec_enet_private *fep = netdev_priv(ndev);
1261 const struct platform_device_id *id_entry =
1262 platform_get_device_id(fep->pdev);
1263 struct phy_device *phy_dev = NULL;
1264 char mdio_bus_id[MII_BUS_ID_SIZE];
1265 char phy_name[MII_BUS_ID_SIZE + 3];
1266 int phy_id;
1267 int dev_id = fep->dev_id;
1268
1269 fep->phy_dev = NULL;
1270
1271 /* check for attached phy */
1272 for (phy_id = 0; (phy_id < PHY_MAX_ADDR); phy_id++) {
1273 if ((fep->mii_bus->phy_mask & (1 << phy_id)))
1274 continue;
1275 if (fep->mii_bus->phy_map[phy_id] == NULL)
1276 continue;
1277 if (fep->mii_bus->phy_map[phy_id]->phy_id == 0)
1278 continue;
1279 if (dev_id--)
1280 continue;
1281 strncpy(mdio_bus_id, fep->mii_bus->id, MII_BUS_ID_SIZE);
1282 break;
1283 }
1284
1285 if (phy_id >= PHY_MAX_ADDR) {
1286 netdev_info(ndev, "no PHY, assuming direct connection to switch\n");
1287 strncpy(mdio_bus_id, "fixed-0", MII_BUS_ID_SIZE);
1288 phy_id = 0;
1289 }
1290
1291 snprintf(phy_name, sizeof(phy_name), PHY_ID_FMT, mdio_bus_id, phy_id);
1292 phy_dev = phy_connect(ndev, phy_name, &fec_enet_adjust_link,
1293 fep->phy_interface);
1294 if (IS_ERR(phy_dev)) {
1295 netdev_err(ndev, "could not attach to PHY\n");
1296 return PTR_ERR(phy_dev);
1297 }
1298
1299 /* mask with MAC supported features */
1300 if (id_entry->driver_data & FEC_QUIRK_HAS_GBIT) {
1301 phy_dev->supported &= PHY_GBIT_FEATURES;
1302#if !defined(CONFIG_M5272)
1303 phy_dev->supported |= SUPPORTED_Pause;
1304#endif
1305 }
1306 else
1307 phy_dev->supported &= PHY_BASIC_FEATURES;
1308
1309 phy_dev->advertising = phy_dev->supported;
1310
1311 fep->phy_dev = phy_dev;
1312 fep->link = 0;
1313 fep->full_duplex = 0;
1314
1315 netdev_info(ndev, "Freescale FEC PHY driver [%s] (mii_bus:phy_addr=%s, irq=%d)\n",
1316 fep->phy_dev->drv->name, dev_name(&fep->phy_dev->dev),
1317 fep->phy_dev->irq);
1318
1319 return 0;
1320}
1321
1322static int fec_enet_mii_init(struct platform_device *pdev)
1323{
1324 static struct mii_bus *fec0_mii_bus;
1325 struct net_device *ndev = platform_get_drvdata(pdev);
1326 struct fec_enet_private *fep = netdev_priv(ndev);
1327 const struct platform_device_id *id_entry =
1328 platform_get_device_id(fep->pdev);
1329 int err = -ENXIO, i;
1330
1331 /*
1332 * The dual fec interfaces are not equivalent with enet-mac.
1333 * Here are the differences:
1334 *
1335 * - fec0 supports MII & RMII modes while fec1 only supports RMII
1336 * - fec0 acts as the 1588 time master while fec1 is slave
1337 * - external phys can only be configured by fec0
1338 *
1339 * That is to say fec1 can not work independently. It only works
1340 * when fec0 is working. The reason behind this design is that the
1341 * second interface is added primarily for Switch mode.
1342 *
1343 * Because of the last point above, both phys are attached on fec0
1344 * mdio interface in board design, and need to be configured by
1345 * fec0 mii_bus.
1346 */
1347 if ((id_entry->driver_data & FEC_QUIRK_ENET_MAC) && fep->dev_id > 0) {
1348 /* fec1 uses fec0 mii_bus */
1349 if (mii_cnt && fec0_mii_bus) {
1350 fep->mii_bus = fec0_mii_bus;
1351 mii_cnt++;
1352 return 0;
1353 }
1354 return -ENOENT;
1355 }
1356
1357 fep->mii_timeout = 0;
1358
1359 /*
1360 * Set MII speed to 2.5 MHz (= clk_get_rate() / 2 * phy_speed)
1361 *
1362 * The formula for FEC MDC is 'ref_freq / (MII_SPEED x 2)' while
1363 * for ENET-MAC is 'ref_freq / ((MII_SPEED + 1) x 2)'. The i.MX28
1364 * Reference Manual has an error on this, and gets fixed on i.MX6Q
1365 * document.
1366 */
1367 fep->phy_speed = DIV_ROUND_UP(clk_get_rate(fep->clk_ahb), 5000000);
1368 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC)
1369 fep->phy_speed--;
1370 fep->phy_speed <<= 1;
1371 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
1372
1373 fep->mii_bus = mdiobus_alloc();
1374 if (fep->mii_bus == NULL) {
1375 err = -ENOMEM;
1376 goto err_out;
1377 }
1378
1379 fep->mii_bus->name = "fec_enet_mii_bus";
1380 fep->mii_bus->read = fec_enet_mdio_read;
1381 fep->mii_bus->write = fec_enet_mdio_write;
1382 snprintf(fep->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
1383 pdev->name, fep->dev_id + 1);
1384 fep->mii_bus->priv = fep;
1385 fep->mii_bus->parent = &pdev->dev;
1386
1387 fep->mii_bus->irq = kmalloc(sizeof(int) * PHY_MAX_ADDR, GFP_KERNEL);
1388 if (!fep->mii_bus->irq) {
1389 err = -ENOMEM;
1390 goto err_out_free_mdiobus;
1391 }
1392
1393 for (i = 0; i < PHY_MAX_ADDR; i++)
1394 fep->mii_bus->irq[i] = PHY_POLL;
1395
1396 if (mdiobus_register(fep->mii_bus))
1397 goto err_out_free_mdio_irq;
1398
1399 mii_cnt++;
1400
1401 /* save fec0 mii_bus */
1402 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC)
1403 fec0_mii_bus = fep->mii_bus;
1404
1405 return 0;
1406
1407err_out_free_mdio_irq:
1408 kfree(fep->mii_bus->irq);
1409err_out_free_mdiobus:
1410 mdiobus_free(fep->mii_bus);
1411err_out:
1412 return err;
1413}
1414
1415static void fec_enet_mii_remove(struct fec_enet_private *fep)
1416{
1417 if (--mii_cnt == 0) {
1418 mdiobus_unregister(fep->mii_bus);
1419 kfree(fep->mii_bus->irq);
1420 mdiobus_free(fep->mii_bus);
1421 }
1422}
1423
1424static int fec_enet_get_settings(struct net_device *ndev,
1425 struct ethtool_cmd *cmd)
1426{
1427 struct fec_enet_private *fep = netdev_priv(ndev);
1428 struct phy_device *phydev = fep->phy_dev;
1429
1430 if (!phydev)
1431 return -ENODEV;
1432
1433 return phy_ethtool_gset(phydev, cmd);
1434}
1435
1436static int fec_enet_set_settings(struct net_device *ndev,
1437 struct ethtool_cmd *cmd)
1438{
1439 struct fec_enet_private *fep = netdev_priv(ndev);
1440 struct phy_device *phydev = fep->phy_dev;
1441
1442 if (!phydev)
1443 return -ENODEV;
1444
1445 return phy_ethtool_sset(phydev, cmd);
1446}
1447
1448static void fec_enet_get_drvinfo(struct net_device *ndev,
1449 struct ethtool_drvinfo *info)
1450{
1451 struct fec_enet_private *fep = netdev_priv(ndev);
1452
1453 strlcpy(info->driver, fep->pdev->dev.driver->name,
1454 sizeof(info->driver));
1455 strlcpy(info->version, "Revision: 1.0", sizeof(info->version));
1456 strlcpy(info->bus_info, dev_name(&ndev->dev), sizeof(info->bus_info));
1457}
1458
1459static int fec_enet_get_ts_info(struct net_device *ndev,
1460 struct ethtool_ts_info *info)
1461{
1462 struct fec_enet_private *fep = netdev_priv(ndev);
1463
1464 if (fep->bufdesc_ex) {
1465
1466 info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE |
1467 SOF_TIMESTAMPING_RX_SOFTWARE |
1468 SOF_TIMESTAMPING_SOFTWARE |
1469 SOF_TIMESTAMPING_TX_HARDWARE |
1470 SOF_TIMESTAMPING_RX_HARDWARE |
1471 SOF_TIMESTAMPING_RAW_HARDWARE;
1472 if (fep->ptp_clock)
1473 info->phc_index = ptp_clock_index(fep->ptp_clock);
1474 else
1475 info->phc_index = -1;
1476
1477 info->tx_types = (1 << HWTSTAMP_TX_OFF) |
1478 (1 << HWTSTAMP_TX_ON);
1479
1480 info->rx_filters = (1 << HWTSTAMP_FILTER_NONE) |
1481 (1 << HWTSTAMP_FILTER_ALL);
1482 return 0;
1483 } else {
1484 return ethtool_op_get_ts_info(ndev, info);
1485 }
1486}
1487
1488#if !defined(CONFIG_M5272)
1489
1490static void fec_enet_get_pauseparam(struct net_device *ndev,
1491 struct ethtool_pauseparam *pause)
1492{
1493 struct fec_enet_private *fep = netdev_priv(ndev);
1494
1495 pause->autoneg = (fep->pause_flag & FEC_PAUSE_FLAG_AUTONEG) != 0;
1496 pause->tx_pause = (fep->pause_flag & FEC_PAUSE_FLAG_ENABLE) != 0;
1497 pause->rx_pause = pause->tx_pause;
1498}
1499
1500static int fec_enet_set_pauseparam(struct net_device *ndev,
1501 struct ethtool_pauseparam *pause)
1502{
1503 struct fec_enet_private *fep = netdev_priv(ndev);
1504
1505 if (pause->tx_pause != pause->rx_pause) {
1506 netdev_info(ndev,
1507 "hardware only support enable/disable both tx and rx");
1508 return -EINVAL;
1509 }
1510
1511 fep->pause_flag = 0;
1512
1513 /* tx pause must be same as rx pause */
1514 fep->pause_flag |= pause->rx_pause ? FEC_PAUSE_FLAG_ENABLE : 0;
1515 fep->pause_flag |= pause->autoneg ? FEC_PAUSE_FLAG_AUTONEG : 0;
1516
1517 if (pause->rx_pause || pause->autoneg) {
1518 fep->phy_dev->supported |= ADVERTISED_Pause;
1519 fep->phy_dev->advertising |= ADVERTISED_Pause;
1520 } else {
1521 fep->phy_dev->supported &= ~ADVERTISED_Pause;
1522 fep->phy_dev->advertising &= ~ADVERTISED_Pause;
1523 }
1524
1525 if (pause->autoneg) {
1526 if (netif_running(ndev))
1527 fec_stop(ndev);
1528 phy_start_aneg(fep->phy_dev);
1529 }
1530 if (netif_running(ndev))
1531 fec_restart(ndev, 0);
1532
1533 return 0;
1534}
1535
1536static const struct fec_stat {
1537 char name[ETH_GSTRING_LEN];
1538 u16 offset;
1539} fec_stats[] = {
1540 /* RMON TX */
1541 { "tx_dropped", RMON_T_DROP },
1542 { "tx_packets", RMON_T_PACKETS },
1543 { "tx_broadcast", RMON_T_BC_PKT },
1544 { "tx_multicast", RMON_T_MC_PKT },
1545 { "tx_crc_errors", RMON_T_CRC_ALIGN },
1546 { "tx_undersize", RMON_T_UNDERSIZE },
1547 { "tx_oversize", RMON_T_OVERSIZE },
1548 { "tx_fragment", RMON_T_FRAG },
1549 { "tx_jabber", RMON_T_JAB },
1550 { "tx_collision", RMON_T_COL },
1551 { "tx_64byte", RMON_T_P64 },
1552 { "tx_65to127byte", RMON_T_P65TO127 },
1553 { "tx_128to255byte", RMON_T_P128TO255 },
1554 { "tx_256to511byte", RMON_T_P256TO511 },
1555 { "tx_512to1023byte", RMON_T_P512TO1023 },
1556 { "tx_1024to2047byte", RMON_T_P1024TO2047 },
1557 { "tx_GTE2048byte", RMON_T_P_GTE2048 },
1558 { "tx_octets", RMON_T_OCTETS },
1559
1560 /* IEEE TX */
1561 { "IEEE_tx_drop", IEEE_T_DROP },
1562 { "IEEE_tx_frame_ok", IEEE_T_FRAME_OK },
1563 { "IEEE_tx_1col", IEEE_T_1COL },
1564 { "IEEE_tx_mcol", IEEE_T_MCOL },
1565 { "IEEE_tx_def", IEEE_T_DEF },
1566 { "IEEE_tx_lcol", IEEE_T_LCOL },
1567 { "IEEE_tx_excol", IEEE_T_EXCOL },
1568 { "IEEE_tx_macerr", IEEE_T_MACERR },
1569 { "IEEE_tx_cserr", IEEE_T_CSERR },
1570 { "IEEE_tx_sqe", IEEE_T_SQE },
1571 { "IEEE_tx_fdxfc", IEEE_T_FDXFC },
1572 { "IEEE_tx_octets_ok", IEEE_T_OCTETS_OK },
1573
1574 /* RMON RX */
1575 { "rx_packets", RMON_R_PACKETS },
1576 { "rx_broadcast", RMON_R_BC_PKT },
1577 { "rx_multicast", RMON_R_MC_PKT },
1578 { "rx_crc_errors", RMON_R_CRC_ALIGN },
1579 { "rx_undersize", RMON_R_UNDERSIZE },
1580 { "rx_oversize", RMON_R_OVERSIZE },
1581 { "rx_fragment", RMON_R_FRAG },
1582 { "rx_jabber", RMON_R_JAB },
1583 { "rx_64byte", RMON_R_P64 },
1584 { "rx_65to127byte", RMON_R_P65TO127 },
1585 { "rx_128to255byte", RMON_R_P128TO255 },
1586 { "rx_256to511byte", RMON_R_P256TO511 },
1587 { "rx_512to1023byte", RMON_R_P512TO1023 },
1588 { "rx_1024to2047byte", RMON_R_P1024TO2047 },
1589 { "rx_GTE2048byte", RMON_R_P_GTE2048 },
1590 { "rx_octets", RMON_R_OCTETS },
1591
1592 /* IEEE RX */
1593 { "IEEE_rx_drop", IEEE_R_DROP },
1594 { "IEEE_rx_frame_ok", IEEE_R_FRAME_OK },
1595 { "IEEE_rx_crc", IEEE_R_CRC },
1596 { "IEEE_rx_align", IEEE_R_ALIGN },
1597 { "IEEE_rx_macerr", IEEE_R_MACERR },
1598 { "IEEE_rx_fdxfc", IEEE_R_FDXFC },
1599 { "IEEE_rx_octets_ok", IEEE_R_OCTETS_OK },
1600};
1601
1602static void fec_enet_get_ethtool_stats(struct net_device *dev,
1603 struct ethtool_stats *stats, u64 *data)
1604{
1605 struct fec_enet_private *fep = netdev_priv(dev);
1606 int i;
1607
1608 for (i = 0; i < ARRAY_SIZE(fec_stats); i++)
1609 data[i] = readl(fep->hwp + fec_stats[i].offset);
1610}
1611
1612static void fec_enet_get_strings(struct net_device *netdev,
1613 u32 stringset, u8 *data)
1614{
1615 int i;
1616 switch (stringset) {
1617 case ETH_SS_STATS:
1618 for (i = 0; i < ARRAY_SIZE(fec_stats); i++)
1619 memcpy(data + i * ETH_GSTRING_LEN,
1620 fec_stats[i].name, ETH_GSTRING_LEN);
1621 break;
1622 }
1623}
1624
1625static int fec_enet_get_sset_count(struct net_device *dev, int sset)
1626{
1627 switch (sset) {
1628 case ETH_SS_STATS:
1629 return ARRAY_SIZE(fec_stats);
1630 default:
1631 return -EOPNOTSUPP;
1632 }
1633}
1634#endif /* !defined(CONFIG_M5272) */
1635
1636static int fec_enet_nway_reset(struct net_device *dev)
1637{
1638 struct fec_enet_private *fep = netdev_priv(dev);
1639 struct phy_device *phydev = fep->phy_dev;
1640
1641 if (!phydev)
1642 return -ENODEV;
1643
1644 return genphy_restart_aneg(phydev);
1645}
1646
1647static const struct ethtool_ops fec_enet_ethtool_ops = {
1648#if !defined(CONFIG_M5272)
1649 .get_pauseparam = fec_enet_get_pauseparam,
1650 .set_pauseparam = fec_enet_set_pauseparam,
1651#endif
1652 .get_settings = fec_enet_get_settings,
1653 .set_settings = fec_enet_set_settings,
1654 .get_drvinfo = fec_enet_get_drvinfo,
1655 .get_link = ethtool_op_get_link,
1656 .get_ts_info = fec_enet_get_ts_info,
1657 .nway_reset = fec_enet_nway_reset,
1658#ifndef CONFIG_M5272
1659 .get_ethtool_stats = fec_enet_get_ethtool_stats,
1660 .get_strings = fec_enet_get_strings,
1661 .get_sset_count = fec_enet_get_sset_count,
1662#endif
1663};
1664
1665static int fec_enet_ioctl(struct net_device *ndev, struct ifreq *rq, int cmd)
1666{
1667 struct fec_enet_private *fep = netdev_priv(ndev);
1668 struct phy_device *phydev = fep->phy_dev;
1669
1670 if (!netif_running(ndev))
1671 return -EINVAL;
1672
1673 if (!phydev)
1674 return -ENODEV;
1675
1676 if (fep->bufdesc_ex) {
1677 if (cmd == SIOCSHWTSTAMP)
1678 return fec_ptp_set(ndev, rq);
1679 if (cmd == SIOCGHWTSTAMP)
1680 return fec_ptp_get(ndev, rq);
1681 }
1682
1683 return phy_mii_ioctl(phydev, rq, cmd);
1684}
1685
1686static void fec_enet_free_buffers(struct net_device *ndev)
1687{
1688 struct fec_enet_private *fep = netdev_priv(ndev);
1689 unsigned int i;
1690 struct sk_buff *skb;
1691 struct bufdesc *bdp;
1692
1693 bdp = fep->rx_bd_base;
1694 for (i = 0; i < fep->rx_ring_size; i++) {
1695 skb = fep->rx_skbuff[i];
1696
1697 if (bdp->cbd_bufaddr)
1698 dma_unmap_single(&fep->pdev->dev, bdp->cbd_bufaddr,
1699 FEC_ENET_RX_FRSIZE, DMA_FROM_DEVICE);
1700 if (skb)
1701 dev_kfree_skb(skb);
1702 bdp = fec_enet_get_nextdesc(bdp, fep);
1703 }
1704
1705 bdp = fep->tx_bd_base;
1706 for (i = 0; i < fep->tx_ring_size; i++)
1707 kfree(fep->tx_bounce[i]);
1708}
1709
1710static int fec_enet_alloc_buffers(struct net_device *ndev)
1711{
1712 struct fec_enet_private *fep = netdev_priv(ndev);
1713 unsigned int i;
1714 struct sk_buff *skb;
1715 struct bufdesc *bdp;
1716
1717 bdp = fep->rx_bd_base;
1718 for (i = 0; i < fep->rx_ring_size; i++) {
1719 skb = netdev_alloc_skb(ndev, FEC_ENET_RX_FRSIZE);
1720 if (!skb) {
1721 fec_enet_free_buffers(ndev);
1722 return -ENOMEM;
1723 }
1724 fep->rx_skbuff[i] = skb;
1725
1726 bdp->cbd_bufaddr = dma_map_single(&fep->pdev->dev, skb->data,
1727 FEC_ENET_RX_FRSIZE, DMA_FROM_DEVICE);
1728 if (dma_mapping_error(&fep->pdev->dev, bdp->cbd_bufaddr)) {
1729 fec_enet_free_buffers(ndev);
1730 if (net_ratelimit())
1731 netdev_err(ndev, "Rx DMA memory map failed\n");
1732 return -ENOMEM;
1733 }
1734 bdp->cbd_sc = BD_ENET_RX_EMPTY;
1735
1736 if (fep->bufdesc_ex) {
1737 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
1738 ebdp->cbd_esc = BD_ENET_RX_INT;
1739 }
1740
1741 bdp = fec_enet_get_nextdesc(bdp, fep);
1742 }
1743
1744 /* Set the last buffer to wrap. */
1745 bdp = fec_enet_get_prevdesc(bdp, fep);
1746 bdp->cbd_sc |= BD_SC_WRAP;
1747
1748 bdp = fep->tx_bd_base;
1749 for (i = 0; i < fep->tx_ring_size; i++) {
1750 fep->tx_bounce[i] = kmalloc(FEC_ENET_TX_FRSIZE, GFP_KERNEL);
1751
1752 bdp->cbd_sc = 0;
1753 bdp->cbd_bufaddr = 0;
1754
1755 if (fep->bufdesc_ex) {
1756 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
1757 ebdp->cbd_esc = BD_ENET_TX_INT;
1758 }
1759
1760 bdp = fec_enet_get_nextdesc(bdp, fep);
1761 }
1762
1763 /* Set the last buffer to wrap. */
1764 bdp = fec_enet_get_prevdesc(bdp, fep);
1765 bdp->cbd_sc |= BD_SC_WRAP;
1766
1767 return 0;
1768}
1769
1770static int
1771fec_enet_open(struct net_device *ndev)
1772{
1773 struct fec_enet_private *fep = netdev_priv(ndev);
1774 int ret;
1775
1776 /* I should reset the ring buffers here, but I don't yet know
1777 * a simple way to do that.
1778 */
1779
1780 ret = fec_enet_alloc_buffers(ndev);
1781 if (ret)
1782 return ret;
1783
1784 /* Probe and connect to PHY when open the interface */
1785 ret = fec_enet_mii_probe(ndev);
1786 if (ret) {
1787 fec_enet_free_buffers(ndev);
1788 return ret;
1789 }
1790
1791 napi_enable(&fep->napi);
1792 phy_start(fep->phy_dev);
1793 netif_start_queue(ndev);
1794 fep->opened = 1;
1795 return 0;
1796}
1797
1798static int
1799fec_enet_close(struct net_device *ndev)
1800{
1801 struct fec_enet_private *fep = netdev_priv(ndev);
1802
1803 /* Don't know what to do yet. */
1804 napi_disable(&fep->napi);
1805 fep->opened = 0;
1806 netif_stop_queue(ndev);
1807 fec_stop(ndev);
1808
1809 if (fep->phy_dev) {
1810 phy_stop(fep->phy_dev);
1811 phy_disconnect(fep->phy_dev);
1812 }
1813
1814 fec_enet_free_buffers(ndev);
1815
1816 return 0;
1817}
1818
1819/* Set or clear the multicast filter for this adaptor.
1820 * Skeleton taken from sunlance driver.
1821 * The CPM Ethernet implementation allows Multicast as well as individual
1822 * MAC address filtering. Some of the drivers check to make sure it is
1823 * a group multicast address, and discard those that are not. I guess I
1824 * will do the same for now, but just remove the test if you want
1825 * individual filtering as well (do the upper net layers want or support
1826 * this kind of feature?).
1827 */
1828
1829#define HASH_BITS 6 /* #bits in hash */
1830#define CRC32_POLY 0xEDB88320
1831
1832static void set_multicast_list(struct net_device *ndev)
1833{
1834 struct fec_enet_private *fep = netdev_priv(ndev);
1835 struct netdev_hw_addr *ha;
1836 unsigned int i, bit, data, crc, tmp;
1837 unsigned char hash;
1838
1839 if (ndev->flags & IFF_PROMISC) {
1840 tmp = readl(fep->hwp + FEC_R_CNTRL);
1841 tmp |= 0x8;
1842 writel(tmp, fep->hwp + FEC_R_CNTRL);
1843 return;
1844 }
1845
1846 tmp = readl(fep->hwp + FEC_R_CNTRL);
1847 tmp &= ~0x8;
1848 writel(tmp, fep->hwp + FEC_R_CNTRL);
1849
1850 if (ndev->flags & IFF_ALLMULTI) {
1851 /* Catch all multicast addresses, so set the
1852 * filter to all 1's
1853 */
1854 writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
1855 writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
1856
1857 return;
1858 }
1859
1860 /* Clear filter and add the addresses in hash register
1861 */
1862 writel(0, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
1863 writel(0, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
1864
1865 netdev_for_each_mc_addr(ha, ndev) {
1866 /* calculate crc32 value of mac address */
1867 crc = 0xffffffff;
1868
1869 for (i = 0; i < ndev->addr_len; i++) {
1870 data = ha->addr[i];
1871 for (bit = 0; bit < 8; bit++, data >>= 1) {
1872 crc = (crc >> 1) ^
1873 (((crc ^ data) & 1) ? CRC32_POLY : 0);
1874 }
1875 }
1876
1877 /* only upper 6 bits (HASH_BITS) are used
1878 * which point to specific bit in he hash registers
1879 */
1880 hash = (crc >> (32 - HASH_BITS)) & 0x3f;
1881
1882 if (hash > 31) {
1883 tmp = readl(fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
1884 tmp |= 1 << (hash - 32);
1885 writel(tmp, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
1886 } else {
1887 tmp = readl(fep->hwp + FEC_GRP_HASH_TABLE_LOW);
1888 tmp |= 1 << hash;
1889 writel(tmp, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
1890 }
1891 }
1892}
1893
1894/* Set a MAC change in hardware. */
1895static int
1896fec_set_mac_address(struct net_device *ndev, void *p)
1897{
1898 struct fec_enet_private *fep = netdev_priv(ndev);
1899 struct sockaddr *addr = p;
1900
1901 if (addr) {
1902 if (!is_valid_ether_addr(addr->sa_data))
1903 return -EADDRNOTAVAIL;
1904 memcpy(ndev->dev_addr, addr->sa_data, ndev->addr_len);
1905 }
1906
1907 writel(ndev->dev_addr[3] | (ndev->dev_addr[2] << 8) |
1908 (ndev->dev_addr[1] << 16) | (ndev->dev_addr[0] << 24),
1909 fep->hwp + FEC_ADDR_LOW);
1910 writel((ndev->dev_addr[5] << 16) | (ndev->dev_addr[4] << 24),
1911 fep->hwp + FEC_ADDR_HIGH);
1912 return 0;
1913}
1914
1915#ifdef CONFIG_NET_POLL_CONTROLLER
1916/**
1917 * fec_poll_controller - FEC Poll controller function
1918 * @dev: The FEC network adapter
1919 *
1920 * Polled functionality used by netconsole and others in non interrupt mode
1921 *
1922 */
1923static void fec_poll_controller(struct net_device *dev)
1924{
1925 int i;
1926 struct fec_enet_private *fep = netdev_priv(dev);
1927
1928 for (i = 0; i < FEC_IRQ_NUM; i++) {
1929 if (fep->irq[i] > 0) {
1930 disable_irq(fep->irq[i]);
1931 fec_enet_interrupt(fep->irq[i], dev);
1932 enable_irq(fep->irq[i]);
1933 }
1934 }
1935}
1936#endif
1937
1938static int fec_set_features(struct net_device *netdev,
1939 netdev_features_t features)
1940{
1941 struct fec_enet_private *fep = netdev_priv(netdev);
1942 netdev_features_t changed = features ^ netdev->features;
1943
1944 netdev->features = features;
1945
1946 /* Receive checksum has been changed */
1947 if (changed & NETIF_F_RXCSUM) {
1948 if (features & NETIF_F_RXCSUM)
1949 fep->csum_flags |= FLAG_RX_CSUM_ENABLED;
1950 else
1951 fep->csum_flags &= ~FLAG_RX_CSUM_ENABLED;
1952
1953 if (netif_running(netdev)) {
1954 fec_stop(netdev);
1955 fec_restart(netdev, fep->phy_dev->duplex);
1956 netif_wake_queue(netdev);
1957 } else {
1958 fec_restart(netdev, fep->phy_dev->duplex);
1959 }
1960 }
1961
1962 return 0;
1963}
1964
1965static const struct net_device_ops fec_netdev_ops = {
1966 .ndo_open = fec_enet_open,
1967 .ndo_stop = fec_enet_close,
1968 .ndo_start_xmit = fec_enet_start_xmit,
1969 .ndo_set_rx_mode = set_multicast_list,
1970 .ndo_change_mtu = eth_change_mtu,
1971 .ndo_validate_addr = eth_validate_addr,
1972 .ndo_tx_timeout = fec_timeout,
1973 .ndo_set_mac_address = fec_set_mac_address,
1974 .ndo_do_ioctl = fec_enet_ioctl,
1975#ifdef CONFIG_NET_POLL_CONTROLLER
1976 .ndo_poll_controller = fec_poll_controller,
1977#endif
1978 .ndo_set_features = fec_set_features,
1979};
1980
1981 /*
1982 * XXX: We need to clean up on failure exits here.
1983 *
1984 */
1985static int fec_enet_init(struct net_device *ndev)
1986{
1987 struct fec_enet_private *fep = netdev_priv(ndev);
1988 const struct platform_device_id *id_entry =
1989 platform_get_device_id(fep->pdev);
1990 struct bufdesc *cbd_base;
1991
1992 /* Allocate memory for buffer descriptors. */
1993 cbd_base = dma_alloc_coherent(NULL, PAGE_SIZE, &fep->bd_dma,
1994 GFP_KERNEL);
1995 if (!cbd_base)
1996 return -ENOMEM;
1997
1998 memset(cbd_base, 0, PAGE_SIZE);
1999
2000 fep->netdev = ndev;
2001
2002 /* Get the Ethernet address */
2003 fec_get_mac(ndev);
2004 /* make sure MAC we just acquired is programmed into the hw */
2005 fec_set_mac_address(ndev, NULL);
2006
2007 /* init the tx & rx ring size */
2008 fep->tx_ring_size = TX_RING_SIZE;
2009 fep->rx_ring_size = RX_RING_SIZE;
2010
2011 /* Set receive and transmit descriptor base. */
2012 fep->rx_bd_base = cbd_base;
2013 if (fep->bufdesc_ex)
2014 fep->tx_bd_base = (struct bufdesc *)
2015 (((struct bufdesc_ex *)cbd_base) + fep->rx_ring_size);
2016 else
2017 fep->tx_bd_base = cbd_base + fep->rx_ring_size;
2018
2019 /* The FEC Ethernet specific entries in the device structure */
2020 ndev->watchdog_timeo = TX_TIMEOUT;
2021 ndev->netdev_ops = &fec_netdev_ops;
2022 ndev->ethtool_ops = &fec_enet_ethtool_ops;
2023
2024 writel(FEC_RX_DISABLED_IMASK, fep->hwp + FEC_IMASK);
2025 netif_napi_add(ndev, &fep->napi, fec_enet_rx_napi, NAPI_POLL_WEIGHT);
2026
2027 if (id_entry->driver_data & FEC_QUIRK_HAS_VLAN) {
2028 /* enable hw VLAN support */
2029 ndev->features |= NETIF_F_HW_VLAN_CTAG_RX;
2030 ndev->hw_features |= NETIF_F_HW_VLAN_CTAG_RX;
2031 }
2032
2033 if (id_entry->driver_data & FEC_QUIRK_HAS_CSUM) {
2034 /* enable hw accelerator */
2035 ndev->features |= (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM
2036 | NETIF_F_RXCSUM);
2037 ndev->hw_features |= (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM
2038 | NETIF_F_RXCSUM);
2039 fep->csum_flags |= FLAG_RX_CSUM_ENABLED;
2040 }
2041
2042 fec_restart(ndev, 0);
2043
2044 return 0;
2045}
2046
2047#ifdef CONFIG_OF
2048static void fec_reset_phy(struct platform_device *pdev)
2049{
2050 int err, phy_reset;
2051 int msec = 1;
2052 struct device_node *np = pdev->dev.of_node;
2053
2054 if (!np)
2055 return;
2056
2057 of_property_read_u32(np, "phy-reset-duration", &msec);
2058 /* A sane reset duration should not be longer than 1s */
2059 if (msec > 1000)
2060 msec = 1;
2061
2062 phy_reset = of_get_named_gpio(np, "phy-reset-gpios", 0);
2063 if (!gpio_is_valid(phy_reset))
2064 return;
2065
2066 err = devm_gpio_request_one(&pdev->dev, phy_reset,
2067 GPIOF_OUT_INIT_LOW, "phy-reset");
2068 if (err) {
2069 dev_err(&pdev->dev, "failed to get phy-reset-gpios: %d\n", err);
2070 return;
2071 }
2072 msleep(msec);
2073 gpio_set_value(phy_reset, 1);
2074}
2075#else /* CONFIG_OF */
2076static void fec_reset_phy(struct platform_device *pdev)
2077{
2078 /*
2079 * In case of platform probe, the reset has been done
2080 * by machine code.
2081 */
2082}
2083#endif /* CONFIG_OF */
2084
2085static int
2086fec_probe(struct platform_device *pdev)
2087{
2088 struct fec_enet_private *fep;
2089 struct fec_platform_data *pdata;
2090 struct net_device *ndev;
2091 int i, irq, ret = 0;
2092 struct resource *r;
2093 const struct of_device_id *of_id;
2094 static int dev_id;
2095
2096 of_id = of_match_device(fec_dt_ids, &pdev->dev);
2097 if (of_id)
2098 pdev->id_entry = of_id->data;
2099
2100 /* Init network device */
2101 ndev = alloc_etherdev(sizeof(struct fec_enet_private));
2102 if (!ndev)
2103 return -ENOMEM;
2104
2105 SET_NETDEV_DEV(ndev, &pdev->dev);
2106
2107 /* setup board info structure */
2108 fep = netdev_priv(ndev);
2109
2110#if !defined(CONFIG_M5272)
2111 /* default enable pause frame auto negotiation */
2112 if (pdev->id_entry &&
2113 (pdev->id_entry->driver_data & FEC_QUIRK_HAS_GBIT))
2114 fep->pause_flag |= FEC_PAUSE_FLAG_AUTONEG;
2115#endif
2116
2117 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2118 fep->hwp = devm_ioremap_resource(&pdev->dev, r);
2119 if (IS_ERR(fep->hwp)) {
2120 ret = PTR_ERR(fep->hwp);
2121 goto failed_ioremap;
2122 }
2123
2124 fep->pdev = pdev;
2125 fep->dev_id = dev_id++;
2126
2127 fep->bufdesc_ex = 0;
2128
2129 platform_set_drvdata(pdev, ndev);
2130
2131 ret = of_get_phy_mode(pdev->dev.of_node);
2132 if (ret < 0) {
2133 pdata = dev_get_platdata(&pdev->dev);
2134 if (pdata)
2135 fep->phy_interface = pdata->phy;
2136 else
2137 fep->phy_interface = PHY_INTERFACE_MODE_MII;
2138 } else {
2139 fep->phy_interface = ret;
2140 }
2141
2142 fep->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
2143 if (IS_ERR(fep->clk_ipg)) {
2144 ret = PTR_ERR(fep->clk_ipg);
2145 goto failed_clk;
2146 }
2147
2148 fep->clk_ahb = devm_clk_get(&pdev->dev, "ahb");
2149 if (IS_ERR(fep->clk_ahb)) {
2150 ret = PTR_ERR(fep->clk_ahb);
2151 goto failed_clk;
2152 }
2153
2154 /* enet_out is optional, depends on board */
2155 fep->clk_enet_out = devm_clk_get(&pdev->dev, "enet_out");
2156 if (IS_ERR(fep->clk_enet_out))
2157 fep->clk_enet_out = NULL;
2158
2159 fep->clk_ptp = devm_clk_get(&pdev->dev, "ptp");
2160 fep->bufdesc_ex =
2161 pdev->id_entry->driver_data & FEC_QUIRK_HAS_BUFDESC_EX;
2162 if (IS_ERR(fep->clk_ptp)) {
2163 fep->clk_ptp = NULL;
2164 fep->bufdesc_ex = 0;
2165 }
2166
2167 ret = clk_prepare_enable(fep->clk_ahb);
2168 if (ret)
2169 goto failed_clk;
2170
2171 ret = clk_prepare_enable(fep->clk_ipg);
2172 if (ret)
2173 goto failed_clk_ipg;
2174
2175 if (fep->clk_enet_out) {
2176 ret = clk_prepare_enable(fep->clk_enet_out);
2177 if (ret)
2178 goto failed_clk_enet_out;
2179 }
2180
2181 if (fep->clk_ptp) {
2182 ret = clk_prepare_enable(fep->clk_ptp);
2183 if (ret)
2184 goto failed_clk_ptp;
2185 }
2186
2187 fep->reg_phy = devm_regulator_get(&pdev->dev, "phy");
2188 if (!IS_ERR(fep->reg_phy)) {
2189 ret = regulator_enable(fep->reg_phy);
2190 if (ret) {
2191 dev_err(&pdev->dev,
2192 "Failed to enable phy regulator: %d\n", ret);
2193 goto failed_regulator;
2194 }
2195 } else {
2196 fep->reg_phy = NULL;
2197 }
2198
2199 fec_reset_phy(pdev);
2200
2201 if (fep->bufdesc_ex)
2202 fec_ptp_init(pdev);
2203
2204 ret = fec_enet_init(ndev);
2205 if (ret)
2206 goto failed_init;
2207
2208 for (i = 0; i < FEC_IRQ_NUM; i++) {
2209 irq = platform_get_irq(pdev, i);
2210 if (irq < 0) {
2211 if (i)
2212 break;
2213 ret = irq;
2214 goto failed_irq;
2215 }
2216 ret = devm_request_irq(&pdev->dev, irq, fec_enet_interrupt,
2217 0, pdev->name, ndev);
2218 if (ret)
2219 goto failed_irq;
2220 }
2221
2222 ret = fec_enet_mii_init(pdev);
2223 if (ret)
2224 goto failed_mii_init;
2225
2226 /* Carrier starts down, phylib will bring it up */
2227 netif_carrier_off(ndev);
2228
2229 ret = register_netdev(ndev);
2230 if (ret)
2231 goto failed_register;
2232
2233 if (fep->bufdesc_ex && fep->ptp_clock)
2234 netdev_info(ndev, "registered PHC device %d\n", fep->dev_id);
2235
2236 INIT_DELAYED_WORK(&(fep->delay_work.delay_work), fec_enet_work);
2237 return 0;
2238
2239failed_register:
2240 fec_enet_mii_remove(fep);
2241failed_mii_init:
2242failed_irq:
2243failed_init:
2244 if (fep->reg_phy)
2245 regulator_disable(fep->reg_phy);
2246failed_regulator:
2247 if (fep->clk_ptp)
2248 clk_disable_unprepare(fep->clk_ptp);
2249failed_clk_ptp:
2250 if (fep->clk_enet_out)
2251 clk_disable_unprepare(fep->clk_enet_out);
2252failed_clk_enet_out:
2253 clk_disable_unprepare(fep->clk_ipg);
2254failed_clk_ipg:
2255 clk_disable_unprepare(fep->clk_ahb);
2256failed_clk:
2257failed_ioremap:
2258 free_netdev(ndev);
2259
2260 return ret;
2261}
2262
2263static int
2264fec_drv_remove(struct platform_device *pdev)
2265{
2266 struct net_device *ndev = platform_get_drvdata(pdev);
2267 struct fec_enet_private *fep = netdev_priv(ndev);
2268
2269 cancel_delayed_work_sync(&(fep->delay_work.delay_work));
2270 unregister_netdev(ndev);
2271 fec_enet_mii_remove(fep);
2272 del_timer_sync(&fep->time_keep);
2273 if (fep->reg_phy)
2274 regulator_disable(fep->reg_phy);
2275 if (fep->clk_ptp)
2276 clk_disable_unprepare(fep->clk_ptp);
2277 if (fep->ptp_clock)
2278 ptp_clock_unregister(fep->ptp_clock);
2279 if (fep->clk_enet_out)
2280 clk_disable_unprepare(fep->clk_enet_out);
2281 clk_disable_unprepare(fep->clk_ipg);
2282 clk_disable_unprepare(fep->clk_ahb);
2283 free_netdev(ndev);
2284
2285 return 0;
2286}
2287
2288#ifdef CONFIG_PM_SLEEP
2289static int
2290fec_suspend(struct device *dev)
2291{
2292 struct net_device *ndev = dev_get_drvdata(dev);
2293 struct fec_enet_private *fep = netdev_priv(ndev);
2294
2295 if (netif_running(ndev)) {
2296 fec_stop(ndev);
2297 netif_device_detach(ndev);
2298 }
2299 if (fep->clk_ptp)
2300 clk_disable_unprepare(fep->clk_ptp);
2301 if (fep->clk_enet_out)
2302 clk_disable_unprepare(fep->clk_enet_out);
2303 clk_disable_unprepare(fep->clk_ipg);
2304 clk_disable_unprepare(fep->clk_ahb);
2305
2306 if (fep->reg_phy)
2307 regulator_disable(fep->reg_phy);
2308
2309 return 0;
2310}
2311
2312static int
2313fec_resume(struct device *dev)
2314{
2315 struct net_device *ndev = dev_get_drvdata(dev);
2316 struct fec_enet_private *fep = netdev_priv(ndev);
2317 int ret;
2318
2319 if (fep->reg_phy) {
2320 ret = regulator_enable(fep->reg_phy);
2321 if (ret)
2322 return ret;
2323 }
2324
2325 ret = clk_prepare_enable(fep->clk_ahb);
2326 if (ret)
2327 goto failed_clk_ahb;
2328
2329 ret = clk_prepare_enable(fep->clk_ipg);
2330 if (ret)
2331 goto failed_clk_ipg;
2332
2333 if (fep->clk_enet_out) {
2334 ret = clk_prepare_enable(fep->clk_enet_out);
2335 if (ret)
2336 goto failed_clk_enet_out;
2337 }
2338
2339 if (fep->clk_ptp) {
2340 ret = clk_prepare_enable(fep->clk_ptp);
2341 if (ret)
2342 goto failed_clk_ptp;
2343 }
2344
2345 if (netif_running(ndev)) {
2346 fec_restart(ndev, fep->full_duplex);
2347 netif_device_attach(ndev);
2348 }
2349
2350 return 0;
2351
2352failed_clk_ptp:
2353 if (fep->clk_enet_out)
2354 clk_disable_unprepare(fep->clk_enet_out);
2355failed_clk_enet_out:
2356 clk_disable_unprepare(fep->clk_ipg);
2357failed_clk_ipg:
2358 clk_disable_unprepare(fep->clk_ahb);
2359failed_clk_ahb:
2360 if (fep->reg_phy)
2361 regulator_disable(fep->reg_phy);
2362 return ret;
2363}
2364#endif /* CONFIG_PM_SLEEP */
2365
2366static SIMPLE_DEV_PM_OPS(fec_pm_ops, fec_suspend, fec_resume);
2367
2368static struct platform_driver fec_driver = {
2369 .driver = {
2370 .name = DRIVER_NAME,
2371 .owner = THIS_MODULE,
2372 .pm = &fec_pm_ops,
2373 .of_match_table = fec_dt_ids,
2374 },
2375 .id_table = fec_devtype,
2376 .probe = fec_probe,
2377 .remove = fec_drv_remove,
2378};
2379
2380module_platform_driver(fec_driver);
2381
2382MODULE_ALIAS("platform:"DRIVER_NAME);
2383MODULE_LICENSE("GPL");