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1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * Synopsys DesignWare I2C adapter driver.
4 *
5 * Based on the TI DAVINCI I2C adapter driver.
6 *
7 * Copyright (C) 2006 Texas Instruments.
8 * Copyright (C) 2007 MontaVista Software Inc.
9 * Copyright (C) 2009 Provigent Ltd.
10 */
11
12#define DEFAULT_SYMBOL_NAMESPACE "I2C_DW_COMMON"
13
14#include <linux/acpi.h>
15#include <linux/clk.h>
16#include <linux/delay.h>
17#include <linux/device.h>
18#include <linux/err.h>
19#include <linux/errno.h>
20#include <linux/export.h>
21#include <linux/i2c.h>
22#include <linux/interrupt.h>
23#include <linux/io.h>
24#include <linux/kernel.h>
25#include <linux/module.h>
26#include <linux/of.h>
27#include <linux/pm.h>
28#include <linux/pm_runtime.h>
29#include <linux/property.h>
30#include <linux/regmap.h>
31#include <linux/swab.h>
32#include <linux/types.h>
33#include <linux/units.h>
34
35#include "i2c-designware-core.h"
36
37static const char *const abort_sources[] = {
38 [ABRT_7B_ADDR_NOACK] =
39 "slave address not acknowledged (7bit mode)",
40 [ABRT_10ADDR1_NOACK] =
41 "first address byte not acknowledged (10bit mode)",
42 [ABRT_10ADDR2_NOACK] =
43 "second address byte not acknowledged (10bit mode)",
44 [ABRT_TXDATA_NOACK] =
45 "data not acknowledged",
46 [ABRT_GCALL_NOACK] =
47 "no acknowledgement for a general call",
48 [ABRT_GCALL_READ] =
49 "read after general call",
50 [ABRT_SBYTE_ACKDET] =
51 "start byte acknowledged",
52 [ABRT_SBYTE_NORSTRT] =
53 "trying to send start byte when restart is disabled",
54 [ABRT_10B_RD_NORSTRT] =
55 "trying to read when restart is disabled (10bit mode)",
56 [ABRT_MASTER_DIS] =
57 "trying to use disabled adapter",
58 [ARB_LOST] =
59 "lost arbitration",
60 [ABRT_SLAVE_FLUSH_TXFIFO] =
61 "read command so flush old data in the TX FIFO",
62 [ABRT_SLAVE_ARBLOST] =
63 "slave lost the bus while transmitting data to a remote master",
64 [ABRT_SLAVE_RD_INTX] =
65 "incorrect slave-transmitter mode configuration",
66};
67
68static int dw_reg_read(void *context, unsigned int reg, unsigned int *val)
69{
70 struct dw_i2c_dev *dev = context;
71
72 *val = readl(dev->base + reg);
73
74 return 0;
75}
76
77static int dw_reg_write(void *context, unsigned int reg, unsigned int val)
78{
79 struct dw_i2c_dev *dev = context;
80
81 writel(val, dev->base + reg);
82
83 return 0;
84}
85
86static int dw_reg_read_swab(void *context, unsigned int reg, unsigned int *val)
87{
88 struct dw_i2c_dev *dev = context;
89
90 *val = swab32(readl(dev->base + reg));
91
92 return 0;
93}
94
95static int dw_reg_write_swab(void *context, unsigned int reg, unsigned int val)
96{
97 struct dw_i2c_dev *dev = context;
98
99 writel(swab32(val), dev->base + reg);
100
101 return 0;
102}
103
104static int dw_reg_read_word(void *context, unsigned int reg, unsigned int *val)
105{
106 struct dw_i2c_dev *dev = context;
107
108 *val = readw(dev->base + reg) |
109 (readw(dev->base + reg + 2) << 16);
110
111 return 0;
112}
113
114static int dw_reg_write_word(void *context, unsigned int reg, unsigned int val)
115{
116 struct dw_i2c_dev *dev = context;
117
118 writew(val, dev->base + reg);
119 writew(val >> 16, dev->base + reg + 2);
120
121 return 0;
122}
123
124/**
125 * i2c_dw_init_regmap() - Initialize registers map
126 * @dev: device private data
127 *
128 * Autodetects needed register access mode and creates the regmap with
129 * corresponding read/write callbacks. This must be called before doing any
130 * other register access.
131 *
132 * Return: 0 on success, or negative errno otherwise.
133 */
134int i2c_dw_init_regmap(struct dw_i2c_dev *dev)
135{
136 struct regmap_config map_cfg = {
137 .reg_bits = 32,
138 .val_bits = 32,
139 .reg_stride = 4,
140 .disable_locking = true,
141 .reg_read = dw_reg_read,
142 .reg_write = dw_reg_write,
143 .max_register = DW_IC_COMP_TYPE,
144 };
145 u32 reg;
146 int ret;
147
148 /*
149 * Skip detecting the registers map configuration if the regmap has
150 * already been provided by a higher code.
151 */
152 if (dev->map)
153 return 0;
154
155 ret = i2c_dw_acquire_lock(dev);
156 if (ret)
157 return ret;
158
159 reg = readl(dev->base + DW_IC_COMP_TYPE);
160 i2c_dw_release_lock(dev);
161
162 if ((dev->flags & MODEL_MASK) == MODEL_AMD_NAVI_GPU)
163 map_cfg.max_register = AMD_UCSI_INTR_REG;
164
165 if (reg == swab32(DW_IC_COMP_TYPE_VALUE)) {
166 map_cfg.reg_read = dw_reg_read_swab;
167 map_cfg.reg_write = dw_reg_write_swab;
168 } else if (reg == (DW_IC_COMP_TYPE_VALUE & 0x0000ffff)) {
169 map_cfg.reg_read = dw_reg_read_word;
170 map_cfg.reg_write = dw_reg_write_word;
171 } else if (reg != DW_IC_COMP_TYPE_VALUE) {
172 dev_err(dev->dev,
173 "Unknown Synopsys component type: 0x%08x\n", reg);
174 return -ENODEV;
175 }
176
177 /*
178 * Note we'll check the return value of the regmap IO accessors only
179 * at the probe stage. The rest of the code won't do this because
180 * basically we have MMIO-based regmap, so none of the read/write methods
181 * can fail.
182 */
183 dev->map = devm_regmap_init(dev->dev, NULL, dev, &map_cfg);
184 if (IS_ERR(dev->map)) {
185 dev_err(dev->dev, "Failed to init the registers map\n");
186 return PTR_ERR(dev->map);
187 }
188
189 return 0;
190}
191
192static const u32 supported_speeds[] = {
193 I2C_MAX_HIGH_SPEED_MODE_FREQ,
194 I2C_MAX_FAST_MODE_PLUS_FREQ,
195 I2C_MAX_FAST_MODE_FREQ,
196 I2C_MAX_STANDARD_MODE_FREQ,
197};
198
199static int i2c_dw_validate_speed(struct dw_i2c_dev *dev)
200{
201 struct i2c_timings *t = &dev->timings;
202 unsigned int i;
203
204 /*
205 * Only standard mode at 100kHz, fast mode at 400kHz,
206 * fast mode plus at 1MHz and high speed mode at 3.4MHz are supported.
207 */
208 for (i = 0; i < ARRAY_SIZE(supported_speeds); i++) {
209 if (t->bus_freq_hz == supported_speeds[i])
210 return 0;
211 }
212
213 dev_err(dev->dev,
214 "%d Hz is unsupported, only 100kHz, 400kHz, 1MHz and 3.4MHz are supported\n",
215 t->bus_freq_hz);
216
217 return -EINVAL;
218}
219
220#ifdef CONFIG_OF
221
222#include <linux/platform_device.h>
223
224#define MSCC_ICPU_CFG_TWI_DELAY 0x0
225#define MSCC_ICPU_CFG_TWI_DELAY_ENABLE BIT(0)
226#define MSCC_ICPU_CFG_TWI_SPIKE_FILTER 0x4
227
228static int mscc_twi_set_sda_hold_time(struct dw_i2c_dev *dev)
229{
230 writel((dev->sda_hold_time << 1) | MSCC_ICPU_CFG_TWI_DELAY_ENABLE,
231 dev->ext + MSCC_ICPU_CFG_TWI_DELAY);
232
233 return 0;
234}
235
236static void i2c_dw_of_configure(struct device *device)
237{
238 struct platform_device *pdev = to_platform_device(device);
239 struct dw_i2c_dev *dev = dev_get_drvdata(device);
240
241 switch (dev->flags & MODEL_MASK) {
242 case MODEL_MSCC_OCELOT:
243 dev->ext = devm_platform_ioremap_resource(pdev, 1);
244 if (!IS_ERR(dev->ext))
245 dev->set_sda_hold_time = mscc_twi_set_sda_hold_time;
246 break;
247 default:
248 break;
249 }
250}
251
252#else /* CONFIG_OF */
253
254static inline void i2c_dw_of_configure(struct device *device) { }
255
256#endif /* CONFIG_OF */
257
258#ifdef CONFIG_ACPI
259
260#include <linux/dmi.h>
261
262/*
263 * The HCNT/LCNT information coming from ACPI should be the most accurate
264 * for given platform. However, some systems get it wrong. On such systems
265 * we get better results by calculating those based on the input clock.
266 */
267static const struct dmi_system_id i2c_dw_no_acpi_params[] = {
268 {
269 .ident = "Dell Inspiron 7348",
270 .matches = {
271 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
272 DMI_MATCH(DMI_PRODUCT_NAME, "Inspiron 7348"),
273 },
274 },
275 {}
276};
277
278static void i2c_dw_acpi_params(struct device *device, char method[],
279 u16 *hcnt, u16 *lcnt, u32 *sda_hold)
280{
281 struct acpi_buffer buf = { ACPI_ALLOCATE_BUFFER };
282 acpi_handle handle = ACPI_HANDLE(device);
283 union acpi_object *obj;
284
285 if (dmi_check_system(i2c_dw_no_acpi_params))
286 return;
287
288 if (ACPI_FAILURE(acpi_evaluate_object(handle, method, NULL, &buf)))
289 return;
290
291 obj = (union acpi_object *)buf.pointer;
292 if (obj->type == ACPI_TYPE_PACKAGE && obj->package.count == 3) {
293 const union acpi_object *objs = obj->package.elements;
294
295 *hcnt = (u16)objs[0].integer.value;
296 *lcnt = (u16)objs[1].integer.value;
297 *sda_hold = (u32)objs[2].integer.value;
298 }
299
300 kfree(buf.pointer);
301}
302
303static void i2c_dw_acpi_configure(struct device *device)
304{
305 struct dw_i2c_dev *dev = dev_get_drvdata(device);
306 struct i2c_timings *t = &dev->timings;
307 u32 ss_ht = 0, fp_ht = 0, hs_ht = 0, fs_ht = 0;
308
309 /*
310 * Try to get SDA hold time and *CNT values from an ACPI method for
311 * selected speed modes.
312 */
313 i2c_dw_acpi_params(device, "SSCN", &dev->ss_hcnt, &dev->ss_lcnt, &ss_ht);
314 i2c_dw_acpi_params(device, "FMCN", &dev->fs_hcnt, &dev->fs_lcnt, &fs_ht);
315 i2c_dw_acpi_params(device, "FPCN", &dev->fp_hcnt, &dev->fp_lcnt, &fp_ht);
316 i2c_dw_acpi_params(device, "HSCN", &dev->hs_hcnt, &dev->hs_lcnt, &hs_ht);
317
318 switch (t->bus_freq_hz) {
319 case I2C_MAX_STANDARD_MODE_FREQ:
320 dev->sda_hold_time = ss_ht;
321 break;
322 case I2C_MAX_FAST_MODE_PLUS_FREQ:
323 dev->sda_hold_time = fp_ht;
324 break;
325 case I2C_MAX_HIGH_SPEED_MODE_FREQ:
326 dev->sda_hold_time = hs_ht;
327 break;
328 case I2C_MAX_FAST_MODE_FREQ:
329 default:
330 dev->sda_hold_time = fs_ht;
331 break;
332 }
333}
334
335static u32 i2c_dw_acpi_round_bus_speed(struct device *device)
336{
337 u32 acpi_speed;
338 int i;
339
340 acpi_speed = i2c_acpi_find_bus_speed(device);
341 /*
342 * Some DSDTs use a non standard speed, round down to the lowest
343 * standard speed.
344 */
345 for (i = 0; i < ARRAY_SIZE(supported_speeds); i++) {
346 if (acpi_speed >= supported_speeds[i])
347 return supported_speeds[i];
348 }
349
350 return 0;
351}
352
353#else /* CONFIG_ACPI */
354
355static inline void i2c_dw_acpi_configure(struct device *device) { }
356
357static inline u32 i2c_dw_acpi_round_bus_speed(struct device *device) { return 0; }
358
359#endif /* CONFIG_ACPI */
360
361static void i2c_dw_adjust_bus_speed(struct dw_i2c_dev *dev)
362{
363 u32 acpi_speed = i2c_dw_acpi_round_bus_speed(dev->dev);
364 struct i2c_timings *t = &dev->timings;
365
366 /*
367 * Find bus speed from the "clock-frequency" device property, ACPI
368 * or by using fast mode if neither is set.
369 */
370 if (acpi_speed && t->bus_freq_hz)
371 t->bus_freq_hz = min(t->bus_freq_hz, acpi_speed);
372 else if (acpi_speed || t->bus_freq_hz)
373 t->bus_freq_hz = max(t->bus_freq_hz, acpi_speed);
374 else
375 t->bus_freq_hz = I2C_MAX_FAST_MODE_FREQ;
376}
377
378int i2c_dw_fw_parse_and_configure(struct dw_i2c_dev *dev)
379{
380 struct i2c_timings *t = &dev->timings;
381 struct device *device = dev->dev;
382 struct fwnode_handle *fwnode = dev_fwnode(device);
383
384 i2c_parse_fw_timings(device, t, false);
385
386 if (device_property_read_u32(device, "snps,bus-capacitance-pf", &dev->bus_capacitance_pF))
387 dev->bus_capacitance_pF = 100;
388
389 dev->clk_freq_optimized = device_property_read_bool(device, "snps,clk-freq-optimized");
390
391 i2c_dw_adjust_bus_speed(dev);
392
393 if (is_of_node(fwnode))
394 i2c_dw_of_configure(device);
395 else if (is_acpi_node(fwnode))
396 i2c_dw_acpi_configure(device);
397
398 return i2c_dw_validate_speed(dev);
399}
400EXPORT_SYMBOL_GPL(i2c_dw_fw_parse_and_configure);
401
402static u32 i2c_dw_read_scl_reg(struct dw_i2c_dev *dev, u32 reg)
403{
404 u32 val;
405 int ret;
406
407 ret = i2c_dw_acquire_lock(dev);
408 if (ret)
409 return 0;
410
411 ret = regmap_read(dev->map, reg, &val);
412 i2c_dw_release_lock(dev);
413
414 return ret ? 0 : val;
415}
416
417u32 i2c_dw_scl_hcnt(struct dw_i2c_dev *dev, unsigned int reg, u32 ic_clk,
418 u32 tSYMBOL, u32 tf, int offset)
419{
420 if (!ic_clk)
421 return i2c_dw_read_scl_reg(dev, reg);
422
423 /*
424 * Conditional expression:
425 *
426 * IC_[FS]S_SCL_HCNT + 3 >= IC_CLK * (tHD;STA + tf)
427 *
428 * This is just experimental rule; the tHD;STA period turned
429 * out to be proportinal to (_HCNT + 3). With this setting,
430 * we could meet both tHIGH and tHD;STA timing specs.
431 *
432 * If unsure, you'd better to take this alternative.
433 *
434 * The reason why we need to take into account "tf" here,
435 * is the same as described in i2c_dw_scl_lcnt().
436 */
437 return DIV_ROUND_CLOSEST_ULL((u64)ic_clk * (tSYMBOL + tf), MICRO) - 3 + offset;
438}
439
440u32 i2c_dw_scl_lcnt(struct dw_i2c_dev *dev, unsigned int reg, u32 ic_clk,
441 u32 tLOW, u32 tf, int offset)
442{
443 if (!ic_clk)
444 return i2c_dw_read_scl_reg(dev, reg);
445
446 /*
447 * Conditional expression:
448 *
449 * IC_[FS]S_SCL_LCNT + 1 >= IC_CLK * (tLOW + tf)
450 *
451 * DW I2C core starts counting the SCL CNTs for the LOW period
452 * of the SCL clock (tLOW) as soon as it pulls the SCL line.
453 * In order to meet the tLOW timing spec, we need to take into
454 * account the fall time of SCL signal (tf). Default tf value
455 * should be 0.3 us, for safety.
456 */
457 return DIV_ROUND_CLOSEST_ULL((u64)ic_clk * (tLOW + tf), MICRO) - 1 + offset;
458}
459
460int i2c_dw_set_sda_hold(struct dw_i2c_dev *dev)
461{
462 unsigned int reg;
463 int ret;
464
465 ret = i2c_dw_acquire_lock(dev);
466 if (ret)
467 return ret;
468
469 /* Configure SDA Hold Time if required */
470 ret = regmap_read(dev->map, DW_IC_COMP_VERSION, ®);
471 if (ret)
472 goto err_release_lock;
473
474 if (reg >= DW_IC_SDA_HOLD_MIN_VERS) {
475 if (!dev->sda_hold_time) {
476 /* Keep previous hold time setting if no one set it */
477 ret = regmap_read(dev->map, DW_IC_SDA_HOLD,
478 &dev->sda_hold_time);
479 if (ret)
480 goto err_release_lock;
481 }
482
483 /*
484 * Workaround for avoiding TX arbitration lost in case I2C
485 * slave pulls SDA down "too quickly" after falling edge of
486 * SCL by enabling non-zero SDA RX hold. Specification says it
487 * extends incoming SDA low to high transition while SCL is
488 * high but it appears to help also above issue.
489 */
490 if (!(dev->sda_hold_time & DW_IC_SDA_HOLD_RX_MASK))
491 dev->sda_hold_time |= 1 << DW_IC_SDA_HOLD_RX_SHIFT;
492
493 dev_dbg(dev->dev, "SDA Hold Time TX:RX = %d:%d\n",
494 dev->sda_hold_time & ~(u32)DW_IC_SDA_HOLD_RX_MASK,
495 dev->sda_hold_time >> DW_IC_SDA_HOLD_RX_SHIFT);
496 } else if (dev->set_sda_hold_time) {
497 dev->set_sda_hold_time(dev);
498 } else if (dev->sda_hold_time) {
499 dev_warn(dev->dev,
500 "Hardware too old to adjust SDA hold time.\n");
501 dev->sda_hold_time = 0;
502 }
503
504err_release_lock:
505 i2c_dw_release_lock(dev);
506
507 return ret;
508}
509
510void __i2c_dw_disable(struct dw_i2c_dev *dev)
511{
512 struct i2c_timings *t = &dev->timings;
513 unsigned int raw_intr_stats, ic_stats;
514 unsigned int enable;
515 int timeout = 100;
516 bool abort_needed;
517 unsigned int status;
518 int ret;
519
520 regmap_read(dev->map, DW_IC_RAW_INTR_STAT, &raw_intr_stats);
521 regmap_read(dev->map, DW_IC_STATUS, &ic_stats);
522 regmap_read(dev->map, DW_IC_ENABLE, &enable);
523
524 abort_needed = (raw_intr_stats & DW_IC_INTR_MST_ON_HOLD) ||
525 (ic_stats & DW_IC_STATUS_MASTER_HOLD_TX_FIFO_EMPTY);
526 if (abort_needed) {
527 if (!(enable & DW_IC_ENABLE_ENABLE)) {
528 regmap_write(dev->map, DW_IC_ENABLE, DW_IC_ENABLE_ENABLE);
529 /*
530 * Wait 10 times the signaling period of the highest I2C
531 * transfer supported by the driver (for 400KHz this is
532 * 25us) to ensure the I2C ENABLE bit is already set
533 * as described in the DesignWare I2C databook.
534 */
535 fsleep(DIV_ROUND_CLOSEST_ULL(10 * MICRO, t->bus_freq_hz));
536 /* Set ENABLE bit before setting ABORT */
537 enable |= DW_IC_ENABLE_ENABLE;
538 }
539
540 regmap_write(dev->map, DW_IC_ENABLE, enable | DW_IC_ENABLE_ABORT);
541 ret = regmap_read_poll_timeout(dev->map, DW_IC_ENABLE, enable,
542 !(enable & DW_IC_ENABLE_ABORT), 10,
543 100);
544 if (ret)
545 dev_err(dev->dev, "timeout while trying to abort current transfer\n");
546 }
547
548 do {
549 __i2c_dw_disable_nowait(dev);
550 /*
551 * The enable status register may be unimplemented, but
552 * in that case this test reads zero and exits the loop.
553 */
554 regmap_read(dev->map, DW_IC_ENABLE_STATUS, &status);
555 if ((status & 1) == 0)
556 return;
557
558 /*
559 * Wait 10 times the signaling period of the highest I2C
560 * transfer supported by the driver (for 400kHz this is
561 * 25us) as described in the DesignWare I2C databook.
562 */
563 usleep_range(25, 250);
564 } while (timeout--);
565
566 dev_warn(dev->dev, "timeout in disabling adapter\n");
567}
568
569u32 i2c_dw_clk_rate(struct dw_i2c_dev *dev)
570{
571 /*
572 * Clock is not necessary if we got LCNT/HCNT values directly from
573 * the platform code.
574 */
575 if (WARN_ON_ONCE(!dev->get_clk_rate_khz))
576 return 0;
577 return dev->get_clk_rate_khz(dev);
578}
579
580int i2c_dw_prepare_clk(struct dw_i2c_dev *dev, bool prepare)
581{
582 int ret;
583
584 if (prepare) {
585 /* Optional interface clock */
586 ret = clk_prepare_enable(dev->pclk);
587 if (ret)
588 return ret;
589
590 ret = clk_prepare_enable(dev->clk);
591 if (ret)
592 clk_disable_unprepare(dev->pclk);
593
594 return ret;
595 }
596
597 clk_disable_unprepare(dev->clk);
598 clk_disable_unprepare(dev->pclk);
599
600 return 0;
601}
602EXPORT_SYMBOL_GPL(i2c_dw_prepare_clk);
603
604int i2c_dw_acquire_lock(struct dw_i2c_dev *dev)
605{
606 int ret;
607
608 if (!dev->acquire_lock)
609 return 0;
610
611 ret = dev->acquire_lock();
612 if (!ret)
613 return 0;
614
615 dev_err(dev->dev, "couldn't acquire bus ownership\n");
616
617 return ret;
618}
619
620void i2c_dw_release_lock(struct dw_i2c_dev *dev)
621{
622 if (dev->release_lock)
623 dev->release_lock();
624}
625
626/*
627 * Waiting for bus not busy
628 */
629int i2c_dw_wait_bus_not_busy(struct dw_i2c_dev *dev)
630{
631 unsigned int status;
632 int ret;
633
634 ret = regmap_read_poll_timeout(dev->map, DW_IC_STATUS, status,
635 !(status & DW_IC_STATUS_ACTIVITY),
636 1100, 20000);
637 if (ret) {
638 dev_warn(dev->dev, "timeout waiting for bus ready\n");
639
640 i2c_recover_bus(&dev->adapter);
641
642 regmap_read(dev->map, DW_IC_STATUS, &status);
643 if (!(status & DW_IC_STATUS_ACTIVITY))
644 ret = 0;
645 }
646
647 return ret;
648}
649
650int i2c_dw_handle_tx_abort(struct dw_i2c_dev *dev)
651{
652 unsigned long abort_source = dev->abort_source;
653 int i;
654
655 if (abort_source & DW_IC_TX_ABRT_NOACK) {
656 for_each_set_bit(i, &abort_source, ARRAY_SIZE(abort_sources))
657 dev_dbg(dev->dev,
658 "%s: %s\n", __func__, abort_sources[i]);
659 return -EREMOTEIO;
660 }
661
662 for_each_set_bit(i, &abort_source, ARRAY_SIZE(abort_sources))
663 dev_err(dev->dev, "%s: %s\n", __func__, abort_sources[i]);
664
665 if (abort_source & DW_IC_TX_ARB_LOST)
666 return -EAGAIN;
667 if (abort_source & DW_IC_TX_ABRT_GCALL_READ)
668 return -EINVAL; /* wrong msgs[] data */
669
670 return -EIO;
671}
672
673int i2c_dw_set_fifo_size(struct dw_i2c_dev *dev)
674{
675 u32 tx_fifo_depth, rx_fifo_depth;
676 unsigned int param;
677 int ret;
678
679 /* DW_IC_COMP_PARAM_1 not implement for IP issue */
680 if ((dev->flags & MODEL_MASK) == MODEL_WANGXUN_SP) {
681 dev->tx_fifo_depth = TXGBE_TX_FIFO_DEPTH;
682 dev->rx_fifo_depth = TXGBE_RX_FIFO_DEPTH;
683
684 return 0;
685 }
686
687 /*
688 * Try to detect the FIFO depth if not set by interface driver,
689 * the depth could be from 2 to 256 from HW spec.
690 */
691 ret = i2c_dw_acquire_lock(dev);
692 if (ret)
693 return ret;
694
695 ret = regmap_read(dev->map, DW_IC_COMP_PARAM_1, ¶m);
696 i2c_dw_release_lock(dev);
697 if (ret)
698 return ret;
699
700 tx_fifo_depth = ((param >> 16) & 0xff) + 1;
701 rx_fifo_depth = ((param >> 8) & 0xff) + 1;
702 if (!dev->tx_fifo_depth) {
703 dev->tx_fifo_depth = tx_fifo_depth;
704 dev->rx_fifo_depth = rx_fifo_depth;
705 } else if (tx_fifo_depth >= 2) {
706 dev->tx_fifo_depth = min_t(u32, dev->tx_fifo_depth,
707 tx_fifo_depth);
708 dev->rx_fifo_depth = min_t(u32, dev->rx_fifo_depth,
709 rx_fifo_depth);
710 }
711
712 return 0;
713}
714
715u32 i2c_dw_func(struct i2c_adapter *adap)
716{
717 struct dw_i2c_dev *dev = i2c_get_adapdata(adap);
718
719 return dev->functionality;
720}
721
722void i2c_dw_disable(struct dw_i2c_dev *dev)
723{
724 unsigned int dummy;
725 int ret;
726
727 ret = i2c_dw_acquire_lock(dev);
728 if (ret)
729 return;
730
731 /* Disable controller */
732 __i2c_dw_disable(dev);
733
734 /* Disable all interrupts */
735 __i2c_dw_write_intr_mask(dev, 0);
736 regmap_read(dev->map, DW_IC_CLR_INTR, &dummy);
737
738 i2c_dw_release_lock(dev);
739}
740EXPORT_SYMBOL_GPL(i2c_dw_disable);
741
742int i2c_dw_probe(struct dw_i2c_dev *dev)
743{
744 device_set_node(&dev->adapter.dev, dev_fwnode(dev->dev));
745
746 switch (dev->mode) {
747 case DW_IC_SLAVE:
748 return i2c_dw_probe_slave(dev);
749 case DW_IC_MASTER:
750 return i2c_dw_probe_master(dev);
751 default:
752 dev_err(dev->dev, "Wrong operation mode: %d\n", dev->mode);
753 return -EINVAL;
754 }
755}
756EXPORT_SYMBOL_GPL(i2c_dw_probe);
757
758static int i2c_dw_prepare(struct device *device)
759{
760 /*
761 * If the ACPI companion device object is present for this device,
762 * it may be accessed during suspend and resume of other devices via
763 * I2C operation regions, so tell the PM core and middle layers to
764 * avoid skipping system suspend/resume callbacks for it in that case.
765 */
766 return !has_acpi_companion(device);
767}
768
769static int i2c_dw_runtime_suspend(struct device *device)
770{
771 struct dw_i2c_dev *dev = dev_get_drvdata(device);
772
773 if (dev->shared_with_punit)
774 return 0;
775
776 i2c_dw_disable(dev);
777 i2c_dw_prepare_clk(dev, false);
778
779 return 0;
780}
781
782static int i2c_dw_suspend(struct device *device)
783{
784 struct dw_i2c_dev *dev = dev_get_drvdata(device);
785
786 i2c_mark_adapter_suspended(&dev->adapter);
787
788 return i2c_dw_runtime_suspend(device);
789}
790
791static int i2c_dw_runtime_resume(struct device *device)
792{
793 struct dw_i2c_dev *dev = dev_get_drvdata(device);
794
795 if (!dev->shared_with_punit)
796 i2c_dw_prepare_clk(dev, true);
797
798 dev->init(dev);
799
800 return 0;
801}
802
803static int i2c_dw_resume(struct device *device)
804{
805 struct dw_i2c_dev *dev = dev_get_drvdata(device);
806
807 i2c_dw_runtime_resume(device);
808 i2c_mark_adapter_resumed(&dev->adapter);
809
810 return 0;
811}
812
813EXPORT_GPL_DEV_PM_OPS(i2c_dw_dev_pm_ops) = {
814 .prepare = pm_sleep_ptr(i2c_dw_prepare),
815 LATE_SYSTEM_SLEEP_PM_OPS(i2c_dw_suspend, i2c_dw_resume)
816 RUNTIME_PM_OPS(i2c_dw_runtime_suspend, i2c_dw_runtime_resume, NULL)
817};
818
819MODULE_DESCRIPTION("Synopsys DesignWare I2C bus adapter core");
820MODULE_LICENSE("GPL");