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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Intel IO-APIC support for multi-Pentium hosts.
4 *
5 * Copyright (C) 1997, 1998, 1999, 2000, 2009 Ingo Molnar, Hajnalka Szabo
6 *
7 * Many thanks to Stig Venaas for trying out countless experimental
8 * patches and reporting/debugging problems patiently!
9 *
10 * (c) 1999, Multiple IO-APIC support, developed by
11 * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
12 * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
13 * further tested and cleaned up by Zach Brown <zab@redhat.com>
14 * and Ingo Molnar <mingo@redhat.com>
15 *
16 * Fixes
17 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
18 * thanks to Eric Gilmore
19 * and Rolf G. Tews
20 * for testing these extensively
21 * Paul Diefenbaugh : Added full ACPI support
22 *
23 * Historical information which is worth to be preserved:
24 *
25 * - SiS APIC rmw bug:
26 *
27 * We used to have a workaround for a bug in SiS chips which
28 * required to rewrite the index register for a read-modify-write
29 * operation as the chip lost the index information which was
30 * setup for the read already. We cache the data now, so that
31 * workaround has been removed.
32 */
33
34#include <linux/mm.h>
35#include <linux/interrupt.h>
36#include <linux/irq.h>
37#include <linux/init.h>
38#include <linux/delay.h>
39#include <linux/sched.h>
40#include <linux/pci.h>
41#include <linux/mc146818rtc.h>
42#include <linux/compiler.h>
43#include <linux/acpi.h>
44#include <linux/export.h>
45#include <linux/syscore_ops.h>
46#include <linux/freezer.h>
47#include <linux/kthread.h>
48#include <linux/jiffies.h> /* time_after() */
49#include <linux/slab.h>
50#include <linux/memblock.h>
51#include <linux/msi.h>
52
53#include <asm/irqdomain.h>
54#include <asm/io.h>
55#include <asm/smp.h>
56#include <asm/cpu.h>
57#include <asm/desc.h>
58#include <asm/proto.h>
59#include <asm/acpi.h>
60#include <asm/dma.h>
61#include <asm/timer.h>
62#include <asm/time.h>
63#include <asm/i8259.h>
64#include <asm/setup.h>
65#include <asm/irq_remapping.h>
66#include <asm/hw_irq.h>
67#include <asm/apic.h>
68#include <asm/pgtable.h>
69#include <asm/x86_init.h>
70
71#define for_each_ioapic(idx) \
72 for ((idx) = 0; (idx) < nr_ioapics; (idx)++)
73#define for_each_ioapic_reverse(idx) \
74 for ((idx) = nr_ioapics - 1; (idx) >= 0; (idx)--)
75#define for_each_pin(idx, pin) \
76 for ((pin) = 0; (pin) < ioapics[(idx)].nr_registers; (pin)++)
77#define for_each_ioapic_pin(idx, pin) \
78 for_each_ioapic((idx)) \
79 for_each_pin((idx), (pin))
80#define for_each_irq_pin(entry, head) \
81 list_for_each_entry(entry, &head, list)
82
83static DEFINE_RAW_SPINLOCK(ioapic_lock);
84static DEFINE_MUTEX(ioapic_mutex);
85static unsigned int ioapic_dynirq_base;
86static int ioapic_initialized;
87
88struct irq_pin_list {
89 struct list_head list;
90 int apic, pin;
91};
92
93struct mp_chip_data {
94 struct list_head irq_2_pin;
95 struct IO_APIC_route_entry entry;
96 bool is_level;
97 bool active_low;
98 bool isa_irq;
99 u32 count;
100};
101
102struct mp_ioapic_gsi {
103 u32 gsi_base;
104 u32 gsi_end;
105};
106
107static struct ioapic {
108 /* # of IRQ routing registers */
109 int nr_registers;
110 /* Saved state during suspend/resume, or while enabling intr-remap. */
111 struct IO_APIC_route_entry *saved_registers;
112 /* I/O APIC config */
113 struct mpc_ioapic mp_config;
114 /* IO APIC gsi routing info */
115 struct mp_ioapic_gsi gsi_config;
116 struct ioapic_domain_cfg irqdomain_cfg;
117 struct irq_domain *irqdomain;
118 struct resource *iomem_res;
119} ioapics[MAX_IO_APICS];
120
121#define mpc_ioapic_ver(ioapic_idx) ioapics[ioapic_idx].mp_config.apicver
122
123int mpc_ioapic_id(int ioapic_idx)
124{
125 return ioapics[ioapic_idx].mp_config.apicid;
126}
127
128unsigned int mpc_ioapic_addr(int ioapic_idx)
129{
130 return ioapics[ioapic_idx].mp_config.apicaddr;
131}
132
133static inline struct mp_ioapic_gsi *mp_ioapic_gsi_routing(int ioapic_idx)
134{
135 return &ioapics[ioapic_idx].gsi_config;
136}
137
138static inline int mp_ioapic_pin_count(int ioapic)
139{
140 struct mp_ioapic_gsi *gsi_cfg = mp_ioapic_gsi_routing(ioapic);
141
142 return gsi_cfg->gsi_end - gsi_cfg->gsi_base + 1;
143}
144
145static inline u32 mp_pin_to_gsi(int ioapic, int pin)
146{
147 return mp_ioapic_gsi_routing(ioapic)->gsi_base + pin;
148}
149
150static inline bool mp_is_legacy_irq(int irq)
151{
152 return irq >= 0 && irq < nr_legacy_irqs();
153}
154
155static inline struct irq_domain *mp_ioapic_irqdomain(int ioapic)
156{
157 return ioapics[ioapic].irqdomain;
158}
159
160int nr_ioapics;
161
162/* The one past the highest gsi number used */
163u32 gsi_top;
164
165/* MP IRQ source entries */
166struct mpc_intsrc mp_irqs[MAX_IRQ_SOURCES];
167
168/* # of MP IRQ source entries */
169int mp_irq_entries;
170
171#ifdef CONFIG_EISA
172int mp_bus_id_to_type[MAX_MP_BUSSES];
173#endif
174
175DECLARE_BITMAP(mp_bus_not_pci, MAX_MP_BUSSES);
176
177bool ioapic_is_disabled __ro_after_init;
178
179/**
180 * disable_ioapic_support() - disables ioapic support at runtime
181 */
182void disable_ioapic_support(void)
183{
184#ifdef CONFIG_PCI
185 noioapicquirk = 1;
186 noioapicreroute = -1;
187#endif
188 ioapic_is_disabled = true;
189}
190
191static int __init parse_noapic(char *str)
192{
193 /* disable IO-APIC */
194 disable_ioapic_support();
195 return 0;
196}
197early_param("noapic", parse_noapic);
198
199/* Will be called in mpparse/ACPI codes for saving IRQ info */
200void mp_save_irq(struct mpc_intsrc *m)
201{
202 int i;
203
204 apic_pr_verbose("Int: type %d, pol %d, trig %d, bus %02x, IRQ %02x, APIC ID %x, APIC INT %02x\n",
205 m->irqtype, m->irqflag & 3, (m->irqflag >> 2) & 3, m->srcbus,
206 m->srcbusirq, m->dstapic, m->dstirq);
207
208 for (i = 0; i < mp_irq_entries; i++) {
209 if (!memcmp(&mp_irqs[i], m, sizeof(*m)))
210 return;
211 }
212
213 memcpy(&mp_irqs[mp_irq_entries], m, sizeof(*m));
214 if (++mp_irq_entries == MAX_IRQ_SOURCES)
215 panic("Max # of irq sources exceeded!!\n");
216}
217
218static void alloc_ioapic_saved_registers(int idx)
219{
220 size_t size;
221
222 if (ioapics[idx].saved_registers)
223 return;
224
225 size = sizeof(struct IO_APIC_route_entry) * ioapics[idx].nr_registers;
226 ioapics[idx].saved_registers = kzalloc(size, GFP_KERNEL);
227 if (!ioapics[idx].saved_registers)
228 pr_err("IOAPIC %d: suspend/resume impossible!\n", idx);
229}
230
231static void free_ioapic_saved_registers(int idx)
232{
233 kfree(ioapics[idx].saved_registers);
234 ioapics[idx].saved_registers = NULL;
235}
236
237int __init arch_early_ioapic_init(void)
238{
239 int i;
240
241 if (!nr_legacy_irqs())
242 io_apic_irqs = ~0UL;
243
244 for_each_ioapic(i)
245 alloc_ioapic_saved_registers(i);
246
247 return 0;
248}
249
250struct io_apic {
251 unsigned int index;
252 unsigned int unused[3];
253 unsigned int data;
254 unsigned int unused2[11];
255 unsigned int eoi;
256};
257
258static __attribute_const__ struct io_apic __iomem *io_apic_base(int idx)
259{
260 return (void __iomem *) __fix_to_virt(FIX_IO_APIC_BASE_0 + idx)
261 + (mpc_ioapic_addr(idx) & ~PAGE_MASK);
262}
263
264static inline void io_apic_eoi(unsigned int apic, unsigned int vector)
265{
266 struct io_apic __iomem *io_apic = io_apic_base(apic);
267
268 writel(vector, &io_apic->eoi);
269}
270
271unsigned int native_io_apic_read(unsigned int apic, unsigned int reg)
272{
273 struct io_apic __iomem *io_apic = io_apic_base(apic);
274
275 writel(reg, &io_apic->index);
276 return readl(&io_apic->data);
277}
278
279static void io_apic_write(unsigned int apic, unsigned int reg,
280 unsigned int value)
281{
282 struct io_apic __iomem *io_apic = io_apic_base(apic);
283
284 writel(reg, &io_apic->index);
285 writel(value, &io_apic->data);
286}
287
288static struct IO_APIC_route_entry __ioapic_read_entry(int apic, int pin)
289{
290 struct IO_APIC_route_entry entry;
291
292 entry.w1 = io_apic_read(apic, 0x10 + 2 * pin);
293 entry.w2 = io_apic_read(apic, 0x11 + 2 * pin);
294
295 return entry;
296}
297
298static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin)
299{
300 guard(raw_spinlock_irqsave)(&ioapic_lock);
301 return __ioapic_read_entry(apic, pin);
302}
303
304/*
305 * When we write a new IO APIC routing entry, we need to write the high
306 * word first! If the mask bit in the low word is clear, we will enable
307 * the interrupt, and we need to make sure the entry is fully populated
308 * before that happens.
309 */
310static void __ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
311{
312 io_apic_write(apic, 0x11 + 2*pin, e.w2);
313 io_apic_write(apic, 0x10 + 2*pin, e.w1);
314}
315
316static void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
317{
318 guard(raw_spinlock_irqsave)(&ioapic_lock);
319 __ioapic_write_entry(apic, pin, e);
320}
321
322/*
323 * When we mask an IO APIC routing entry, we need to write the low
324 * word first, in order to set the mask bit before we change the
325 * high bits!
326 */
327static void ioapic_mask_entry(int apic, int pin)
328{
329 struct IO_APIC_route_entry e = { .masked = true };
330
331 guard(raw_spinlock_irqsave)(&ioapic_lock);
332 io_apic_write(apic, 0x10 + 2*pin, e.w1);
333 io_apic_write(apic, 0x11 + 2*pin, e.w2);
334}
335
336/*
337 * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
338 * shared ISA-space IRQs, so we have to support them. We are super
339 * fast in the common case, and fast for shared ISA-space IRQs.
340 */
341static bool add_pin_to_irq_node(struct mp_chip_data *data, int node, int apic, int pin)
342{
343 struct irq_pin_list *entry;
344
345 /* Don't allow duplicates */
346 for_each_irq_pin(entry, data->irq_2_pin) {
347 if (entry->apic == apic && entry->pin == pin)
348 return true;
349 }
350
351 entry = kzalloc_node(sizeof(struct irq_pin_list), GFP_ATOMIC, node);
352 if (!entry) {
353 pr_err("Cannot allocate irq_pin_list (%d,%d,%d)\n", node, apic, pin);
354 return false;
355 }
356
357 entry->apic = apic;
358 entry->pin = pin;
359 list_add_tail(&entry->list, &data->irq_2_pin);
360 return true;
361}
362
363static void __remove_pin_from_irq(struct mp_chip_data *data, int apic, int pin)
364{
365 struct irq_pin_list *tmp, *entry;
366
367 list_for_each_entry_safe(entry, tmp, &data->irq_2_pin, list) {
368 if (entry->apic == apic && entry->pin == pin) {
369 list_del(&entry->list);
370 kfree(entry);
371 return;
372 }
373 }
374}
375
376static void io_apic_modify_irq(struct mp_chip_data *data, bool masked,
377 void (*final)(struct irq_pin_list *entry))
378{
379 struct irq_pin_list *entry;
380
381 data->entry.masked = masked;
382
383 for_each_irq_pin(entry, data->irq_2_pin) {
384 io_apic_write(entry->apic, 0x10 + 2 * entry->pin, data->entry.w1);
385 if (final)
386 final(entry);
387 }
388}
389
390/*
391 * Synchronize the IO-APIC and the CPU by doing a dummy read from the
392 * IO-APIC
393 */
394static void io_apic_sync(struct irq_pin_list *entry)
395{
396 struct io_apic __iomem *io_apic;
397
398 io_apic = io_apic_base(entry->apic);
399 readl(&io_apic->data);
400}
401
402static void mask_ioapic_irq(struct irq_data *irq_data)
403{
404 struct mp_chip_data *data = irq_data->chip_data;
405
406 guard(raw_spinlock_irqsave)(&ioapic_lock);
407 io_apic_modify_irq(data, true, &io_apic_sync);
408}
409
410static void __unmask_ioapic(struct mp_chip_data *data)
411{
412 io_apic_modify_irq(data, false, NULL);
413}
414
415static void unmask_ioapic_irq(struct irq_data *irq_data)
416{
417 struct mp_chip_data *data = irq_data->chip_data;
418
419 guard(raw_spinlock_irqsave)(&ioapic_lock);
420 __unmask_ioapic(data);
421}
422
423/*
424 * IO-APIC versions below 0x20 don't support EOI register.
425 * For the record, here is the information about various versions:
426 * 0Xh 82489DX
427 * 1Xh I/OAPIC or I/O(x)APIC which are not PCI 2.2 Compliant
428 * 2Xh I/O(x)APIC which is PCI 2.2 Compliant
429 * 30h-FFh Reserved
430 *
431 * Some of the Intel ICH Specs (ICH2 to ICH5) documents the io-apic
432 * version as 0x2. This is an error with documentation and these ICH chips
433 * use io-apic's of version 0x20.
434 *
435 * For IO-APIC's with EOI register, we use that to do an explicit EOI.
436 * Otherwise, we simulate the EOI message manually by changing the trigger
437 * mode to edge and then back to level, with RTE being masked during this.
438 */
439static void __eoi_ioapic_pin(int apic, int pin, int vector)
440{
441 if (mpc_ioapic_ver(apic) >= 0x20) {
442 io_apic_eoi(apic, vector);
443 } else {
444 struct IO_APIC_route_entry entry, entry1;
445
446 entry = entry1 = __ioapic_read_entry(apic, pin);
447
448 /* Mask the entry and change the trigger mode to edge. */
449 entry1.masked = true;
450 entry1.is_level = false;
451
452 __ioapic_write_entry(apic, pin, entry1);
453
454 /* Restore the previous level triggered entry. */
455 __ioapic_write_entry(apic, pin, entry);
456 }
457}
458
459static void eoi_ioapic_pin(int vector, struct mp_chip_data *data)
460{
461 struct irq_pin_list *entry;
462
463 guard(raw_spinlock_irqsave)(&ioapic_lock);
464 for_each_irq_pin(entry, data->irq_2_pin)
465 __eoi_ioapic_pin(entry->apic, entry->pin, vector);
466}
467
468static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
469{
470 struct IO_APIC_route_entry entry;
471
472 /* Check delivery_mode to be sure we're not clearing an SMI pin */
473 entry = ioapic_read_entry(apic, pin);
474 if (entry.delivery_mode == APIC_DELIVERY_MODE_SMI)
475 return;
476
477 /*
478 * Make sure the entry is masked and re-read the contents to check
479 * if it is a level triggered pin and if the remote-IRR is set.
480 */
481 if (!entry.masked) {
482 entry.masked = true;
483 ioapic_write_entry(apic, pin, entry);
484 entry = ioapic_read_entry(apic, pin);
485 }
486
487 if (entry.irr) {
488 /*
489 * Make sure the trigger mode is set to level. Explicit EOI
490 * doesn't clear the remote-IRR if the trigger mode is not
491 * set to level.
492 */
493 if (!entry.is_level) {
494 entry.is_level = true;
495 ioapic_write_entry(apic, pin, entry);
496 }
497 guard(raw_spinlock_irqsave)(&ioapic_lock);
498 __eoi_ioapic_pin(apic, pin, entry.vector);
499 }
500
501 /*
502 * Clear the rest of the bits in the IO-APIC RTE except for the mask
503 * bit.
504 */
505 ioapic_mask_entry(apic, pin);
506 entry = ioapic_read_entry(apic, pin);
507 if (entry.irr)
508 pr_err("Unable to reset IRR for apic: %d, pin :%d\n",
509 mpc_ioapic_id(apic), pin);
510}
511
512void clear_IO_APIC (void)
513{
514 int apic, pin;
515
516 for_each_ioapic_pin(apic, pin)
517 clear_IO_APIC_pin(apic, pin);
518}
519
520#ifdef CONFIG_X86_32
521/*
522 * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to
523 * specific CPU-side IRQs.
524 */
525
526#define MAX_PIRQS 8
527static int pirq_entries[MAX_PIRQS] = {
528 [0 ... MAX_PIRQS - 1] = -1
529};
530
531static int __init ioapic_pirq_setup(char *str)
532{
533 int i, max, ints[MAX_PIRQS+1];
534
535 get_options(str, ARRAY_SIZE(ints), ints);
536
537 apic_pr_verbose("PIRQ redirection, working around broken MP-BIOS.\n");
538
539 max = MAX_PIRQS;
540 if (ints[0] < MAX_PIRQS)
541 max = ints[0];
542
543 for (i = 0; i < max; i++) {
544 apic_pr_verbose("... PIRQ%d -> IRQ %d\n", i, ints[i + 1]);
545 /* PIRQs are mapped upside down, usually */
546 pirq_entries[MAX_PIRQS-i-1] = ints[i+1];
547 }
548 return 1;
549}
550__setup("pirq=", ioapic_pirq_setup);
551#endif /* CONFIG_X86_32 */
552
553/*
554 * Saves all the IO-APIC RTE's
555 */
556int save_ioapic_entries(void)
557{
558 int apic, pin;
559 int err = 0;
560
561 for_each_ioapic(apic) {
562 if (!ioapics[apic].saved_registers) {
563 err = -ENOMEM;
564 continue;
565 }
566
567 for_each_pin(apic, pin)
568 ioapics[apic].saved_registers[pin] = ioapic_read_entry(apic, pin);
569 }
570
571 return err;
572}
573
574/*
575 * Mask all IO APIC entries.
576 */
577void mask_ioapic_entries(void)
578{
579 int apic, pin;
580
581 for_each_ioapic(apic) {
582 if (!ioapics[apic].saved_registers)
583 continue;
584
585 for_each_pin(apic, pin) {
586 struct IO_APIC_route_entry entry;
587
588 entry = ioapics[apic].saved_registers[pin];
589 if (!entry.masked) {
590 entry.masked = true;
591 ioapic_write_entry(apic, pin, entry);
592 }
593 }
594 }
595}
596
597/*
598 * Restore IO APIC entries which was saved in the ioapic structure.
599 */
600int restore_ioapic_entries(void)
601{
602 int apic, pin;
603
604 for_each_ioapic(apic) {
605 if (!ioapics[apic].saved_registers)
606 continue;
607
608 for_each_pin(apic, pin)
609 ioapic_write_entry(apic, pin, ioapics[apic].saved_registers[pin]);
610 }
611 return 0;
612}
613
614/*
615 * Find the IRQ entry number of a certain pin.
616 */
617static int find_irq_entry(int ioapic_idx, int pin, int type)
618{
619 int i;
620
621 for (i = 0; i < mp_irq_entries; i++) {
622 if (mp_irqs[i].irqtype == type &&
623 (mp_irqs[i].dstapic == mpc_ioapic_id(ioapic_idx) ||
624 mp_irqs[i].dstapic == MP_APIC_ALL) &&
625 mp_irqs[i].dstirq == pin)
626 return i;
627 }
628
629 return -1;
630}
631
632/*
633 * Find the pin to which IRQ[irq] (ISA) is connected
634 */
635static int __init find_isa_irq_pin(int irq, int type)
636{
637 int i;
638
639 for (i = 0; i < mp_irq_entries; i++) {
640 int lbus = mp_irqs[i].srcbus;
641
642 if (test_bit(lbus, mp_bus_not_pci) && (mp_irqs[i].irqtype == type) &&
643 (mp_irqs[i].srcbusirq == irq))
644 return mp_irqs[i].dstirq;
645 }
646 return -1;
647}
648
649static int __init find_isa_irq_apic(int irq, int type)
650{
651 int i;
652
653 for (i = 0; i < mp_irq_entries; i++) {
654 int lbus = mp_irqs[i].srcbus;
655
656 if (test_bit(lbus, mp_bus_not_pci) && (mp_irqs[i].irqtype == type) &&
657 (mp_irqs[i].srcbusirq == irq))
658 break;
659 }
660
661 if (i < mp_irq_entries) {
662 int ioapic_idx;
663
664 for_each_ioapic(ioapic_idx) {
665 if (mpc_ioapic_id(ioapic_idx) == mp_irqs[i].dstapic)
666 return ioapic_idx;
667 }
668 }
669
670 return -1;
671}
672
673static bool irq_active_low(int idx)
674{
675 int bus = mp_irqs[idx].srcbus;
676
677 /*
678 * Determine IRQ line polarity (high active or low active):
679 */
680 switch (mp_irqs[idx].irqflag & MP_IRQPOL_MASK) {
681 case MP_IRQPOL_DEFAULT:
682 /*
683 * Conforms to spec, ie. bus-type dependent polarity. PCI
684 * defaults to low active. [E]ISA defaults to high active.
685 */
686 return !test_bit(bus, mp_bus_not_pci);
687 case MP_IRQPOL_ACTIVE_HIGH:
688 return false;
689 case MP_IRQPOL_RESERVED:
690 pr_warn("IOAPIC: Invalid polarity: 2, defaulting to low\n");
691 fallthrough;
692 case MP_IRQPOL_ACTIVE_LOW:
693 default: /* Pointless default required due to do gcc stupidity */
694 return true;
695 }
696}
697
698#ifdef CONFIG_EISA
699/*
700 * EISA Edge/Level control register, ELCR
701 */
702static bool EISA_ELCR(unsigned int irq)
703{
704 if (irq < nr_legacy_irqs()) {
705 unsigned int port = PIC_ELCR1 + (irq >> 3);
706 return (inb(port) >> (irq & 7)) & 1;
707 }
708 apic_pr_verbose("Broken MPtable reports ISA irq %d\n", irq);
709 return false;
710}
711
712/*
713 * EISA interrupts are always active high and can be edge or level
714 * triggered depending on the ELCR value. If an interrupt is listed as
715 * EISA conforming in the MP table, that means its trigger type must be
716 * read in from the ELCR.
717 */
718static bool eisa_irq_is_level(int idx, int bus, bool level)
719{
720 switch (mp_bus_id_to_type[bus]) {
721 case MP_BUS_PCI:
722 case MP_BUS_ISA:
723 return level;
724 case MP_BUS_EISA:
725 return EISA_ELCR(mp_irqs[idx].srcbusirq);
726 }
727 pr_warn("IOAPIC: Invalid srcbus: %d defaulting to level\n", bus);
728 return true;
729}
730#else
731static inline int eisa_irq_is_level(int idx, int bus, bool level)
732{
733 return level;
734}
735#endif
736
737static bool irq_is_level(int idx)
738{
739 int bus = mp_irqs[idx].srcbus;
740 bool level;
741
742 /*
743 * Determine IRQ trigger mode (edge or level sensitive):
744 */
745 switch (mp_irqs[idx].irqflag & MP_IRQTRIG_MASK) {
746 case MP_IRQTRIG_DEFAULT:
747 /*
748 * Conforms to spec, ie. bus-type dependent trigger
749 * mode. PCI defaults to level, ISA to edge.
750 */
751 level = !test_bit(bus, mp_bus_not_pci);
752 /* Take EISA into account */
753 return eisa_irq_is_level(idx, bus, level);
754 case MP_IRQTRIG_EDGE:
755 return false;
756 case MP_IRQTRIG_RESERVED:
757 pr_warn("IOAPIC: Invalid trigger mode 2 defaulting to level\n");
758 fallthrough;
759 case MP_IRQTRIG_LEVEL:
760 default: /* Pointless default required due to do gcc stupidity */
761 return true;
762 }
763}
764
765static int __acpi_get_override_irq(u32 gsi, bool *trigger, bool *polarity)
766{
767 int ioapic, pin, idx;
768
769 if (ioapic_is_disabled)
770 return -1;
771
772 ioapic = mp_find_ioapic(gsi);
773 if (ioapic < 0)
774 return -1;
775
776 pin = mp_find_ioapic_pin(ioapic, gsi);
777 if (pin < 0)
778 return -1;
779
780 idx = find_irq_entry(ioapic, pin, mp_INT);
781 if (idx < 0)
782 return -1;
783
784 *trigger = irq_is_level(idx);
785 *polarity = irq_active_low(idx);
786 return 0;
787}
788
789#ifdef CONFIG_ACPI
790int acpi_get_override_irq(u32 gsi, int *is_level, int *active_low)
791{
792 *is_level = *active_low = 0;
793 return __acpi_get_override_irq(gsi, (bool *)is_level,
794 (bool *)active_low);
795}
796#endif
797
798void ioapic_set_alloc_attr(struct irq_alloc_info *info, int node,
799 int trigger, int polarity)
800{
801 init_irq_alloc_info(info, NULL);
802 info->type = X86_IRQ_ALLOC_TYPE_IOAPIC;
803 info->ioapic.node = node;
804 info->ioapic.is_level = trigger;
805 info->ioapic.active_low = polarity;
806 info->ioapic.valid = 1;
807}
808
809static void ioapic_copy_alloc_attr(struct irq_alloc_info *dst,
810 struct irq_alloc_info *src,
811 u32 gsi, int ioapic_idx, int pin)
812{
813 bool level, pol_low;
814
815 copy_irq_alloc_info(dst, src);
816 dst->type = X86_IRQ_ALLOC_TYPE_IOAPIC;
817 dst->devid = mpc_ioapic_id(ioapic_idx);
818 dst->ioapic.pin = pin;
819 dst->ioapic.valid = 1;
820 if (src && src->ioapic.valid) {
821 dst->ioapic.node = src->ioapic.node;
822 dst->ioapic.is_level = src->ioapic.is_level;
823 dst->ioapic.active_low = src->ioapic.active_low;
824 } else {
825 dst->ioapic.node = NUMA_NO_NODE;
826 if (__acpi_get_override_irq(gsi, &level, &pol_low) >= 0) {
827 dst->ioapic.is_level = level;
828 dst->ioapic.active_low = pol_low;
829 } else {
830 /*
831 * PCI interrupts are always active low level
832 * triggered.
833 */
834 dst->ioapic.is_level = true;
835 dst->ioapic.active_low = true;
836 }
837 }
838}
839
840static int ioapic_alloc_attr_node(struct irq_alloc_info *info)
841{
842 return (info && info->ioapic.valid) ? info->ioapic.node : NUMA_NO_NODE;
843}
844
845static void mp_register_handler(unsigned int irq, bool level)
846{
847 irq_flow_handler_t hdl;
848 bool fasteoi;
849
850 if (level) {
851 irq_set_status_flags(irq, IRQ_LEVEL);
852 fasteoi = true;
853 } else {
854 irq_clear_status_flags(irq, IRQ_LEVEL);
855 fasteoi = false;
856 }
857
858 hdl = fasteoi ? handle_fasteoi_irq : handle_edge_irq;
859 __irq_set_handler(irq, hdl, 0, fasteoi ? "fasteoi" : "edge");
860}
861
862static bool mp_check_pin_attr(int irq, struct irq_alloc_info *info)
863{
864 struct mp_chip_data *data = irq_get_chip_data(irq);
865
866 /*
867 * setup_IO_APIC_irqs() programs all legacy IRQs with default trigger
868 * and polarity attributes. So allow the first user to reprogram the
869 * pin with real trigger and polarity attributes.
870 */
871 if (irq < nr_legacy_irqs() && data->count == 1) {
872 if (info->ioapic.is_level != data->is_level)
873 mp_register_handler(irq, info->ioapic.is_level);
874 data->entry.is_level = data->is_level = info->ioapic.is_level;
875 data->entry.active_low = data->active_low = info->ioapic.active_low;
876 }
877
878 return data->is_level == info->ioapic.is_level &&
879 data->active_low == info->ioapic.active_low;
880}
881
882static int alloc_irq_from_domain(struct irq_domain *domain, int ioapic, u32 gsi,
883 struct irq_alloc_info *info)
884{
885 int type = ioapics[ioapic].irqdomain_cfg.type;
886 bool legacy = false;
887 int irq = -1;
888
889 switch (type) {
890 case IOAPIC_DOMAIN_LEGACY:
891 /*
892 * Dynamically allocate IRQ number for non-ISA IRQs in the first
893 * 16 GSIs on some weird platforms.
894 */
895 if (!ioapic_initialized || gsi >= nr_legacy_irqs())
896 irq = gsi;
897 legacy = mp_is_legacy_irq(irq);
898 break;
899 case IOAPIC_DOMAIN_STRICT:
900 irq = gsi;
901 break;
902 case IOAPIC_DOMAIN_DYNAMIC:
903 break;
904 default:
905 WARN(1, "ioapic: unknown irqdomain type %d\n", type);
906 return -1;
907 }
908
909 return __irq_domain_alloc_irqs(domain, irq, 1, ioapic_alloc_attr_node(info),
910 info, legacy, NULL);
911}
912
913/*
914 * Need special handling for ISA IRQs because there may be multiple IOAPIC pins
915 * sharing the same ISA IRQ number and irqdomain only supports 1:1 mapping
916 * between IOAPIC pin and IRQ number. A typical IOAPIC has 24 pins, pin 0-15 are
917 * used for legacy IRQs and pin 16-23 are used for PCI IRQs (PIRQ A-H).
918 * When ACPI is disabled, only legacy IRQ numbers (IRQ0-15) are available, and
919 * some BIOSes may use MP Interrupt Source records to override IRQ numbers for
920 * PIRQs instead of reprogramming the interrupt routing logic. Thus there may be
921 * multiple pins sharing the same legacy IRQ number when ACPI is disabled.
922 */
923static int alloc_isa_irq_from_domain(struct irq_domain *domain, int irq, int ioapic, int pin,
924 struct irq_alloc_info *info)
925{
926 struct irq_data *irq_data = irq_get_irq_data(irq);
927 int node = ioapic_alloc_attr_node(info);
928 struct mp_chip_data *data;
929
930 /*
931 * Legacy ISA IRQ has already been allocated, just add pin to
932 * the pin list associated with this IRQ and program the IOAPIC
933 * entry.
934 */
935 if (irq_data && irq_data->parent_data) {
936 if (!mp_check_pin_attr(irq, info))
937 return -EBUSY;
938 if (!add_pin_to_irq_node(irq_data->chip_data, node, ioapic, info->ioapic.pin))
939 return -ENOMEM;
940 } else {
941 info->flags |= X86_IRQ_ALLOC_LEGACY;
942 irq = __irq_domain_alloc_irqs(domain, irq, 1, node, info, true, NULL);
943 if (irq >= 0) {
944 irq_data = irq_domain_get_irq_data(domain, irq);
945 data = irq_data->chip_data;
946 data->isa_irq = true;
947 }
948 }
949
950 return irq;
951}
952
953static int mp_map_pin_to_irq(u32 gsi, int idx, int ioapic, int pin,
954 unsigned int flags, struct irq_alloc_info *info)
955{
956 struct irq_domain *domain = mp_ioapic_irqdomain(ioapic);
957 struct irq_alloc_info tmp;
958 struct mp_chip_data *data;
959 bool legacy = false;
960 int irq;
961
962 if (!domain)
963 return -ENOSYS;
964
965 if (idx >= 0 && test_bit(mp_irqs[idx].srcbus, mp_bus_not_pci)) {
966 irq = mp_irqs[idx].srcbusirq;
967 legacy = mp_is_legacy_irq(irq);
968 /*
969 * IRQ2 is unusable for historical reasons on systems which
970 * have a legacy PIC. See the comment vs. IRQ2 further down.
971 *
972 * If this gets removed at some point then the related code
973 * in lapic_assign_system_vectors() needs to be adjusted as
974 * well.
975 */
976 if (legacy && irq == PIC_CASCADE_IR)
977 return -EINVAL;
978 }
979
980 guard(mutex)(&ioapic_mutex);
981 if (!(flags & IOAPIC_MAP_ALLOC)) {
982 if (!legacy) {
983 irq = irq_find_mapping(domain, pin);
984 if (irq == 0)
985 irq = -ENOENT;
986 }
987 } else {
988 ioapic_copy_alloc_attr(&tmp, info, gsi, ioapic, pin);
989 if (legacy)
990 irq = alloc_isa_irq_from_domain(domain, irq,
991 ioapic, pin, &tmp);
992 else if ((irq = irq_find_mapping(domain, pin)) == 0)
993 irq = alloc_irq_from_domain(domain, ioapic, gsi, &tmp);
994 else if (!mp_check_pin_attr(irq, &tmp))
995 irq = -EBUSY;
996 if (irq >= 0) {
997 data = irq_get_chip_data(irq);
998 data->count++;
999 }
1000 }
1001 return irq;
1002}
1003
1004static int pin_2_irq(int idx, int ioapic, int pin, unsigned int flags)
1005{
1006 u32 gsi = mp_pin_to_gsi(ioapic, pin);
1007
1008 /* Debugging check, we are in big trouble if this message pops up! */
1009 if (mp_irqs[idx].dstirq != pin)
1010 pr_err("broken BIOS or MPTABLE parser, ayiee!!\n");
1011
1012#ifdef CONFIG_X86_32
1013 /* PCI IRQ command line redirection. Yes, limits are hardcoded. */
1014 if ((pin >= 16) && (pin <= 23)) {
1015 if (pirq_entries[pin - 16] != -1) {
1016 if (!pirq_entries[pin - 16]) {
1017 apic_pr_verbose("Disabling PIRQ%d\n", pin - 16);
1018 } else {
1019 int irq = pirq_entries[pin-16];
1020
1021 apic_pr_verbose("Using PIRQ%d -> IRQ %d\n", pin - 16, irq);
1022 return irq;
1023 }
1024 }
1025 }
1026#endif
1027
1028 return mp_map_pin_to_irq(gsi, idx, ioapic, pin, flags, NULL);
1029}
1030
1031int mp_map_gsi_to_irq(u32 gsi, unsigned int flags, struct irq_alloc_info *info)
1032{
1033 int ioapic, pin, idx;
1034
1035 ioapic = mp_find_ioapic(gsi);
1036 if (ioapic < 0)
1037 return -ENODEV;
1038
1039 pin = mp_find_ioapic_pin(ioapic, gsi);
1040 idx = find_irq_entry(ioapic, pin, mp_INT);
1041 if ((flags & IOAPIC_MAP_CHECK) && idx < 0)
1042 return -ENODEV;
1043
1044 return mp_map_pin_to_irq(gsi, idx, ioapic, pin, flags, info);
1045}
1046
1047void mp_unmap_irq(int irq)
1048{
1049 struct irq_data *irq_data = irq_get_irq_data(irq);
1050 struct mp_chip_data *data;
1051
1052 if (!irq_data || !irq_data->domain)
1053 return;
1054
1055 data = irq_data->chip_data;
1056 if (!data || data->isa_irq)
1057 return;
1058
1059 guard(mutex)(&ioapic_mutex);
1060 if (--data->count == 0)
1061 irq_domain_free_irqs(irq, 1);
1062}
1063
1064/*
1065 * Find a specific PCI IRQ entry.
1066 * Not an __init, possibly needed by modules
1067 */
1068int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin)
1069{
1070 int irq, i, best_ioapic = -1, best_idx = -1;
1071
1072 apic_pr_debug("Querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n",
1073 bus, slot, pin);
1074 if (test_bit(bus, mp_bus_not_pci)) {
1075 apic_pr_verbose("PCI BIOS passed nonexistent PCI bus %d!\n", bus);
1076 return -1;
1077 }
1078
1079 for (i = 0; i < mp_irq_entries; i++) {
1080 int lbus = mp_irqs[i].srcbus;
1081 int ioapic_idx, found = 0;
1082
1083 if (bus != lbus || mp_irqs[i].irqtype != mp_INT ||
1084 slot != ((mp_irqs[i].srcbusirq >> 2) & 0x1f))
1085 continue;
1086
1087 for_each_ioapic(ioapic_idx)
1088 if (mpc_ioapic_id(ioapic_idx) == mp_irqs[i].dstapic ||
1089 mp_irqs[i].dstapic == MP_APIC_ALL) {
1090 found = 1;
1091 break;
1092 }
1093 if (!found)
1094 continue;
1095
1096 /* Skip ISA IRQs */
1097 irq = pin_2_irq(i, ioapic_idx, mp_irqs[i].dstirq, 0);
1098 if (irq > 0 && !IO_APIC_IRQ(irq))
1099 continue;
1100
1101 if (pin == (mp_irqs[i].srcbusirq & 3)) {
1102 best_idx = i;
1103 best_ioapic = ioapic_idx;
1104 goto out;
1105 }
1106
1107 /*
1108 * Use the first all-but-pin matching entry as a
1109 * best-guess fuzzy result for broken mptables.
1110 */
1111 if (best_idx < 0) {
1112 best_idx = i;
1113 best_ioapic = ioapic_idx;
1114 }
1115 }
1116 if (best_idx < 0)
1117 return -1;
1118
1119out:
1120 return pin_2_irq(best_idx, best_ioapic, mp_irqs[best_idx].dstirq, IOAPIC_MAP_ALLOC);
1121}
1122EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector);
1123
1124static struct irq_chip ioapic_chip, ioapic_ir_chip;
1125
1126static void __init setup_IO_APIC_irqs(void)
1127{
1128 unsigned int ioapic, pin;
1129 int idx;
1130
1131 apic_pr_verbose("Init IO_APIC IRQs\n");
1132
1133 for_each_ioapic_pin(ioapic, pin) {
1134 idx = find_irq_entry(ioapic, pin, mp_INT);
1135 if (idx < 0) {
1136 apic_pr_verbose("apic %d pin %d not connected\n",
1137 mpc_ioapic_id(ioapic), pin);
1138 } else {
1139 pin_2_irq(idx, ioapic, pin, ioapic ? 0 : IOAPIC_MAP_ALLOC);
1140 }
1141 }
1142}
1143
1144void ioapic_zap_locks(void)
1145{
1146 raw_spin_lock_init(&ioapic_lock);
1147}
1148
1149static void io_apic_print_entries(unsigned int apic, unsigned int nr_entries)
1150{
1151 struct IO_APIC_route_entry entry;
1152 char buf[256];
1153 int i;
1154
1155 apic_dbg("IOAPIC %d:\n", apic);
1156 for (i = 0; i <= nr_entries; i++) {
1157 entry = ioapic_read_entry(apic, i);
1158 snprintf(buf, sizeof(buf), " pin%02x, %s, %s, %s, V(%02X), IRR(%1d), S(%1d)",
1159 i, entry.masked ? "disabled" : "enabled ",
1160 entry.is_level ? "level" : "edge ",
1161 entry.active_low ? "low " : "high",
1162 entry.vector, entry.irr, entry.delivery_status);
1163 if (entry.ir_format) {
1164 apic_dbg("%s, remapped, I(%04X), Z(%X)\n", buf,
1165 (entry.ir_index_15 << 15) | entry.ir_index_0_14, entry.ir_zero);
1166 } else {
1167 apic_dbg("%s, %s, D(%02X%02X), M(%1d)\n", buf,
1168 entry.dest_mode_logical ? "logical " : "physic al",
1169 entry.virt_destid_8_14, entry.destid_0_7, entry.delivery_mode);
1170 }
1171 }
1172}
1173
1174static void __init print_IO_APIC(int ioapic_idx)
1175{
1176 union IO_APIC_reg_00 reg_00;
1177 union IO_APIC_reg_01 reg_01;
1178 union IO_APIC_reg_02 reg_02;
1179 union IO_APIC_reg_03 reg_03;
1180
1181 scoped_guard (raw_spinlock_irqsave, &ioapic_lock) {
1182 reg_00.raw = io_apic_read(ioapic_idx, 0);
1183 reg_01.raw = io_apic_read(ioapic_idx, 1);
1184 if (reg_01.bits.version >= 0x10)
1185 reg_02.raw = io_apic_read(ioapic_idx, 2);
1186 if (reg_01.bits.version >= 0x20)
1187 reg_03.raw = io_apic_read(ioapic_idx, 3);
1188 }
1189
1190 apic_dbg("IO APIC #%d......\n", mpc_ioapic_id(ioapic_idx));
1191 apic_dbg(".... register #00: %08X\n", reg_00.raw);
1192 apic_dbg("....... : physical APIC id: %02X\n", reg_00.bits.ID);
1193 apic_dbg("....... : Delivery Type: %X\n", reg_00.bits.delivery_type);
1194 apic_dbg("....... : LTS : %X\n", reg_00.bits.LTS);
1195 apic_dbg(".... register #01: %08X\n", *(int *)®_01);
1196 apic_dbg("....... : max redirection entries: %02X\n", reg_01.bits.entries);
1197 apic_dbg("....... : PRQ implemented: %X\n", reg_01.bits.PRQ);
1198 apic_dbg("....... : IO APIC version: %02X\n", reg_01.bits.version);
1199
1200 /*
1201 * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02,
1202 * but the value of reg_02 is read as the previous read register
1203 * value, so ignore it if reg_02 == reg_01.
1204 */
1205 if (reg_01.bits.version >= 0x10 && reg_02.raw != reg_01.raw) {
1206 apic_dbg(".... register #02: %08X\n", reg_02.raw);
1207 apic_dbg("....... : arbitration: %02X\n", reg_02.bits.arbitration);
1208 }
1209
1210 /*
1211 * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02
1212 * or reg_03, but the value of reg_0[23] is read as the previous read
1213 * register value, so ignore it if reg_03 == reg_0[12].
1214 */
1215 if (reg_01.bits.version >= 0x20 && reg_03.raw != reg_02.raw &&
1216 reg_03.raw != reg_01.raw) {
1217 apic_dbg(".... register #03: %08X\n", reg_03.raw);
1218 apic_dbg("....... : Boot DT : %X\n", reg_03.bits.boot_DT);
1219 }
1220
1221 apic_dbg(".... IRQ redirection table:\n");
1222 io_apic_print_entries(ioapic_idx, reg_01.bits.entries);
1223}
1224
1225void __init print_IO_APICs(void)
1226{
1227 int ioapic_idx;
1228 unsigned int irq;
1229
1230 apic_dbg("number of MP IRQ sources: %d.\n", mp_irq_entries);
1231 for_each_ioapic(ioapic_idx) {
1232 apic_dbg("number of IO-APIC #%d registers: %d.\n",
1233 mpc_ioapic_id(ioapic_idx), ioapics[ioapic_idx].nr_registers);
1234 }
1235
1236 /*
1237 * We are a bit conservative about what we expect. We have to
1238 * know about every hardware change ASAP.
1239 */
1240 printk(KERN_INFO "testing the IO APIC.......................\n");
1241
1242 for_each_ioapic(ioapic_idx)
1243 print_IO_APIC(ioapic_idx);
1244
1245 apic_dbg("IRQ to pin mappings:\n");
1246 for_each_active_irq(irq) {
1247 struct irq_pin_list *entry;
1248 struct irq_chip *chip;
1249 struct mp_chip_data *data;
1250
1251 chip = irq_get_chip(irq);
1252 if (chip != &ioapic_chip && chip != &ioapic_ir_chip)
1253 continue;
1254 data = irq_get_chip_data(irq);
1255 if (!data)
1256 continue;
1257 if (list_empty(&data->irq_2_pin))
1258 continue;
1259
1260 apic_dbg("IRQ%d ", irq);
1261 for_each_irq_pin(entry, data->irq_2_pin)
1262 pr_cont("-> %d:%d", entry->apic, entry->pin);
1263 pr_cont("\n");
1264 }
1265
1266 printk(KERN_INFO ".................................... done.\n");
1267}
1268
1269/* Where if anywhere is the i8259 connect in external int mode */
1270static struct { int pin, apic; } ioapic_i8259 = { -1, -1 };
1271
1272void __init enable_IO_APIC(void)
1273{
1274 int i8259_apic, i8259_pin, apic, pin;
1275
1276 if (ioapic_is_disabled)
1277 nr_ioapics = 0;
1278
1279 if (!nr_legacy_irqs() || !nr_ioapics)
1280 return;
1281
1282 for_each_ioapic_pin(apic, pin) {
1283 /* See if any of the pins is in ExtINT mode */
1284 struct IO_APIC_route_entry entry = ioapic_read_entry(apic, pin);
1285
1286 /*
1287 * If the interrupt line is enabled and in ExtInt mode I
1288 * have found the pin where the i8259 is connected.
1289 */
1290 if (!entry.masked && entry.delivery_mode == APIC_DELIVERY_MODE_EXTINT) {
1291 ioapic_i8259.apic = apic;
1292 ioapic_i8259.pin = pin;
1293 break;
1294 }
1295 }
1296
1297 /*
1298 * Look to see what if the MP table has reported the ExtINT
1299 *
1300 * If we could not find the appropriate pin by looking at the ioapic
1301 * the i8259 probably is not connected the ioapic but give the
1302 * mptable a chance anyway.
1303 */
1304 i8259_pin = find_isa_irq_pin(0, mp_ExtINT);
1305 i8259_apic = find_isa_irq_apic(0, mp_ExtINT);
1306 /* Trust the MP table if nothing is setup in the hardware */
1307 if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) {
1308 pr_warn("ExtINT not setup in hardware but reported by MP table\n");
1309 ioapic_i8259.pin = i8259_pin;
1310 ioapic_i8259.apic = i8259_apic;
1311 }
1312 /* Complain if the MP table and the hardware disagree */
1313 if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) &&
1314 (i8259_pin >= 0) && (ioapic_i8259.pin >= 0))
1315 pr_warn("ExtINT in hardware and MP table differ\n");
1316
1317 /* Do not trust the IO-APIC being empty at bootup */
1318 clear_IO_APIC();
1319}
1320
1321void native_restore_boot_irq_mode(void)
1322{
1323 /*
1324 * If the i8259 is routed through an IOAPIC Put that IOAPIC in
1325 * virtual wire mode so legacy interrupts can be delivered.
1326 */
1327 if (ioapic_i8259.pin != -1) {
1328 struct IO_APIC_route_entry entry;
1329 u32 apic_id = read_apic_id();
1330
1331 memset(&entry, 0, sizeof(entry));
1332 entry.masked = false;
1333 entry.is_level = false;
1334 entry.active_low = false;
1335 entry.dest_mode_logical = false;
1336 entry.delivery_mode = APIC_DELIVERY_MODE_EXTINT;
1337 entry.destid_0_7 = apic_id & 0xFF;
1338 entry.virt_destid_8_14 = apic_id >> 8;
1339
1340 /* Add it to the IO-APIC irq-routing table */
1341 ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry);
1342 }
1343
1344 if (boot_cpu_has(X86_FEATURE_APIC) || apic_from_smp_config())
1345 disconnect_bsp_APIC(ioapic_i8259.pin != -1);
1346}
1347
1348void restore_boot_irq_mode(void)
1349{
1350 if (!nr_legacy_irqs())
1351 return;
1352
1353 x86_apic_ops.restore();
1354}
1355
1356#ifdef CONFIG_X86_32
1357/*
1358 * function to set the IO-APIC physical IDs based on the
1359 * values stored in the MPC table.
1360 *
1361 * by Matt Domsch <Matt_Domsch@dell.com> Tue Dec 21 12:25:05 CST 1999
1362 */
1363static void __init setup_ioapic_ids_from_mpc_nocheck(void)
1364{
1365 DECLARE_BITMAP(phys_id_present_map, MAX_LOCAL_APIC);
1366 const u32 broadcast_id = 0xF;
1367 union IO_APIC_reg_00 reg_00;
1368 unsigned char old_id;
1369 int ioapic_idx, i;
1370
1371 /*
1372 * This is broken; anything with a real cpu count has to
1373 * circumvent this idiocy regardless.
1374 */
1375 copy_phys_cpu_present_map(phys_id_present_map);
1376
1377 /*
1378 * Set the IOAPIC ID to the value stored in the MPC table.
1379 */
1380 for_each_ioapic(ioapic_idx) {
1381 /* Read the register 0 value */
1382 scoped_guard (raw_spinlock_irqsave, &ioapic_lock)
1383 reg_00.raw = io_apic_read(ioapic_idx, 0);
1384
1385 old_id = mpc_ioapic_id(ioapic_idx);
1386
1387 if (mpc_ioapic_id(ioapic_idx) >= broadcast_id) {
1388 pr_err(FW_BUG "IO-APIC#%d ID is %d in the MPC table!...\n",
1389 ioapic_idx, mpc_ioapic_id(ioapic_idx));
1390 pr_err("... fixing up to %d. (tell your hw vendor)\n", reg_00.bits.ID);
1391 ioapics[ioapic_idx].mp_config.apicid = reg_00.bits.ID;
1392 }
1393
1394 /*
1395 * Sanity check, is the ID really free? Every APIC in a
1396 * system must have a unique ID or we get lots of nice
1397 * 'stuck on smp_invalidate_needed IPI wait' messages.
1398 */
1399 if (test_bit(mpc_ioapic_id(ioapic_idx), phys_id_present_map)) {
1400 pr_err(FW_BUG "IO-APIC#%d ID %d is already used!...\n",
1401 ioapic_idx, mpc_ioapic_id(ioapic_idx));
1402 for (i = 0; i < broadcast_id; i++)
1403 if (!test_bit(i, phys_id_present_map))
1404 break;
1405 if (i >= broadcast_id)
1406 panic("Max APIC ID exceeded!\n");
1407 pr_err("... fixing up to %d. (tell your hw vendor)\n", i);
1408 set_bit(i, phys_id_present_map);
1409 ioapics[ioapic_idx].mp_config.apicid = i;
1410 } else {
1411 apic_pr_verbose("Setting %d in the phys_id_present_map\n",
1412 mpc_ioapic_id(ioapic_idx));
1413 set_bit(mpc_ioapic_id(ioapic_idx), phys_id_present_map);
1414 }
1415
1416 /*
1417 * We need to adjust the IRQ routing table if the ID
1418 * changed.
1419 */
1420 if (old_id != mpc_ioapic_id(ioapic_idx)) {
1421 for (i = 0; i < mp_irq_entries; i++) {
1422 if (mp_irqs[i].dstapic == old_id)
1423 mp_irqs[i].dstapic = mpc_ioapic_id(ioapic_idx);
1424 }
1425 }
1426
1427 /*
1428 * Update the ID register according to the right value from
1429 * the MPC table if they are different.
1430 */
1431 if (mpc_ioapic_id(ioapic_idx) == reg_00.bits.ID)
1432 continue;
1433
1434 apic_pr_verbose("...changing IO-APIC physical APIC ID to %d ...",
1435 mpc_ioapic_id(ioapic_idx));
1436
1437 reg_00.bits.ID = mpc_ioapic_id(ioapic_idx);
1438 scoped_guard (raw_spinlock_irqsave, &ioapic_lock) {
1439 io_apic_write(ioapic_idx, 0, reg_00.raw);
1440 reg_00.raw = io_apic_read(ioapic_idx, 0);
1441 }
1442 /* Sanity check */
1443 if (reg_00.bits.ID != mpc_ioapic_id(ioapic_idx))
1444 pr_cont("could not set ID!\n");
1445 else
1446 apic_pr_verbose(" ok.\n");
1447 }
1448}
1449
1450void __init setup_ioapic_ids_from_mpc(void)
1451{
1452
1453 if (acpi_ioapic)
1454 return;
1455 /*
1456 * Don't check I/O APIC IDs for xAPIC systems. They have
1457 * no meaning without the serial APIC bus.
1458 */
1459 if (!(boot_cpu_data.x86_vendor == X86_VENDOR_INTEL)
1460 || APIC_XAPIC(boot_cpu_apic_version))
1461 return;
1462 setup_ioapic_ids_from_mpc_nocheck();
1463}
1464#endif
1465
1466int no_timer_check __initdata;
1467
1468static int __init notimercheck(char *s)
1469{
1470 no_timer_check = 1;
1471 return 1;
1472}
1473__setup("no_timer_check", notimercheck);
1474
1475static void __init delay_with_tsc(void)
1476{
1477 unsigned long long start, now;
1478 unsigned long end = jiffies + 4;
1479
1480 start = rdtsc();
1481
1482 /*
1483 * We don't know the TSC frequency yet, but waiting for
1484 * 40000000000/HZ TSC cycles is safe:
1485 * 4 GHz == 10 jiffies
1486 * 1 GHz == 40 jiffies
1487 */
1488 do {
1489 rep_nop();
1490 now = rdtsc();
1491 } while ((now - start) < 40000000000ULL / HZ && time_before_eq(jiffies, end));
1492}
1493
1494static void __init delay_without_tsc(void)
1495{
1496 unsigned long end = jiffies + 4;
1497 int band = 1;
1498
1499 /*
1500 * We don't know any frequency yet, but waiting for
1501 * 40940000000/HZ cycles is safe:
1502 * 4 GHz == 10 jiffies
1503 * 1 GHz == 40 jiffies
1504 * 1 << 1 + 1 << 2 +...+ 1 << 11 = 4094
1505 */
1506 do {
1507 __delay(((1U << band++) * 10000000UL) / HZ);
1508 } while (band < 12 && time_before_eq(jiffies, end));
1509}
1510
1511/*
1512 * There is a nasty bug in some older SMP boards, their mptable lies
1513 * about the timer IRQ. We do the following to work around the situation:
1514 *
1515 * - timer IRQ defaults to IO-APIC IRQ
1516 * - if this function detects that timer IRQs are defunct, then we fall
1517 * back to ISA timer IRQs
1518 */
1519static int __init timer_irq_works(void)
1520{
1521 unsigned long t1 = jiffies;
1522
1523 if (no_timer_check)
1524 return 1;
1525
1526 local_irq_enable();
1527 if (boot_cpu_has(X86_FEATURE_TSC))
1528 delay_with_tsc();
1529 else
1530 delay_without_tsc();
1531
1532 /*
1533 * Expect a few ticks at least, to be sure some possible
1534 * glue logic does not lock up after one or two first
1535 * ticks in a non-ExtINT mode. Also the local APIC
1536 * might have cached one ExtINT interrupt. Finally, at
1537 * least one tick may be lost due to delays.
1538 */
1539
1540 local_irq_disable();
1541
1542 /* Did jiffies advance? */
1543 return time_after(jiffies, t1 + 4);
1544}
1545
1546/*
1547 * In the SMP+IOAPIC case it might happen that there are an unspecified
1548 * number of pending IRQ events unhandled. These cases are very rare,
1549 * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
1550 * better to do it this way as thus we do not have to be aware of
1551 * 'pending' interrupts in the IRQ path, except at this point.
1552 *
1553 *
1554 * Edge triggered needs to resend any interrupt that was delayed but this
1555 * is now handled in the device independent code.
1556 *
1557 * Starting up a edge-triggered IO-APIC interrupt is nasty - we need to
1558 * make sure that we get the edge. If it is already asserted for some
1559 * reason, we need return 1 to indicate that is was pending.
1560 *
1561 * This is not complete - we should be able to fake an edge even if it
1562 * isn't on the 8259A...
1563 */
1564static unsigned int startup_ioapic_irq(struct irq_data *data)
1565{
1566 int was_pending = 0, irq = data->irq;
1567
1568 guard(raw_spinlock_irqsave)(&ioapic_lock);
1569 if (irq < nr_legacy_irqs()) {
1570 legacy_pic->mask(irq);
1571 if (legacy_pic->irq_pending(irq))
1572 was_pending = 1;
1573 }
1574 __unmask_ioapic(data->chip_data);
1575 return was_pending;
1576}
1577
1578atomic_t irq_mis_count;
1579
1580#ifdef CONFIG_GENERIC_PENDING_IRQ
1581static bool io_apic_level_ack_pending(struct mp_chip_data *data)
1582{
1583 struct irq_pin_list *entry;
1584
1585 guard(raw_spinlock_irqsave)(&ioapic_lock);
1586 for_each_irq_pin(entry, data->irq_2_pin) {
1587 struct IO_APIC_route_entry e;
1588 int pin;
1589
1590 pin = entry->pin;
1591 e.w1 = io_apic_read(entry->apic, 0x10 + pin*2);
1592 /* Is the remote IRR bit set? */
1593 if (e.irr)
1594 return true;
1595 }
1596 return false;
1597}
1598
1599static inline bool ioapic_prepare_move(struct irq_data *data)
1600{
1601 /* If we are moving the IRQ we need to mask it */
1602 if (unlikely(irqd_is_setaffinity_pending(data))) {
1603 if (!irqd_irq_masked(data))
1604 mask_ioapic_irq(data);
1605 return true;
1606 }
1607 return false;
1608}
1609
1610static inline void ioapic_finish_move(struct irq_data *data, bool moveit)
1611{
1612 if (unlikely(moveit)) {
1613 /*
1614 * Only migrate the irq if the ack has been received.
1615 *
1616 * On rare occasions the broadcast level triggered ack gets
1617 * delayed going to ioapics, and if we reprogram the
1618 * vector while Remote IRR is still set the irq will never
1619 * fire again.
1620 *
1621 * To prevent this scenario we read the Remote IRR bit
1622 * of the ioapic. This has two effects.
1623 * - On any sane system the read of the ioapic will
1624 * flush writes (and acks) going to the ioapic from
1625 * this cpu.
1626 * - We get to see if the ACK has actually been delivered.
1627 *
1628 * Based on failed experiments of reprogramming the
1629 * ioapic entry from outside of irq context starting
1630 * with masking the ioapic entry and then polling until
1631 * Remote IRR was clear before reprogramming the
1632 * ioapic I don't trust the Remote IRR bit to be
1633 * completely accurate.
1634 *
1635 * However there appears to be no other way to plug
1636 * this race, so if the Remote IRR bit is not
1637 * accurate and is causing problems then it is a hardware bug
1638 * and you can go talk to the chipset vendor about it.
1639 */
1640 if (!io_apic_level_ack_pending(data->chip_data))
1641 irq_move_masked_irq(data);
1642 /* If the IRQ is masked in the core, leave it: */
1643 if (!irqd_irq_masked(data))
1644 unmask_ioapic_irq(data);
1645 }
1646}
1647#else
1648static inline bool ioapic_prepare_move(struct irq_data *data)
1649{
1650 return false;
1651}
1652static inline void ioapic_finish_move(struct irq_data *data, bool moveit)
1653{
1654}
1655#endif
1656
1657static void ioapic_ack_level(struct irq_data *irq_data)
1658{
1659 struct irq_cfg *cfg = irqd_cfg(irq_data);
1660 unsigned long v;
1661 bool moveit;
1662 int i;
1663
1664 irq_complete_move(cfg);
1665 moveit = ioapic_prepare_move(irq_data);
1666
1667 /*
1668 * It appears there is an erratum which affects at least version 0x11
1669 * of I/O APIC (that's the 82093AA and cores integrated into various
1670 * chipsets). Under certain conditions a level-triggered interrupt is
1671 * erroneously delivered as edge-triggered one but the respective IRR
1672 * bit gets set nevertheless. As a result the I/O unit expects an EOI
1673 * message but it will never arrive and further interrupts are blocked
1674 * from the source. The exact reason is so far unknown, but the
1675 * phenomenon was observed when two consecutive interrupt requests
1676 * from a given source get delivered to the same CPU and the source is
1677 * temporarily disabled in between.
1678 *
1679 * A workaround is to simulate an EOI message manually. We achieve it
1680 * by setting the trigger mode to edge and then to level when the edge
1681 * trigger mode gets detected in the TMR of a local APIC for a
1682 * level-triggered interrupt. We mask the source for the time of the
1683 * operation to prevent an edge-triggered interrupt escaping meanwhile.
1684 * The idea is from Manfred Spraul. --macro
1685 *
1686 * Also in the case when cpu goes offline, fixup_irqs() will forward
1687 * any unhandled interrupt on the offlined cpu to the new cpu
1688 * destination that is handling the corresponding interrupt. This
1689 * interrupt forwarding is done via IPI's. Hence, in this case also
1690 * level-triggered io-apic interrupt will be seen as an edge
1691 * interrupt in the IRR. And we can't rely on the cpu's EOI
1692 * to be broadcasted to the IO-APIC's which will clear the remoteIRR
1693 * corresponding to the level-triggered interrupt. Hence on IO-APIC's
1694 * supporting EOI register, we do an explicit EOI to clear the
1695 * remote IRR and on IO-APIC's which don't have an EOI register,
1696 * we use the above logic (mask+edge followed by unmask+level) from
1697 * Manfred Spraul to clear the remote IRR.
1698 */
1699 i = cfg->vector;
1700 v = apic_read(APIC_TMR + ((i & ~0x1f) >> 1));
1701
1702 /*
1703 * We must acknowledge the irq before we move it or the acknowledge will
1704 * not propagate properly.
1705 */
1706 apic_eoi();
1707
1708 /*
1709 * Tail end of clearing remote IRR bit (either by delivering the EOI
1710 * message via io-apic EOI register write or simulating it using
1711 * mask+edge followed by unmask+level logic) manually when the
1712 * level triggered interrupt is seen as the edge triggered interrupt
1713 * at the cpu.
1714 */
1715 if (!(v & (1 << (i & 0x1f)))) {
1716 atomic_inc(&irq_mis_count);
1717 eoi_ioapic_pin(cfg->vector, irq_data->chip_data);
1718 }
1719
1720 ioapic_finish_move(irq_data, moveit);
1721}
1722
1723static void ioapic_ir_ack_level(struct irq_data *irq_data)
1724{
1725 struct mp_chip_data *data = irq_data->chip_data;
1726
1727 /*
1728 * Intr-remapping uses pin number as the virtual vector
1729 * in the RTE. Actual vector is programmed in
1730 * intr-remapping table entry. Hence for the io-apic
1731 * EOI we use the pin number.
1732 */
1733 apic_ack_irq(irq_data);
1734 eoi_ioapic_pin(data->entry.vector, data);
1735}
1736
1737/*
1738 * The I/OAPIC is just a device for generating MSI messages from legacy
1739 * interrupt pins. Various fields of the RTE translate into bits of the
1740 * resulting MSI which had a historical meaning.
1741 *
1742 * With interrupt remapping, many of those bits have different meanings
1743 * in the underlying MSI, but the way that the I/OAPIC transforms them
1744 * from its RTE to the MSI message is the same. This function allows
1745 * the parent IRQ domain to compose the MSI message, then takes the
1746 * relevant bits to put them in the appropriate places in the RTE in
1747 * order to generate that message when the IRQ happens.
1748 *
1749 * The setup here relies on a preconfigured route entry (is_level,
1750 * active_low, masked) because the parent domain is merely composing the
1751 * generic message routing information which is used for the MSI.
1752 */
1753static void ioapic_setup_msg_from_msi(struct irq_data *irq_data,
1754 struct IO_APIC_route_entry *entry)
1755{
1756 struct msi_msg msg;
1757
1758 /* Let the parent domain compose the MSI message */
1759 irq_chip_compose_msi_msg(irq_data, &msg);
1760
1761 /*
1762 * - Real vector
1763 * - DMAR/IR: 8bit subhandle (ioapic.pin)
1764 * - AMD/IR: 8bit IRTE index
1765 */
1766 entry->vector = msg.arch_data.vector;
1767 /* Delivery mode (for DMAR/IR all 0) */
1768 entry->delivery_mode = msg.arch_data.delivery_mode;
1769 /* Destination mode or DMAR/IR index bit 15 */
1770 entry->dest_mode_logical = msg.arch_addr_lo.dest_mode_logical;
1771 /* DMAR/IR: 1, 0 for all other modes */
1772 entry->ir_format = msg.arch_addr_lo.dmar_format;
1773 /*
1774 * - DMAR/IR: index bit 0-14.
1775 *
1776 * - Virt: If the host supports x2apic without a virtualized IR
1777 * unit then bit 0-6 of dmar_index_0_14 are providing bit
1778 * 8-14 of the destination id.
1779 *
1780 * All other modes have bit 0-6 of dmar_index_0_14 cleared and the
1781 * topmost 8 bits are destination id bit 0-7 (entry::destid_0_7).
1782 */
1783 entry->ir_index_0_14 = msg.arch_addr_lo.dmar_index_0_14;
1784}
1785
1786static void ioapic_configure_entry(struct irq_data *irqd)
1787{
1788 struct mp_chip_data *mpd = irqd->chip_data;
1789 struct irq_pin_list *entry;
1790
1791 ioapic_setup_msg_from_msi(irqd, &mpd->entry);
1792
1793 for_each_irq_pin(entry, mpd->irq_2_pin)
1794 __ioapic_write_entry(entry->apic, entry->pin, mpd->entry);
1795}
1796
1797static int ioapic_set_affinity(struct irq_data *irq_data, const struct cpumask *mask, bool force)
1798{
1799 struct irq_data *parent = irq_data->parent_data;
1800 int ret;
1801
1802 ret = parent->chip->irq_set_affinity(parent, mask, force);
1803
1804 guard(raw_spinlock_irqsave)(&ioapic_lock);
1805 if (ret >= 0 && ret != IRQ_SET_MASK_OK_DONE)
1806 ioapic_configure_entry(irq_data);
1807
1808 return ret;
1809}
1810
1811/*
1812 * Interrupt shutdown masks the ioapic pin, but the interrupt might already
1813 * be in flight, but not yet serviced by the target CPU. That means
1814 * __synchronize_hardirq() would return and claim that everything is calmed
1815 * down. So free_irq() would proceed and deactivate the interrupt and free
1816 * resources.
1817 *
1818 * Once the target CPU comes around to service it it will find a cleared
1819 * vector and complain. While the spurious interrupt is harmless, the full
1820 * release of resources might prevent the interrupt from being acknowledged
1821 * which keeps the hardware in a weird state.
1822 *
1823 * Verify that the corresponding Remote-IRR bits are clear.
1824 */
1825static int ioapic_irq_get_chip_state(struct irq_data *irqd, enum irqchip_irq_state which,
1826 bool *state)
1827{
1828 struct mp_chip_data *mcd = irqd->chip_data;
1829 struct IO_APIC_route_entry rentry;
1830 struct irq_pin_list *p;
1831
1832 if (which != IRQCHIP_STATE_ACTIVE)
1833 return -EINVAL;
1834
1835 *state = false;
1836
1837 guard(raw_spinlock)(&ioapic_lock);
1838 for_each_irq_pin(p, mcd->irq_2_pin) {
1839 rentry = __ioapic_read_entry(p->apic, p->pin);
1840 /*
1841 * The remote IRR is only valid in level trigger mode. It's
1842 * meaning is undefined for edge triggered interrupts and
1843 * irrelevant because the IO-APIC treats them as fire and
1844 * forget.
1845 */
1846 if (rentry.irr && rentry.is_level) {
1847 *state = true;
1848 break;
1849 }
1850 }
1851 return 0;
1852}
1853
1854static struct irq_chip ioapic_chip __read_mostly = {
1855 .name = "IO-APIC",
1856 .irq_startup = startup_ioapic_irq,
1857 .irq_mask = mask_ioapic_irq,
1858 .irq_unmask = unmask_ioapic_irq,
1859 .irq_ack = irq_chip_ack_parent,
1860 .irq_eoi = ioapic_ack_level,
1861 .irq_set_affinity = ioapic_set_affinity,
1862 .irq_retrigger = irq_chip_retrigger_hierarchy,
1863 .irq_get_irqchip_state = ioapic_irq_get_chip_state,
1864 .flags = IRQCHIP_SKIP_SET_WAKE |
1865 IRQCHIP_AFFINITY_PRE_STARTUP,
1866};
1867
1868static struct irq_chip ioapic_ir_chip __read_mostly = {
1869 .name = "IR-IO-APIC",
1870 .irq_startup = startup_ioapic_irq,
1871 .irq_mask = mask_ioapic_irq,
1872 .irq_unmask = unmask_ioapic_irq,
1873 .irq_ack = irq_chip_ack_parent,
1874 .irq_eoi = ioapic_ir_ack_level,
1875 .irq_set_affinity = ioapic_set_affinity,
1876 .irq_retrigger = irq_chip_retrigger_hierarchy,
1877 .irq_get_irqchip_state = ioapic_irq_get_chip_state,
1878 .flags = IRQCHIP_SKIP_SET_WAKE |
1879 IRQCHIP_AFFINITY_PRE_STARTUP,
1880};
1881
1882static inline void init_IO_APIC_traps(void)
1883{
1884 struct irq_cfg *cfg;
1885 unsigned int irq;
1886
1887 for_each_active_irq(irq) {
1888 cfg = irq_cfg(irq);
1889 if (IO_APIC_IRQ(irq) && cfg && !cfg->vector) {
1890 /*
1891 * Hmm.. We don't have an entry for this, so
1892 * default to an old-fashioned 8259 interrupt if we
1893 * can. Otherwise set the dummy interrupt chip.
1894 */
1895 if (irq < nr_legacy_irqs())
1896 legacy_pic->make_irq(irq);
1897 else
1898 irq_set_chip(irq, &no_irq_chip);
1899 }
1900 }
1901}
1902
1903/*
1904 * The local APIC irq-chip implementation:
1905 */
1906static void mask_lapic_irq(struct irq_data *data)
1907{
1908 unsigned long v = apic_read(APIC_LVT0);
1909
1910 apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
1911}
1912
1913static void unmask_lapic_irq(struct irq_data *data)
1914{
1915 unsigned long v = apic_read(APIC_LVT0);
1916
1917 apic_write(APIC_LVT0, v & ~APIC_LVT_MASKED);
1918}
1919
1920static void ack_lapic_irq(struct irq_data *data)
1921{
1922 apic_eoi();
1923}
1924
1925static struct irq_chip lapic_chip __read_mostly = {
1926 .name = "local-APIC",
1927 .irq_mask = mask_lapic_irq,
1928 .irq_unmask = unmask_lapic_irq,
1929 .irq_ack = ack_lapic_irq,
1930};
1931
1932static void lapic_register_intr(int irq)
1933{
1934 irq_clear_status_flags(irq, IRQ_LEVEL);
1935 irq_set_chip_and_handler_name(irq, &lapic_chip, handle_edge_irq, "edge");
1936}
1937
1938/*
1939 * This looks a bit hackish but it's about the only one way of sending
1940 * a few INTA cycles to 8259As and any associated glue logic. ICR does
1941 * not support the ExtINT mode, unfortunately. We need to send these
1942 * cycles as some i82489DX-based boards have glue logic that keeps the
1943 * 8259A interrupt line asserted until INTA. --macro
1944 */
1945static inline void __init unlock_ExtINT_logic(void)
1946{
1947 unsigned char save_control, save_freq_select;
1948 struct IO_APIC_route_entry entry0, entry1;
1949 int apic, pin, i;
1950 u32 apic_id;
1951
1952 pin = find_isa_irq_pin(8, mp_INT);
1953 if (pin == -1) {
1954 WARN_ON_ONCE(1);
1955 return;
1956 }
1957 apic = find_isa_irq_apic(8, mp_INT);
1958 if (apic == -1) {
1959 WARN_ON_ONCE(1);
1960 return;
1961 }
1962
1963 entry0 = ioapic_read_entry(apic, pin);
1964 clear_IO_APIC_pin(apic, pin);
1965
1966 apic_id = read_apic_id();
1967 memset(&entry1, 0, sizeof(entry1));
1968
1969 entry1.dest_mode_logical = true;
1970 entry1.masked = false;
1971 entry1.destid_0_7 = apic_id & 0xFF;
1972 entry1.virt_destid_8_14 = apic_id >> 8;
1973 entry1.delivery_mode = APIC_DELIVERY_MODE_EXTINT;
1974 entry1.active_low = entry0.active_low;
1975 entry1.is_level = false;
1976 entry1.vector = 0;
1977
1978 ioapic_write_entry(apic, pin, entry1);
1979
1980 save_control = CMOS_READ(RTC_CONTROL);
1981 save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
1982 CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6,
1983 RTC_FREQ_SELECT);
1984 CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL);
1985
1986 i = 100;
1987 while (i-- > 0) {
1988 mdelay(10);
1989 if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF)
1990 i -= 10;
1991 }
1992
1993 CMOS_WRITE(save_control, RTC_CONTROL);
1994 CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
1995 clear_IO_APIC_pin(apic, pin);
1996
1997 ioapic_write_entry(apic, pin, entry0);
1998}
1999
2000static int disable_timer_pin_1 __initdata;
2001/* Actually the next is obsolete, but keep it for paranoid reasons -AK */
2002static int __init disable_timer_pin_setup(char *arg)
2003{
2004 disable_timer_pin_1 = 1;
2005 return 0;
2006}
2007early_param("disable_timer_pin_1", disable_timer_pin_setup);
2008
2009static int __init mp_alloc_timer_irq(int ioapic, int pin)
2010{
2011 struct irq_domain *domain = mp_ioapic_irqdomain(ioapic);
2012 int irq = -1;
2013
2014 if (domain) {
2015 struct irq_alloc_info info;
2016
2017 ioapic_set_alloc_attr(&info, NUMA_NO_NODE, 0, 0);
2018 info.devid = mpc_ioapic_id(ioapic);
2019 info.ioapic.pin = pin;
2020 guard(mutex)(&ioapic_mutex);
2021 irq = alloc_isa_irq_from_domain(domain, 0, ioapic, pin, &info);
2022 }
2023
2024 return irq;
2025}
2026
2027static void __init replace_pin_at_irq_node(struct mp_chip_data *data, int node,
2028 int oldapic, int oldpin,
2029 int newapic, int newpin)
2030{
2031 struct irq_pin_list *entry;
2032
2033 for_each_irq_pin(entry, data->irq_2_pin) {
2034 if (entry->apic == oldapic && entry->pin == oldpin) {
2035 entry->apic = newapic;
2036 entry->pin = newpin;
2037 return;
2038 }
2039 }
2040
2041 /* Old apic/pin didn't exist, so just add a new one */
2042 add_pin_to_irq_node(data, node, newapic, newpin);
2043}
2044
2045/*
2046 * This code may look a bit paranoid, but it's supposed to cooperate with
2047 * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ
2048 * is so screwy. Thanks to Brian Perkins for testing/hacking this beast
2049 * fanatically on his truly buggy board.
2050 */
2051static inline void __init check_timer(void)
2052{
2053 struct irq_data *irq_data = irq_get_irq_data(0);
2054 struct mp_chip_data *data = irq_data->chip_data;
2055 struct irq_cfg *cfg = irqd_cfg(irq_data);
2056 int node = cpu_to_node(0);
2057 int apic1, pin1, apic2, pin2;
2058 int no_pin1 = 0;
2059
2060 if (!global_clock_event)
2061 return;
2062
2063 local_irq_disable();
2064
2065 /*
2066 * get/set the timer IRQ vector:
2067 */
2068 legacy_pic->mask(0);
2069
2070 /*
2071 * As IRQ0 is to be enabled in the 8259A, the virtual
2072 * wire has to be disabled in the local APIC. Also
2073 * timer interrupts need to be acknowledged manually in
2074 * the 8259A for the i82489DX when using the NMI
2075 * watchdog as that APIC treats NMIs as level-triggered.
2076 * The AEOI mode will finish them in the 8259A
2077 * automatically.
2078 */
2079 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
2080 legacy_pic->init(1);
2081
2082 pin1 = find_isa_irq_pin(0, mp_INT);
2083 apic1 = find_isa_irq_apic(0, mp_INT);
2084 pin2 = ioapic_i8259.pin;
2085 apic2 = ioapic_i8259.apic;
2086
2087 pr_info("..TIMER: vector=0x%02X apic1=%d pin1=%d apic2=%d pin2=%d\n",
2088 cfg->vector, apic1, pin1, apic2, pin2);
2089
2090 /*
2091 * Some BIOS writers are clueless and report the ExtINTA
2092 * I/O APIC input from the cascaded 8259A as the timer
2093 * interrupt input. So just in case, if only one pin
2094 * was found above, try it both directly and through the
2095 * 8259A.
2096 */
2097 if (pin1 == -1) {
2098 panic_if_irq_remap(FW_BUG "Timer not connected to IO-APIC");
2099 pin1 = pin2;
2100 apic1 = apic2;
2101 no_pin1 = 1;
2102 } else if (pin2 == -1) {
2103 pin2 = pin1;
2104 apic2 = apic1;
2105 }
2106
2107 if (pin1 != -1) {
2108 /* Ok, does IRQ0 through the IOAPIC work? */
2109 if (no_pin1) {
2110 mp_alloc_timer_irq(apic1, pin1);
2111 } else {
2112 /*
2113 * for edge trigger, it's already unmasked,
2114 * so only need to unmask if it is level-trigger
2115 * do we really have level trigger timer?
2116 */
2117 int idx = find_irq_entry(apic1, pin1, mp_INT);
2118
2119 if (idx != -1 && irq_is_level(idx))
2120 unmask_ioapic_irq(irq_get_irq_data(0));
2121 }
2122 irq_domain_deactivate_irq(irq_data);
2123 irq_domain_activate_irq(irq_data, false);
2124 if (timer_irq_works()) {
2125 if (disable_timer_pin_1 > 0)
2126 clear_IO_APIC_pin(0, pin1);
2127 goto out;
2128 }
2129 panic_if_irq_remap("timer doesn't work through Interrupt-remapped IO-APIC");
2130 clear_IO_APIC_pin(apic1, pin1);
2131 if (!no_pin1)
2132 pr_err("..MP-BIOS bug: 8254 timer not connected to IO-APIC\n");
2133
2134 pr_info("...trying to set up timer (IRQ0) through the 8259A ...\n");
2135 pr_info("..... (found apic %d pin %d) ...\n", apic2, pin2);
2136 /*
2137 * legacy devices should be connected to IO APIC #0
2138 */
2139 replace_pin_at_irq_node(data, node, apic1, pin1, apic2, pin2);
2140 irq_domain_deactivate_irq(irq_data);
2141 irq_domain_activate_irq(irq_data, false);
2142 legacy_pic->unmask(0);
2143 if (timer_irq_works()) {
2144 pr_info("....... works.\n");
2145 goto out;
2146 }
2147 /*
2148 * Cleanup, just in case ...
2149 */
2150 legacy_pic->mask(0);
2151 clear_IO_APIC_pin(apic2, pin2);
2152 pr_info("....... failed.\n");
2153 }
2154
2155 pr_info("...trying to set up timer as Virtual Wire IRQ...\n");
2156
2157 lapic_register_intr(0);
2158 apic_write(APIC_LVT0, APIC_DM_FIXED | cfg->vector); /* Fixed mode */
2159 legacy_pic->unmask(0);
2160
2161 if (timer_irq_works()) {
2162 pr_info("..... works.\n");
2163 goto out;
2164 }
2165 legacy_pic->mask(0);
2166 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | cfg->vector);
2167 pr_info("..... failed.\n");
2168
2169 pr_info("...trying to set up timer as ExtINT IRQ...\n");
2170
2171 legacy_pic->init(0);
2172 legacy_pic->make_irq(0);
2173 apic_write(APIC_LVT0, APIC_DM_EXTINT);
2174 legacy_pic->unmask(0);
2175
2176 unlock_ExtINT_logic();
2177
2178 if (timer_irq_works()) {
2179 pr_info("..... works.\n");
2180 goto out;
2181 }
2182
2183 pr_info("..... failed :\n");
2184 if (apic_is_x2apic_enabled()) {
2185 pr_info("Perhaps problem with the pre-enabled x2apic mode\n"
2186 "Try booting with x2apic and interrupt-remapping disabled in the bios.\n");
2187 }
2188 panic("IO-APIC + timer doesn't work! Boot with apic=debug and send a "
2189 "report. Then try booting with the 'noapic' option.\n");
2190out:
2191 local_irq_enable();
2192}
2193
2194/*
2195 * Traditionally ISA IRQ2 is the cascade IRQ, and is not available
2196 * to devices. However there may be an I/O APIC pin available for
2197 * this interrupt regardless. The pin may be left unconnected, but
2198 * typically it will be reused as an ExtINT cascade interrupt for
2199 * the master 8259A. In the MPS case such a pin will normally be
2200 * reported as an ExtINT interrupt in the MP table. With ACPI
2201 * there is no provision for ExtINT interrupts, and in the absence
2202 * of an override it would be treated as an ordinary ISA I/O APIC
2203 * interrupt, that is edge-triggered and unmasked by default. We
2204 * used to do this, but it caused problems on some systems because
2205 * of the NMI watchdog and sometimes IRQ0 of the 8254 timer using
2206 * the same ExtINT cascade interrupt to drive the local APIC of the
2207 * bootstrap processor. Therefore we refrain from routing IRQ2 to
2208 * the I/O APIC in all cases now. No actual device should request
2209 * it anyway. --macro
2210 */
2211#define PIC_IRQS (1UL << PIC_CASCADE_IR)
2212
2213static int mp_irqdomain_create(int ioapic)
2214{
2215 struct mp_ioapic_gsi *gsi_cfg = mp_ioapic_gsi_routing(ioapic);
2216 int hwirqs = mp_ioapic_pin_count(ioapic);
2217 struct ioapic *ip = &ioapics[ioapic];
2218 struct ioapic_domain_cfg *cfg = &ip->irqdomain_cfg;
2219 struct irq_domain *parent;
2220 struct fwnode_handle *fn;
2221 struct irq_fwspec fwspec;
2222
2223 if (cfg->type == IOAPIC_DOMAIN_INVALID)
2224 return 0;
2225
2226 /* Handle device tree enumerated APICs proper */
2227 if (cfg->dev) {
2228 fn = of_node_to_fwnode(cfg->dev);
2229 } else {
2230 fn = irq_domain_alloc_named_id_fwnode("IO-APIC", mpc_ioapic_id(ioapic));
2231 if (!fn)
2232 return -ENOMEM;
2233 }
2234
2235 fwspec.fwnode = fn;
2236 fwspec.param_count = 1;
2237 fwspec.param[0] = mpc_ioapic_id(ioapic);
2238
2239 parent = irq_find_matching_fwspec(&fwspec, DOMAIN_BUS_GENERIC_MSI);
2240 if (!parent) {
2241 if (!cfg->dev)
2242 irq_domain_free_fwnode(fn);
2243 return -ENODEV;
2244 }
2245
2246 ip->irqdomain = irq_domain_create_hierarchy(parent, 0, hwirqs, fn, cfg->ops,
2247 (void *)(long)ioapic);
2248 if (!ip->irqdomain) {
2249 /* Release fw handle if it was allocated above */
2250 if (!cfg->dev)
2251 irq_domain_free_fwnode(fn);
2252 return -ENOMEM;
2253 }
2254
2255 if (cfg->type == IOAPIC_DOMAIN_LEGACY || cfg->type == IOAPIC_DOMAIN_STRICT)
2256 ioapic_dynirq_base = max(ioapic_dynirq_base, gsi_cfg->gsi_end + 1);
2257
2258 return 0;
2259}
2260
2261static void ioapic_destroy_irqdomain(int idx)
2262{
2263 struct ioapic_domain_cfg *cfg = &ioapics[idx].irqdomain_cfg;
2264 struct fwnode_handle *fn = ioapics[idx].irqdomain->fwnode;
2265
2266 if (ioapics[idx].irqdomain) {
2267 irq_domain_remove(ioapics[idx].irqdomain);
2268 if (!cfg->dev)
2269 irq_domain_free_fwnode(fn);
2270 ioapics[idx].irqdomain = NULL;
2271 }
2272}
2273
2274void __init setup_IO_APIC(void)
2275{
2276 int ioapic;
2277
2278 if (ioapic_is_disabled || !nr_ioapics)
2279 return;
2280
2281 io_apic_irqs = nr_legacy_irqs() ? ~PIC_IRQS : ~0UL;
2282
2283 apic_pr_verbose("ENABLING IO-APIC IRQs\n");
2284 for_each_ioapic(ioapic)
2285 BUG_ON(mp_irqdomain_create(ioapic));
2286
2287 /* Set up IO-APIC IRQ routing. */
2288 x86_init.mpparse.setup_ioapic_ids();
2289
2290 sync_Arb_IDs();
2291 setup_IO_APIC_irqs();
2292 init_IO_APIC_traps();
2293 if (nr_legacy_irqs())
2294 check_timer();
2295
2296 ioapic_initialized = 1;
2297}
2298
2299static void resume_ioapic_id(int ioapic_idx)
2300{
2301 union IO_APIC_reg_00 reg_00;
2302
2303 guard(raw_spinlock_irqsave)(&ioapic_lock);
2304 reg_00.raw = io_apic_read(ioapic_idx, 0);
2305 if (reg_00.bits.ID != mpc_ioapic_id(ioapic_idx)) {
2306 reg_00.bits.ID = mpc_ioapic_id(ioapic_idx);
2307 io_apic_write(ioapic_idx, 0, reg_00.raw);
2308 }
2309}
2310
2311static void ioapic_resume(void)
2312{
2313 int ioapic_idx;
2314
2315 for_each_ioapic_reverse(ioapic_idx)
2316 resume_ioapic_id(ioapic_idx);
2317
2318 restore_ioapic_entries();
2319}
2320
2321static struct syscore_ops ioapic_syscore_ops = {
2322 .suspend = save_ioapic_entries,
2323 .resume = ioapic_resume,
2324};
2325
2326static int __init ioapic_init_ops(void)
2327{
2328 register_syscore_ops(&ioapic_syscore_ops);
2329
2330 return 0;
2331}
2332
2333device_initcall(ioapic_init_ops);
2334
2335static int io_apic_get_redir_entries(int ioapic)
2336{
2337 union IO_APIC_reg_01 reg_01;
2338
2339 guard(raw_spinlock_irqsave)(&ioapic_lock);
2340 reg_01.raw = io_apic_read(ioapic, 1);
2341
2342 /*
2343 * The register returns the maximum index redir index supported,
2344 * which is one less than the total number of redir entries.
2345 */
2346 return reg_01.bits.entries + 1;
2347}
2348
2349unsigned int arch_dynirq_lower_bound(unsigned int from)
2350{
2351 unsigned int ret;
2352
2353 /*
2354 * dmar_alloc_hwirq() may be called before setup_IO_APIC(), so use
2355 * gsi_top if ioapic_dynirq_base hasn't been initialized yet.
2356 */
2357 ret = ioapic_dynirq_base ? : gsi_top;
2358
2359 /*
2360 * For DT enabled machines ioapic_dynirq_base is irrelevant and
2361 * always 0. gsi_top can be 0 if there is no IO/APIC registered.
2362 * 0 is an invalid interrupt number for dynamic allocations. Return
2363 * @from instead.
2364 */
2365 return ret ? : from;
2366}
2367
2368#ifdef CONFIG_X86_32
2369static int io_apic_get_unique_id(int ioapic, int apic_id)
2370{
2371 static DECLARE_BITMAP(apic_id_map, MAX_LOCAL_APIC);
2372 const u32 broadcast_id = 0xF;
2373 union IO_APIC_reg_00 reg_00;
2374 int i = 0;
2375
2376 /* Initialize the ID map */
2377 if (bitmap_empty(apic_id_map, MAX_LOCAL_APIC))
2378 copy_phys_cpu_present_map(apic_id_map);
2379
2380 scoped_guard (raw_spinlock_irqsave, &ioapic_lock)
2381 reg_00.raw = io_apic_read(ioapic, 0);
2382
2383 if (apic_id >= broadcast_id) {
2384 pr_warn("IOAPIC[%d]: Invalid apic_id %d, trying %d\n",
2385 ioapic, apic_id, reg_00.bits.ID);
2386 apic_id = reg_00.bits.ID;
2387 }
2388
2389 /* Every APIC in a system must have a unique ID */
2390 if (test_bit(apic_id, apic_id_map)) {
2391 for (i = 0; i < broadcast_id; i++) {
2392 if (!test_bit(i, apic_id_map))
2393 break;
2394 }
2395
2396 if (i == broadcast_id)
2397 panic("Max apic_id exceeded!\n");
2398
2399 pr_warn("IOAPIC[%d]: apic_id %d already used, trying %d\n", ioapic, apic_id, i);
2400 apic_id = i;
2401 }
2402
2403 set_bit(apic_id, apic_id_map);
2404
2405 if (reg_00.bits.ID != apic_id) {
2406 reg_00.bits.ID = apic_id;
2407
2408 scoped_guard (raw_spinlock_irqsave, &ioapic_lock) {
2409 io_apic_write(ioapic, 0, reg_00.raw);
2410 reg_00.raw = io_apic_read(ioapic, 0);
2411 }
2412
2413 /* Sanity check */
2414 if (reg_00.bits.ID != apic_id) {
2415 pr_err("IOAPIC[%d]: Unable to change apic_id!\n", ioapic);
2416 return -1;
2417 }
2418 }
2419
2420 apic_pr_verbose("IOAPIC[%d]: Assigned apic_id %d\n", ioapic, apic_id);
2421
2422 return apic_id;
2423}
2424
2425static u8 io_apic_unique_id(int idx, u8 id)
2426{
2427 if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) && !APIC_XAPIC(boot_cpu_apic_version))
2428 return io_apic_get_unique_id(idx, id);
2429 return id;
2430}
2431#else
2432static u8 io_apic_unique_id(int idx, u8 id)
2433{
2434 union IO_APIC_reg_00 reg_00;
2435 DECLARE_BITMAP(used, 256);
2436 u8 new_id;
2437 int i;
2438
2439 bitmap_zero(used, 256);
2440 for_each_ioapic(i)
2441 __set_bit(mpc_ioapic_id(i), used);
2442
2443 /* Hand out the requested id if available */
2444 if (!test_bit(id, used))
2445 return id;
2446
2447 /*
2448 * Read the current id from the ioapic and keep it if
2449 * available.
2450 */
2451 scoped_guard (raw_spinlock_irqsave, &ioapic_lock)
2452 reg_00.raw = io_apic_read(idx, 0);
2453
2454 new_id = reg_00.bits.ID;
2455 if (!test_bit(new_id, used)) {
2456 apic_pr_verbose("IOAPIC[%d]: Using reg apic_id %d instead of %d\n",
2457 idx, new_id, id);
2458 return new_id;
2459 }
2460
2461 /* Get the next free id and write it to the ioapic. */
2462 new_id = find_first_zero_bit(used, 256);
2463 reg_00.bits.ID = new_id;
2464 scoped_guard (raw_spinlock_irqsave, &ioapic_lock) {
2465 io_apic_write(idx, 0, reg_00.raw);
2466 reg_00.raw = io_apic_read(idx, 0);
2467 }
2468 /* Sanity check */
2469 BUG_ON(reg_00.bits.ID != new_id);
2470
2471 return new_id;
2472}
2473#endif
2474
2475static int io_apic_get_version(int ioapic)
2476{
2477 union IO_APIC_reg_01 reg_01;
2478
2479 guard(raw_spinlock_irqsave)(&ioapic_lock);
2480 reg_01.raw = io_apic_read(ioapic, 1);
2481
2482 return reg_01.bits.version;
2483}
2484
2485/*
2486 * This function updates target affinity of IOAPIC interrupts to include
2487 * the CPUs which came online during SMP bringup.
2488 */
2489#define IOAPIC_RESOURCE_NAME_SIZE 11
2490
2491static struct resource *ioapic_resources;
2492
2493static struct resource * __init ioapic_setup_resources(void)
2494{
2495 struct resource *res;
2496 unsigned long n;
2497 char *mem;
2498 int i;
2499
2500 if (nr_ioapics == 0)
2501 return NULL;
2502
2503 n = IOAPIC_RESOURCE_NAME_SIZE + sizeof(struct resource);
2504 n *= nr_ioapics;
2505
2506 mem = memblock_alloc(n, SMP_CACHE_BYTES);
2507 if (!mem)
2508 panic("%s: Failed to allocate %lu bytes\n", __func__, n);
2509 res = (void *)mem;
2510
2511 mem += sizeof(struct resource) * nr_ioapics;
2512
2513 for_each_ioapic(i) {
2514 res[i].name = mem;
2515 res[i].flags = IORESOURCE_MEM | IORESOURCE_BUSY;
2516 snprintf(mem, IOAPIC_RESOURCE_NAME_SIZE, "IOAPIC %u", i);
2517 mem += IOAPIC_RESOURCE_NAME_SIZE;
2518 ioapics[i].iomem_res = &res[i];
2519 }
2520
2521 ioapic_resources = res;
2522
2523 return res;
2524}
2525
2526static void io_apic_set_fixmap(enum fixed_addresses idx, phys_addr_t phys)
2527{
2528 pgprot_t flags = FIXMAP_PAGE_NOCACHE;
2529
2530 /*
2531 * Ensure fixmaps for IO-APIC MMIO respect memory encryption pgprot
2532 * bits, just like normal ioremap():
2533 */
2534 if (cc_platform_has(CC_ATTR_GUEST_MEM_ENCRYPT)) {
2535 if (x86_platform.hyper.is_private_mmio(phys))
2536 flags = pgprot_encrypted(flags);
2537 else
2538 flags = pgprot_decrypted(flags);
2539 }
2540
2541 __set_fixmap(idx, phys, flags);
2542}
2543
2544void __init io_apic_init_mappings(void)
2545{
2546 unsigned long ioapic_phys, idx = FIX_IO_APIC_BASE_0;
2547 struct resource *ioapic_res;
2548 int i;
2549
2550 ioapic_res = ioapic_setup_resources();
2551 for_each_ioapic(i) {
2552 if (smp_found_config) {
2553 ioapic_phys = mpc_ioapic_addr(i);
2554#ifdef CONFIG_X86_32
2555 if (!ioapic_phys) {
2556 pr_err("WARNING: bogus zero IO-APIC address found in MPTABLE, "
2557 "disabling IO/APIC support!\n");
2558 smp_found_config = 0;
2559 ioapic_is_disabled = true;
2560 goto fake_ioapic_page;
2561 }
2562#endif
2563 } else {
2564#ifdef CONFIG_X86_32
2565fake_ioapic_page:
2566#endif
2567 ioapic_phys = (unsigned long)memblock_alloc(PAGE_SIZE,
2568 PAGE_SIZE);
2569 if (!ioapic_phys)
2570 panic("%s: Failed to allocate %lu bytes align=0x%lx\n",
2571 __func__, PAGE_SIZE, PAGE_SIZE);
2572 ioapic_phys = __pa(ioapic_phys);
2573 }
2574 io_apic_set_fixmap(idx, ioapic_phys);
2575 apic_pr_verbose("mapped IOAPIC to %08lx (%08lx)\n",
2576 __fix_to_virt(idx) + (ioapic_phys & ~PAGE_MASK), ioapic_phys);
2577 idx++;
2578
2579 ioapic_res->start = ioapic_phys;
2580 ioapic_res->end = ioapic_phys + IO_APIC_SLOT_SIZE - 1;
2581 ioapic_res++;
2582 }
2583}
2584
2585void __init ioapic_insert_resources(void)
2586{
2587 struct resource *r = ioapic_resources;
2588 int i;
2589
2590 if (!r) {
2591 if (nr_ioapics > 0)
2592 pr_err("IO APIC resources couldn't be allocated.\n");
2593 return;
2594 }
2595
2596 for_each_ioapic(i) {
2597 insert_resource(&iomem_resource, r);
2598 r++;
2599 }
2600}
2601
2602int mp_find_ioapic(u32 gsi)
2603{
2604 int i;
2605
2606 if (nr_ioapics == 0)
2607 return -1;
2608
2609 /* Find the IOAPIC that manages this GSI. */
2610 for_each_ioapic(i) {
2611 struct mp_ioapic_gsi *gsi_cfg = mp_ioapic_gsi_routing(i);
2612
2613 if (gsi >= gsi_cfg->gsi_base && gsi <= gsi_cfg->gsi_end)
2614 return i;
2615 }
2616
2617 pr_err("ERROR: Unable to locate IOAPIC for GSI %d\n", gsi);
2618 return -1;
2619}
2620
2621int mp_find_ioapic_pin(int ioapic, u32 gsi)
2622{
2623 struct mp_ioapic_gsi *gsi_cfg;
2624
2625 if (WARN_ON(ioapic < 0))
2626 return -1;
2627
2628 gsi_cfg = mp_ioapic_gsi_routing(ioapic);
2629 if (WARN_ON(gsi > gsi_cfg->gsi_end))
2630 return -1;
2631
2632 return gsi - gsi_cfg->gsi_base;
2633}
2634
2635static int bad_ioapic_register(int idx)
2636{
2637 union IO_APIC_reg_00 reg_00;
2638 union IO_APIC_reg_01 reg_01;
2639 union IO_APIC_reg_02 reg_02;
2640
2641 reg_00.raw = io_apic_read(idx, 0);
2642 reg_01.raw = io_apic_read(idx, 1);
2643 reg_02.raw = io_apic_read(idx, 2);
2644
2645 if (reg_00.raw == -1 && reg_01.raw == -1 && reg_02.raw == -1) {
2646 pr_warn("I/O APIC 0x%x registers return all ones, skipping!\n",
2647 mpc_ioapic_addr(idx));
2648 return 1;
2649 }
2650
2651 return 0;
2652}
2653
2654static int find_free_ioapic_entry(void)
2655{
2656 for (int idx = 0; idx < MAX_IO_APICS; idx++) {
2657 if (ioapics[idx].nr_registers == 0)
2658 return idx;
2659 }
2660 return MAX_IO_APICS;
2661}
2662
2663/**
2664 * mp_register_ioapic - Register an IOAPIC device
2665 * @id: hardware IOAPIC ID
2666 * @address: physical address of IOAPIC register area
2667 * @gsi_base: base of GSI associated with the IOAPIC
2668 * @cfg: configuration information for the IOAPIC
2669 */
2670int mp_register_ioapic(int id, u32 address, u32 gsi_base, struct ioapic_domain_cfg *cfg)
2671{
2672 bool hotplug = !!ioapic_initialized;
2673 struct mp_ioapic_gsi *gsi_cfg;
2674 int idx, ioapic, entries;
2675 u32 gsi_end;
2676
2677 if (!address) {
2678 pr_warn("Bogus (zero) I/O APIC address found, skipping!\n");
2679 return -EINVAL;
2680 }
2681
2682 for_each_ioapic(ioapic) {
2683 if (ioapics[ioapic].mp_config.apicaddr == address) {
2684 pr_warn("address 0x%x conflicts with IOAPIC%d\n", address, ioapic);
2685 return -EEXIST;
2686 }
2687 }
2688
2689 idx = find_free_ioapic_entry();
2690 if (idx >= MAX_IO_APICS) {
2691 pr_warn("Max # of I/O APICs (%d) exceeded (found %d), skipping\n",
2692 MAX_IO_APICS, idx);
2693 return -ENOSPC;
2694 }
2695
2696 ioapics[idx].mp_config.type = MP_IOAPIC;
2697 ioapics[idx].mp_config.flags = MPC_APIC_USABLE;
2698 ioapics[idx].mp_config.apicaddr = address;
2699
2700 io_apic_set_fixmap(FIX_IO_APIC_BASE_0 + idx, address);
2701 if (bad_ioapic_register(idx)) {
2702 clear_fixmap(FIX_IO_APIC_BASE_0 + idx);
2703 return -ENODEV;
2704 }
2705
2706 ioapics[idx].mp_config.apicid = io_apic_unique_id(idx, id);
2707 ioapics[idx].mp_config.apicver = io_apic_get_version(idx);
2708
2709 /*
2710 * Build basic GSI lookup table to facilitate gsi->io_apic lookups
2711 * and to prevent reprogramming of IOAPIC pins (PCI GSIs).
2712 */
2713 entries = io_apic_get_redir_entries(idx);
2714 gsi_end = gsi_base + entries - 1;
2715 for_each_ioapic(ioapic) {
2716 gsi_cfg = mp_ioapic_gsi_routing(ioapic);
2717 if ((gsi_base >= gsi_cfg->gsi_base &&
2718 gsi_base <= gsi_cfg->gsi_end) ||
2719 (gsi_end >= gsi_cfg->gsi_base &&
2720 gsi_end <= gsi_cfg->gsi_end)) {
2721 pr_warn("GSI range [%u-%u] for new IOAPIC conflicts with GSI[%u-%u]\n",
2722 gsi_base, gsi_end, gsi_cfg->gsi_base, gsi_cfg->gsi_end);
2723 clear_fixmap(FIX_IO_APIC_BASE_0 + idx);
2724 return -ENOSPC;
2725 }
2726 }
2727 gsi_cfg = mp_ioapic_gsi_routing(idx);
2728 gsi_cfg->gsi_base = gsi_base;
2729 gsi_cfg->gsi_end = gsi_end;
2730
2731 ioapics[idx].irqdomain = NULL;
2732 ioapics[idx].irqdomain_cfg = *cfg;
2733
2734 /*
2735 * If mp_register_ioapic() is called during early boot stage when
2736 * walking ACPI/DT tables, it's too early to create irqdomain,
2737 * we are still using bootmem allocator. So delay it to setup_IO_APIC().
2738 */
2739 if (hotplug) {
2740 if (mp_irqdomain_create(idx)) {
2741 clear_fixmap(FIX_IO_APIC_BASE_0 + idx);
2742 return -ENOMEM;
2743 }
2744 alloc_ioapic_saved_registers(idx);
2745 }
2746
2747 if (gsi_cfg->gsi_end >= gsi_top)
2748 gsi_top = gsi_cfg->gsi_end + 1;
2749 if (nr_ioapics <= idx)
2750 nr_ioapics = idx + 1;
2751
2752 /* Set nr_registers to mark entry present */
2753 ioapics[idx].nr_registers = entries;
2754
2755 pr_info("IOAPIC[%d]: apic_id %d, version %d, address 0x%x, GSI %d-%d\n",
2756 idx, mpc_ioapic_id(idx), mpc_ioapic_ver(idx), mpc_ioapic_addr(idx),
2757 gsi_cfg->gsi_base, gsi_cfg->gsi_end);
2758
2759 return 0;
2760}
2761
2762int mp_unregister_ioapic(u32 gsi_base)
2763{
2764 int ioapic, pin;
2765 int found = 0;
2766
2767 for_each_ioapic(ioapic) {
2768 if (ioapics[ioapic].gsi_config.gsi_base == gsi_base) {
2769 found = 1;
2770 break;
2771 }
2772 }
2773
2774 if (!found) {
2775 pr_warn("can't find IOAPIC for GSI %d\n", gsi_base);
2776 return -ENODEV;
2777 }
2778
2779 for_each_pin(ioapic, pin) {
2780 u32 gsi = mp_pin_to_gsi(ioapic, pin);
2781 int irq = mp_map_gsi_to_irq(gsi, 0, NULL);
2782 struct mp_chip_data *data;
2783
2784 if (irq >= 0) {
2785 data = irq_get_chip_data(irq);
2786 if (data && data->count) {
2787 pr_warn("pin%d on IOAPIC%d is still in use.\n", pin, ioapic);
2788 return -EBUSY;
2789 }
2790 }
2791 }
2792
2793 /* Mark entry not present */
2794 ioapics[ioapic].nr_registers = 0;
2795 ioapic_destroy_irqdomain(ioapic);
2796 free_ioapic_saved_registers(ioapic);
2797 if (ioapics[ioapic].iomem_res)
2798 release_resource(ioapics[ioapic].iomem_res);
2799 clear_fixmap(FIX_IO_APIC_BASE_0 + ioapic);
2800 memset(&ioapics[ioapic], 0, sizeof(ioapics[ioapic]));
2801
2802 return 0;
2803}
2804
2805int mp_ioapic_registered(u32 gsi_base)
2806{
2807 int ioapic;
2808
2809 for_each_ioapic(ioapic)
2810 if (ioapics[ioapic].gsi_config.gsi_base == gsi_base)
2811 return 1;
2812
2813 return 0;
2814}
2815
2816static void mp_irqdomain_get_attr(u32 gsi, struct mp_chip_data *data,
2817 struct irq_alloc_info *info)
2818{
2819 if (info && info->ioapic.valid) {
2820 data->is_level = info->ioapic.is_level;
2821 data->active_low = info->ioapic.active_low;
2822 } else if (__acpi_get_override_irq(gsi, &data->is_level, &data->active_low) < 0) {
2823 /* PCI interrupts are always active low level triggered. */
2824 data->is_level = true;
2825 data->active_low = true;
2826 }
2827}
2828
2829/*
2830 * Configure the I/O-APIC specific fields in the routing entry.
2831 *
2832 * This is important to setup the I/O-APIC specific bits (is_level,
2833 * active_low, masked) because the underlying parent domain will only
2834 * provide the routing information and is oblivious of the I/O-APIC
2835 * specific bits.
2836 *
2837 * The entry is just preconfigured at this point and not written into the
2838 * RTE. This happens later during activation which will fill in the actual
2839 * routing information.
2840 */
2841static void mp_preconfigure_entry(struct mp_chip_data *data)
2842{
2843 struct IO_APIC_route_entry *entry = &data->entry;
2844
2845 memset(entry, 0, sizeof(*entry));
2846 entry->is_level = data->is_level;
2847 entry->active_low = data->active_low;
2848 /*
2849 * Mask level triggered irqs. Edge triggered irqs are masked
2850 * by the irq core code in case they fire.
2851 */
2852 entry->masked = data->is_level;
2853}
2854
2855int mp_irqdomain_alloc(struct irq_domain *domain, unsigned int virq,
2856 unsigned int nr_irqs, void *arg)
2857{
2858 struct irq_alloc_info *info = arg;
2859 struct mp_chip_data *data;
2860 struct irq_data *irq_data;
2861 int ret, ioapic, pin;
2862 unsigned long flags;
2863
2864 if (!info || nr_irqs > 1)
2865 return -EINVAL;
2866 irq_data = irq_domain_get_irq_data(domain, virq);
2867 if (!irq_data)
2868 return -EINVAL;
2869
2870 ioapic = mp_irqdomain_ioapic_idx(domain);
2871 pin = info->ioapic.pin;
2872 if (irq_find_mapping(domain, (irq_hw_number_t)pin) > 0)
2873 return -EEXIST;
2874
2875 data = kzalloc(sizeof(*data), GFP_KERNEL);
2876 if (!data)
2877 return -ENOMEM;
2878
2879 ret = irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, info);
2880 if (ret < 0)
2881 goto free_data;
2882
2883 INIT_LIST_HEAD(&data->irq_2_pin);
2884 irq_data->hwirq = info->ioapic.pin;
2885 irq_data->chip = (domain->parent == x86_vector_domain) ?
2886 &ioapic_chip : &ioapic_ir_chip;
2887 irq_data->chip_data = data;
2888 mp_irqdomain_get_attr(mp_pin_to_gsi(ioapic, pin), data, info);
2889
2890 if (!add_pin_to_irq_node(data, ioapic_alloc_attr_node(info), ioapic, pin)) {
2891 ret = -ENOMEM;
2892 goto free_irqs;
2893 }
2894
2895 mp_preconfigure_entry(data);
2896 mp_register_handler(virq, data->is_level);
2897
2898 local_irq_save(flags);
2899 if (virq < nr_legacy_irqs())
2900 legacy_pic->mask(virq);
2901 local_irq_restore(flags);
2902
2903 apic_pr_verbose("IOAPIC[%d]: Preconfigured routing entry (%d-%d -> IRQ %d Level:%i ActiveLow:%i)\n",
2904 ioapic, mpc_ioapic_id(ioapic), pin, virq, data->is_level, data->active_low);
2905 return 0;
2906
2907free_irqs:
2908 irq_domain_free_irqs_parent(domain, virq, nr_irqs);
2909free_data:
2910 kfree(data);
2911 return ret;
2912}
2913
2914void mp_irqdomain_free(struct irq_domain *domain, unsigned int virq,
2915 unsigned int nr_irqs)
2916{
2917 struct irq_data *irq_data;
2918 struct mp_chip_data *data;
2919
2920 BUG_ON(nr_irqs != 1);
2921 irq_data = irq_domain_get_irq_data(domain, virq);
2922 if (irq_data && irq_data->chip_data) {
2923 data = irq_data->chip_data;
2924 __remove_pin_from_irq(data, mp_irqdomain_ioapic_idx(domain), (int)irq_data->hwirq);
2925 WARN_ON(!list_empty(&data->irq_2_pin));
2926 kfree(irq_data->chip_data);
2927 }
2928 irq_domain_free_irqs_top(domain, virq, nr_irqs);
2929}
2930
2931int mp_irqdomain_activate(struct irq_domain *domain, struct irq_data *irq_data, bool reserve)
2932{
2933 guard(raw_spinlock_irqsave)(&ioapic_lock);
2934 ioapic_configure_entry(irq_data);
2935 return 0;
2936}
2937
2938void mp_irqdomain_deactivate(struct irq_domain *domain,
2939 struct irq_data *irq_data)
2940{
2941 /* It won't be called for IRQ with multiple IOAPIC pins associated */
2942 ioapic_mask_entry(mp_irqdomain_ioapic_idx(domain), (int)irq_data->hwirq);
2943}
2944
2945int mp_irqdomain_ioapic_idx(struct irq_domain *domain)
2946{
2947 return (int)(long)domain->host_data;
2948}
2949
2950const struct irq_domain_ops mp_ioapic_irqdomain_ops = {
2951 .alloc = mp_irqdomain_alloc,
2952 .free = mp_irqdomain_free,
2953 .activate = mp_irqdomain_activate,
2954 .deactivate = mp_irqdomain_deactivate,
2955};
1/*
2 * Intel IO-APIC support for multi-Pentium hosts.
3 *
4 * Copyright (C) 1997, 1998, 1999, 2000, 2009 Ingo Molnar, Hajnalka Szabo
5 *
6 * Many thanks to Stig Venaas for trying out countless experimental
7 * patches and reporting/debugging problems patiently!
8 *
9 * (c) 1999, Multiple IO-APIC support, developed by
10 * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
11 * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
12 * further tested and cleaned up by Zach Brown <zab@redhat.com>
13 * and Ingo Molnar <mingo@redhat.com>
14 *
15 * Fixes
16 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
17 * thanks to Eric Gilmore
18 * and Rolf G. Tews
19 * for testing these extensively
20 * Paul Diefenbaugh : Added full ACPI support
21 */
22
23#include <linux/mm.h>
24#include <linux/interrupt.h>
25#include <linux/init.h>
26#include <linux/delay.h>
27#include <linux/sched.h>
28#include <linux/pci.h>
29#include <linux/mc146818rtc.h>
30#include <linux/compiler.h>
31#include <linux/acpi.h>
32#include <linux/module.h>
33#include <linux/syscore_ops.h>
34#include <linux/msi.h>
35#include <linux/htirq.h>
36#include <linux/freezer.h>
37#include <linux/kthread.h>
38#include <linux/jiffies.h> /* time_after() */
39#include <linux/slab.h>
40#ifdef CONFIG_ACPI
41#include <acpi/acpi_bus.h>
42#endif
43#include <linux/bootmem.h>
44#include <linux/dmar.h>
45#include <linux/hpet.h>
46
47#include <asm/idle.h>
48#include <asm/io.h>
49#include <asm/smp.h>
50#include <asm/cpu.h>
51#include <asm/desc.h>
52#include <asm/proto.h>
53#include <asm/acpi.h>
54#include <asm/dma.h>
55#include <asm/timer.h>
56#include <asm/i8259.h>
57#include <asm/msidef.h>
58#include <asm/hypertransport.h>
59#include <asm/setup.h>
60#include <asm/irq_remapping.h>
61#include <asm/hpet.h>
62#include <asm/hw_irq.h>
63
64#include <asm/apic.h>
65
66#define __apicdebuginit(type) static type __init
67#define for_each_irq_pin(entry, head) \
68 for (entry = head; entry; entry = entry->next)
69
70/*
71 * Is the SiS APIC rmw bug present ?
72 * -1 = don't know, 0 = no, 1 = yes
73 */
74int sis_apic_bug = -1;
75
76static DEFINE_RAW_SPINLOCK(ioapic_lock);
77static DEFINE_RAW_SPINLOCK(vector_lock);
78
79static struct ioapic {
80 /*
81 * # of IRQ routing registers
82 */
83 int nr_registers;
84 /*
85 * Saved state during suspend/resume, or while enabling intr-remap.
86 */
87 struct IO_APIC_route_entry *saved_registers;
88 /* I/O APIC config */
89 struct mpc_ioapic mp_config;
90 /* IO APIC gsi routing info */
91 struct mp_ioapic_gsi gsi_config;
92 DECLARE_BITMAP(pin_programmed, MP_MAX_IOAPIC_PIN + 1);
93} ioapics[MAX_IO_APICS];
94
95#define mpc_ioapic_ver(id) ioapics[id].mp_config.apicver
96
97int mpc_ioapic_id(int id)
98{
99 return ioapics[id].mp_config.apicid;
100}
101
102unsigned int mpc_ioapic_addr(int id)
103{
104 return ioapics[id].mp_config.apicaddr;
105}
106
107struct mp_ioapic_gsi *mp_ioapic_gsi_routing(int id)
108{
109 return &ioapics[id].gsi_config;
110}
111
112int nr_ioapics;
113
114/* The one past the highest gsi number used */
115u32 gsi_top;
116
117/* MP IRQ source entries */
118struct mpc_intsrc mp_irqs[MAX_IRQ_SOURCES];
119
120/* # of MP IRQ source entries */
121int mp_irq_entries;
122
123/* GSI interrupts */
124static int nr_irqs_gsi = NR_IRQS_LEGACY;
125
126#if defined (CONFIG_MCA) || defined (CONFIG_EISA)
127int mp_bus_id_to_type[MAX_MP_BUSSES];
128#endif
129
130DECLARE_BITMAP(mp_bus_not_pci, MAX_MP_BUSSES);
131
132int skip_ioapic_setup;
133
134/**
135 * disable_ioapic_support() - disables ioapic support at runtime
136 */
137void disable_ioapic_support(void)
138{
139#ifdef CONFIG_PCI
140 noioapicquirk = 1;
141 noioapicreroute = -1;
142#endif
143 skip_ioapic_setup = 1;
144}
145
146static int __init parse_noapic(char *str)
147{
148 /* disable IO-APIC */
149 disable_ioapic_support();
150 return 0;
151}
152early_param("noapic", parse_noapic);
153
154static int io_apic_setup_irq_pin(unsigned int irq, int node,
155 struct io_apic_irq_attr *attr);
156
157/* Will be called in mpparse/acpi/sfi codes for saving IRQ info */
158void mp_save_irq(struct mpc_intsrc *m)
159{
160 int i;
161
162 apic_printk(APIC_VERBOSE, "Int: type %d, pol %d, trig %d, bus %02x,"
163 " IRQ %02x, APIC ID %x, APIC INT %02x\n",
164 m->irqtype, m->irqflag & 3, (m->irqflag >> 2) & 3, m->srcbus,
165 m->srcbusirq, m->dstapic, m->dstirq);
166
167 for (i = 0; i < mp_irq_entries; i++) {
168 if (!memcmp(&mp_irqs[i], m, sizeof(*m)))
169 return;
170 }
171
172 memcpy(&mp_irqs[mp_irq_entries], m, sizeof(*m));
173 if (++mp_irq_entries == MAX_IRQ_SOURCES)
174 panic("Max # of irq sources exceeded!!\n");
175}
176
177struct irq_pin_list {
178 int apic, pin;
179 struct irq_pin_list *next;
180};
181
182static struct irq_pin_list *alloc_irq_pin_list(int node)
183{
184 return kzalloc_node(sizeof(struct irq_pin_list), GFP_KERNEL, node);
185}
186
187
188/* irq_cfg is indexed by the sum of all RTEs in all I/O APICs. */
189#ifdef CONFIG_SPARSE_IRQ
190static struct irq_cfg irq_cfgx[NR_IRQS_LEGACY];
191#else
192static struct irq_cfg irq_cfgx[NR_IRQS];
193#endif
194
195int __init arch_early_irq_init(void)
196{
197 struct irq_cfg *cfg;
198 int count, node, i;
199
200 if (!legacy_pic->nr_legacy_irqs) {
201 nr_irqs_gsi = 0;
202 io_apic_irqs = ~0UL;
203 }
204
205 for (i = 0; i < nr_ioapics; i++) {
206 ioapics[i].saved_registers =
207 kzalloc(sizeof(struct IO_APIC_route_entry) *
208 ioapics[i].nr_registers, GFP_KERNEL);
209 if (!ioapics[i].saved_registers)
210 pr_err("IOAPIC %d: suspend/resume impossible!\n", i);
211 }
212
213 cfg = irq_cfgx;
214 count = ARRAY_SIZE(irq_cfgx);
215 node = cpu_to_node(0);
216
217 /* Make sure the legacy interrupts are marked in the bitmap */
218 irq_reserve_irqs(0, legacy_pic->nr_legacy_irqs);
219
220 for (i = 0; i < count; i++) {
221 irq_set_chip_data(i, &cfg[i]);
222 zalloc_cpumask_var_node(&cfg[i].domain, GFP_KERNEL, node);
223 zalloc_cpumask_var_node(&cfg[i].old_domain, GFP_KERNEL, node);
224 /*
225 * For legacy IRQ's, start with assigning irq0 to irq15 to
226 * IRQ0_VECTOR to IRQ15_VECTOR on cpu 0.
227 */
228 if (i < legacy_pic->nr_legacy_irqs) {
229 cfg[i].vector = IRQ0_VECTOR + i;
230 cpumask_set_cpu(0, cfg[i].domain);
231 }
232 }
233
234 return 0;
235}
236
237#ifdef CONFIG_SPARSE_IRQ
238static struct irq_cfg *irq_cfg(unsigned int irq)
239{
240 return irq_get_chip_data(irq);
241}
242
243static struct irq_cfg *alloc_irq_cfg(unsigned int irq, int node)
244{
245 struct irq_cfg *cfg;
246
247 cfg = kzalloc_node(sizeof(*cfg), GFP_KERNEL, node);
248 if (!cfg)
249 return NULL;
250 if (!zalloc_cpumask_var_node(&cfg->domain, GFP_KERNEL, node))
251 goto out_cfg;
252 if (!zalloc_cpumask_var_node(&cfg->old_domain, GFP_KERNEL, node))
253 goto out_domain;
254 return cfg;
255out_domain:
256 free_cpumask_var(cfg->domain);
257out_cfg:
258 kfree(cfg);
259 return NULL;
260}
261
262static void free_irq_cfg(unsigned int at, struct irq_cfg *cfg)
263{
264 if (!cfg)
265 return;
266 irq_set_chip_data(at, NULL);
267 free_cpumask_var(cfg->domain);
268 free_cpumask_var(cfg->old_domain);
269 kfree(cfg);
270}
271
272#else
273
274struct irq_cfg *irq_cfg(unsigned int irq)
275{
276 return irq < nr_irqs ? irq_cfgx + irq : NULL;
277}
278
279static struct irq_cfg *alloc_irq_cfg(unsigned int irq, int node)
280{
281 return irq_cfgx + irq;
282}
283
284static inline void free_irq_cfg(unsigned int at, struct irq_cfg *cfg) { }
285
286#endif
287
288static struct irq_cfg *alloc_irq_and_cfg_at(unsigned int at, int node)
289{
290 int res = irq_alloc_desc_at(at, node);
291 struct irq_cfg *cfg;
292
293 if (res < 0) {
294 if (res != -EEXIST)
295 return NULL;
296 cfg = irq_get_chip_data(at);
297 if (cfg)
298 return cfg;
299 }
300
301 cfg = alloc_irq_cfg(at, node);
302 if (cfg)
303 irq_set_chip_data(at, cfg);
304 else
305 irq_free_desc(at);
306 return cfg;
307}
308
309static int alloc_irq_from(unsigned int from, int node)
310{
311 return irq_alloc_desc_from(from, node);
312}
313
314static void free_irq_at(unsigned int at, struct irq_cfg *cfg)
315{
316 free_irq_cfg(at, cfg);
317 irq_free_desc(at);
318}
319
320struct io_apic {
321 unsigned int index;
322 unsigned int unused[3];
323 unsigned int data;
324 unsigned int unused2[11];
325 unsigned int eoi;
326};
327
328static __attribute_const__ struct io_apic __iomem *io_apic_base(int idx)
329{
330 return (void __iomem *) __fix_to_virt(FIX_IO_APIC_BASE_0 + idx)
331 + (mpc_ioapic_addr(idx) & ~PAGE_MASK);
332}
333
334static inline void io_apic_eoi(unsigned int apic, unsigned int vector)
335{
336 struct io_apic __iomem *io_apic = io_apic_base(apic);
337 writel(vector, &io_apic->eoi);
338}
339
340static inline unsigned int io_apic_read(unsigned int apic, unsigned int reg)
341{
342 struct io_apic __iomem *io_apic = io_apic_base(apic);
343 writel(reg, &io_apic->index);
344 return readl(&io_apic->data);
345}
346
347static inline void io_apic_write(unsigned int apic, unsigned int reg, unsigned int value)
348{
349 struct io_apic __iomem *io_apic = io_apic_base(apic);
350 writel(reg, &io_apic->index);
351 writel(value, &io_apic->data);
352}
353
354/*
355 * Re-write a value: to be used for read-modify-write
356 * cycles where the read already set up the index register.
357 *
358 * Older SiS APIC requires we rewrite the index register
359 */
360static inline void io_apic_modify(unsigned int apic, unsigned int reg, unsigned int value)
361{
362 struct io_apic __iomem *io_apic = io_apic_base(apic);
363
364 if (sis_apic_bug)
365 writel(reg, &io_apic->index);
366 writel(value, &io_apic->data);
367}
368
369static bool io_apic_level_ack_pending(struct irq_cfg *cfg)
370{
371 struct irq_pin_list *entry;
372 unsigned long flags;
373
374 raw_spin_lock_irqsave(&ioapic_lock, flags);
375 for_each_irq_pin(entry, cfg->irq_2_pin) {
376 unsigned int reg;
377 int pin;
378
379 pin = entry->pin;
380 reg = io_apic_read(entry->apic, 0x10 + pin*2);
381 /* Is the remote IRR bit set? */
382 if (reg & IO_APIC_REDIR_REMOTE_IRR) {
383 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
384 return true;
385 }
386 }
387 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
388
389 return false;
390}
391
392union entry_union {
393 struct { u32 w1, w2; };
394 struct IO_APIC_route_entry entry;
395};
396
397static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin)
398{
399 union entry_union eu;
400 unsigned long flags;
401 raw_spin_lock_irqsave(&ioapic_lock, flags);
402 eu.w1 = io_apic_read(apic, 0x10 + 2 * pin);
403 eu.w2 = io_apic_read(apic, 0x11 + 2 * pin);
404 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
405 return eu.entry;
406}
407
408/*
409 * When we write a new IO APIC routing entry, we need to write the high
410 * word first! If the mask bit in the low word is clear, we will enable
411 * the interrupt, and we need to make sure the entry is fully populated
412 * before that happens.
413 */
414static void
415__ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
416{
417 union entry_union eu = {{0, 0}};
418
419 eu.entry = e;
420 io_apic_write(apic, 0x11 + 2*pin, eu.w2);
421 io_apic_write(apic, 0x10 + 2*pin, eu.w1);
422}
423
424static void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
425{
426 unsigned long flags;
427 raw_spin_lock_irqsave(&ioapic_lock, flags);
428 __ioapic_write_entry(apic, pin, e);
429 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
430}
431
432/*
433 * When we mask an IO APIC routing entry, we need to write the low
434 * word first, in order to set the mask bit before we change the
435 * high bits!
436 */
437static void ioapic_mask_entry(int apic, int pin)
438{
439 unsigned long flags;
440 union entry_union eu = { .entry.mask = 1 };
441
442 raw_spin_lock_irqsave(&ioapic_lock, flags);
443 io_apic_write(apic, 0x10 + 2*pin, eu.w1);
444 io_apic_write(apic, 0x11 + 2*pin, eu.w2);
445 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
446}
447
448/*
449 * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
450 * shared ISA-space IRQs, so we have to support them. We are super
451 * fast in the common case, and fast for shared ISA-space IRQs.
452 */
453static int
454__add_pin_to_irq_node(struct irq_cfg *cfg, int node, int apic, int pin)
455{
456 struct irq_pin_list **last, *entry;
457
458 /* don't allow duplicates */
459 last = &cfg->irq_2_pin;
460 for_each_irq_pin(entry, cfg->irq_2_pin) {
461 if (entry->apic == apic && entry->pin == pin)
462 return 0;
463 last = &entry->next;
464 }
465
466 entry = alloc_irq_pin_list(node);
467 if (!entry) {
468 printk(KERN_ERR "can not alloc irq_pin_list (%d,%d,%d)\n",
469 node, apic, pin);
470 return -ENOMEM;
471 }
472 entry->apic = apic;
473 entry->pin = pin;
474
475 *last = entry;
476 return 0;
477}
478
479static void add_pin_to_irq_node(struct irq_cfg *cfg, int node, int apic, int pin)
480{
481 if (__add_pin_to_irq_node(cfg, node, apic, pin))
482 panic("IO-APIC: failed to add irq-pin. Can not proceed\n");
483}
484
485/*
486 * Reroute an IRQ to a different pin.
487 */
488static void __init replace_pin_at_irq_node(struct irq_cfg *cfg, int node,
489 int oldapic, int oldpin,
490 int newapic, int newpin)
491{
492 struct irq_pin_list *entry;
493
494 for_each_irq_pin(entry, cfg->irq_2_pin) {
495 if (entry->apic == oldapic && entry->pin == oldpin) {
496 entry->apic = newapic;
497 entry->pin = newpin;
498 /* every one is different, right? */
499 return;
500 }
501 }
502
503 /* old apic/pin didn't exist, so just add new ones */
504 add_pin_to_irq_node(cfg, node, newapic, newpin);
505}
506
507static void __io_apic_modify_irq(struct irq_pin_list *entry,
508 int mask_and, int mask_or,
509 void (*final)(struct irq_pin_list *entry))
510{
511 unsigned int reg, pin;
512
513 pin = entry->pin;
514 reg = io_apic_read(entry->apic, 0x10 + pin * 2);
515 reg &= mask_and;
516 reg |= mask_or;
517 io_apic_modify(entry->apic, 0x10 + pin * 2, reg);
518 if (final)
519 final(entry);
520}
521
522static void io_apic_modify_irq(struct irq_cfg *cfg,
523 int mask_and, int mask_or,
524 void (*final)(struct irq_pin_list *entry))
525{
526 struct irq_pin_list *entry;
527
528 for_each_irq_pin(entry, cfg->irq_2_pin)
529 __io_apic_modify_irq(entry, mask_and, mask_or, final);
530}
531
532static void __mask_and_edge_IO_APIC_irq(struct irq_pin_list *entry)
533{
534 __io_apic_modify_irq(entry, ~IO_APIC_REDIR_LEVEL_TRIGGER,
535 IO_APIC_REDIR_MASKED, NULL);
536}
537
538static void __unmask_and_level_IO_APIC_irq(struct irq_pin_list *entry)
539{
540 __io_apic_modify_irq(entry, ~IO_APIC_REDIR_MASKED,
541 IO_APIC_REDIR_LEVEL_TRIGGER, NULL);
542}
543
544static void io_apic_sync(struct irq_pin_list *entry)
545{
546 /*
547 * Synchronize the IO-APIC and the CPU by doing
548 * a dummy read from the IO-APIC
549 */
550 struct io_apic __iomem *io_apic;
551 io_apic = io_apic_base(entry->apic);
552 readl(&io_apic->data);
553}
554
555static void mask_ioapic(struct irq_cfg *cfg)
556{
557 unsigned long flags;
558
559 raw_spin_lock_irqsave(&ioapic_lock, flags);
560 io_apic_modify_irq(cfg, ~0, IO_APIC_REDIR_MASKED, &io_apic_sync);
561 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
562}
563
564static void mask_ioapic_irq(struct irq_data *data)
565{
566 mask_ioapic(data->chip_data);
567}
568
569static void __unmask_ioapic(struct irq_cfg *cfg)
570{
571 io_apic_modify_irq(cfg, ~IO_APIC_REDIR_MASKED, 0, NULL);
572}
573
574static void unmask_ioapic(struct irq_cfg *cfg)
575{
576 unsigned long flags;
577
578 raw_spin_lock_irqsave(&ioapic_lock, flags);
579 __unmask_ioapic(cfg);
580 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
581}
582
583static void unmask_ioapic_irq(struct irq_data *data)
584{
585 unmask_ioapic(data->chip_data);
586}
587
588static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
589{
590 struct IO_APIC_route_entry entry;
591
592 /* Check delivery_mode to be sure we're not clearing an SMI pin */
593 entry = ioapic_read_entry(apic, pin);
594 if (entry.delivery_mode == dest_SMI)
595 return;
596 /*
597 * Disable it in the IO-APIC irq-routing table:
598 */
599 ioapic_mask_entry(apic, pin);
600}
601
602static void clear_IO_APIC (void)
603{
604 int apic, pin;
605
606 for (apic = 0; apic < nr_ioapics; apic++)
607 for (pin = 0; pin < ioapics[apic].nr_registers; pin++)
608 clear_IO_APIC_pin(apic, pin);
609}
610
611#ifdef CONFIG_X86_32
612/*
613 * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to
614 * specific CPU-side IRQs.
615 */
616
617#define MAX_PIRQS 8
618static int pirq_entries[MAX_PIRQS] = {
619 [0 ... MAX_PIRQS - 1] = -1
620};
621
622static int __init ioapic_pirq_setup(char *str)
623{
624 int i, max;
625 int ints[MAX_PIRQS+1];
626
627 get_options(str, ARRAY_SIZE(ints), ints);
628
629 apic_printk(APIC_VERBOSE, KERN_INFO
630 "PIRQ redirection, working around broken MP-BIOS.\n");
631 max = MAX_PIRQS;
632 if (ints[0] < MAX_PIRQS)
633 max = ints[0];
634
635 for (i = 0; i < max; i++) {
636 apic_printk(APIC_VERBOSE, KERN_DEBUG
637 "... PIRQ%d -> IRQ %d\n", i, ints[i+1]);
638 /*
639 * PIRQs are mapped upside down, usually.
640 */
641 pirq_entries[MAX_PIRQS-i-1] = ints[i+1];
642 }
643 return 1;
644}
645
646__setup("pirq=", ioapic_pirq_setup);
647#endif /* CONFIG_X86_32 */
648
649/*
650 * Saves all the IO-APIC RTE's
651 */
652int save_ioapic_entries(void)
653{
654 int apic, pin;
655 int err = 0;
656
657 for (apic = 0; apic < nr_ioapics; apic++) {
658 if (!ioapics[apic].saved_registers) {
659 err = -ENOMEM;
660 continue;
661 }
662
663 for (pin = 0; pin < ioapics[apic].nr_registers; pin++)
664 ioapics[apic].saved_registers[pin] =
665 ioapic_read_entry(apic, pin);
666 }
667
668 return err;
669}
670
671/*
672 * Mask all IO APIC entries.
673 */
674void mask_ioapic_entries(void)
675{
676 int apic, pin;
677
678 for (apic = 0; apic < nr_ioapics; apic++) {
679 if (!ioapics[apic].saved_registers)
680 continue;
681
682 for (pin = 0; pin < ioapics[apic].nr_registers; pin++) {
683 struct IO_APIC_route_entry entry;
684
685 entry = ioapics[apic].saved_registers[pin];
686 if (!entry.mask) {
687 entry.mask = 1;
688 ioapic_write_entry(apic, pin, entry);
689 }
690 }
691 }
692}
693
694/*
695 * Restore IO APIC entries which was saved in the ioapic structure.
696 */
697int restore_ioapic_entries(void)
698{
699 int apic, pin;
700
701 for (apic = 0; apic < nr_ioapics; apic++) {
702 if (!ioapics[apic].saved_registers)
703 continue;
704
705 for (pin = 0; pin < ioapics[apic].nr_registers; pin++)
706 ioapic_write_entry(apic, pin,
707 ioapics[apic].saved_registers[pin]);
708 }
709 return 0;
710}
711
712/*
713 * Find the IRQ entry number of a certain pin.
714 */
715static int find_irq_entry(int apic, int pin, int type)
716{
717 int i;
718
719 for (i = 0; i < mp_irq_entries; i++)
720 if (mp_irqs[i].irqtype == type &&
721 (mp_irqs[i].dstapic == mpc_ioapic_id(apic) ||
722 mp_irqs[i].dstapic == MP_APIC_ALL) &&
723 mp_irqs[i].dstirq == pin)
724 return i;
725
726 return -1;
727}
728
729/*
730 * Find the pin to which IRQ[irq] (ISA) is connected
731 */
732static int __init find_isa_irq_pin(int irq, int type)
733{
734 int i;
735
736 for (i = 0; i < mp_irq_entries; i++) {
737 int lbus = mp_irqs[i].srcbus;
738
739 if (test_bit(lbus, mp_bus_not_pci) &&
740 (mp_irqs[i].irqtype == type) &&
741 (mp_irqs[i].srcbusirq == irq))
742
743 return mp_irqs[i].dstirq;
744 }
745 return -1;
746}
747
748static int __init find_isa_irq_apic(int irq, int type)
749{
750 int i;
751
752 for (i = 0; i < mp_irq_entries; i++) {
753 int lbus = mp_irqs[i].srcbus;
754
755 if (test_bit(lbus, mp_bus_not_pci) &&
756 (mp_irqs[i].irqtype == type) &&
757 (mp_irqs[i].srcbusirq == irq))
758 break;
759 }
760 if (i < mp_irq_entries) {
761 int apic;
762 for(apic = 0; apic < nr_ioapics; apic++) {
763 if (mpc_ioapic_id(apic) == mp_irqs[i].dstapic)
764 return apic;
765 }
766 }
767
768 return -1;
769}
770
771#if defined(CONFIG_EISA) || defined(CONFIG_MCA)
772/*
773 * EISA Edge/Level control register, ELCR
774 */
775static int EISA_ELCR(unsigned int irq)
776{
777 if (irq < legacy_pic->nr_legacy_irqs) {
778 unsigned int port = 0x4d0 + (irq >> 3);
779 return (inb(port) >> (irq & 7)) & 1;
780 }
781 apic_printk(APIC_VERBOSE, KERN_INFO
782 "Broken MPtable reports ISA irq %d\n", irq);
783 return 0;
784}
785
786#endif
787
788/* ISA interrupts are always polarity zero edge triggered,
789 * when listed as conforming in the MP table. */
790
791#define default_ISA_trigger(idx) (0)
792#define default_ISA_polarity(idx) (0)
793
794/* EISA interrupts are always polarity zero and can be edge or level
795 * trigger depending on the ELCR value. If an interrupt is listed as
796 * EISA conforming in the MP table, that means its trigger type must
797 * be read in from the ELCR */
798
799#define default_EISA_trigger(idx) (EISA_ELCR(mp_irqs[idx].srcbusirq))
800#define default_EISA_polarity(idx) default_ISA_polarity(idx)
801
802/* PCI interrupts are always polarity one level triggered,
803 * when listed as conforming in the MP table. */
804
805#define default_PCI_trigger(idx) (1)
806#define default_PCI_polarity(idx) (1)
807
808/* MCA interrupts are always polarity zero level triggered,
809 * when listed as conforming in the MP table. */
810
811#define default_MCA_trigger(idx) (1)
812#define default_MCA_polarity(idx) default_ISA_polarity(idx)
813
814static int irq_polarity(int idx)
815{
816 int bus = mp_irqs[idx].srcbus;
817 int polarity;
818
819 /*
820 * Determine IRQ line polarity (high active or low active):
821 */
822 switch (mp_irqs[idx].irqflag & 3)
823 {
824 case 0: /* conforms, ie. bus-type dependent polarity */
825 if (test_bit(bus, mp_bus_not_pci))
826 polarity = default_ISA_polarity(idx);
827 else
828 polarity = default_PCI_polarity(idx);
829 break;
830 case 1: /* high active */
831 {
832 polarity = 0;
833 break;
834 }
835 case 2: /* reserved */
836 {
837 printk(KERN_WARNING "broken BIOS!!\n");
838 polarity = 1;
839 break;
840 }
841 case 3: /* low active */
842 {
843 polarity = 1;
844 break;
845 }
846 default: /* invalid */
847 {
848 printk(KERN_WARNING "broken BIOS!!\n");
849 polarity = 1;
850 break;
851 }
852 }
853 return polarity;
854}
855
856static int irq_trigger(int idx)
857{
858 int bus = mp_irqs[idx].srcbus;
859 int trigger;
860
861 /*
862 * Determine IRQ trigger mode (edge or level sensitive):
863 */
864 switch ((mp_irqs[idx].irqflag>>2) & 3)
865 {
866 case 0: /* conforms, ie. bus-type dependent */
867 if (test_bit(bus, mp_bus_not_pci))
868 trigger = default_ISA_trigger(idx);
869 else
870 trigger = default_PCI_trigger(idx);
871#if defined(CONFIG_EISA) || defined(CONFIG_MCA)
872 switch (mp_bus_id_to_type[bus]) {
873 case MP_BUS_ISA: /* ISA pin */
874 {
875 /* set before the switch */
876 break;
877 }
878 case MP_BUS_EISA: /* EISA pin */
879 {
880 trigger = default_EISA_trigger(idx);
881 break;
882 }
883 case MP_BUS_PCI: /* PCI pin */
884 {
885 /* set before the switch */
886 break;
887 }
888 case MP_BUS_MCA: /* MCA pin */
889 {
890 trigger = default_MCA_trigger(idx);
891 break;
892 }
893 default:
894 {
895 printk(KERN_WARNING "broken BIOS!!\n");
896 trigger = 1;
897 break;
898 }
899 }
900#endif
901 break;
902 case 1: /* edge */
903 {
904 trigger = 0;
905 break;
906 }
907 case 2: /* reserved */
908 {
909 printk(KERN_WARNING "broken BIOS!!\n");
910 trigger = 1;
911 break;
912 }
913 case 3: /* level */
914 {
915 trigger = 1;
916 break;
917 }
918 default: /* invalid */
919 {
920 printk(KERN_WARNING "broken BIOS!!\n");
921 trigger = 0;
922 break;
923 }
924 }
925 return trigger;
926}
927
928static int pin_2_irq(int idx, int apic, int pin)
929{
930 int irq;
931 int bus = mp_irqs[idx].srcbus;
932 struct mp_ioapic_gsi *gsi_cfg = mp_ioapic_gsi_routing(apic);
933
934 /*
935 * Debugging check, we are in big trouble if this message pops up!
936 */
937 if (mp_irqs[idx].dstirq != pin)
938 printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n");
939
940 if (test_bit(bus, mp_bus_not_pci)) {
941 irq = mp_irqs[idx].srcbusirq;
942 } else {
943 u32 gsi = gsi_cfg->gsi_base + pin;
944
945 if (gsi >= NR_IRQS_LEGACY)
946 irq = gsi;
947 else
948 irq = gsi_top + gsi;
949 }
950
951#ifdef CONFIG_X86_32
952 /*
953 * PCI IRQ command line redirection. Yes, limits are hardcoded.
954 */
955 if ((pin >= 16) && (pin <= 23)) {
956 if (pirq_entries[pin-16] != -1) {
957 if (!pirq_entries[pin-16]) {
958 apic_printk(APIC_VERBOSE, KERN_DEBUG
959 "disabling PIRQ%d\n", pin-16);
960 } else {
961 irq = pirq_entries[pin-16];
962 apic_printk(APIC_VERBOSE, KERN_DEBUG
963 "using PIRQ%d -> IRQ %d\n",
964 pin-16, irq);
965 }
966 }
967 }
968#endif
969
970 return irq;
971}
972
973/*
974 * Find a specific PCI IRQ entry.
975 * Not an __init, possibly needed by modules
976 */
977int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin,
978 struct io_apic_irq_attr *irq_attr)
979{
980 int apic, i, best_guess = -1;
981
982 apic_printk(APIC_DEBUG,
983 "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n",
984 bus, slot, pin);
985 if (test_bit(bus, mp_bus_not_pci)) {
986 apic_printk(APIC_VERBOSE,
987 "PCI BIOS passed nonexistent PCI bus %d!\n", bus);
988 return -1;
989 }
990 for (i = 0; i < mp_irq_entries; i++) {
991 int lbus = mp_irqs[i].srcbus;
992
993 for (apic = 0; apic < nr_ioapics; apic++)
994 if (mpc_ioapic_id(apic) == mp_irqs[i].dstapic ||
995 mp_irqs[i].dstapic == MP_APIC_ALL)
996 break;
997
998 if (!test_bit(lbus, mp_bus_not_pci) &&
999 !mp_irqs[i].irqtype &&
1000 (bus == lbus) &&
1001 (slot == ((mp_irqs[i].srcbusirq >> 2) & 0x1f))) {
1002 int irq = pin_2_irq(i, apic, mp_irqs[i].dstirq);
1003
1004 if (!(apic || IO_APIC_IRQ(irq)))
1005 continue;
1006
1007 if (pin == (mp_irqs[i].srcbusirq & 3)) {
1008 set_io_apic_irq_attr(irq_attr, apic,
1009 mp_irqs[i].dstirq,
1010 irq_trigger(i),
1011 irq_polarity(i));
1012 return irq;
1013 }
1014 /*
1015 * Use the first all-but-pin matching entry as a
1016 * best-guess fuzzy result for broken mptables.
1017 */
1018 if (best_guess < 0) {
1019 set_io_apic_irq_attr(irq_attr, apic,
1020 mp_irqs[i].dstirq,
1021 irq_trigger(i),
1022 irq_polarity(i));
1023 best_guess = irq;
1024 }
1025 }
1026 }
1027 return best_guess;
1028}
1029EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector);
1030
1031void lock_vector_lock(void)
1032{
1033 /* Used to the online set of cpus does not change
1034 * during assign_irq_vector.
1035 */
1036 raw_spin_lock(&vector_lock);
1037}
1038
1039void unlock_vector_lock(void)
1040{
1041 raw_spin_unlock(&vector_lock);
1042}
1043
1044static int
1045__assign_irq_vector(int irq, struct irq_cfg *cfg, const struct cpumask *mask)
1046{
1047 /*
1048 * NOTE! The local APIC isn't very good at handling
1049 * multiple interrupts at the same interrupt level.
1050 * As the interrupt level is determined by taking the
1051 * vector number and shifting that right by 4, we
1052 * want to spread these out a bit so that they don't
1053 * all fall in the same interrupt level.
1054 *
1055 * Also, we've got to be careful not to trash gate
1056 * 0x80, because int 0x80 is hm, kind of importantish. ;)
1057 */
1058 static int current_vector = FIRST_EXTERNAL_VECTOR + VECTOR_OFFSET_START;
1059 static int current_offset = VECTOR_OFFSET_START % 8;
1060 unsigned int old_vector;
1061 int cpu, err;
1062 cpumask_var_t tmp_mask;
1063
1064 if (cfg->move_in_progress)
1065 return -EBUSY;
1066
1067 if (!alloc_cpumask_var(&tmp_mask, GFP_ATOMIC))
1068 return -ENOMEM;
1069
1070 old_vector = cfg->vector;
1071 if (old_vector) {
1072 cpumask_and(tmp_mask, mask, cpu_online_mask);
1073 cpumask_and(tmp_mask, cfg->domain, tmp_mask);
1074 if (!cpumask_empty(tmp_mask)) {
1075 free_cpumask_var(tmp_mask);
1076 return 0;
1077 }
1078 }
1079
1080 /* Only try and allocate irqs on cpus that are present */
1081 err = -ENOSPC;
1082 for_each_cpu_and(cpu, mask, cpu_online_mask) {
1083 int new_cpu;
1084 int vector, offset;
1085
1086 apic->vector_allocation_domain(cpu, tmp_mask);
1087
1088 vector = current_vector;
1089 offset = current_offset;
1090next:
1091 vector += 8;
1092 if (vector >= first_system_vector) {
1093 /* If out of vectors on large boxen, must share them. */
1094 offset = (offset + 1) % 8;
1095 vector = FIRST_EXTERNAL_VECTOR + offset;
1096 }
1097 if (unlikely(current_vector == vector))
1098 continue;
1099
1100 if (test_bit(vector, used_vectors))
1101 goto next;
1102
1103 for_each_cpu_and(new_cpu, tmp_mask, cpu_online_mask)
1104 if (per_cpu(vector_irq, new_cpu)[vector] != -1)
1105 goto next;
1106 /* Found one! */
1107 current_vector = vector;
1108 current_offset = offset;
1109 if (old_vector) {
1110 cfg->move_in_progress = 1;
1111 cpumask_copy(cfg->old_domain, cfg->domain);
1112 }
1113 for_each_cpu_and(new_cpu, tmp_mask, cpu_online_mask)
1114 per_cpu(vector_irq, new_cpu)[vector] = irq;
1115 cfg->vector = vector;
1116 cpumask_copy(cfg->domain, tmp_mask);
1117 err = 0;
1118 break;
1119 }
1120 free_cpumask_var(tmp_mask);
1121 return err;
1122}
1123
1124int assign_irq_vector(int irq, struct irq_cfg *cfg, const struct cpumask *mask)
1125{
1126 int err;
1127 unsigned long flags;
1128
1129 raw_spin_lock_irqsave(&vector_lock, flags);
1130 err = __assign_irq_vector(irq, cfg, mask);
1131 raw_spin_unlock_irqrestore(&vector_lock, flags);
1132 return err;
1133}
1134
1135static void __clear_irq_vector(int irq, struct irq_cfg *cfg)
1136{
1137 int cpu, vector;
1138
1139 BUG_ON(!cfg->vector);
1140
1141 vector = cfg->vector;
1142 for_each_cpu_and(cpu, cfg->domain, cpu_online_mask)
1143 per_cpu(vector_irq, cpu)[vector] = -1;
1144
1145 cfg->vector = 0;
1146 cpumask_clear(cfg->domain);
1147
1148 if (likely(!cfg->move_in_progress))
1149 return;
1150 for_each_cpu_and(cpu, cfg->old_domain, cpu_online_mask) {
1151 for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS;
1152 vector++) {
1153 if (per_cpu(vector_irq, cpu)[vector] != irq)
1154 continue;
1155 per_cpu(vector_irq, cpu)[vector] = -1;
1156 break;
1157 }
1158 }
1159 cfg->move_in_progress = 0;
1160}
1161
1162void __setup_vector_irq(int cpu)
1163{
1164 /* Initialize vector_irq on a new cpu */
1165 int irq, vector;
1166 struct irq_cfg *cfg;
1167
1168 /*
1169 * vector_lock will make sure that we don't run into irq vector
1170 * assignments that might be happening on another cpu in parallel,
1171 * while we setup our initial vector to irq mappings.
1172 */
1173 raw_spin_lock(&vector_lock);
1174 /* Mark the inuse vectors */
1175 for_each_active_irq(irq) {
1176 cfg = irq_get_chip_data(irq);
1177 if (!cfg)
1178 continue;
1179 /*
1180 * If it is a legacy IRQ handled by the legacy PIC, this cpu
1181 * will be part of the irq_cfg's domain.
1182 */
1183 if (irq < legacy_pic->nr_legacy_irqs && !IO_APIC_IRQ(irq))
1184 cpumask_set_cpu(cpu, cfg->domain);
1185
1186 if (!cpumask_test_cpu(cpu, cfg->domain))
1187 continue;
1188 vector = cfg->vector;
1189 per_cpu(vector_irq, cpu)[vector] = irq;
1190 }
1191 /* Mark the free vectors */
1192 for (vector = 0; vector < NR_VECTORS; ++vector) {
1193 irq = per_cpu(vector_irq, cpu)[vector];
1194 if (irq < 0)
1195 continue;
1196
1197 cfg = irq_cfg(irq);
1198 if (!cpumask_test_cpu(cpu, cfg->domain))
1199 per_cpu(vector_irq, cpu)[vector] = -1;
1200 }
1201 raw_spin_unlock(&vector_lock);
1202}
1203
1204static struct irq_chip ioapic_chip;
1205static struct irq_chip ir_ioapic_chip;
1206
1207#ifdef CONFIG_X86_32
1208static inline int IO_APIC_irq_trigger(int irq)
1209{
1210 int apic, idx, pin;
1211
1212 for (apic = 0; apic < nr_ioapics; apic++) {
1213 for (pin = 0; pin < ioapics[apic].nr_registers; pin++) {
1214 idx = find_irq_entry(apic, pin, mp_INT);
1215 if ((idx != -1) && (irq == pin_2_irq(idx, apic, pin)))
1216 return irq_trigger(idx);
1217 }
1218 }
1219 /*
1220 * nonexistent IRQs are edge default
1221 */
1222 return 0;
1223}
1224#else
1225static inline int IO_APIC_irq_trigger(int irq)
1226{
1227 return 1;
1228}
1229#endif
1230
1231static void ioapic_register_intr(unsigned int irq, struct irq_cfg *cfg,
1232 unsigned long trigger)
1233{
1234 struct irq_chip *chip = &ioapic_chip;
1235 irq_flow_handler_t hdl;
1236 bool fasteoi;
1237
1238 if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
1239 trigger == IOAPIC_LEVEL) {
1240 irq_set_status_flags(irq, IRQ_LEVEL);
1241 fasteoi = true;
1242 } else {
1243 irq_clear_status_flags(irq, IRQ_LEVEL);
1244 fasteoi = false;
1245 }
1246
1247 if (irq_remapped(cfg)) {
1248 irq_set_status_flags(irq, IRQ_MOVE_PCNTXT);
1249 chip = &ir_ioapic_chip;
1250 fasteoi = trigger != 0;
1251 }
1252
1253 hdl = fasteoi ? handle_fasteoi_irq : handle_edge_irq;
1254 irq_set_chip_and_handler_name(irq, chip, hdl,
1255 fasteoi ? "fasteoi" : "edge");
1256}
1257
1258static int setup_ioapic_entry(int apic_id, int irq,
1259 struct IO_APIC_route_entry *entry,
1260 unsigned int destination, int trigger,
1261 int polarity, int vector, int pin)
1262{
1263 /*
1264 * add it to the IO-APIC irq-routing table:
1265 */
1266 memset(entry,0,sizeof(*entry));
1267
1268 if (intr_remapping_enabled) {
1269 struct intel_iommu *iommu = map_ioapic_to_ir(apic_id);
1270 struct irte irte;
1271 struct IR_IO_APIC_route_entry *ir_entry =
1272 (struct IR_IO_APIC_route_entry *) entry;
1273 int index;
1274
1275 if (!iommu)
1276 panic("No mapping iommu for ioapic %d\n", apic_id);
1277
1278 index = alloc_irte(iommu, irq, 1);
1279 if (index < 0)
1280 panic("Failed to allocate IRTE for ioapic %d\n", apic_id);
1281
1282 prepare_irte(&irte, vector, destination);
1283
1284 /* Set source-id of interrupt request */
1285 set_ioapic_sid(&irte, apic_id);
1286
1287 modify_irte(irq, &irte);
1288
1289 ir_entry->index2 = (index >> 15) & 0x1;
1290 ir_entry->zero = 0;
1291 ir_entry->format = 1;
1292 ir_entry->index = (index & 0x7fff);
1293 /*
1294 * IO-APIC RTE will be configured with virtual vector.
1295 * irq handler will do the explicit EOI to the io-apic.
1296 */
1297 ir_entry->vector = pin;
1298
1299 apic_printk(APIC_VERBOSE, KERN_DEBUG "IOAPIC[%d]: "
1300 "Set IRTE entry (P:%d FPD:%d Dst_Mode:%d "
1301 "Redir_hint:%d Trig_Mode:%d Dlvry_Mode:%X "
1302 "Avail:%X Vector:%02X Dest:%08X "
1303 "SID:%04X SQ:%X SVT:%X)\n",
1304 apic_id, irte.present, irte.fpd, irte.dst_mode,
1305 irte.redir_hint, irte.trigger_mode, irte.dlvry_mode,
1306 irte.avail, irte.vector, irte.dest_id,
1307 irte.sid, irte.sq, irte.svt);
1308 } else {
1309 entry->delivery_mode = apic->irq_delivery_mode;
1310 entry->dest_mode = apic->irq_dest_mode;
1311 entry->dest = destination;
1312 entry->vector = vector;
1313 }
1314
1315 entry->mask = 0; /* enable IRQ */
1316 entry->trigger = trigger;
1317 entry->polarity = polarity;
1318
1319 /* Mask level triggered irqs.
1320 * Use IRQ_DELAYED_DISABLE for edge triggered irqs.
1321 */
1322 if (trigger)
1323 entry->mask = 1;
1324 return 0;
1325}
1326
1327static void setup_ioapic_irq(int apic_id, int pin, unsigned int irq,
1328 struct irq_cfg *cfg, int trigger, int polarity)
1329{
1330 struct IO_APIC_route_entry entry;
1331 unsigned int dest;
1332
1333 if (!IO_APIC_IRQ(irq))
1334 return;
1335 /*
1336 * For legacy irqs, cfg->domain starts with cpu 0 for legacy
1337 * controllers like 8259. Now that IO-APIC can handle this irq, update
1338 * the cfg->domain.
1339 */
1340 if (irq < legacy_pic->nr_legacy_irqs && cpumask_test_cpu(0, cfg->domain))
1341 apic->vector_allocation_domain(0, cfg->domain);
1342
1343 if (assign_irq_vector(irq, cfg, apic->target_cpus()))
1344 return;
1345
1346 dest = apic->cpu_mask_to_apicid_and(cfg->domain, apic->target_cpus());
1347
1348 apic_printk(APIC_VERBOSE,KERN_DEBUG
1349 "IOAPIC[%d]: Set routing entry (%d-%d -> 0x%x -> "
1350 "IRQ %d Mode:%i Active:%i Dest:%d)\n",
1351 apic_id, mpc_ioapic_id(apic_id), pin, cfg->vector,
1352 irq, trigger, polarity, dest);
1353
1354
1355 if (setup_ioapic_entry(mpc_ioapic_id(apic_id), irq, &entry,
1356 dest, trigger, polarity, cfg->vector, pin)) {
1357 printk("Failed to setup ioapic entry for ioapic %d, pin %d\n",
1358 mpc_ioapic_id(apic_id), pin);
1359 __clear_irq_vector(irq, cfg);
1360 return;
1361 }
1362
1363 ioapic_register_intr(irq, cfg, trigger);
1364 if (irq < legacy_pic->nr_legacy_irqs)
1365 legacy_pic->mask(irq);
1366
1367 ioapic_write_entry(apic_id, pin, entry);
1368}
1369
1370static bool __init io_apic_pin_not_connected(int idx, int apic_id, int pin)
1371{
1372 if (idx != -1)
1373 return false;
1374
1375 apic_printk(APIC_VERBOSE, KERN_DEBUG " apic %d pin %d not connected\n",
1376 mpc_ioapic_id(apic_id), pin);
1377 return true;
1378}
1379
1380static void __init __io_apic_setup_irqs(unsigned int apic_id)
1381{
1382 int idx, node = cpu_to_node(0);
1383 struct io_apic_irq_attr attr;
1384 unsigned int pin, irq;
1385
1386 for (pin = 0; pin < ioapics[apic_id].nr_registers; pin++) {
1387 idx = find_irq_entry(apic_id, pin, mp_INT);
1388 if (io_apic_pin_not_connected(idx, apic_id, pin))
1389 continue;
1390
1391 irq = pin_2_irq(idx, apic_id, pin);
1392
1393 if ((apic_id > 0) && (irq > 16))
1394 continue;
1395
1396 /*
1397 * Skip the timer IRQ if there's a quirk handler
1398 * installed and if it returns 1:
1399 */
1400 if (apic->multi_timer_check &&
1401 apic->multi_timer_check(apic_id, irq))
1402 continue;
1403
1404 set_io_apic_irq_attr(&attr, apic_id, pin, irq_trigger(idx),
1405 irq_polarity(idx));
1406
1407 io_apic_setup_irq_pin(irq, node, &attr);
1408 }
1409}
1410
1411static void __init setup_IO_APIC_irqs(void)
1412{
1413 unsigned int apic_id;
1414
1415 apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n");
1416
1417 for (apic_id = 0; apic_id < nr_ioapics; apic_id++)
1418 __io_apic_setup_irqs(apic_id);
1419}
1420
1421/*
1422 * for the gsit that is not in first ioapic
1423 * but could not use acpi_register_gsi()
1424 * like some special sci in IBM x3330
1425 */
1426void setup_IO_APIC_irq_extra(u32 gsi)
1427{
1428 int apic_id = 0, pin, idx, irq, node = cpu_to_node(0);
1429 struct io_apic_irq_attr attr;
1430
1431 /*
1432 * Convert 'gsi' to 'ioapic.pin'.
1433 */
1434 apic_id = mp_find_ioapic(gsi);
1435 if (apic_id < 0)
1436 return;
1437
1438 pin = mp_find_ioapic_pin(apic_id, gsi);
1439 idx = find_irq_entry(apic_id, pin, mp_INT);
1440 if (idx == -1)
1441 return;
1442
1443 irq = pin_2_irq(idx, apic_id, pin);
1444
1445 /* Only handle the non legacy irqs on secondary ioapics */
1446 if (apic_id == 0 || irq < NR_IRQS_LEGACY)
1447 return;
1448
1449 set_io_apic_irq_attr(&attr, apic_id, pin, irq_trigger(idx),
1450 irq_polarity(idx));
1451
1452 io_apic_setup_irq_pin_once(irq, node, &attr);
1453}
1454
1455/*
1456 * Set up the timer pin, possibly with the 8259A-master behind.
1457 */
1458static void __init setup_timer_IRQ0_pin(unsigned int apic_id, unsigned int pin,
1459 int vector)
1460{
1461 struct IO_APIC_route_entry entry;
1462
1463 if (intr_remapping_enabled)
1464 return;
1465
1466 memset(&entry, 0, sizeof(entry));
1467
1468 /*
1469 * We use logical delivery to get the timer IRQ
1470 * to the first CPU.
1471 */
1472 entry.dest_mode = apic->irq_dest_mode;
1473 entry.mask = 0; /* don't mask IRQ for edge */
1474 entry.dest = apic->cpu_mask_to_apicid(apic->target_cpus());
1475 entry.delivery_mode = apic->irq_delivery_mode;
1476 entry.polarity = 0;
1477 entry.trigger = 0;
1478 entry.vector = vector;
1479
1480 /*
1481 * The timer IRQ doesn't have to know that behind the
1482 * scene we may have a 8259A-master in AEOI mode ...
1483 */
1484 irq_set_chip_and_handler_name(0, &ioapic_chip, handle_edge_irq,
1485 "edge");
1486
1487 /*
1488 * Add it to the IO-APIC irq-routing table:
1489 */
1490 ioapic_write_entry(apic_id, pin, entry);
1491}
1492
1493
1494__apicdebuginit(void) print_IO_APIC(void)
1495{
1496 int apic, i;
1497 union IO_APIC_reg_00 reg_00;
1498 union IO_APIC_reg_01 reg_01;
1499 union IO_APIC_reg_02 reg_02;
1500 union IO_APIC_reg_03 reg_03;
1501 unsigned long flags;
1502 struct irq_cfg *cfg;
1503 unsigned int irq;
1504
1505 printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
1506 for (i = 0; i < nr_ioapics; i++)
1507 printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
1508 mpc_ioapic_id(i), ioapics[i].nr_registers);
1509
1510 /*
1511 * We are a bit conservative about what we expect. We have to
1512 * know about every hardware change ASAP.
1513 */
1514 printk(KERN_INFO "testing the IO APIC.......................\n");
1515
1516 for (apic = 0; apic < nr_ioapics; apic++) {
1517
1518 raw_spin_lock_irqsave(&ioapic_lock, flags);
1519 reg_00.raw = io_apic_read(apic, 0);
1520 reg_01.raw = io_apic_read(apic, 1);
1521 if (reg_01.bits.version >= 0x10)
1522 reg_02.raw = io_apic_read(apic, 2);
1523 if (reg_01.bits.version >= 0x20)
1524 reg_03.raw = io_apic_read(apic, 3);
1525 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
1526
1527 printk("\n");
1528 printk(KERN_DEBUG "IO APIC #%d......\n", mpc_ioapic_id(apic));
1529 printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw);
1530 printk(KERN_DEBUG "....... : physical APIC id: %02X\n", reg_00.bits.ID);
1531 printk(KERN_DEBUG "....... : Delivery Type: %X\n", reg_00.bits.delivery_type);
1532 printk(KERN_DEBUG "....... : LTS : %X\n", reg_00.bits.LTS);
1533
1534 printk(KERN_DEBUG ".... register #01: %08X\n", *(int *)®_01);
1535 printk(KERN_DEBUG "....... : max redirection entries: %02X\n",
1536 reg_01.bits.entries);
1537
1538 printk(KERN_DEBUG "....... : PRQ implemented: %X\n", reg_01.bits.PRQ);
1539 printk(KERN_DEBUG "....... : IO APIC version: %02X\n",
1540 reg_01.bits.version);
1541
1542 /*
1543 * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02,
1544 * but the value of reg_02 is read as the previous read register
1545 * value, so ignore it if reg_02 == reg_01.
1546 */
1547 if (reg_01.bits.version >= 0x10 && reg_02.raw != reg_01.raw) {
1548 printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw);
1549 printk(KERN_DEBUG "....... : arbitration: %02X\n", reg_02.bits.arbitration);
1550 }
1551
1552 /*
1553 * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02
1554 * or reg_03, but the value of reg_0[23] is read as the previous read
1555 * register value, so ignore it if reg_03 == reg_0[12].
1556 */
1557 if (reg_01.bits.version >= 0x20 && reg_03.raw != reg_02.raw &&
1558 reg_03.raw != reg_01.raw) {
1559 printk(KERN_DEBUG ".... register #03: %08X\n", reg_03.raw);
1560 printk(KERN_DEBUG "....... : Boot DT : %X\n", reg_03.bits.boot_DT);
1561 }
1562
1563 printk(KERN_DEBUG ".... IRQ redirection table:\n");
1564
1565 if (intr_remapping_enabled) {
1566 printk(KERN_DEBUG " NR Indx Fmt Mask Trig IRR"
1567 " Pol Stat Indx2 Zero Vect:\n");
1568 } else {
1569 printk(KERN_DEBUG " NR Dst Mask Trig IRR Pol"
1570 " Stat Dmod Deli Vect:\n");
1571 }
1572
1573 for (i = 0; i <= reg_01.bits.entries; i++) {
1574 if (intr_remapping_enabled) {
1575 struct IO_APIC_route_entry entry;
1576 struct IR_IO_APIC_route_entry *ir_entry;
1577
1578 entry = ioapic_read_entry(apic, i);
1579 ir_entry = (struct IR_IO_APIC_route_entry *) &entry;
1580 printk(KERN_DEBUG " %02x %04X ",
1581 i,
1582 ir_entry->index
1583 );
1584 printk("%1d %1d %1d %1d %1d "
1585 "%1d %1d %X %02X\n",
1586 ir_entry->format,
1587 ir_entry->mask,
1588 ir_entry->trigger,
1589 ir_entry->irr,
1590 ir_entry->polarity,
1591 ir_entry->delivery_status,
1592 ir_entry->index2,
1593 ir_entry->zero,
1594 ir_entry->vector
1595 );
1596 } else {
1597 struct IO_APIC_route_entry entry;
1598
1599 entry = ioapic_read_entry(apic, i);
1600 printk(KERN_DEBUG " %02x %02X ",
1601 i,
1602 entry.dest
1603 );
1604 printk("%1d %1d %1d %1d %1d "
1605 "%1d %1d %02X\n",
1606 entry.mask,
1607 entry.trigger,
1608 entry.irr,
1609 entry.polarity,
1610 entry.delivery_status,
1611 entry.dest_mode,
1612 entry.delivery_mode,
1613 entry.vector
1614 );
1615 }
1616 }
1617 }
1618
1619 printk(KERN_DEBUG "IRQ to pin mappings:\n");
1620 for_each_active_irq(irq) {
1621 struct irq_pin_list *entry;
1622
1623 cfg = irq_get_chip_data(irq);
1624 if (!cfg)
1625 continue;
1626 entry = cfg->irq_2_pin;
1627 if (!entry)
1628 continue;
1629 printk(KERN_DEBUG "IRQ%d ", irq);
1630 for_each_irq_pin(entry, cfg->irq_2_pin)
1631 printk("-> %d:%d", entry->apic, entry->pin);
1632 printk("\n");
1633 }
1634
1635 printk(KERN_INFO ".................................... done.\n");
1636
1637 return;
1638}
1639
1640__apicdebuginit(void) print_APIC_field(int base)
1641{
1642 int i;
1643
1644 printk(KERN_DEBUG);
1645
1646 for (i = 0; i < 8; i++)
1647 printk(KERN_CONT "%08x", apic_read(base + i*0x10));
1648
1649 printk(KERN_CONT "\n");
1650}
1651
1652__apicdebuginit(void) print_local_APIC(void *dummy)
1653{
1654 unsigned int i, v, ver, maxlvt;
1655 u64 icr;
1656
1657 printk(KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n",
1658 smp_processor_id(), hard_smp_processor_id());
1659 v = apic_read(APIC_ID);
1660 printk(KERN_INFO "... APIC ID: %08x (%01x)\n", v, read_apic_id());
1661 v = apic_read(APIC_LVR);
1662 printk(KERN_INFO "... APIC VERSION: %08x\n", v);
1663 ver = GET_APIC_VERSION(v);
1664 maxlvt = lapic_get_maxlvt();
1665
1666 v = apic_read(APIC_TASKPRI);
1667 printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK);
1668
1669 if (APIC_INTEGRATED(ver)) { /* !82489DX */
1670 if (!APIC_XAPIC(ver)) {
1671 v = apic_read(APIC_ARBPRI);
1672 printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v,
1673 v & APIC_ARBPRI_MASK);
1674 }
1675 v = apic_read(APIC_PROCPRI);
1676 printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v);
1677 }
1678
1679 /*
1680 * Remote read supported only in the 82489DX and local APIC for
1681 * Pentium processors.
1682 */
1683 if (!APIC_INTEGRATED(ver) || maxlvt == 3) {
1684 v = apic_read(APIC_RRR);
1685 printk(KERN_DEBUG "... APIC RRR: %08x\n", v);
1686 }
1687
1688 v = apic_read(APIC_LDR);
1689 printk(KERN_DEBUG "... APIC LDR: %08x\n", v);
1690 if (!x2apic_enabled()) {
1691 v = apic_read(APIC_DFR);
1692 printk(KERN_DEBUG "... APIC DFR: %08x\n", v);
1693 }
1694 v = apic_read(APIC_SPIV);
1695 printk(KERN_DEBUG "... APIC SPIV: %08x\n", v);
1696
1697 printk(KERN_DEBUG "... APIC ISR field:\n");
1698 print_APIC_field(APIC_ISR);
1699 printk(KERN_DEBUG "... APIC TMR field:\n");
1700 print_APIC_field(APIC_TMR);
1701 printk(KERN_DEBUG "... APIC IRR field:\n");
1702 print_APIC_field(APIC_IRR);
1703
1704 if (APIC_INTEGRATED(ver)) { /* !82489DX */
1705 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
1706 apic_write(APIC_ESR, 0);
1707
1708 v = apic_read(APIC_ESR);
1709 printk(KERN_DEBUG "... APIC ESR: %08x\n", v);
1710 }
1711
1712 icr = apic_icr_read();
1713 printk(KERN_DEBUG "... APIC ICR: %08x\n", (u32)icr);
1714 printk(KERN_DEBUG "... APIC ICR2: %08x\n", (u32)(icr >> 32));
1715
1716 v = apic_read(APIC_LVTT);
1717 printk(KERN_DEBUG "... APIC LVTT: %08x\n", v);
1718
1719 if (maxlvt > 3) { /* PC is LVT#4. */
1720 v = apic_read(APIC_LVTPC);
1721 printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v);
1722 }
1723 v = apic_read(APIC_LVT0);
1724 printk(KERN_DEBUG "... APIC LVT0: %08x\n", v);
1725 v = apic_read(APIC_LVT1);
1726 printk(KERN_DEBUG "... APIC LVT1: %08x\n", v);
1727
1728 if (maxlvt > 2) { /* ERR is LVT#3. */
1729 v = apic_read(APIC_LVTERR);
1730 printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v);
1731 }
1732
1733 v = apic_read(APIC_TMICT);
1734 printk(KERN_DEBUG "... APIC TMICT: %08x\n", v);
1735 v = apic_read(APIC_TMCCT);
1736 printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v);
1737 v = apic_read(APIC_TDCR);
1738 printk(KERN_DEBUG "... APIC TDCR: %08x\n", v);
1739
1740 if (boot_cpu_has(X86_FEATURE_EXTAPIC)) {
1741 v = apic_read(APIC_EFEAT);
1742 maxlvt = (v >> 16) & 0xff;
1743 printk(KERN_DEBUG "... APIC EFEAT: %08x\n", v);
1744 v = apic_read(APIC_ECTRL);
1745 printk(KERN_DEBUG "... APIC ECTRL: %08x\n", v);
1746 for (i = 0; i < maxlvt; i++) {
1747 v = apic_read(APIC_EILVTn(i));
1748 printk(KERN_DEBUG "... APIC EILVT%d: %08x\n", i, v);
1749 }
1750 }
1751 printk("\n");
1752}
1753
1754__apicdebuginit(void) print_local_APICs(int maxcpu)
1755{
1756 int cpu;
1757
1758 if (!maxcpu)
1759 return;
1760
1761 preempt_disable();
1762 for_each_online_cpu(cpu) {
1763 if (cpu >= maxcpu)
1764 break;
1765 smp_call_function_single(cpu, print_local_APIC, NULL, 1);
1766 }
1767 preempt_enable();
1768}
1769
1770__apicdebuginit(void) print_PIC(void)
1771{
1772 unsigned int v;
1773 unsigned long flags;
1774
1775 if (!legacy_pic->nr_legacy_irqs)
1776 return;
1777
1778 printk(KERN_DEBUG "\nprinting PIC contents\n");
1779
1780 raw_spin_lock_irqsave(&i8259A_lock, flags);
1781
1782 v = inb(0xa1) << 8 | inb(0x21);
1783 printk(KERN_DEBUG "... PIC IMR: %04x\n", v);
1784
1785 v = inb(0xa0) << 8 | inb(0x20);
1786 printk(KERN_DEBUG "... PIC IRR: %04x\n", v);
1787
1788 outb(0x0b,0xa0);
1789 outb(0x0b,0x20);
1790 v = inb(0xa0) << 8 | inb(0x20);
1791 outb(0x0a,0xa0);
1792 outb(0x0a,0x20);
1793
1794 raw_spin_unlock_irqrestore(&i8259A_lock, flags);
1795
1796 printk(KERN_DEBUG "... PIC ISR: %04x\n", v);
1797
1798 v = inb(0x4d1) << 8 | inb(0x4d0);
1799 printk(KERN_DEBUG "... PIC ELCR: %04x\n", v);
1800}
1801
1802static int __initdata show_lapic = 1;
1803static __init int setup_show_lapic(char *arg)
1804{
1805 int num = -1;
1806
1807 if (strcmp(arg, "all") == 0) {
1808 show_lapic = CONFIG_NR_CPUS;
1809 } else {
1810 get_option(&arg, &num);
1811 if (num >= 0)
1812 show_lapic = num;
1813 }
1814
1815 return 1;
1816}
1817__setup("show_lapic=", setup_show_lapic);
1818
1819__apicdebuginit(int) print_ICs(void)
1820{
1821 if (apic_verbosity == APIC_QUIET)
1822 return 0;
1823
1824 print_PIC();
1825
1826 /* don't print out if apic is not there */
1827 if (!cpu_has_apic && !apic_from_smp_config())
1828 return 0;
1829
1830 print_local_APICs(show_lapic);
1831 print_IO_APIC();
1832
1833 return 0;
1834}
1835
1836late_initcall(print_ICs);
1837
1838
1839/* Where if anywhere is the i8259 connect in external int mode */
1840static struct { int pin, apic; } ioapic_i8259 = { -1, -1 };
1841
1842void __init enable_IO_APIC(void)
1843{
1844 int i8259_apic, i8259_pin;
1845 int apic;
1846
1847 if (!legacy_pic->nr_legacy_irqs)
1848 return;
1849
1850 for(apic = 0; apic < nr_ioapics; apic++) {
1851 int pin;
1852 /* See if any of the pins is in ExtINT mode */
1853 for (pin = 0; pin < ioapics[apic].nr_registers; pin++) {
1854 struct IO_APIC_route_entry entry;
1855 entry = ioapic_read_entry(apic, pin);
1856
1857 /* If the interrupt line is enabled and in ExtInt mode
1858 * I have found the pin where the i8259 is connected.
1859 */
1860 if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) {
1861 ioapic_i8259.apic = apic;
1862 ioapic_i8259.pin = pin;
1863 goto found_i8259;
1864 }
1865 }
1866 }
1867 found_i8259:
1868 /* Look to see what if the MP table has reported the ExtINT */
1869 /* If we could not find the appropriate pin by looking at the ioapic
1870 * the i8259 probably is not connected the ioapic but give the
1871 * mptable a chance anyway.
1872 */
1873 i8259_pin = find_isa_irq_pin(0, mp_ExtINT);
1874 i8259_apic = find_isa_irq_apic(0, mp_ExtINT);
1875 /* Trust the MP table if nothing is setup in the hardware */
1876 if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) {
1877 printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n");
1878 ioapic_i8259.pin = i8259_pin;
1879 ioapic_i8259.apic = i8259_apic;
1880 }
1881 /* Complain if the MP table and the hardware disagree */
1882 if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) &&
1883 (i8259_pin >= 0) && (ioapic_i8259.pin >= 0))
1884 {
1885 printk(KERN_WARNING "ExtINT in hardware and MP table differ\n");
1886 }
1887
1888 /*
1889 * Do not trust the IO-APIC being empty at bootup
1890 */
1891 clear_IO_APIC();
1892}
1893
1894/*
1895 * Not an __init, needed by the reboot code
1896 */
1897void disable_IO_APIC(void)
1898{
1899 /*
1900 * Clear the IO-APIC before rebooting:
1901 */
1902 clear_IO_APIC();
1903
1904 if (!legacy_pic->nr_legacy_irqs)
1905 return;
1906
1907 /*
1908 * If the i8259 is routed through an IOAPIC
1909 * Put that IOAPIC in virtual wire mode
1910 * so legacy interrupts can be delivered.
1911 *
1912 * With interrupt-remapping, for now we will use virtual wire A mode,
1913 * as virtual wire B is little complex (need to configure both
1914 * IOAPIC RTE as well as interrupt-remapping table entry).
1915 * As this gets called during crash dump, keep this simple for now.
1916 */
1917 if (ioapic_i8259.pin != -1 && !intr_remapping_enabled) {
1918 struct IO_APIC_route_entry entry;
1919
1920 memset(&entry, 0, sizeof(entry));
1921 entry.mask = 0; /* Enabled */
1922 entry.trigger = 0; /* Edge */
1923 entry.irr = 0;
1924 entry.polarity = 0; /* High */
1925 entry.delivery_status = 0;
1926 entry.dest_mode = 0; /* Physical */
1927 entry.delivery_mode = dest_ExtINT; /* ExtInt */
1928 entry.vector = 0;
1929 entry.dest = read_apic_id();
1930
1931 /*
1932 * Add it to the IO-APIC irq-routing table:
1933 */
1934 ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry);
1935 }
1936
1937 /*
1938 * Use virtual wire A mode when interrupt remapping is enabled.
1939 */
1940 if (cpu_has_apic || apic_from_smp_config())
1941 disconnect_bsp_APIC(!intr_remapping_enabled &&
1942 ioapic_i8259.pin != -1);
1943}
1944
1945#ifdef CONFIG_X86_32
1946/*
1947 * function to set the IO-APIC physical IDs based on the
1948 * values stored in the MPC table.
1949 *
1950 * by Matt Domsch <Matt_Domsch@dell.com> Tue Dec 21 12:25:05 CST 1999
1951 */
1952void __init setup_ioapic_ids_from_mpc_nocheck(void)
1953{
1954 union IO_APIC_reg_00 reg_00;
1955 physid_mask_t phys_id_present_map;
1956 int apic_id;
1957 int i;
1958 unsigned char old_id;
1959 unsigned long flags;
1960
1961 /*
1962 * This is broken; anything with a real cpu count has to
1963 * circumvent this idiocy regardless.
1964 */
1965 apic->ioapic_phys_id_map(&phys_cpu_present_map, &phys_id_present_map);
1966
1967 /*
1968 * Set the IOAPIC ID to the value stored in the MPC table.
1969 */
1970 for (apic_id = 0; apic_id < nr_ioapics; apic_id++) {
1971
1972 /* Read the register 0 value */
1973 raw_spin_lock_irqsave(&ioapic_lock, flags);
1974 reg_00.raw = io_apic_read(apic_id, 0);
1975 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
1976
1977 old_id = mpc_ioapic_id(apic_id);
1978
1979 if (mpc_ioapic_id(apic_id) >= get_physical_broadcast()) {
1980 printk(KERN_ERR "BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n",
1981 apic_id, mpc_ioapic_id(apic_id));
1982 printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
1983 reg_00.bits.ID);
1984 ioapics[apic_id].mp_config.apicid = reg_00.bits.ID;
1985 }
1986
1987 /*
1988 * Sanity check, is the ID really free? Every APIC in a
1989 * system must have a unique ID or we get lots of nice
1990 * 'stuck on smp_invalidate_needed IPI wait' messages.
1991 */
1992 if (apic->check_apicid_used(&phys_id_present_map,
1993 mpc_ioapic_id(apic_id))) {
1994 printk(KERN_ERR "BIOS bug, IO-APIC#%d ID %d is already used!...\n",
1995 apic_id, mpc_ioapic_id(apic_id));
1996 for (i = 0; i < get_physical_broadcast(); i++)
1997 if (!physid_isset(i, phys_id_present_map))
1998 break;
1999 if (i >= get_physical_broadcast())
2000 panic("Max APIC ID exceeded!\n");
2001 printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
2002 i);
2003 physid_set(i, phys_id_present_map);
2004 ioapics[apic_id].mp_config.apicid = i;
2005 } else {
2006 physid_mask_t tmp;
2007 apic->apicid_to_cpu_present(mpc_ioapic_id(apic_id),
2008 &tmp);
2009 apic_printk(APIC_VERBOSE, "Setting %d in the "
2010 "phys_id_present_map\n",
2011 mpc_ioapic_id(apic_id));
2012 physids_or(phys_id_present_map, phys_id_present_map, tmp);
2013 }
2014
2015 /*
2016 * We need to adjust the IRQ routing table
2017 * if the ID changed.
2018 */
2019 if (old_id != mpc_ioapic_id(apic_id))
2020 for (i = 0; i < mp_irq_entries; i++)
2021 if (mp_irqs[i].dstapic == old_id)
2022 mp_irqs[i].dstapic
2023 = mpc_ioapic_id(apic_id);
2024
2025 /*
2026 * Update the ID register according to the right value
2027 * from the MPC table if they are different.
2028 */
2029 if (mpc_ioapic_id(apic_id) == reg_00.bits.ID)
2030 continue;
2031
2032 apic_printk(APIC_VERBOSE, KERN_INFO
2033 "...changing IO-APIC physical APIC ID to %d ...",
2034 mpc_ioapic_id(apic_id));
2035
2036 reg_00.bits.ID = mpc_ioapic_id(apic_id);
2037 raw_spin_lock_irqsave(&ioapic_lock, flags);
2038 io_apic_write(apic_id, 0, reg_00.raw);
2039 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2040
2041 /*
2042 * Sanity check
2043 */
2044 raw_spin_lock_irqsave(&ioapic_lock, flags);
2045 reg_00.raw = io_apic_read(apic_id, 0);
2046 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2047 if (reg_00.bits.ID != mpc_ioapic_id(apic_id))
2048 printk("could not set ID!\n");
2049 else
2050 apic_printk(APIC_VERBOSE, " ok.\n");
2051 }
2052}
2053
2054void __init setup_ioapic_ids_from_mpc(void)
2055{
2056
2057 if (acpi_ioapic)
2058 return;
2059 /*
2060 * Don't check I/O APIC IDs for xAPIC systems. They have
2061 * no meaning without the serial APIC bus.
2062 */
2063 if (!(boot_cpu_data.x86_vendor == X86_VENDOR_INTEL)
2064 || APIC_XAPIC(apic_version[boot_cpu_physical_apicid]))
2065 return;
2066 setup_ioapic_ids_from_mpc_nocheck();
2067}
2068#endif
2069
2070int no_timer_check __initdata;
2071
2072static int __init notimercheck(char *s)
2073{
2074 no_timer_check = 1;
2075 return 1;
2076}
2077__setup("no_timer_check", notimercheck);
2078
2079/*
2080 * There is a nasty bug in some older SMP boards, their mptable lies
2081 * about the timer IRQ. We do the following to work around the situation:
2082 *
2083 * - timer IRQ defaults to IO-APIC IRQ
2084 * - if this function detects that timer IRQs are defunct, then we fall
2085 * back to ISA timer IRQs
2086 */
2087static int __init timer_irq_works(void)
2088{
2089 unsigned long t1 = jiffies;
2090 unsigned long flags;
2091
2092 if (no_timer_check)
2093 return 1;
2094
2095 local_save_flags(flags);
2096 local_irq_enable();
2097 /* Let ten ticks pass... */
2098 mdelay((10 * 1000) / HZ);
2099 local_irq_restore(flags);
2100
2101 /*
2102 * Expect a few ticks at least, to be sure some possible
2103 * glue logic does not lock up after one or two first
2104 * ticks in a non-ExtINT mode. Also the local APIC
2105 * might have cached one ExtINT interrupt. Finally, at
2106 * least one tick may be lost due to delays.
2107 */
2108
2109 /* jiffies wrap? */
2110 if (time_after(jiffies, t1 + 4))
2111 return 1;
2112 return 0;
2113}
2114
2115/*
2116 * In the SMP+IOAPIC case it might happen that there are an unspecified
2117 * number of pending IRQ events unhandled. These cases are very rare,
2118 * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
2119 * better to do it this way as thus we do not have to be aware of
2120 * 'pending' interrupts in the IRQ path, except at this point.
2121 */
2122/*
2123 * Edge triggered needs to resend any interrupt
2124 * that was delayed but this is now handled in the device
2125 * independent code.
2126 */
2127
2128/*
2129 * Starting up a edge-triggered IO-APIC interrupt is
2130 * nasty - we need to make sure that we get the edge.
2131 * If it is already asserted for some reason, we need
2132 * return 1 to indicate that is was pending.
2133 *
2134 * This is not complete - we should be able to fake
2135 * an edge even if it isn't on the 8259A...
2136 */
2137
2138static unsigned int startup_ioapic_irq(struct irq_data *data)
2139{
2140 int was_pending = 0, irq = data->irq;
2141 unsigned long flags;
2142
2143 raw_spin_lock_irqsave(&ioapic_lock, flags);
2144 if (irq < legacy_pic->nr_legacy_irqs) {
2145 legacy_pic->mask(irq);
2146 if (legacy_pic->irq_pending(irq))
2147 was_pending = 1;
2148 }
2149 __unmask_ioapic(data->chip_data);
2150 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2151
2152 return was_pending;
2153}
2154
2155static int ioapic_retrigger_irq(struct irq_data *data)
2156{
2157 struct irq_cfg *cfg = data->chip_data;
2158 unsigned long flags;
2159
2160 raw_spin_lock_irqsave(&vector_lock, flags);
2161 apic->send_IPI_mask(cpumask_of(cpumask_first(cfg->domain)), cfg->vector);
2162 raw_spin_unlock_irqrestore(&vector_lock, flags);
2163
2164 return 1;
2165}
2166
2167/*
2168 * Level and edge triggered IO-APIC interrupts need different handling,
2169 * so we use two separate IRQ descriptors. Edge triggered IRQs can be
2170 * handled with the level-triggered descriptor, but that one has slightly
2171 * more overhead. Level-triggered interrupts cannot be handled with the
2172 * edge-triggered handler, without risking IRQ storms and other ugly
2173 * races.
2174 */
2175
2176#ifdef CONFIG_SMP
2177void send_cleanup_vector(struct irq_cfg *cfg)
2178{
2179 cpumask_var_t cleanup_mask;
2180
2181 if (unlikely(!alloc_cpumask_var(&cleanup_mask, GFP_ATOMIC))) {
2182 unsigned int i;
2183 for_each_cpu_and(i, cfg->old_domain, cpu_online_mask)
2184 apic->send_IPI_mask(cpumask_of(i), IRQ_MOVE_CLEANUP_VECTOR);
2185 } else {
2186 cpumask_and(cleanup_mask, cfg->old_domain, cpu_online_mask);
2187 apic->send_IPI_mask(cleanup_mask, IRQ_MOVE_CLEANUP_VECTOR);
2188 free_cpumask_var(cleanup_mask);
2189 }
2190 cfg->move_in_progress = 0;
2191}
2192
2193static void __target_IO_APIC_irq(unsigned int irq, unsigned int dest, struct irq_cfg *cfg)
2194{
2195 int apic, pin;
2196 struct irq_pin_list *entry;
2197 u8 vector = cfg->vector;
2198
2199 for_each_irq_pin(entry, cfg->irq_2_pin) {
2200 unsigned int reg;
2201
2202 apic = entry->apic;
2203 pin = entry->pin;
2204 /*
2205 * With interrupt-remapping, destination information comes
2206 * from interrupt-remapping table entry.
2207 */
2208 if (!irq_remapped(cfg))
2209 io_apic_write(apic, 0x11 + pin*2, dest);
2210 reg = io_apic_read(apic, 0x10 + pin*2);
2211 reg &= ~IO_APIC_REDIR_VECTOR_MASK;
2212 reg |= vector;
2213 io_apic_modify(apic, 0x10 + pin*2, reg);
2214 }
2215}
2216
2217/*
2218 * Either sets data->affinity to a valid value, and returns
2219 * ->cpu_mask_to_apicid of that in dest_id, or returns -1 and
2220 * leaves data->affinity untouched.
2221 */
2222int __ioapic_set_affinity(struct irq_data *data, const struct cpumask *mask,
2223 unsigned int *dest_id)
2224{
2225 struct irq_cfg *cfg = data->chip_data;
2226
2227 if (!cpumask_intersects(mask, cpu_online_mask))
2228 return -1;
2229
2230 if (assign_irq_vector(data->irq, data->chip_data, mask))
2231 return -1;
2232
2233 cpumask_copy(data->affinity, mask);
2234
2235 *dest_id = apic->cpu_mask_to_apicid_and(mask, cfg->domain);
2236 return 0;
2237}
2238
2239static int
2240ioapic_set_affinity(struct irq_data *data, const struct cpumask *mask,
2241 bool force)
2242{
2243 unsigned int dest, irq = data->irq;
2244 unsigned long flags;
2245 int ret;
2246
2247 raw_spin_lock_irqsave(&ioapic_lock, flags);
2248 ret = __ioapic_set_affinity(data, mask, &dest);
2249 if (!ret) {
2250 /* Only the high 8 bits are valid. */
2251 dest = SET_APIC_LOGICAL_ID(dest);
2252 __target_IO_APIC_irq(irq, dest, data->chip_data);
2253 }
2254 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2255 return ret;
2256}
2257
2258#ifdef CONFIG_INTR_REMAP
2259
2260/*
2261 * Migrate the IO-APIC irq in the presence of intr-remapping.
2262 *
2263 * For both level and edge triggered, irq migration is a simple atomic
2264 * update(of vector and cpu destination) of IRTE and flush the hardware cache.
2265 *
2266 * For level triggered, we eliminate the io-apic RTE modification (with the
2267 * updated vector information), by using a virtual vector (io-apic pin number).
2268 * Real vector that is used for interrupting cpu will be coming from
2269 * the interrupt-remapping table entry.
2270 */
2271static int
2272ir_ioapic_set_affinity(struct irq_data *data, const struct cpumask *mask,
2273 bool force)
2274{
2275 struct irq_cfg *cfg = data->chip_data;
2276 unsigned int dest, irq = data->irq;
2277 struct irte irte;
2278
2279 if (!cpumask_intersects(mask, cpu_online_mask))
2280 return -EINVAL;
2281
2282 if (get_irte(irq, &irte))
2283 return -EBUSY;
2284
2285 if (assign_irq_vector(irq, cfg, mask))
2286 return -EBUSY;
2287
2288 dest = apic->cpu_mask_to_apicid_and(cfg->domain, mask);
2289
2290 irte.vector = cfg->vector;
2291 irte.dest_id = IRTE_DEST(dest);
2292
2293 /*
2294 * Modified the IRTE and flushes the Interrupt entry cache.
2295 */
2296 modify_irte(irq, &irte);
2297
2298 if (cfg->move_in_progress)
2299 send_cleanup_vector(cfg);
2300
2301 cpumask_copy(data->affinity, mask);
2302 return 0;
2303}
2304
2305#else
2306static inline int
2307ir_ioapic_set_affinity(struct irq_data *data, const struct cpumask *mask,
2308 bool force)
2309{
2310 return 0;
2311}
2312#endif
2313
2314asmlinkage void smp_irq_move_cleanup_interrupt(void)
2315{
2316 unsigned vector, me;
2317
2318 ack_APIC_irq();
2319 exit_idle();
2320 irq_enter();
2321
2322 me = smp_processor_id();
2323 for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; vector++) {
2324 unsigned int irq;
2325 unsigned int irr;
2326 struct irq_desc *desc;
2327 struct irq_cfg *cfg;
2328 irq = __this_cpu_read(vector_irq[vector]);
2329
2330 if (irq == -1)
2331 continue;
2332
2333 desc = irq_to_desc(irq);
2334 if (!desc)
2335 continue;
2336
2337 cfg = irq_cfg(irq);
2338 raw_spin_lock(&desc->lock);
2339
2340 /*
2341 * Check if the irq migration is in progress. If so, we
2342 * haven't received the cleanup request yet for this irq.
2343 */
2344 if (cfg->move_in_progress)
2345 goto unlock;
2346
2347 if (vector == cfg->vector && cpumask_test_cpu(me, cfg->domain))
2348 goto unlock;
2349
2350 irr = apic_read(APIC_IRR + (vector / 32 * 0x10));
2351 /*
2352 * Check if the vector that needs to be cleanedup is
2353 * registered at the cpu's IRR. If so, then this is not
2354 * the best time to clean it up. Lets clean it up in the
2355 * next attempt by sending another IRQ_MOVE_CLEANUP_VECTOR
2356 * to myself.
2357 */
2358 if (irr & (1 << (vector % 32))) {
2359 apic->send_IPI_self(IRQ_MOVE_CLEANUP_VECTOR);
2360 goto unlock;
2361 }
2362 __this_cpu_write(vector_irq[vector], -1);
2363unlock:
2364 raw_spin_unlock(&desc->lock);
2365 }
2366
2367 irq_exit();
2368}
2369
2370static void __irq_complete_move(struct irq_cfg *cfg, unsigned vector)
2371{
2372 unsigned me;
2373
2374 if (likely(!cfg->move_in_progress))
2375 return;
2376
2377 me = smp_processor_id();
2378
2379 if (vector == cfg->vector && cpumask_test_cpu(me, cfg->domain))
2380 send_cleanup_vector(cfg);
2381}
2382
2383static void irq_complete_move(struct irq_cfg *cfg)
2384{
2385 __irq_complete_move(cfg, ~get_irq_regs()->orig_ax);
2386}
2387
2388void irq_force_complete_move(int irq)
2389{
2390 struct irq_cfg *cfg = irq_get_chip_data(irq);
2391
2392 if (!cfg)
2393 return;
2394
2395 __irq_complete_move(cfg, cfg->vector);
2396}
2397#else
2398static inline void irq_complete_move(struct irq_cfg *cfg) { }
2399#endif
2400
2401static void ack_apic_edge(struct irq_data *data)
2402{
2403 irq_complete_move(data->chip_data);
2404 irq_move_irq(data);
2405 ack_APIC_irq();
2406}
2407
2408atomic_t irq_mis_count;
2409
2410/*
2411 * IO-APIC versions below 0x20 don't support EOI register.
2412 * For the record, here is the information about various versions:
2413 * 0Xh 82489DX
2414 * 1Xh I/OAPIC or I/O(x)APIC which are not PCI 2.2 Compliant
2415 * 2Xh I/O(x)APIC which is PCI 2.2 Compliant
2416 * 30h-FFh Reserved
2417 *
2418 * Some of the Intel ICH Specs (ICH2 to ICH5) documents the io-apic
2419 * version as 0x2. This is an error with documentation and these ICH chips
2420 * use io-apic's of version 0x20.
2421 *
2422 * For IO-APIC's with EOI register, we use that to do an explicit EOI.
2423 * Otherwise, we simulate the EOI message manually by changing the trigger
2424 * mode to edge and then back to level, with RTE being masked during this.
2425*/
2426static void eoi_ioapic_irq(unsigned int irq, struct irq_cfg *cfg)
2427{
2428 struct irq_pin_list *entry;
2429 unsigned long flags;
2430
2431 raw_spin_lock_irqsave(&ioapic_lock, flags);
2432 for_each_irq_pin(entry, cfg->irq_2_pin) {
2433 if (mpc_ioapic_ver(entry->apic) >= 0x20) {
2434 /*
2435 * Intr-remapping uses pin number as the virtual vector
2436 * in the RTE. Actual vector is programmed in
2437 * intr-remapping table entry. Hence for the io-apic
2438 * EOI we use the pin number.
2439 */
2440 if (irq_remapped(cfg))
2441 io_apic_eoi(entry->apic, entry->pin);
2442 else
2443 io_apic_eoi(entry->apic, cfg->vector);
2444 } else {
2445 __mask_and_edge_IO_APIC_irq(entry);
2446 __unmask_and_level_IO_APIC_irq(entry);
2447 }
2448 }
2449 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2450}
2451
2452static void ack_apic_level(struct irq_data *data)
2453{
2454 struct irq_cfg *cfg = data->chip_data;
2455 int i, do_unmask_irq = 0, irq = data->irq;
2456 unsigned long v;
2457
2458 irq_complete_move(cfg);
2459#ifdef CONFIG_GENERIC_PENDING_IRQ
2460 /* If we are moving the irq we need to mask it */
2461 if (unlikely(irqd_is_setaffinity_pending(data))) {
2462 do_unmask_irq = 1;
2463 mask_ioapic(cfg);
2464 }
2465#endif
2466
2467 /*
2468 * It appears there is an erratum which affects at least version 0x11
2469 * of I/O APIC (that's the 82093AA and cores integrated into various
2470 * chipsets). Under certain conditions a level-triggered interrupt is
2471 * erroneously delivered as edge-triggered one but the respective IRR
2472 * bit gets set nevertheless. As a result the I/O unit expects an EOI
2473 * message but it will never arrive and further interrupts are blocked
2474 * from the source. The exact reason is so far unknown, but the
2475 * phenomenon was observed when two consecutive interrupt requests
2476 * from a given source get delivered to the same CPU and the source is
2477 * temporarily disabled in between.
2478 *
2479 * A workaround is to simulate an EOI message manually. We achieve it
2480 * by setting the trigger mode to edge and then to level when the edge
2481 * trigger mode gets detected in the TMR of a local APIC for a
2482 * level-triggered interrupt. We mask the source for the time of the
2483 * operation to prevent an edge-triggered interrupt escaping meanwhile.
2484 * The idea is from Manfred Spraul. --macro
2485 *
2486 * Also in the case when cpu goes offline, fixup_irqs() will forward
2487 * any unhandled interrupt on the offlined cpu to the new cpu
2488 * destination that is handling the corresponding interrupt. This
2489 * interrupt forwarding is done via IPI's. Hence, in this case also
2490 * level-triggered io-apic interrupt will be seen as an edge
2491 * interrupt in the IRR. And we can't rely on the cpu's EOI
2492 * to be broadcasted to the IO-APIC's which will clear the remoteIRR
2493 * corresponding to the level-triggered interrupt. Hence on IO-APIC's
2494 * supporting EOI register, we do an explicit EOI to clear the
2495 * remote IRR and on IO-APIC's which don't have an EOI register,
2496 * we use the above logic (mask+edge followed by unmask+level) from
2497 * Manfred Spraul to clear the remote IRR.
2498 */
2499 i = cfg->vector;
2500 v = apic_read(APIC_TMR + ((i & ~0x1f) >> 1));
2501
2502 /*
2503 * We must acknowledge the irq before we move it or the acknowledge will
2504 * not propagate properly.
2505 */
2506 ack_APIC_irq();
2507
2508 /*
2509 * Tail end of clearing remote IRR bit (either by delivering the EOI
2510 * message via io-apic EOI register write or simulating it using
2511 * mask+edge followed by unnask+level logic) manually when the
2512 * level triggered interrupt is seen as the edge triggered interrupt
2513 * at the cpu.
2514 */
2515 if (!(v & (1 << (i & 0x1f)))) {
2516 atomic_inc(&irq_mis_count);
2517
2518 eoi_ioapic_irq(irq, cfg);
2519 }
2520
2521 /* Now we can move and renable the irq */
2522 if (unlikely(do_unmask_irq)) {
2523 /* Only migrate the irq if the ack has been received.
2524 *
2525 * On rare occasions the broadcast level triggered ack gets
2526 * delayed going to ioapics, and if we reprogram the
2527 * vector while Remote IRR is still set the irq will never
2528 * fire again.
2529 *
2530 * To prevent this scenario we read the Remote IRR bit
2531 * of the ioapic. This has two effects.
2532 * - On any sane system the read of the ioapic will
2533 * flush writes (and acks) going to the ioapic from
2534 * this cpu.
2535 * - We get to see if the ACK has actually been delivered.
2536 *
2537 * Based on failed experiments of reprogramming the
2538 * ioapic entry from outside of irq context starting
2539 * with masking the ioapic entry and then polling until
2540 * Remote IRR was clear before reprogramming the
2541 * ioapic I don't trust the Remote IRR bit to be
2542 * completey accurate.
2543 *
2544 * However there appears to be no other way to plug
2545 * this race, so if the Remote IRR bit is not
2546 * accurate and is causing problems then it is a hardware bug
2547 * and you can go talk to the chipset vendor about it.
2548 */
2549 if (!io_apic_level_ack_pending(cfg))
2550 irq_move_masked_irq(data);
2551 unmask_ioapic(cfg);
2552 }
2553}
2554
2555#ifdef CONFIG_INTR_REMAP
2556static void ir_ack_apic_edge(struct irq_data *data)
2557{
2558 ack_APIC_irq();
2559}
2560
2561static void ir_ack_apic_level(struct irq_data *data)
2562{
2563 ack_APIC_irq();
2564 eoi_ioapic_irq(data->irq, data->chip_data);
2565}
2566#endif /* CONFIG_INTR_REMAP */
2567
2568static struct irq_chip ioapic_chip __read_mostly = {
2569 .name = "IO-APIC",
2570 .irq_startup = startup_ioapic_irq,
2571 .irq_mask = mask_ioapic_irq,
2572 .irq_unmask = unmask_ioapic_irq,
2573 .irq_ack = ack_apic_edge,
2574 .irq_eoi = ack_apic_level,
2575#ifdef CONFIG_SMP
2576 .irq_set_affinity = ioapic_set_affinity,
2577#endif
2578 .irq_retrigger = ioapic_retrigger_irq,
2579};
2580
2581static struct irq_chip ir_ioapic_chip __read_mostly = {
2582 .name = "IR-IO-APIC",
2583 .irq_startup = startup_ioapic_irq,
2584 .irq_mask = mask_ioapic_irq,
2585 .irq_unmask = unmask_ioapic_irq,
2586#ifdef CONFIG_INTR_REMAP
2587 .irq_ack = ir_ack_apic_edge,
2588 .irq_eoi = ir_ack_apic_level,
2589#ifdef CONFIG_SMP
2590 .irq_set_affinity = ir_ioapic_set_affinity,
2591#endif
2592#endif
2593 .irq_retrigger = ioapic_retrigger_irq,
2594};
2595
2596static inline void init_IO_APIC_traps(void)
2597{
2598 struct irq_cfg *cfg;
2599 unsigned int irq;
2600
2601 /*
2602 * NOTE! The local APIC isn't very good at handling
2603 * multiple interrupts at the same interrupt level.
2604 * As the interrupt level is determined by taking the
2605 * vector number and shifting that right by 4, we
2606 * want to spread these out a bit so that they don't
2607 * all fall in the same interrupt level.
2608 *
2609 * Also, we've got to be careful not to trash gate
2610 * 0x80, because int 0x80 is hm, kind of importantish. ;)
2611 */
2612 for_each_active_irq(irq) {
2613 cfg = irq_get_chip_data(irq);
2614 if (IO_APIC_IRQ(irq) && cfg && !cfg->vector) {
2615 /*
2616 * Hmm.. We don't have an entry for this,
2617 * so default to an old-fashioned 8259
2618 * interrupt if we can..
2619 */
2620 if (irq < legacy_pic->nr_legacy_irqs)
2621 legacy_pic->make_irq(irq);
2622 else
2623 /* Strange. Oh, well.. */
2624 irq_set_chip(irq, &no_irq_chip);
2625 }
2626 }
2627}
2628
2629/*
2630 * The local APIC irq-chip implementation:
2631 */
2632
2633static void mask_lapic_irq(struct irq_data *data)
2634{
2635 unsigned long v;
2636
2637 v = apic_read(APIC_LVT0);
2638 apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
2639}
2640
2641static void unmask_lapic_irq(struct irq_data *data)
2642{
2643 unsigned long v;
2644
2645 v = apic_read(APIC_LVT0);
2646 apic_write(APIC_LVT0, v & ~APIC_LVT_MASKED);
2647}
2648
2649static void ack_lapic_irq(struct irq_data *data)
2650{
2651 ack_APIC_irq();
2652}
2653
2654static struct irq_chip lapic_chip __read_mostly = {
2655 .name = "local-APIC",
2656 .irq_mask = mask_lapic_irq,
2657 .irq_unmask = unmask_lapic_irq,
2658 .irq_ack = ack_lapic_irq,
2659};
2660
2661static void lapic_register_intr(int irq)
2662{
2663 irq_clear_status_flags(irq, IRQ_LEVEL);
2664 irq_set_chip_and_handler_name(irq, &lapic_chip, handle_edge_irq,
2665 "edge");
2666}
2667
2668/*
2669 * This looks a bit hackish but it's about the only one way of sending
2670 * a few INTA cycles to 8259As and any associated glue logic. ICR does
2671 * not support the ExtINT mode, unfortunately. We need to send these
2672 * cycles as some i82489DX-based boards have glue logic that keeps the
2673 * 8259A interrupt line asserted until INTA. --macro
2674 */
2675static inline void __init unlock_ExtINT_logic(void)
2676{
2677 int apic, pin, i;
2678 struct IO_APIC_route_entry entry0, entry1;
2679 unsigned char save_control, save_freq_select;
2680
2681 pin = find_isa_irq_pin(8, mp_INT);
2682 if (pin == -1) {
2683 WARN_ON_ONCE(1);
2684 return;
2685 }
2686 apic = find_isa_irq_apic(8, mp_INT);
2687 if (apic == -1) {
2688 WARN_ON_ONCE(1);
2689 return;
2690 }
2691
2692 entry0 = ioapic_read_entry(apic, pin);
2693 clear_IO_APIC_pin(apic, pin);
2694
2695 memset(&entry1, 0, sizeof(entry1));
2696
2697 entry1.dest_mode = 0; /* physical delivery */
2698 entry1.mask = 0; /* unmask IRQ now */
2699 entry1.dest = hard_smp_processor_id();
2700 entry1.delivery_mode = dest_ExtINT;
2701 entry1.polarity = entry0.polarity;
2702 entry1.trigger = 0;
2703 entry1.vector = 0;
2704
2705 ioapic_write_entry(apic, pin, entry1);
2706
2707 save_control = CMOS_READ(RTC_CONTROL);
2708 save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
2709 CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6,
2710 RTC_FREQ_SELECT);
2711 CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL);
2712
2713 i = 100;
2714 while (i-- > 0) {
2715 mdelay(10);
2716 if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF)
2717 i -= 10;
2718 }
2719
2720 CMOS_WRITE(save_control, RTC_CONTROL);
2721 CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
2722 clear_IO_APIC_pin(apic, pin);
2723
2724 ioapic_write_entry(apic, pin, entry0);
2725}
2726
2727static int disable_timer_pin_1 __initdata;
2728/* Actually the next is obsolete, but keep it for paranoid reasons -AK */
2729static int __init disable_timer_pin_setup(char *arg)
2730{
2731 disable_timer_pin_1 = 1;
2732 return 0;
2733}
2734early_param("disable_timer_pin_1", disable_timer_pin_setup);
2735
2736int timer_through_8259 __initdata;
2737
2738/*
2739 * This code may look a bit paranoid, but it's supposed to cooperate with
2740 * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ
2741 * is so screwy. Thanks to Brian Perkins for testing/hacking this beast
2742 * fanatically on his truly buggy board.
2743 *
2744 * FIXME: really need to revamp this for all platforms.
2745 */
2746static inline void __init check_timer(void)
2747{
2748 struct irq_cfg *cfg = irq_get_chip_data(0);
2749 int node = cpu_to_node(0);
2750 int apic1, pin1, apic2, pin2;
2751 unsigned long flags;
2752 int no_pin1 = 0;
2753
2754 local_irq_save(flags);
2755
2756 /*
2757 * get/set the timer IRQ vector:
2758 */
2759 legacy_pic->mask(0);
2760 assign_irq_vector(0, cfg, apic->target_cpus());
2761
2762 /*
2763 * As IRQ0 is to be enabled in the 8259A, the virtual
2764 * wire has to be disabled in the local APIC. Also
2765 * timer interrupts need to be acknowledged manually in
2766 * the 8259A for the i82489DX when using the NMI
2767 * watchdog as that APIC treats NMIs as level-triggered.
2768 * The AEOI mode will finish them in the 8259A
2769 * automatically.
2770 */
2771 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
2772 legacy_pic->init(1);
2773
2774 pin1 = find_isa_irq_pin(0, mp_INT);
2775 apic1 = find_isa_irq_apic(0, mp_INT);
2776 pin2 = ioapic_i8259.pin;
2777 apic2 = ioapic_i8259.apic;
2778
2779 apic_printk(APIC_QUIET, KERN_INFO "..TIMER: vector=0x%02X "
2780 "apic1=%d pin1=%d apic2=%d pin2=%d\n",
2781 cfg->vector, apic1, pin1, apic2, pin2);
2782
2783 /*
2784 * Some BIOS writers are clueless and report the ExtINTA
2785 * I/O APIC input from the cascaded 8259A as the timer
2786 * interrupt input. So just in case, if only one pin
2787 * was found above, try it both directly and through the
2788 * 8259A.
2789 */
2790 if (pin1 == -1) {
2791 if (intr_remapping_enabled)
2792 panic("BIOS bug: timer not connected to IO-APIC");
2793 pin1 = pin2;
2794 apic1 = apic2;
2795 no_pin1 = 1;
2796 } else if (pin2 == -1) {
2797 pin2 = pin1;
2798 apic2 = apic1;
2799 }
2800
2801 if (pin1 != -1) {
2802 /*
2803 * Ok, does IRQ0 through the IOAPIC work?
2804 */
2805 if (no_pin1) {
2806 add_pin_to_irq_node(cfg, node, apic1, pin1);
2807 setup_timer_IRQ0_pin(apic1, pin1, cfg->vector);
2808 } else {
2809 /* for edge trigger, setup_ioapic_irq already
2810 * leave it unmasked.
2811 * so only need to unmask if it is level-trigger
2812 * do we really have level trigger timer?
2813 */
2814 int idx;
2815 idx = find_irq_entry(apic1, pin1, mp_INT);
2816 if (idx != -1 && irq_trigger(idx))
2817 unmask_ioapic(cfg);
2818 }
2819 if (timer_irq_works()) {
2820 if (disable_timer_pin_1 > 0)
2821 clear_IO_APIC_pin(0, pin1);
2822 goto out;
2823 }
2824 if (intr_remapping_enabled)
2825 panic("timer doesn't work through Interrupt-remapped IO-APIC");
2826 local_irq_disable();
2827 clear_IO_APIC_pin(apic1, pin1);
2828 if (!no_pin1)
2829 apic_printk(APIC_QUIET, KERN_ERR "..MP-BIOS bug: "
2830 "8254 timer not connected to IO-APIC\n");
2831
2832 apic_printk(APIC_QUIET, KERN_INFO "...trying to set up timer "
2833 "(IRQ0) through the 8259A ...\n");
2834 apic_printk(APIC_QUIET, KERN_INFO
2835 "..... (found apic %d pin %d) ...\n", apic2, pin2);
2836 /*
2837 * legacy devices should be connected to IO APIC #0
2838 */
2839 replace_pin_at_irq_node(cfg, node, apic1, pin1, apic2, pin2);
2840 setup_timer_IRQ0_pin(apic2, pin2, cfg->vector);
2841 legacy_pic->unmask(0);
2842 if (timer_irq_works()) {
2843 apic_printk(APIC_QUIET, KERN_INFO "....... works.\n");
2844 timer_through_8259 = 1;
2845 goto out;
2846 }
2847 /*
2848 * Cleanup, just in case ...
2849 */
2850 local_irq_disable();
2851 legacy_pic->mask(0);
2852 clear_IO_APIC_pin(apic2, pin2);
2853 apic_printk(APIC_QUIET, KERN_INFO "....... failed.\n");
2854 }
2855
2856 apic_printk(APIC_QUIET, KERN_INFO
2857 "...trying to set up timer as Virtual Wire IRQ...\n");
2858
2859 lapic_register_intr(0);
2860 apic_write(APIC_LVT0, APIC_DM_FIXED | cfg->vector); /* Fixed mode */
2861 legacy_pic->unmask(0);
2862
2863 if (timer_irq_works()) {
2864 apic_printk(APIC_QUIET, KERN_INFO "..... works.\n");
2865 goto out;
2866 }
2867 local_irq_disable();
2868 legacy_pic->mask(0);
2869 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | cfg->vector);
2870 apic_printk(APIC_QUIET, KERN_INFO "..... failed.\n");
2871
2872 apic_printk(APIC_QUIET, KERN_INFO
2873 "...trying to set up timer as ExtINT IRQ...\n");
2874
2875 legacy_pic->init(0);
2876 legacy_pic->make_irq(0);
2877 apic_write(APIC_LVT0, APIC_DM_EXTINT);
2878
2879 unlock_ExtINT_logic();
2880
2881 if (timer_irq_works()) {
2882 apic_printk(APIC_QUIET, KERN_INFO "..... works.\n");
2883 goto out;
2884 }
2885 local_irq_disable();
2886 apic_printk(APIC_QUIET, KERN_INFO "..... failed :(.\n");
2887 panic("IO-APIC + timer doesn't work! Boot with apic=debug and send a "
2888 "report. Then try booting with the 'noapic' option.\n");
2889out:
2890 local_irq_restore(flags);
2891}
2892
2893/*
2894 * Traditionally ISA IRQ2 is the cascade IRQ, and is not available
2895 * to devices. However there may be an I/O APIC pin available for
2896 * this interrupt regardless. The pin may be left unconnected, but
2897 * typically it will be reused as an ExtINT cascade interrupt for
2898 * the master 8259A. In the MPS case such a pin will normally be
2899 * reported as an ExtINT interrupt in the MP table. With ACPI
2900 * there is no provision for ExtINT interrupts, and in the absence
2901 * of an override it would be treated as an ordinary ISA I/O APIC
2902 * interrupt, that is edge-triggered and unmasked by default. We
2903 * used to do this, but it caused problems on some systems because
2904 * of the NMI watchdog and sometimes IRQ0 of the 8254 timer using
2905 * the same ExtINT cascade interrupt to drive the local APIC of the
2906 * bootstrap processor. Therefore we refrain from routing IRQ2 to
2907 * the I/O APIC in all cases now. No actual device should request
2908 * it anyway. --macro
2909 */
2910#define PIC_IRQS (1UL << PIC_CASCADE_IR)
2911
2912void __init setup_IO_APIC(void)
2913{
2914
2915 /*
2916 * calling enable_IO_APIC() is moved to setup_local_APIC for BP
2917 */
2918 io_apic_irqs = legacy_pic->nr_legacy_irqs ? ~PIC_IRQS : ~0UL;
2919
2920 apic_printk(APIC_VERBOSE, "ENABLING IO-APIC IRQs\n");
2921 /*
2922 * Set up IO-APIC IRQ routing.
2923 */
2924 x86_init.mpparse.setup_ioapic_ids();
2925
2926 sync_Arb_IDs();
2927 setup_IO_APIC_irqs();
2928 init_IO_APIC_traps();
2929 if (legacy_pic->nr_legacy_irqs)
2930 check_timer();
2931}
2932
2933/*
2934 * Called after all the initialization is done. If we didn't find any
2935 * APIC bugs then we can allow the modify fast path
2936 */
2937
2938static int __init io_apic_bug_finalize(void)
2939{
2940 if (sis_apic_bug == -1)
2941 sis_apic_bug = 0;
2942 return 0;
2943}
2944
2945late_initcall(io_apic_bug_finalize);
2946
2947static void resume_ioapic_id(int ioapic_id)
2948{
2949 unsigned long flags;
2950 union IO_APIC_reg_00 reg_00;
2951
2952
2953 raw_spin_lock_irqsave(&ioapic_lock, flags);
2954 reg_00.raw = io_apic_read(ioapic_id, 0);
2955 if (reg_00.bits.ID != mpc_ioapic_id(ioapic_id)) {
2956 reg_00.bits.ID = mpc_ioapic_id(ioapic_id);
2957 io_apic_write(ioapic_id, 0, reg_00.raw);
2958 }
2959 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2960}
2961
2962static void ioapic_resume(void)
2963{
2964 int ioapic_id;
2965
2966 for (ioapic_id = nr_ioapics - 1; ioapic_id >= 0; ioapic_id--)
2967 resume_ioapic_id(ioapic_id);
2968
2969 restore_ioapic_entries();
2970}
2971
2972static struct syscore_ops ioapic_syscore_ops = {
2973 .suspend = save_ioapic_entries,
2974 .resume = ioapic_resume,
2975};
2976
2977static int __init ioapic_init_ops(void)
2978{
2979 register_syscore_ops(&ioapic_syscore_ops);
2980
2981 return 0;
2982}
2983
2984device_initcall(ioapic_init_ops);
2985
2986/*
2987 * Dynamic irq allocate and deallocation
2988 */
2989unsigned int create_irq_nr(unsigned int from, int node)
2990{
2991 struct irq_cfg *cfg;
2992 unsigned long flags;
2993 unsigned int ret = 0;
2994 int irq;
2995
2996 if (from < nr_irqs_gsi)
2997 from = nr_irqs_gsi;
2998
2999 irq = alloc_irq_from(from, node);
3000 if (irq < 0)
3001 return 0;
3002 cfg = alloc_irq_cfg(irq, node);
3003 if (!cfg) {
3004 free_irq_at(irq, NULL);
3005 return 0;
3006 }
3007
3008 raw_spin_lock_irqsave(&vector_lock, flags);
3009 if (!__assign_irq_vector(irq, cfg, apic->target_cpus()))
3010 ret = irq;
3011 raw_spin_unlock_irqrestore(&vector_lock, flags);
3012
3013 if (ret) {
3014 irq_set_chip_data(irq, cfg);
3015 irq_clear_status_flags(irq, IRQ_NOREQUEST);
3016 } else {
3017 free_irq_at(irq, cfg);
3018 }
3019 return ret;
3020}
3021
3022int create_irq(void)
3023{
3024 int node = cpu_to_node(0);
3025 unsigned int irq_want;
3026 int irq;
3027
3028 irq_want = nr_irqs_gsi;
3029 irq = create_irq_nr(irq_want, node);
3030
3031 if (irq == 0)
3032 irq = -1;
3033
3034 return irq;
3035}
3036
3037void destroy_irq(unsigned int irq)
3038{
3039 struct irq_cfg *cfg = irq_get_chip_data(irq);
3040 unsigned long flags;
3041
3042 irq_set_status_flags(irq, IRQ_NOREQUEST|IRQ_NOPROBE);
3043
3044 if (irq_remapped(cfg))
3045 free_irte(irq);
3046 raw_spin_lock_irqsave(&vector_lock, flags);
3047 __clear_irq_vector(irq, cfg);
3048 raw_spin_unlock_irqrestore(&vector_lock, flags);
3049 free_irq_at(irq, cfg);
3050}
3051
3052/*
3053 * MSI message composition
3054 */
3055#ifdef CONFIG_PCI_MSI
3056static int msi_compose_msg(struct pci_dev *pdev, unsigned int irq,
3057 struct msi_msg *msg, u8 hpet_id)
3058{
3059 struct irq_cfg *cfg;
3060 int err;
3061 unsigned dest;
3062
3063 if (disable_apic)
3064 return -ENXIO;
3065
3066 cfg = irq_cfg(irq);
3067 err = assign_irq_vector(irq, cfg, apic->target_cpus());
3068 if (err)
3069 return err;
3070
3071 dest = apic->cpu_mask_to_apicid_and(cfg->domain, apic->target_cpus());
3072
3073 if (irq_remapped(cfg)) {
3074 struct irte irte;
3075 int ir_index;
3076 u16 sub_handle;
3077
3078 ir_index = map_irq_to_irte_handle(irq, &sub_handle);
3079 BUG_ON(ir_index == -1);
3080
3081 prepare_irte(&irte, cfg->vector, dest);
3082
3083 /* Set source-id of interrupt request */
3084 if (pdev)
3085 set_msi_sid(&irte, pdev);
3086 else
3087 set_hpet_sid(&irte, hpet_id);
3088
3089 modify_irte(irq, &irte);
3090
3091 msg->address_hi = MSI_ADDR_BASE_HI;
3092 msg->data = sub_handle;
3093 msg->address_lo = MSI_ADDR_BASE_LO | MSI_ADDR_IR_EXT_INT |
3094 MSI_ADDR_IR_SHV |
3095 MSI_ADDR_IR_INDEX1(ir_index) |
3096 MSI_ADDR_IR_INDEX2(ir_index);
3097 } else {
3098 if (x2apic_enabled())
3099 msg->address_hi = MSI_ADDR_BASE_HI |
3100 MSI_ADDR_EXT_DEST_ID(dest);
3101 else
3102 msg->address_hi = MSI_ADDR_BASE_HI;
3103
3104 msg->address_lo =
3105 MSI_ADDR_BASE_LO |
3106 ((apic->irq_dest_mode == 0) ?
3107 MSI_ADDR_DEST_MODE_PHYSICAL:
3108 MSI_ADDR_DEST_MODE_LOGICAL) |
3109 ((apic->irq_delivery_mode != dest_LowestPrio) ?
3110 MSI_ADDR_REDIRECTION_CPU:
3111 MSI_ADDR_REDIRECTION_LOWPRI) |
3112 MSI_ADDR_DEST_ID(dest);
3113
3114 msg->data =
3115 MSI_DATA_TRIGGER_EDGE |
3116 MSI_DATA_LEVEL_ASSERT |
3117 ((apic->irq_delivery_mode != dest_LowestPrio) ?
3118 MSI_DATA_DELIVERY_FIXED:
3119 MSI_DATA_DELIVERY_LOWPRI) |
3120 MSI_DATA_VECTOR(cfg->vector);
3121 }
3122 return err;
3123}
3124
3125#ifdef CONFIG_SMP
3126static int
3127msi_set_affinity(struct irq_data *data, const struct cpumask *mask, bool force)
3128{
3129 struct irq_cfg *cfg = data->chip_data;
3130 struct msi_msg msg;
3131 unsigned int dest;
3132
3133 if (__ioapic_set_affinity(data, mask, &dest))
3134 return -1;
3135
3136 __get_cached_msi_msg(data->msi_desc, &msg);
3137
3138 msg.data &= ~MSI_DATA_VECTOR_MASK;
3139 msg.data |= MSI_DATA_VECTOR(cfg->vector);
3140 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
3141 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
3142
3143 __write_msi_msg(data->msi_desc, &msg);
3144
3145 return 0;
3146}
3147#ifdef CONFIG_INTR_REMAP
3148/*
3149 * Migrate the MSI irq to another cpumask. This migration is
3150 * done in the process context using interrupt-remapping hardware.
3151 */
3152static int
3153ir_msi_set_affinity(struct irq_data *data, const struct cpumask *mask,
3154 bool force)
3155{
3156 struct irq_cfg *cfg = data->chip_data;
3157 unsigned int dest, irq = data->irq;
3158 struct irte irte;
3159
3160 if (get_irte(irq, &irte))
3161 return -1;
3162
3163 if (__ioapic_set_affinity(data, mask, &dest))
3164 return -1;
3165
3166 irte.vector = cfg->vector;
3167 irte.dest_id = IRTE_DEST(dest);
3168
3169 /*
3170 * atomically update the IRTE with the new destination and vector.
3171 */
3172 modify_irte(irq, &irte);
3173
3174 /*
3175 * After this point, all the interrupts will start arriving
3176 * at the new destination. So, time to cleanup the previous
3177 * vector allocation.
3178 */
3179 if (cfg->move_in_progress)
3180 send_cleanup_vector(cfg);
3181
3182 return 0;
3183}
3184
3185#endif
3186#endif /* CONFIG_SMP */
3187
3188/*
3189 * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices,
3190 * which implement the MSI or MSI-X Capability Structure.
3191 */
3192static struct irq_chip msi_chip = {
3193 .name = "PCI-MSI",
3194 .irq_unmask = unmask_msi_irq,
3195 .irq_mask = mask_msi_irq,
3196 .irq_ack = ack_apic_edge,
3197#ifdef CONFIG_SMP
3198 .irq_set_affinity = msi_set_affinity,
3199#endif
3200 .irq_retrigger = ioapic_retrigger_irq,
3201};
3202
3203static struct irq_chip msi_ir_chip = {
3204 .name = "IR-PCI-MSI",
3205 .irq_unmask = unmask_msi_irq,
3206 .irq_mask = mask_msi_irq,
3207#ifdef CONFIG_INTR_REMAP
3208 .irq_ack = ir_ack_apic_edge,
3209#ifdef CONFIG_SMP
3210 .irq_set_affinity = ir_msi_set_affinity,
3211#endif
3212#endif
3213 .irq_retrigger = ioapic_retrigger_irq,
3214};
3215
3216/*
3217 * Map the PCI dev to the corresponding remapping hardware unit
3218 * and allocate 'nvec' consecutive interrupt-remapping table entries
3219 * in it.
3220 */
3221static int msi_alloc_irte(struct pci_dev *dev, int irq, int nvec)
3222{
3223 struct intel_iommu *iommu;
3224 int index;
3225
3226 iommu = map_dev_to_ir(dev);
3227 if (!iommu) {
3228 printk(KERN_ERR
3229 "Unable to map PCI %s to iommu\n", pci_name(dev));
3230 return -ENOENT;
3231 }
3232
3233 index = alloc_irte(iommu, irq, nvec);
3234 if (index < 0) {
3235 printk(KERN_ERR
3236 "Unable to allocate %d IRTE for PCI %s\n", nvec,
3237 pci_name(dev));
3238 return -ENOSPC;
3239 }
3240 return index;
3241}
3242
3243static int setup_msi_irq(struct pci_dev *dev, struct msi_desc *msidesc, int irq)
3244{
3245 struct irq_chip *chip = &msi_chip;
3246 struct msi_msg msg;
3247 int ret;
3248
3249 ret = msi_compose_msg(dev, irq, &msg, -1);
3250 if (ret < 0)
3251 return ret;
3252
3253 irq_set_msi_desc(irq, msidesc);
3254 write_msi_msg(irq, &msg);
3255
3256 if (irq_remapped(irq_get_chip_data(irq))) {
3257 irq_set_status_flags(irq, IRQ_MOVE_PCNTXT);
3258 chip = &msi_ir_chip;
3259 }
3260
3261 irq_set_chip_and_handler_name(irq, chip, handle_edge_irq, "edge");
3262
3263 dev_printk(KERN_DEBUG, &dev->dev, "irq %d for MSI/MSI-X\n", irq);
3264
3265 return 0;
3266}
3267
3268int native_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
3269{
3270 int node, ret, sub_handle, index = 0;
3271 unsigned int irq, irq_want;
3272 struct msi_desc *msidesc;
3273 struct intel_iommu *iommu = NULL;
3274
3275 /* x86 doesn't support multiple MSI yet */
3276 if (type == PCI_CAP_ID_MSI && nvec > 1)
3277 return 1;
3278
3279 node = dev_to_node(&dev->dev);
3280 irq_want = nr_irqs_gsi;
3281 sub_handle = 0;
3282 list_for_each_entry(msidesc, &dev->msi_list, list) {
3283 irq = create_irq_nr(irq_want, node);
3284 if (irq == 0)
3285 return -1;
3286 irq_want = irq + 1;
3287 if (!intr_remapping_enabled)
3288 goto no_ir;
3289
3290 if (!sub_handle) {
3291 /*
3292 * allocate the consecutive block of IRTE's
3293 * for 'nvec'
3294 */
3295 index = msi_alloc_irte(dev, irq, nvec);
3296 if (index < 0) {
3297 ret = index;
3298 goto error;
3299 }
3300 } else {
3301 iommu = map_dev_to_ir(dev);
3302 if (!iommu) {
3303 ret = -ENOENT;
3304 goto error;
3305 }
3306 /*
3307 * setup the mapping between the irq and the IRTE
3308 * base index, the sub_handle pointing to the
3309 * appropriate interrupt remap table entry.
3310 */
3311 set_irte_irq(irq, iommu, index, sub_handle);
3312 }
3313no_ir:
3314 ret = setup_msi_irq(dev, msidesc, irq);
3315 if (ret < 0)
3316 goto error;
3317 sub_handle++;
3318 }
3319 return 0;
3320
3321error:
3322 destroy_irq(irq);
3323 return ret;
3324}
3325
3326void native_teardown_msi_irq(unsigned int irq)
3327{
3328 destroy_irq(irq);
3329}
3330
3331#if defined (CONFIG_DMAR) || defined (CONFIG_INTR_REMAP)
3332#ifdef CONFIG_SMP
3333static int
3334dmar_msi_set_affinity(struct irq_data *data, const struct cpumask *mask,
3335 bool force)
3336{
3337 struct irq_cfg *cfg = data->chip_data;
3338 unsigned int dest, irq = data->irq;
3339 struct msi_msg msg;
3340
3341 if (__ioapic_set_affinity(data, mask, &dest))
3342 return -1;
3343
3344 dmar_msi_read(irq, &msg);
3345
3346 msg.data &= ~MSI_DATA_VECTOR_MASK;
3347 msg.data |= MSI_DATA_VECTOR(cfg->vector);
3348 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
3349 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
3350 msg.address_hi = MSI_ADDR_BASE_HI | MSI_ADDR_EXT_DEST_ID(dest);
3351
3352 dmar_msi_write(irq, &msg);
3353
3354 return 0;
3355}
3356
3357#endif /* CONFIG_SMP */
3358
3359static struct irq_chip dmar_msi_type = {
3360 .name = "DMAR_MSI",
3361 .irq_unmask = dmar_msi_unmask,
3362 .irq_mask = dmar_msi_mask,
3363 .irq_ack = ack_apic_edge,
3364#ifdef CONFIG_SMP
3365 .irq_set_affinity = dmar_msi_set_affinity,
3366#endif
3367 .irq_retrigger = ioapic_retrigger_irq,
3368};
3369
3370int arch_setup_dmar_msi(unsigned int irq)
3371{
3372 int ret;
3373 struct msi_msg msg;
3374
3375 ret = msi_compose_msg(NULL, irq, &msg, -1);
3376 if (ret < 0)
3377 return ret;
3378 dmar_msi_write(irq, &msg);
3379 irq_set_chip_and_handler_name(irq, &dmar_msi_type, handle_edge_irq,
3380 "edge");
3381 return 0;
3382}
3383#endif
3384
3385#ifdef CONFIG_HPET_TIMER
3386
3387#ifdef CONFIG_SMP
3388static int hpet_msi_set_affinity(struct irq_data *data,
3389 const struct cpumask *mask, bool force)
3390{
3391 struct irq_cfg *cfg = data->chip_data;
3392 struct msi_msg msg;
3393 unsigned int dest;
3394
3395 if (__ioapic_set_affinity(data, mask, &dest))
3396 return -1;
3397
3398 hpet_msi_read(data->handler_data, &msg);
3399
3400 msg.data &= ~MSI_DATA_VECTOR_MASK;
3401 msg.data |= MSI_DATA_VECTOR(cfg->vector);
3402 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
3403 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
3404
3405 hpet_msi_write(data->handler_data, &msg);
3406
3407 return 0;
3408}
3409
3410#endif /* CONFIG_SMP */
3411
3412static struct irq_chip ir_hpet_msi_type = {
3413 .name = "IR-HPET_MSI",
3414 .irq_unmask = hpet_msi_unmask,
3415 .irq_mask = hpet_msi_mask,
3416#ifdef CONFIG_INTR_REMAP
3417 .irq_ack = ir_ack_apic_edge,
3418#ifdef CONFIG_SMP
3419 .irq_set_affinity = ir_msi_set_affinity,
3420#endif
3421#endif
3422 .irq_retrigger = ioapic_retrigger_irq,
3423};
3424
3425static struct irq_chip hpet_msi_type = {
3426 .name = "HPET_MSI",
3427 .irq_unmask = hpet_msi_unmask,
3428 .irq_mask = hpet_msi_mask,
3429 .irq_ack = ack_apic_edge,
3430#ifdef CONFIG_SMP
3431 .irq_set_affinity = hpet_msi_set_affinity,
3432#endif
3433 .irq_retrigger = ioapic_retrigger_irq,
3434};
3435
3436int arch_setup_hpet_msi(unsigned int irq, unsigned int id)
3437{
3438 struct irq_chip *chip = &hpet_msi_type;
3439 struct msi_msg msg;
3440 int ret;
3441
3442 if (intr_remapping_enabled) {
3443 struct intel_iommu *iommu = map_hpet_to_ir(id);
3444 int index;
3445
3446 if (!iommu)
3447 return -1;
3448
3449 index = alloc_irte(iommu, irq, 1);
3450 if (index < 0)
3451 return -1;
3452 }
3453
3454 ret = msi_compose_msg(NULL, irq, &msg, id);
3455 if (ret < 0)
3456 return ret;
3457
3458 hpet_msi_write(irq_get_handler_data(irq), &msg);
3459 irq_set_status_flags(irq, IRQ_MOVE_PCNTXT);
3460 if (irq_remapped(irq_get_chip_data(irq)))
3461 chip = &ir_hpet_msi_type;
3462
3463 irq_set_chip_and_handler_name(irq, chip, handle_edge_irq, "edge");
3464 return 0;
3465}
3466#endif
3467
3468#endif /* CONFIG_PCI_MSI */
3469/*
3470 * Hypertransport interrupt support
3471 */
3472#ifdef CONFIG_HT_IRQ
3473
3474#ifdef CONFIG_SMP
3475
3476static void target_ht_irq(unsigned int irq, unsigned int dest, u8 vector)
3477{
3478 struct ht_irq_msg msg;
3479 fetch_ht_irq_msg(irq, &msg);
3480
3481 msg.address_lo &= ~(HT_IRQ_LOW_VECTOR_MASK | HT_IRQ_LOW_DEST_ID_MASK);
3482 msg.address_hi &= ~(HT_IRQ_HIGH_DEST_ID_MASK);
3483
3484 msg.address_lo |= HT_IRQ_LOW_VECTOR(vector) | HT_IRQ_LOW_DEST_ID(dest);
3485 msg.address_hi |= HT_IRQ_HIGH_DEST_ID(dest);
3486
3487 write_ht_irq_msg(irq, &msg);
3488}
3489
3490static int
3491ht_set_affinity(struct irq_data *data, const struct cpumask *mask, bool force)
3492{
3493 struct irq_cfg *cfg = data->chip_data;
3494 unsigned int dest;
3495
3496 if (__ioapic_set_affinity(data, mask, &dest))
3497 return -1;
3498
3499 target_ht_irq(data->irq, dest, cfg->vector);
3500 return 0;
3501}
3502
3503#endif
3504
3505static struct irq_chip ht_irq_chip = {
3506 .name = "PCI-HT",
3507 .irq_mask = mask_ht_irq,
3508 .irq_unmask = unmask_ht_irq,
3509 .irq_ack = ack_apic_edge,
3510#ifdef CONFIG_SMP
3511 .irq_set_affinity = ht_set_affinity,
3512#endif
3513 .irq_retrigger = ioapic_retrigger_irq,
3514};
3515
3516int arch_setup_ht_irq(unsigned int irq, struct pci_dev *dev)
3517{
3518 struct irq_cfg *cfg;
3519 int err;
3520
3521 if (disable_apic)
3522 return -ENXIO;
3523
3524 cfg = irq_cfg(irq);
3525 err = assign_irq_vector(irq, cfg, apic->target_cpus());
3526 if (!err) {
3527 struct ht_irq_msg msg;
3528 unsigned dest;
3529
3530 dest = apic->cpu_mask_to_apicid_and(cfg->domain,
3531 apic->target_cpus());
3532
3533 msg.address_hi = HT_IRQ_HIGH_DEST_ID(dest);
3534
3535 msg.address_lo =
3536 HT_IRQ_LOW_BASE |
3537 HT_IRQ_LOW_DEST_ID(dest) |
3538 HT_IRQ_LOW_VECTOR(cfg->vector) |
3539 ((apic->irq_dest_mode == 0) ?
3540 HT_IRQ_LOW_DM_PHYSICAL :
3541 HT_IRQ_LOW_DM_LOGICAL) |
3542 HT_IRQ_LOW_RQEOI_EDGE |
3543 ((apic->irq_delivery_mode != dest_LowestPrio) ?
3544 HT_IRQ_LOW_MT_FIXED :
3545 HT_IRQ_LOW_MT_ARBITRATED) |
3546 HT_IRQ_LOW_IRQ_MASKED;
3547
3548 write_ht_irq_msg(irq, &msg);
3549
3550 irq_set_chip_and_handler_name(irq, &ht_irq_chip,
3551 handle_edge_irq, "edge");
3552
3553 dev_printk(KERN_DEBUG, &dev->dev, "irq %d for HT\n", irq);
3554 }
3555 return err;
3556}
3557#endif /* CONFIG_HT_IRQ */
3558
3559static int
3560io_apic_setup_irq_pin(unsigned int irq, int node, struct io_apic_irq_attr *attr)
3561{
3562 struct irq_cfg *cfg = alloc_irq_and_cfg_at(irq, node);
3563 int ret;
3564
3565 if (!cfg)
3566 return -EINVAL;
3567 ret = __add_pin_to_irq_node(cfg, node, attr->ioapic, attr->ioapic_pin);
3568 if (!ret)
3569 setup_ioapic_irq(attr->ioapic, attr->ioapic_pin, irq, cfg,
3570 attr->trigger, attr->polarity);
3571 return ret;
3572}
3573
3574int io_apic_setup_irq_pin_once(unsigned int irq, int node,
3575 struct io_apic_irq_attr *attr)
3576{
3577 unsigned int id = attr->ioapic, pin = attr->ioapic_pin;
3578 int ret;
3579
3580 /* Avoid redundant programming */
3581 if (test_bit(pin, ioapics[id].pin_programmed)) {
3582 pr_debug("Pin %d-%d already programmed\n",
3583 mpc_ioapic_id(id), pin);
3584 return 0;
3585 }
3586 ret = io_apic_setup_irq_pin(irq, node, attr);
3587 if (!ret)
3588 set_bit(pin, ioapics[id].pin_programmed);
3589 return ret;
3590}
3591
3592static int __init io_apic_get_redir_entries(int ioapic)
3593{
3594 union IO_APIC_reg_01 reg_01;
3595 unsigned long flags;
3596
3597 raw_spin_lock_irqsave(&ioapic_lock, flags);
3598 reg_01.raw = io_apic_read(ioapic, 1);
3599 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
3600
3601 /* The register returns the maximum index redir index
3602 * supported, which is one less than the total number of redir
3603 * entries.
3604 */
3605 return reg_01.bits.entries + 1;
3606}
3607
3608static void __init probe_nr_irqs_gsi(void)
3609{
3610 int nr;
3611
3612 nr = gsi_top + NR_IRQS_LEGACY;
3613 if (nr > nr_irqs_gsi)
3614 nr_irqs_gsi = nr;
3615
3616 printk(KERN_DEBUG "nr_irqs_gsi: %d\n", nr_irqs_gsi);
3617}
3618
3619int get_nr_irqs_gsi(void)
3620{
3621 return nr_irqs_gsi;
3622}
3623
3624#ifdef CONFIG_SPARSE_IRQ
3625int __init arch_probe_nr_irqs(void)
3626{
3627 int nr;
3628
3629 if (nr_irqs > (NR_VECTORS * nr_cpu_ids))
3630 nr_irqs = NR_VECTORS * nr_cpu_ids;
3631
3632 nr = nr_irqs_gsi + 8 * nr_cpu_ids;
3633#if defined(CONFIG_PCI_MSI) || defined(CONFIG_HT_IRQ)
3634 /*
3635 * for MSI and HT dyn irq
3636 */
3637 nr += nr_irqs_gsi * 16;
3638#endif
3639 if (nr < nr_irqs)
3640 nr_irqs = nr;
3641
3642 return NR_IRQS_LEGACY;
3643}
3644#endif
3645
3646int io_apic_set_pci_routing(struct device *dev, int irq,
3647 struct io_apic_irq_attr *irq_attr)
3648{
3649 int node;
3650
3651 if (!IO_APIC_IRQ(irq)) {
3652 apic_printk(APIC_QUIET,KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n",
3653 irq_attr->ioapic);
3654 return -EINVAL;
3655 }
3656
3657 node = dev ? dev_to_node(dev) : cpu_to_node(0);
3658
3659 return io_apic_setup_irq_pin_once(irq, node, irq_attr);
3660}
3661
3662#ifdef CONFIG_X86_32
3663static int __init io_apic_get_unique_id(int ioapic, int apic_id)
3664{
3665 union IO_APIC_reg_00 reg_00;
3666 static physid_mask_t apic_id_map = PHYSID_MASK_NONE;
3667 physid_mask_t tmp;
3668 unsigned long flags;
3669 int i = 0;
3670
3671 /*
3672 * The P4 platform supports up to 256 APIC IDs on two separate APIC
3673 * buses (one for LAPICs, one for IOAPICs), where predecessors only
3674 * supports up to 16 on one shared APIC bus.
3675 *
3676 * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full
3677 * advantage of new APIC bus architecture.
3678 */
3679
3680 if (physids_empty(apic_id_map))
3681 apic->ioapic_phys_id_map(&phys_cpu_present_map, &apic_id_map);
3682
3683 raw_spin_lock_irqsave(&ioapic_lock, flags);
3684 reg_00.raw = io_apic_read(ioapic, 0);
3685 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
3686
3687 if (apic_id >= get_physical_broadcast()) {
3688 printk(KERN_WARNING "IOAPIC[%d]: Invalid apic_id %d, trying "
3689 "%d\n", ioapic, apic_id, reg_00.bits.ID);
3690 apic_id = reg_00.bits.ID;
3691 }
3692
3693 /*
3694 * Every APIC in a system must have a unique ID or we get lots of nice
3695 * 'stuck on smp_invalidate_needed IPI wait' messages.
3696 */
3697 if (apic->check_apicid_used(&apic_id_map, apic_id)) {
3698
3699 for (i = 0; i < get_physical_broadcast(); i++) {
3700 if (!apic->check_apicid_used(&apic_id_map, i))
3701 break;
3702 }
3703
3704 if (i == get_physical_broadcast())
3705 panic("Max apic_id exceeded!\n");
3706
3707 printk(KERN_WARNING "IOAPIC[%d]: apic_id %d already used, "
3708 "trying %d\n", ioapic, apic_id, i);
3709
3710 apic_id = i;
3711 }
3712
3713 apic->apicid_to_cpu_present(apic_id, &tmp);
3714 physids_or(apic_id_map, apic_id_map, tmp);
3715
3716 if (reg_00.bits.ID != apic_id) {
3717 reg_00.bits.ID = apic_id;
3718
3719 raw_spin_lock_irqsave(&ioapic_lock, flags);
3720 io_apic_write(ioapic, 0, reg_00.raw);
3721 reg_00.raw = io_apic_read(ioapic, 0);
3722 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
3723
3724 /* Sanity check */
3725 if (reg_00.bits.ID != apic_id) {
3726 printk("IOAPIC[%d]: Unable to change apic_id!\n", ioapic);
3727 return -1;
3728 }
3729 }
3730
3731 apic_printk(APIC_VERBOSE, KERN_INFO
3732 "IOAPIC[%d]: Assigned apic_id %d\n", ioapic, apic_id);
3733
3734 return apic_id;
3735}
3736
3737static u8 __init io_apic_unique_id(u8 id)
3738{
3739 if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) &&
3740 !APIC_XAPIC(apic_version[boot_cpu_physical_apicid]))
3741 return io_apic_get_unique_id(nr_ioapics, id);
3742 else
3743 return id;
3744}
3745#else
3746static u8 __init io_apic_unique_id(u8 id)
3747{
3748 int i;
3749 DECLARE_BITMAP(used, 256);
3750
3751 bitmap_zero(used, 256);
3752 for (i = 0; i < nr_ioapics; i++) {
3753 __set_bit(mpc_ioapic_id(i), used);
3754 }
3755 if (!test_bit(id, used))
3756 return id;
3757 return find_first_zero_bit(used, 256);
3758}
3759#endif
3760
3761static int __init io_apic_get_version(int ioapic)
3762{
3763 union IO_APIC_reg_01 reg_01;
3764 unsigned long flags;
3765
3766 raw_spin_lock_irqsave(&ioapic_lock, flags);
3767 reg_01.raw = io_apic_read(ioapic, 1);
3768 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
3769
3770 return reg_01.bits.version;
3771}
3772
3773int acpi_get_override_irq(u32 gsi, int *trigger, int *polarity)
3774{
3775 int ioapic, pin, idx;
3776
3777 if (skip_ioapic_setup)
3778 return -1;
3779
3780 ioapic = mp_find_ioapic(gsi);
3781 if (ioapic < 0)
3782 return -1;
3783
3784 pin = mp_find_ioapic_pin(ioapic, gsi);
3785 if (pin < 0)
3786 return -1;
3787
3788 idx = find_irq_entry(ioapic, pin, mp_INT);
3789 if (idx < 0)
3790 return -1;
3791
3792 *trigger = irq_trigger(idx);
3793 *polarity = irq_polarity(idx);
3794 return 0;
3795}
3796
3797/*
3798 * This function currently is only a helper for the i386 smp boot process where
3799 * we need to reprogram the ioredtbls to cater for the cpus which have come online
3800 * so mask in all cases should simply be apic->target_cpus()
3801 */
3802#ifdef CONFIG_SMP
3803void __init setup_ioapic_dest(void)
3804{
3805 int pin, ioapic, irq, irq_entry;
3806 const struct cpumask *mask;
3807 struct irq_data *idata;
3808
3809 if (skip_ioapic_setup == 1)
3810 return;
3811
3812 for (ioapic = 0; ioapic < nr_ioapics; ioapic++)
3813 for (pin = 0; pin < ioapics[ioapic].nr_registers; pin++) {
3814 irq_entry = find_irq_entry(ioapic, pin, mp_INT);
3815 if (irq_entry == -1)
3816 continue;
3817 irq = pin_2_irq(irq_entry, ioapic, pin);
3818
3819 if ((ioapic > 0) && (irq > 16))
3820 continue;
3821
3822 idata = irq_get_irq_data(irq);
3823
3824 /*
3825 * Honour affinities which have been set in early boot
3826 */
3827 if (!irqd_can_balance(idata) || irqd_affinity_was_set(idata))
3828 mask = idata->affinity;
3829 else
3830 mask = apic->target_cpus();
3831
3832 if (intr_remapping_enabled)
3833 ir_ioapic_set_affinity(idata, mask, false);
3834 else
3835 ioapic_set_affinity(idata, mask, false);
3836 }
3837
3838}
3839#endif
3840
3841#define IOAPIC_RESOURCE_NAME_SIZE 11
3842
3843static struct resource *ioapic_resources;
3844
3845static struct resource * __init ioapic_setup_resources(int nr_ioapics)
3846{
3847 unsigned long n;
3848 struct resource *res;
3849 char *mem;
3850 int i;
3851
3852 if (nr_ioapics <= 0)
3853 return NULL;
3854
3855 n = IOAPIC_RESOURCE_NAME_SIZE + sizeof(struct resource);
3856 n *= nr_ioapics;
3857
3858 mem = alloc_bootmem(n);
3859 res = (void *)mem;
3860
3861 mem += sizeof(struct resource) * nr_ioapics;
3862
3863 for (i = 0; i < nr_ioapics; i++) {
3864 res[i].name = mem;
3865 res[i].flags = IORESOURCE_MEM | IORESOURCE_BUSY;
3866 snprintf(mem, IOAPIC_RESOURCE_NAME_SIZE, "IOAPIC %u", i);
3867 mem += IOAPIC_RESOURCE_NAME_SIZE;
3868 }
3869
3870 ioapic_resources = res;
3871
3872 return res;
3873}
3874
3875void __init ioapic_and_gsi_init(void)
3876{
3877 unsigned long ioapic_phys, idx = FIX_IO_APIC_BASE_0;
3878 struct resource *ioapic_res;
3879 int i;
3880
3881 ioapic_res = ioapic_setup_resources(nr_ioapics);
3882 for (i = 0; i < nr_ioapics; i++) {
3883 if (smp_found_config) {
3884 ioapic_phys = mpc_ioapic_addr(i);
3885#ifdef CONFIG_X86_32
3886 if (!ioapic_phys) {
3887 printk(KERN_ERR
3888 "WARNING: bogus zero IO-APIC "
3889 "address found in MPTABLE, "
3890 "disabling IO/APIC support!\n");
3891 smp_found_config = 0;
3892 skip_ioapic_setup = 1;
3893 goto fake_ioapic_page;
3894 }
3895#endif
3896 } else {
3897#ifdef CONFIG_X86_32
3898fake_ioapic_page:
3899#endif
3900 ioapic_phys = (unsigned long)alloc_bootmem_pages(PAGE_SIZE);
3901 ioapic_phys = __pa(ioapic_phys);
3902 }
3903 set_fixmap_nocache(idx, ioapic_phys);
3904 apic_printk(APIC_VERBOSE, "mapped IOAPIC to %08lx (%08lx)\n",
3905 __fix_to_virt(idx) + (ioapic_phys & ~PAGE_MASK),
3906 ioapic_phys);
3907 idx++;
3908
3909 ioapic_res->start = ioapic_phys;
3910 ioapic_res->end = ioapic_phys + IO_APIC_SLOT_SIZE - 1;
3911 ioapic_res++;
3912 }
3913
3914 probe_nr_irqs_gsi();
3915}
3916
3917void __init ioapic_insert_resources(void)
3918{
3919 int i;
3920 struct resource *r = ioapic_resources;
3921
3922 if (!r) {
3923 if (nr_ioapics > 0)
3924 printk(KERN_ERR
3925 "IO APIC resources couldn't be allocated.\n");
3926 return;
3927 }
3928
3929 for (i = 0; i < nr_ioapics; i++) {
3930 insert_resource(&iomem_resource, r);
3931 r++;
3932 }
3933}
3934
3935int mp_find_ioapic(u32 gsi)
3936{
3937 int i = 0;
3938
3939 if (nr_ioapics == 0)
3940 return -1;
3941
3942 /* Find the IOAPIC that manages this GSI. */
3943 for (i = 0; i < nr_ioapics; i++) {
3944 struct mp_ioapic_gsi *gsi_cfg = mp_ioapic_gsi_routing(i);
3945 if ((gsi >= gsi_cfg->gsi_base)
3946 && (gsi <= gsi_cfg->gsi_end))
3947 return i;
3948 }
3949
3950 printk(KERN_ERR "ERROR: Unable to locate IOAPIC for GSI %d\n", gsi);
3951 return -1;
3952}
3953
3954int mp_find_ioapic_pin(int ioapic, u32 gsi)
3955{
3956 struct mp_ioapic_gsi *gsi_cfg;
3957
3958 if (WARN_ON(ioapic == -1))
3959 return -1;
3960
3961 gsi_cfg = mp_ioapic_gsi_routing(ioapic);
3962 if (WARN_ON(gsi > gsi_cfg->gsi_end))
3963 return -1;
3964
3965 return gsi - gsi_cfg->gsi_base;
3966}
3967
3968static __init int bad_ioapic(unsigned long address)
3969{
3970 if (nr_ioapics >= MAX_IO_APICS) {
3971 printk(KERN_WARNING "WARNING: Max # of I/O APICs (%d) exceeded "
3972 "(found %d), skipping\n", MAX_IO_APICS, nr_ioapics);
3973 return 1;
3974 }
3975 if (!address) {
3976 printk(KERN_WARNING "WARNING: Bogus (zero) I/O APIC address"
3977 " found in table, skipping!\n");
3978 return 1;
3979 }
3980 return 0;
3981}
3982
3983void __init mp_register_ioapic(int id, u32 address, u32 gsi_base)
3984{
3985 int idx = 0;
3986 int entries;
3987 struct mp_ioapic_gsi *gsi_cfg;
3988
3989 if (bad_ioapic(address))
3990 return;
3991
3992 idx = nr_ioapics;
3993
3994 ioapics[idx].mp_config.type = MP_IOAPIC;
3995 ioapics[idx].mp_config.flags = MPC_APIC_USABLE;
3996 ioapics[idx].mp_config.apicaddr = address;
3997
3998 set_fixmap_nocache(FIX_IO_APIC_BASE_0 + idx, address);
3999 ioapics[idx].mp_config.apicid = io_apic_unique_id(id);
4000 ioapics[idx].mp_config.apicver = io_apic_get_version(idx);
4001
4002 /*
4003 * Build basic GSI lookup table to facilitate gsi->io_apic lookups
4004 * and to prevent reprogramming of IOAPIC pins (PCI GSIs).
4005 */
4006 entries = io_apic_get_redir_entries(idx);
4007 gsi_cfg = mp_ioapic_gsi_routing(idx);
4008 gsi_cfg->gsi_base = gsi_base;
4009 gsi_cfg->gsi_end = gsi_base + entries - 1;
4010
4011 /*
4012 * The number of IO-APIC IRQ registers (== #pins):
4013 */
4014 ioapics[idx].nr_registers = entries;
4015
4016 if (gsi_cfg->gsi_end >= gsi_top)
4017 gsi_top = gsi_cfg->gsi_end + 1;
4018
4019 printk(KERN_INFO "IOAPIC[%d]: apic_id %d, version %d, address 0x%x, "
4020 "GSI %d-%d\n", idx, mpc_ioapic_id(idx),
4021 mpc_ioapic_ver(idx), mpc_ioapic_addr(idx),
4022 gsi_cfg->gsi_base, gsi_cfg->gsi_end);
4023
4024 nr_ioapics++;
4025}
4026
4027/* Enable IOAPIC early just for system timer */
4028void __init pre_init_apic_IRQ0(void)
4029{
4030 struct io_apic_irq_attr attr = { 0, 0, 0, 0 };
4031
4032 printk(KERN_INFO "Early APIC setup for system timer0\n");
4033#ifndef CONFIG_SMP
4034 physid_set_mask_of_physid(boot_cpu_physical_apicid,
4035 &phys_cpu_present_map);
4036#endif
4037 setup_local_APIC();
4038
4039 io_apic_setup_irq_pin(0, 0, &attr);
4040 irq_set_chip_and_handler_name(0, &ioapic_chip, handle_edge_irq,
4041 "edge");
4042}