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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Intel IO-APIC support for multi-Pentium hosts.
4 *
5 * Copyright (C) 1997, 1998, 1999, 2000, 2009 Ingo Molnar, Hajnalka Szabo
6 *
7 * Many thanks to Stig Venaas for trying out countless experimental
8 * patches and reporting/debugging problems patiently!
9 *
10 * (c) 1999, Multiple IO-APIC support, developed by
11 * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
12 * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
13 * further tested and cleaned up by Zach Brown <zab@redhat.com>
14 * and Ingo Molnar <mingo@redhat.com>
15 *
16 * Fixes
17 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
18 * thanks to Eric Gilmore
19 * and Rolf G. Tews
20 * for testing these extensively
21 * Paul Diefenbaugh : Added full ACPI support
22 *
23 * Historical information which is worth to be preserved:
24 *
25 * - SiS APIC rmw bug:
26 *
27 * We used to have a workaround for a bug in SiS chips which
28 * required to rewrite the index register for a read-modify-write
29 * operation as the chip lost the index information which was
30 * setup for the read already. We cache the data now, so that
31 * workaround has been removed.
32 */
33
34#include <linux/mm.h>
35#include <linux/interrupt.h>
36#include <linux/irq.h>
37#include <linux/init.h>
38#include <linux/delay.h>
39#include <linux/sched.h>
40#include <linux/pci.h>
41#include <linux/mc146818rtc.h>
42#include <linux/compiler.h>
43#include <linux/acpi.h>
44#include <linux/export.h>
45#include <linux/syscore_ops.h>
46#include <linux/freezer.h>
47#include <linux/kthread.h>
48#include <linux/jiffies.h> /* time_after() */
49#include <linux/slab.h>
50#include <linux/memblock.h>
51#include <linux/msi.h>
52
53#include <asm/irqdomain.h>
54#include <asm/io.h>
55#include <asm/smp.h>
56#include <asm/cpu.h>
57#include <asm/desc.h>
58#include <asm/proto.h>
59#include <asm/acpi.h>
60#include <asm/dma.h>
61#include <asm/timer.h>
62#include <asm/time.h>
63#include <asm/i8259.h>
64#include <asm/setup.h>
65#include <asm/irq_remapping.h>
66#include <asm/hw_irq.h>
67#include <asm/apic.h>
68#include <asm/pgtable.h>
69#include <asm/x86_init.h>
70
71#define for_each_ioapic(idx) \
72 for ((idx) = 0; (idx) < nr_ioapics; (idx)++)
73#define for_each_ioapic_reverse(idx) \
74 for ((idx) = nr_ioapics - 1; (idx) >= 0; (idx)--)
75#define for_each_pin(idx, pin) \
76 for ((pin) = 0; (pin) < ioapics[(idx)].nr_registers; (pin)++)
77#define for_each_ioapic_pin(idx, pin) \
78 for_each_ioapic((idx)) \
79 for_each_pin((idx), (pin))
80#define for_each_irq_pin(entry, head) \
81 list_for_each_entry(entry, &head, list)
82
83static DEFINE_RAW_SPINLOCK(ioapic_lock);
84static DEFINE_MUTEX(ioapic_mutex);
85static unsigned int ioapic_dynirq_base;
86static int ioapic_initialized;
87
88struct irq_pin_list {
89 struct list_head list;
90 int apic, pin;
91};
92
93struct mp_chip_data {
94 struct list_head irq_2_pin;
95 struct IO_APIC_route_entry entry;
96 bool is_level;
97 bool active_low;
98 bool isa_irq;
99 u32 count;
100};
101
102struct mp_ioapic_gsi {
103 u32 gsi_base;
104 u32 gsi_end;
105};
106
107static struct ioapic {
108 /* # of IRQ routing registers */
109 int nr_registers;
110 /* Saved state during suspend/resume, or while enabling intr-remap. */
111 struct IO_APIC_route_entry *saved_registers;
112 /* I/O APIC config */
113 struct mpc_ioapic mp_config;
114 /* IO APIC gsi routing info */
115 struct mp_ioapic_gsi gsi_config;
116 struct ioapic_domain_cfg irqdomain_cfg;
117 struct irq_domain *irqdomain;
118 struct resource *iomem_res;
119} ioapics[MAX_IO_APICS];
120
121#define mpc_ioapic_ver(ioapic_idx) ioapics[ioapic_idx].mp_config.apicver
122
123int mpc_ioapic_id(int ioapic_idx)
124{
125 return ioapics[ioapic_idx].mp_config.apicid;
126}
127
128unsigned int mpc_ioapic_addr(int ioapic_idx)
129{
130 return ioapics[ioapic_idx].mp_config.apicaddr;
131}
132
133static inline struct mp_ioapic_gsi *mp_ioapic_gsi_routing(int ioapic_idx)
134{
135 return &ioapics[ioapic_idx].gsi_config;
136}
137
138static inline int mp_ioapic_pin_count(int ioapic)
139{
140 struct mp_ioapic_gsi *gsi_cfg = mp_ioapic_gsi_routing(ioapic);
141
142 return gsi_cfg->gsi_end - gsi_cfg->gsi_base + 1;
143}
144
145static inline u32 mp_pin_to_gsi(int ioapic, int pin)
146{
147 return mp_ioapic_gsi_routing(ioapic)->gsi_base + pin;
148}
149
150static inline bool mp_is_legacy_irq(int irq)
151{
152 return irq >= 0 && irq < nr_legacy_irqs();
153}
154
155static inline struct irq_domain *mp_ioapic_irqdomain(int ioapic)
156{
157 return ioapics[ioapic].irqdomain;
158}
159
160int nr_ioapics;
161
162/* The one past the highest gsi number used */
163u32 gsi_top;
164
165/* MP IRQ source entries */
166struct mpc_intsrc mp_irqs[MAX_IRQ_SOURCES];
167
168/* # of MP IRQ source entries */
169int mp_irq_entries;
170
171#ifdef CONFIG_EISA
172int mp_bus_id_to_type[MAX_MP_BUSSES];
173#endif
174
175DECLARE_BITMAP(mp_bus_not_pci, MAX_MP_BUSSES);
176
177bool ioapic_is_disabled __ro_after_init;
178
179/**
180 * disable_ioapic_support() - disables ioapic support at runtime
181 */
182void disable_ioapic_support(void)
183{
184#ifdef CONFIG_PCI
185 noioapicquirk = 1;
186 noioapicreroute = -1;
187#endif
188 ioapic_is_disabled = true;
189}
190
191static int __init parse_noapic(char *str)
192{
193 /* disable IO-APIC */
194 disable_ioapic_support();
195 return 0;
196}
197early_param("noapic", parse_noapic);
198
199/* Will be called in mpparse/ACPI codes for saving IRQ info */
200void mp_save_irq(struct mpc_intsrc *m)
201{
202 int i;
203
204 apic_pr_verbose("Int: type %d, pol %d, trig %d, bus %02x, IRQ %02x, APIC ID %x, APIC INT %02x\n",
205 m->irqtype, m->irqflag & 3, (m->irqflag >> 2) & 3, m->srcbus,
206 m->srcbusirq, m->dstapic, m->dstirq);
207
208 for (i = 0; i < mp_irq_entries; i++) {
209 if (!memcmp(&mp_irqs[i], m, sizeof(*m)))
210 return;
211 }
212
213 memcpy(&mp_irqs[mp_irq_entries], m, sizeof(*m));
214 if (++mp_irq_entries == MAX_IRQ_SOURCES)
215 panic("Max # of irq sources exceeded!!\n");
216}
217
218static void alloc_ioapic_saved_registers(int idx)
219{
220 size_t size;
221
222 if (ioapics[idx].saved_registers)
223 return;
224
225 size = sizeof(struct IO_APIC_route_entry) * ioapics[idx].nr_registers;
226 ioapics[idx].saved_registers = kzalloc(size, GFP_KERNEL);
227 if (!ioapics[idx].saved_registers)
228 pr_err("IOAPIC %d: suspend/resume impossible!\n", idx);
229}
230
231static void free_ioapic_saved_registers(int idx)
232{
233 kfree(ioapics[idx].saved_registers);
234 ioapics[idx].saved_registers = NULL;
235}
236
237int __init arch_early_ioapic_init(void)
238{
239 int i;
240
241 if (!nr_legacy_irqs())
242 io_apic_irqs = ~0UL;
243
244 for_each_ioapic(i)
245 alloc_ioapic_saved_registers(i);
246
247 return 0;
248}
249
250struct io_apic {
251 unsigned int index;
252 unsigned int unused[3];
253 unsigned int data;
254 unsigned int unused2[11];
255 unsigned int eoi;
256};
257
258static __attribute_const__ struct io_apic __iomem *io_apic_base(int idx)
259{
260 return (void __iomem *) __fix_to_virt(FIX_IO_APIC_BASE_0 + idx)
261 + (mpc_ioapic_addr(idx) & ~PAGE_MASK);
262}
263
264static inline void io_apic_eoi(unsigned int apic, unsigned int vector)
265{
266 struct io_apic __iomem *io_apic = io_apic_base(apic);
267
268 writel(vector, &io_apic->eoi);
269}
270
271unsigned int native_io_apic_read(unsigned int apic, unsigned int reg)
272{
273 struct io_apic __iomem *io_apic = io_apic_base(apic);
274
275 writel(reg, &io_apic->index);
276 return readl(&io_apic->data);
277}
278
279static void io_apic_write(unsigned int apic, unsigned int reg,
280 unsigned int value)
281{
282 struct io_apic __iomem *io_apic = io_apic_base(apic);
283
284 writel(reg, &io_apic->index);
285 writel(value, &io_apic->data);
286}
287
288static struct IO_APIC_route_entry __ioapic_read_entry(int apic, int pin)
289{
290 struct IO_APIC_route_entry entry;
291
292 entry.w1 = io_apic_read(apic, 0x10 + 2 * pin);
293 entry.w2 = io_apic_read(apic, 0x11 + 2 * pin);
294
295 return entry;
296}
297
298static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin)
299{
300 guard(raw_spinlock_irqsave)(&ioapic_lock);
301 return __ioapic_read_entry(apic, pin);
302}
303
304/*
305 * When we write a new IO APIC routing entry, we need to write the high
306 * word first! If the mask bit in the low word is clear, we will enable
307 * the interrupt, and we need to make sure the entry is fully populated
308 * before that happens.
309 */
310static void __ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
311{
312 io_apic_write(apic, 0x11 + 2*pin, e.w2);
313 io_apic_write(apic, 0x10 + 2*pin, e.w1);
314}
315
316static void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
317{
318 guard(raw_spinlock_irqsave)(&ioapic_lock);
319 __ioapic_write_entry(apic, pin, e);
320}
321
322/*
323 * When we mask an IO APIC routing entry, we need to write the low
324 * word first, in order to set the mask bit before we change the
325 * high bits!
326 */
327static void ioapic_mask_entry(int apic, int pin)
328{
329 struct IO_APIC_route_entry e = { .masked = true };
330
331 guard(raw_spinlock_irqsave)(&ioapic_lock);
332 io_apic_write(apic, 0x10 + 2*pin, e.w1);
333 io_apic_write(apic, 0x11 + 2*pin, e.w2);
334}
335
336/*
337 * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
338 * shared ISA-space IRQs, so we have to support them. We are super
339 * fast in the common case, and fast for shared ISA-space IRQs.
340 */
341static bool add_pin_to_irq_node(struct mp_chip_data *data, int node, int apic, int pin)
342{
343 struct irq_pin_list *entry;
344
345 /* Don't allow duplicates */
346 for_each_irq_pin(entry, data->irq_2_pin) {
347 if (entry->apic == apic && entry->pin == pin)
348 return true;
349 }
350
351 entry = kzalloc_node(sizeof(struct irq_pin_list), GFP_ATOMIC, node);
352 if (!entry) {
353 pr_err("Cannot allocate irq_pin_list (%d,%d,%d)\n", node, apic, pin);
354 return false;
355 }
356
357 entry->apic = apic;
358 entry->pin = pin;
359 list_add_tail(&entry->list, &data->irq_2_pin);
360 return true;
361}
362
363static void __remove_pin_from_irq(struct mp_chip_data *data, int apic, int pin)
364{
365 struct irq_pin_list *tmp, *entry;
366
367 list_for_each_entry_safe(entry, tmp, &data->irq_2_pin, list) {
368 if (entry->apic == apic && entry->pin == pin) {
369 list_del(&entry->list);
370 kfree(entry);
371 return;
372 }
373 }
374}
375
376static void io_apic_modify_irq(struct mp_chip_data *data, bool masked,
377 void (*final)(struct irq_pin_list *entry))
378{
379 struct irq_pin_list *entry;
380
381 data->entry.masked = masked;
382
383 for_each_irq_pin(entry, data->irq_2_pin) {
384 io_apic_write(entry->apic, 0x10 + 2 * entry->pin, data->entry.w1);
385 if (final)
386 final(entry);
387 }
388}
389
390/*
391 * Synchronize the IO-APIC and the CPU by doing a dummy read from the
392 * IO-APIC
393 */
394static void io_apic_sync(struct irq_pin_list *entry)
395{
396 struct io_apic __iomem *io_apic;
397
398 io_apic = io_apic_base(entry->apic);
399 readl(&io_apic->data);
400}
401
402static void mask_ioapic_irq(struct irq_data *irq_data)
403{
404 struct mp_chip_data *data = irq_data->chip_data;
405
406 guard(raw_spinlock_irqsave)(&ioapic_lock);
407 io_apic_modify_irq(data, true, &io_apic_sync);
408}
409
410static void __unmask_ioapic(struct mp_chip_data *data)
411{
412 io_apic_modify_irq(data, false, NULL);
413}
414
415static void unmask_ioapic_irq(struct irq_data *irq_data)
416{
417 struct mp_chip_data *data = irq_data->chip_data;
418
419 guard(raw_spinlock_irqsave)(&ioapic_lock);
420 __unmask_ioapic(data);
421}
422
423/*
424 * IO-APIC versions below 0x20 don't support EOI register.
425 * For the record, here is the information about various versions:
426 * 0Xh 82489DX
427 * 1Xh I/OAPIC or I/O(x)APIC which are not PCI 2.2 Compliant
428 * 2Xh I/O(x)APIC which is PCI 2.2 Compliant
429 * 30h-FFh Reserved
430 *
431 * Some of the Intel ICH Specs (ICH2 to ICH5) documents the io-apic
432 * version as 0x2. This is an error with documentation and these ICH chips
433 * use io-apic's of version 0x20.
434 *
435 * For IO-APIC's with EOI register, we use that to do an explicit EOI.
436 * Otherwise, we simulate the EOI message manually by changing the trigger
437 * mode to edge and then back to level, with RTE being masked during this.
438 */
439static void __eoi_ioapic_pin(int apic, int pin, int vector)
440{
441 if (mpc_ioapic_ver(apic) >= 0x20) {
442 io_apic_eoi(apic, vector);
443 } else {
444 struct IO_APIC_route_entry entry, entry1;
445
446 entry = entry1 = __ioapic_read_entry(apic, pin);
447
448 /* Mask the entry and change the trigger mode to edge. */
449 entry1.masked = true;
450 entry1.is_level = false;
451
452 __ioapic_write_entry(apic, pin, entry1);
453
454 /* Restore the previous level triggered entry. */
455 __ioapic_write_entry(apic, pin, entry);
456 }
457}
458
459static void eoi_ioapic_pin(int vector, struct mp_chip_data *data)
460{
461 struct irq_pin_list *entry;
462
463 guard(raw_spinlock_irqsave)(&ioapic_lock);
464 for_each_irq_pin(entry, data->irq_2_pin)
465 __eoi_ioapic_pin(entry->apic, entry->pin, vector);
466}
467
468static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
469{
470 struct IO_APIC_route_entry entry;
471
472 /* Check delivery_mode to be sure we're not clearing an SMI pin */
473 entry = ioapic_read_entry(apic, pin);
474 if (entry.delivery_mode == APIC_DELIVERY_MODE_SMI)
475 return;
476
477 /*
478 * Make sure the entry is masked and re-read the contents to check
479 * if it is a level triggered pin and if the remote-IRR is set.
480 */
481 if (!entry.masked) {
482 entry.masked = true;
483 ioapic_write_entry(apic, pin, entry);
484 entry = ioapic_read_entry(apic, pin);
485 }
486
487 if (entry.irr) {
488 /*
489 * Make sure the trigger mode is set to level. Explicit EOI
490 * doesn't clear the remote-IRR if the trigger mode is not
491 * set to level.
492 */
493 if (!entry.is_level) {
494 entry.is_level = true;
495 ioapic_write_entry(apic, pin, entry);
496 }
497 guard(raw_spinlock_irqsave)(&ioapic_lock);
498 __eoi_ioapic_pin(apic, pin, entry.vector);
499 }
500
501 /*
502 * Clear the rest of the bits in the IO-APIC RTE except for the mask
503 * bit.
504 */
505 ioapic_mask_entry(apic, pin);
506 entry = ioapic_read_entry(apic, pin);
507 if (entry.irr)
508 pr_err("Unable to reset IRR for apic: %d, pin :%d\n",
509 mpc_ioapic_id(apic), pin);
510}
511
512void clear_IO_APIC (void)
513{
514 int apic, pin;
515
516 for_each_ioapic_pin(apic, pin)
517 clear_IO_APIC_pin(apic, pin);
518}
519
520#ifdef CONFIG_X86_32
521/*
522 * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to
523 * specific CPU-side IRQs.
524 */
525
526#define MAX_PIRQS 8
527static int pirq_entries[MAX_PIRQS] = {
528 [0 ... MAX_PIRQS - 1] = -1
529};
530
531static int __init ioapic_pirq_setup(char *str)
532{
533 int i, max, ints[MAX_PIRQS+1];
534
535 get_options(str, ARRAY_SIZE(ints), ints);
536
537 apic_pr_verbose("PIRQ redirection, working around broken MP-BIOS.\n");
538
539 max = MAX_PIRQS;
540 if (ints[0] < MAX_PIRQS)
541 max = ints[0];
542
543 for (i = 0; i < max; i++) {
544 apic_pr_verbose("... PIRQ%d -> IRQ %d\n", i, ints[i + 1]);
545 /* PIRQs are mapped upside down, usually */
546 pirq_entries[MAX_PIRQS-i-1] = ints[i+1];
547 }
548 return 1;
549}
550__setup("pirq=", ioapic_pirq_setup);
551#endif /* CONFIG_X86_32 */
552
553/*
554 * Saves all the IO-APIC RTE's
555 */
556int save_ioapic_entries(void)
557{
558 int apic, pin;
559 int err = 0;
560
561 for_each_ioapic(apic) {
562 if (!ioapics[apic].saved_registers) {
563 err = -ENOMEM;
564 continue;
565 }
566
567 for_each_pin(apic, pin)
568 ioapics[apic].saved_registers[pin] = ioapic_read_entry(apic, pin);
569 }
570
571 return err;
572}
573
574/*
575 * Mask all IO APIC entries.
576 */
577void mask_ioapic_entries(void)
578{
579 int apic, pin;
580
581 for_each_ioapic(apic) {
582 if (!ioapics[apic].saved_registers)
583 continue;
584
585 for_each_pin(apic, pin) {
586 struct IO_APIC_route_entry entry;
587
588 entry = ioapics[apic].saved_registers[pin];
589 if (!entry.masked) {
590 entry.masked = true;
591 ioapic_write_entry(apic, pin, entry);
592 }
593 }
594 }
595}
596
597/*
598 * Restore IO APIC entries which was saved in the ioapic structure.
599 */
600int restore_ioapic_entries(void)
601{
602 int apic, pin;
603
604 for_each_ioapic(apic) {
605 if (!ioapics[apic].saved_registers)
606 continue;
607
608 for_each_pin(apic, pin)
609 ioapic_write_entry(apic, pin, ioapics[apic].saved_registers[pin]);
610 }
611 return 0;
612}
613
614/*
615 * Find the IRQ entry number of a certain pin.
616 */
617static int find_irq_entry(int ioapic_idx, int pin, int type)
618{
619 int i;
620
621 for (i = 0; i < mp_irq_entries; i++) {
622 if (mp_irqs[i].irqtype == type &&
623 (mp_irqs[i].dstapic == mpc_ioapic_id(ioapic_idx) ||
624 mp_irqs[i].dstapic == MP_APIC_ALL) &&
625 mp_irqs[i].dstirq == pin)
626 return i;
627 }
628
629 return -1;
630}
631
632/*
633 * Find the pin to which IRQ[irq] (ISA) is connected
634 */
635static int __init find_isa_irq_pin(int irq, int type)
636{
637 int i;
638
639 for (i = 0; i < mp_irq_entries; i++) {
640 int lbus = mp_irqs[i].srcbus;
641
642 if (test_bit(lbus, mp_bus_not_pci) && (mp_irqs[i].irqtype == type) &&
643 (mp_irqs[i].srcbusirq == irq))
644 return mp_irqs[i].dstirq;
645 }
646 return -1;
647}
648
649static int __init find_isa_irq_apic(int irq, int type)
650{
651 int i;
652
653 for (i = 0; i < mp_irq_entries; i++) {
654 int lbus = mp_irqs[i].srcbus;
655
656 if (test_bit(lbus, mp_bus_not_pci) && (mp_irqs[i].irqtype == type) &&
657 (mp_irqs[i].srcbusirq == irq))
658 break;
659 }
660
661 if (i < mp_irq_entries) {
662 int ioapic_idx;
663
664 for_each_ioapic(ioapic_idx) {
665 if (mpc_ioapic_id(ioapic_idx) == mp_irqs[i].dstapic)
666 return ioapic_idx;
667 }
668 }
669
670 return -1;
671}
672
673static bool irq_active_low(int idx)
674{
675 int bus = mp_irqs[idx].srcbus;
676
677 /*
678 * Determine IRQ line polarity (high active or low active):
679 */
680 switch (mp_irqs[idx].irqflag & MP_IRQPOL_MASK) {
681 case MP_IRQPOL_DEFAULT:
682 /*
683 * Conforms to spec, ie. bus-type dependent polarity. PCI
684 * defaults to low active. [E]ISA defaults to high active.
685 */
686 return !test_bit(bus, mp_bus_not_pci);
687 case MP_IRQPOL_ACTIVE_HIGH:
688 return false;
689 case MP_IRQPOL_RESERVED:
690 pr_warn("IOAPIC: Invalid polarity: 2, defaulting to low\n");
691 fallthrough;
692 case MP_IRQPOL_ACTIVE_LOW:
693 default: /* Pointless default required due to do gcc stupidity */
694 return true;
695 }
696}
697
698#ifdef CONFIG_EISA
699/*
700 * EISA Edge/Level control register, ELCR
701 */
702static bool EISA_ELCR(unsigned int irq)
703{
704 if (irq < nr_legacy_irqs()) {
705 unsigned int port = PIC_ELCR1 + (irq >> 3);
706 return (inb(port) >> (irq & 7)) & 1;
707 }
708 apic_pr_verbose("Broken MPtable reports ISA irq %d\n", irq);
709 return false;
710}
711
712/*
713 * EISA interrupts are always active high and can be edge or level
714 * triggered depending on the ELCR value. If an interrupt is listed as
715 * EISA conforming in the MP table, that means its trigger type must be
716 * read in from the ELCR.
717 */
718static bool eisa_irq_is_level(int idx, int bus, bool level)
719{
720 switch (mp_bus_id_to_type[bus]) {
721 case MP_BUS_PCI:
722 case MP_BUS_ISA:
723 return level;
724 case MP_BUS_EISA:
725 return EISA_ELCR(mp_irqs[idx].srcbusirq);
726 }
727 pr_warn("IOAPIC: Invalid srcbus: %d defaulting to level\n", bus);
728 return true;
729}
730#else
731static inline int eisa_irq_is_level(int idx, int bus, bool level)
732{
733 return level;
734}
735#endif
736
737static bool irq_is_level(int idx)
738{
739 int bus = mp_irqs[idx].srcbus;
740 bool level;
741
742 /*
743 * Determine IRQ trigger mode (edge or level sensitive):
744 */
745 switch (mp_irqs[idx].irqflag & MP_IRQTRIG_MASK) {
746 case MP_IRQTRIG_DEFAULT:
747 /*
748 * Conforms to spec, ie. bus-type dependent trigger
749 * mode. PCI defaults to level, ISA to edge.
750 */
751 level = !test_bit(bus, mp_bus_not_pci);
752 /* Take EISA into account */
753 return eisa_irq_is_level(idx, bus, level);
754 case MP_IRQTRIG_EDGE:
755 return false;
756 case MP_IRQTRIG_RESERVED:
757 pr_warn("IOAPIC: Invalid trigger mode 2 defaulting to level\n");
758 fallthrough;
759 case MP_IRQTRIG_LEVEL:
760 default: /* Pointless default required due to do gcc stupidity */
761 return true;
762 }
763}
764
765static int __acpi_get_override_irq(u32 gsi, bool *trigger, bool *polarity)
766{
767 int ioapic, pin, idx;
768
769 if (ioapic_is_disabled)
770 return -1;
771
772 ioapic = mp_find_ioapic(gsi);
773 if (ioapic < 0)
774 return -1;
775
776 pin = mp_find_ioapic_pin(ioapic, gsi);
777 if (pin < 0)
778 return -1;
779
780 idx = find_irq_entry(ioapic, pin, mp_INT);
781 if (idx < 0)
782 return -1;
783
784 *trigger = irq_is_level(idx);
785 *polarity = irq_active_low(idx);
786 return 0;
787}
788
789#ifdef CONFIG_ACPI
790int acpi_get_override_irq(u32 gsi, int *is_level, int *active_low)
791{
792 *is_level = *active_low = 0;
793 return __acpi_get_override_irq(gsi, (bool *)is_level,
794 (bool *)active_low);
795}
796#endif
797
798void ioapic_set_alloc_attr(struct irq_alloc_info *info, int node,
799 int trigger, int polarity)
800{
801 init_irq_alloc_info(info, NULL);
802 info->type = X86_IRQ_ALLOC_TYPE_IOAPIC;
803 info->ioapic.node = node;
804 info->ioapic.is_level = trigger;
805 info->ioapic.active_low = polarity;
806 info->ioapic.valid = 1;
807}
808
809static void ioapic_copy_alloc_attr(struct irq_alloc_info *dst,
810 struct irq_alloc_info *src,
811 u32 gsi, int ioapic_idx, int pin)
812{
813 bool level, pol_low;
814
815 copy_irq_alloc_info(dst, src);
816 dst->type = X86_IRQ_ALLOC_TYPE_IOAPIC;
817 dst->devid = mpc_ioapic_id(ioapic_idx);
818 dst->ioapic.pin = pin;
819 dst->ioapic.valid = 1;
820 if (src && src->ioapic.valid) {
821 dst->ioapic.node = src->ioapic.node;
822 dst->ioapic.is_level = src->ioapic.is_level;
823 dst->ioapic.active_low = src->ioapic.active_low;
824 } else {
825 dst->ioapic.node = NUMA_NO_NODE;
826 if (__acpi_get_override_irq(gsi, &level, &pol_low) >= 0) {
827 dst->ioapic.is_level = level;
828 dst->ioapic.active_low = pol_low;
829 } else {
830 /*
831 * PCI interrupts are always active low level
832 * triggered.
833 */
834 dst->ioapic.is_level = true;
835 dst->ioapic.active_low = true;
836 }
837 }
838}
839
840static int ioapic_alloc_attr_node(struct irq_alloc_info *info)
841{
842 return (info && info->ioapic.valid) ? info->ioapic.node : NUMA_NO_NODE;
843}
844
845static void mp_register_handler(unsigned int irq, bool level)
846{
847 irq_flow_handler_t hdl;
848 bool fasteoi;
849
850 if (level) {
851 irq_set_status_flags(irq, IRQ_LEVEL);
852 fasteoi = true;
853 } else {
854 irq_clear_status_flags(irq, IRQ_LEVEL);
855 fasteoi = false;
856 }
857
858 hdl = fasteoi ? handle_fasteoi_irq : handle_edge_irq;
859 __irq_set_handler(irq, hdl, 0, fasteoi ? "fasteoi" : "edge");
860}
861
862static bool mp_check_pin_attr(int irq, struct irq_alloc_info *info)
863{
864 struct mp_chip_data *data = irq_get_chip_data(irq);
865
866 /*
867 * setup_IO_APIC_irqs() programs all legacy IRQs with default trigger
868 * and polarity attributes. So allow the first user to reprogram the
869 * pin with real trigger and polarity attributes.
870 */
871 if (irq < nr_legacy_irqs() && data->count == 1) {
872 if (info->ioapic.is_level != data->is_level)
873 mp_register_handler(irq, info->ioapic.is_level);
874 data->entry.is_level = data->is_level = info->ioapic.is_level;
875 data->entry.active_low = data->active_low = info->ioapic.active_low;
876 }
877
878 return data->is_level == info->ioapic.is_level &&
879 data->active_low == info->ioapic.active_low;
880}
881
882static int alloc_irq_from_domain(struct irq_domain *domain, int ioapic, u32 gsi,
883 struct irq_alloc_info *info)
884{
885 int type = ioapics[ioapic].irqdomain_cfg.type;
886 bool legacy = false;
887 int irq = -1;
888
889 switch (type) {
890 case IOAPIC_DOMAIN_LEGACY:
891 /*
892 * Dynamically allocate IRQ number for non-ISA IRQs in the first
893 * 16 GSIs on some weird platforms.
894 */
895 if (!ioapic_initialized || gsi >= nr_legacy_irqs())
896 irq = gsi;
897 legacy = mp_is_legacy_irq(irq);
898 break;
899 case IOAPIC_DOMAIN_STRICT:
900 irq = gsi;
901 break;
902 case IOAPIC_DOMAIN_DYNAMIC:
903 break;
904 default:
905 WARN(1, "ioapic: unknown irqdomain type %d\n", type);
906 return -1;
907 }
908
909 return __irq_domain_alloc_irqs(domain, irq, 1, ioapic_alloc_attr_node(info),
910 info, legacy, NULL);
911}
912
913/*
914 * Need special handling for ISA IRQs because there may be multiple IOAPIC pins
915 * sharing the same ISA IRQ number and irqdomain only supports 1:1 mapping
916 * between IOAPIC pin and IRQ number. A typical IOAPIC has 24 pins, pin 0-15 are
917 * used for legacy IRQs and pin 16-23 are used for PCI IRQs (PIRQ A-H).
918 * When ACPI is disabled, only legacy IRQ numbers (IRQ0-15) are available, and
919 * some BIOSes may use MP Interrupt Source records to override IRQ numbers for
920 * PIRQs instead of reprogramming the interrupt routing logic. Thus there may be
921 * multiple pins sharing the same legacy IRQ number when ACPI is disabled.
922 */
923static int alloc_isa_irq_from_domain(struct irq_domain *domain, int irq, int ioapic, int pin,
924 struct irq_alloc_info *info)
925{
926 struct irq_data *irq_data = irq_get_irq_data(irq);
927 int node = ioapic_alloc_attr_node(info);
928 struct mp_chip_data *data;
929
930 /*
931 * Legacy ISA IRQ has already been allocated, just add pin to
932 * the pin list associated with this IRQ and program the IOAPIC
933 * entry.
934 */
935 if (irq_data && irq_data->parent_data) {
936 if (!mp_check_pin_attr(irq, info))
937 return -EBUSY;
938 if (!add_pin_to_irq_node(irq_data->chip_data, node, ioapic, info->ioapic.pin))
939 return -ENOMEM;
940 } else {
941 info->flags |= X86_IRQ_ALLOC_LEGACY;
942 irq = __irq_domain_alloc_irqs(domain, irq, 1, node, info, true, NULL);
943 if (irq >= 0) {
944 irq_data = irq_domain_get_irq_data(domain, irq);
945 data = irq_data->chip_data;
946 data->isa_irq = true;
947 }
948 }
949
950 return irq;
951}
952
953static int mp_map_pin_to_irq(u32 gsi, int idx, int ioapic, int pin,
954 unsigned int flags, struct irq_alloc_info *info)
955{
956 struct irq_domain *domain = mp_ioapic_irqdomain(ioapic);
957 struct irq_alloc_info tmp;
958 struct mp_chip_data *data;
959 bool legacy = false;
960 int irq;
961
962 if (!domain)
963 return -ENOSYS;
964
965 if (idx >= 0 && test_bit(mp_irqs[idx].srcbus, mp_bus_not_pci)) {
966 irq = mp_irqs[idx].srcbusirq;
967 legacy = mp_is_legacy_irq(irq);
968 /*
969 * IRQ2 is unusable for historical reasons on systems which
970 * have a legacy PIC. See the comment vs. IRQ2 further down.
971 *
972 * If this gets removed at some point then the related code
973 * in lapic_assign_system_vectors() needs to be adjusted as
974 * well.
975 */
976 if (legacy && irq == PIC_CASCADE_IR)
977 return -EINVAL;
978 }
979
980 guard(mutex)(&ioapic_mutex);
981 if (!(flags & IOAPIC_MAP_ALLOC)) {
982 if (!legacy) {
983 irq = irq_find_mapping(domain, pin);
984 if (irq == 0)
985 irq = -ENOENT;
986 }
987 } else {
988 ioapic_copy_alloc_attr(&tmp, info, gsi, ioapic, pin);
989 if (legacy)
990 irq = alloc_isa_irq_from_domain(domain, irq,
991 ioapic, pin, &tmp);
992 else if ((irq = irq_find_mapping(domain, pin)) == 0)
993 irq = alloc_irq_from_domain(domain, ioapic, gsi, &tmp);
994 else if (!mp_check_pin_attr(irq, &tmp))
995 irq = -EBUSY;
996 if (irq >= 0) {
997 data = irq_get_chip_data(irq);
998 data->count++;
999 }
1000 }
1001 return irq;
1002}
1003
1004static int pin_2_irq(int idx, int ioapic, int pin, unsigned int flags)
1005{
1006 u32 gsi = mp_pin_to_gsi(ioapic, pin);
1007
1008 /* Debugging check, we are in big trouble if this message pops up! */
1009 if (mp_irqs[idx].dstirq != pin)
1010 pr_err("broken BIOS or MPTABLE parser, ayiee!!\n");
1011
1012#ifdef CONFIG_X86_32
1013 /* PCI IRQ command line redirection. Yes, limits are hardcoded. */
1014 if ((pin >= 16) && (pin <= 23)) {
1015 if (pirq_entries[pin - 16] != -1) {
1016 if (!pirq_entries[pin - 16]) {
1017 apic_pr_verbose("Disabling PIRQ%d\n", pin - 16);
1018 } else {
1019 int irq = pirq_entries[pin-16];
1020
1021 apic_pr_verbose("Using PIRQ%d -> IRQ %d\n", pin - 16, irq);
1022 return irq;
1023 }
1024 }
1025 }
1026#endif
1027
1028 return mp_map_pin_to_irq(gsi, idx, ioapic, pin, flags, NULL);
1029}
1030
1031int mp_map_gsi_to_irq(u32 gsi, unsigned int flags, struct irq_alloc_info *info)
1032{
1033 int ioapic, pin, idx;
1034
1035 ioapic = mp_find_ioapic(gsi);
1036 if (ioapic < 0)
1037 return -ENODEV;
1038
1039 pin = mp_find_ioapic_pin(ioapic, gsi);
1040 idx = find_irq_entry(ioapic, pin, mp_INT);
1041 if ((flags & IOAPIC_MAP_CHECK) && idx < 0)
1042 return -ENODEV;
1043
1044 return mp_map_pin_to_irq(gsi, idx, ioapic, pin, flags, info);
1045}
1046
1047void mp_unmap_irq(int irq)
1048{
1049 struct irq_data *irq_data = irq_get_irq_data(irq);
1050 struct mp_chip_data *data;
1051
1052 if (!irq_data || !irq_data->domain)
1053 return;
1054
1055 data = irq_data->chip_data;
1056 if (!data || data->isa_irq)
1057 return;
1058
1059 guard(mutex)(&ioapic_mutex);
1060 if (--data->count == 0)
1061 irq_domain_free_irqs(irq, 1);
1062}
1063
1064/*
1065 * Find a specific PCI IRQ entry.
1066 * Not an __init, possibly needed by modules
1067 */
1068int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin)
1069{
1070 int irq, i, best_ioapic = -1, best_idx = -1;
1071
1072 apic_pr_debug("Querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n",
1073 bus, slot, pin);
1074 if (test_bit(bus, mp_bus_not_pci)) {
1075 apic_pr_verbose("PCI BIOS passed nonexistent PCI bus %d!\n", bus);
1076 return -1;
1077 }
1078
1079 for (i = 0; i < mp_irq_entries; i++) {
1080 int lbus = mp_irqs[i].srcbus;
1081 int ioapic_idx, found = 0;
1082
1083 if (bus != lbus || mp_irqs[i].irqtype != mp_INT ||
1084 slot != ((mp_irqs[i].srcbusirq >> 2) & 0x1f))
1085 continue;
1086
1087 for_each_ioapic(ioapic_idx)
1088 if (mpc_ioapic_id(ioapic_idx) == mp_irqs[i].dstapic ||
1089 mp_irqs[i].dstapic == MP_APIC_ALL) {
1090 found = 1;
1091 break;
1092 }
1093 if (!found)
1094 continue;
1095
1096 /* Skip ISA IRQs */
1097 irq = pin_2_irq(i, ioapic_idx, mp_irqs[i].dstirq, 0);
1098 if (irq > 0 && !IO_APIC_IRQ(irq))
1099 continue;
1100
1101 if (pin == (mp_irqs[i].srcbusirq & 3)) {
1102 best_idx = i;
1103 best_ioapic = ioapic_idx;
1104 goto out;
1105 }
1106
1107 /*
1108 * Use the first all-but-pin matching entry as a
1109 * best-guess fuzzy result for broken mptables.
1110 */
1111 if (best_idx < 0) {
1112 best_idx = i;
1113 best_ioapic = ioapic_idx;
1114 }
1115 }
1116 if (best_idx < 0)
1117 return -1;
1118
1119out:
1120 return pin_2_irq(best_idx, best_ioapic, mp_irqs[best_idx].dstirq, IOAPIC_MAP_ALLOC);
1121}
1122EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector);
1123
1124static struct irq_chip ioapic_chip, ioapic_ir_chip;
1125
1126static void __init setup_IO_APIC_irqs(void)
1127{
1128 unsigned int ioapic, pin;
1129 int idx;
1130
1131 apic_pr_verbose("Init IO_APIC IRQs\n");
1132
1133 for_each_ioapic_pin(ioapic, pin) {
1134 idx = find_irq_entry(ioapic, pin, mp_INT);
1135 if (idx < 0) {
1136 apic_pr_verbose("apic %d pin %d not connected\n",
1137 mpc_ioapic_id(ioapic), pin);
1138 } else {
1139 pin_2_irq(idx, ioapic, pin, ioapic ? 0 : IOAPIC_MAP_ALLOC);
1140 }
1141 }
1142}
1143
1144void ioapic_zap_locks(void)
1145{
1146 raw_spin_lock_init(&ioapic_lock);
1147}
1148
1149static void io_apic_print_entries(unsigned int apic, unsigned int nr_entries)
1150{
1151 struct IO_APIC_route_entry entry;
1152 char buf[256];
1153 int i;
1154
1155 apic_dbg("IOAPIC %d:\n", apic);
1156 for (i = 0; i <= nr_entries; i++) {
1157 entry = ioapic_read_entry(apic, i);
1158 snprintf(buf, sizeof(buf), " pin%02x, %s, %s, %s, V(%02X), IRR(%1d), S(%1d)",
1159 i, entry.masked ? "disabled" : "enabled ",
1160 entry.is_level ? "level" : "edge ",
1161 entry.active_low ? "low " : "high",
1162 entry.vector, entry.irr, entry.delivery_status);
1163 if (entry.ir_format) {
1164 apic_dbg("%s, remapped, I(%04X), Z(%X)\n", buf,
1165 (entry.ir_index_15 << 15) | entry.ir_index_0_14, entry.ir_zero);
1166 } else {
1167 apic_dbg("%s, %s, D(%02X%02X), M(%1d)\n", buf,
1168 entry.dest_mode_logical ? "logical " : "physic al",
1169 entry.virt_destid_8_14, entry.destid_0_7, entry.delivery_mode);
1170 }
1171 }
1172}
1173
1174static void __init print_IO_APIC(int ioapic_idx)
1175{
1176 union IO_APIC_reg_00 reg_00;
1177 union IO_APIC_reg_01 reg_01;
1178 union IO_APIC_reg_02 reg_02;
1179 union IO_APIC_reg_03 reg_03;
1180
1181 scoped_guard (raw_spinlock_irqsave, &ioapic_lock) {
1182 reg_00.raw = io_apic_read(ioapic_idx, 0);
1183 reg_01.raw = io_apic_read(ioapic_idx, 1);
1184 if (reg_01.bits.version >= 0x10)
1185 reg_02.raw = io_apic_read(ioapic_idx, 2);
1186 if (reg_01.bits.version >= 0x20)
1187 reg_03.raw = io_apic_read(ioapic_idx, 3);
1188 }
1189
1190 apic_dbg("IO APIC #%d......\n", mpc_ioapic_id(ioapic_idx));
1191 apic_dbg(".... register #00: %08X\n", reg_00.raw);
1192 apic_dbg("....... : physical APIC id: %02X\n", reg_00.bits.ID);
1193 apic_dbg("....... : Delivery Type: %X\n", reg_00.bits.delivery_type);
1194 apic_dbg("....... : LTS : %X\n", reg_00.bits.LTS);
1195 apic_dbg(".... register #01: %08X\n", *(int *)®_01);
1196 apic_dbg("....... : max redirection entries: %02X\n", reg_01.bits.entries);
1197 apic_dbg("....... : PRQ implemented: %X\n", reg_01.bits.PRQ);
1198 apic_dbg("....... : IO APIC version: %02X\n", reg_01.bits.version);
1199
1200 /*
1201 * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02,
1202 * but the value of reg_02 is read as the previous read register
1203 * value, so ignore it if reg_02 == reg_01.
1204 */
1205 if (reg_01.bits.version >= 0x10 && reg_02.raw != reg_01.raw) {
1206 apic_dbg(".... register #02: %08X\n", reg_02.raw);
1207 apic_dbg("....... : arbitration: %02X\n", reg_02.bits.arbitration);
1208 }
1209
1210 /*
1211 * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02
1212 * or reg_03, but the value of reg_0[23] is read as the previous read
1213 * register value, so ignore it if reg_03 == reg_0[12].
1214 */
1215 if (reg_01.bits.version >= 0x20 && reg_03.raw != reg_02.raw &&
1216 reg_03.raw != reg_01.raw) {
1217 apic_dbg(".... register #03: %08X\n", reg_03.raw);
1218 apic_dbg("....... : Boot DT : %X\n", reg_03.bits.boot_DT);
1219 }
1220
1221 apic_dbg(".... IRQ redirection table:\n");
1222 io_apic_print_entries(ioapic_idx, reg_01.bits.entries);
1223}
1224
1225void __init print_IO_APICs(void)
1226{
1227 int ioapic_idx;
1228 unsigned int irq;
1229
1230 apic_dbg("number of MP IRQ sources: %d.\n", mp_irq_entries);
1231 for_each_ioapic(ioapic_idx) {
1232 apic_dbg("number of IO-APIC #%d registers: %d.\n",
1233 mpc_ioapic_id(ioapic_idx), ioapics[ioapic_idx].nr_registers);
1234 }
1235
1236 /*
1237 * We are a bit conservative about what we expect. We have to
1238 * know about every hardware change ASAP.
1239 */
1240 printk(KERN_INFO "testing the IO APIC.......................\n");
1241
1242 for_each_ioapic(ioapic_idx)
1243 print_IO_APIC(ioapic_idx);
1244
1245 apic_dbg("IRQ to pin mappings:\n");
1246 for_each_active_irq(irq) {
1247 struct irq_pin_list *entry;
1248 struct irq_chip *chip;
1249 struct mp_chip_data *data;
1250
1251 chip = irq_get_chip(irq);
1252 if (chip != &ioapic_chip && chip != &ioapic_ir_chip)
1253 continue;
1254 data = irq_get_chip_data(irq);
1255 if (!data)
1256 continue;
1257 if (list_empty(&data->irq_2_pin))
1258 continue;
1259
1260 apic_dbg("IRQ%d ", irq);
1261 for_each_irq_pin(entry, data->irq_2_pin)
1262 pr_cont("-> %d:%d", entry->apic, entry->pin);
1263 pr_cont("\n");
1264 }
1265
1266 printk(KERN_INFO ".................................... done.\n");
1267}
1268
1269/* Where if anywhere is the i8259 connect in external int mode */
1270static struct { int pin, apic; } ioapic_i8259 = { -1, -1 };
1271
1272void __init enable_IO_APIC(void)
1273{
1274 int i8259_apic, i8259_pin, apic, pin;
1275
1276 if (ioapic_is_disabled)
1277 nr_ioapics = 0;
1278
1279 if (!nr_legacy_irqs() || !nr_ioapics)
1280 return;
1281
1282 for_each_ioapic_pin(apic, pin) {
1283 /* See if any of the pins is in ExtINT mode */
1284 struct IO_APIC_route_entry entry = ioapic_read_entry(apic, pin);
1285
1286 /*
1287 * If the interrupt line is enabled and in ExtInt mode I
1288 * have found the pin where the i8259 is connected.
1289 */
1290 if (!entry.masked && entry.delivery_mode == APIC_DELIVERY_MODE_EXTINT) {
1291 ioapic_i8259.apic = apic;
1292 ioapic_i8259.pin = pin;
1293 break;
1294 }
1295 }
1296
1297 /*
1298 * Look to see what if the MP table has reported the ExtINT
1299 *
1300 * If we could not find the appropriate pin by looking at the ioapic
1301 * the i8259 probably is not connected the ioapic but give the
1302 * mptable a chance anyway.
1303 */
1304 i8259_pin = find_isa_irq_pin(0, mp_ExtINT);
1305 i8259_apic = find_isa_irq_apic(0, mp_ExtINT);
1306 /* Trust the MP table if nothing is setup in the hardware */
1307 if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) {
1308 pr_warn("ExtINT not setup in hardware but reported by MP table\n");
1309 ioapic_i8259.pin = i8259_pin;
1310 ioapic_i8259.apic = i8259_apic;
1311 }
1312 /* Complain if the MP table and the hardware disagree */
1313 if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) &&
1314 (i8259_pin >= 0) && (ioapic_i8259.pin >= 0))
1315 pr_warn("ExtINT in hardware and MP table differ\n");
1316
1317 /* Do not trust the IO-APIC being empty at bootup */
1318 clear_IO_APIC();
1319}
1320
1321void native_restore_boot_irq_mode(void)
1322{
1323 /*
1324 * If the i8259 is routed through an IOAPIC Put that IOAPIC in
1325 * virtual wire mode so legacy interrupts can be delivered.
1326 */
1327 if (ioapic_i8259.pin != -1) {
1328 struct IO_APIC_route_entry entry;
1329 u32 apic_id = read_apic_id();
1330
1331 memset(&entry, 0, sizeof(entry));
1332 entry.masked = false;
1333 entry.is_level = false;
1334 entry.active_low = false;
1335 entry.dest_mode_logical = false;
1336 entry.delivery_mode = APIC_DELIVERY_MODE_EXTINT;
1337 entry.destid_0_7 = apic_id & 0xFF;
1338 entry.virt_destid_8_14 = apic_id >> 8;
1339
1340 /* Add it to the IO-APIC irq-routing table */
1341 ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry);
1342 }
1343
1344 if (boot_cpu_has(X86_FEATURE_APIC) || apic_from_smp_config())
1345 disconnect_bsp_APIC(ioapic_i8259.pin != -1);
1346}
1347
1348void restore_boot_irq_mode(void)
1349{
1350 if (!nr_legacy_irqs())
1351 return;
1352
1353 x86_apic_ops.restore();
1354}
1355
1356#ifdef CONFIG_X86_32
1357/*
1358 * function to set the IO-APIC physical IDs based on the
1359 * values stored in the MPC table.
1360 *
1361 * by Matt Domsch <Matt_Domsch@dell.com> Tue Dec 21 12:25:05 CST 1999
1362 */
1363static void __init setup_ioapic_ids_from_mpc_nocheck(void)
1364{
1365 DECLARE_BITMAP(phys_id_present_map, MAX_LOCAL_APIC);
1366 const u32 broadcast_id = 0xF;
1367 union IO_APIC_reg_00 reg_00;
1368 unsigned char old_id;
1369 int ioapic_idx, i;
1370
1371 /*
1372 * This is broken; anything with a real cpu count has to
1373 * circumvent this idiocy regardless.
1374 */
1375 copy_phys_cpu_present_map(phys_id_present_map);
1376
1377 /*
1378 * Set the IOAPIC ID to the value stored in the MPC table.
1379 */
1380 for_each_ioapic(ioapic_idx) {
1381 /* Read the register 0 value */
1382 scoped_guard (raw_spinlock_irqsave, &ioapic_lock)
1383 reg_00.raw = io_apic_read(ioapic_idx, 0);
1384
1385 old_id = mpc_ioapic_id(ioapic_idx);
1386
1387 if (mpc_ioapic_id(ioapic_idx) >= broadcast_id) {
1388 pr_err(FW_BUG "IO-APIC#%d ID is %d in the MPC table!...\n",
1389 ioapic_idx, mpc_ioapic_id(ioapic_idx));
1390 pr_err("... fixing up to %d. (tell your hw vendor)\n", reg_00.bits.ID);
1391 ioapics[ioapic_idx].mp_config.apicid = reg_00.bits.ID;
1392 }
1393
1394 /*
1395 * Sanity check, is the ID really free? Every APIC in a
1396 * system must have a unique ID or we get lots of nice
1397 * 'stuck on smp_invalidate_needed IPI wait' messages.
1398 */
1399 if (test_bit(mpc_ioapic_id(ioapic_idx), phys_id_present_map)) {
1400 pr_err(FW_BUG "IO-APIC#%d ID %d is already used!...\n",
1401 ioapic_idx, mpc_ioapic_id(ioapic_idx));
1402 for (i = 0; i < broadcast_id; i++)
1403 if (!test_bit(i, phys_id_present_map))
1404 break;
1405 if (i >= broadcast_id)
1406 panic("Max APIC ID exceeded!\n");
1407 pr_err("... fixing up to %d. (tell your hw vendor)\n", i);
1408 set_bit(i, phys_id_present_map);
1409 ioapics[ioapic_idx].mp_config.apicid = i;
1410 } else {
1411 apic_pr_verbose("Setting %d in the phys_id_present_map\n",
1412 mpc_ioapic_id(ioapic_idx));
1413 set_bit(mpc_ioapic_id(ioapic_idx), phys_id_present_map);
1414 }
1415
1416 /*
1417 * We need to adjust the IRQ routing table if the ID
1418 * changed.
1419 */
1420 if (old_id != mpc_ioapic_id(ioapic_idx)) {
1421 for (i = 0; i < mp_irq_entries; i++) {
1422 if (mp_irqs[i].dstapic == old_id)
1423 mp_irqs[i].dstapic = mpc_ioapic_id(ioapic_idx);
1424 }
1425 }
1426
1427 /*
1428 * Update the ID register according to the right value from
1429 * the MPC table if they are different.
1430 */
1431 if (mpc_ioapic_id(ioapic_idx) == reg_00.bits.ID)
1432 continue;
1433
1434 apic_pr_verbose("...changing IO-APIC physical APIC ID to %d ...",
1435 mpc_ioapic_id(ioapic_idx));
1436
1437 reg_00.bits.ID = mpc_ioapic_id(ioapic_idx);
1438 scoped_guard (raw_spinlock_irqsave, &ioapic_lock) {
1439 io_apic_write(ioapic_idx, 0, reg_00.raw);
1440 reg_00.raw = io_apic_read(ioapic_idx, 0);
1441 }
1442 /* Sanity check */
1443 if (reg_00.bits.ID != mpc_ioapic_id(ioapic_idx))
1444 pr_cont("could not set ID!\n");
1445 else
1446 apic_pr_verbose(" ok.\n");
1447 }
1448}
1449
1450void __init setup_ioapic_ids_from_mpc(void)
1451{
1452
1453 if (acpi_ioapic)
1454 return;
1455 /*
1456 * Don't check I/O APIC IDs for xAPIC systems. They have
1457 * no meaning without the serial APIC bus.
1458 */
1459 if (!(boot_cpu_data.x86_vendor == X86_VENDOR_INTEL)
1460 || APIC_XAPIC(boot_cpu_apic_version))
1461 return;
1462 setup_ioapic_ids_from_mpc_nocheck();
1463}
1464#endif
1465
1466int no_timer_check __initdata;
1467
1468static int __init notimercheck(char *s)
1469{
1470 no_timer_check = 1;
1471 return 1;
1472}
1473__setup("no_timer_check", notimercheck);
1474
1475static void __init delay_with_tsc(void)
1476{
1477 unsigned long long start, now;
1478 unsigned long end = jiffies + 4;
1479
1480 start = rdtsc();
1481
1482 /*
1483 * We don't know the TSC frequency yet, but waiting for
1484 * 40000000000/HZ TSC cycles is safe:
1485 * 4 GHz == 10 jiffies
1486 * 1 GHz == 40 jiffies
1487 */
1488 do {
1489 rep_nop();
1490 now = rdtsc();
1491 } while ((now - start) < 40000000000ULL / HZ && time_before_eq(jiffies, end));
1492}
1493
1494static void __init delay_without_tsc(void)
1495{
1496 unsigned long end = jiffies + 4;
1497 int band = 1;
1498
1499 /*
1500 * We don't know any frequency yet, but waiting for
1501 * 40940000000/HZ cycles is safe:
1502 * 4 GHz == 10 jiffies
1503 * 1 GHz == 40 jiffies
1504 * 1 << 1 + 1 << 2 +...+ 1 << 11 = 4094
1505 */
1506 do {
1507 __delay(((1U << band++) * 10000000UL) / HZ);
1508 } while (band < 12 && time_before_eq(jiffies, end));
1509}
1510
1511/*
1512 * There is a nasty bug in some older SMP boards, their mptable lies
1513 * about the timer IRQ. We do the following to work around the situation:
1514 *
1515 * - timer IRQ defaults to IO-APIC IRQ
1516 * - if this function detects that timer IRQs are defunct, then we fall
1517 * back to ISA timer IRQs
1518 */
1519static int __init timer_irq_works(void)
1520{
1521 unsigned long t1 = jiffies;
1522
1523 if (no_timer_check)
1524 return 1;
1525
1526 local_irq_enable();
1527 if (boot_cpu_has(X86_FEATURE_TSC))
1528 delay_with_tsc();
1529 else
1530 delay_without_tsc();
1531
1532 /*
1533 * Expect a few ticks at least, to be sure some possible
1534 * glue logic does not lock up after one or two first
1535 * ticks in a non-ExtINT mode. Also the local APIC
1536 * might have cached one ExtINT interrupt. Finally, at
1537 * least one tick may be lost due to delays.
1538 */
1539
1540 local_irq_disable();
1541
1542 /* Did jiffies advance? */
1543 return time_after(jiffies, t1 + 4);
1544}
1545
1546/*
1547 * In the SMP+IOAPIC case it might happen that there are an unspecified
1548 * number of pending IRQ events unhandled. These cases are very rare,
1549 * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
1550 * better to do it this way as thus we do not have to be aware of
1551 * 'pending' interrupts in the IRQ path, except at this point.
1552 *
1553 *
1554 * Edge triggered needs to resend any interrupt that was delayed but this
1555 * is now handled in the device independent code.
1556 *
1557 * Starting up a edge-triggered IO-APIC interrupt is nasty - we need to
1558 * make sure that we get the edge. If it is already asserted for some
1559 * reason, we need return 1 to indicate that is was pending.
1560 *
1561 * This is not complete - we should be able to fake an edge even if it
1562 * isn't on the 8259A...
1563 */
1564static unsigned int startup_ioapic_irq(struct irq_data *data)
1565{
1566 int was_pending = 0, irq = data->irq;
1567
1568 guard(raw_spinlock_irqsave)(&ioapic_lock);
1569 if (irq < nr_legacy_irqs()) {
1570 legacy_pic->mask(irq);
1571 if (legacy_pic->irq_pending(irq))
1572 was_pending = 1;
1573 }
1574 __unmask_ioapic(data->chip_data);
1575 return was_pending;
1576}
1577
1578atomic_t irq_mis_count;
1579
1580#ifdef CONFIG_GENERIC_PENDING_IRQ
1581static bool io_apic_level_ack_pending(struct mp_chip_data *data)
1582{
1583 struct irq_pin_list *entry;
1584
1585 guard(raw_spinlock_irqsave)(&ioapic_lock);
1586 for_each_irq_pin(entry, data->irq_2_pin) {
1587 struct IO_APIC_route_entry e;
1588 int pin;
1589
1590 pin = entry->pin;
1591 e.w1 = io_apic_read(entry->apic, 0x10 + pin*2);
1592 /* Is the remote IRR bit set? */
1593 if (e.irr)
1594 return true;
1595 }
1596 return false;
1597}
1598
1599static inline bool ioapic_prepare_move(struct irq_data *data)
1600{
1601 /* If we are moving the IRQ we need to mask it */
1602 if (unlikely(irqd_is_setaffinity_pending(data))) {
1603 if (!irqd_irq_masked(data))
1604 mask_ioapic_irq(data);
1605 return true;
1606 }
1607 return false;
1608}
1609
1610static inline void ioapic_finish_move(struct irq_data *data, bool moveit)
1611{
1612 if (unlikely(moveit)) {
1613 /*
1614 * Only migrate the irq if the ack has been received.
1615 *
1616 * On rare occasions the broadcast level triggered ack gets
1617 * delayed going to ioapics, and if we reprogram the
1618 * vector while Remote IRR is still set the irq will never
1619 * fire again.
1620 *
1621 * To prevent this scenario we read the Remote IRR bit
1622 * of the ioapic. This has two effects.
1623 * - On any sane system the read of the ioapic will
1624 * flush writes (and acks) going to the ioapic from
1625 * this cpu.
1626 * - We get to see if the ACK has actually been delivered.
1627 *
1628 * Based on failed experiments of reprogramming the
1629 * ioapic entry from outside of irq context starting
1630 * with masking the ioapic entry and then polling until
1631 * Remote IRR was clear before reprogramming the
1632 * ioapic I don't trust the Remote IRR bit to be
1633 * completely accurate.
1634 *
1635 * However there appears to be no other way to plug
1636 * this race, so if the Remote IRR bit is not
1637 * accurate and is causing problems then it is a hardware bug
1638 * and you can go talk to the chipset vendor about it.
1639 */
1640 if (!io_apic_level_ack_pending(data->chip_data))
1641 irq_move_masked_irq(data);
1642 /* If the IRQ is masked in the core, leave it: */
1643 if (!irqd_irq_masked(data))
1644 unmask_ioapic_irq(data);
1645 }
1646}
1647#else
1648static inline bool ioapic_prepare_move(struct irq_data *data)
1649{
1650 return false;
1651}
1652static inline void ioapic_finish_move(struct irq_data *data, bool moveit)
1653{
1654}
1655#endif
1656
1657static void ioapic_ack_level(struct irq_data *irq_data)
1658{
1659 struct irq_cfg *cfg = irqd_cfg(irq_data);
1660 unsigned long v;
1661 bool moveit;
1662 int i;
1663
1664 irq_complete_move(cfg);
1665 moveit = ioapic_prepare_move(irq_data);
1666
1667 /*
1668 * It appears there is an erratum which affects at least version 0x11
1669 * of I/O APIC (that's the 82093AA and cores integrated into various
1670 * chipsets). Under certain conditions a level-triggered interrupt is
1671 * erroneously delivered as edge-triggered one but the respective IRR
1672 * bit gets set nevertheless. As a result the I/O unit expects an EOI
1673 * message but it will never arrive and further interrupts are blocked
1674 * from the source. The exact reason is so far unknown, but the
1675 * phenomenon was observed when two consecutive interrupt requests
1676 * from a given source get delivered to the same CPU and the source is
1677 * temporarily disabled in between.
1678 *
1679 * A workaround is to simulate an EOI message manually. We achieve it
1680 * by setting the trigger mode to edge and then to level when the edge
1681 * trigger mode gets detected in the TMR of a local APIC for a
1682 * level-triggered interrupt. We mask the source for the time of the
1683 * operation to prevent an edge-triggered interrupt escaping meanwhile.
1684 * The idea is from Manfred Spraul. --macro
1685 *
1686 * Also in the case when cpu goes offline, fixup_irqs() will forward
1687 * any unhandled interrupt on the offlined cpu to the new cpu
1688 * destination that is handling the corresponding interrupt. This
1689 * interrupt forwarding is done via IPI's. Hence, in this case also
1690 * level-triggered io-apic interrupt will be seen as an edge
1691 * interrupt in the IRR. And we can't rely on the cpu's EOI
1692 * to be broadcasted to the IO-APIC's which will clear the remoteIRR
1693 * corresponding to the level-triggered interrupt. Hence on IO-APIC's
1694 * supporting EOI register, we do an explicit EOI to clear the
1695 * remote IRR and on IO-APIC's which don't have an EOI register,
1696 * we use the above logic (mask+edge followed by unmask+level) from
1697 * Manfred Spraul to clear the remote IRR.
1698 */
1699 i = cfg->vector;
1700 v = apic_read(APIC_TMR + ((i & ~0x1f) >> 1));
1701
1702 /*
1703 * We must acknowledge the irq before we move it or the acknowledge will
1704 * not propagate properly.
1705 */
1706 apic_eoi();
1707
1708 /*
1709 * Tail end of clearing remote IRR bit (either by delivering the EOI
1710 * message via io-apic EOI register write or simulating it using
1711 * mask+edge followed by unmask+level logic) manually when the
1712 * level triggered interrupt is seen as the edge triggered interrupt
1713 * at the cpu.
1714 */
1715 if (!(v & (1 << (i & 0x1f)))) {
1716 atomic_inc(&irq_mis_count);
1717 eoi_ioapic_pin(cfg->vector, irq_data->chip_data);
1718 }
1719
1720 ioapic_finish_move(irq_data, moveit);
1721}
1722
1723static void ioapic_ir_ack_level(struct irq_data *irq_data)
1724{
1725 struct mp_chip_data *data = irq_data->chip_data;
1726
1727 /*
1728 * Intr-remapping uses pin number as the virtual vector
1729 * in the RTE. Actual vector is programmed in
1730 * intr-remapping table entry. Hence for the io-apic
1731 * EOI we use the pin number.
1732 */
1733 apic_ack_irq(irq_data);
1734 eoi_ioapic_pin(data->entry.vector, data);
1735}
1736
1737/*
1738 * The I/OAPIC is just a device for generating MSI messages from legacy
1739 * interrupt pins. Various fields of the RTE translate into bits of the
1740 * resulting MSI which had a historical meaning.
1741 *
1742 * With interrupt remapping, many of those bits have different meanings
1743 * in the underlying MSI, but the way that the I/OAPIC transforms them
1744 * from its RTE to the MSI message is the same. This function allows
1745 * the parent IRQ domain to compose the MSI message, then takes the
1746 * relevant bits to put them in the appropriate places in the RTE in
1747 * order to generate that message when the IRQ happens.
1748 *
1749 * The setup here relies on a preconfigured route entry (is_level,
1750 * active_low, masked) because the parent domain is merely composing the
1751 * generic message routing information which is used for the MSI.
1752 */
1753static void ioapic_setup_msg_from_msi(struct irq_data *irq_data,
1754 struct IO_APIC_route_entry *entry)
1755{
1756 struct msi_msg msg;
1757
1758 /* Let the parent domain compose the MSI message */
1759 irq_chip_compose_msi_msg(irq_data, &msg);
1760
1761 /*
1762 * - Real vector
1763 * - DMAR/IR: 8bit subhandle (ioapic.pin)
1764 * - AMD/IR: 8bit IRTE index
1765 */
1766 entry->vector = msg.arch_data.vector;
1767 /* Delivery mode (for DMAR/IR all 0) */
1768 entry->delivery_mode = msg.arch_data.delivery_mode;
1769 /* Destination mode or DMAR/IR index bit 15 */
1770 entry->dest_mode_logical = msg.arch_addr_lo.dest_mode_logical;
1771 /* DMAR/IR: 1, 0 for all other modes */
1772 entry->ir_format = msg.arch_addr_lo.dmar_format;
1773 /*
1774 * - DMAR/IR: index bit 0-14.
1775 *
1776 * - Virt: If the host supports x2apic without a virtualized IR
1777 * unit then bit 0-6 of dmar_index_0_14 are providing bit
1778 * 8-14 of the destination id.
1779 *
1780 * All other modes have bit 0-6 of dmar_index_0_14 cleared and the
1781 * topmost 8 bits are destination id bit 0-7 (entry::destid_0_7).
1782 */
1783 entry->ir_index_0_14 = msg.arch_addr_lo.dmar_index_0_14;
1784}
1785
1786static void ioapic_configure_entry(struct irq_data *irqd)
1787{
1788 struct mp_chip_data *mpd = irqd->chip_data;
1789 struct irq_pin_list *entry;
1790
1791 ioapic_setup_msg_from_msi(irqd, &mpd->entry);
1792
1793 for_each_irq_pin(entry, mpd->irq_2_pin)
1794 __ioapic_write_entry(entry->apic, entry->pin, mpd->entry);
1795}
1796
1797static int ioapic_set_affinity(struct irq_data *irq_data, const struct cpumask *mask, bool force)
1798{
1799 struct irq_data *parent = irq_data->parent_data;
1800 int ret;
1801
1802 ret = parent->chip->irq_set_affinity(parent, mask, force);
1803
1804 guard(raw_spinlock_irqsave)(&ioapic_lock);
1805 if (ret >= 0 && ret != IRQ_SET_MASK_OK_DONE)
1806 ioapic_configure_entry(irq_data);
1807
1808 return ret;
1809}
1810
1811/*
1812 * Interrupt shutdown masks the ioapic pin, but the interrupt might already
1813 * be in flight, but not yet serviced by the target CPU. That means
1814 * __synchronize_hardirq() would return and claim that everything is calmed
1815 * down. So free_irq() would proceed and deactivate the interrupt and free
1816 * resources.
1817 *
1818 * Once the target CPU comes around to service it it will find a cleared
1819 * vector and complain. While the spurious interrupt is harmless, the full
1820 * release of resources might prevent the interrupt from being acknowledged
1821 * which keeps the hardware in a weird state.
1822 *
1823 * Verify that the corresponding Remote-IRR bits are clear.
1824 */
1825static int ioapic_irq_get_chip_state(struct irq_data *irqd, enum irqchip_irq_state which,
1826 bool *state)
1827{
1828 struct mp_chip_data *mcd = irqd->chip_data;
1829 struct IO_APIC_route_entry rentry;
1830 struct irq_pin_list *p;
1831
1832 if (which != IRQCHIP_STATE_ACTIVE)
1833 return -EINVAL;
1834
1835 *state = false;
1836
1837 guard(raw_spinlock)(&ioapic_lock);
1838 for_each_irq_pin(p, mcd->irq_2_pin) {
1839 rentry = __ioapic_read_entry(p->apic, p->pin);
1840 /*
1841 * The remote IRR is only valid in level trigger mode. It's
1842 * meaning is undefined for edge triggered interrupts and
1843 * irrelevant because the IO-APIC treats them as fire and
1844 * forget.
1845 */
1846 if (rentry.irr && rentry.is_level) {
1847 *state = true;
1848 break;
1849 }
1850 }
1851 return 0;
1852}
1853
1854static struct irq_chip ioapic_chip __read_mostly = {
1855 .name = "IO-APIC",
1856 .irq_startup = startup_ioapic_irq,
1857 .irq_mask = mask_ioapic_irq,
1858 .irq_unmask = unmask_ioapic_irq,
1859 .irq_ack = irq_chip_ack_parent,
1860 .irq_eoi = ioapic_ack_level,
1861 .irq_set_affinity = ioapic_set_affinity,
1862 .irq_retrigger = irq_chip_retrigger_hierarchy,
1863 .irq_get_irqchip_state = ioapic_irq_get_chip_state,
1864 .flags = IRQCHIP_SKIP_SET_WAKE |
1865 IRQCHIP_AFFINITY_PRE_STARTUP,
1866};
1867
1868static struct irq_chip ioapic_ir_chip __read_mostly = {
1869 .name = "IR-IO-APIC",
1870 .irq_startup = startup_ioapic_irq,
1871 .irq_mask = mask_ioapic_irq,
1872 .irq_unmask = unmask_ioapic_irq,
1873 .irq_ack = irq_chip_ack_parent,
1874 .irq_eoi = ioapic_ir_ack_level,
1875 .irq_set_affinity = ioapic_set_affinity,
1876 .irq_retrigger = irq_chip_retrigger_hierarchy,
1877 .irq_get_irqchip_state = ioapic_irq_get_chip_state,
1878 .flags = IRQCHIP_SKIP_SET_WAKE |
1879 IRQCHIP_AFFINITY_PRE_STARTUP,
1880};
1881
1882static inline void init_IO_APIC_traps(void)
1883{
1884 struct irq_cfg *cfg;
1885 unsigned int irq;
1886
1887 for_each_active_irq(irq) {
1888 cfg = irq_cfg(irq);
1889 if (IO_APIC_IRQ(irq) && cfg && !cfg->vector) {
1890 /*
1891 * Hmm.. We don't have an entry for this, so
1892 * default to an old-fashioned 8259 interrupt if we
1893 * can. Otherwise set the dummy interrupt chip.
1894 */
1895 if (irq < nr_legacy_irqs())
1896 legacy_pic->make_irq(irq);
1897 else
1898 irq_set_chip(irq, &no_irq_chip);
1899 }
1900 }
1901}
1902
1903/*
1904 * The local APIC irq-chip implementation:
1905 */
1906static void mask_lapic_irq(struct irq_data *data)
1907{
1908 unsigned long v = apic_read(APIC_LVT0);
1909
1910 apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
1911}
1912
1913static void unmask_lapic_irq(struct irq_data *data)
1914{
1915 unsigned long v = apic_read(APIC_LVT0);
1916
1917 apic_write(APIC_LVT0, v & ~APIC_LVT_MASKED);
1918}
1919
1920static void ack_lapic_irq(struct irq_data *data)
1921{
1922 apic_eoi();
1923}
1924
1925static struct irq_chip lapic_chip __read_mostly = {
1926 .name = "local-APIC",
1927 .irq_mask = mask_lapic_irq,
1928 .irq_unmask = unmask_lapic_irq,
1929 .irq_ack = ack_lapic_irq,
1930};
1931
1932static void lapic_register_intr(int irq)
1933{
1934 irq_clear_status_flags(irq, IRQ_LEVEL);
1935 irq_set_chip_and_handler_name(irq, &lapic_chip, handle_edge_irq, "edge");
1936}
1937
1938/*
1939 * This looks a bit hackish but it's about the only one way of sending
1940 * a few INTA cycles to 8259As and any associated glue logic. ICR does
1941 * not support the ExtINT mode, unfortunately. We need to send these
1942 * cycles as some i82489DX-based boards have glue logic that keeps the
1943 * 8259A interrupt line asserted until INTA. --macro
1944 */
1945static inline void __init unlock_ExtINT_logic(void)
1946{
1947 unsigned char save_control, save_freq_select;
1948 struct IO_APIC_route_entry entry0, entry1;
1949 int apic, pin, i;
1950 u32 apic_id;
1951
1952 pin = find_isa_irq_pin(8, mp_INT);
1953 if (pin == -1) {
1954 WARN_ON_ONCE(1);
1955 return;
1956 }
1957 apic = find_isa_irq_apic(8, mp_INT);
1958 if (apic == -1) {
1959 WARN_ON_ONCE(1);
1960 return;
1961 }
1962
1963 entry0 = ioapic_read_entry(apic, pin);
1964 clear_IO_APIC_pin(apic, pin);
1965
1966 apic_id = read_apic_id();
1967 memset(&entry1, 0, sizeof(entry1));
1968
1969 entry1.dest_mode_logical = true;
1970 entry1.masked = false;
1971 entry1.destid_0_7 = apic_id & 0xFF;
1972 entry1.virt_destid_8_14 = apic_id >> 8;
1973 entry1.delivery_mode = APIC_DELIVERY_MODE_EXTINT;
1974 entry1.active_low = entry0.active_low;
1975 entry1.is_level = false;
1976 entry1.vector = 0;
1977
1978 ioapic_write_entry(apic, pin, entry1);
1979
1980 save_control = CMOS_READ(RTC_CONTROL);
1981 save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
1982 CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6,
1983 RTC_FREQ_SELECT);
1984 CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL);
1985
1986 i = 100;
1987 while (i-- > 0) {
1988 mdelay(10);
1989 if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF)
1990 i -= 10;
1991 }
1992
1993 CMOS_WRITE(save_control, RTC_CONTROL);
1994 CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
1995 clear_IO_APIC_pin(apic, pin);
1996
1997 ioapic_write_entry(apic, pin, entry0);
1998}
1999
2000static int disable_timer_pin_1 __initdata;
2001/* Actually the next is obsolete, but keep it for paranoid reasons -AK */
2002static int __init disable_timer_pin_setup(char *arg)
2003{
2004 disable_timer_pin_1 = 1;
2005 return 0;
2006}
2007early_param("disable_timer_pin_1", disable_timer_pin_setup);
2008
2009static int __init mp_alloc_timer_irq(int ioapic, int pin)
2010{
2011 struct irq_domain *domain = mp_ioapic_irqdomain(ioapic);
2012 int irq = -1;
2013
2014 if (domain) {
2015 struct irq_alloc_info info;
2016
2017 ioapic_set_alloc_attr(&info, NUMA_NO_NODE, 0, 0);
2018 info.devid = mpc_ioapic_id(ioapic);
2019 info.ioapic.pin = pin;
2020 guard(mutex)(&ioapic_mutex);
2021 irq = alloc_isa_irq_from_domain(domain, 0, ioapic, pin, &info);
2022 }
2023
2024 return irq;
2025}
2026
2027static void __init replace_pin_at_irq_node(struct mp_chip_data *data, int node,
2028 int oldapic, int oldpin,
2029 int newapic, int newpin)
2030{
2031 struct irq_pin_list *entry;
2032
2033 for_each_irq_pin(entry, data->irq_2_pin) {
2034 if (entry->apic == oldapic && entry->pin == oldpin) {
2035 entry->apic = newapic;
2036 entry->pin = newpin;
2037 return;
2038 }
2039 }
2040
2041 /* Old apic/pin didn't exist, so just add a new one */
2042 add_pin_to_irq_node(data, node, newapic, newpin);
2043}
2044
2045/*
2046 * This code may look a bit paranoid, but it's supposed to cooperate with
2047 * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ
2048 * is so screwy. Thanks to Brian Perkins for testing/hacking this beast
2049 * fanatically on his truly buggy board.
2050 */
2051static inline void __init check_timer(void)
2052{
2053 struct irq_data *irq_data = irq_get_irq_data(0);
2054 struct mp_chip_data *data = irq_data->chip_data;
2055 struct irq_cfg *cfg = irqd_cfg(irq_data);
2056 int node = cpu_to_node(0);
2057 int apic1, pin1, apic2, pin2;
2058 int no_pin1 = 0;
2059
2060 if (!global_clock_event)
2061 return;
2062
2063 local_irq_disable();
2064
2065 /*
2066 * get/set the timer IRQ vector:
2067 */
2068 legacy_pic->mask(0);
2069
2070 /*
2071 * As IRQ0 is to be enabled in the 8259A, the virtual
2072 * wire has to be disabled in the local APIC. Also
2073 * timer interrupts need to be acknowledged manually in
2074 * the 8259A for the i82489DX when using the NMI
2075 * watchdog as that APIC treats NMIs as level-triggered.
2076 * The AEOI mode will finish them in the 8259A
2077 * automatically.
2078 */
2079 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
2080 legacy_pic->init(1);
2081
2082 pin1 = find_isa_irq_pin(0, mp_INT);
2083 apic1 = find_isa_irq_apic(0, mp_INT);
2084 pin2 = ioapic_i8259.pin;
2085 apic2 = ioapic_i8259.apic;
2086
2087 pr_info("..TIMER: vector=0x%02X apic1=%d pin1=%d apic2=%d pin2=%d\n",
2088 cfg->vector, apic1, pin1, apic2, pin2);
2089
2090 /*
2091 * Some BIOS writers are clueless and report the ExtINTA
2092 * I/O APIC input from the cascaded 8259A as the timer
2093 * interrupt input. So just in case, if only one pin
2094 * was found above, try it both directly and through the
2095 * 8259A.
2096 */
2097 if (pin1 == -1) {
2098 panic_if_irq_remap(FW_BUG "Timer not connected to IO-APIC");
2099 pin1 = pin2;
2100 apic1 = apic2;
2101 no_pin1 = 1;
2102 } else if (pin2 == -1) {
2103 pin2 = pin1;
2104 apic2 = apic1;
2105 }
2106
2107 if (pin1 != -1) {
2108 /* Ok, does IRQ0 through the IOAPIC work? */
2109 if (no_pin1) {
2110 mp_alloc_timer_irq(apic1, pin1);
2111 } else {
2112 /*
2113 * for edge trigger, it's already unmasked,
2114 * so only need to unmask if it is level-trigger
2115 * do we really have level trigger timer?
2116 */
2117 int idx = find_irq_entry(apic1, pin1, mp_INT);
2118
2119 if (idx != -1 && irq_is_level(idx))
2120 unmask_ioapic_irq(irq_get_irq_data(0));
2121 }
2122 irq_domain_deactivate_irq(irq_data);
2123 irq_domain_activate_irq(irq_data, false);
2124 if (timer_irq_works()) {
2125 if (disable_timer_pin_1 > 0)
2126 clear_IO_APIC_pin(0, pin1);
2127 goto out;
2128 }
2129 panic_if_irq_remap("timer doesn't work through Interrupt-remapped IO-APIC");
2130 clear_IO_APIC_pin(apic1, pin1);
2131 if (!no_pin1)
2132 pr_err("..MP-BIOS bug: 8254 timer not connected to IO-APIC\n");
2133
2134 pr_info("...trying to set up timer (IRQ0) through the 8259A ...\n");
2135 pr_info("..... (found apic %d pin %d) ...\n", apic2, pin2);
2136 /*
2137 * legacy devices should be connected to IO APIC #0
2138 */
2139 replace_pin_at_irq_node(data, node, apic1, pin1, apic2, pin2);
2140 irq_domain_deactivate_irq(irq_data);
2141 irq_domain_activate_irq(irq_data, false);
2142 legacy_pic->unmask(0);
2143 if (timer_irq_works()) {
2144 pr_info("....... works.\n");
2145 goto out;
2146 }
2147 /*
2148 * Cleanup, just in case ...
2149 */
2150 legacy_pic->mask(0);
2151 clear_IO_APIC_pin(apic2, pin2);
2152 pr_info("....... failed.\n");
2153 }
2154
2155 pr_info("...trying to set up timer as Virtual Wire IRQ...\n");
2156
2157 lapic_register_intr(0);
2158 apic_write(APIC_LVT0, APIC_DM_FIXED | cfg->vector); /* Fixed mode */
2159 legacy_pic->unmask(0);
2160
2161 if (timer_irq_works()) {
2162 pr_info("..... works.\n");
2163 goto out;
2164 }
2165 legacy_pic->mask(0);
2166 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | cfg->vector);
2167 pr_info("..... failed.\n");
2168
2169 pr_info("...trying to set up timer as ExtINT IRQ...\n");
2170
2171 legacy_pic->init(0);
2172 legacy_pic->make_irq(0);
2173 apic_write(APIC_LVT0, APIC_DM_EXTINT);
2174 legacy_pic->unmask(0);
2175
2176 unlock_ExtINT_logic();
2177
2178 if (timer_irq_works()) {
2179 pr_info("..... works.\n");
2180 goto out;
2181 }
2182
2183 pr_info("..... failed :\n");
2184 if (apic_is_x2apic_enabled()) {
2185 pr_info("Perhaps problem with the pre-enabled x2apic mode\n"
2186 "Try booting with x2apic and interrupt-remapping disabled in the bios.\n");
2187 }
2188 panic("IO-APIC + timer doesn't work! Boot with apic=debug and send a "
2189 "report. Then try booting with the 'noapic' option.\n");
2190out:
2191 local_irq_enable();
2192}
2193
2194/*
2195 * Traditionally ISA IRQ2 is the cascade IRQ, and is not available
2196 * to devices. However there may be an I/O APIC pin available for
2197 * this interrupt regardless. The pin may be left unconnected, but
2198 * typically it will be reused as an ExtINT cascade interrupt for
2199 * the master 8259A. In the MPS case such a pin will normally be
2200 * reported as an ExtINT interrupt in the MP table. With ACPI
2201 * there is no provision for ExtINT interrupts, and in the absence
2202 * of an override it would be treated as an ordinary ISA I/O APIC
2203 * interrupt, that is edge-triggered and unmasked by default. We
2204 * used to do this, but it caused problems on some systems because
2205 * of the NMI watchdog and sometimes IRQ0 of the 8254 timer using
2206 * the same ExtINT cascade interrupt to drive the local APIC of the
2207 * bootstrap processor. Therefore we refrain from routing IRQ2 to
2208 * the I/O APIC in all cases now. No actual device should request
2209 * it anyway. --macro
2210 */
2211#define PIC_IRQS (1UL << PIC_CASCADE_IR)
2212
2213static int mp_irqdomain_create(int ioapic)
2214{
2215 struct mp_ioapic_gsi *gsi_cfg = mp_ioapic_gsi_routing(ioapic);
2216 int hwirqs = mp_ioapic_pin_count(ioapic);
2217 struct ioapic *ip = &ioapics[ioapic];
2218 struct ioapic_domain_cfg *cfg = &ip->irqdomain_cfg;
2219 struct irq_domain *parent;
2220 struct fwnode_handle *fn;
2221 struct irq_fwspec fwspec;
2222
2223 if (cfg->type == IOAPIC_DOMAIN_INVALID)
2224 return 0;
2225
2226 /* Handle device tree enumerated APICs proper */
2227 if (cfg->dev) {
2228 fn = of_node_to_fwnode(cfg->dev);
2229 } else {
2230 fn = irq_domain_alloc_named_id_fwnode("IO-APIC", mpc_ioapic_id(ioapic));
2231 if (!fn)
2232 return -ENOMEM;
2233 }
2234
2235 fwspec.fwnode = fn;
2236 fwspec.param_count = 1;
2237 fwspec.param[0] = mpc_ioapic_id(ioapic);
2238
2239 parent = irq_find_matching_fwspec(&fwspec, DOMAIN_BUS_GENERIC_MSI);
2240 if (!parent) {
2241 if (!cfg->dev)
2242 irq_domain_free_fwnode(fn);
2243 return -ENODEV;
2244 }
2245
2246 ip->irqdomain = irq_domain_create_hierarchy(parent, 0, hwirqs, fn, cfg->ops,
2247 (void *)(long)ioapic);
2248 if (!ip->irqdomain) {
2249 /* Release fw handle if it was allocated above */
2250 if (!cfg->dev)
2251 irq_domain_free_fwnode(fn);
2252 return -ENOMEM;
2253 }
2254
2255 if (cfg->type == IOAPIC_DOMAIN_LEGACY || cfg->type == IOAPIC_DOMAIN_STRICT)
2256 ioapic_dynirq_base = max(ioapic_dynirq_base, gsi_cfg->gsi_end + 1);
2257
2258 return 0;
2259}
2260
2261static void ioapic_destroy_irqdomain(int idx)
2262{
2263 struct ioapic_domain_cfg *cfg = &ioapics[idx].irqdomain_cfg;
2264 struct fwnode_handle *fn = ioapics[idx].irqdomain->fwnode;
2265
2266 if (ioapics[idx].irqdomain) {
2267 irq_domain_remove(ioapics[idx].irqdomain);
2268 if (!cfg->dev)
2269 irq_domain_free_fwnode(fn);
2270 ioapics[idx].irqdomain = NULL;
2271 }
2272}
2273
2274void __init setup_IO_APIC(void)
2275{
2276 int ioapic;
2277
2278 if (ioapic_is_disabled || !nr_ioapics)
2279 return;
2280
2281 io_apic_irqs = nr_legacy_irqs() ? ~PIC_IRQS : ~0UL;
2282
2283 apic_pr_verbose("ENABLING IO-APIC IRQs\n");
2284 for_each_ioapic(ioapic)
2285 BUG_ON(mp_irqdomain_create(ioapic));
2286
2287 /* Set up IO-APIC IRQ routing. */
2288 x86_init.mpparse.setup_ioapic_ids();
2289
2290 sync_Arb_IDs();
2291 setup_IO_APIC_irqs();
2292 init_IO_APIC_traps();
2293 if (nr_legacy_irqs())
2294 check_timer();
2295
2296 ioapic_initialized = 1;
2297}
2298
2299static void resume_ioapic_id(int ioapic_idx)
2300{
2301 union IO_APIC_reg_00 reg_00;
2302
2303 guard(raw_spinlock_irqsave)(&ioapic_lock);
2304 reg_00.raw = io_apic_read(ioapic_idx, 0);
2305 if (reg_00.bits.ID != mpc_ioapic_id(ioapic_idx)) {
2306 reg_00.bits.ID = mpc_ioapic_id(ioapic_idx);
2307 io_apic_write(ioapic_idx, 0, reg_00.raw);
2308 }
2309}
2310
2311static void ioapic_resume(void)
2312{
2313 int ioapic_idx;
2314
2315 for_each_ioapic_reverse(ioapic_idx)
2316 resume_ioapic_id(ioapic_idx);
2317
2318 restore_ioapic_entries();
2319}
2320
2321static struct syscore_ops ioapic_syscore_ops = {
2322 .suspend = save_ioapic_entries,
2323 .resume = ioapic_resume,
2324};
2325
2326static int __init ioapic_init_ops(void)
2327{
2328 register_syscore_ops(&ioapic_syscore_ops);
2329
2330 return 0;
2331}
2332
2333device_initcall(ioapic_init_ops);
2334
2335static int io_apic_get_redir_entries(int ioapic)
2336{
2337 union IO_APIC_reg_01 reg_01;
2338
2339 guard(raw_spinlock_irqsave)(&ioapic_lock);
2340 reg_01.raw = io_apic_read(ioapic, 1);
2341
2342 /*
2343 * The register returns the maximum index redir index supported,
2344 * which is one less than the total number of redir entries.
2345 */
2346 return reg_01.bits.entries + 1;
2347}
2348
2349unsigned int arch_dynirq_lower_bound(unsigned int from)
2350{
2351 unsigned int ret;
2352
2353 /*
2354 * dmar_alloc_hwirq() may be called before setup_IO_APIC(), so use
2355 * gsi_top if ioapic_dynirq_base hasn't been initialized yet.
2356 */
2357 ret = ioapic_dynirq_base ? : gsi_top;
2358
2359 /*
2360 * For DT enabled machines ioapic_dynirq_base is irrelevant and
2361 * always 0. gsi_top can be 0 if there is no IO/APIC registered.
2362 * 0 is an invalid interrupt number for dynamic allocations. Return
2363 * @from instead.
2364 */
2365 return ret ? : from;
2366}
2367
2368#ifdef CONFIG_X86_32
2369static int io_apic_get_unique_id(int ioapic, int apic_id)
2370{
2371 static DECLARE_BITMAP(apic_id_map, MAX_LOCAL_APIC);
2372 const u32 broadcast_id = 0xF;
2373 union IO_APIC_reg_00 reg_00;
2374 int i = 0;
2375
2376 /* Initialize the ID map */
2377 if (bitmap_empty(apic_id_map, MAX_LOCAL_APIC))
2378 copy_phys_cpu_present_map(apic_id_map);
2379
2380 scoped_guard (raw_spinlock_irqsave, &ioapic_lock)
2381 reg_00.raw = io_apic_read(ioapic, 0);
2382
2383 if (apic_id >= broadcast_id) {
2384 pr_warn("IOAPIC[%d]: Invalid apic_id %d, trying %d\n",
2385 ioapic, apic_id, reg_00.bits.ID);
2386 apic_id = reg_00.bits.ID;
2387 }
2388
2389 /* Every APIC in a system must have a unique ID */
2390 if (test_bit(apic_id, apic_id_map)) {
2391 for (i = 0; i < broadcast_id; i++) {
2392 if (!test_bit(i, apic_id_map))
2393 break;
2394 }
2395
2396 if (i == broadcast_id)
2397 panic("Max apic_id exceeded!\n");
2398
2399 pr_warn("IOAPIC[%d]: apic_id %d already used, trying %d\n", ioapic, apic_id, i);
2400 apic_id = i;
2401 }
2402
2403 set_bit(apic_id, apic_id_map);
2404
2405 if (reg_00.bits.ID != apic_id) {
2406 reg_00.bits.ID = apic_id;
2407
2408 scoped_guard (raw_spinlock_irqsave, &ioapic_lock) {
2409 io_apic_write(ioapic, 0, reg_00.raw);
2410 reg_00.raw = io_apic_read(ioapic, 0);
2411 }
2412
2413 /* Sanity check */
2414 if (reg_00.bits.ID != apic_id) {
2415 pr_err("IOAPIC[%d]: Unable to change apic_id!\n", ioapic);
2416 return -1;
2417 }
2418 }
2419
2420 apic_pr_verbose("IOAPIC[%d]: Assigned apic_id %d\n", ioapic, apic_id);
2421
2422 return apic_id;
2423}
2424
2425static u8 io_apic_unique_id(int idx, u8 id)
2426{
2427 if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) && !APIC_XAPIC(boot_cpu_apic_version))
2428 return io_apic_get_unique_id(idx, id);
2429 return id;
2430}
2431#else
2432static u8 io_apic_unique_id(int idx, u8 id)
2433{
2434 union IO_APIC_reg_00 reg_00;
2435 DECLARE_BITMAP(used, 256);
2436 u8 new_id;
2437 int i;
2438
2439 bitmap_zero(used, 256);
2440 for_each_ioapic(i)
2441 __set_bit(mpc_ioapic_id(i), used);
2442
2443 /* Hand out the requested id if available */
2444 if (!test_bit(id, used))
2445 return id;
2446
2447 /*
2448 * Read the current id from the ioapic and keep it if
2449 * available.
2450 */
2451 scoped_guard (raw_spinlock_irqsave, &ioapic_lock)
2452 reg_00.raw = io_apic_read(idx, 0);
2453
2454 new_id = reg_00.bits.ID;
2455 if (!test_bit(new_id, used)) {
2456 apic_pr_verbose("IOAPIC[%d]: Using reg apic_id %d instead of %d\n",
2457 idx, new_id, id);
2458 return new_id;
2459 }
2460
2461 /* Get the next free id and write it to the ioapic. */
2462 new_id = find_first_zero_bit(used, 256);
2463 reg_00.bits.ID = new_id;
2464 scoped_guard (raw_spinlock_irqsave, &ioapic_lock) {
2465 io_apic_write(idx, 0, reg_00.raw);
2466 reg_00.raw = io_apic_read(idx, 0);
2467 }
2468 /* Sanity check */
2469 BUG_ON(reg_00.bits.ID != new_id);
2470
2471 return new_id;
2472}
2473#endif
2474
2475static int io_apic_get_version(int ioapic)
2476{
2477 union IO_APIC_reg_01 reg_01;
2478
2479 guard(raw_spinlock_irqsave)(&ioapic_lock);
2480 reg_01.raw = io_apic_read(ioapic, 1);
2481
2482 return reg_01.bits.version;
2483}
2484
2485/*
2486 * This function updates target affinity of IOAPIC interrupts to include
2487 * the CPUs which came online during SMP bringup.
2488 */
2489#define IOAPIC_RESOURCE_NAME_SIZE 11
2490
2491static struct resource *ioapic_resources;
2492
2493static struct resource * __init ioapic_setup_resources(void)
2494{
2495 struct resource *res;
2496 unsigned long n;
2497 char *mem;
2498 int i;
2499
2500 if (nr_ioapics == 0)
2501 return NULL;
2502
2503 n = IOAPIC_RESOURCE_NAME_SIZE + sizeof(struct resource);
2504 n *= nr_ioapics;
2505
2506 mem = memblock_alloc(n, SMP_CACHE_BYTES);
2507 if (!mem)
2508 panic("%s: Failed to allocate %lu bytes\n", __func__, n);
2509 res = (void *)mem;
2510
2511 mem += sizeof(struct resource) * nr_ioapics;
2512
2513 for_each_ioapic(i) {
2514 res[i].name = mem;
2515 res[i].flags = IORESOURCE_MEM | IORESOURCE_BUSY;
2516 snprintf(mem, IOAPIC_RESOURCE_NAME_SIZE, "IOAPIC %u", i);
2517 mem += IOAPIC_RESOURCE_NAME_SIZE;
2518 ioapics[i].iomem_res = &res[i];
2519 }
2520
2521 ioapic_resources = res;
2522
2523 return res;
2524}
2525
2526static void io_apic_set_fixmap(enum fixed_addresses idx, phys_addr_t phys)
2527{
2528 pgprot_t flags = FIXMAP_PAGE_NOCACHE;
2529
2530 /*
2531 * Ensure fixmaps for IO-APIC MMIO respect memory encryption pgprot
2532 * bits, just like normal ioremap():
2533 */
2534 if (cc_platform_has(CC_ATTR_GUEST_MEM_ENCRYPT)) {
2535 if (x86_platform.hyper.is_private_mmio(phys))
2536 flags = pgprot_encrypted(flags);
2537 else
2538 flags = pgprot_decrypted(flags);
2539 }
2540
2541 __set_fixmap(idx, phys, flags);
2542}
2543
2544void __init io_apic_init_mappings(void)
2545{
2546 unsigned long ioapic_phys, idx = FIX_IO_APIC_BASE_0;
2547 struct resource *ioapic_res;
2548 int i;
2549
2550 ioapic_res = ioapic_setup_resources();
2551 for_each_ioapic(i) {
2552 if (smp_found_config) {
2553 ioapic_phys = mpc_ioapic_addr(i);
2554#ifdef CONFIG_X86_32
2555 if (!ioapic_phys) {
2556 pr_err("WARNING: bogus zero IO-APIC address found in MPTABLE, "
2557 "disabling IO/APIC support!\n");
2558 smp_found_config = 0;
2559 ioapic_is_disabled = true;
2560 goto fake_ioapic_page;
2561 }
2562#endif
2563 } else {
2564#ifdef CONFIG_X86_32
2565fake_ioapic_page:
2566#endif
2567 ioapic_phys = (unsigned long)memblock_alloc(PAGE_SIZE,
2568 PAGE_SIZE);
2569 if (!ioapic_phys)
2570 panic("%s: Failed to allocate %lu bytes align=0x%lx\n",
2571 __func__, PAGE_SIZE, PAGE_SIZE);
2572 ioapic_phys = __pa(ioapic_phys);
2573 }
2574 io_apic_set_fixmap(idx, ioapic_phys);
2575 apic_pr_verbose("mapped IOAPIC to %08lx (%08lx)\n",
2576 __fix_to_virt(idx) + (ioapic_phys & ~PAGE_MASK), ioapic_phys);
2577 idx++;
2578
2579 ioapic_res->start = ioapic_phys;
2580 ioapic_res->end = ioapic_phys + IO_APIC_SLOT_SIZE - 1;
2581 ioapic_res++;
2582 }
2583}
2584
2585void __init ioapic_insert_resources(void)
2586{
2587 struct resource *r = ioapic_resources;
2588 int i;
2589
2590 if (!r) {
2591 if (nr_ioapics > 0)
2592 pr_err("IO APIC resources couldn't be allocated.\n");
2593 return;
2594 }
2595
2596 for_each_ioapic(i) {
2597 insert_resource(&iomem_resource, r);
2598 r++;
2599 }
2600}
2601
2602int mp_find_ioapic(u32 gsi)
2603{
2604 int i;
2605
2606 if (nr_ioapics == 0)
2607 return -1;
2608
2609 /* Find the IOAPIC that manages this GSI. */
2610 for_each_ioapic(i) {
2611 struct mp_ioapic_gsi *gsi_cfg = mp_ioapic_gsi_routing(i);
2612
2613 if (gsi >= gsi_cfg->gsi_base && gsi <= gsi_cfg->gsi_end)
2614 return i;
2615 }
2616
2617 pr_err("ERROR: Unable to locate IOAPIC for GSI %d\n", gsi);
2618 return -1;
2619}
2620
2621int mp_find_ioapic_pin(int ioapic, u32 gsi)
2622{
2623 struct mp_ioapic_gsi *gsi_cfg;
2624
2625 if (WARN_ON(ioapic < 0))
2626 return -1;
2627
2628 gsi_cfg = mp_ioapic_gsi_routing(ioapic);
2629 if (WARN_ON(gsi > gsi_cfg->gsi_end))
2630 return -1;
2631
2632 return gsi - gsi_cfg->gsi_base;
2633}
2634
2635static int bad_ioapic_register(int idx)
2636{
2637 union IO_APIC_reg_00 reg_00;
2638 union IO_APIC_reg_01 reg_01;
2639 union IO_APIC_reg_02 reg_02;
2640
2641 reg_00.raw = io_apic_read(idx, 0);
2642 reg_01.raw = io_apic_read(idx, 1);
2643 reg_02.raw = io_apic_read(idx, 2);
2644
2645 if (reg_00.raw == -1 && reg_01.raw == -1 && reg_02.raw == -1) {
2646 pr_warn("I/O APIC 0x%x registers return all ones, skipping!\n",
2647 mpc_ioapic_addr(idx));
2648 return 1;
2649 }
2650
2651 return 0;
2652}
2653
2654static int find_free_ioapic_entry(void)
2655{
2656 for (int idx = 0; idx < MAX_IO_APICS; idx++) {
2657 if (ioapics[idx].nr_registers == 0)
2658 return idx;
2659 }
2660 return MAX_IO_APICS;
2661}
2662
2663/**
2664 * mp_register_ioapic - Register an IOAPIC device
2665 * @id: hardware IOAPIC ID
2666 * @address: physical address of IOAPIC register area
2667 * @gsi_base: base of GSI associated with the IOAPIC
2668 * @cfg: configuration information for the IOAPIC
2669 */
2670int mp_register_ioapic(int id, u32 address, u32 gsi_base, struct ioapic_domain_cfg *cfg)
2671{
2672 bool hotplug = !!ioapic_initialized;
2673 struct mp_ioapic_gsi *gsi_cfg;
2674 int idx, ioapic, entries;
2675 u32 gsi_end;
2676
2677 if (!address) {
2678 pr_warn("Bogus (zero) I/O APIC address found, skipping!\n");
2679 return -EINVAL;
2680 }
2681
2682 for_each_ioapic(ioapic) {
2683 if (ioapics[ioapic].mp_config.apicaddr == address) {
2684 pr_warn("address 0x%x conflicts with IOAPIC%d\n", address, ioapic);
2685 return -EEXIST;
2686 }
2687 }
2688
2689 idx = find_free_ioapic_entry();
2690 if (idx >= MAX_IO_APICS) {
2691 pr_warn("Max # of I/O APICs (%d) exceeded (found %d), skipping\n",
2692 MAX_IO_APICS, idx);
2693 return -ENOSPC;
2694 }
2695
2696 ioapics[idx].mp_config.type = MP_IOAPIC;
2697 ioapics[idx].mp_config.flags = MPC_APIC_USABLE;
2698 ioapics[idx].mp_config.apicaddr = address;
2699
2700 io_apic_set_fixmap(FIX_IO_APIC_BASE_0 + idx, address);
2701 if (bad_ioapic_register(idx)) {
2702 clear_fixmap(FIX_IO_APIC_BASE_0 + idx);
2703 return -ENODEV;
2704 }
2705
2706 ioapics[idx].mp_config.apicid = io_apic_unique_id(idx, id);
2707 ioapics[idx].mp_config.apicver = io_apic_get_version(idx);
2708
2709 /*
2710 * Build basic GSI lookup table to facilitate gsi->io_apic lookups
2711 * and to prevent reprogramming of IOAPIC pins (PCI GSIs).
2712 */
2713 entries = io_apic_get_redir_entries(idx);
2714 gsi_end = gsi_base + entries - 1;
2715 for_each_ioapic(ioapic) {
2716 gsi_cfg = mp_ioapic_gsi_routing(ioapic);
2717 if ((gsi_base >= gsi_cfg->gsi_base &&
2718 gsi_base <= gsi_cfg->gsi_end) ||
2719 (gsi_end >= gsi_cfg->gsi_base &&
2720 gsi_end <= gsi_cfg->gsi_end)) {
2721 pr_warn("GSI range [%u-%u] for new IOAPIC conflicts with GSI[%u-%u]\n",
2722 gsi_base, gsi_end, gsi_cfg->gsi_base, gsi_cfg->gsi_end);
2723 clear_fixmap(FIX_IO_APIC_BASE_0 + idx);
2724 return -ENOSPC;
2725 }
2726 }
2727 gsi_cfg = mp_ioapic_gsi_routing(idx);
2728 gsi_cfg->gsi_base = gsi_base;
2729 gsi_cfg->gsi_end = gsi_end;
2730
2731 ioapics[idx].irqdomain = NULL;
2732 ioapics[idx].irqdomain_cfg = *cfg;
2733
2734 /*
2735 * If mp_register_ioapic() is called during early boot stage when
2736 * walking ACPI/DT tables, it's too early to create irqdomain,
2737 * we are still using bootmem allocator. So delay it to setup_IO_APIC().
2738 */
2739 if (hotplug) {
2740 if (mp_irqdomain_create(idx)) {
2741 clear_fixmap(FIX_IO_APIC_BASE_0 + idx);
2742 return -ENOMEM;
2743 }
2744 alloc_ioapic_saved_registers(idx);
2745 }
2746
2747 if (gsi_cfg->gsi_end >= gsi_top)
2748 gsi_top = gsi_cfg->gsi_end + 1;
2749 if (nr_ioapics <= idx)
2750 nr_ioapics = idx + 1;
2751
2752 /* Set nr_registers to mark entry present */
2753 ioapics[idx].nr_registers = entries;
2754
2755 pr_info("IOAPIC[%d]: apic_id %d, version %d, address 0x%x, GSI %d-%d\n",
2756 idx, mpc_ioapic_id(idx), mpc_ioapic_ver(idx), mpc_ioapic_addr(idx),
2757 gsi_cfg->gsi_base, gsi_cfg->gsi_end);
2758
2759 return 0;
2760}
2761
2762int mp_unregister_ioapic(u32 gsi_base)
2763{
2764 int ioapic, pin;
2765 int found = 0;
2766
2767 for_each_ioapic(ioapic) {
2768 if (ioapics[ioapic].gsi_config.gsi_base == gsi_base) {
2769 found = 1;
2770 break;
2771 }
2772 }
2773
2774 if (!found) {
2775 pr_warn("can't find IOAPIC for GSI %d\n", gsi_base);
2776 return -ENODEV;
2777 }
2778
2779 for_each_pin(ioapic, pin) {
2780 u32 gsi = mp_pin_to_gsi(ioapic, pin);
2781 int irq = mp_map_gsi_to_irq(gsi, 0, NULL);
2782 struct mp_chip_data *data;
2783
2784 if (irq >= 0) {
2785 data = irq_get_chip_data(irq);
2786 if (data && data->count) {
2787 pr_warn("pin%d on IOAPIC%d is still in use.\n", pin, ioapic);
2788 return -EBUSY;
2789 }
2790 }
2791 }
2792
2793 /* Mark entry not present */
2794 ioapics[ioapic].nr_registers = 0;
2795 ioapic_destroy_irqdomain(ioapic);
2796 free_ioapic_saved_registers(ioapic);
2797 if (ioapics[ioapic].iomem_res)
2798 release_resource(ioapics[ioapic].iomem_res);
2799 clear_fixmap(FIX_IO_APIC_BASE_0 + ioapic);
2800 memset(&ioapics[ioapic], 0, sizeof(ioapics[ioapic]));
2801
2802 return 0;
2803}
2804
2805int mp_ioapic_registered(u32 gsi_base)
2806{
2807 int ioapic;
2808
2809 for_each_ioapic(ioapic)
2810 if (ioapics[ioapic].gsi_config.gsi_base == gsi_base)
2811 return 1;
2812
2813 return 0;
2814}
2815
2816static void mp_irqdomain_get_attr(u32 gsi, struct mp_chip_data *data,
2817 struct irq_alloc_info *info)
2818{
2819 if (info && info->ioapic.valid) {
2820 data->is_level = info->ioapic.is_level;
2821 data->active_low = info->ioapic.active_low;
2822 } else if (__acpi_get_override_irq(gsi, &data->is_level, &data->active_low) < 0) {
2823 /* PCI interrupts are always active low level triggered. */
2824 data->is_level = true;
2825 data->active_low = true;
2826 }
2827}
2828
2829/*
2830 * Configure the I/O-APIC specific fields in the routing entry.
2831 *
2832 * This is important to setup the I/O-APIC specific bits (is_level,
2833 * active_low, masked) because the underlying parent domain will only
2834 * provide the routing information and is oblivious of the I/O-APIC
2835 * specific bits.
2836 *
2837 * The entry is just preconfigured at this point and not written into the
2838 * RTE. This happens later during activation which will fill in the actual
2839 * routing information.
2840 */
2841static void mp_preconfigure_entry(struct mp_chip_data *data)
2842{
2843 struct IO_APIC_route_entry *entry = &data->entry;
2844
2845 memset(entry, 0, sizeof(*entry));
2846 entry->is_level = data->is_level;
2847 entry->active_low = data->active_low;
2848 /*
2849 * Mask level triggered irqs. Edge triggered irqs are masked
2850 * by the irq core code in case they fire.
2851 */
2852 entry->masked = data->is_level;
2853}
2854
2855int mp_irqdomain_alloc(struct irq_domain *domain, unsigned int virq,
2856 unsigned int nr_irqs, void *arg)
2857{
2858 struct irq_alloc_info *info = arg;
2859 struct mp_chip_data *data;
2860 struct irq_data *irq_data;
2861 int ret, ioapic, pin;
2862 unsigned long flags;
2863
2864 if (!info || nr_irqs > 1)
2865 return -EINVAL;
2866 irq_data = irq_domain_get_irq_data(domain, virq);
2867 if (!irq_data)
2868 return -EINVAL;
2869
2870 ioapic = mp_irqdomain_ioapic_idx(domain);
2871 pin = info->ioapic.pin;
2872 if (irq_find_mapping(domain, (irq_hw_number_t)pin) > 0)
2873 return -EEXIST;
2874
2875 data = kzalloc(sizeof(*data), GFP_KERNEL);
2876 if (!data)
2877 return -ENOMEM;
2878
2879 ret = irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, info);
2880 if (ret < 0)
2881 goto free_data;
2882
2883 INIT_LIST_HEAD(&data->irq_2_pin);
2884 irq_data->hwirq = info->ioapic.pin;
2885 irq_data->chip = (domain->parent == x86_vector_domain) ?
2886 &ioapic_chip : &ioapic_ir_chip;
2887 irq_data->chip_data = data;
2888 mp_irqdomain_get_attr(mp_pin_to_gsi(ioapic, pin), data, info);
2889
2890 if (!add_pin_to_irq_node(data, ioapic_alloc_attr_node(info), ioapic, pin)) {
2891 ret = -ENOMEM;
2892 goto free_irqs;
2893 }
2894
2895 mp_preconfigure_entry(data);
2896 mp_register_handler(virq, data->is_level);
2897
2898 local_irq_save(flags);
2899 if (virq < nr_legacy_irqs())
2900 legacy_pic->mask(virq);
2901 local_irq_restore(flags);
2902
2903 apic_pr_verbose("IOAPIC[%d]: Preconfigured routing entry (%d-%d -> IRQ %d Level:%i ActiveLow:%i)\n",
2904 ioapic, mpc_ioapic_id(ioapic), pin, virq, data->is_level, data->active_low);
2905 return 0;
2906
2907free_irqs:
2908 irq_domain_free_irqs_parent(domain, virq, nr_irqs);
2909free_data:
2910 kfree(data);
2911 return ret;
2912}
2913
2914void mp_irqdomain_free(struct irq_domain *domain, unsigned int virq,
2915 unsigned int nr_irqs)
2916{
2917 struct irq_data *irq_data;
2918 struct mp_chip_data *data;
2919
2920 BUG_ON(nr_irqs != 1);
2921 irq_data = irq_domain_get_irq_data(domain, virq);
2922 if (irq_data && irq_data->chip_data) {
2923 data = irq_data->chip_data;
2924 __remove_pin_from_irq(data, mp_irqdomain_ioapic_idx(domain), (int)irq_data->hwirq);
2925 WARN_ON(!list_empty(&data->irq_2_pin));
2926 kfree(irq_data->chip_data);
2927 }
2928 irq_domain_free_irqs_top(domain, virq, nr_irqs);
2929}
2930
2931int mp_irqdomain_activate(struct irq_domain *domain, struct irq_data *irq_data, bool reserve)
2932{
2933 guard(raw_spinlock_irqsave)(&ioapic_lock);
2934 ioapic_configure_entry(irq_data);
2935 return 0;
2936}
2937
2938void mp_irqdomain_deactivate(struct irq_domain *domain,
2939 struct irq_data *irq_data)
2940{
2941 /* It won't be called for IRQ with multiple IOAPIC pins associated */
2942 ioapic_mask_entry(mp_irqdomain_ioapic_idx(domain), (int)irq_data->hwirq);
2943}
2944
2945int mp_irqdomain_ioapic_idx(struct irq_domain *domain)
2946{
2947 return (int)(long)domain->host_data;
2948}
2949
2950const struct irq_domain_ops mp_ioapic_irqdomain_ops = {
2951 .alloc = mp_irqdomain_alloc,
2952 .free = mp_irqdomain_free,
2953 .activate = mp_irqdomain_activate,
2954 .deactivate = mp_irqdomain_deactivate,
2955};
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Intel IO-APIC support for multi-Pentium hosts.
4 *
5 * Copyright (C) 1997, 1998, 1999, 2000, 2009 Ingo Molnar, Hajnalka Szabo
6 *
7 * Many thanks to Stig Venaas for trying out countless experimental
8 * patches and reporting/debugging problems patiently!
9 *
10 * (c) 1999, Multiple IO-APIC support, developed by
11 * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
12 * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
13 * further tested and cleaned up by Zach Brown <zab@redhat.com>
14 * and Ingo Molnar <mingo@redhat.com>
15 *
16 * Fixes
17 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
18 * thanks to Eric Gilmore
19 * and Rolf G. Tews
20 * for testing these extensively
21 * Paul Diefenbaugh : Added full ACPI support
22 *
23 * Historical information which is worth to be preserved:
24 *
25 * - SiS APIC rmw bug:
26 *
27 * We used to have a workaround for a bug in SiS chips which
28 * required to rewrite the index register for a read-modify-write
29 * operation as the chip lost the index information which was
30 * setup for the read already. We cache the data now, so that
31 * workaround has been removed.
32 */
33
34#include <linux/mm.h>
35#include <linux/interrupt.h>
36#include <linux/irq.h>
37#include <linux/init.h>
38#include <linux/delay.h>
39#include <linux/sched.h>
40#include <linux/pci.h>
41#include <linux/mc146818rtc.h>
42#include <linux/compiler.h>
43#include <linux/acpi.h>
44#include <linux/export.h>
45#include <linux/syscore_ops.h>
46#include <linux/freezer.h>
47#include <linux/kthread.h>
48#include <linux/jiffies.h> /* time_after() */
49#include <linux/slab.h>
50#include <linux/memblock.h>
51#include <linux/msi.h>
52
53#include <asm/irqdomain.h>
54#include <asm/io.h>
55#include <asm/smp.h>
56#include <asm/cpu.h>
57#include <asm/desc.h>
58#include <asm/proto.h>
59#include <asm/acpi.h>
60#include <asm/dma.h>
61#include <asm/timer.h>
62#include <asm/time.h>
63#include <asm/i8259.h>
64#include <asm/setup.h>
65#include <asm/irq_remapping.h>
66#include <asm/hw_irq.h>
67#include <asm/apic.h>
68
69#define for_each_ioapic(idx) \
70 for ((idx) = 0; (idx) < nr_ioapics; (idx)++)
71#define for_each_ioapic_reverse(idx) \
72 for ((idx) = nr_ioapics - 1; (idx) >= 0; (idx)--)
73#define for_each_pin(idx, pin) \
74 for ((pin) = 0; (pin) < ioapics[(idx)].nr_registers; (pin)++)
75#define for_each_ioapic_pin(idx, pin) \
76 for_each_ioapic((idx)) \
77 for_each_pin((idx), (pin))
78#define for_each_irq_pin(entry, head) \
79 list_for_each_entry(entry, &head, list)
80
81static DEFINE_RAW_SPINLOCK(ioapic_lock);
82static DEFINE_MUTEX(ioapic_mutex);
83static unsigned int ioapic_dynirq_base;
84static int ioapic_initialized;
85
86struct irq_pin_list {
87 struct list_head list;
88 int apic, pin;
89};
90
91struct mp_chip_data {
92 struct list_head irq_2_pin;
93 struct IO_APIC_route_entry entry;
94 bool is_level;
95 bool active_low;
96 bool isa_irq;
97 u32 count;
98};
99
100struct mp_ioapic_gsi {
101 u32 gsi_base;
102 u32 gsi_end;
103};
104
105static struct ioapic {
106 /*
107 * # of IRQ routing registers
108 */
109 int nr_registers;
110 /*
111 * Saved state during suspend/resume, or while enabling intr-remap.
112 */
113 struct IO_APIC_route_entry *saved_registers;
114 /* I/O APIC config */
115 struct mpc_ioapic mp_config;
116 /* IO APIC gsi routing info */
117 struct mp_ioapic_gsi gsi_config;
118 struct ioapic_domain_cfg irqdomain_cfg;
119 struct irq_domain *irqdomain;
120 struct resource *iomem_res;
121} ioapics[MAX_IO_APICS];
122
123#define mpc_ioapic_ver(ioapic_idx) ioapics[ioapic_idx].mp_config.apicver
124
125int mpc_ioapic_id(int ioapic_idx)
126{
127 return ioapics[ioapic_idx].mp_config.apicid;
128}
129
130unsigned int mpc_ioapic_addr(int ioapic_idx)
131{
132 return ioapics[ioapic_idx].mp_config.apicaddr;
133}
134
135static inline struct mp_ioapic_gsi *mp_ioapic_gsi_routing(int ioapic_idx)
136{
137 return &ioapics[ioapic_idx].gsi_config;
138}
139
140static inline int mp_ioapic_pin_count(int ioapic)
141{
142 struct mp_ioapic_gsi *gsi_cfg = mp_ioapic_gsi_routing(ioapic);
143
144 return gsi_cfg->gsi_end - gsi_cfg->gsi_base + 1;
145}
146
147static inline u32 mp_pin_to_gsi(int ioapic, int pin)
148{
149 return mp_ioapic_gsi_routing(ioapic)->gsi_base + pin;
150}
151
152static inline bool mp_is_legacy_irq(int irq)
153{
154 return irq >= 0 && irq < nr_legacy_irqs();
155}
156
157static inline struct irq_domain *mp_ioapic_irqdomain(int ioapic)
158{
159 return ioapics[ioapic].irqdomain;
160}
161
162int nr_ioapics;
163
164/* The one past the highest gsi number used */
165u32 gsi_top;
166
167/* MP IRQ source entries */
168struct mpc_intsrc mp_irqs[MAX_IRQ_SOURCES];
169
170/* # of MP IRQ source entries */
171int mp_irq_entries;
172
173#ifdef CONFIG_EISA
174int mp_bus_id_to_type[MAX_MP_BUSSES];
175#endif
176
177DECLARE_BITMAP(mp_bus_not_pci, MAX_MP_BUSSES);
178
179int skip_ioapic_setup;
180
181/**
182 * disable_ioapic_support() - disables ioapic support at runtime
183 */
184void disable_ioapic_support(void)
185{
186#ifdef CONFIG_PCI
187 noioapicquirk = 1;
188 noioapicreroute = -1;
189#endif
190 skip_ioapic_setup = 1;
191}
192
193static int __init parse_noapic(char *str)
194{
195 /* disable IO-APIC */
196 disable_ioapic_support();
197 return 0;
198}
199early_param("noapic", parse_noapic);
200
201/* Will be called in mpparse/ACPI codes for saving IRQ info */
202void mp_save_irq(struct mpc_intsrc *m)
203{
204 int i;
205
206 apic_printk(APIC_VERBOSE, "Int: type %d, pol %d, trig %d, bus %02x,"
207 " IRQ %02x, APIC ID %x, APIC INT %02x\n",
208 m->irqtype, m->irqflag & 3, (m->irqflag >> 2) & 3, m->srcbus,
209 m->srcbusirq, m->dstapic, m->dstirq);
210
211 for (i = 0; i < mp_irq_entries; i++) {
212 if (!memcmp(&mp_irqs[i], m, sizeof(*m)))
213 return;
214 }
215
216 memcpy(&mp_irqs[mp_irq_entries], m, sizeof(*m));
217 if (++mp_irq_entries == MAX_IRQ_SOURCES)
218 panic("Max # of irq sources exceeded!!\n");
219}
220
221static void alloc_ioapic_saved_registers(int idx)
222{
223 size_t size;
224
225 if (ioapics[idx].saved_registers)
226 return;
227
228 size = sizeof(struct IO_APIC_route_entry) * ioapics[idx].nr_registers;
229 ioapics[idx].saved_registers = kzalloc(size, GFP_KERNEL);
230 if (!ioapics[idx].saved_registers)
231 pr_err("IOAPIC %d: suspend/resume impossible!\n", idx);
232}
233
234static void free_ioapic_saved_registers(int idx)
235{
236 kfree(ioapics[idx].saved_registers);
237 ioapics[idx].saved_registers = NULL;
238}
239
240int __init arch_early_ioapic_init(void)
241{
242 int i;
243
244 if (!nr_legacy_irqs())
245 io_apic_irqs = ~0UL;
246
247 for_each_ioapic(i)
248 alloc_ioapic_saved_registers(i);
249
250 return 0;
251}
252
253struct io_apic {
254 unsigned int index;
255 unsigned int unused[3];
256 unsigned int data;
257 unsigned int unused2[11];
258 unsigned int eoi;
259};
260
261static __attribute_const__ struct io_apic __iomem *io_apic_base(int idx)
262{
263 return (void __iomem *) __fix_to_virt(FIX_IO_APIC_BASE_0 + idx)
264 + (mpc_ioapic_addr(idx) & ~PAGE_MASK);
265}
266
267static inline void io_apic_eoi(unsigned int apic, unsigned int vector)
268{
269 struct io_apic __iomem *io_apic = io_apic_base(apic);
270 writel(vector, &io_apic->eoi);
271}
272
273unsigned int native_io_apic_read(unsigned int apic, unsigned int reg)
274{
275 struct io_apic __iomem *io_apic = io_apic_base(apic);
276 writel(reg, &io_apic->index);
277 return readl(&io_apic->data);
278}
279
280static void io_apic_write(unsigned int apic, unsigned int reg,
281 unsigned int value)
282{
283 struct io_apic __iomem *io_apic = io_apic_base(apic);
284
285 writel(reg, &io_apic->index);
286 writel(value, &io_apic->data);
287}
288
289static struct IO_APIC_route_entry __ioapic_read_entry(int apic, int pin)
290{
291 struct IO_APIC_route_entry entry;
292
293 entry.w1 = io_apic_read(apic, 0x10 + 2 * pin);
294 entry.w2 = io_apic_read(apic, 0x11 + 2 * pin);
295
296 return entry;
297}
298
299static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin)
300{
301 struct IO_APIC_route_entry entry;
302 unsigned long flags;
303
304 raw_spin_lock_irqsave(&ioapic_lock, flags);
305 entry = __ioapic_read_entry(apic, pin);
306 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
307
308 return entry;
309}
310
311/*
312 * When we write a new IO APIC routing entry, we need to write the high
313 * word first! If the mask bit in the low word is clear, we will enable
314 * the interrupt, and we need to make sure the entry is fully populated
315 * before that happens.
316 */
317static void __ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
318{
319 io_apic_write(apic, 0x11 + 2*pin, e.w2);
320 io_apic_write(apic, 0x10 + 2*pin, e.w1);
321}
322
323static void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
324{
325 unsigned long flags;
326
327 raw_spin_lock_irqsave(&ioapic_lock, flags);
328 __ioapic_write_entry(apic, pin, e);
329 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
330}
331
332/*
333 * When we mask an IO APIC routing entry, we need to write the low
334 * word first, in order to set the mask bit before we change the
335 * high bits!
336 */
337static void ioapic_mask_entry(int apic, int pin)
338{
339 struct IO_APIC_route_entry e = { .masked = true };
340 unsigned long flags;
341
342 raw_spin_lock_irqsave(&ioapic_lock, flags);
343 io_apic_write(apic, 0x10 + 2*pin, e.w1);
344 io_apic_write(apic, 0x11 + 2*pin, e.w2);
345 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
346}
347
348/*
349 * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
350 * shared ISA-space IRQs, so we have to support them. We are super
351 * fast in the common case, and fast for shared ISA-space IRQs.
352 */
353static int __add_pin_to_irq_node(struct mp_chip_data *data,
354 int node, int apic, int pin)
355{
356 struct irq_pin_list *entry;
357
358 /* don't allow duplicates */
359 for_each_irq_pin(entry, data->irq_2_pin)
360 if (entry->apic == apic && entry->pin == pin)
361 return 0;
362
363 entry = kzalloc_node(sizeof(struct irq_pin_list), GFP_ATOMIC, node);
364 if (!entry) {
365 pr_err("can not alloc irq_pin_list (%d,%d,%d)\n",
366 node, apic, pin);
367 return -ENOMEM;
368 }
369 entry->apic = apic;
370 entry->pin = pin;
371 list_add_tail(&entry->list, &data->irq_2_pin);
372
373 return 0;
374}
375
376static void __remove_pin_from_irq(struct mp_chip_data *data, int apic, int pin)
377{
378 struct irq_pin_list *tmp, *entry;
379
380 list_for_each_entry_safe(entry, tmp, &data->irq_2_pin, list)
381 if (entry->apic == apic && entry->pin == pin) {
382 list_del(&entry->list);
383 kfree(entry);
384 return;
385 }
386}
387
388static void add_pin_to_irq_node(struct mp_chip_data *data,
389 int node, int apic, int pin)
390{
391 if (__add_pin_to_irq_node(data, node, apic, pin))
392 panic("IO-APIC: failed to add irq-pin. Can not proceed\n");
393}
394
395/*
396 * Reroute an IRQ to a different pin.
397 */
398static void __init replace_pin_at_irq_node(struct mp_chip_data *data, int node,
399 int oldapic, int oldpin,
400 int newapic, int newpin)
401{
402 struct irq_pin_list *entry;
403
404 for_each_irq_pin(entry, data->irq_2_pin) {
405 if (entry->apic == oldapic && entry->pin == oldpin) {
406 entry->apic = newapic;
407 entry->pin = newpin;
408 /* every one is different, right? */
409 return;
410 }
411 }
412
413 /* old apic/pin didn't exist, so just add new ones */
414 add_pin_to_irq_node(data, node, newapic, newpin);
415}
416
417static void io_apic_modify_irq(struct mp_chip_data *data, bool masked,
418 void (*final)(struct irq_pin_list *entry))
419{
420 struct irq_pin_list *entry;
421
422 data->entry.masked = masked;
423
424 for_each_irq_pin(entry, data->irq_2_pin) {
425 io_apic_write(entry->apic, 0x10 + 2 * entry->pin, data->entry.w1);
426 if (final)
427 final(entry);
428 }
429}
430
431static void io_apic_sync(struct irq_pin_list *entry)
432{
433 /*
434 * Synchronize the IO-APIC and the CPU by doing
435 * a dummy read from the IO-APIC
436 */
437 struct io_apic __iomem *io_apic;
438
439 io_apic = io_apic_base(entry->apic);
440 readl(&io_apic->data);
441}
442
443static void mask_ioapic_irq(struct irq_data *irq_data)
444{
445 struct mp_chip_data *data = irq_data->chip_data;
446 unsigned long flags;
447
448 raw_spin_lock_irqsave(&ioapic_lock, flags);
449 io_apic_modify_irq(data, true, &io_apic_sync);
450 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
451}
452
453static void __unmask_ioapic(struct mp_chip_data *data)
454{
455 io_apic_modify_irq(data, false, NULL);
456}
457
458static void unmask_ioapic_irq(struct irq_data *irq_data)
459{
460 struct mp_chip_data *data = irq_data->chip_data;
461 unsigned long flags;
462
463 raw_spin_lock_irqsave(&ioapic_lock, flags);
464 __unmask_ioapic(data);
465 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
466}
467
468/*
469 * IO-APIC versions below 0x20 don't support EOI register.
470 * For the record, here is the information about various versions:
471 * 0Xh 82489DX
472 * 1Xh I/OAPIC or I/O(x)APIC which are not PCI 2.2 Compliant
473 * 2Xh I/O(x)APIC which is PCI 2.2 Compliant
474 * 30h-FFh Reserved
475 *
476 * Some of the Intel ICH Specs (ICH2 to ICH5) documents the io-apic
477 * version as 0x2. This is an error with documentation and these ICH chips
478 * use io-apic's of version 0x20.
479 *
480 * For IO-APIC's with EOI register, we use that to do an explicit EOI.
481 * Otherwise, we simulate the EOI message manually by changing the trigger
482 * mode to edge and then back to level, with RTE being masked during this.
483 */
484static void __eoi_ioapic_pin(int apic, int pin, int vector)
485{
486 if (mpc_ioapic_ver(apic) >= 0x20) {
487 io_apic_eoi(apic, vector);
488 } else {
489 struct IO_APIC_route_entry entry, entry1;
490
491 entry = entry1 = __ioapic_read_entry(apic, pin);
492
493 /*
494 * Mask the entry and change the trigger mode to edge.
495 */
496 entry1.masked = true;
497 entry1.is_level = false;
498
499 __ioapic_write_entry(apic, pin, entry1);
500
501 /*
502 * Restore the previous level triggered entry.
503 */
504 __ioapic_write_entry(apic, pin, entry);
505 }
506}
507
508static void eoi_ioapic_pin(int vector, struct mp_chip_data *data)
509{
510 unsigned long flags;
511 struct irq_pin_list *entry;
512
513 raw_spin_lock_irqsave(&ioapic_lock, flags);
514 for_each_irq_pin(entry, data->irq_2_pin)
515 __eoi_ioapic_pin(entry->apic, entry->pin, vector);
516 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
517}
518
519static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
520{
521 struct IO_APIC_route_entry entry;
522
523 /* Check delivery_mode to be sure we're not clearing an SMI pin */
524 entry = ioapic_read_entry(apic, pin);
525 if (entry.delivery_mode == APIC_DELIVERY_MODE_SMI)
526 return;
527
528 /*
529 * Make sure the entry is masked and re-read the contents to check
530 * if it is a level triggered pin and if the remote-IRR is set.
531 */
532 if (!entry.masked) {
533 entry.masked = true;
534 ioapic_write_entry(apic, pin, entry);
535 entry = ioapic_read_entry(apic, pin);
536 }
537
538 if (entry.irr) {
539 unsigned long flags;
540
541 /*
542 * Make sure the trigger mode is set to level. Explicit EOI
543 * doesn't clear the remote-IRR if the trigger mode is not
544 * set to level.
545 */
546 if (!entry.is_level) {
547 entry.is_level = true;
548 ioapic_write_entry(apic, pin, entry);
549 }
550 raw_spin_lock_irqsave(&ioapic_lock, flags);
551 __eoi_ioapic_pin(apic, pin, entry.vector);
552 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
553 }
554
555 /*
556 * Clear the rest of the bits in the IO-APIC RTE except for the mask
557 * bit.
558 */
559 ioapic_mask_entry(apic, pin);
560 entry = ioapic_read_entry(apic, pin);
561 if (entry.irr)
562 pr_err("Unable to reset IRR for apic: %d, pin :%d\n",
563 mpc_ioapic_id(apic), pin);
564}
565
566void clear_IO_APIC (void)
567{
568 int apic, pin;
569
570 for_each_ioapic_pin(apic, pin)
571 clear_IO_APIC_pin(apic, pin);
572}
573
574#ifdef CONFIG_X86_32
575/*
576 * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to
577 * specific CPU-side IRQs.
578 */
579
580#define MAX_PIRQS 8
581static int pirq_entries[MAX_PIRQS] = {
582 [0 ... MAX_PIRQS - 1] = -1
583};
584
585static int __init ioapic_pirq_setup(char *str)
586{
587 int i, max;
588 int ints[MAX_PIRQS+1];
589
590 get_options(str, ARRAY_SIZE(ints), ints);
591
592 apic_printk(APIC_VERBOSE, KERN_INFO
593 "PIRQ redirection, working around broken MP-BIOS.\n");
594 max = MAX_PIRQS;
595 if (ints[0] < MAX_PIRQS)
596 max = ints[0];
597
598 for (i = 0; i < max; i++) {
599 apic_printk(APIC_VERBOSE, KERN_DEBUG
600 "... PIRQ%d -> IRQ %d\n", i, ints[i+1]);
601 /*
602 * PIRQs are mapped upside down, usually.
603 */
604 pirq_entries[MAX_PIRQS-i-1] = ints[i+1];
605 }
606 return 1;
607}
608
609__setup("pirq=", ioapic_pirq_setup);
610#endif /* CONFIG_X86_32 */
611
612/*
613 * Saves all the IO-APIC RTE's
614 */
615int save_ioapic_entries(void)
616{
617 int apic, pin;
618 int err = 0;
619
620 for_each_ioapic(apic) {
621 if (!ioapics[apic].saved_registers) {
622 err = -ENOMEM;
623 continue;
624 }
625
626 for_each_pin(apic, pin)
627 ioapics[apic].saved_registers[pin] =
628 ioapic_read_entry(apic, pin);
629 }
630
631 return err;
632}
633
634/*
635 * Mask all IO APIC entries.
636 */
637void mask_ioapic_entries(void)
638{
639 int apic, pin;
640
641 for_each_ioapic(apic) {
642 if (!ioapics[apic].saved_registers)
643 continue;
644
645 for_each_pin(apic, pin) {
646 struct IO_APIC_route_entry entry;
647
648 entry = ioapics[apic].saved_registers[pin];
649 if (!entry.masked) {
650 entry.masked = true;
651 ioapic_write_entry(apic, pin, entry);
652 }
653 }
654 }
655}
656
657/*
658 * Restore IO APIC entries which was saved in the ioapic structure.
659 */
660int restore_ioapic_entries(void)
661{
662 int apic, pin;
663
664 for_each_ioapic(apic) {
665 if (!ioapics[apic].saved_registers)
666 continue;
667
668 for_each_pin(apic, pin)
669 ioapic_write_entry(apic, pin,
670 ioapics[apic].saved_registers[pin]);
671 }
672 return 0;
673}
674
675/*
676 * Find the IRQ entry number of a certain pin.
677 */
678static int find_irq_entry(int ioapic_idx, int pin, int type)
679{
680 int i;
681
682 for (i = 0; i < mp_irq_entries; i++)
683 if (mp_irqs[i].irqtype == type &&
684 (mp_irqs[i].dstapic == mpc_ioapic_id(ioapic_idx) ||
685 mp_irqs[i].dstapic == MP_APIC_ALL) &&
686 mp_irqs[i].dstirq == pin)
687 return i;
688
689 return -1;
690}
691
692/*
693 * Find the pin to which IRQ[irq] (ISA) is connected
694 */
695static int __init find_isa_irq_pin(int irq, int type)
696{
697 int i;
698
699 for (i = 0; i < mp_irq_entries; i++) {
700 int lbus = mp_irqs[i].srcbus;
701
702 if (test_bit(lbus, mp_bus_not_pci) &&
703 (mp_irqs[i].irqtype == type) &&
704 (mp_irqs[i].srcbusirq == irq))
705
706 return mp_irqs[i].dstirq;
707 }
708 return -1;
709}
710
711static int __init find_isa_irq_apic(int irq, int type)
712{
713 int i;
714
715 for (i = 0; i < mp_irq_entries; i++) {
716 int lbus = mp_irqs[i].srcbus;
717
718 if (test_bit(lbus, mp_bus_not_pci) &&
719 (mp_irqs[i].irqtype == type) &&
720 (mp_irqs[i].srcbusirq == irq))
721 break;
722 }
723
724 if (i < mp_irq_entries) {
725 int ioapic_idx;
726
727 for_each_ioapic(ioapic_idx)
728 if (mpc_ioapic_id(ioapic_idx) == mp_irqs[i].dstapic)
729 return ioapic_idx;
730 }
731
732 return -1;
733}
734
735static bool irq_active_low(int idx)
736{
737 int bus = mp_irqs[idx].srcbus;
738
739 /*
740 * Determine IRQ line polarity (high active or low active):
741 */
742 switch (mp_irqs[idx].irqflag & MP_IRQPOL_MASK) {
743 case MP_IRQPOL_DEFAULT:
744 /*
745 * Conforms to spec, ie. bus-type dependent polarity. PCI
746 * defaults to low active. [E]ISA defaults to high active.
747 */
748 return !test_bit(bus, mp_bus_not_pci);
749 case MP_IRQPOL_ACTIVE_HIGH:
750 return false;
751 case MP_IRQPOL_RESERVED:
752 pr_warn("IOAPIC: Invalid polarity: 2, defaulting to low\n");
753 fallthrough;
754 case MP_IRQPOL_ACTIVE_LOW:
755 default: /* Pointless default required due to do gcc stupidity */
756 return true;
757 }
758}
759
760#ifdef CONFIG_EISA
761/*
762 * EISA Edge/Level control register, ELCR
763 */
764static bool EISA_ELCR(unsigned int irq)
765{
766 if (irq < nr_legacy_irqs()) {
767 unsigned int port = 0x4d0 + (irq >> 3);
768 return (inb(port) >> (irq & 7)) & 1;
769 }
770 apic_printk(APIC_VERBOSE, KERN_INFO
771 "Broken MPtable reports ISA irq %d\n", irq);
772 return false;
773}
774
775/*
776 * EISA interrupts are always active high and can be edge or level
777 * triggered depending on the ELCR value. If an interrupt is listed as
778 * EISA conforming in the MP table, that means its trigger type must be
779 * read in from the ELCR.
780 */
781static bool eisa_irq_is_level(int idx, int bus, bool level)
782{
783 switch (mp_bus_id_to_type[bus]) {
784 case MP_BUS_PCI:
785 case MP_BUS_ISA:
786 return level;
787 case MP_BUS_EISA:
788 return EISA_ELCR(mp_irqs[idx].srcbusirq);
789 }
790 pr_warn("IOAPIC: Invalid srcbus: %d defaulting to level\n", bus);
791 return true;
792}
793#else
794static inline int eisa_irq_is_level(int idx, int bus, bool level)
795{
796 return level;
797}
798#endif
799
800static bool irq_is_level(int idx)
801{
802 int bus = mp_irqs[idx].srcbus;
803 bool level;
804
805 /*
806 * Determine IRQ trigger mode (edge or level sensitive):
807 */
808 switch (mp_irqs[idx].irqflag & MP_IRQTRIG_MASK) {
809 case MP_IRQTRIG_DEFAULT:
810 /*
811 * Conforms to spec, ie. bus-type dependent trigger
812 * mode. PCI defaults to level, ISA to edge.
813 */
814 level = !test_bit(bus, mp_bus_not_pci);
815 /* Take EISA into account */
816 return eisa_irq_is_level(idx, bus, level);
817 case MP_IRQTRIG_EDGE:
818 return false;
819 case MP_IRQTRIG_RESERVED:
820 pr_warn("IOAPIC: Invalid trigger mode 2 defaulting to level\n");
821 fallthrough;
822 case MP_IRQTRIG_LEVEL:
823 default: /* Pointless default required due to do gcc stupidity */
824 return true;
825 }
826}
827
828static int __acpi_get_override_irq(u32 gsi, bool *trigger, bool *polarity)
829{
830 int ioapic, pin, idx;
831
832 if (skip_ioapic_setup)
833 return -1;
834
835 ioapic = mp_find_ioapic(gsi);
836 if (ioapic < 0)
837 return -1;
838
839 pin = mp_find_ioapic_pin(ioapic, gsi);
840 if (pin < 0)
841 return -1;
842
843 idx = find_irq_entry(ioapic, pin, mp_INT);
844 if (idx < 0)
845 return -1;
846
847 *trigger = irq_is_level(idx);
848 *polarity = irq_active_low(idx);
849 return 0;
850}
851
852#ifdef CONFIG_ACPI
853int acpi_get_override_irq(u32 gsi, int *is_level, int *active_low)
854{
855 *is_level = *active_low = 0;
856 return __acpi_get_override_irq(gsi, (bool *)is_level,
857 (bool *)active_low);
858}
859#endif
860
861void ioapic_set_alloc_attr(struct irq_alloc_info *info, int node,
862 int trigger, int polarity)
863{
864 init_irq_alloc_info(info, NULL);
865 info->type = X86_IRQ_ALLOC_TYPE_IOAPIC;
866 info->ioapic.node = node;
867 info->ioapic.is_level = trigger;
868 info->ioapic.active_low = polarity;
869 info->ioapic.valid = 1;
870}
871
872static void ioapic_copy_alloc_attr(struct irq_alloc_info *dst,
873 struct irq_alloc_info *src,
874 u32 gsi, int ioapic_idx, int pin)
875{
876 bool level, pol_low;
877
878 copy_irq_alloc_info(dst, src);
879 dst->type = X86_IRQ_ALLOC_TYPE_IOAPIC;
880 dst->devid = mpc_ioapic_id(ioapic_idx);
881 dst->ioapic.pin = pin;
882 dst->ioapic.valid = 1;
883 if (src && src->ioapic.valid) {
884 dst->ioapic.node = src->ioapic.node;
885 dst->ioapic.is_level = src->ioapic.is_level;
886 dst->ioapic.active_low = src->ioapic.active_low;
887 } else {
888 dst->ioapic.node = NUMA_NO_NODE;
889 if (__acpi_get_override_irq(gsi, &level, &pol_low) >= 0) {
890 dst->ioapic.is_level = level;
891 dst->ioapic.active_low = pol_low;
892 } else {
893 /*
894 * PCI interrupts are always active low level
895 * triggered.
896 */
897 dst->ioapic.is_level = true;
898 dst->ioapic.active_low = true;
899 }
900 }
901}
902
903static int ioapic_alloc_attr_node(struct irq_alloc_info *info)
904{
905 return (info && info->ioapic.valid) ? info->ioapic.node : NUMA_NO_NODE;
906}
907
908static void mp_register_handler(unsigned int irq, bool level)
909{
910 irq_flow_handler_t hdl;
911 bool fasteoi;
912
913 if (level) {
914 irq_set_status_flags(irq, IRQ_LEVEL);
915 fasteoi = true;
916 } else {
917 irq_clear_status_flags(irq, IRQ_LEVEL);
918 fasteoi = false;
919 }
920
921 hdl = fasteoi ? handle_fasteoi_irq : handle_edge_irq;
922 __irq_set_handler(irq, hdl, 0, fasteoi ? "fasteoi" : "edge");
923}
924
925static bool mp_check_pin_attr(int irq, struct irq_alloc_info *info)
926{
927 struct mp_chip_data *data = irq_get_chip_data(irq);
928
929 /*
930 * setup_IO_APIC_irqs() programs all legacy IRQs with default trigger
931 * and polarity attributes. So allow the first user to reprogram the
932 * pin with real trigger and polarity attributes.
933 */
934 if (irq < nr_legacy_irqs() && data->count == 1) {
935 if (info->ioapic.is_level != data->is_level)
936 mp_register_handler(irq, info->ioapic.is_level);
937 data->entry.is_level = data->is_level = info->ioapic.is_level;
938 data->entry.active_low = data->active_low = info->ioapic.active_low;
939 }
940
941 return data->is_level == info->ioapic.is_level &&
942 data->active_low == info->ioapic.active_low;
943}
944
945static int alloc_irq_from_domain(struct irq_domain *domain, int ioapic, u32 gsi,
946 struct irq_alloc_info *info)
947{
948 bool legacy = false;
949 int irq = -1;
950 int type = ioapics[ioapic].irqdomain_cfg.type;
951
952 switch (type) {
953 case IOAPIC_DOMAIN_LEGACY:
954 /*
955 * Dynamically allocate IRQ number for non-ISA IRQs in the first
956 * 16 GSIs on some weird platforms.
957 */
958 if (!ioapic_initialized || gsi >= nr_legacy_irqs())
959 irq = gsi;
960 legacy = mp_is_legacy_irq(irq);
961 break;
962 case IOAPIC_DOMAIN_STRICT:
963 irq = gsi;
964 break;
965 case IOAPIC_DOMAIN_DYNAMIC:
966 break;
967 default:
968 WARN(1, "ioapic: unknown irqdomain type %d\n", type);
969 return -1;
970 }
971
972 return __irq_domain_alloc_irqs(domain, irq, 1,
973 ioapic_alloc_attr_node(info),
974 info, legacy, NULL);
975}
976
977/*
978 * Need special handling for ISA IRQs because there may be multiple IOAPIC pins
979 * sharing the same ISA IRQ number and irqdomain only supports 1:1 mapping
980 * between IOAPIC pin and IRQ number. A typical IOAPIC has 24 pins, pin 0-15 are
981 * used for legacy IRQs and pin 16-23 are used for PCI IRQs (PIRQ A-H).
982 * When ACPI is disabled, only legacy IRQ numbers (IRQ0-15) are available, and
983 * some BIOSes may use MP Interrupt Source records to override IRQ numbers for
984 * PIRQs instead of reprogramming the interrupt routing logic. Thus there may be
985 * multiple pins sharing the same legacy IRQ number when ACPI is disabled.
986 */
987static int alloc_isa_irq_from_domain(struct irq_domain *domain,
988 int irq, int ioapic, int pin,
989 struct irq_alloc_info *info)
990{
991 struct mp_chip_data *data;
992 struct irq_data *irq_data = irq_get_irq_data(irq);
993 int node = ioapic_alloc_attr_node(info);
994
995 /*
996 * Legacy ISA IRQ has already been allocated, just add pin to
997 * the pin list associated with this IRQ and program the IOAPIC
998 * entry. The IOAPIC entry
999 */
1000 if (irq_data && irq_data->parent_data) {
1001 if (!mp_check_pin_attr(irq, info))
1002 return -EBUSY;
1003 if (__add_pin_to_irq_node(irq_data->chip_data, node, ioapic,
1004 info->ioapic.pin))
1005 return -ENOMEM;
1006 } else {
1007 info->flags |= X86_IRQ_ALLOC_LEGACY;
1008 irq = __irq_domain_alloc_irqs(domain, irq, 1, node, info, true,
1009 NULL);
1010 if (irq >= 0) {
1011 irq_data = irq_domain_get_irq_data(domain, irq);
1012 data = irq_data->chip_data;
1013 data->isa_irq = true;
1014 }
1015 }
1016
1017 return irq;
1018}
1019
1020static int mp_map_pin_to_irq(u32 gsi, int idx, int ioapic, int pin,
1021 unsigned int flags, struct irq_alloc_info *info)
1022{
1023 int irq;
1024 bool legacy = false;
1025 struct irq_alloc_info tmp;
1026 struct mp_chip_data *data;
1027 struct irq_domain *domain = mp_ioapic_irqdomain(ioapic);
1028
1029 if (!domain)
1030 return -ENOSYS;
1031
1032 if (idx >= 0 && test_bit(mp_irqs[idx].srcbus, mp_bus_not_pci)) {
1033 irq = mp_irqs[idx].srcbusirq;
1034 legacy = mp_is_legacy_irq(irq);
1035 /*
1036 * IRQ2 is unusable for historical reasons on systems which
1037 * have a legacy PIC. See the comment vs. IRQ2 further down.
1038 *
1039 * If this gets removed at some point then the related code
1040 * in lapic_assign_system_vectors() needs to be adjusted as
1041 * well.
1042 */
1043 if (legacy && irq == PIC_CASCADE_IR)
1044 return -EINVAL;
1045 }
1046
1047 mutex_lock(&ioapic_mutex);
1048 if (!(flags & IOAPIC_MAP_ALLOC)) {
1049 if (!legacy) {
1050 irq = irq_find_mapping(domain, pin);
1051 if (irq == 0)
1052 irq = -ENOENT;
1053 }
1054 } else {
1055 ioapic_copy_alloc_attr(&tmp, info, gsi, ioapic, pin);
1056 if (legacy)
1057 irq = alloc_isa_irq_from_domain(domain, irq,
1058 ioapic, pin, &tmp);
1059 else if ((irq = irq_find_mapping(domain, pin)) == 0)
1060 irq = alloc_irq_from_domain(domain, ioapic, gsi, &tmp);
1061 else if (!mp_check_pin_attr(irq, &tmp))
1062 irq = -EBUSY;
1063 if (irq >= 0) {
1064 data = irq_get_chip_data(irq);
1065 data->count++;
1066 }
1067 }
1068 mutex_unlock(&ioapic_mutex);
1069
1070 return irq;
1071}
1072
1073static int pin_2_irq(int idx, int ioapic, int pin, unsigned int flags)
1074{
1075 u32 gsi = mp_pin_to_gsi(ioapic, pin);
1076
1077 /*
1078 * Debugging check, we are in big trouble if this message pops up!
1079 */
1080 if (mp_irqs[idx].dstirq != pin)
1081 pr_err("broken BIOS or MPTABLE parser, ayiee!!\n");
1082
1083#ifdef CONFIG_X86_32
1084 /*
1085 * PCI IRQ command line redirection. Yes, limits are hardcoded.
1086 */
1087 if ((pin >= 16) && (pin <= 23)) {
1088 if (pirq_entries[pin-16] != -1) {
1089 if (!pirq_entries[pin-16]) {
1090 apic_printk(APIC_VERBOSE, KERN_DEBUG
1091 "disabling PIRQ%d\n", pin-16);
1092 } else {
1093 int irq = pirq_entries[pin-16];
1094 apic_printk(APIC_VERBOSE, KERN_DEBUG
1095 "using PIRQ%d -> IRQ %d\n",
1096 pin-16, irq);
1097 return irq;
1098 }
1099 }
1100 }
1101#endif
1102
1103 return mp_map_pin_to_irq(gsi, idx, ioapic, pin, flags, NULL);
1104}
1105
1106int mp_map_gsi_to_irq(u32 gsi, unsigned int flags, struct irq_alloc_info *info)
1107{
1108 int ioapic, pin, idx;
1109
1110 ioapic = mp_find_ioapic(gsi);
1111 if (ioapic < 0)
1112 return -ENODEV;
1113
1114 pin = mp_find_ioapic_pin(ioapic, gsi);
1115 idx = find_irq_entry(ioapic, pin, mp_INT);
1116 if ((flags & IOAPIC_MAP_CHECK) && idx < 0)
1117 return -ENODEV;
1118
1119 return mp_map_pin_to_irq(gsi, idx, ioapic, pin, flags, info);
1120}
1121
1122void mp_unmap_irq(int irq)
1123{
1124 struct irq_data *irq_data = irq_get_irq_data(irq);
1125 struct mp_chip_data *data;
1126
1127 if (!irq_data || !irq_data->domain)
1128 return;
1129
1130 data = irq_data->chip_data;
1131 if (!data || data->isa_irq)
1132 return;
1133
1134 mutex_lock(&ioapic_mutex);
1135 if (--data->count == 0)
1136 irq_domain_free_irqs(irq, 1);
1137 mutex_unlock(&ioapic_mutex);
1138}
1139
1140/*
1141 * Find a specific PCI IRQ entry.
1142 * Not an __init, possibly needed by modules
1143 */
1144int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin)
1145{
1146 int irq, i, best_ioapic = -1, best_idx = -1;
1147
1148 apic_printk(APIC_DEBUG,
1149 "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n",
1150 bus, slot, pin);
1151 if (test_bit(bus, mp_bus_not_pci)) {
1152 apic_printk(APIC_VERBOSE,
1153 "PCI BIOS passed nonexistent PCI bus %d!\n", bus);
1154 return -1;
1155 }
1156
1157 for (i = 0; i < mp_irq_entries; i++) {
1158 int lbus = mp_irqs[i].srcbus;
1159 int ioapic_idx, found = 0;
1160
1161 if (bus != lbus || mp_irqs[i].irqtype != mp_INT ||
1162 slot != ((mp_irqs[i].srcbusirq >> 2) & 0x1f))
1163 continue;
1164
1165 for_each_ioapic(ioapic_idx)
1166 if (mpc_ioapic_id(ioapic_idx) == mp_irqs[i].dstapic ||
1167 mp_irqs[i].dstapic == MP_APIC_ALL) {
1168 found = 1;
1169 break;
1170 }
1171 if (!found)
1172 continue;
1173
1174 /* Skip ISA IRQs */
1175 irq = pin_2_irq(i, ioapic_idx, mp_irqs[i].dstirq, 0);
1176 if (irq > 0 && !IO_APIC_IRQ(irq))
1177 continue;
1178
1179 if (pin == (mp_irqs[i].srcbusirq & 3)) {
1180 best_idx = i;
1181 best_ioapic = ioapic_idx;
1182 goto out;
1183 }
1184
1185 /*
1186 * Use the first all-but-pin matching entry as a
1187 * best-guess fuzzy result for broken mptables.
1188 */
1189 if (best_idx < 0) {
1190 best_idx = i;
1191 best_ioapic = ioapic_idx;
1192 }
1193 }
1194 if (best_idx < 0)
1195 return -1;
1196
1197out:
1198 return pin_2_irq(best_idx, best_ioapic, mp_irqs[best_idx].dstirq,
1199 IOAPIC_MAP_ALLOC);
1200}
1201EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector);
1202
1203static struct irq_chip ioapic_chip, ioapic_ir_chip;
1204
1205static void __init setup_IO_APIC_irqs(void)
1206{
1207 unsigned int ioapic, pin;
1208 int idx;
1209
1210 apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n");
1211
1212 for_each_ioapic_pin(ioapic, pin) {
1213 idx = find_irq_entry(ioapic, pin, mp_INT);
1214 if (idx < 0)
1215 apic_printk(APIC_VERBOSE,
1216 KERN_DEBUG " apic %d pin %d not connected\n",
1217 mpc_ioapic_id(ioapic), pin);
1218 else
1219 pin_2_irq(idx, ioapic, pin,
1220 ioapic ? 0 : IOAPIC_MAP_ALLOC);
1221 }
1222}
1223
1224void ioapic_zap_locks(void)
1225{
1226 raw_spin_lock_init(&ioapic_lock);
1227}
1228
1229static void io_apic_print_entries(unsigned int apic, unsigned int nr_entries)
1230{
1231 struct IO_APIC_route_entry entry;
1232 char buf[256];
1233 int i;
1234
1235 printk(KERN_DEBUG "IOAPIC %d:\n", apic);
1236 for (i = 0; i <= nr_entries; i++) {
1237 entry = ioapic_read_entry(apic, i);
1238 snprintf(buf, sizeof(buf),
1239 " pin%02x, %s, %s, %s, V(%02X), IRR(%1d), S(%1d)",
1240 i,
1241 entry.masked ? "disabled" : "enabled ",
1242 entry.is_level ? "level" : "edge ",
1243 entry.active_low ? "low " : "high",
1244 entry.vector, entry.irr, entry.delivery_status);
1245 if (entry.ir_format) {
1246 printk(KERN_DEBUG "%s, remapped, I(%04X), Z(%X)\n",
1247 buf,
1248 (entry.ir_index_15 << 15) | entry.ir_index_0_14,
1249 entry.ir_zero);
1250 } else {
1251 printk(KERN_DEBUG "%s, %s, D(%02X%02X), M(%1d)\n", buf,
1252 entry.dest_mode_logical ? "logical " : "physical",
1253 entry.virt_destid_8_14, entry.destid_0_7,
1254 entry.delivery_mode);
1255 }
1256 }
1257}
1258
1259static void __init print_IO_APIC(int ioapic_idx)
1260{
1261 union IO_APIC_reg_00 reg_00;
1262 union IO_APIC_reg_01 reg_01;
1263 union IO_APIC_reg_02 reg_02;
1264 union IO_APIC_reg_03 reg_03;
1265 unsigned long flags;
1266
1267 raw_spin_lock_irqsave(&ioapic_lock, flags);
1268 reg_00.raw = io_apic_read(ioapic_idx, 0);
1269 reg_01.raw = io_apic_read(ioapic_idx, 1);
1270 if (reg_01.bits.version >= 0x10)
1271 reg_02.raw = io_apic_read(ioapic_idx, 2);
1272 if (reg_01.bits.version >= 0x20)
1273 reg_03.raw = io_apic_read(ioapic_idx, 3);
1274 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
1275
1276 printk(KERN_DEBUG "IO APIC #%d......\n", mpc_ioapic_id(ioapic_idx));
1277 printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw);
1278 printk(KERN_DEBUG "....... : physical APIC id: %02X\n", reg_00.bits.ID);
1279 printk(KERN_DEBUG "....... : Delivery Type: %X\n", reg_00.bits.delivery_type);
1280 printk(KERN_DEBUG "....... : LTS : %X\n", reg_00.bits.LTS);
1281
1282 printk(KERN_DEBUG ".... register #01: %08X\n", *(int *)®_01);
1283 printk(KERN_DEBUG "....... : max redirection entries: %02X\n",
1284 reg_01.bits.entries);
1285
1286 printk(KERN_DEBUG "....... : PRQ implemented: %X\n", reg_01.bits.PRQ);
1287 printk(KERN_DEBUG "....... : IO APIC version: %02X\n",
1288 reg_01.bits.version);
1289
1290 /*
1291 * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02,
1292 * but the value of reg_02 is read as the previous read register
1293 * value, so ignore it if reg_02 == reg_01.
1294 */
1295 if (reg_01.bits.version >= 0x10 && reg_02.raw != reg_01.raw) {
1296 printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw);
1297 printk(KERN_DEBUG "....... : arbitration: %02X\n", reg_02.bits.arbitration);
1298 }
1299
1300 /*
1301 * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02
1302 * or reg_03, but the value of reg_0[23] is read as the previous read
1303 * register value, so ignore it if reg_03 == reg_0[12].
1304 */
1305 if (reg_01.bits.version >= 0x20 && reg_03.raw != reg_02.raw &&
1306 reg_03.raw != reg_01.raw) {
1307 printk(KERN_DEBUG ".... register #03: %08X\n", reg_03.raw);
1308 printk(KERN_DEBUG "....... : Boot DT : %X\n", reg_03.bits.boot_DT);
1309 }
1310
1311 printk(KERN_DEBUG ".... IRQ redirection table:\n");
1312 io_apic_print_entries(ioapic_idx, reg_01.bits.entries);
1313}
1314
1315void __init print_IO_APICs(void)
1316{
1317 int ioapic_idx;
1318 unsigned int irq;
1319
1320 printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
1321 for_each_ioapic(ioapic_idx)
1322 printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
1323 mpc_ioapic_id(ioapic_idx),
1324 ioapics[ioapic_idx].nr_registers);
1325
1326 /*
1327 * We are a bit conservative about what we expect. We have to
1328 * know about every hardware change ASAP.
1329 */
1330 printk(KERN_INFO "testing the IO APIC.......................\n");
1331
1332 for_each_ioapic(ioapic_idx)
1333 print_IO_APIC(ioapic_idx);
1334
1335 printk(KERN_DEBUG "IRQ to pin mappings:\n");
1336 for_each_active_irq(irq) {
1337 struct irq_pin_list *entry;
1338 struct irq_chip *chip;
1339 struct mp_chip_data *data;
1340
1341 chip = irq_get_chip(irq);
1342 if (chip != &ioapic_chip && chip != &ioapic_ir_chip)
1343 continue;
1344 data = irq_get_chip_data(irq);
1345 if (!data)
1346 continue;
1347 if (list_empty(&data->irq_2_pin))
1348 continue;
1349
1350 printk(KERN_DEBUG "IRQ%d ", irq);
1351 for_each_irq_pin(entry, data->irq_2_pin)
1352 pr_cont("-> %d:%d", entry->apic, entry->pin);
1353 pr_cont("\n");
1354 }
1355
1356 printk(KERN_INFO ".................................... done.\n");
1357}
1358
1359/* Where if anywhere is the i8259 connect in external int mode */
1360static struct { int pin, apic; } ioapic_i8259 = { -1, -1 };
1361
1362void __init enable_IO_APIC(void)
1363{
1364 int i8259_apic, i8259_pin;
1365 int apic, pin;
1366
1367 if (skip_ioapic_setup)
1368 nr_ioapics = 0;
1369
1370 if (!nr_legacy_irqs() || !nr_ioapics)
1371 return;
1372
1373 for_each_ioapic_pin(apic, pin) {
1374 /* See if any of the pins is in ExtINT mode */
1375 struct IO_APIC_route_entry entry = ioapic_read_entry(apic, pin);
1376
1377 /* If the interrupt line is enabled and in ExtInt mode
1378 * I have found the pin where the i8259 is connected.
1379 */
1380 if (!entry.masked &&
1381 entry.delivery_mode == APIC_DELIVERY_MODE_EXTINT) {
1382 ioapic_i8259.apic = apic;
1383 ioapic_i8259.pin = pin;
1384 goto found_i8259;
1385 }
1386 }
1387 found_i8259:
1388 /* Look to see what if the MP table has reported the ExtINT */
1389 /* If we could not find the appropriate pin by looking at the ioapic
1390 * the i8259 probably is not connected the ioapic but give the
1391 * mptable a chance anyway.
1392 */
1393 i8259_pin = find_isa_irq_pin(0, mp_ExtINT);
1394 i8259_apic = find_isa_irq_apic(0, mp_ExtINT);
1395 /* Trust the MP table if nothing is setup in the hardware */
1396 if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) {
1397 printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n");
1398 ioapic_i8259.pin = i8259_pin;
1399 ioapic_i8259.apic = i8259_apic;
1400 }
1401 /* Complain if the MP table and the hardware disagree */
1402 if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) &&
1403 (i8259_pin >= 0) && (ioapic_i8259.pin >= 0))
1404 {
1405 printk(KERN_WARNING "ExtINT in hardware and MP table differ\n");
1406 }
1407
1408 /*
1409 * Do not trust the IO-APIC being empty at bootup
1410 */
1411 clear_IO_APIC();
1412}
1413
1414void native_restore_boot_irq_mode(void)
1415{
1416 /*
1417 * If the i8259 is routed through an IOAPIC
1418 * Put that IOAPIC in virtual wire mode
1419 * so legacy interrupts can be delivered.
1420 */
1421 if (ioapic_i8259.pin != -1) {
1422 struct IO_APIC_route_entry entry;
1423 u32 apic_id = read_apic_id();
1424
1425 memset(&entry, 0, sizeof(entry));
1426 entry.masked = false;
1427 entry.is_level = false;
1428 entry.active_low = false;
1429 entry.dest_mode_logical = false;
1430 entry.delivery_mode = APIC_DELIVERY_MODE_EXTINT;
1431 entry.destid_0_7 = apic_id & 0xFF;
1432 entry.virt_destid_8_14 = apic_id >> 8;
1433
1434 /*
1435 * Add it to the IO-APIC irq-routing table:
1436 */
1437 ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry);
1438 }
1439
1440 if (boot_cpu_has(X86_FEATURE_APIC) || apic_from_smp_config())
1441 disconnect_bsp_APIC(ioapic_i8259.pin != -1);
1442}
1443
1444void restore_boot_irq_mode(void)
1445{
1446 if (!nr_legacy_irqs())
1447 return;
1448
1449 x86_apic_ops.restore();
1450}
1451
1452#ifdef CONFIG_X86_32
1453/*
1454 * function to set the IO-APIC physical IDs based on the
1455 * values stored in the MPC table.
1456 *
1457 * by Matt Domsch <Matt_Domsch@dell.com> Tue Dec 21 12:25:05 CST 1999
1458 */
1459void __init setup_ioapic_ids_from_mpc_nocheck(void)
1460{
1461 union IO_APIC_reg_00 reg_00;
1462 physid_mask_t phys_id_present_map;
1463 int ioapic_idx;
1464 int i;
1465 unsigned char old_id;
1466 unsigned long flags;
1467
1468 /*
1469 * This is broken; anything with a real cpu count has to
1470 * circumvent this idiocy regardless.
1471 */
1472 apic->ioapic_phys_id_map(&phys_cpu_present_map, &phys_id_present_map);
1473
1474 /*
1475 * Set the IOAPIC ID to the value stored in the MPC table.
1476 */
1477 for_each_ioapic(ioapic_idx) {
1478 /* Read the register 0 value */
1479 raw_spin_lock_irqsave(&ioapic_lock, flags);
1480 reg_00.raw = io_apic_read(ioapic_idx, 0);
1481 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
1482
1483 old_id = mpc_ioapic_id(ioapic_idx);
1484
1485 if (mpc_ioapic_id(ioapic_idx) >= get_physical_broadcast()) {
1486 printk(KERN_ERR "BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n",
1487 ioapic_idx, mpc_ioapic_id(ioapic_idx));
1488 printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
1489 reg_00.bits.ID);
1490 ioapics[ioapic_idx].mp_config.apicid = reg_00.bits.ID;
1491 }
1492
1493 /*
1494 * Sanity check, is the ID really free? Every APIC in a
1495 * system must have a unique ID or we get lots of nice
1496 * 'stuck on smp_invalidate_needed IPI wait' messages.
1497 */
1498 if (apic->check_apicid_used(&phys_id_present_map,
1499 mpc_ioapic_id(ioapic_idx))) {
1500 printk(KERN_ERR "BIOS bug, IO-APIC#%d ID %d is already used!...\n",
1501 ioapic_idx, mpc_ioapic_id(ioapic_idx));
1502 for (i = 0; i < get_physical_broadcast(); i++)
1503 if (!physid_isset(i, phys_id_present_map))
1504 break;
1505 if (i >= get_physical_broadcast())
1506 panic("Max APIC ID exceeded!\n");
1507 printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
1508 i);
1509 physid_set(i, phys_id_present_map);
1510 ioapics[ioapic_idx].mp_config.apicid = i;
1511 } else {
1512 physid_mask_t tmp;
1513 apic->apicid_to_cpu_present(mpc_ioapic_id(ioapic_idx),
1514 &tmp);
1515 apic_printk(APIC_VERBOSE, "Setting %d in the "
1516 "phys_id_present_map\n",
1517 mpc_ioapic_id(ioapic_idx));
1518 physids_or(phys_id_present_map, phys_id_present_map, tmp);
1519 }
1520
1521 /*
1522 * We need to adjust the IRQ routing table
1523 * if the ID changed.
1524 */
1525 if (old_id != mpc_ioapic_id(ioapic_idx))
1526 for (i = 0; i < mp_irq_entries; i++)
1527 if (mp_irqs[i].dstapic == old_id)
1528 mp_irqs[i].dstapic
1529 = mpc_ioapic_id(ioapic_idx);
1530
1531 /*
1532 * Update the ID register according to the right value
1533 * from the MPC table if they are different.
1534 */
1535 if (mpc_ioapic_id(ioapic_idx) == reg_00.bits.ID)
1536 continue;
1537
1538 apic_printk(APIC_VERBOSE, KERN_INFO
1539 "...changing IO-APIC physical APIC ID to %d ...",
1540 mpc_ioapic_id(ioapic_idx));
1541
1542 reg_00.bits.ID = mpc_ioapic_id(ioapic_idx);
1543 raw_spin_lock_irqsave(&ioapic_lock, flags);
1544 io_apic_write(ioapic_idx, 0, reg_00.raw);
1545 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
1546
1547 /*
1548 * Sanity check
1549 */
1550 raw_spin_lock_irqsave(&ioapic_lock, flags);
1551 reg_00.raw = io_apic_read(ioapic_idx, 0);
1552 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
1553 if (reg_00.bits.ID != mpc_ioapic_id(ioapic_idx))
1554 pr_cont("could not set ID!\n");
1555 else
1556 apic_printk(APIC_VERBOSE, " ok.\n");
1557 }
1558}
1559
1560void __init setup_ioapic_ids_from_mpc(void)
1561{
1562
1563 if (acpi_ioapic)
1564 return;
1565 /*
1566 * Don't check I/O APIC IDs for xAPIC systems. They have
1567 * no meaning without the serial APIC bus.
1568 */
1569 if (!(boot_cpu_data.x86_vendor == X86_VENDOR_INTEL)
1570 || APIC_XAPIC(boot_cpu_apic_version))
1571 return;
1572 setup_ioapic_ids_from_mpc_nocheck();
1573}
1574#endif
1575
1576int no_timer_check __initdata;
1577
1578static int __init notimercheck(char *s)
1579{
1580 no_timer_check = 1;
1581 return 1;
1582}
1583__setup("no_timer_check", notimercheck);
1584
1585static void __init delay_with_tsc(void)
1586{
1587 unsigned long long start, now;
1588 unsigned long end = jiffies + 4;
1589
1590 start = rdtsc();
1591
1592 /*
1593 * We don't know the TSC frequency yet, but waiting for
1594 * 40000000000/HZ TSC cycles is safe:
1595 * 4 GHz == 10 jiffies
1596 * 1 GHz == 40 jiffies
1597 */
1598 do {
1599 rep_nop();
1600 now = rdtsc();
1601 } while ((now - start) < 40000000000ULL / HZ &&
1602 time_before_eq(jiffies, end));
1603}
1604
1605static void __init delay_without_tsc(void)
1606{
1607 unsigned long end = jiffies + 4;
1608 int band = 1;
1609
1610 /*
1611 * We don't know any frequency yet, but waiting for
1612 * 40940000000/HZ cycles is safe:
1613 * 4 GHz == 10 jiffies
1614 * 1 GHz == 40 jiffies
1615 * 1 << 1 + 1 << 2 +...+ 1 << 11 = 4094
1616 */
1617 do {
1618 __delay(((1U << band++) * 10000000UL) / HZ);
1619 } while (band < 12 && time_before_eq(jiffies, end));
1620}
1621
1622/*
1623 * There is a nasty bug in some older SMP boards, their mptable lies
1624 * about the timer IRQ. We do the following to work around the situation:
1625 *
1626 * - timer IRQ defaults to IO-APIC IRQ
1627 * - if this function detects that timer IRQs are defunct, then we fall
1628 * back to ISA timer IRQs
1629 */
1630static int __init timer_irq_works(void)
1631{
1632 unsigned long t1 = jiffies;
1633
1634 if (no_timer_check)
1635 return 1;
1636
1637 local_irq_enable();
1638 if (boot_cpu_has(X86_FEATURE_TSC))
1639 delay_with_tsc();
1640 else
1641 delay_without_tsc();
1642
1643 /*
1644 * Expect a few ticks at least, to be sure some possible
1645 * glue logic does not lock up after one or two first
1646 * ticks in a non-ExtINT mode. Also the local APIC
1647 * might have cached one ExtINT interrupt. Finally, at
1648 * least one tick may be lost due to delays.
1649 */
1650
1651 local_irq_disable();
1652
1653 /* Did jiffies advance? */
1654 return time_after(jiffies, t1 + 4);
1655}
1656
1657/*
1658 * In the SMP+IOAPIC case it might happen that there are an unspecified
1659 * number of pending IRQ events unhandled. These cases are very rare,
1660 * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
1661 * better to do it this way as thus we do not have to be aware of
1662 * 'pending' interrupts in the IRQ path, except at this point.
1663 */
1664/*
1665 * Edge triggered needs to resend any interrupt
1666 * that was delayed but this is now handled in the device
1667 * independent code.
1668 */
1669
1670/*
1671 * Starting up a edge-triggered IO-APIC interrupt is
1672 * nasty - we need to make sure that we get the edge.
1673 * If it is already asserted for some reason, we need
1674 * return 1 to indicate that is was pending.
1675 *
1676 * This is not complete - we should be able to fake
1677 * an edge even if it isn't on the 8259A...
1678 */
1679static unsigned int startup_ioapic_irq(struct irq_data *data)
1680{
1681 int was_pending = 0, irq = data->irq;
1682 unsigned long flags;
1683
1684 raw_spin_lock_irqsave(&ioapic_lock, flags);
1685 if (irq < nr_legacy_irqs()) {
1686 legacy_pic->mask(irq);
1687 if (legacy_pic->irq_pending(irq))
1688 was_pending = 1;
1689 }
1690 __unmask_ioapic(data->chip_data);
1691 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
1692
1693 return was_pending;
1694}
1695
1696atomic_t irq_mis_count;
1697
1698#ifdef CONFIG_GENERIC_PENDING_IRQ
1699static bool io_apic_level_ack_pending(struct mp_chip_data *data)
1700{
1701 struct irq_pin_list *entry;
1702 unsigned long flags;
1703
1704 raw_spin_lock_irqsave(&ioapic_lock, flags);
1705 for_each_irq_pin(entry, data->irq_2_pin) {
1706 struct IO_APIC_route_entry e;
1707 int pin;
1708
1709 pin = entry->pin;
1710 e.w1 = io_apic_read(entry->apic, 0x10 + pin*2);
1711 /* Is the remote IRR bit set? */
1712 if (e.irr) {
1713 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
1714 return true;
1715 }
1716 }
1717 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
1718
1719 return false;
1720}
1721
1722static inline bool ioapic_prepare_move(struct irq_data *data)
1723{
1724 /* If we are moving the IRQ we need to mask it */
1725 if (unlikely(irqd_is_setaffinity_pending(data))) {
1726 if (!irqd_irq_masked(data))
1727 mask_ioapic_irq(data);
1728 return true;
1729 }
1730 return false;
1731}
1732
1733static inline void ioapic_finish_move(struct irq_data *data, bool moveit)
1734{
1735 if (unlikely(moveit)) {
1736 /* Only migrate the irq if the ack has been received.
1737 *
1738 * On rare occasions the broadcast level triggered ack gets
1739 * delayed going to ioapics, and if we reprogram the
1740 * vector while Remote IRR is still set the irq will never
1741 * fire again.
1742 *
1743 * To prevent this scenario we read the Remote IRR bit
1744 * of the ioapic. This has two effects.
1745 * - On any sane system the read of the ioapic will
1746 * flush writes (and acks) going to the ioapic from
1747 * this cpu.
1748 * - We get to see if the ACK has actually been delivered.
1749 *
1750 * Based on failed experiments of reprogramming the
1751 * ioapic entry from outside of irq context starting
1752 * with masking the ioapic entry and then polling until
1753 * Remote IRR was clear before reprogramming the
1754 * ioapic I don't trust the Remote IRR bit to be
1755 * completely accurate.
1756 *
1757 * However there appears to be no other way to plug
1758 * this race, so if the Remote IRR bit is not
1759 * accurate and is causing problems then it is a hardware bug
1760 * and you can go talk to the chipset vendor about it.
1761 */
1762 if (!io_apic_level_ack_pending(data->chip_data))
1763 irq_move_masked_irq(data);
1764 /* If the IRQ is masked in the core, leave it: */
1765 if (!irqd_irq_masked(data))
1766 unmask_ioapic_irq(data);
1767 }
1768}
1769#else
1770static inline bool ioapic_prepare_move(struct irq_data *data)
1771{
1772 return false;
1773}
1774static inline void ioapic_finish_move(struct irq_data *data, bool moveit)
1775{
1776}
1777#endif
1778
1779static void ioapic_ack_level(struct irq_data *irq_data)
1780{
1781 struct irq_cfg *cfg = irqd_cfg(irq_data);
1782 unsigned long v;
1783 bool moveit;
1784 int i;
1785
1786 irq_complete_move(cfg);
1787 moveit = ioapic_prepare_move(irq_data);
1788
1789 /*
1790 * It appears there is an erratum which affects at least version 0x11
1791 * of I/O APIC (that's the 82093AA and cores integrated into various
1792 * chipsets). Under certain conditions a level-triggered interrupt is
1793 * erroneously delivered as edge-triggered one but the respective IRR
1794 * bit gets set nevertheless. As a result the I/O unit expects an EOI
1795 * message but it will never arrive and further interrupts are blocked
1796 * from the source. The exact reason is so far unknown, but the
1797 * phenomenon was observed when two consecutive interrupt requests
1798 * from a given source get delivered to the same CPU and the source is
1799 * temporarily disabled in between.
1800 *
1801 * A workaround is to simulate an EOI message manually. We achieve it
1802 * by setting the trigger mode to edge and then to level when the edge
1803 * trigger mode gets detected in the TMR of a local APIC for a
1804 * level-triggered interrupt. We mask the source for the time of the
1805 * operation to prevent an edge-triggered interrupt escaping meanwhile.
1806 * The idea is from Manfred Spraul. --macro
1807 *
1808 * Also in the case when cpu goes offline, fixup_irqs() will forward
1809 * any unhandled interrupt on the offlined cpu to the new cpu
1810 * destination that is handling the corresponding interrupt. This
1811 * interrupt forwarding is done via IPI's. Hence, in this case also
1812 * level-triggered io-apic interrupt will be seen as an edge
1813 * interrupt in the IRR. And we can't rely on the cpu's EOI
1814 * to be broadcasted to the IO-APIC's which will clear the remoteIRR
1815 * corresponding to the level-triggered interrupt. Hence on IO-APIC's
1816 * supporting EOI register, we do an explicit EOI to clear the
1817 * remote IRR and on IO-APIC's which don't have an EOI register,
1818 * we use the above logic (mask+edge followed by unmask+level) from
1819 * Manfred Spraul to clear the remote IRR.
1820 */
1821 i = cfg->vector;
1822 v = apic_read(APIC_TMR + ((i & ~0x1f) >> 1));
1823
1824 /*
1825 * We must acknowledge the irq before we move it or the acknowledge will
1826 * not propagate properly.
1827 */
1828 ack_APIC_irq();
1829
1830 /*
1831 * Tail end of clearing remote IRR bit (either by delivering the EOI
1832 * message via io-apic EOI register write or simulating it using
1833 * mask+edge followed by unmask+level logic) manually when the
1834 * level triggered interrupt is seen as the edge triggered interrupt
1835 * at the cpu.
1836 */
1837 if (!(v & (1 << (i & 0x1f)))) {
1838 atomic_inc(&irq_mis_count);
1839 eoi_ioapic_pin(cfg->vector, irq_data->chip_data);
1840 }
1841
1842 ioapic_finish_move(irq_data, moveit);
1843}
1844
1845static void ioapic_ir_ack_level(struct irq_data *irq_data)
1846{
1847 struct mp_chip_data *data = irq_data->chip_data;
1848
1849 /*
1850 * Intr-remapping uses pin number as the virtual vector
1851 * in the RTE. Actual vector is programmed in
1852 * intr-remapping table entry. Hence for the io-apic
1853 * EOI we use the pin number.
1854 */
1855 apic_ack_irq(irq_data);
1856 eoi_ioapic_pin(data->entry.vector, data);
1857}
1858
1859/*
1860 * The I/OAPIC is just a device for generating MSI messages from legacy
1861 * interrupt pins. Various fields of the RTE translate into bits of the
1862 * resulting MSI which had a historical meaning.
1863 *
1864 * With interrupt remapping, many of those bits have different meanings
1865 * in the underlying MSI, but the way that the I/OAPIC transforms them
1866 * from its RTE to the MSI message is the same. This function allows
1867 * the parent IRQ domain to compose the MSI message, then takes the
1868 * relevant bits to put them in the appropriate places in the RTE in
1869 * order to generate that message when the IRQ happens.
1870 *
1871 * The setup here relies on a preconfigured route entry (is_level,
1872 * active_low, masked) because the parent domain is merely composing the
1873 * generic message routing information which is used for the MSI.
1874 */
1875static void ioapic_setup_msg_from_msi(struct irq_data *irq_data,
1876 struct IO_APIC_route_entry *entry)
1877{
1878 struct msi_msg msg;
1879
1880 /* Let the parent domain compose the MSI message */
1881 irq_chip_compose_msi_msg(irq_data, &msg);
1882
1883 /*
1884 * - Real vector
1885 * - DMAR/IR: 8bit subhandle (ioapic.pin)
1886 * - AMD/IR: 8bit IRTE index
1887 */
1888 entry->vector = msg.arch_data.vector;
1889 /* Delivery mode (for DMAR/IR all 0) */
1890 entry->delivery_mode = msg.arch_data.delivery_mode;
1891 /* Destination mode or DMAR/IR index bit 15 */
1892 entry->dest_mode_logical = msg.arch_addr_lo.dest_mode_logical;
1893 /* DMAR/IR: 1, 0 for all other modes */
1894 entry->ir_format = msg.arch_addr_lo.dmar_format;
1895 /*
1896 * - DMAR/IR: index bit 0-14.
1897 *
1898 * - Virt: If the host supports x2apic without a virtualized IR
1899 * unit then bit 0-6 of dmar_index_0_14 are providing bit
1900 * 8-14 of the destination id.
1901 *
1902 * All other modes have bit 0-6 of dmar_index_0_14 cleared and the
1903 * topmost 8 bits are destination id bit 0-7 (entry::destid_0_7).
1904 */
1905 entry->ir_index_0_14 = msg.arch_addr_lo.dmar_index_0_14;
1906}
1907
1908static void ioapic_configure_entry(struct irq_data *irqd)
1909{
1910 struct mp_chip_data *mpd = irqd->chip_data;
1911 struct irq_pin_list *entry;
1912
1913 ioapic_setup_msg_from_msi(irqd, &mpd->entry);
1914
1915 for_each_irq_pin(entry, mpd->irq_2_pin)
1916 __ioapic_write_entry(entry->apic, entry->pin, mpd->entry);
1917}
1918
1919static int ioapic_set_affinity(struct irq_data *irq_data,
1920 const struct cpumask *mask, bool force)
1921{
1922 struct irq_data *parent = irq_data->parent_data;
1923 unsigned long flags;
1924 int ret;
1925
1926 ret = parent->chip->irq_set_affinity(parent, mask, force);
1927 raw_spin_lock_irqsave(&ioapic_lock, flags);
1928 if (ret >= 0 && ret != IRQ_SET_MASK_OK_DONE)
1929 ioapic_configure_entry(irq_data);
1930 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
1931
1932 return ret;
1933}
1934
1935/*
1936 * Interrupt shutdown masks the ioapic pin, but the interrupt might already
1937 * be in flight, but not yet serviced by the target CPU. That means
1938 * __synchronize_hardirq() would return and claim that everything is calmed
1939 * down. So free_irq() would proceed and deactivate the interrupt and free
1940 * resources.
1941 *
1942 * Once the target CPU comes around to service it it will find a cleared
1943 * vector and complain. While the spurious interrupt is harmless, the full
1944 * release of resources might prevent the interrupt from being acknowledged
1945 * which keeps the hardware in a weird state.
1946 *
1947 * Verify that the corresponding Remote-IRR bits are clear.
1948 */
1949static int ioapic_irq_get_chip_state(struct irq_data *irqd,
1950 enum irqchip_irq_state which,
1951 bool *state)
1952{
1953 struct mp_chip_data *mcd = irqd->chip_data;
1954 struct IO_APIC_route_entry rentry;
1955 struct irq_pin_list *p;
1956
1957 if (which != IRQCHIP_STATE_ACTIVE)
1958 return -EINVAL;
1959
1960 *state = false;
1961 raw_spin_lock(&ioapic_lock);
1962 for_each_irq_pin(p, mcd->irq_2_pin) {
1963 rentry = __ioapic_read_entry(p->apic, p->pin);
1964 /*
1965 * The remote IRR is only valid in level trigger mode. It's
1966 * meaning is undefined for edge triggered interrupts and
1967 * irrelevant because the IO-APIC treats them as fire and
1968 * forget.
1969 */
1970 if (rentry.irr && rentry.is_level) {
1971 *state = true;
1972 break;
1973 }
1974 }
1975 raw_spin_unlock(&ioapic_lock);
1976 return 0;
1977}
1978
1979static struct irq_chip ioapic_chip __read_mostly = {
1980 .name = "IO-APIC",
1981 .irq_startup = startup_ioapic_irq,
1982 .irq_mask = mask_ioapic_irq,
1983 .irq_unmask = unmask_ioapic_irq,
1984 .irq_ack = irq_chip_ack_parent,
1985 .irq_eoi = ioapic_ack_level,
1986 .irq_set_affinity = ioapic_set_affinity,
1987 .irq_retrigger = irq_chip_retrigger_hierarchy,
1988 .irq_get_irqchip_state = ioapic_irq_get_chip_state,
1989 .flags = IRQCHIP_SKIP_SET_WAKE |
1990 IRQCHIP_AFFINITY_PRE_STARTUP,
1991};
1992
1993static struct irq_chip ioapic_ir_chip __read_mostly = {
1994 .name = "IR-IO-APIC",
1995 .irq_startup = startup_ioapic_irq,
1996 .irq_mask = mask_ioapic_irq,
1997 .irq_unmask = unmask_ioapic_irq,
1998 .irq_ack = irq_chip_ack_parent,
1999 .irq_eoi = ioapic_ir_ack_level,
2000 .irq_set_affinity = ioapic_set_affinity,
2001 .irq_retrigger = irq_chip_retrigger_hierarchy,
2002 .irq_get_irqchip_state = ioapic_irq_get_chip_state,
2003 .flags = IRQCHIP_SKIP_SET_WAKE |
2004 IRQCHIP_AFFINITY_PRE_STARTUP,
2005};
2006
2007static inline void init_IO_APIC_traps(void)
2008{
2009 struct irq_cfg *cfg;
2010 unsigned int irq;
2011
2012 for_each_active_irq(irq) {
2013 cfg = irq_cfg(irq);
2014 if (IO_APIC_IRQ(irq) && cfg && !cfg->vector) {
2015 /*
2016 * Hmm.. We don't have an entry for this,
2017 * so default to an old-fashioned 8259
2018 * interrupt if we can..
2019 */
2020 if (irq < nr_legacy_irqs())
2021 legacy_pic->make_irq(irq);
2022 else
2023 /* Strange. Oh, well.. */
2024 irq_set_chip(irq, &no_irq_chip);
2025 }
2026 }
2027}
2028
2029/*
2030 * The local APIC irq-chip implementation:
2031 */
2032
2033static void mask_lapic_irq(struct irq_data *data)
2034{
2035 unsigned long v;
2036
2037 v = apic_read(APIC_LVT0);
2038 apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
2039}
2040
2041static void unmask_lapic_irq(struct irq_data *data)
2042{
2043 unsigned long v;
2044
2045 v = apic_read(APIC_LVT0);
2046 apic_write(APIC_LVT0, v & ~APIC_LVT_MASKED);
2047}
2048
2049static void ack_lapic_irq(struct irq_data *data)
2050{
2051 ack_APIC_irq();
2052}
2053
2054static struct irq_chip lapic_chip __read_mostly = {
2055 .name = "local-APIC",
2056 .irq_mask = mask_lapic_irq,
2057 .irq_unmask = unmask_lapic_irq,
2058 .irq_ack = ack_lapic_irq,
2059};
2060
2061static void lapic_register_intr(int irq)
2062{
2063 irq_clear_status_flags(irq, IRQ_LEVEL);
2064 irq_set_chip_and_handler_name(irq, &lapic_chip, handle_edge_irq,
2065 "edge");
2066}
2067
2068/*
2069 * This looks a bit hackish but it's about the only one way of sending
2070 * a few INTA cycles to 8259As and any associated glue logic. ICR does
2071 * not support the ExtINT mode, unfortunately. We need to send these
2072 * cycles as some i82489DX-based boards have glue logic that keeps the
2073 * 8259A interrupt line asserted until INTA. --macro
2074 */
2075static inline void __init unlock_ExtINT_logic(void)
2076{
2077 int apic, pin, i;
2078 struct IO_APIC_route_entry entry0, entry1;
2079 unsigned char save_control, save_freq_select;
2080 u32 apic_id;
2081
2082 pin = find_isa_irq_pin(8, mp_INT);
2083 if (pin == -1) {
2084 WARN_ON_ONCE(1);
2085 return;
2086 }
2087 apic = find_isa_irq_apic(8, mp_INT);
2088 if (apic == -1) {
2089 WARN_ON_ONCE(1);
2090 return;
2091 }
2092
2093 entry0 = ioapic_read_entry(apic, pin);
2094 clear_IO_APIC_pin(apic, pin);
2095
2096 apic_id = hard_smp_processor_id();
2097 memset(&entry1, 0, sizeof(entry1));
2098
2099 entry1.dest_mode_logical = true;
2100 entry1.masked = false;
2101 entry1.destid_0_7 = apic_id & 0xFF;
2102 entry1.virt_destid_8_14 = apic_id >> 8;
2103 entry1.delivery_mode = APIC_DELIVERY_MODE_EXTINT;
2104 entry1.active_low = entry0.active_low;
2105 entry1.is_level = false;
2106 entry1.vector = 0;
2107
2108 ioapic_write_entry(apic, pin, entry1);
2109
2110 save_control = CMOS_READ(RTC_CONTROL);
2111 save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
2112 CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6,
2113 RTC_FREQ_SELECT);
2114 CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL);
2115
2116 i = 100;
2117 while (i-- > 0) {
2118 mdelay(10);
2119 if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF)
2120 i -= 10;
2121 }
2122
2123 CMOS_WRITE(save_control, RTC_CONTROL);
2124 CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
2125 clear_IO_APIC_pin(apic, pin);
2126
2127 ioapic_write_entry(apic, pin, entry0);
2128}
2129
2130static int disable_timer_pin_1 __initdata;
2131/* Actually the next is obsolete, but keep it for paranoid reasons -AK */
2132static int __init disable_timer_pin_setup(char *arg)
2133{
2134 disable_timer_pin_1 = 1;
2135 return 0;
2136}
2137early_param("disable_timer_pin_1", disable_timer_pin_setup);
2138
2139static int mp_alloc_timer_irq(int ioapic, int pin)
2140{
2141 int irq = -1;
2142 struct irq_domain *domain = mp_ioapic_irqdomain(ioapic);
2143
2144 if (domain) {
2145 struct irq_alloc_info info;
2146
2147 ioapic_set_alloc_attr(&info, NUMA_NO_NODE, 0, 0);
2148 info.devid = mpc_ioapic_id(ioapic);
2149 info.ioapic.pin = pin;
2150 mutex_lock(&ioapic_mutex);
2151 irq = alloc_isa_irq_from_domain(domain, 0, ioapic, pin, &info);
2152 mutex_unlock(&ioapic_mutex);
2153 }
2154
2155 return irq;
2156}
2157
2158/*
2159 * This code may look a bit paranoid, but it's supposed to cooperate with
2160 * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ
2161 * is so screwy. Thanks to Brian Perkins for testing/hacking this beast
2162 * fanatically on his truly buggy board.
2163 *
2164 * FIXME: really need to revamp this for all platforms.
2165 */
2166static inline void __init check_timer(void)
2167{
2168 struct irq_data *irq_data = irq_get_irq_data(0);
2169 struct mp_chip_data *data = irq_data->chip_data;
2170 struct irq_cfg *cfg = irqd_cfg(irq_data);
2171 int node = cpu_to_node(0);
2172 int apic1, pin1, apic2, pin2;
2173 int no_pin1 = 0;
2174
2175 if (!global_clock_event)
2176 return;
2177
2178 local_irq_disable();
2179
2180 /*
2181 * get/set the timer IRQ vector:
2182 */
2183 legacy_pic->mask(0);
2184
2185 /*
2186 * As IRQ0 is to be enabled in the 8259A, the virtual
2187 * wire has to be disabled in the local APIC. Also
2188 * timer interrupts need to be acknowledged manually in
2189 * the 8259A for the i82489DX when using the NMI
2190 * watchdog as that APIC treats NMIs as level-triggered.
2191 * The AEOI mode will finish them in the 8259A
2192 * automatically.
2193 */
2194 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
2195 legacy_pic->init(1);
2196
2197 pin1 = find_isa_irq_pin(0, mp_INT);
2198 apic1 = find_isa_irq_apic(0, mp_INT);
2199 pin2 = ioapic_i8259.pin;
2200 apic2 = ioapic_i8259.apic;
2201
2202 apic_printk(APIC_QUIET, KERN_INFO "..TIMER: vector=0x%02X "
2203 "apic1=%d pin1=%d apic2=%d pin2=%d\n",
2204 cfg->vector, apic1, pin1, apic2, pin2);
2205
2206 /*
2207 * Some BIOS writers are clueless and report the ExtINTA
2208 * I/O APIC input from the cascaded 8259A as the timer
2209 * interrupt input. So just in case, if only one pin
2210 * was found above, try it both directly and through the
2211 * 8259A.
2212 */
2213 if (pin1 == -1) {
2214 panic_if_irq_remap("BIOS bug: timer not connected to IO-APIC");
2215 pin1 = pin2;
2216 apic1 = apic2;
2217 no_pin1 = 1;
2218 } else if (pin2 == -1) {
2219 pin2 = pin1;
2220 apic2 = apic1;
2221 }
2222
2223 if (pin1 != -1) {
2224 /* Ok, does IRQ0 through the IOAPIC work? */
2225 if (no_pin1) {
2226 mp_alloc_timer_irq(apic1, pin1);
2227 } else {
2228 /*
2229 * for edge trigger, it's already unmasked,
2230 * so only need to unmask if it is level-trigger
2231 * do we really have level trigger timer?
2232 */
2233 int idx = find_irq_entry(apic1, pin1, mp_INT);
2234
2235 if (idx != -1 && irq_is_level(idx))
2236 unmask_ioapic_irq(irq_get_irq_data(0));
2237 }
2238 irq_domain_deactivate_irq(irq_data);
2239 irq_domain_activate_irq(irq_data, false);
2240 if (timer_irq_works()) {
2241 if (disable_timer_pin_1 > 0)
2242 clear_IO_APIC_pin(0, pin1);
2243 goto out;
2244 }
2245 panic_if_irq_remap("timer doesn't work through Interrupt-remapped IO-APIC");
2246 clear_IO_APIC_pin(apic1, pin1);
2247 if (!no_pin1)
2248 apic_printk(APIC_QUIET, KERN_ERR "..MP-BIOS bug: "
2249 "8254 timer not connected to IO-APIC\n");
2250
2251 apic_printk(APIC_QUIET, KERN_INFO "...trying to set up timer "
2252 "(IRQ0) through the 8259A ...\n");
2253 apic_printk(APIC_QUIET, KERN_INFO
2254 "..... (found apic %d pin %d) ...\n", apic2, pin2);
2255 /*
2256 * legacy devices should be connected to IO APIC #0
2257 */
2258 replace_pin_at_irq_node(data, node, apic1, pin1, apic2, pin2);
2259 irq_domain_deactivate_irq(irq_data);
2260 irq_domain_activate_irq(irq_data, false);
2261 legacy_pic->unmask(0);
2262 if (timer_irq_works()) {
2263 apic_printk(APIC_QUIET, KERN_INFO "....... works.\n");
2264 goto out;
2265 }
2266 /*
2267 * Cleanup, just in case ...
2268 */
2269 legacy_pic->mask(0);
2270 clear_IO_APIC_pin(apic2, pin2);
2271 apic_printk(APIC_QUIET, KERN_INFO "....... failed.\n");
2272 }
2273
2274 apic_printk(APIC_QUIET, KERN_INFO
2275 "...trying to set up timer as Virtual Wire IRQ...\n");
2276
2277 lapic_register_intr(0);
2278 apic_write(APIC_LVT0, APIC_DM_FIXED | cfg->vector); /* Fixed mode */
2279 legacy_pic->unmask(0);
2280
2281 if (timer_irq_works()) {
2282 apic_printk(APIC_QUIET, KERN_INFO "..... works.\n");
2283 goto out;
2284 }
2285 legacy_pic->mask(0);
2286 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | cfg->vector);
2287 apic_printk(APIC_QUIET, KERN_INFO "..... failed.\n");
2288
2289 apic_printk(APIC_QUIET, KERN_INFO
2290 "...trying to set up timer as ExtINT IRQ...\n");
2291
2292 legacy_pic->init(0);
2293 legacy_pic->make_irq(0);
2294 apic_write(APIC_LVT0, APIC_DM_EXTINT);
2295 legacy_pic->unmask(0);
2296
2297 unlock_ExtINT_logic();
2298
2299 if (timer_irq_works()) {
2300 apic_printk(APIC_QUIET, KERN_INFO "..... works.\n");
2301 goto out;
2302 }
2303 apic_printk(APIC_QUIET, KERN_INFO "..... failed :(.\n");
2304 if (apic_is_x2apic_enabled())
2305 apic_printk(APIC_QUIET, KERN_INFO
2306 "Perhaps problem with the pre-enabled x2apic mode\n"
2307 "Try booting with x2apic and interrupt-remapping disabled in the bios.\n");
2308 panic("IO-APIC + timer doesn't work! Boot with apic=debug and send a "
2309 "report. Then try booting with the 'noapic' option.\n");
2310out:
2311 local_irq_enable();
2312}
2313
2314/*
2315 * Traditionally ISA IRQ2 is the cascade IRQ, and is not available
2316 * to devices. However there may be an I/O APIC pin available for
2317 * this interrupt regardless. The pin may be left unconnected, but
2318 * typically it will be reused as an ExtINT cascade interrupt for
2319 * the master 8259A. In the MPS case such a pin will normally be
2320 * reported as an ExtINT interrupt in the MP table. With ACPI
2321 * there is no provision for ExtINT interrupts, and in the absence
2322 * of an override it would be treated as an ordinary ISA I/O APIC
2323 * interrupt, that is edge-triggered and unmasked by default. We
2324 * used to do this, but it caused problems on some systems because
2325 * of the NMI watchdog and sometimes IRQ0 of the 8254 timer using
2326 * the same ExtINT cascade interrupt to drive the local APIC of the
2327 * bootstrap processor. Therefore we refrain from routing IRQ2 to
2328 * the I/O APIC in all cases now. No actual device should request
2329 * it anyway. --macro
2330 */
2331#define PIC_IRQS (1UL << PIC_CASCADE_IR)
2332
2333static int mp_irqdomain_create(int ioapic)
2334{
2335 struct irq_domain *parent;
2336 int hwirqs = mp_ioapic_pin_count(ioapic);
2337 struct ioapic *ip = &ioapics[ioapic];
2338 struct ioapic_domain_cfg *cfg = &ip->irqdomain_cfg;
2339 struct mp_ioapic_gsi *gsi_cfg = mp_ioapic_gsi_routing(ioapic);
2340 struct fwnode_handle *fn;
2341 struct irq_fwspec fwspec;
2342
2343 if (cfg->type == IOAPIC_DOMAIN_INVALID)
2344 return 0;
2345
2346 /* Handle device tree enumerated APICs proper */
2347 if (cfg->dev) {
2348 fn = of_node_to_fwnode(cfg->dev);
2349 } else {
2350 fn = irq_domain_alloc_named_id_fwnode("IO-APIC", mpc_ioapic_id(ioapic));
2351 if (!fn)
2352 return -ENOMEM;
2353 }
2354
2355 fwspec.fwnode = fn;
2356 fwspec.param_count = 1;
2357 fwspec.param[0] = mpc_ioapic_id(ioapic);
2358
2359 parent = irq_find_matching_fwspec(&fwspec, DOMAIN_BUS_ANY);
2360 if (!parent) {
2361 if (!cfg->dev)
2362 irq_domain_free_fwnode(fn);
2363 return -ENODEV;
2364 }
2365
2366 ip->irqdomain = irq_domain_create_linear(fn, hwirqs, cfg->ops,
2367 (void *)(long)ioapic);
2368
2369 if (!ip->irqdomain) {
2370 /* Release fw handle if it was allocated above */
2371 if (!cfg->dev)
2372 irq_domain_free_fwnode(fn);
2373 return -ENOMEM;
2374 }
2375
2376 ip->irqdomain->parent = parent;
2377
2378 if (cfg->type == IOAPIC_DOMAIN_LEGACY ||
2379 cfg->type == IOAPIC_DOMAIN_STRICT)
2380 ioapic_dynirq_base = max(ioapic_dynirq_base,
2381 gsi_cfg->gsi_end + 1);
2382
2383 return 0;
2384}
2385
2386static void ioapic_destroy_irqdomain(int idx)
2387{
2388 struct ioapic_domain_cfg *cfg = &ioapics[idx].irqdomain_cfg;
2389 struct fwnode_handle *fn = ioapics[idx].irqdomain->fwnode;
2390
2391 if (ioapics[idx].irqdomain) {
2392 irq_domain_remove(ioapics[idx].irqdomain);
2393 if (!cfg->dev)
2394 irq_domain_free_fwnode(fn);
2395 ioapics[idx].irqdomain = NULL;
2396 }
2397}
2398
2399void __init setup_IO_APIC(void)
2400{
2401 int ioapic;
2402
2403 if (skip_ioapic_setup || !nr_ioapics)
2404 return;
2405
2406 io_apic_irqs = nr_legacy_irqs() ? ~PIC_IRQS : ~0UL;
2407
2408 apic_printk(APIC_VERBOSE, "ENABLING IO-APIC IRQs\n");
2409 for_each_ioapic(ioapic)
2410 BUG_ON(mp_irqdomain_create(ioapic));
2411
2412 /*
2413 * Set up IO-APIC IRQ routing.
2414 */
2415 x86_init.mpparse.setup_ioapic_ids();
2416
2417 sync_Arb_IDs();
2418 setup_IO_APIC_irqs();
2419 init_IO_APIC_traps();
2420 if (nr_legacy_irqs())
2421 check_timer();
2422
2423 ioapic_initialized = 1;
2424}
2425
2426static void resume_ioapic_id(int ioapic_idx)
2427{
2428 unsigned long flags;
2429 union IO_APIC_reg_00 reg_00;
2430
2431 raw_spin_lock_irqsave(&ioapic_lock, flags);
2432 reg_00.raw = io_apic_read(ioapic_idx, 0);
2433 if (reg_00.bits.ID != mpc_ioapic_id(ioapic_idx)) {
2434 reg_00.bits.ID = mpc_ioapic_id(ioapic_idx);
2435 io_apic_write(ioapic_idx, 0, reg_00.raw);
2436 }
2437 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2438}
2439
2440static void ioapic_resume(void)
2441{
2442 int ioapic_idx;
2443
2444 for_each_ioapic_reverse(ioapic_idx)
2445 resume_ioapic_id(ioapic_idx);
2446
2447 restore_ioapic_entries();
2448}
2449
2450static struct syscore_ops ioapic_syscore_ops = {
2451 .suspend = save_ioapic_entries,
2452 .resume = ioapic_resume,
2453};
2454
2455static int __init ioapic_init_ops(void)
2456{
2457 register_syscore_ops(&ioapic_syscore_ops);
2458
2459 return 0;
2460}
2461
2462device_initcall(ioapic_init_ops);
2463
2464static int io_apic_get_redir_entries(int ioapic)
2465{
2466 union IO_APIC_reg_01 reg_01;
2467 unsigned long flags;
2468
2469 raw_spin_lock_irqsave(&ioapic_lock, flags);
2470 reg_01.raw = io_apic_read(ioapic, 1);
2471 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2472
2473 /* The register returns the maximum index redir index
2474 * supported, which is one less than the total number of redir
2475 * entries.
2476 */
2477 return reg_01.bits.entries + 1;
2478}
2479
2480unsigned int arch_dynirq_lower_bound(unsigned int from)
2481{
2482 /*
2483 * dmar_alloc_hwirq() may be called before setup_IO_APIC(), so use
2484 * gsi_top if ioapic_dynirq_base hasn't been initialized yet.
2485 */
2486 if (!ioapic_initialized)
2487 return gsi_top;
2488 /*
2489 * For DT enabled machines ioapic_dynirq_base is irrelevant and not
2490 * updated. So simply return @from if ioapic_dynirq_base == 0.
2491 */
2492 return ioapic_dynirq_base ? : from;
2493}
2494
2495#ifdef CONFIG_X86_32
2496static int io_apic_get_unique_id(int ioapic, int apic_id)
2497{
2498 union IO_APIC_reg_00 reg_00;
2499 static physid_mask_t apic_id_map = PHYSID_MASK_NONE;
2500 physid_mask_t tmp;
2501 unsigned long flags;
2502 int i = 0;
2503
2504 /*
2505 * The P4 platform supports up to 256 APIC IDs on two separate APIC
2506 * buses (one for LAPICs, one for IOAPICs), where predecessors only
2507 * supports up to 16 on one shared APIC bus.
2508 *
2509 * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full
2510 * advantage of new APIC bus architecture.
2511 */
2512
2513 if (physids_empty(apic_id_map))
2514 apic->ioapic_phys_id_map(&phys_cpu_present_map, &apic_id_map);
2515
2516 raw_spin_lock_irqsave(&ioapic_lock, flags);
2517 reg_00.raw = io_apic_read(ioapic, 0);
2518 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2519
2520 if (apic_id >= get_physical_broadcast()) {
2521 printk(KERN_WARNING "IOAPIC[%d]: Invalid apic_id %d, trying "
2522 "%d\n", ioapic, apic_id, reg_00.bits.ID);
2523 apic_id = reg_00.bits.ID;
2524 }
2525
2526 /*
2527 * Every APIC in a system must have a unique ID or we get lots of nice
2528 * 'stuck on smp_invalidate_needed IPI wait' messages.
2529 */
2530 if (apic->check_apicid_used(&apic_id_map, apic_id)) {
2531
2532 for (i = 0; i < get_physical_broadcast(); i++) {
2533 if (!apic->check_apicid_used(&apic_id_map, i))
2534 break;
2535 }
2536
2537 if (i == get_physical_broadcast())
2538 panic("Max apic_id exceeded!\n");
2539
2540 printk(KERN_WARNING "IOAPIC[%d]: apic_id %d already used, "
2541 "trying %d\n", ioapic, apic_id, i);
2542
2543 apic_id = i;
2544 }
2545
2546 apic->apicid_to_cpu_present(apic_id, &tmp);
2547 physids_or(apic_id_map, apic_id_map, tmp);
2548
2549 if (reg_00.bits.ID != apic_id) {
2550 reg_00.bits.ID = apic_id;
2551
2552 raw_spin_lock_irqsave(&ioapic_lock, flags);
2553 io_apic_write(ioapic, 0, reg_00.raw);
2554 reg_00.raw = io_apic_read(ioapic, 0);
2555 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2556
2557 /* Sanity check */
2558 if (reg_00.bits.ID != apic_id) {
2559 pr_err("IOAPIC[%d]: Unable to change apic_id!\n",
2560 ioapic);
2561 return -1;
2562 }
2563 }
2564
2565 apic_printk(APIC_VERBOSE, KERN_INFO
2566 "IOAPIC[%d]: Assigned apic_id %d\n", ioapic, apic_id);
2567
2568 return apic_id;
2569}
2570
2571static u8 io_apic_unique_id(int idx, u8 id)
2572{
2573 if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) &&
2574 !APIC_XAPIC(boot_cpu_apic_version))
2575 return io_apic_get_unique_id(idx, id);
2576 else
2577 return id;
2578}
2579#else
2580static u8 io_apic_unique_id(int idx, u8 id)
2581{
2582 union IO_APIC_reg_00 reg_00;
2583 DECLARE_BITMAP(used, 256);
2584 unsigned long flags;
2585 u8 new_id;
2586 int i;
2587
2588 bitmap_zero(used, 256);
2589 for_each_ioapic(i)
2590 __set_bit(mpc_ioapic_id(i), used);
2591
2592 /* Hand out the requested id if available */
2593 if (!test_bit(id, used))
2594 return id;
2595
2596 /*
2597 * Read the current id from the ioapic and keep it if
2598 * available.
2599 */
2600 raw_spin_lock_irqsave(&ioapic_lock, flags);
2601 reg_00.raw = io_apic_read(idx, 0);
2602 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2603 new_id = reg_00.bits.ID;
2604 if (!test_bit(new_id, used)) {
2605 apic_printk(APIC_VERBOSE, KERN_INFO
2606 "IOAPIC[%d]: Using reg apic_id %d instead of %d\n",
2607 idx, new_id, id);
2608 return new_id;
2609 }
2610
2611 /*
2612 * Get the next free id and write it to the ioapic.
2613 */
2614 new_id = find_first_zero_bit(used, 256);
2615 reg_00.bits.ID = new_id;
2616 raw_spin_lock_irqsave(&ioapic_lock, flags);
2617 io_apic_write(idx, 0, reg_00.raw);
2618 reg_00.raw = io_apic_read(idx, 0);
2619 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2620 /* Sanity check */
2621 BUG_ON(reg_00.bits.ID != new_id);
2622
2623 return new_id;
2624}
2625#endif
2626
2627static int io_apic_get_version(int ioapic)
2628{
2629 union IO_APIC_reg_01 reg_01;
2630 unsigned long flags;
2631
2632 raw_spin_lock_irqsave(&ioapic_lock, flags);
2633 reg_01.raw = io_apic_read(ioapic, 1);
2634 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2635
2636 return reg_01.bits.version;
2637}
2638
2639/*
2640 * This function updates target affinity of IOAPIC interrupts to include
2641 * the CPUs which came online during SMP bringup.
2642 */
2643#define IOAPIC_RESOURCE_NAME_SIZE 11
2644
2645static struct resource *ioapic_resources;
2646
2647static struct resource * __init ioapic_setup_resources(void)
2648{
2649 unsigned long n;
2650 struct resource *res;
2651 char *mem;
2652 int i;
2653
2654 if (nr_ioapics == 0)
2655 return NULL;
2656
2657 n = IOAPIC_RESOURCE_NAME_SIZE + sizeof(struct resource);
2658 n *= nr_ioapics;
2659
2660 mem = memblock_alloc(n, SMP_CACHE_BYTES);
2661 if (!mem)
2662 panic("%s: Failed to allocate %lu bytes\n", __func__, n);
2663 res = (void *)mem;
2664
2665 mem += sizeof(struct resource) * nr_ioapics;
2666
2667 for_each_ioapic(i) {
2668 res[i].name = mem;
2669 res[i].flags = IORESOURCE_MEM | IORESOURCE_BUSY;
2670 snprintf(mem, IOAPIC_RESOURCE_NAME_SIZE, "IOAPIC %u", i);
2671 mem += IOAPIC_RESOURCE_NAME_SIZE;
2672 ioapics[i].iomem_res = &res[i];
2673 }
2674
2675 ioapic_resources = res;
2676
2677 return res;
2678}
2679
2680void __init io_apic_init_mappings(void)
2681{
2682 unsigned long ioapic_phys, idx = FIX_IO_APIC_BASE_0;
2683 struct resource *ioapic_res;
2684 int i;
2685
2686 ioapic_res = ioapic_setup_resources();
2687 for_each_ioapic(i) {
2688 if (smp_found_config) {
2689 ioapic_phys = mpc_ioapic_addr(i);
2690#ifdef CONFIG_X86_32
2691 if (!ioapic_phys) {
2692 printk(KERN_ERR
2693 "WARNING: bogus zero IO-APIC "
2694 "address found in MPTABLE, "
2695 "disabling IO/APIC support!\n");
2696 smp_found_config = 0;
2697 skip_ioapic_setup = 1;
2698 goto fake_ioapic_page;
2699 }
2700#endif
2701 } else {
2702#ifdef CONFIG_X86_32
2703fake_ioapic_page:
2704#endif
2705 ioapic_phys = (unsigned long)memblock_alloc(PAGE_SIZE,
2706 PAGE_SIZE);
2707 if (!ioapic_phys)
2708 panic("%s: Failed to allocate %lu bytes align=0x%lx\n",
2709 __func__, PAGE_SIZE, PAGE_SIZE);
2710 ioapic_phys = __pa(ioapic_phys);
2711 }
2712 set_fixmap_nocache(idx, ioapic_phys);
2713 apic_printk(APIC_VERBOSE, "mapped IOAPIC to %08lx (%08lx)\n",
2714 __fix_to_virt(idx) + (ioapic_phys & ~PAGE_MASK),
2715 ioapic_phys);
2716 idx++;
2717
2718 ioapic_res->start = ioapic_phys;
2719 ioapic_res->end = ioapic_phys + IO_APIC_SLOT_SIZE - 1;
2720 ioapic_res++;
2721 }
2722}
2723
2724void __init ioapic_insert_resources(void)
2725{
2726 int i;
2727 struct resource *r = ioapic_resources;
2728
2729 if (!r) {
2730 if (nr_ioapics > 0)
2731 printk(KERN_ERR
2732 "IO APIC resources couldn't be allocated.\n");
2733 return;
2734 }
2735
2736 for_each_ioapic(i) {
2737 insert_resource(&iomem_resource, r);
2738 r++;
2739 }
2740}
2741
2742int mp_find_ioapic(u32 gsi)
2743{
2744 int i;
2745
2746 if (nr_ioapics == 0)
2747 return -1;
2748
2749 /* Find the IOAPIC that manages this GSI. */
2750 for_each_ioapic(i) {
2751 struct mp_ioapic_gsi *gsi_cfg = mp_ioapic_gsi_routing(i);
2752 if (gsi >= gsi_cfg->gsi_base && gsi <= gsi_cfg->gsi_end)
2753 return i;
2754 }
2755
2756 printk(KERN_ERR "ERROR: Unable to locate IOAPIC for GSI %d\n", gsi);
2757 return -1;
2758}
2759
2760int mp_find_ioapic_pin(int ioapic, u32 gsi)
2761{
2762 struct mp_ioapic_gsi *gsi_cfg;
2763
2764 if (WARN_ON(ioapic < 0))
2765 return -1;
2766
2767 gsi_cfg = mp_ioapic_gsi_routing(ioapic);
2768 if (WARN_ON(gsi > gsi_cfg->gsi_end))
2769 return -1;
2770
2771 return gsi - gsi_cfg->gsi_base;
2772}
2773
2774static int bad_ioapic_register(int idx)
2775{
2776 union IO_APIC_reg_00 reg_00;
2777 union IO_APIC_reg_01 reg_01;
2778 union IO_APIC_reg_02 reg_02;
2779
2780 reg_00.raw = io_apic_read(idx, 0);
2781 reg_01.raw = io_apic_read(idx, 1);
2782 reg_02.raw = io_apic_read(idx, 2);
2783
2784 if (reg_00.raw == -1 && reg_01.raw == -1 && reg_02.raw == -1) {
2785 pr_warn("I/O APIC 0x%x registers return all ones, skipping!\n",
2786 mpc_ioapic_addr(idx));
2787 return 1;
2788 }
2789
2790 return 0;
2791}
2792
2793static int find_free_ioapic_entry(void)
2794{
2795 int idx;
2796
2797 for (idx = 0; idx < MAX_IO_APICS; idx++)
2798 if (ioapics[idx].nr_registers == 0)
2799 return idx;
2800
2801 return MAX_IO_APICS;
2802}
2803
2804/**
2805 * mp_register_ioapic - Register an IOAPIC device
2806 * @id: hardware IOAPIC ID
2807 * @address: physical address of IOAPIC register area
2808 * @gsi_base: base of GSI associated with the IOAPIC
2809 * @cfg: configuration information for the IOAPIC
2810 */
2811int mp_register_ioapic(int id, u32 address, u32 gsi_base,
2812 struct ioapic_domain_cfg *cfg)
2813{
2814 bool hotplug = !!ioapic_initialized;
2815 struct mp_ioapic_gsi *gsi_cfg;
2816 int idx, ioapic, entries;
2817 u32 gsi_end;
2818
2819 if (!address) {
2820 pr_warn("Bogus (zero) I/O APIC address found, skipping!\n");
2821 return -EINVAL;
2822 }
2823 for_each_ioapic(ioapic)
2824 if (ioapics[ioapic].mp_config.apicaddr == address) {
2825 pr_warn("address 0x%x conflicts with IOAPIC%d\n",
2826 address, ioapic);
2827 return -EEXIST;
2828 }
2829
2830 idx = find_free_ioapic_entry();
2831 if (idx >= MAX_IO_APICS) {
2832 pr_warn("Max # of I/O APICs (%d) exceeded (found %d), skipping\n",
2833 MAX_IO_APICS, idx);
2834 return -ENOSPC;
2835 }
2836
2837 ioapics[idx].mp_config.type = MP_IOAPIC;
2838 ioapics[idx].mp_config.flags = MPC_APIC_USABLE;
2839 ioapics[idx].mp_config.apicaddr = address;
2840
2841 set_fixmap_nocache(FIX_IO_APIC_BASE_0 + idx, address);
2842 if (bad_ioapic_register(idx)) {
2843 clear_fixmap(FIX_IO_APIC_BASE_0 + idx);
2844 return -ENODEV;
2845 }
2846
2847 ioapics[idx].mp_config.apicid = io_apic_unique_id(idx, id);
2848 ioapics[idx].mp_config.apicver = io_apic_get_version(idx);
2849
2850 /*
2851 * Build basic GSI lookup table to facilitate gsi->io_apic lookups
2852 * and to prevent reprogramming of IOAPIC pins (PCI GSIs).
2853 */
2854 entries = io_apic_get_redir_entries(idx);
2855 gsi_end = gsi_base + entries - 1;
2856 for_each_ioapic(ioapic) {
2857 gsi_cfg = mp_ioapic_gsi_routing(ioapic);
2858 if ((gsi_base >= gsi_cfg->gsi_base &&
2859 gsi_base <= gsi_cfg->gsi_end) ||
2860 (gsi_end >= gsi_cfg->gsi_base &&
2861 gsi_end <= gsi_cfg->gsi_end)) {
2862 pr_warn("GSI range [%u-%u] for new IOAPIC conflicts with GSI[%u-%u]\n",
2863 gsi_base, gsi_end,
2864 gsi_cfg->gsi_base, gsi_cfg->gsi_end);
2865 clear_fixmap(FIX_IO_APIC_BASE_0 + idx);
2866 return -ENOSPC;
2867 }
2868 }
2869 gsi_cfg = mp_ioapic_gsi_routing(idx);
2870 gsi_cfg->gsi_base = gsi_base;
2871 gsi_cfg->gsi_end = gsi_end;
2872
2873 ioapics[idx].irqdomain = NULL;
2874 ioapics[idx].irqdomain_cfg = *cfg;
2875
2876 /*
2877 * If mp_register_ioapic() is called during early boot stage when
2878 * walking ACPI/DT tables, it's too early to create irqdomain,
2879 * we are still using bootmem allocator. So delay it to setup_IO_APIC().
2880 */
2881 if (hotplug) {
2882 if (mp_irqdomain_create(idx)) {
2883 clear_fixmap(FIX_IO_APIC_BASE_0 + idx);
2884 return -ENOMEM;
2885 }
2886 alloc_ioapic_saved_registers(idx);
2887 }
2888
2889 if (gsi_cfg->gsi_end >= gsi_top)
2890 gsi_top = gsi_cfg->gsi_end + 1;
2891 if (nr_ioapics <= idx)
2892 nr_ioapics = idx + 1;
2893
2894 /* Set nr_registers to mark entry present */
2895 ioapics[idx].nr_registers = entries;
2896
2897 pr_info("IOAPIC[%d]: apic_id %d, version %d, address 0x%x, GSI %d-%d\n",
2898 idx, mpc_ioapic_id(idx),
2899 mpc_ioapic_ver(idx), mpc_ioapic_addr(idx),
2900 gsi_cfg->gsi_base, gsi_cfg->gsi_end);
2901
2902 return 0;
2903}
2904
2905int mp_unregister_ioapic(u32 gsi_base)
2906{
2907 int ioapic, pin;
2908 int found = 0;
2909
2910 for_each_ioapic(ioapic)
2911 if (ioapics[ioapic].gsi_config.gsi_base == gsi_base) {
2912 found = 1;
2913 break;
2914 }
2915 if (!found) {
2916 pr_warn("can't find IOAPIC for GSI %d\n", gsi_base);
2917 return -ENODEV;
2918 }
2919
2920 for_each_pin(ioapic, pin) {
2921 u32 gsi = mp_pin_to_gsi(ioapic, pin);
2922 int irq = mp_map_gsi_to_irq(gsi, 0, NULL);
2923 struct mp_chip_data *data;
2924
2925 if (irq >= 0) {
2926 data = irq_get_chip_data(irq);
2927 if (data && data->count) {
2928 pr_warn("pin%d on IOAPIC%d is still in use.\n",
2929 pin, ioapic);
2930 return -EBUSY;
2931 }
2932 }
2933 }
2934
2935 /* Mark entry not present */
2936 ioapics[ioapic].nr_registers = 0;
2937 ioapic_destroy_irqdomain(ioapic);
2938 free_ioapic_saved_registers(ioapic);
2939 if (ioapics[ioapic].iomem_res)
2940 release_resource(ioapics[ioapic].iomem_res);
2941 clear_fixmap(FIX_IO_APIC_BASE_0 + ioapic);
2942 memset(&ioapics[ioapic], 0, sizeof(ioapics[ioapic]));
2943
2944 return 0;
2945}
2946
2947int mp_ioapic_registered(u32 gsi_base)
2948{
2949 int ioapic;
2950
2951 for_each_ioapic(ioapic)
2952 if (ioapics[ioapic].gsi_config.gsi_base == gsi_base)
2953 return 1;
2954
2955 return 0;
2956}
2957
2958static void mp_irqdomain_get_attr(u32 gsi, struct mp_chip_data *data,
2959 struct irq_alloc_info *info)
2960{
2961 if (info && info->ioapic.valid) {
2962 data->is_level = info->ioapic.is_level;
2963 data->active_low = info->ioapic.active_low;
2964 } else if (__acpi_get_override_irq(gsi, &data->is_level,
2965 &data->active_low) < 0) {
2966 /* PCI interrupts are always active low level triggered. */
2967 data->is_level = true;
2968 data->active_low = true;
2969 }
2970}
2971
2972/*
2973 * Configure the I/O-APIC specific fields in the routing entry.
2974 *
2975 * This is important to setup the I/O-APIC specific bits (is_level,
2976 * active_low, masked) because the underlying parent domain will only
2977 * provide the routing information and is oblivious of the I/O-APIC
2978 * specific bits.
2979 *
2980 * The entry is just preconfigured at this point and not written into the
2981 * RTE. This happens later during activation which will fill in the actual
2982 * routing information.
2983 */
2984static void mp_preconfigure_entry(struct mp_chip_data *data)
2985{
2986 struct IO_APIC_route_entry *entry = &data->entry;
2987
2988 memset(entry, 0, sizeof(*entry));
2989 entry->is_level = data->is_level;
2990 entry->active_low = data->active_low;
2991 /*
2992 * Mask level triggered irqs. Edge triggered irqs are masked
2993 * by the irq core code in case they fire.
2994 */
2995 entry->masked = data->is_level;
2996}
2997
2998int mp_irqdomain_alloc(struct irq_domain *domain, unsigned int virq,
2999 unsigned int nr_irqs, void *arg)
3000{
3001 struct irq_alloc_info *info = arg;
3002 struct mp_chip_data *data;
3003 struct irq_data *irq_data;
3004 int ret, ioapic, pin;
3005 unsigned long flags;
3006
3007 if (!info || nr_irqs > 1)
3008 return -EINVAL;
3009 irq_data = irq_domain_get_irq_data(domain, virq);
3010 if (!irq_data)
3011 return -EINVAL;
3012
3013 ioapic = mp_irqdomain_ioapic_idx(domain);
3014 pin = info->ioapic.pin;
3015 if (irq_find_mapping(domain, (irq_hw_number_t)pin) > 0)
3016 return -EEXIST;
3017
3018 data = kzalloc(sizeof(*data), GFP_KERNEL);
3019 if (!data)
3020 return -ENOMEM;
3021
3022 ret = irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, info);
3023 if (ret < 0) {
3024 kfree(data);
3025 return ret;
3026 }
3027
3028 INIT_LIST_HEAD(&data->irq_2_pin);
3029 irq_data->hwirq = info->ioapic.pin;
3030 irq_data->chip = (domain->parent == x86_vector_domain) ?
3031 &ioapic_chip : &ioapic_ir_chip;
3032 irq_data->chip_data = data;
3033 mp_irqdomain_get_attr(mp_pin_to_gsi(ioapic, pin), data, info);
3034
3035 add_pin_to_irq_node(data, ioapic_alloc_attr_node(info), ioapic, pin);
3036
3037 mp_preconfigure_entry(data);
3038 mp_register_handler(virq, data->is_level);
3039
3040 local_irq_save(flags);
3041 if (virq < nr_legacy_irqs())
3042 legacy_pic->mask(virq);
3043 local_irq_restore(flags);
3044
3045 apic_printk(APIC_VERBOSE, KERN_DEBUG
3046 "IOAPIC[%d]: Preconfigured routing entry (%d-%d -> IRQ %d Level:%i ActiveLow:%i)\n",
3047 ioapic, mpc_ioapic_id(ioapic), pin, virq,
3048 data->is_level, data->active_low);
3049 return 0;
3050}
3051
3052void mp_irqdomain_free(struct irq_domain *domain, unsigned int virq,
3053 unsigned int nr_irqs)
3054{
3055 struct irq_data *irq_data;
3056 struct mp_chip_data *data;
3057
3058 BUG_ON(nr_irqs != 1);
3059 irq_data = irq_domain_get_irq_data(domain, virq);
3060 if (irq_data && irq_data->chip_data) {
3061 data = irq_data->chip_data;
3062 __remove_pin_from_irq(data, mp_irqdomain_ioapic_idx(domain),
3063 (int)irq_data->hwirq);
3064 WARN_ON(!list_empty(&data->irq_2_pin));
3065 kfree(irq_data->chip_data);
3066 }
3067 irq_domain_free_irqs_top(domain, virq, nr_irqs);
3068}
3069
3070int mp_irqdomain_activate(struct irq_domain *domain,
3071 struct irq_data *irq_data, bool reserve)
3072{
3073 unsigned long flags;
3074
3075 raw_spin_lock_irqsave(&ioapic_lock, flags);
3076 ioapic_configure_entry(irq_data);
3077 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
3078 return 0;
3079}
3080
3081void mp_irqdomain_deactivate(struct irq_domain *domain,
3082 struct irq_data *irq_data)
3083{
3084 /* It won't be called for IRQ with multiple IOAPIC pins associated */
3085 ioapic_mask_entry(mp_irqdomain_ioapic_idx(domain),
3086 (int)irq_data->hwirq);
3087}
3088
3089int mp_irqdomain_ioapic_idx(struct irq_domain *domain)
3090{
3091 return (int)(long)domain->host_data;
3092}
3093
3094const struct irq_domain_ops mp_ioapic_irqdomain_ops = {
3095 .alloc = mp_irqdomain_alloc,
3096 .free = mp_irqdomain_free,
3097 .activate = mp_irqdomain_activate,
3098 .deactivate = mp_irqdomain_deactivate,
3099};