1/* SPDX-License-Identifier: GPL-2.0-or-later */
 
 
 2/*
 3 * AT91 Power Management
 
 4 *
 5 * Copyright (C) 2005 David Brownell
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 6 */
 7#ifndef __ARCH_ARM_MACH_AT91_PM
 8#define __ARCH_ARM_MACH_AT91_PM
 9
10#include <asm/proc-fns.h>
 
 
 
 
 
11
12#include <linux/mfd/syscon/atmel-mc.h>
13#include <soc/at91/at91sam9_ddrsdr.h>
14#include <soc/at91/at91sam9_sdramc.h>
15#include <soc/at91/sama7-ddr.h>
16#include <soc/at91/sama7-sfrbu.h>
17
18#define AT91_MEMCTRL_MC		0
19#define AT91_MEMCTRL_SDRAMC	1
20#define AT91_MEMCTRL_DDRSDR	2
21
22#define	AT91_PM_STANDBY		0x00
23#define AT91_PM_ULP0		0x01
24#define AT91_PM_ULP0_FAST	0x02
25#define AT91_PM_ULP1		0x03
26#define	AT91_PM_BACKUP		0x04
27
28#ifndef __ASSEMBLY__
29struct at91_pm_data {
30	void __iomem *pmc;
31	void __iomem *ramc[2];
32	void __iomem *ramc_phy;
33	unsigned long uhp_udp_mask;
34	unsigned int memctrl;
35	unsigned int mode;
36	void __iomem *shdwc;
37	void __iomem *sfrbu;
38	unsigned int standby_mode;
39	unsigned int suspend_mode;
40	unsigned int pmc_mckr_offset;
41	unsigned int pmc_version;
42};
43#endif
 
 
 
 
 
 
 
 
 
 
 
 
 
 
44
45#endif

  1#ifdef CONFIG_ARCH_AT91RM9200
  2#include <mach/at91rm9200_mc.h>
  3
  4/*
  5 * The AT91RM9200 goes into self-refresh mode with this command, and will
  6 * terminate self-refresh automatically on the next SDRAM access.
  7 *
  8 * Self-refresh mode is exited as soon as a memory access is made, but we don't
  9 * know for sure when that happens. However, we need to restore the low-power
 10 * mode if it was enabled before going idle. Restoring low-power mode while
 11 * still in self-refresh is "not recommended", but seems to work.
 12 */
 13
 14static inline u32 sdram_selfrefresh_enable(void)
 15{
 16	u32 saved_lpr = at91_sys_read(AT91_SDRAMC_LPR);
 17
 18	at91_sys_write(AT91_SDRAMC_LPR, 0);
 19	at91_sys_write(AT91_SDRAMC_SRR, 1);
 20	return saved_lpr;
 21}
 22
 23#define sdram_selfrefresh_disable(saved_lpr)	at91_sys_write(AT91_SDRAMC_LPR, saved_lpr)
 24#define wait_for_interrupt_enable()		asm volatile ("mcr p15, 0, %0, c7, c0, 4" \
 25								: : "r" (0))
 26
 27#elif defined(CONFIG_ARCH_AT91CAP9)
 28#include <mach/at91cap9_ddrsdr.h>
 29
 30
 31static inline u32 sdram_selfrefresh_enable(void)
 32{
 33	u32 saved_lpr, lpr;
 34
 35	saved_lpr = at91_ramc_read(0, AT91_DDRSDRC_LPR);
 36
 37	lpr = saved_lpr & ~AT91_DDRSDRC_LPCB;
 38	at91_ramc_write(0, AT91_DDRSDRC_LPR, lpr | AT91_DDRSDRC_LPCB_SELF_REFRESH);
 39	return saved_lpr;
 40}
 41
 42#define sdram_selfrefresh_disable(saved_lpr)	at91_ramc_write(0, AT91_DDRSDRC_LPR, saved_lpr)
 43#define wait_for_interrupt_enable()		cpu_do_idle()
 44
 45#elif defined(CONFIG_ARCH_AT91SAM9G45)
 46#include <mach/at91sam9_ddrsdr.h>
 47
 48/* We manage both DDRAM/SDRAM controllers, we need more than one value to
 49 * remember.
 50 */
 51static u32 saved_lpr1;
 
 52
 53static inline u32 sdram_selfrefresh_enable(void)
 54{
 55	/* Those tow values allow us to delay self-refresh activation
 56	 * to the maximum. */
 57	u32 lpr0, lpr1;
 58	u32 saved_lpr0;
 59
 60	saved_lpr1 = at91_ramc_read(1, AT91_DDRSDRC_LPR);
 61	lpr1 = saved_lpr1 & ~AT91_DDRSDRC_LPCB;
 62	lpr1 |= AT91_DDRSDRC_LPCB_SELF_REFRESH;
 63
 64	saved_lpr0 = at91_ramc_read(0, AT91_DDRSDRC_LPR);
 65	lpr0 = saved_lpr0 & ~AT91_DDRSDRC_LPCB;
 66	lpr0 |= AT91_DDRSDRC_LPCB_SELF_REFRESH;
 67
 68	/* self-refresh mode now */
 69	at91_ramc_write(0, AT91_DDRSDRC_LPR, lpr0);
 70	at91_ramc_write(1, AT91_DDRSDRC_LPR, lpr1);
 71
 72	return saved_lpr0;
 73}
 74
 75#define sdram_selfrefresh_disable(saved_lpr0)	\
 76	do { \
 77		at91_ramc_write(0, AT91_DDRSDRC_LPR, saved_lpr0); \
 78		at91_ramc_write(1, AT91_DDRSDRC_LPR, saved_lpr1); \
 79	} while (0)
 80#define wait_for_interrupt_enable()		cpu_do_idle()
 81
 82#else
 83#include <mach/at91sam9_sdramc.h>
 84
 85#ifdef CONFIG_ARCH_AT91SAM9263
 86/*
 87 * FIXME either or both the SDRAM controllers (EB0, EB1) might be in use;
 88 * handle those cases both here and in the Suspend-To-RAM support.
 89 */
 90#warning Assuming EB1 SDRAM controller is *NOT* used
 91#endif
 92
 93static inline u32 sdram_selfrefresh_enable(void)
 94{
 95	u32 saved_lpr, lpr;
 96
 97	saved_lpr = at91_ramc_read(0, AT91_SDRAMC_LPR);
 98
 99	lpr = saved_lpr & ~AT91_SDRAMC_LPCB;
100	at91_ramc_write(0, AT91_SDRAMC_LPR, lpr | AT91_SDRAMC_LPCB_SELF_REFRESH);
101	return saved_lpr;
102}
103
104#define sdram_selfrefresh_disable(saved_lpr)	at91_ramc_write(0, AT91_SDRAMC_LPR, saved_lpr)
105#define wait_for_interrupt_enable()		cpu_do_idle()
106
107#endif