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1// SPDX-License-Identifier: GPL-2.0+
2//
3// Copyright 2013 Freescale Semiconductor, Inc.
4// Copyright 2020 NXP
5//
6// Freescale DSPI driver
7// This file contains a driver for the Freescale DSPI
8
9#include <linux/clk.h>
10#include <linux/delay.h>
11#include <linux/dmaengine.h>
12#include <linux/dma-mapping.h>
13#include <linux/interrupt.h>
14#include <linux/kernel.h>
15#include <linux/module.h>
16#include <linux/of_device.h>
17#include <linux/pinctrl/consumer.h>
18#include <linux/regmap.h>
19#include <linux/spi/spi.h>
20#include <linux/spi/spi-fsl-dspi.h>
21
22#define DRIVER_NAME "fsl-dspi"
23
24#define SPI_MCR 0x00
25#define SPI_MCR_MASTER BIT(31)
26#define SPI_MCR_PCSIS(x) ((x) << 16)
27#define SPI_MCR_CLR_TXF BIT(11)
28#define SPI_MCR_CLR_RXF BIT(10)
29#define SPI_MCR_XSPI BIT(3)
30#define SPI_MCR_DIS_TXF BIT(13)
31#define SPI_MCR_DIS_RXF BIT(12)
32#define SPI_MCR_HALT BIT(0)
33
34#define SPI_TCR 0x08
35#define SPI_TCR_GET_TCNT(x) (((x) & GENMASK(31, 16)) >> 16)
36
37#define SPI_CTAR(x) (0x0c + (((x) & GENMASK(1, 0)) * 4))
38#define SPI_CTAR_FMSZ(x) (((x) << 27) & GENMASK(30, 27))
39#define SPI_CTAR_CPOL BIT(26)
40#define SPI_CTAR_CPHA BIT(25)
41#define SPI_CTAR_LSBFE BIT(24)
42#define SPI_CTAR_PCSSCK(x) (((x) << 22) & GENMASK(23, 22))
43#define SPI_CTAR_PASC(x) (((x) << 20) & GENMASK(21, 20))
44#define SPI_CTAR_PDT(x) (((x) << 18) & GENMASK(19, 18))
45#define SPI_CTAR_PBR(x) (((x) << 16) & GENMASK(17, 16))
46#define SPI_CTAR_CSSCK(x) (((x) << 12) & GENMASK(15, 12))
47#define SPI_CTAR_ASC(x) (((x) << 8) & GENMASK(11, 8))
48#define SPI_CTAR_DT(x) (((x) << 4) & GENMASK(7, 4))
49#define SPI_CTAR_BR(x) ((x) & GENMASK(3, 0))
50#define SPI_CTAR_SCALE_BITS 0xf
51
52#define SPI_CTAR0_SLAVE 0x0c
53
54#define SPI_SR 0x2c
55#define SPI_SR_TCFQF BIT(31)
56#define SPI_SR_EOQF BIT(28)
57#define SPI_SR_TFUF BIT(27)
58#define SPI_SR_TFFF BIT(25)
59#define SPI_SR_CMDTCF BIT(23)
60#define SPI_SR_SPEF BIT(21)
61#define SPI_SR_RFOF BIT(19)
62#define SPI_SR_TFIWF BIT(18)
63#define SPI_SR_RFDF BIT(17)
64#define SPI_SR_CMDFFF BIT(16)
65#define SPI_SR_CLEAR (SPI_SR_TCFQF | SPI_SR_EOQF | \
66 SPI_SR_TFUF | SPI_SR_TFFF | \
67 SPI_SR_CMDTCF | SPI_SR_SPEF | \
68 SPI_SR_RFOF | SPI_SR_TFIWF | \
69 SPI_SR_RFDF | SPI_SR_CMDFFF)
70
71#define SPI_RSER_TFFFE BIT(25)
72#define SPI_RSER_TFFFD BIT(24)
73#define SPI_RSER_RFDFE BIT(17)
74#define SPI_RSER_RFDFD BIT(16)
75
76#define SPI_RSER 0x30
77#define SPI_RSER_TCFQE BIT(31)
78#define SPI_RSER_EOQFE BIT(28)
79#define SPI_RSER_CMDTCFE BIT(23)
80
81#define SPI_PUSHR 0x34
82#define SPI_PUSHR_CMD_CONT BIT(15)
83#define SPI_PUSHR_CMD_CTAS(x) (((x) << 12 & GENMASK(14, 12)))
84#define SPI_PUSHR_CMD_EOQ BIT(11)
85#define SPI_PUSHR_CMD_CTCNT BIT(10)
86#define SPI_PUSHR_CMD_PCS(x) (BIT(x) & GENMASK(5, 0))
87
88#define SPI_PUSHR_SLAVE 0x34
89
90#define SPI_POPR 0x38
91
92#define SPI_TXFR0 0x3c
93#define SPI_TXFR1 0x40
94#define SPI_TXFR2 0x44
95#define SPI_TXFR3 0x48
96#define SPI_RXFR0 0x7c
97#define SPI_RXFR1 0x80
98#define SPI_RXFR2 0x84
99#define SPI_RXFR3 0x88
100
101#define SPI_CTARE(x) (0x11c + (((x) & GENMASK(1, 0)) * 4))
102#define SPI_CTARE_FMSZE(x) (((x) & 0x1) << 16)
103#define SPI_CTARE_DTCP(x) ((x) & 0x7ff)
104
105#define SPI_SREX 0x13c
106
107#define SPI_FRAME_BITS(bits) SPI_CTAR_FMSZ((bits) - 1)
108#define SPI_FRAME_EBITS(bits) SPI_CTARE_FMSZE(((bits) - 1) >> 4)
109
110#define DMA_COMPLETION_TIMEOUT msecs_to_jiffies(3000)
111
112struct chip_data {
113 u32 ctar_val;
114};
115
116enum dspi_trans_mode {
117 DSPI_EOQ_MODE = 0,
118 DSPI_XSPI_MODE,
119 DSPI_DMA_MODE,
120};
121
122struct fsl_dspi_devtype_data {
123 enum dspi_trans_mode trans_mode;
124 u8 max_clock_factor;
125 int fifo_size;
126};
127
128enum {
129 LS1021A,
130 LS1012A,
131 LS1028A,
132 LS1043A,
133 LS1046A,
134 LS2080A,
135 LS2085A,
136 LX2160A,
137 MCF5441X,
138 VF610,
139};
140
141static const struct fsl_dspi_devtype_data devtype_data[] = {
142 [VF610] = {
143 .trans_mode = DSPI_DMA_MODE,
144 .max_clock_factor = 2,
145 .fifo_size = 4,
146 },
147 [LS1021A] = {
148 /* Has A-011218 DMA erratum */
149 .trans_mode = DSPI_XSPI_MODE,
150 .max_clock_factor = 8,
151 .fifo_size = 4,
152 },
153 [LS1012A] = {
154 /* Has A-011218 DMA erratum */
155 .trans_mode = DSPI_XSPI_MODE,
156 .max_clock_factor = 8,
157 .fifo_size = 16,
158 },
159 [LS1028A] = {
160 .trans_mode = DSPI_XSPI_MODE,
161 .max_clock_factor = 8,
162 .fifo_size = 4,
163 },
164 [LS1043A] = {
165 /* Has A-011218 DMA erratum */
166 .trans_mode = DSPI_XSPI_MODE,
167 .max_clock_factor = 8,
168 .fifo_size = 16,
169 },
170 [LS1046A] = {
171 /* Has A-011218 DMA erratum */
172 .trans_mode = DSPI_XSPI_MODE,
173 .max_clock_factor = 8,
174 .fifo_size = 16,
175 },
176 [LS2080A] = {
177 .trans_mode = DSPI_XSPI_MODE,
178 .max_clock_factor = 8,
179 .fifo_size = 4,
180 },
181 [LS2085A] = {
182 .trans_mode = DSPI_XSPI_MODE,
183 .max_clock_factor = 8,
184 .fifo_size = 4,
185 },
186 [LX2160A] = {
187 .trans_mode = DSPI_XSPI_MODE,
188 .max_clock_factor = 8,
189 .fifo_size = 4,
190 },
191 [MCF5441X] = {
192 .trans_mode = DSPI_EOQ_MODE,
193 .max_clock_factor = 8,
194 .fifo_size = 16,
195 },
196};
197
198struct fsl_dspi_dma {
199 u32 *tx_dma_buf;
200 struct dma_chan *chan_tx;
201 dma_addr_t tx_dma_phys;
202 struct completion cmd_tx_complete;
203 struct dma_async_tx_descriptor *tx_desc;
204
205 u32 *rx_dma_buf;
206 struct dma_chan *chan_rx;
207 dma_addr_t rx_dma_phys;
208 struct completion cmd_rx_complete;
209 struct dma_async_tx_descriptor *rx_desc;
210};
211
212struct fsl_dspi {
213 struct spi_controller *ctlr;
214 struct platform_device *pdev;
215
216 struct regmap *regmap;
217 struct regmap *regmap_pushr;
218 int irq;
219 struct clk *clk;
220
221 struct spi_transfer *cur_transfer;
222 struct spi_message *cur_msg;
223 struct chip_data *cur_chip;
224 size_t progress;
225 size_t len;
226 const void *tx;
227 void *rx;
228 u16 tx_cmd;
229 const struct fsl_dspi_devtype_data *devtype_data;
230
231 struct completion xfer_done;
232
233 struct fsl_dspi_dma *dma;
234
235 int oper_word_size;
236 int oper_bits_per_word;
237
238 int words_in_flight;
239
240 /*
241 * Offsets for CMD and TXDATA within SPI_PUSHR when accessed
242 * individually (in XSPI mode)
243 */
244 int pushr_cmd;
245 int pushr_tx;
246
247 void (*host_to_dev)(struct fsl_dspi *dspi, u32 *txdata);
248 void (*dev_to_host)(struct fsl_dspi *dspi, u32 rxdata);
249};
250
251static void dspi_native_host_to_dev(struct fsl_dspi *dspi, u32 *txdata)
252{
253 switch (dspi->oper_word_size) {
254 case 1:
255 *txdata = *(u8 *)dspi->tx;
256 break;
257 case 2:
258 *txdata = *(u16 *)dspi->tx;
259 break;
260 case 4:
261 *txdata = *(u32 *)dspi->tx;
262 break;
263 }
264 dspi->tx += dspi->oper_word_size;
265}
266
267static void dspi_native_dev_to_host(struct fsl_dspi *dspi, u32 rxdata)
268{
269 switch (dspi->oper_word_size) {
270 case 1:
271 *(u8 *)dspi->rx = rxdata;
272 break;
273 case 2:
274 *(u16 *)dspi->rx = rxdata;
275 break;
276 case 4:
277 *(u32 *)dspi->rx = rxdata;
278 break;
279 }
280 dspi->rx += dspi->oper_word_size;
281}
282
283static void dspi_8on32_host_to_dev(struct fsl_dspi *dspi, u32 *txdata)
284{
285 *txdata = cpu_to_be32(*(u32 *)dspi->tx);
286 dspi->tx += sizeof(u32);
287}
288
289static void dspi_8on32_dev_to_host(struct fsl_dspi *dspi, u32 rxdata)
290{
291 *(u32 *)dspi->rx = be32_to_cpu(rxdata);
292 dspi->rx += sizeof(u32);
293}
294
295static void dspi_8on16_host_to_dev(struct fsl_dspi *dspi, u32 *txdata)
296{
297 *txdata = cpu_to_be16(*(u16 *)dspi->tx);
298 dspi->tx += sizeof(u16);
299}
300
301static void dspi_8on16_dev_to_host(struct fsl_dspi *dspi, u32 rxdata)
302{
303 *(u16 *)dspi->rx = be16_to_cpu(rxdata);
304 dspi->rx += sizeof(u16);
305}
306
307static void dspi_16on32_host_to_dev(struct fsl_dspi *dspi, u32 *txdata)
308{
309 u16 hi = *(u16 *)dspi->tx;
310 u16 lo = *(u16 *)(dspi->tx + 2);
311
312 *txdata = (u32)hi << 16 | lo;
313 dspi->tx += sizeof(u32);
314}
315
316static void dspi_16on32_dev_to_host(struct fsl_dspi *dspi, u32 rxdata)
317{
318 u16 hi = rxdata & 0xffff;
319 u16 lo = rxdata >> 16;
320
321 *(u16 *)dspi->rx = lo;
322 *(u16 *)(dspi->rx + 2) = hi;
323 dspi->rx += sizeof(u32);
324}
325
326/*
327 * Pop one word from the TX buffer for pushing into the
328 * PUSHR register (TX FIFO)
329 */
330static u32 dspi_pop_tx(struct fsl_dspi *dspi)
331{
332 u32 txdata = 0;
333
334 if (dspi->tx)
335 dspi->host_to_dev(dspi, &txdata);
336 dspi->len -= dspi->oper_word_size;
337 return txdata;
338}
339
340/* Prepare one TX FIFO entry (txdata plus cmd) */
341static u32 dspi_pop_tx_pushr(struct fsl_dspi *dspi)
342{
343 u16 cmd = dspi->tx_cmd, data = dspi_pop_tx(dspi);
344
345 if (spi_controller_is_slave(dspi->ctlr))
346 return data;
347
348 if (dspi->len > 0)
349 cmd |= SPI_PUSHR_CMD_CONT;
350 return cmd << 16 | data;
351}
352
353/* Push one word to the RX buffer from the POPR register (RX FIFO) */
354static void dspi_push_rx(struct fsl_dspi *dspi, u32 rxdata)
355{
356 if (!dspi->rx)
357 return;
358 dspi->dev_to_host(dspi, rxdata);
359}
360
361static void dspi_tx_dma_callback(void *arg)
362{
363 struct fsl_dspi *dspi = arg;
364 struct fsl_dspi_dma *dma = dspi->dma;
365
366 complete(&dma->cmd_tx_complete);
367}
368
369static void dspi_rx_dma_callback(void *arg)
370{
371 struct fsl_dspi *dspi = arg;
372 struct fsl_dspi_dma *dma = dspi->dma;
373 int i;
374
375 if (dspi->rx) {
376 for (i = 0; i < dspi->words_in_flight; i++)
377 dspi_push_rx(dspi, dspi->dma->rx_dma_buf[i]);
378 }
379
380 complete(&dma->cmd_rx_complete);
381}
382
383static int dspi_next_xfer_dma_submit(struct fsl_dspi *dspi)
384{
385 struct device *dev = &dspi->pdev->dev;
386 struct fsl_dspi_dma *dma = dspi->dma;
387 int time_left;
388 int i;
389
390 for (i = 0; i < dspi->words_in_flight; i++)
391 dspi->dma->tx_dma_buf[i] = dspi_pop_tx_pushr(dspi);
392
393 dma->tx_desc = dmaengine_prep_slave_single(dma->chan_tx,
394 dma->tx_dma_phys,
395 dspi->words_in_flight *
396 DMA_SLAVE_BUSWIDTH_4_BYTES,
397 DMA_MEM_TO_DEV,
398 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
399 if (!dma->tx_desc) {
400 dev_err(dev, "Not able to get desc for DMA xfer\n");
401 return -EIO;
402 }
403
404 dma->tx_desc->callback = dspi_tx_dma_callback;
405 dma->tx_desc->callback_param = dspi;
406 if (dma_submit_error(dmaengine_submit(dma->tx_desc))) {
407 dev_err(dev, "DMA submit failed\n");
408 return -EINVAL;
409 }
410
411 dma->rx_desc = dmaengine_prep_slave_single(dma->chan_rx,
412 dma->rx_dma_phys,
413 dspi->words_in_flight *
414 DMA_SLAVE_BUSWIDTH_4_BYTES,
415 DMA_DEV_TO_MEM,
416 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
417 if (!dma->rx_desc) {
418 dev_err(dev, "Not able to get desc for DMA xfer\n");
419 return -EIO;
420 }
421
422 dma->rx_desc->callback = dspi_rx_dma_callback;
423 dma->rx_desc->callback_param = dspi;
424 if (dma_submit_error(dmaengine_submit(dma->rx_desc))) {
425 dev_err(dev, "DMA submit failed\n");
426 return -EINVAL;
427 }
428
429 reinit_completion(&dspi->dma->cmd_rx_complete);
430 reinit_completion(&dspi->dma->cmd_tx_complete);
431
432 dma_async_issue_pending(dma->chan_rx);
433 dma_async_issue_pending(dma->chan_tx);
434
435 if (spi_controller_is_slave(dspi->ctlr)) {
436 wait_for_completion_interruptible(&dspi->dma->cmd_rx_complete);
437 return 0;
438 }
439
440 time_left = wait_for_completion_timeout(&dspi->dma->cmd_tx_complete,
441 DMA_COMPLETION_TIMEOUT);
442 if (time_left == 0) {
443 dev_err(dev, "DMA tx timeout\n");
444 dmaengine_terminate_all(dma->chan_tx);
445 dmaengine_terminate_all(dma->chan_rx);
446 return -ETIMEDOUT;
447 }
448
449 time_left = wait_for_completion_timeout(&dspi->dma->cmd_rx_complete,
450 DMA_COMPLETION_TIMEOUT);
451 if (time_left == 0) {
452 dev_err(dev, "DMA rx timeout\n");
453 dmaengine_terminate_all(dma->chan_tx);
454 dmaengine_terminate_all(dma->chan_rx);
455 return -ETIMEDOUT;
456 }
457
458 return 0;
459}
460
461static void dspi_setup_accel(struct fsl_dspi *dspi);
462
463static int dspi_dma_xfer(struct fsl_dspi *dspi)
464{
465 struct spi_message *message = dspi->cur_msg;
466 struct device *dev = &dspi->pdev->dev;
467 int ret = 0;
468
469 /*
470 * dspi->len gets decremented by dspi_pop_tx_pushr in
471 * dspi_next_xfer_dma_submit
472 */
473 while (dspi->len) {
474 /* Figure out operational bits-per-word for this chunk */
475 dspi_setup_accel(dspi);
476
477 dspi->words_in_flight = dspi->len / dspi->oper_word_size;
478 if (dspi->words_in_flight > dspi->devtype_data->fifo_size)
479 dspi->words_in_flight = dspi->devtype_data->fifo_size;
480
481 message->actual_length += dspi->words_in_flight *
482 dspi->oper_word_size;
483
484 ret = dspi_next_xfer_dma_submit(dspi);
485 if (ret) {
486 dev_err(dev, "DMA transfer failed\n");
487 break;
488 }
489 }
490
491 return ret;
492}
493
494static int dspi_request_dma(struct fsl_dspi *dspi, phys_addr_t phy_addr)
495{
496 int dma_bufsize = dspi->devtype_data->fifo_size * 2;
497 struct device *dev = &dspi->pdev->dev;
498 struct dma_slave_config cfg;
499 struct fsl_dspi_dma *dma;
500 int ret;
501
502 dma = devm_kzalloc(dev, sizeof(*dma), GFP_KERNEL);
503 if (!dma)
504 return -ENOMEM;
505
506 dma->chan_rx = dma_request_chan(dev, "rx");
507 if (IS_ERR(dma->chan_rx)) {
508 dev_err(dev, "rx dma channel not available\n");
509 ret = PTR_ERR(dma->chan_rx);
510 return ret;
511 }
512
513 dma->chan_tx = dma_request_chan(dev, "tx");
514 if (IS_ERR(dma->chan_tx)) {
515 dev_err(dev, "tx dma channel not available\n");
516 ret = PTR_ERR(dma->chan_tx);
517 goto err_tx_channel;
518 }
519
520 dma->tx_dma_buf = dma_alloc_coherent(dma->chan_tx->device->dev,
521 dma_bufsize, &dma->tx_dma_phys,
522 GFP_KERNEL);
523 if (!dma->tx_dma_buf) {
524 ret = -ENOMEM;
525 goto err_tx_dma_buf;
526 }
527
528 dma->rx_dma_buf = dma_alloc_coherent(dma->chan_rx->device->dev,
529 dma_bufsize, &dma->rx_dma_phys,
530 GFP_KERNEL);
531 if (!dma->rx_dma_buf) {
532 ret = -ENOMEM;
533 goto err_rx_dma_buf;
534 }
535
536 cfg.src_addr = phy_addr + SPI_POPR;
537 cfg.dst_addr = phy_addr + SPI_PUSHR;
538 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
539 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
540 cfg.src_maxburst = 1;
541 cfg.dst_maxburst = 1;
542
543 cfg.direction = DMA_DEV_TO_MEM;
544 ret = dmaengine_slave_config(dma->chan_rx, &cfg);
545 if (ret) {
546 dev_err(dev, "can't configure rx dma channel\n");
547 ret = -EINVAL;
548 goto err_slave_config;
549 }
550
551 cfg.direction = DMA_MEM_TO_DEV;
552 ret = dmaengine_slave_config(dma->chan_tx, &cfg);
553 if (ret) {
554 dev_err(dev, "can't configure tx dma channel\n");
555 ret = -EINVAL;
556 goto err_slave_config;
557 }
558
559 dspi->dma = dma;
560 init_completion(&dma->cmd_tx_complete);
561 init_completion(&dma->cmd_rx_complete);
562
563 return 0;
564
565err_slave_config:
566 dma_free_coherent(dma->chan_rx->device->dev,
567 dma_bufsize, dma->rx_dma_buf, dma->rx_dma_phys);
568err_rx_dma_buf:
569 dma_free_coherent(dma->chan_tx->device->dev,
570 dma_bufsize, dma->tx_dma_buf, dma->tx_dma_phys);
571err_tx_dma_buf:
572 dma_release_channel(dma->chan_tx);
573err_tx_channel:
574 dma_release_channel(dma->chan_rx);
575
576 devm_kfree(dev, dma);
577 dspi->dma = NULL;
578
579 return ret;
580}
581
582static void dspi_release_dma(struct fsl_dspi *dspi)
583{
584 int dma_bufsize = dspi->devtype_data->fifo_size * 2;
585 struct fsl_dspi_dma *dma = dspi->dma;
586
587 if (!dma)
588 return;
589
590 if (dma->chan_tx) {
591 dma_free_coherent(dma->chan_tx->device->dev, dma_bufsize,
592 dma->tx_dma_buf, dma->tx_dma_phys);
593 dma_release_channel(dma->chan_tx);
594 }
595
596 if (dma->chan_rx) {
597 dma_free_coherent(dma->chan_rx->device->dev, dma_bufsize,
598 dma->rx_dma_buf, dma->rx_dma_phys);
599 dma_release_channel(dma->chan_rx);
600 }
601}
602
603static void hz_to_spi_baud(char *pbr, char *br, int speed_hz,
604 unsigned long clkrate)
605{
606 /* Valid baud rate pre-scaler values */
607 int pbr_tbl[4] = {2, 3, 5, 7};
608 int brs[16] = { 2, 4, 6, 8,
609 16, 32, 64, 128,
610 256, 512, 1024, 2048,
611 4096, 8192, 16384, 32768 };
612 int scale_needed, scale, minscale = INT_MAX;
613 int i, j;
614
615 scale_needed = clkrate / speed_hz;
616 if (clkrate % speed_hz)
617 scale_needed++;
618
619 for (i = 0; i < ARRAY_SIZE(brs); i++)
620 for (j = 0; j < ARRAY_SIZE(pbr_tbl); j++) {
621 scale = brs[i] * pbr_tbl[j];
622 if (scale >= scale_needed) {
623 if (scale < minscale) {
624 minscale = scale;
625 *br = i;
626 *pbr = j;
627 }
628 break;
629 }
630 }
631
632 if (minscale == INT_MAX) {
633 pr_warn("Can not find valid baud rate,speed_hz is %d,clkrate is %ld, we use the max prescaler value.\n",
634 speed_hz, clkrate);
635 *pbr = ARRAY_SIZE(pbr_tbl) - 1;
636 *br = ARRAY_SIZE(brs) - 1;
637 }
638}
639
640static void ns_delay_scale(char *psc, char *sc, int delay_ns,
641 unsigned long clkrate)
642{
643 int scale_needed, scale, minscale = INT_MAX;
644 int pscale_tbl[4] = {1, 3, 5, 7};
645 u32 remainder;
646 int i, j;
647
648 scale_needed = div_u64_rem((u64)delay_ns * clkrate, NSEC_PER_SEC,
649 &remainder);
650 if (remainder)
651 scale_needed++;
652
653 for (i = 0; i < ARRAY_SIZE(pscale_tbl); i++)
654 for (j = 0; j <= SPI_CTAR_SCALE_BITS; j++) {
655 scale = pscale_tbl[i] * (2 << j);
656 if (scale >= scale_needed) {
657 if (scale < minscale) {
658 minscale = scale;
659 *psc = i;
660 *sc = j;
661 }
662 break;
663 }
664 }
665
666 if (minscale == INT_MAX) {
667 pr_warn("Cannot find correct scale values for %dns delay at clkrate %ld, using max prescaler value",
668 delay_ns, clkrate);
669 *psc = ARRAY_SIZE(pscale_tbl) - 1;
670 *sc = SPI_CTAR_SCALE_BITS;
671 }
672}
673
674static void dspi_pushr_write(struct fsl_dspi *dspi)
675{
676 regmap_write(dspi->regmap, SPI_PUSHR, dspi_pop_tx_pushr(dspi));
677}
678
679static void dspi_pushr_cmd_write(struct fsl_dspi *dspi, u16 cmd)
680{
681 /*
682 * The only time when the PCS doesn't need continuation after this word
683 * is when it's last. We need to look ahead, because we actually call
684 * dspi_pop_tx (the function that decrements dspi->len) _after_
685 * dspi_pushr_cmd_write with XSPI mode. As for how much in advance? One
686 * word is enough. If there's more to transmit than that,
687 * dspi_xspi_write will know to split the FIFO writes in 2, and
688 * generate a new PUSHR command with the final word that will have PCS
689 * deasserted (not continued) here.
690 */
691 if (dspi->len > dspi->oper_word_size)
692 cmd |= SPI_PUSHR_CMD_CONT;
693 regmap_write(dspi->regmap_pushr, dspi->pushr_cmd, cmd);
694}
695
696static void dspi_pushr_txdata_write(struct fsl_dspi *dspi, u16 txdata)
697{
698 regmap_write(dspi->regmap_pushr, dspi->pushr_tx, txdata);
699}
700
701static void dspi_xspi_fifo_write(struct fsl_dspi *dspi, int num_words)
702{
703 int num_bytes = num_words * dspi->oper_word_size;
704 u16 tx_cmd = dspi->tx_cmd;
705
706 /*
707 * If the PCS needs to de-assert (i.e. we're at the end of the buffer
708 * and cs_change does not want the PCS to stay on), then we need a new
709 * PUSHR command, since this one (for the body of the buffer)
710 * necessarily has the CONT bit set.
711 * So send one word less during this go, to force a split and a command
712 * with a single word next time, when CONT will be unset.
713 */
714 if (!(dspi->tx_cmd & SPI_PUSHR_CMD_CONT) && num_bytes == dspi->len)
715 tx_cmd |= SPI_PUSHR_CMD_EOQ;
716
717 /* Update CTARE */
718 regmap_write(dspi->regmap, SPI_CTARE(0),
719 SPI_FRAME_EBITS(dspi->oper_bits_per_word) |
720 SPI_CTARE_DTCP(num_words));
721
722 /*
723 * Write the CMD FIFO entry first, and then the two
724 * corresponding TX FIFO entries (or one...).
725 */
726 dspi_pushr_cmd_write(dspi, tx_cmd);
727
728 /* Fill TX FIFO with as many transfers as possible */
729 while (num_words--) {
730 u32 data = dspi_pop_tx(dspi);
731
732 dspi_pushr_txdata_write(dspi, data & 0xFFFF);
733 if (dspi->oper_bits_per_word > 16)
734 dspi_pushr_txdata_write(dspi, data >> 16);
735 }
736}
737
738static void dspi_eoq_fifo_write(struct fsl_dspi *dspi, int num_words)
739{
740 u16 xfer_cmd = dspi->tx_cmd;
741
742 /* Fill TX FIFO with as many transfers as possible */
743 while (num_words--) {
744 dspi->tx_cmd = xfer_cmd;
745 /* Request EOQF for last transfer in FIFO */
746 if (num_words == 0)
747 dspi->tx_cmd |= SPI_PUSHR_CMD_EOQ;
748 /* Write combined TX FIFO and CMD FIFO entry */
749 dspi_pushr_write(dspi);
750 }
751}
752
753static u32 dspi_popr_read(struct fsl_dspi *dspi)
754{
755 u32 rxdata = 0;
756
757 regmap_read(dspi->regmap, SPI_POPR, &rxdata);
758 return rxdata;
759}
760
761static void dspi_fifo_read(struct fsl_dspi *dspi)
762{
763 int num_fifo_entries = dspi->words_in_flight;
764
765 /* Read one FIFO entry and push to rx buffer */
766 while (num_fifo_entries--)
767 dspi_push_rx(dspi, dspi_popr_read(dspi));
768}
769
770static void dspi_setup_accel(struct fsl_dspi *dspi)
771{
772 struct spi_transfer *xfer = dspi->cur_transfer;
773 bool odd = !!(dspi->len & 1);
774
775 /* No accel for frames not multiple of 8 bits at the moment */
776 if (xfer->bits_per_word % 8)
777 goto no_accel;
778
779 if (!odd && dspi->len <= dspi->devtype_data->fifo_size * 2) {
780 dspi->oper_bits_per_word = 16;
781 } else if (odd && dspi->len <= dspi->devtype_data->fifo_size) {
782 dspi->oper_bits_per_word = 8;
783 } else {
784 /* Start off with maximum supported by hardware */
785 if (dspi->devtype_data->trans_mode == DSPI_XSPI_MODE)
786 dspi->oper_bits_per_word = 32;
787 else
788 dspi->oper_bits_per_word = 16;
789
790 /*
791 * And go down only if the buffer can't be sent with
792 * words this big
793 */
794 do {
795 if (dspi->len >= DIV_ROUND_UP(dspi->oper_bits_per_word, 8))
796 break;
797
798 dspi->oper_bits_per_word /= 2;
799 } while (dspi->oper_bits_per_word > 8);
800 }
801
802 if (xfer->bits_per_word == 8 && dspi->oper_bits_per_word == 32) {
803 dspi->dev_to_host = dspi_8on32_dev_to_host;
804 dspi->host_to_dev = dspi_8on32_host_to_dev;
805 } else if (xfer->bits_per_word == 8 && dspi->oper_bits_per_word == 16) {
806 dspi->dev_to_host = dspi_8on16_dev_to_host;
807 dspi->host_to_dev = dspi_8on16_host_to_dev;
808 } else if (xfer->bits_per_word == 16 && dspi->oper_bits_per_word == 32) {
809 dspi->dev_to_host = dspi_16on32_dev_to_host;
810 dspi->host_to_dev = dspi_16on32_host_to_dev;
811 } else {
812no_accel:
813 dspi->dev_to_host = dspi_native_dev_to_host;
814 dspi->host_to_dev = dspi_native_host_to_dev;
815 dspi->oper_bits_per_word = xfer->bits_per_word;
816 }
817
818 dspi->oper_word_size = DIV_ROUND_UP(dspi->oper_bits_per_word, 8);
819
820 /*
821 * Update CTAR here (code is common for EOQ, XSPI and DMA modes).
822 * We will update CTARE in the portion specific to XSPI, when we
823 * also know the preload value (DTCP).
824 */
825 regmap_write(dspi->regmap, SPI_CTAR(0),
826 dspi->cur_chip->ctar_val |
827 SPI_FRAME_BITS(dspi->oper_bits_per_word));
828}
829
830static void dspi_fifo_write(struct fsl_dspi *dspi)
831{
832 int num_fifo_entries = dspi->devtype_data->fifo_size;
833 struct spi_transfer *xfer = dspi->cur_transfer;
834 struct spi_message *msg = dspi->cur_msg;
835 int num_words, num_bytes;
836
837 dspi_setup_accel(dspi);
838
839 /* In XSPI mode each 32-bit word occupies 2 TX FIFO entries */
840 if (dspi->oper_word_size == 4)
841 num_fifo_entries /= 2;
842
843 /*
844 * Integer division intentionally trims off odd (or non-multiple of 4)
845 * numbers of bytes at the end of the buffer, which will be sent next
846 * time using a smaller oper_word_size.
847 */
848 num_words = dspi->len / dspi->oper_word_size;
849 if (num_words > num_fifo_entries)
850 num_words = num_fifo_entries;
851
852 /* Update total number of bytes that were transferred */
853 num_bytes = num_words * dspi->oper_word_size;
854 msg->actual_length += num_bytes;
855 dspi->progress += num_bytes / DIV_ROUND_UP(xfer->bits_per_word, 8);
856
857 /*
858 * Update shared variable for use in the next interrupt (both in
859 * dspi_fifo_read and in dspi_fifo_write).
860 */
861 dspi->words_in_flight = num_words;
862
863 spi_take_timestamp_pre(dspi->ctlr, xfer, dspi->progress, !dspi->irq);
864
865 if (dspi->devtype_data->trans_mode == DSPI_EOQ_MODE)
866 dspi_eoq_fifo_write(dspi, num_words);
867 else
868 dspi_xspi_fifo_write(dspi, num_words);
869 /*
870 * Everything after this point is in a potential race with the next
871 * interrupt, so we must never use dspi->words_in_flight again since it
872 * might already be modified by the next dspi_fifo_write.
873 */
874
875 spi_take_timestamp_post(dspi->ctlr, dspi->cur_transfer,
876 dspi->progress, !dspi->irq);
877}
878
879static int dspi_rxtx(struct fsl_dspi *dspi)
880{
881 dspi_fifo_read(dspi);
882
883 if (!dspi->len)
884 /* Success! */
885 return 0;
886
887 dspi_fifo_write(dspi);
888
889 return -EINPROGRESS;
890}
891
892static int dspi_poll(struct fsl_dspi *dspi)
893{
894 int tries = 1000;
895 u32 spi_sr;
896
897 do {
898 regmap_read(dspi->regmap, SPI_SR, &spi_sr);
899 regmap_write(dspi->regmap, SPI_SR, spi_sr);
900
901 if (spi_sr & (SPI_SR_EOQF | SPI_SR_CMDTCF))
902 break;
903 } while (--tries);
904
905 if (!tries)
906 return -ETIMEDOUT;
907
908 return dspi_rxtx(dspi);
909}
910
911static irqreturn_t dspi_interrupt(int irq, void *dev_id)
912{
913 struct fsl_dspi *dspi = (struct fsl_dspi *)dev_id;
914 u32 spi_sr;
915
916 regmap_read(dspi->regmap, SPI_SR, &spi_sr);
917 regmap_write(dspi->regmap, SPI_SR, spi_sr);
918
919 if (!(spi_sr & (SPI_SR_EOQF | SPI_SR_CMDTCF)))
920 return IRQ_NONE;
921
922 if (dspi_rxtx(dspi) == 0)
923 complete(&dspi->xfer_done);
924
925 return IRQ_HANDLED;
926}
927
928static int dspi_transfer_one_message(struct spi_controller *ctlr,
929 struct spi_message *message)
930{
931 struct fsl_dspi *dspi = spi_controller_get_devdata(ctlr);
932 struct spi_device *spi = message->spi;
933 struct spi_transfer *transfer;
934 int status = 0;
935
936 message->actual_length = 0;
937
938 list_for_each_entry(transfer, &message->transfers, transfer_list) {
939 dspi->cur_transfer = transfer;
940 dspi->cur_msg = message;
941 dspi->cur_chip = spi_get_ctldata(spi);
942 /* Prepare command word for CMD FIFO */
943 dspi->tx_cmd = SPI_PUSHR_CMD_CTAS(0) |
944 SPI_PUSHR_CMD_PCS(spi->chip_select);
945 if (list_is_last(&dspi->cur_transfer->transfer_list,
946 &dspi->cur_msg->transfers)) {
947 /* Leave PCS activated after last transfer when
948 * cs_change is set.
949 */
950 if (transfer->cs_change)
951 dspi->tx_cmd |= SPI_PUSHR_CMD_CONT;
952 } else {
953 /* Keep PCS active between transfers in same message
954 * when cs_change is not set, and de-activate PCS
955 * between transfers in the same message when
956 * cs_change is set.
957 */
958 if (!transfer->cs_change)
959 dspi->tx_cmd |= SPI_PUSHR_CMD_CONT;
960 }
961
962 dspi->tx = transfer->tx_buf;
963 dspi->rx = transfer->rx_buf;
964 dspi->len = transfer->len;
965 dspi->progress = 0;
966
967 regmap_update_bits(dspi->regmap, SPI_MCR,
968 SPI_MCR_CLR_TXF | SPI_MCR_CLR_RXF,
969 SPI_MCR_CLR_TXF | SPI_MCR_CLR_RXF);
970
971 spi_take_timestamp_pre(dspi->ctlr, dspi->cur_transfer,
972 dspi->progress, !dspi->irq);
973
974 if (dspi->devtype_data->trans_mode == DSPI_DMA_MODE) {
975 status = dspi_dma_xfer(dspi);
976 } else {
977 dspi_fifo_write(dspi);
978
979 if (dspi->irq) {
980 wait_for_completion(&dspi->xfer_done);
981 reinit_completion(&dspi->xfer_done);
982 } else {
983 do {
984 status = dspi_poll(dspi);
985 } while (status == -EINPROGRESS);
986 }
987 }
988 if (status)
989 break;
990
991 spi_transfer_delay_exec(transfer);
992 }
993
994 message->status = status;
995 spi_finalize_current_message(ctlr);
996
997 return status;
998}
999
1000static int dspi_setup(struct spi_device *spi)
1001{
1002 struct fsl_dspi *dspi = spi_controller_get_devdata(spi->controller);
1003 unsigned char br = 0, pbr = 0, pcssck = 0, cssck = 0;
1004 u32 cs_sck_delay = 0, sck_cs_delay = 0;
1005 struct fsl_dspi_platform_data *pdata;
1006 unsigned char pasc = 0, asc = 0;
1007 struct chip_data *chip;
1008 unsigned long clkrate;
1009
1010 /* Only alloc on first setup */
1011 chip = spi_get_ctldata(spi);
1012 if (chip == NULL) {
1013 chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL);
1014 if (!chip)
1015 return -ENOMEM;
1016 }
1017
1018 pdata = dev_get_platdata(&dspi->pdev->dev);
1019
1020 if (!pdata) {
1021 of_property_read_u32(spi->dev.of_node, "fsl,spi-cs-sck-delay",
1022 &cs_sck_delay);
1023
1024 of_property_read_u32(spi->dev.of_node, "fsl,spi-sck-cs-delay",
1025 &sck_cs_delay);
1026 } else {
1027 cs_sck_delay = pdata->cs_sck_delay;
1028 sck_cs_delay = pdata->sck_cs_delay;
1029 }
1030
1031 clkrate = clk_get_rate(dspi->clk);
1032 hz_to_spi_baud(&pbr, &br, spi->max_speed_hz, clkrate);
1033
1034 /* Set PCS to SCK delay scale values */
1035 ns_delay_scale(&pcssck, &cssck, cs_sck_delay, clkrate);
1036
1037 /* Set After SCK delay scale values */
1038 ns_delay_scale(&pasc, &asc, sck_cs_delay, clkrate);
1039
1040 chip->ctar_val = 0;
1041 if (spi->mode & SPI_CPOL)
1042 chip->ctar_val |= SPI_CTAR_CPOL;
1043 if (spi->mode & SPI_CPHA)
1044 chip->ctar_val |= SPI_CTAR_CPHA;
1045
1046 if (!spi_controller_is_slave(dspi->ctlr)) {
1047 chip->ctar_val |= SPI_CTAR_PCSSCK(pcssck) |
1048 SPI_CTAR_CSSCK(cssck) |
1049 SPI_CTAR_PASC(pasc) |
1050 SPI_CTAR_ASC(asc) |
1051 SPI_CTAR_PBR(pbr) |
1052 SPI_CTAR_BR(br);
1053
1054 if (spi->mode & SPI_LSB_FIRST)
1055 chip->ctar_val |= SPI_CTAR_LSBFE;
1056 }
1057
1058 spi_set_ctldata(spi, chip);
1059
1060 return 0;
1061}
1062
1063static void dspi_cleanup(struct spi_device *spi)
1064{
1065 struct chip_data *chip = spi_get_ctldata((struct spi_device *)spi);
1066
1067 dev_dbg(&spi->dev, "spi_device %u.%u cleanup\n",
1068 spi->controller->bus_num, spi->chip_select);
1069
1070 kfree(chip);
1071}
1072
1073static const struct of_device_id fsl_dspi_dt_ids[] = {
1074 {
1075 .compatible = "fsl,vf610-dspi",
1076 .data = &devtype_data[VF610],
1077 }, {
1078 .compatible = "fsl,ls1021a-v1.0-dspi",
1079 .data = &devtype_data[LS1021A],
1080 }, {
1081 .compatible = "fsl,ls1012a-dspi",
1082 .data = &devtype_data[LS1012A],
1083 }, {
1084 .compatible = "fsl,ls1028a-dspi",
1085 .data = &devtype_data[LS1028A],
1086 }, {
1087 .compatible = "fsl,ls1043a-dspi",
1088 .data = &devtype_data[LS1043A],
1089 }, {
1090 .compatible = "fsl,ls1046a-dspi",
1091 .data = &devtype_data[LS1046A],
1092 }, {
1093 .compatible = "fsl,ls2080a-dspi",
1094 .data = &devtype_data[LS2080A],
1095 }, {
1096 .compatible = "fsl,ls2085a-dspi",
1097 .data = &devtype_data[LS2085A],
1098 }, {
1099 .compatible = "fsl,lx2160a-dspi",
1100 .data = &devtype_data[LX2160A],
1101 },
1102 { /* sentinel */ }
1103};
1104MODULE_DEVICE_TABLE(of, fsl_dspi_dt_ids);
1105
1106#ifdef CONFIG_PM_SLEEP
1107static int dspi_suspend(struct device *dev)
1108{
1109 struct spi_controller *ctlr = dev_get_drvdata(dev);
1110 struct fsl_dspi *dspi = spi_controller_get_devdata(ctlr);
1111
1112 if (dspi->irq)
1113 disable_irq(dspi->irq);
1114 spi_controller_suspend(ctlr);
1115 clk_disable_unprepare(dspi->clk);
1116
1117 pinctrl_pm_select_sleep_state(dev);
1118
1119 return 0;
1120}
1121
1122static int dspi_resume(struct device *dev)
1123{
1124 struct spi_controller *ctlr = dev_get_drvdata(dev);
1125 struct fsl_dspi *dspi = spi_controller_get_devdata(ctlr);
1126 int ret;
1127
1128 pinctrl_pm_select_default_state(dev);
1129
1130 ret = clk_prepare_enable(dspi->clk);
1131 if (ret)
1132 return ret;
1133 spi_controller_resume(ctlr);
1134 if (dspi->irq)
1135 enable_irq(dspi->irq);
1136
1137 return 0;
1138}
1139#endif /* CONFIG_PM_SLEEP */
1140
1141static SIMPLE_DEV_PM_OPS(dspi_pm, dspi_suspend, dspi_resume);
1142
1143static const struct regmap_range dspi_volatile_ranges[] = {
1144 regmap_reg_range(SPI_MCR, SPI_TCR),
1145 regmap_reg_range(SPI_SR, SPI_SR),
1146 regmap_reg_range(SPI_PUSHR, SPI_RXFR3),
1147};
1148
1149static const struct regmap_access_table dspi_volatile_table = {
1150 .yes_ranges = dspi_volatile_ranges,
1151 .n_yes_ranges = ARRAY_SIZE(dspi_volatile_ranges),
1152};
1153
1154static const struct regmap_config dspi_regmap_config = {
1155 .reg_bits = 32,
1156 .val_bits = 32,
1157 .reg_stride = 4,
1158 .max_register = 0x88,
1159 .volatile_table = &dspi_volatile_table,
1160};
1161
1162static const struct regmap_range dspi_xspi_volatile_ranges[] = {
1163 regmap_reg_range(SPI_MCR, SPI_TCR),
1164 regmap_reg_range(SPI_SR, SPI_SR),
1165 regmap_reg_range(SPI_PUSHR, SPI_RXFR3),
1166 regmap_reg_range(SPI_SREX, SPI_SREX),
1167};
1168
1169static const struct regmap_access_table dspi_xspi_volatile_table = {
1170 .yes_ranges = dspi_xspi_volatile_ranges,
1171 .n_yes_ranges = ARRAY_SIZE(dspi_xspi_volatile_ranges),
1172};
1173
1174static const struct regmap_config dspi_xspi_regmap_config[] = {
1175 {
1176 .reg_bits = 32,
1177 .val_bits = 32,
1178 .reg_stride = 4,
1179 .max_register = 0x13c,
1180 .volatile_table = &dspi_xspi_volatile_table,
1181 },
1182 {
1183 .name = "pushr",
1184 .reg_bits = 16,
1185 .val_bits = 16,
1186 .reg_stride = 2,
1187 .max_register = 0x2,
1188 },
1189};
1190
1191static int dspi_init(struct fsl_dspi *dspi)
1192{
1193 unsigned int mcr;
1194
1195 /* Set idle states for all chip select signals to high */
1196 mcr = SPI_MCR_PCSIS(GENMASK(dspi->ctlr->num_chipselect - 1, 0));
1197
1198 if (dspi->devtype_data->trans_mode == DSPI_XSPI_MODE)
1199 mcr |= SPI_MCR_XSPI;
1200 if (!spi_controller_is_slave(dspi->ctlr))
1201 mcr |= SPI_MCR_MASTER;
1202
1203 regmap_write(dspi->regmap, SPI_MCR, mcr);
1204 regmap_write(dspi->regmap, SPI_SR, SPI_SR_CLEAR);
1205
1206 switch (dspi->devtype_data->trans_mode) {
1207 case DSPI_EOQ_MODE:
1208 regmap_write(dspi->regmap, SPI_RSER, SPI_RSER_EOQFE);
1209 break;
1210 case DSPI_XSPI_MODE:
1211 regmap_write(dspi->regmap, SPI_RSER, SPI_RSER_CMDTCFE);
1212 break;
1213 case DSPI_DMA_MODE:
1214 regmap_write(dspi->regmap, SPI_RSER,
1215 SPI_RSER_TFFFE | SPI_RSER_TFFFD |
1216 SPI_RSER_RFDFE | SPI_RSER_RFDFD);
1217 break;
1218 default:
1219 dev_err(&dspi->pdev->dev, "unsupported trans_mode %u\n",
1220 dspi->devtype_data->trans_mode);
1221 return -EINVAL;
1222 }
1223
1224 return 0;
1225}
1226
1227static int dspi_slave_abort(struct spi_master *master)
1228{
1229 struct fsl_dspi *dspi = spi_master_get_devdata(master);
1230
1231 /*
1232 * Terminate all pending DMA transactions for the SPI working
1233 * in SLAVE mode.
1234 */
1235 if (dspi->devtype_data->trans_mode == DSPI_DMA_MODE) {
1236 dmaengine_terminate_sync(dspi->dma->chan_rx);
1237 dmaengine_terminate_sync(dspi->dma->chan_tx);
1238 }
1239
1240 /* Clear the internal DSPI RX and TX FIFO buffers */
1241 regmap_update_bits(dspi->regmap, SPI_MCR,
1242 SPI_MCR_CLR_TXF | SPI_MCR_CLR_RXF,
1243 SPI_MCR_CLR_TXF | SPI_MCR_CLR_RXF);
1244
1245 return 0;
1246}
1247
1248/*
1249 * EOQ mode will inevitably deassert its PCS signal on last word in a queue
1250 * (hardware limitation), so we need to inform the spi_device that larger
1251 * buffers than the FIFO size are going to have the chip select randomly
1252 * toggling, so it has a chance to adapt its message sizes.
1253 */
1254static size_t dspi_max_message_size(struct spi_device *spi)
1255{
1256 struct fsl_dspi *dspi = spi_controller_get_devdata(spi->controller);
1257
1258 if (dspi->devtype_data->trans_mode == DSPI_EOQ_MODE)
1259 return dspi->devtype_data->fifo_size;
1260
1261 return SIZE_MAX;
1262}
1263
1264static int dspi_probe(struct platform_device *pdev)
1265{
1266 struct device_node *np = pdev->dev.of_node;
1267 const struct regmap_config *regmap_config;
1268 struct fsl_dspi_platform_data *pdata;
1269 struct spi_controller *ctlr;
1270 int ret, cs_num, bus_num = -1;
1271 struct fsl_dspi *dspi;
1272 struct resource *res;
1273 void __iomem *base;
1274 bool big_endian;
1275
1276 dspi = devm_kzalloc(&pdev->dev, sizeof(*dspi), GFP_KERNEL);
1277 if (!dspi)
1278 return -ENOMEM;
1279
1280 ctlr = spi_alloc_master(&pdev->dev, 0);
1281 if (!ctlr)
1282 return -ENOMEM;
1283
1284 spi_controller_set_devdata(ctlr, dspi);
1285 platform_set_drvdata(pdev, dspi);
1286
1287 dspi->pdev = pdev;
1288 dspi->ctlr = ctlr;
1289
1290 ctlr->setup = dspi_setup;
1291 ctlr->transfer_one_message = dspi_transfer_one_message;
1292 ctlr->max_message_size = dspi_max_message_size;
1293 ctlr->dev.of_node = pdev->dev.of_node;
1294
1295 ctlr->cleanup = dspi_cleanup;
1296 ctlr->slave_abort = dspi_slave_abort;
1297 ctlr->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST;
1298
1299 pdata = dev_get_platdata(&pdev->dev);
1300 if (pdata) {
1301 ctlr->num_chipselect = pdata->cs_num;
1302 ctlr->bus_num = pdata->bus_num;
1303
1304 /* Only Coldfire uses platform data */
1305 dspi->devtype_data = &devtype_data[MCF5441X];
1306 big_endian = true;
1307 } else {
1308
1309 ret = of_property_read_u32(np, "spi-num-chipselects", &cs_num);
1310 if (ret < 0) {
1311 dev_err(&pdev->dev, "can't get spi-num-chipselects\n");
1312 goto out_ctlr_put;
1313 }
1314 ctlr->num_chipselect = cs_num;
1315
1316 of_property_read_u32(np, "bus-num", &bus_num);
1317 ctlr->bus_num = bus_num;
1318
1319 if (of_property_read_bool(np, "spi-slave"))
1320 ctlr->slave = true;
1321
1322 dspi->devtype_data = of_device_get_match_data(&pdev->dev);
1323 if (!dspi->devtype_data) {
1324 dev_err(&pdev->dev, "can't get devtype_data\n");
1325 ret = -EFAULT;
1326 goto out_ctlr_put;
1327 }
1328
1329 big_endian = of_device_is_big_endian(np);
1330 }
1331 if (big_endian) {
1332 dspi->pushr_cmd = 0;
1333 dspi->pushr_tx = 2;
1334 } else {
1335 dspi->pushr_cmd = 2;
1336 dspi->pushr_tx = 0;
1337 }
1338
1339 if (dspi->devtype_data->trans_mode == DSPI_XSPI_MODE)
1340 ctlr->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32);
1341 else
1342 ctlr->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 16);
1343
1344 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1345 base = devm_ioremap_resource(&pdev->dev, res);
1346 if (IS_ERR(base)) {
1347 ret = PTR_ERR(base);
1348 goto out_ctlr_put;
1349 }
1350
1351 if (dspi->devtype_data->trans_mode == DSPI_XSPI_MODE)
1352 regmap_config = &dspi_xspi_regmap_config[0];
1353 else
1354 regmap_config = &dspi_regmap_config;
1355 dspi->regmap = devm_regmap_init_mmio(&pdev->dev, base, regmap_config);
1356 if (IS_ERR(dspi->regmap)) {
1357 dev_err(&pdev->dev, "failed to init regmap: %ld\n",
1358 PTR_ERR(dspi->regmap));
1359 ret = PTR_ERR(dspi->regmap);
1360 goto out_ctlr_put;
1361 }
1362
1363 if (dspi->devtype_data->trans_mode == DSPI_XSPI_MODE) {
1364 dspi->regmap_pushr = devm_regmap_init_mmio(
1365 &pdev->dev, base + SPI_PUSHR,
1366 &dspi_xspi_regmap_config[1]);
1367 if (IS_ERR(dspi->regmap_pushr)) {
1368 dev_err(&pdev->dev,
1369 "failed to init pushr regmap: %ld\n",
1370 PTR_ERR(dspi->regmap_pushr));
1371 ret = PTR_ERR(dspi->regmap_pushr);
1372 goto out_ctlr_put;
1373 }
1374 }
1375
1376 dspi->clk = devm_clk_get(&pdev->dev, "dspi");
1377 if (IS_ERR(dspi->clk)) {
1378 ret = PTR_ERR(dspi->clk);
1379 dev_err(&pdev->dev, "unable to get clock\n");
1380 goto out_ctlr_put;
1381 }
1382 ret = clk_prepare_enable(dspi->clk);
1383 if (ret)
1384 goto out_ctlr_put;
1385
1386 ret = dspi_init(dspi);
1387 if (ret)
1388 goto out_clk_put;
1389
1390 dspi->irq = platform_get_irq(pdev, 0);
1391 if (dspi->irq <= 0) {
1392 dev_info(&pdev->dev,
1393 "can't get platform irq, using poll mode\n");
1394 dspi->irq = 0;
1395 goto poll_mode;
1396 }
1397
1398 init_completion(&dspi->xfer_done);
1399
1400 ret = request_threaded_irq(dspi->irq, dspi_interrupt, NULL,
1401 IRQF_SHARED, pdev->name, dspi);
1402 if (ret < 0) {
1403 dev_err(&pdev->dev, "Unable to attach DSPI interrupt\n");
1404 goto out_clk_put;
1405 }
1406
1407poll_mode:
1408
1409 if (dspi->devtype_data->trans_mode == DSPI_DMA_MODE) {
1410 ret = dspi_request_dma(dspi, res->start);
1411 if (ret < 0) {
1412 dev_err(&pdev->dev, "can't get dma channels\n");
1413 goto out_free_irq;
1414 }
1415 }
1416
1417 ctlr->max_speed_hz =
1418 clk_get_rate(dspi->clk) / dspi->devtype_data->max_clock_factor;
1419
1420 if (dspi->devtype_data->trans_mode != DSPI_DMA_MODE)
1421 ctlr->ptp_sts_supported = true;
1422
1423 ret = spi_register_controller(ctlr);
1424 if (ret != 0) {
1425 dev_err(&pdev->dev, "Problem registering DSPI ctlr\n");
1426 goto out_free_irq;
1427 }
1428
1429 return ret;
1430
1431out_free_irq:
1432 if (dspi->irq)
1433 free_irq(dspi->irq, dspi);
1434out_clk_put:
1435 clk_disable_unprepare(dspi->clk);
1436out_ctlr_put:
1437 spi_controller_put(ctlr);
1438
1439 return ret;
1440}
1441
1442static int dspi_remove(struct platform_device *pdev)
1443{
1444 struct fsl_dspi *dspi = platform_get_drvdata(pdev);
1445
1446 /* Disconnect from the SPI framework */
1447 spi_unregister_controller(dspi->ctlr);
1448
1449 /* Disable RX and TX */
1450 regmap_update_bits(dspi->regmap, SPI_MCR,
1451 SPI_MCR_DIS_TXF | SPI_MCR_DIS_RXF,
1452 SPI_MCR_DIS_TXF | SPI_MCR_DIS_RXF);
1453
1454 /* Stop Running */
1455 regmap_update_bits(dspi->regmap, SPI_MCR, SPI_MCR_HALT, SPI_MCR_HALT);
1456
1457 dspi_release_dma(dspi);
1458 if (dspi->irq)
1459 free_irq(dspi->irq, dspi);
1460 clk_disable_unprepare(dspi->clk);
1461
1462 return 0;
1463}
1464
1465static void dspi_shutdown(struct platform_device *pdev)
1466{
1467 dspi_remove(pdev);
1468}
1469
1470static struct platform_driver fsl_dspi_driver = {
1471 .driver.name = DRIVER_NAME,
1472 .driver.of_match_table = fsl_dspi_dt_ids,
1473 .driver.owner = THIS_MODULE,
1474 .driver.pm = &dspi_pm,
1475 .probe = dspi_probe,
1476 .remove = dspi_remove,
1477 .shutdown = dspi_shutdown,
1478};
1479module_platform_driver(fsl_dspi_driver);
1480
1481MODULE_DESCRIPTION("Freescale DSPI Controller Driver");
1482MODULE_LICENSE("GPL");
1483MODULE_ALIAS("platform:" DRIVER_NAME);
1// SPDX-License-Identifier: GPL-2.0+
2//
3// Copyright 2013 Freescale Semiconductor, Inc.
4// Copyright 2020 NXP
5//
6// Freescale DSPI driver
7// This file contains a driver for the Freescale DSPI
8
9#include <linux/clk.h>
10#include <linux/delay.h>
11#include <linux/dmaengine.h>
12#include <linux/dma-mapping.h>
13#include <linux/interrupt.h>
14#include <linux/kernel.h>
15#include <linux/module.h>
16#include <linux/of.h>
17#include <linux/platform_device.h>
18#include <linux/pinctrl/consumer.h>
19#include <linux/regmap.h>
20#include <linux/spi/spi.h>
21#include <linux/spi/spi-fsl-dspi.h>
22
23#define DRIVER_NAME "fsl-dspi"
24
25#define SPI_MCR 0x00
26#define SPI_MCR_HOST BIT(31)
27#define SPI_MCR_PCSIS(x) ((x) << 16)
28#define SPI_MCR_CLR_TXF BIT(11)
29#define SPI_MCR_CLR_RXF BIT(10)
30#define SPI_MCR_XSPI BIT(3)
31#define SPI_MCR_DIS_TXF BIT(13)
32#define SPI_MCR_DIS_RXF BIT(12)
33#define SPI_MCR_HALT BIT(0)
34
35#define SPI_TCR 0x08
36#define SPI_TCR_GET_TCNT(x) (((x) & GENMASK(31, 16)) >> 16)
37
38#define SPI_CTAR(x) (0x0c + (((x) & GENMASK(1, 0)) * 4))
39#define SPI_CTAR_FMSZ(x) (((x) << 27) & GENMASK(30, 27))
40#define SPI_CTAR_CPOL BIT(26)
41#define SPI_CTAR_CPHA BIT(25)
42#define SPI_CTAR_LSBFE BIT(24)
43#define SPI_CTAR_PCSSCK(x) (((x) << 22) & GENMASK(23, 22))
44#define SPI_CTAR_PASC(x) (((x) << 20) & GENMASK(21, 20))
45#define SPI_CTAR_PDT(x) (((x) << 18) & GENMASK(19, 18))
46#define SPI_CTAR_PBR(x) (((x) << 16) & GENMASK(17, 16))
47#define SPI_CTAR_CSSCK(x) (((x) << 12) & GENMASK(15, 12))
48#define SPI_CTAR_ASC(x) (((x) << 8) & GENMASK(11, 8))
49#define SPI_CTAR_DT(x) (((x) << 4) & GENMASK(7, 4))
50#define SPI_CTAR_BR(x) ((x) & GENMASK(3, 0))
51#define SPI_CTAR_SCALE_BITS 0xf
52
53#define SPI_CTAR0_SLAVE 0x0c
54
55#define SPI_SR 0x2c
56#define SPI_SR_TCFQF BIT(31)
57#define SPI_SR_TFUF BIT(27)
58#define SPI_SR_TFFF BIT(25)
59#define SPI_SR_CMDTCF BIT(23)
60#define SPI_SR_SPEF BIT(21)
61#define SPI_SR_RFOF BIT(19)
62#define SPI_SR_TFIWF BIT(18)
63#define SPI_SR_RFDF BIT(17)
64#define SPI_SR_CMDFFF BIT(16)
65#define SPI_SR_CLEAR (SPI_SR_TCFQF | \
66 SPI_SR_TFUF | SPI_SR_TFFF | \
67 SPI_SR_CMDTCF | SPI_SR_SPEF | \
68 SPI_SR_RFOF | SPI_SR_TFIWF | \
69 SPI_SR_RFDF | SPI_SR_CMDFFF)
70
71#define SPI_RSER_TFFFE BIT(25)
72#define SPI_RSER_TFFFD BIT(24)
73#define SPI_RSER_RFDFE BIT(17)
74#define SPI_RSER_RFDFD BIT(16)
75
76#define SPI_RSER 0x30
77#define SPI_RSER_TCFQE BIT(31)
78#define SPI_RSER_CMDTCFE BIT(23)
79
80#define SPI_PUSHR 0x34
81#define SPI_PUSHR_CMD_CONT BIT(15)
82#define SPI_PUSHR_CMD_CTAS(x) (((x) << 12 & GENMASK(14, 12)))
83#define SPI_PUSHR_CMD_EOQ BIT(11)
84#define SPI_PUSHR_CMD_CTCNT BIT(10)
85#define SPI_PUSHR_CMD_PCS(x) (BIT(x) & GENMASK(5, 0))
86
87#define SPI_PUSHR_SLAVE 0x34
88
89#define SPI_POPR 0x38
90
91#define SPI_TXFR0 0x3c
92#define SPI_TXFR1 0x40
93#define SPI_TXFR2 0x44
94#define SPI_TXFR3 0x48
95#define SPI_RXFR0 0x7c
96#define SPI_RXFR1 0x80
97#define SPI_RXFR2 0x84
98#define SPI_RXFR3 0x88
99
100#define SPI_CTARE(x) (0x11c + (((x) & GENMASK(1, 0)) * 4))
101#define SPI_CTARE_FMSZE(x) (((x) & 0x1) << 16)
102#define SPI_CTARE_DTCP(x) ((x) & 0x7ff)
103
104#define SPI_SREX 0x13c
105
106#define SPI_FRAME_BITS(bits) SPI_CTAR_FMSZ((bits) - 1)
107#define SPI_FRAME_EBITS(bits) SPI_CTARE_FMSZE(((bits) - 1) >> 4)
108
109#define DMA_COMPLETION_TIMEOUT msecs_to_jiffies(3000)
110
111struct chip_data {
112 u32 ctar_val;
113};
114
115enum dspi_trans_mode {
116 DSPI_XSPI_MODE,
117 DSPI_DMA_MODE,
118};
119
120struct fsl_dspi_devtype_data {
121 enum dspi_trans_mode trans_mode;
122 u8 max_clock_factor;
123 int fifo_size;
124};
125
126enum {
127 LS1021A,
128 LS1012A,
129 LS1028A,
130 LS1043A,
131 LS1046A,
132 LS2080A,
133 LS2085A,
134 LX2160A,
135 MCF5441X,
136 VF610,
137};
138
139static const struct fsl_dspi_devtype_data devtype_data[] = {
140 [VF610] = {
141 .trans_mode = DSPI_DMA_MODE,
142 .max_clock_factor = 2,
143 .fifo_size = 4,
144 },
145 [LS1021A] = {
146 /* Has A-011218 DMA erratum */
147 .trans_mode = DSPI_XSPI_MODE,
148 .max_clock_factor = 8,
149 .fifo_size = 4,
150 },
151 [LS1012A] = {
152 /* Has A-011218 DMA erratum */
153 .trans_mode = DSPI_XSPI_MODE,
154 .max_clock_factor = 8,
155 .fifo_size = 16,
156 },
157 [LS1028A] = {
158 .trans_mode = DSPI_XSPI_MODE,
159 .max_clock_factor = 8,
160 .fifo_size = 4,
161 },
162 [LS1043A] = {
163 /* Has A-011218 DMA erratum */
164 .trans_mode = DSPI_XSPI_MODE,
165 .max_clock_factor = 8,
166 .fifo_size = 16,
167 },
168 [LS1046A] = {
169 /* Has A-011218 DMA erratum */
170 .trans_mode = DSPI_XSPI_MODE,
171 .max_clock_factor = 8,
172 .fifo_size = 16,
173 },
174 [LS2080A] = {
175 .trans_mode = DSPI_XSPI_MODE,
176 .max_clock_factor = 8,
177 .fifo_size = 4,
178 },
179 [LS2085A] = {
180 .trans_mode = DSPI_XSPI_MODE,
181 .max_clock_factor = 8,
182 .fifo_size = 4,
183 },
184 [LX2160A] = {
185 .trans_mode = DSPI_XSPI_MODE,
186 .max_clock_factor = 8,
187 .fifo_size = 4,
188 },
189 [MCF5441X] = {
190 .trans_mode = DSPI_DMA_MODE,
191 .max_clock_factor = 8,
192 .fifo_size = 16,
193 },
194};
195
196struct fsl_dspi_dma {
197 u32 *tx_dma_buf;
198 struct dma_chan *chan_tx;
199 dma_addr_t tx_dma_phys;
200 struct completion cmd_tx_complete;
201 struct dma_async_tx_descriptor *tx_desc;
202
203 u32 *rx_dma_buf;
204 struct dma_chan *chan_rx;
205 dma_addr_t rx_dma_phys;
206 struct completion cmd_rx_complete;
207 struct dma_async_tx_descriptor *rx_desc;
208};
209
210struct fsl_dspi {
211 struct spi_controller *ctlr;
212 struct platform_device *pdev;
213
214 struct regmap *regmap;
215 struct regmap *regmap_pushr;
216 int irq;
217 struct clk *clk;
218
219 struct spi_transfer *cur_transfer;
220 struct spi_message *cur_msg;
221 struct chip_data *cur_chip;
222 size_t progress;
223 size_t len;
224 const void *tx;
225 void *rx;
226 u16 tx_cmd;
227 const struct fsl_dspi_devtype_data *devtype_data;
228
229 struct completion xfer_done;
230
231 struct fsl_dspi_dma *dma;
232
233 int oper_word_size;
234 int oper_bits_per_word;
235
236 int words_in_flight;
237
238 /*
239 * Offsets for CMD and TXDATA within SPI_PUSHR when accessed
240 * individually (in XSPI mode)
241 */
242 int pushr_cmd;
243 int pushr_tx;
244
245 void (*host_to_dev)(struct fsl_dspi *dspi, u32 *txdata);
246 void (*dev_to_host)(struct fsl_dspi *dspi, u32 rxdata);
247};
248
249static void dspi_native_host_to_dev(struct fsl_dspi *dspi, u32 *txdata)
250{
251 switch (dspi->oper_word_size) {
252 case 1:
253 *txdata = *(u8 *)dspi->tx;
254 break;
255 case 2:
256 *txdata = *(u16 *)dspi->tx;
257 break;
258 case 4:
259 *txdata = *(u32 *)dspi->tx;
260 break;
261 }
262 dspi->tx += dspi->oper_word_size;
263}
264
265static void dspi_native_dev_to_host(struct fsl_dspi *dspi, u32 rxdata)
266{
267 switch (dspi->oper_word_size) {
268 case 1:
269 *(u8 *)dspi->rx = rxdata;
270 break;
271 case 2:
272 *(u16 *)dspi->rx = rxdata;
273 break;
274 case 4:
275 *(u32 *)dspi->rx = rxdata;
276 break;
277 }
278 dspi->rx += dspi->oper_word_size;
279}
280
281static void dspi_8on32_host_to_dev(struct fsl_dspi *dspi, u32 *txdata)
282{
283 *txdata = cpu_to_be32(*(u32 *)dspi->tx);
284 dspi->tx += sizeof(u32);
285}
286
287static void dspi_8on32_dev_to_host(struct fsl_dspi *dspi, u32 rxdata)
288{
289 *(u32 *)dspi->rx = be32_to_cpu(rxdata);
290 dspi->rx += sizeof(u32);
291}
292
293static void dspi_8on16_host_to_dev(struct fsl_dspi *dspi, u32 *txdata)
294{
295 *txdata = cpu_to_be16(*(u16 *)dspi->tx);
296 dspi->tx += sizeof(u16);
297}
298
299static void dspi_8on16_dev_to_host(struct fsl_dspi *dspi, u32 rxdata)
300{
301 *(u16 *)dspi->rx = be16_to_cpu(rxdata);
302 dspi->rx += sizeof(u16);
303}
304
305static void dspi_16on32_host_to_dev(struct fsl_dspi *dspi, u32 *txdata)
306{
307 u16 hi = *(u16 *)dspi->tx;
308 u16 lo = *(u16 *)(dspi->tx + 2);
309
310 *txdata = (u32)hi << 16 | lo;
311 dspi->tx += sizeof(u32);
312}
313
314static void dspi_16on32_dev_to_host(struct fsl_dspi *dspi, u32 rxdata)
315{
316 u16 hi = rxdata & 0xffff;
317 u16 lo = rxdata >> 16;
318
319 *(u16 *)dspi->rx = lo;
320 *(u16 *)(dspi->rx + 2) = hi;
321 dspi->rx += sizeof(u32);
322}
323
324/*
325 * Pop one word from the TX buffer for pushing into the
326 * PUSHR register (TX FIFO)
327 */
328static u32 dspi_pop_tx(struct fsl_dspi *dspi)
329{
330 u32 txdata = 0;
331
332 if (dspi->tx)
333 dspi->host_to_dev(dspi, &txdata);
334 dspi->len -= dspi->oper_word_size;
335 return txdata;
336}
337
338/* Prepare one TX FIFO entry (txdata plus cmd) */
339static u32 dspi_pop_tx_pushr(struct fsl_dspi *dspi)
340{
341 u16 cmd = dspi->tx_cmd, data = dspi_pop_tx(dspi);
342
343 if (spi_controller_is_target(dspi->ctlr))
344 return data;
345
346 if (dspi->len > 0)
347 cmd |= SPI_PUSHR_CMD_CONT;
348 return cmd << 16 | data;
349}
350
351/* Push one word to the RX buffer from the POPR register (RX FIFO) */
352static void dspi_push_rx(struct fsl_dspi *dspi, u32 rxdata)
353{
354 if (!dspi->rx)
355 return;
356 dspi->dev_to_host(dspi, rxdata);
357}
358
359static void dspi_tx_dma_callback(void *arg)
360{
361 struct fsl_dspi *dspi = arg;
362 struct fsl_dspi_dma *dma = dspi->dma;
363
364 complete(&dma->cmd_tx_complete);
365}
366
367static void dspi_rx_dma_callback(void *arg)
368{
369 struct fsl_dspi *dspi = arg;
370 struct fsl_dspi_dma *dma = dspi->dma;
371 int i;
372
373 if (dspi->rx) {
374 for (i = 0; i < dspi->words_in_flight; i++)
375 dspi_push_rx(dspi, dspi->dma->rx_dma_buf[i]);
376 }
377
378 complete(&dma->cmd_rx_complete);
379}
380
381static int dspi_next_xfer_dma_submit(struct fsl_dspi *dspi)
382{
383 struct device *dev = &dspi->pdev->dev;
384 struct fsl_dspi_dma *dma = dspi->dma;
385 int time_left;
386 int i;
387
388 for (i = 0; i < dspi->words_in_flight; i++)
389 dspi->dma->tx_dma_buf[i] = dspi_pop_tx_pushr(dspi);
390
391 dma->tx_desc = dmaengine_prep_slave_single(dma->chan_tx,
392 dma->tx_dma_phys,
393 dspi->words_in_flight *
394 DMA_SLAVE_BUSWIDTH_4_BYTES,
395 DMA_MEM_TO_DEV,
396 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
397 if (!dma->tx_desc) {
398 dev_err(dev, "Not able to get desc for DMA xfer\n");
399 return -EIO;
400 }
401
402 dma->tx_desc->callback = dspi_tx_dma_callback;
403 dma->tx_desc->callback_param = dspi;
404 if (dma_submit_error(dmaengine_submit(dma->tx_desc))) {
405 dev_err(dev, "DMA submit failed\n");
406 return -EINVAL;
407 }
408
409 dma->rx_desc = dmaengine_prep_slave_single(dma->chan_rx,
410 dma->rx_dma_phys,
411 dspi->words_in_flight *
412 DMA_SLAVE_BUSWIDTH_4_BYTES,
413 DMA_DEV_TO_MEM,
414 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
415 if (!dma->rx_desc) {
416 dev_err(dev, "Not able to get desc for DMA xfer\n");
417 return -EIO;
418 }
419
420 dma->rx_desc->callback = dspi_rx_dma_callback;
421 dma->rx_desc->callback_param = dspi;
422 if (dma_submit_error(dmaengine_submit(dma->rx_desc))) {
423 dev_err(dev, "DMA submit failed\n");
424 return -EINVAL;
425 }
426
427 reinit_completion(&dspi->dma->cmd_rx_complete);
428 reinit_completion(&dspi->dma->cmd_tx_complete);
429
430 dma_async_issue_pending(dma->chan_rx);
431 dma_async_issue_pending(dma->chan_tx);
432
433 if (spi_controller_is_target(dspi->ctlr)) {
434 wait_for_completion_interruptible(&dspi->dma->cmd_rx_complete);
435 return 0;
436 }
437
438 time_left = wait_for_completion_timeout(&dspi->dma->cmd_tx_complete,
439 DMA_COMPLETION_TIMEOUT);
440 if (time_left == 0) {
441 dev_err(dev, "DMA tx timeout\n");
442 dmaengine_terminate_all(dma->chan_tx);
443 dmaengine_terminate_all(dma->chan_rx);
444 return -ETIMEDOUT;
445 }
446
447 time_left = wait_for_completion_timeout(&dspi->dma->cmd_rx_complete,
448 DMA_COMPLETION_TIMEOUT);
449 if (time_left == 0) {
450 dev_err(dev, "DMA rx timeout\n");
451 dmaengine_terminate_all(dma->chan_tx);
452 dmaengine_terminate_all(dma->chan_rx);
453 return -ETIMEDOUT;
454 }
455
456 return 0;
457}
458
459static void dspi_setup_accel(struct fsl_dspi *dspi);
460
461static int dspi_dma_xfer(struct fsl_dspi *dspi)
462{
463 struct spi_message *message = dspi->cur_msg;
464 struct device *dev = &dspi->pdev->dev;
465 int ret = 0;
466
467 /*
468 * dspi->len gets decremented by dspi_pop_tx_pushr in
469 * dspi_next_xfer_dma_submit
470 */
471 while (dspi->len) {
472 /* Figure out operational bits-per-word for this chunk */
473 dspi_setup_accel(dspi);
474
475 dspi->words_in_flight = dspi->len / dspi->oper_word_size;
476 if (dspi->words_in_flight > dspi->devtype_data->fifo_size)
477 dspi->words_in_flight = dspi->devtype_data->fifo_size;
478
479 message->actual_length += dspi->words_in_flight *
480 dspi->oper_word_size;
481
482 ret = dspi_next_xfer_dma_submit(dspi);
483 if (ret) {
484 dev_err(dev, "DMA transfer failed\n");
485 break;
486 }
487 }
488
489 return ret;
490}
491
492static int dspi_request_dma(struct fsl_dspi *dspi, phys_addr_t phy_addr)
493{
494 int dma_bufsize = dspi->devtype_data->fifo_size * 2;
495 struct device *dev = &dspi->pdev->dev;
496 struct dma_slave_config cfg;
497 struct fsl_dspi_dma *dma;
498 int ret;
499
500 dma = devm_kzalloc(dev, sizeof(*dma), GFP_KERNEL);
501 if (!dma)
502 return -ENOMEM;
503
504 dma->chan_rx = dma_request_chan(dev, "rx");
505 if (IS_ERR(dma->chan_rx))
506 return dev_err_probe(dev, PTR_ERR(dma->chan_rx), "rx dma channel not available\n");
507
508 dma->chan_tx = dma_request_chan(dev, "tx");
509 if (IS_ERR(dma->chan_tx)) {
510 ret = dev_err_probe(dev, PTR_ERR(dma->chan_tx), "tx dma channel not available\n");
511 goto err_tx_channel;
512 }
513
514 dma->tx_dma_buf = dma_alloc_coherent(dma->chan_tx->device->dev,
515 dma_bufsize, &dma->tx_dma_phys,
516 GFP_KERNEL);
517 if (!dma->tx_dma_buf) {
518 ret = -ENOMEM;
519 goto err_tx_dma_buf;
520 }
521
522 dma->rx_dma_buf = dma_alloc_coherent(dma->chan_rx->device->dev,
523 dma_bufsize, &dma->rx_dma_phys,
524 GFP_KERNEL);
525 if (!dma->rx_dma_buf) {
526 ret = -ENOMEM;
527 goto err_rx_dma_buf;
528 }
529
530 memset(&cfg, 0, sizeof(cfg));
531 cfg.src_addr = phy_addr + SPI_POPR;
532 cfg.dst_addr = phy_addr + SPI_PUSHR;
533 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
534 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
535 cfg.src_maxburst = 1;
536 cfg.dst_maxburst = 1;
537
538 cfg.direction = DMA_DEV_TO_MEM;
539 ret = dmaengine_slave_config(dma->chan_rx, &cfg);
540 if (ret) {
541 dev_err_probe(dev, ret, "can't configure rx dma channel\n");
542 goto err_slave_config;
543 }
544
545 cfg.direction = DMA_MEM_TO_DEV;
546 ret = dmaengine_slave_config(dma->chan_tx, &cfg);
547 if (ret) {
548 dev_err_probe(dev, ret, "can't configure tx dma channel\n");
549 goto err_slave_config;
550 }
551
552 dspi->dma = dma;
553 init_completion(&dma->cmd_tx_complete);
554 init_completion(&dma->cmd_rx_complete);
555
556 return 0;
557
558err_slave_config:
559 dma_free_coherent(dma->chan_rx->device->dev,
560 dma_bufsize, dma->rx_dma_buf, dma->rx_dma_phys);
561err_rx_dma_buf:
562 dma_free_coherent(dma->chan_tx->device->dev,
563 dma_bufsize, dma->tx_dma_buf, dma->tx_dma_phys);
564err_tx_dma_buf:
565 dma_release_channel(dma->chan_tx);
566err_tx_channel:
567 dma_release_channel(dma->chan_rx);
568
569 devm_kfree(dev, dma);
570 dspi->dma = NULL;
571
572 return ret;
573}
574
575static void dspi_release_dma(struct fsl_dspi *dspi)
576{
577 int dma_bufsize = dspi->devtype_data->fifo_size * 2;
578 struct fsl_dspi_dma *dma = dspi->dma;
579
580 if (!dma)
581 return;
582
583 if (dma->chan_tx) {
584 dma_free_coherent(dma->chan_tx->device->dev, dma_bufsize,
585 dma->tx_dma_buf, dma->tx_dma_phys);
586 dma_release_channel(dma->chan_tx);
587 }
588
589 if (dma->chan_rx) {
590 dma_free_coherent(dma->chan_rx->device->dev, dma_bufsize,
591 dma->rx_dma_buf, dma->rx_dma_phys);
592 dma_release_channel(dma->chan_rx);
593 }
594}
595
596static void hz_to_spi_baud(char *pbr, char *br, int speed_hz,
597 unsigned long clkrate)
598{
599 /* Valid baud rate pre-scaler values */
600 int pbr_tbl[4] = {2, 3, 5, 7};
601 int brs[16] = { 2, 4, 6, 8,
602 16, 32, 64, 128,
603 256, 512, 1024, 2048,
604 4096, 8192, 16384, 32768 };
605 int scale_needed, scale, minscale = INT_MAX;
606 int i, j;
607
608 scale_needed = clkrate / speed_hz;
609 if (clkrate % speed_hz)
610 scale_needed++;
611
612 for (i = 0; i < ARRAY_SIZE(brs); i++)
613 for (j = 0; j < ARRAY_SIZE(pbr_tbl); j++) {
614 scale = brs[i] * pbr_tbl[j];
615 if (scale >= scale_needed) {
616 if (scale < minscale) {
617 minscale = scale;
618 *br = i;
619 *pbr = j;
620 }
621 break;
622 }
623 }
624
625 if (minscale == INT_MAX) {
626 pr_warn("Can not find valid baud rate,speed_hz is %d,clkrate is %ld, we use the max prescaler value.\n",
627 speed_hz, clkrate);
628 *pbr = ARRAY_SIZE(pbr_tbl) - 1;
629 *br = ARRAY_SIZE(brs) - 1;
630 }
631}
632
633static void ns_delay_scale(char *psc, char *sc, int delay_ns,
634 unsigned long clkrate)
635{
636 int scale_needed, scale, minscale = INT_MAX;
637 int pscale_tbl[4] = {1, 3, 5, 7};
638 u32 remainder;
639 int i, j;
640
641 scale_needed = div_u64_rem((u64)delay_ns * clkrate, NSEC_PER_SEC,
642 &remainder);
643 if (remainder)
644 scale_needed++;
645
646 for (i = 0; i < ARRAY_SIZE(pscale_tbl); i++)
647 for (j = 0; j <= SPI_CTAR_SCALE_BITS; j++) {
648 scale = pscale_tbl[i] * (2 << j);
649 if (scale >= scale_needed) {
650 if (scale < minscale) {
651 minscale = scale;
652 *psc = i;
653 *sc = j;
654 }
655 break;
656 }
657 }
658
659 if (minscale == INT_MAX) {
660 pr_warn("Cannot find correct scale values for %dns delay at clkrate %ld, using max prescaler value",
661 delay_ns, clkrate);
662 *psc = ARRAY_SIZE(pscale_tbl) - 1;
663 *sc = SPI_CTAR_SCALE_BITS;
664 }
665}
666
667static void dspi_pushr_cmd_write(struct fsl_dspi *dspi, u16 cmd)
668{
669 /*
670 * The only time when the PCS doesn't need continuation after this word
671 * is when it's last. We need to look ahead, because we actually call
672 * dspi_pop_tx (the function that decrements dspi->len) _after_
673 * dspi_pushr_cmd_write with XSPI mode. As for how much in advance? One
674 * word is enough. If there's more to transmit than that,
675 * dspi_xspi_write will know to split the FIFO writes in 2, and
676 * generate a new PUSHR command with the final word that will have PCS
677 * deasserted (not continued) here.
678 */
679 if (dspi->len > dspi->oper_word_size)
680 cmd |= SPI_PUSHR_CMD_CONT;
681 regmap_write(dspi->regmap_pushr, dspi->pushr_cmd, cmd);
682}
683
684static void dspi_pushr_txdata_write(struct fsl_dspi *dspi, u16 txdata)
685{
686 regmap_write(dspi->regmap_pushr, dspi->pushr_tx, txdata);
687}
688
689static void dspi_xspi_fifo_write(struct fsl_dspi *dspi, int num_words)
690{
691 int num_bytes = num_words * dspi->oper_word_size;
692 u16 tx_cmd = dspi->tx_cmd;
693
694 /*
695 * If the PCS needs to de-assert (i.e. we're at the end of the buffer
696 * and cs_change does not want the PCS to stay on), then we need a new
697 * PUSHR command, since this one (for the body of the buffer)
698 * necessarily has the CONT bit set.
699 * So send one word less during this go, to force a split and a command
700 * with a single word next time, when CONT will be unset.
701 */
702 if (!(dspi->tx_cmd & SPI_PUSHR_CMD_CONT) && num_bytes == dspi->len)
703 tx_cmd |= SPI_PUSHR_CMD_EOQ;
704
705 /* Update CTARE */
706 regmap_write(dspi->regmap, SPI_CTARE(0),
707 SPI_FRAME_EBITS(dspi->oper_bits_per_word) |
708 SPI_CTARE_DTCP(num_words));
709
710 /*
711 * Write the CMD FIFO entry first, and then the two
712 * corresponding TX FIFO entries (or one...).
713 */
714 dspi_pushr_cmd_write(dspi, tx_cmd);
715
716 /* Fill TX FIFO with as many transfers as possible */
717 while (num_words--) {
718 u32 data = dspi_pop_tx(dspi);
719
720 dspi_pushr_txdata_write(dspi, data & 0xFFFF);
721 if (dspi->oper_bits_per_word > 16)
722 dspi_pushr_txdata_write(dspi, data >> 16);
723 }
724}
725
726static u32 dspi_popr_read(struct fsl_dspi *dspi)
727{
728 u32 rxdata = 0;
729
730 regmap_read(dspi->regmap, SPI_POPR, &rxdata);
731 return rxdata;
732}
733
734static void dspi_fifo_read(struct fsl_dspi *dspi)
735{
736 int num_fifo_entries = dspi->words_in_flight;
737
738 /* Read one FIFO entry and push to rx buffer */
739 while (num_fifo_entries--)
740 dspi_push_rx(dspi, dspi_popr_read(dspi));
741}
742
743static void dspi_setup_accel(struct fsl_dspi *dspi)
744{
745 struct spi_transfer *xfer = dspi->cur_transfer;
746 bool odd = !!(dspi->len & 1);
747
748 /* No accel for frames not multiple of 8 bits at the moment */
749 if (xfer->bits_per_word % 8)
750 goto no_accel;
751
752 if (!odd && dspi->len <= dspi->devtype_data->fifo_size * 2) {
753 dspi->oper_bits_per_word = 16;
754 } else if (odd && dspi->len <= dspi->devtype_data->fifo_size) {
755 dspi->oper_bits_per_word = 8;
756 } else {
757 /* Start off with maximum supported by hardware */
758 if (dspi->devtype_data->trans_mode == DSPI_XSPI_MODE)
759 dspi->oper_bits_per_word = 32;
760 else
761 dspi->oper_bits_per_word = 16;
762
763 /*
764 * And go down only if the buffer can't be sent with
765 * words this big
766 */
767 do {
768 if (dspi->len >= DIV_ROUND_UP(dspi->oper_bits_per_word, 8))
769 break;
770
771 dspi->oper_bits_per_word /= 2;
772 } while (dspi->oper_bits_per_word > 8);
773 }
774
775 if (xfer->bits_per_word == 8 && dspi->oper_bits_per_word == 32) {
776 dspi->dev_to_host = dspi_8on32_dev_to_host;
777 dspi->host_to_dev = dspi_8on32_host_to_dev;
778 } else if (xfer->bits_per_word == 8 && dspi->oper_bits_per_word == 16) {
779 dspi->dev_to_host = dspi_8on16_dev_to_host;
780 dspi->host_to_dev = dspi_8on16_host_to_dev;
781 } else if (xfer->bits_per_word == 16 && dspi->oper_bits_per_word == 32) {
782 dspi->dev_to_host = dspi_16on32_dev_to_host;
783 dspi->host_to_dev = dspi_16on32_host_to_dev;
784 } else {
785no_accel:
786 dspi->dev_to_host = dspi_native_dev_to_host;
787 dspi->host_to_dev = dspi_native_host_to_dev;
788 dspi->oper_bits_per_word = xfer->bits_per_word;
789 }
790
791 dspi->oper_word_size = DIV_ROUND_UP(dspi->oper_bits_per_word, 8);
792
793 /*
794 * Update CTAR here (code is common for XSPI and DMA modes).
795 * We will update CTARE in the portion specific to XSPI, when we
796 * also know the preload value (DTCP).
797 */
798 regmap_write(dspi->regmap, SPI_CTAR(0),
799 dspi->cur_chip->ctar_val |
800 SPI_FRAME_BITS(dspi->oper_bits_per_word));
801}
802
803static void dspi_fifo_write(struct fsl_dspi *dspi)
804{
805 int num_fifo_entries = dspi->devtype_data->fifo_size;
806 struct spi_transfer *xfer = dspi->cur_transfer;
807 struct spi_message *msg = dspi->cur_msg;
808 int num_words, num_bytes;
809
810 dspi_setup_accel(dspi);
811
812 /* In XSPI mode each 32-bit word occupies 2 TX FIFO entries */
813 if (dspi->oper_word_size == 4)
814 num_fifo_entries /= 2;
815
816 /*
817 * Integer division intentionally trims off odd (or non-multiple of 4)
818 * numbers of bytes at the end of the buffer, which will be sent next
819 * time using a smaller oper_word_size.
820 */
821 num_words = dspi->len / dspi->oper_word_size;
822 if (num_words > num_fifo_entries)
823 num_words = num_fifo_entries;
824
825 /* Update total number of bytes that were transferred */
826 num_bytes = num_words * dspi->oper_word_size;
827 msg->actual_length += num_bytes;
828 dspi->progress += num_bytes / DIV_ROUND_UP(xfer->bits_per_word, 8);
829
830 /*
831 * Update shared variable for use in the next interrupt (both in
832 * dspi_fifo_read and in dspi_fifo_write).
833 */
834 dspi->words_in_flight = num_words;
835
836 spi_take_timestamp_pre(dspi->ctlr, xfer, dspi->progress, !dspi->irq);
837
838 dspi_xspi_fifo_write(dspi, num_words);
839 /*
840 * Everything after this point is in a potential race with the next
841 * interrupt, so we must never use dspi->words_in_flight again since it
842 * might already be modified by the next dspi_fifo_write.
843 */
844
845 spi_take_timestamp_post(dspi->ctlr, dspi->cur_transfer,
846 dspi->progress, !dspi->irq);
847}
848
849static int dspi_rxtx(struct fsl_dspi *dspi)
850{
851 dspi_fifo_read(dspi);
852
853 if (!dspi->len)
854 /* Success! */
855 return 0;
856
857 dspi_fifo_write(dspi);
858
859 return -EINPROGRESS;
860}
861
862static int dspi_poll(struct fsl_dspi *dspi)
863{
864 int tries = 1000;
865 u32 spi_sr;
866
867 do {
868 regmap_read(dspi->regmap, SPI_SR, &spi_sr);
869 regmap_write(dspi->regmap, SPI_SR, spi_sr);
870
871 if (spi_sr & SPI_SR_CMDTCF)
872 break;
873 } while (--tries);
874
875 if (!tries)
876 return -ETIMEDOUT;
877
878 return dspi_rxtx(dspi);
879}
880
881static irqreturn_t dspi_interrupt(int irq, void *dev_id)
882{
883 struct fsl_dspi *dspi = (struct fsl_dspi *)dev_id;
884 u32 spi_sr;
885
886 regmap_read(dspi->regmap, SPI_SR, &spi_sr);
887 regmap_write(dspi->regmap, SPI_SR, spi_sr);
888
889 if (!(spi_sr & SPI_SR_CMDTCF))
890 return IRQ_NONE;
891
892 if (dspi_rxtx(dspi) == 0)
893 complete(&dspi->xfer_done);
894
895 return IRQ_HANDLED;
896}
897
898static void dspi_assert_cs(struct spi_device *spi, bool *cs)
899{
900 if (!spi_get_csgpiod(spi, 0) || *cs)
901 return;
902
903 gpiod_set_value_cansleep(spi_get_csgpiod(spi, 0), true);
904 *cs = true;
905}
906
907static void dspi_deassert_cs(struct spi_device *spi, bool *cs)
908{
909 if (!spi_get_csgpiod(spi, 0) || !*cs)
910 return;
911
912 gpiod_set_value_cansleep(spi_get_csgpiod(spi, 0), false);
913 *cs = false;
914}
915
916static int dspi_transfer_one_message(struct spi_controller *ctlr,
917 struct spi_message *message)
918{
919 struct fsl_dspi *dspi = spi_controller_get_devdata(ctlr);
920 struct spi_device *spi = message->spi;
921 struct spi_transfer *transfer;
922 bool cs = false;
923 int status = 0;
924
925 message->actual_length = 0;
926
927 list_for_each_entry(transfer, &message->transfers, transfer_list) {
928 dspi->cur_transfer = transfer;
929 dspi->cur_msg = message;
930 dspi->cur_chip = spi_get_ctldata(spi);
931
932 dspi_assert_cs(spi, &cs);
933
934 /* Prepare command word for CMD FIFO */
935 dspi->tx_cmd = SPI_PUSHR_CMD_CTAS(0);
936 if (!spi_get_csgpiod(spi, 0))
937 dspi->tx_cmd |= SPI_PUSHR_CMD_PCS(spi_get_chipselect(spi, 0));
938
939 if (list_is_last(&dspi->cur_transfer->transfer_list,
940 &dspi->cur_msg->transfers)) {
941 /* Leave PCS activated after last transfer when
942 * cs_change is set.
943 */
944 if (transfer->cs_change)
945 dspi->tx_cmd |= SPI_PUSHR_CMD_CONT;
946 } else {
947 /* Keep PCS active between transfers in same message
948 * when cs_change is not set, and de-activate PCS
949 * between transfers in the same message when
950 * cs_change is set.
951 */
952 if (!transfer->cs_change)
953 dspi->tx_cmd |= SPI_PUSHR_CMD_CONT;
954 }
955
956 dspi->tx = transfer->tx_buf;
957 dspi->rx = transfer->rx_buf;
958 dspi->len = transfer->len;
959 dspi->progress = 0;
960
961 regmap_update_bits(dspi->regmap, SPI_MCR,
962 SPI_MCR_CLR_TXF | SPI_MCR_CLR_RXF,
963 SPI_MCR_CLR_TXF | SPI_MCR_CLR_RXF);
964
965 spi_take_timestamp_pre(dspi->ctlr, dspi->cur_transfer,
966 dspi->progress, !dspi->irq);
967
968 if (dspi->devtype_data->trans_mode == DSPI_DMA_MODE) {
969 status = dspi_dma_xfer(dspi);
970 } else {
971 dspi_fifo_write(dspi);
972
973 if (dspi->irq) {
974 wait_for_completion(&dspi->xfer_done);
975 reinit_completion(&dspi->xfer_done);
976 } else {
977 do {
978 status = dspi_poll(dspi);
979 } while (status == -EINPROGRESS);
980 }
981 }
982 if (status)
983 break;
984
985 spi_transfer_delay_exec(transfer);
986
987 if (!(dspi->tx_cmd & SPI_PUSHR_CMD_CONT))
988 dspi_deassert_cs(spi, &cs);
989 }
990
991 message->status = status;
992 spi_finalize_current_message(ctlr);
993
994 return status;
995}
996
997static int dspi_setup(struct spi_device *spi)
998{
999 struct fsl_dspi *dspi = spi_controller_get_devdata(spi->controller);
1000 u32 period_ns = DIV_ROUND_UP(NSEC_PER_SEC, spi->max_speed_hz);
1001 unsigned char br = 0, pbr = 0, pcssck = 0, cssck = 0;
1002 u32 quarter_period_ns = DIV_ROUND_UP(period_ns, 4);
1003 u32 cs_sck_delay = 0, sck_cs_delay = 0;
1004 struct fsl_dspi_platform_data *pdata;
1005 unsigned char pasc = 0, asc = 0;
1006 struct chip_data *chip;
1007 unsigned long clkrate;
1008 bool cs = true;
1009
1010 /* Only alloc on first setup */
1011 chip = spi_get_ctldata(spi);
1012 if (chip == NULL) {
1013 chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL);
1014 if (!chip)
1015 return -ENOMEM;
1016 }
1017
1018 pdata = dev_get_platdata(&dspi->pdev->dev);
1019
1020 if (!pdata) {
1021 of_property_read_u32(spi->dev.of_node, "fsl,spi-cs-sck-delay",
1022 &cs_sck_delay);
1023
1024 of_property_read_u32(spi->dev.of_node, "fsl,spi-sck-cs-delay",
1025 &sck_cs_delay);
1026 } else {
1027 cs_sck_delay = pdata->cs_sck_delay;
1028 sck_cs_delay = pdata->sck_cs_delay;
1029 }
1030
1031 /* Since tCSC and tASC apply to continuous transfers too, avoid SCK
1032 * glitches of half a cycle by never allowing tCSC + tASC to go below
1033 * half a SCK period.
1034 */
1035 if (cs_sck_delay < quarter_period_ns)
1036 cs_sck_delay = quarter_period_ns;
1037 if (sck_cs_delay < quarter_period_ns)
1038 sck_cs_delay = quarter_period_ns;
1039
1040 dev_dbg(&spi->dev,
1041 "DSPI controller timing params: CS-to-SCK delay %u ns, SCK-to-CS delay %u ns\n",
1042 cs_sck_delay, sck_cs_delay);
1043
1044 clkrate = clk_get_rate(dspi->clk);
1045 hz_to_spi_baud(&pbr, &br, spi->max_speed_hz, clkrate);
1046
1047 /* Set PCS to SCK delay scale values */
1048 ns_delay_scale(&pcssck, &cssck, cs_sck_delay, clkrate);
1049
1050 /* Set After SCK delay scale values */
1051 ns_delay_scale(&pasc, &asc, sck_cs_delay, clkrate);
1052
1053 chip->ctar_val = 0;
1054 if (spi->mode & SPI_CPOL)
1055 chip->ctar_val |= SPI_CTAR_CPOL;
1056 if (spi->mode & SPI_CPHA)
1057 chip->ctar_val |= SPI_CTAR_CPHA;
1058
1059 if (!spi_controller_is_target(dspi->ctlr)) {
1060 chip->ctar_val |= SPI_CTAR_PCSSCK(pcssck) |
1061 SPI_CTAR_CSSCK(cssck) |
1062 SPI_CTAR_PASC(pasc) |
1063 SPI_CTAR_ASC(asc) |
1064 SPI_CTAR_PBR(pbr) |
1065 SPI_CTAR_BR(br);
1066
1067 if (spi->mode & SPI_LSB_FIRST)
1068 chip->ctar_val |= SPI_CTAR_LSBFE;
1069 }
1070
1071 gpiod_direction_output(spi_get_csgpiod(spi, 0), false);
1072 dspi_deassert_cs(spi, &cs);
1073
1074 spi_set_ctldata(spi, chip);
1075
1076 return 0;
1077}
1078
1079static void dspi_cleanup(struct spi_device *spi)
1080{
1081 struct chip_data *chip = spi_get_ctldata(spi);
1082
1083 dev_dbg(&spi->dev, "spi_device %u.%u cleanup\n",
1084 spi->controller->bus_num, spi_get_chipselect(spi, 0));
1085
1086 kfree(chip);
1087}
1088
1089static const struct of_device_id fsl_dspi_dt_ids[] = {
1090 {
1091 .compatible = "fsl,vf610-dspi",
1092 .data = &devtype_data[VF610],
1093 }, {
1094 .compatible = "fsl,ls1021a-v1.0-dspi",
1095 .data = &devtype_data[LS1021A],
1096 }, {
1097 .compatible = "fsl,ls1012a-dspi",
1098 .data = &devtype_data[LS1012A],
1099 }, {
1100 .compatible = "fsl,ls1028a-dspi",
1101 .data = &devtype_data[LS1028A],
1102 }, {
1103 .compatible = "fsl,ls1043a-dspi",
1104 .data = &devtype_data[LS1043A],
1105 }, {
1106 .compatible = "fsl,ls1046a-dspi",
1107 .data = &devtype_data[LS1046A],
1108 }, {
1109 .compatible = "fsl,ls2080a-dspi",
1110 .data = &devtype_data[LS2080A],
1111 }, {
1112 .compatible = "fsl,ls2085a-dspi",
1113 .data = &devtype_data[LS2085A],
1114 }, {
1115 .compatible = "fsl,lx2160a-dspi",
1116 .data = &devtype_data[LX2160A],
1117 },
1118 { /* sentinel */ }
1119};
1120MODULE_DEVICE_TABLE(of, fsl_dspi_dt_ids);
1121
1122#ifdef CONFIG_PM_SLEEP
1123static int dspi_suspend(struct device *dev)
1124{
1125 struct fsl_dspi *dspi = dev_get_drvdata(dev);
1126
1127 if (dspi->irq)
1128 disable_irq(dspi->irq);
1129 spi_controller_suspend(dspi->ctlr);
1130 clk_disable_unprepare(dspi->clk);
1131
1132 pinctrl_pm_select_sleep_state(dev);
1133
1134 return 0;
1135}
1136
1137static int dspi_resume(struct device *dev)
1138{
1139 struct fsl_dspi *dspi = dev_get_drvdata(dev);
1140 int ret;
1141
1142 pinctrl_pm_select_default_state(dev);
1143
1144 ret = clk_prepare_enable(dspi->clk);
1145 if (ret)
1146 return ret;
1147 spi_controller_resume(dspi->ctlr);
1148 if (dspi->irq)
1149 enable_irq(dspi->irq);
1150
1151 return 0;
1152}
1153#endif /* CONFIG_PM_SLEEP */
1154
1155static SIMPLE_DEV_PM_OPS(dspi_pm, dspi_suspend, dspi_resume);
1156
1157static const struct regmap_range dspi_volatile_ranges[] = {
1158 regmap_reg_range(SPI_MCR, SPI_TCR),
1159 regmap_reg_range(SPI_SR, SPI_SR),
1160 regmap_reg_range(SPI_PUSHR, SPI_RXFR3),
1161};
1162
1163static const struct regmap_access_table dspi_volatile_table = {
1164 .yes_ranges = dspi_volatile_ranges,
1165 .n_yes_ranges = ARRAY_SIZE(dspi_volatile_ranges),
1166};
1167
1168static const struct regmap_config dspi_regmap_config = {
1169 .reg_bits = 32,
1170 .val_bits = 32,
1171 .reg_stride = 4,
1172 .max_register = 0x88,
1173 .volatile_table = &dspi_volatile_table,
1174};
1175
1176static const struct regmap_range dspi_xspi_volatile_ranges[] = {
1177 regmap_reg_range(SPI_MCR, SPI_TCR),
1178 regmap_reg_range(SPI_SR, SPI_SR),
1179 regmap_reg_range(SPI_PUSHR, SPI_RXFR3),
1180 regmap_reg_range(SPI_SREX, SPI_SREX),
1181};
1182
1183static const struct regmap_access_table dspi_xspi_volatile_table = {
1184 .yes_ranges = dspi_xspi_volatile_ranges,
1185 .n_yes_ranges = ARRAY_SIZE(dspi_xspi_volatile_ranges),
1186};
1187
1188static const struct regmap_config dspi_xspi_regmap_config[] = {
1189 {
1190 .reg_bits = 32,
1191 .val_bits = 32,
1192 .reg_stride = 4,
1193 .max_register = 0x13c,
1194 .volatile_table = &dspi_xspi_volatile_table,
1195 },
1196 {
1197 .name = "pushr",
1198 .reg_bits = 16,
1199 .val_bits = 16,
1200 .reg_stride = 2,
1201 .max_register = 0x2,
1202 },
1203};
1204
1205static int dspi_init(struct fsl_dspi *dspi)
1206{
1207 unsigned int mcr;
1208
1209 /* Set idle states for all chip select signals to high */
1210 mcr = SPI_MCR_PCSIS(GENMASK(dspi->ctlr->max_native_cs - 1, 0));
1211
1212 if (dspi->devtype_data->trans_mode == DSPI_XSPI_MODE)
1213 mcr |= SPI_MCR_XSPI;
1214 if (!spi_controller_is_target(dspi->ctlr))
1215 mcr |= SPI_MCR_HOST;
1216
1217 regmap_write(dspi->regmap, SPI_MCR, mcr);
1218 regmap_write(dspi->regmap, SPI_SR, SPI_SR_CLEAR);
1219
1220 switch (dspi->devtype_data->trans_mode) {
1221 case DSPI_XSPI_MODE:
1222 regmap_write(dspi->regmap, SPI_RSER, SPI_RSER_CMDTCFE);
1223 break;
1224 case DSPI_DMA_MODE:
1225 regmap_write(dspi->regmap, SPI_RSER,
1226 SPI_RSER_TFFFE | SPI_RSER_TFFFD |
1227 SPI_RSER_RFDFE | SPI_RSER_RFDFD);
1228 break;
1229 default:
1230 dev_err(&dspi->pdev->dev, "unsupported trans_mode %u\n",
1231 dspi->devtype_data->trans_mode);
1232 return -EINVAL;
1233 }
1234
1235 return 0;
1236}
1237
1238static int dspi_target_abort(struct spi_controller *host)
1239{
1240 struct fsl_dspi *dspi = spi_controller_get_devdata(host);
1241
1242 /*
1243 * Terminate all pending DMA transactions for the SPI working
1244 * in TARGET mode.
1245 */
1246 if (dspi->devtype_data->trans_mode == DSPI_DMA_MODE) {
1247 dmaengine_terminate_sync(dspi->dma->chan_rx);
1248 dmaengine_terminate_sync(dspi->dma->chan_tx);
1249 }
1250
1251 /* Clear the internal DSPI RX and TX FIFO buffers */
1252 regmap_update_bits(dspi->regmap, SPI_MCR,
1253 SPI_MCR_CLR_TXF | SPI_MCR_CLR_RXF,
1254 SPI_MCR_CLR_TXF | SPI_MCR_CLR_RXF);
1255
1256 return 0;
1257}
1258
1259static int dspi_probe(struct platform_device *pdev)
1260{
1261 struct device_node *np = pdev->dev.of_node;
1262 const struct regmap_config *regmap_config;
1263 struct fsl_dspi_platform_data *pdata;
1264 struct spi_controller *ctlr;
1265 int ret, cs_num, bus_num = -1;
1266 struct fsl_dspi *dspi;
1267 struct resource *res;
1268 void __iomem *base;
1269 bool big_endian;
1270
1271 dspi = devm_kzalloc(&pdev->dev, sizeof(*dspi), GFP_KERNEL);
1272 if (!dspi)
1273 return -ENOMEM;
1274
1275 ctlr = spi_alloc_host(&pdev->dev, 0);
1276 if (!ctlr)
1277 return -ENOMEM;
1278
1279 spi_controller_set_devdata(ctlr, dspi);
1280 platform_set_drvdata(pdev, dspi);
1281
1282 dspi->pdev = pdev;
1283 dspi->ctlr = ctlr;
1284
1285 ctlr->setup = dspi_setup;
1286 ctlr->transfer_one_message = dspi_transfer_one_message;
1287 ctlr->dev.of_node = pdev->dev.of_node;
1288
1289 ctlr->cleanup = dspi_cleanup;
1290 ctlr->target_abort = dspi_target_abort;
1291 ctlr->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST;
1292 ctlr->use_gpio_descriptors = true;
1293
1294 pdata = dev_get_platdata(&pdev->dev);
1295 if (pdata) {
1296 ctlr->num_chipselect = ctlr->max_native_cs = pdata->cs_num;
1297 ctlr->bus_num = pdata->bus_num;
1298
1299 /* Only Coldfire uses platform data */
1300 dspi->devtype_data = &devtype_data[MCF5441X];
1301 big_endian = true;
1302 } else {
1303
1304 ret = of_property_read_u32(np, "spi-num-chipselects", &cs_num);
1305 if (ret < 0) {
1306 dev_err(&pdev->dev, "can't get spi-num-chipselects\n");
1307 goto out_ctlr_put;
1308 }
1309 ctlr->num_chipselect = ctlr->max_native_cs = cs_num;
1310
1311 of_property_read_u32(np, "bus-num", &bus_num);
1312 ctlr->bus_num = bus_num;
1313
1314 if (of_property_read_bool(np, "spi-slave"))
1315 ctlr->target = true;
1316
1317 dspi->devtype_data = of_device_get_match_data(&pdev->dev);
1318 if (!dspi->devtype_data) {
1319 dev_err(&pdev->dev, "can't get devtype_data\n");
1320 ret = -EFAULT;
1321 goto out_ctlr_put;
1322 }
1323
1324 big_endian = of_device_is_big_endian(np);
1325 }
1326 if (big_endian) {
1327 dspi->pushr_cmd = 0;
1328 dspi->pushr_tx = 2;
1329 } else {
1330 dspi->pushr_cmd = 2;
1331 dspi->pushr_tx = 0;
1332 }
1333
1334 if (dspi->devtype_data->trans_mode == DSPI_XSPI_MODE)
1335 ctlr->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32);
1336 else
1337 ctlr->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 16);
1338
1339 base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
1340 if (IS_ERR(base)) {
1341 ret = PTR_ERR(base);
1342 goto out_ctlr_put;
1343 }
1344
1345 if (dspi->devtype_data->trans_mode == DSPI_XSPI_MODE)
1346 regmap_config = &dspi_xspi_regmap_config[0];
1347 else
1348 regmap_config = &dspi_regmap_config;
1349 dspi->regmap = devm_regmap_init_mmio(&pdev->dev, base, regmap_config);
1350 if (IS_ERR(dspi->regmap)) {
1351 dev_err(&pdev->dev, "failed to init regmap: %ld\n",
1352 PTR_ERR(dspi->regmap));
1353 ret = PTR_ERR(dspi->regmap);
1354 goto out_ctlr_put;
1355 }
1356
1357 if (dspi->devtype_data->trans_mode == DSPI_XSPI_MODE) {
1358 dspi->regmap_pushr = devm_regmap_init_mmio(
1359 &pdev->dev, base + SPI_PUSHR,
1360 &dspi_xspi_regmap_config[1]);
1361 if (IS_ERR(dspi->regmap_pushr)) {
1362 dev_err(&pdev->dev,
1363 "failed to init pushr regmap: %ld\n",
1364 PTR_ERR(dspi->regmap_pushr));
1365 ret = PTR_ERR(dspi->regmap_pushr);
1366 goto out_ctlr_put;
1367 }
1368 }
1369
1370 dspi->clk = devm_clk_get_enabled(&pdev->dev, "dspi");
1371 if (IS_ERR(dspi->clk)) {
1372 ret = PTR_ERR(dspi->clk);
1373 dev_err(&pdev->dev, "unable to get clock\n");
1374 goto out_ctlr_put;
1375 }
1376
1377 ret = dspi_init(dspi);
1378 if (ret)
1379 goto out_ctlr_put;
1380
1381 dspi->irq = platform_get_irq(pdev, 0);
1382 if (dspi->irq <= 0) {
1383 dev_info(&pdev->dev,
1384 "can't get platform irq, using poll mode\n");
1385 dspi->irq = 0;
1386 goto poll_mode;
1387 }
1388
1389 init_completion(&dspi->xfer_done);
1390
1391 ret = request_threaded_irq(dspi->irq, dspi_interrupt, NULL,
1392 IRQF_SHARED, pdev->name, dspi);
1393 if (ret < 0) {
1394 dev_err(&pdev->dev, "Unable to attach DSPI interrupt\n");
1395 goto out_ctlr_put;
1396 }
1397
1398poll_mode:
1399
1400 if (dspi->devtype_data->trans_mode == DSPI_DMA_MODE) {
1401 ret = dspi_request_dma(dspi, res->start);
1402 if (ret < 0) {
1403 dev_err(&pdev->dev, "can't get dma channels\n");
1404 goto out_free_irq;
1405 }
1406 }
1407
1408 ctlr->max_speed_hz =
1409 clk_get_rate(dspi->clk) / dspi->devtype_data->max_clock_factor;
1410
1411 if (dspi->devtype_data->trans_mode != DSPI_DMA_MODE)
1412 ctlr->ptp_sts_supported = true;
1413
1414 ret = spi_register_controller(ctlr);
1415 if (ret != 0) {
1416 dev_err(&pdev->dev, "Problem registering DSPI ctlr\n");
1417 goto out_release_dma;
1418 }
1419
1420 return ret;
1421
1422out_release_dma:
1423 dspi_release_dma(dspi);
1424out_free_irq:
1425 if (dspi->irq)
1426 free_irq(dspi->irq, dspi);
1427out_ctlr_put:
1428 spi_controller_put(ctlr);
1429
1430 return ret;
1431}
1432
1433static void dspi_remove(struct platform_device *pdev)
1434{
1435 struct fsl_dspi *dspi = platform_get_drvdata(pdev);
1436
1437 /* Disconnect from the SPI framework */
1438 spi_unregister_controller(dspi->ctlr);
1439
1440 /* Disable RX and TX */
1441 regmap_update_bits(dspi->regmap, SPI_MCR,
1442 SPI_MCR_DIS_TXF | SPI_MCR_DIS_RXF,
1443 SPI_MCR_DIS_TXF | SPI_MCR_DIS_RXF);
1444
1445 /* Stop Running */
1446 regmap_update_bits(dspi->regmap, SPI_MCR, SPI_MCR_HALT, SPI_MCR_HALT);
1447
1448 dspi_release_dma(dspi);
1449 if (dspi->irq)
1450 free_irq(dspi->irq, dspi);
1451}
1452
1453static void dspi_shutdown(struct platform_device *pdev)
1454{
1455 dspi_remove(pdev);
1456}
1457
1458static struct platform_driver fsl_dspi_driver = {
1459 .driver.name = DRIVER_NAME,
1460 .driver.of_match_table = fsl_dspi_dt_ids,
1461 .driver.owner = THIS_MODULE,
1462 .driver.pm = &dspi_pm,
1463 .probe = dspi_probe,
1464 .remove_new = dspi_remove,
1465 .shutdown = dspi_shutdown,
1466};
1467module_platform_driver(fsl_dspi_driver);
1468
1469MODULE_DESCRIPTION("Freescale DSPI Controller Driver");
1470MODULE_LICENSE("GPL");
1471MODULE_ALIAS("platform:" DRIVER_NAME);