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1// SPDX-License-Identifier: GPL-2.0+
2//
3// Copyright 2013 Freescale Semiconductor, Inc.
4// Copyright 2020 NXP
5//
6// Freescale DSPI driver
7// This file contains a driver for the Freescale DSPI
8
9#include <linux/clk.h>
10#include <linux/delay.h>
11#include <linux/dmaengine.h>
12#include <linux/dma-mapping.h>
13#include <linux/interrupt.h>
14#include <linux/kernel.h>
15#include <linux/module.h>
16#include <linux/of_device.h>
17#include <linux/pinctrl/consumer.h>
18#include <linux/regmap.h>
19#include <linux/spi/spi.h>
20#include <linux/spi/spi-fsl-dspi.h>
21
22#define DRIVER_NAME "fsl-dspi"
23
24#define SPI_MCR 0x00
25#define SPI_MCR_MASTER BIT(31)
26#define SPI_MCR_PCSIS(x) ((x) << 16)
27#define SPI_MCR_CLR_TXF BIT(11)
28#define SPI_MCR_CLR_RXF BIT(10)
29#define SPI_MCR_XSPI BIT(3)
30#define SPI_MCR_DIS_TXF BIT(13)
31#define SPI_MCR_DIS_RXF BIT(12)
32#define SPI_MCR_HALT BIT(0)
33
34#define SPI_TCR 0x08
35#define SPI_TCR_GET_TCNT(x) (((x) & GENMASK(31, 16)) >> 16)
36
37#define SPI_CTAR(x) (0x0c + (((x) & GENMASK(1, 0)) * 4))
38#define SPI_CTAR_FMSZ(x) (((x) << 27) & GENMASK(30, 27))
39#define SPI_CTAR_CPOL BIT(26)
40#define SPI_CTAR_CPHA BIT(25)
41#define SPI_CTAR_LSBFE BIT(24)
42#define SPI_CTAR_PCSSCK(x) (((x) << 22) & GENMASK(23, 22))
43#define SPI_CTAR_PASC(x) (((x) << 20) & GENMASK(21, 20))
44#define SPI_CTAR_PDT(x) (((x) << 18) & GENMASK(19, 18))
45#define SPI_CTAR_PBR(x) (((x) << 16) & GENMASK(17, 16))
46#define SPI_CTAR_CSSCK(x) (((x) << 12) & GENMASK(15, 12))
47#define SPI_CTAR_ASC(x) (((x) << 8) & GENMASK(11, 8))
48#define SPI_CTAR_DT(x) (((x) << 4) & GENMASK(7, 4))
49#define SPI_CTAR_BR(x) ((x) & GENMASK(3, 0))
50#define SPI_CTAR_SCALE_BITS 0xf
51
52#define SPI_CTAR0_SLAVE 0x0c
53
54#define SPI_SR 0x2c
55#define SPI_SR_TCFQF BIT(31)
56#define SPI_SR_EOQF BIT(28)
57#define SPI_SR_TFUF BIT(27)
58#define SPI_SR_TFFF BIT(25)
59#define SPI_SR_CMDTCF BIT(23)
60#define SPI_SR_SPEF BIT(21)
61#define SPI_SR_RFOF BIT(19)
62#define SPI_SR_TFIWF BIT(18)
63#define SPI_SR_RFDF BIT(17)
64#define SPI_SR_CMDFFF BIT(16)
65#define SPI_SR_CLEAR (SPI_SR_TCFQF | SPI_SR_EOQF | \
66 SPI_SR_TFUF | SPI_SR_TFFF | \
67 SPI_SR_CMDTCF | SPI_SR_SPEF | \
68 SPI_SR_RFOF | SPI_SR_TFIWF | \
69 SPI_SR_RFDF | SPI_SR_CMDFFF)
70
71#define SPI_RSER_TFFFE BIT(25)
72#define SPI_RSER_TFFFD BIT(24)
73#define SPI_RSER_RFDFE BIT(17)
74#define SPI_RSER_RFDFD BIT(16)
75
76#define SPI_RSER 0x30
77#define SPI_RSER_TCFQE BIT(31)
78#define SPI_RSER_EOQFE BIT(28)
79#define SPI_RSER_CMDTCFE BIT(23)
80
81#define SPI_PUSHR 0x34
82#define SPI_PUSHR_CMD_CONT BIT(15)
83#define SPI_PUSHR_CMD_CTAS(x) (((x) << 12 & GENMASK(14, 12)))
84#define SPI_PUSHR_CMD_EOQ BIT(11)
85#define SPI_PUSHR_CMD_CTCNT BIT(10)
86#define SPI_PUSHR_CMD_PCS(x) (BIT(x) & GENMASK(5, 0))
87
88#define SPI_PUSHR_SLAVE 0x34
89
90#define SPI_POPR 0x38
91
92#define SPI_TXFR0 0x3c
93#define SPI_TXFR1 0x40
94#define SPI_TXFR2 0x44
95#define SPI_TXFR3 0x48
96#define SPI_RXFR0 0x7c
97#define SPI_RXFR1 0x80
98#define SPI_RXFR2 0x84
99#define SPI_RXFR3 0x88
100
101#define SPI_CTARE(x) (0x11c + (((x) & GENMASK(1, 0)) * 4))
102#define SPI_CTARE_FMSZE(x) (((x) & 0x1) << 16)
103#define SPI_CTARE_DTCP(x) ((x) & 0x7ff)
104
105#define SPI_SREX 0x13c
106
107#define SPI_FRAME_BITS(bits) SPI_CTAR_FMSZ((bits) - 1)
108#define SPI_FRAME_EBITS(bits) SPI_CTARE_FMSZE(((bits) - 1) >> 4)
109
110#define DMA_COMPLETION_TIMEOUT msecs_to_jiffies(3000)
111
112struct chip_data {
113 u32 ctar_val;
114};
115
116enum dspi_trans_mode {
117 DSPI_EOQ_MODE = 0,
118 DSPI_XSPI_MODE,
119 DSPI_DMA_MODE,
120};
121
122struct fsl_dspi_devtype_data {
123 enum dspi_trans_mode trans_mode;
124 u8 max_clock_factor;
125 int fifo_size;
126};
127
128enum {
129 LS1021A,
130 LS1012A,
131 LS1028A,
132 LS1043A,
133 LS1046A,
134 LS2080A,
135 LS2085A,
136 LX2160A,
137 MCF5441X,
138 VF610,
139};
140
141static const struct fsl_dspi_devtype_data devtype_data[] = {
142 [VF610] = {
143 .trans_mode = DSPI_DMA_MODE,
144 .max_clock_factor = 2,
145 .fifo_size = 4,
146 },
147 [LS1021A] = {
148 /* Has A-011218 DMA erratum */
149 .trans_mode = DSPI_XSPI_MODE,
150 .max_clock_factor = 8,
151 .fifo_size = 4,
152 },
153 [LS1012A] = {
154 /* Has A-011218 DMA erratum */
155 .trans_mode = DSPI_XSPI_MODE,
156 .max_clock_factor = 8,
157 .fifo_size = 16,
158 },
159 [LS1028A] = {
160 .trans_mode = DSPI_XSPI_MODE,
161 .max_clock_factor = 8,
162 .fifo_size = 4,
163 },
164 [LS1043A] = {
165 /* Has A-011218 DMA erratum */
166 .trans_mode = DSPI_XSPI_MODE,
167 .max_clock_factor = 8,
168 .fifo_size = 16,
169 },
170 [LS1046A] = {
171 /* Has A-011218 DMA erratum */
172 .trans_mode = DSPI_XSPI_MODE,
173 .max_clock_factor = 8,
174 .fifo_size = 16,
175 },
176 [LS2080A] = {
177 .trans_mode = DSPI_XSPI_MODE,
178 .max_clock_factor = 8,
179 .fifo_size = 4,
180 },
181 [LS2085A] = {
182 .trans_mode = DSPI_XSPI_MODE,
183 .max_clock_factor = 8,
184 .fifo_size = 4,
185 },
186 [LX2160A] = {
187 .trans_mode = DSPI_XSPI_MODE,
188 .max_clock_factor = 8,
189 .fifo_size = 4,
190 },
191 [MCF5441X] = {
192 .trans_mode = DSPI_EOQ_MODE,
193 .max_clock_factor = 8,
194 .fifo_size = 16,
195 },
196};
197
198struct fsl_dspi_dma {
199 u32 *tx_dma_buf;
200 struct dma_chan *chan_tx;
201 dma_addr_t tx_dma_phys;
202 struct completion cmd_tx_complete;
203 struct dma_async_tx_descriptor *tx_desc;
204
205 u32 *rx_dma_buf;
206 struct dma_chan *chan_rx;
207 dma_addr_t rx_dma_phys;
208 struct completion cmd_rx_complete;
209 struct dma_async_tx_descriptor *rx_desc;
210};
211
212struct fsl_dspi {
213 struct spi_controller *ctlr;
214 struct platform_device *pdev;
215
216 struct regmap *regmap;
217 struct regmap *regmap_pushr;
218 int irq;
219 struct clk *clk;
220
221 struct spi_transfer *cur_transfer;
222 struct spi_message *cur_msg;
223 struct chip_data *cur_chip;
224 size_t progress;
225 size_t len;
226 const void *tx;
227 void *rx;
228 u16 tx_cmd;
229 const struct fsl_dspi_devtype_data *devtype_data;
230
231 struct completion xfer_done;
232
233 struct fsl_dspi_dma *dma;
234
235 int oper_word_size;
236 int oper_bits_per_word;
237
238 int words_in_flight;
239
240 /*
241 * Offsets for CMD and TXDATA within SPI_PUSHR when accessed
242 * individually (in XSPI mode)
243 */
244 int pushr_cmd;
245 int pushr_tx;
246
247 void (*host_to_dev)(struct fsl_dspi *dspi, u32 *txdata);
248 void (*dev_to_host)(struct fsl_dspi *dspi, u32 rxdata);
249};
250
251static void dspi_native_host_to_dev(struct fsl_dspi *dspi, u32 *txdata)
252{
253 switch (dspi->oper_word_size) {
254 case 1:
255 *txdata = *(u8 *)dspi->tx;
256 break;
257 case 2:
258 *txdata = *(u16 *)dspi->tx;
259 break;
260 case 4:
261 *txdata = *(u32 *)dspi->tx;
262 break;
263 }
264 dspi->tx += dspi->oper_word_size;
265}
266
267static void dspi_native_dev_to_host(struct fsl_dspi *dspi, u32 rxdata)
268{
269 switch (dspi->oper_word_size) {
270 case 1:
271 *(u8 *)dspi->rx = rxdata;
272 break;
273 case 2:
274 *(u16 *)dspi->rx = rxdata;
275 break;
276 case 4:
277 *(u32 *)dspi->rx = rxdata;
278 break;
279 }
280 dspi->rx += dspi->oper_word_size;
281}
282
283static void dspi_8on32_host_to_dev(struct fsl_dspi *dspi, u32 *txdata)
284{
285 *txdata = cpu_to_be32(*(u32 *)dspi->tx);
286 dspi->tx += sizeof(u32);
287}
288
289static void dspi_8on32_dev_to_host(struct fsl_dspi *dspi, u32 rxdata)
290{
291 *(u32 *)dspi->rx = be32_to_cpu(rxdata);
292 dspi->rx += sizeof(u32);
293}
294
295static void dspi_8on16_host_to_dev(struct fsl_dspi *dspi, u32 *txdata)
296{
297 *txdata = cpu_to_be16(*(u16 *)dspi->tx);
298 dspi->tx += sizeof(u16);
299}
300
301static void dspi_8on16_dev_to_host(struct fsl_dspi *dspi, u32 rxdata)
302{
303 *(u16 *)dspi->rx = be16_to_cpu(rxdata);
304 dspi->rx += sizeof(u16);
305}
306
307static void dspi_16on32_host_to_dev(struct fsl_dspi *dspi, u32 *txdata)
308{
309 u16 hi = *(u16 *)dspi->tx;
310 u16 lo = *(u16 *)(dspi->tx + 2);
311
312 *txdata = (u32)hi << 16 | lo;
313 dspi->tx += sizeof(u32);
314}
315
316static void dspi_16on32_dev_to_host(struct fsl_dspi *dspi, u32 rxdata)
317{
318 u16 hi = rxdata & 0xffff;
319 u16 lo = rxdata >> 16;
320
321 *(u16 *)dspi->rx = lo;
322 *(u16 *)(dspi->rx + 2) = hi;
323 dspi->rx += sizeof(u32);
324}
325
326/*
327 * Pop one word from the TX buffer for pushing into the
328 * PUSHR register (TX FIFO)
329 */
330static u32 dspi_pop_tx(struct fsl_dspi *dspi)
331{
332 u32 txdata = 0;
333
334 if (dspi->tx)
335 dspi->host_to_dev(dspi, &txdata);
336 dspi->len -= dspi->oper_word_size;
337 return txdata;
338}
339
340/* Prepare one TX FIFO entry (txdata plus cmd) */
341static u32 dspi_pop_tx_pushr(struct fsl_dspi *dspi)
342{
343 u16 cmd = dspi->tx_cmd, data = dspi_pop_tx(dspi);
344
345 if (spi_controller_is_slave(dspi->ctlr))
346 return data;
347
348 if (dspi->len > 0)
349 cmd |= SPI_PUSHR_CMD_CONT;
350 return cmd << 16 | data;
351}
352
353/* Push one word to the RX buffer from the POPR register (RX FIFO) */
354static void dspi_push_rx(struct fsl_dspi *dspi, u32 rxdata)
355{
356 if (!dspi->rx)
357 return;
358 dspi->dev_to_host(dspi, rxdata);
359}
360
361static void dspi_tx_dma_callback(void *arg)
362{
363 struct fsl_dspi *dspi = arg;
364 struct fsl_dspi_dma *dma = dspi->dma;
365
366 complete(&dma->cmd_tx_complete);
367}
368
369static void dspi_rx_dma_callback(void *arg)
370{
371 struct fsl_dspi *dspi = arg;
372 struct fsl_dspi_dma *dma = dspi->dma;
373 int i;
374
375 if (dspi->rx) {
376 for (i = 0; i < dspi->words_in_flight; i++)
377 dspi_push_rx(dspi, dspi->dma->rx_dma_buf[i]);
378 }
379
380 complete(&dma->cmd_rx_complete);
381}
382
383static int dspi_next_xfer_dma_submit(struct fsl_dspi *dspi)
384{
385 struct device *dev = &dspi->pdev->dev;
386 struct fsl_dspi_dma *dma = dspi->dma;
387 int time_left;
388 int i;
389
390 for (i = 0; i < dspi->words_in_flight; i++)
391 dspi->dma->tx_dma_buf[i] = dspi_pop_tx_pushr(dspi);
392
393 dma->tx_desc = dmaengine_prep_slave_single(dma->chan_tx,
394 dma->tx_dma_phys,
395 dspi->words_in_flight *
396 DMA_SLAVE_BUSWIDTH_4_BYTES,
397 DMA_MEM_TO_DEV,
398 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
399 if (!dma->tx_desc) {
400 dev_err(dev, "Not able to get desc for DMA xfer\n");
401 return -EIO;
402 }
403
404 dma->tx_desc->callback = dspi_tx_dma_callback;
405 dma->tx_desc->callback_param = dspi;
406 if (dma_submit_error(dmaengine_submit(dma->tx_desc))) {
407 dev_err(dev, "DMA submit failed\n");
408 return -EINVAL;
409 }
410
411 dma->rx_desc = dmaengine_prep_slave_single(dma->chan_rx,
412 dma->rx_dma_phys,
413 dspi->words_in_flight *
414 DMA_SLAVE_BUSWIDTH_4_BYTES,
415 DMA_DEV_TO_MEM,
416 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
417 if (!dma->rx_desc) {
418 dev_err(dev, "Not able to get desc for DMA xfer\n");
419 return -EIO;
420 }
421
422 dma->rx_desc->callback = dspi_rx_dma_callback;
423 dma->rx_desc->callback_param = dspi;
424 if (dma_submit_error(dmaengine_submit(dma->rx_desc))) {
425 dev_err(dev, "DMA submit failed\n");
426 return -EINVAL;
427 }
428
429 reinit_completion(&dspi->dma->cmd_rx_complete);
430 reinit_completion(&dspi->dma->cmd_tx_complete);
431
432 dma_async_issue_pending(dma->chan_rx);
433 dma_async_issue_pending(dma->chan_tx);
434
435 if (spi_controller_is_slave(dspi->ctlr)) {
436 wait_for_completion_interruptible(&dspi->dma->cmd_rx_complete);
437 return 0;
438 }
439
440 time_left = wait_for_completion_timeout(&dspi->dma->cmd_tx_complete,
441 DMA_COMPLETION_TIMEOUT);
442 if (time_left == 0) {
443 dev_err(dev, "DMA tx timeout\n");
444 dmaengine_terminate_all(dma->chan_tx);
445 dmaengine_terminate_all(dma->chan_rx);
446 return -ETIMEDOUT;
447 }
448
449 time_left = wait_for_completion_timeout(&dspi->dma->cmd_rx_complete,
450 DMA_COMPLETION_TIMEOUT);
451 if (time_left == 0) {
452 dev_err(dev, "DMA rx timeout\n");
453 dmaengine_terminate_all(dma->chan_tx);
454 dmaengine_terminate_all(dma->chan_rx);
455 return -ETIMEDOUT;
456 }
457
458 return 0;
459}
460
461static void dspi_setup_accel(struct fsl_dspi *dspi);
462
463static int dspi_dma_xfer(struct fsl_dspi *dspi)
464{
465 struct spi_message *message = dspi->cur_msg;
466 struct device *dev = &dspi->pdev->dev;
467 int ret = 0;
468
469 /*
470 * dspi->len gets decremented by dspi_pop_tx_pushr in
471 * dspi_next_xfer_dma_submit
472 */
473 while (dspi->len) {
474 /* Figure out operational bits-per-word for this chunk */
475 dspi_setup_accel(dspi);
476
477 dspi->words_in_flight = dspi->len / dspi->oper_word_size;
478 if (dspi->words_in_flight > dspi->devtype_data->fifo_size)
479 dspi->words_in_flight = dspi->devtype_data->fifo_size;
480
481 message->actual_length += dspi->words_in_flight *
482 dspi->oper_word_size;
483
484 ret = dspi_next_xfer_dma_submit(dspi);
485 if (ret) {
486 dev_err(dev, "DMA transfer failed\n");
487 break;
488 }
489 }
490
491 return ret;
492}
493
494static int dspi_request_dma(struct fsl_dspi *dspi, phys_addr_t phy_addr)
495{
496 int dma_bufsize = dspi->devtype_data->fifo_size * 2;
497 struct device *dev = &dspi->pdev->dev;
498 struct dma_slave_config cfg;
499 struct fsl_dspi_dma *dma;
500 int ret;
501
502 dma = devm_kzalloc(dev, sizeof(*dma), GFP_KERNEL);
503 if (!dma)
504 return -ENOMEM;
505
506 dma->chan_rx = dma_request_chan(dev, "rx");
507 if (IS_ERR(dma->chan_rx)) {
508 dev_err(dev, "rx dma channel not available\n");
509 ret = PTR_ERR(dma->chan_rx);
510 return ret;
511 }
512
513 dma->chan_tx = dma_request_chan(dev, "tx");
514 if (IS_ERR(dma->chan_tx)) {
515 dev_err(dev, "tx dma channel not available\n");
516 ret = PTR_ERR(dma->chan_tx);
517 goto err_tx_channel;
518 }
519
520 dma->tx_dma_buf = dma_alloc_coherent(dma->chan_tx->device->dev,
521 dma_bufsize, &dma->tx_dma_phys,
522 GFP_KERNEL);
523 if (!dma->tx_dma_buf) {
524 ret = -ENOMEM;
525 goto err_tx_dma_buf;
526 }
527
528 dma->rx_dma_buf = dma_alloc_coherent(dma->chan_rx->device->dev,
529 dma_bufsize, &dma->rx_dma_phys,
530 GFP_KERNEL);
531 if (!dma->rx_dma_buf) {
532 ret = -ENOMEM;
533 goto err_rx_dma_buf;
534 }
535
536 cfg.src_addr = phy_addr + SPI_POPR;
537 cfg.dst_addr = phy_addr + SPI_PUSHR;
538 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
539 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
540 cfg.src_maxburst = 1;
541 cfg.dst_maxburst = 1;
542
543 cfg.direction = DMA_DEV_TO_MEM;
544 ret = dmaengine_slave_config(dma->chan_rx, &cfg);
545 if (ret) {
546 dev_err(dev, "can't configure rx dma channel\n");
547 ret = -EINVAL;
548 goto err_slave_config;
549 }
550
551 cfg.direction = DMA_MEM_TO_DEV;
552 ret = dmaengine_slave_config(dma->chan_tx, &cfg);
553 if (ret) {
554 dev_err(dev, "can't configure tx dma channel\n");
555 ret = -EINVAL;
556 goto err_slave_config;
557 }
558
559 dspi->dma = dma;
560 init_completion(&dma->cmd_tx_complete);
561 init_completion(&dma->cmd_rx_complete);
562
563 return 0;
564
565err_slave_config:
566 dma_free_coherent(dma->chan_rx->device->dev,
567 dma_bufsize, dma->rx_dma_buf, dma->rx_dma_phys);
568err_rx_dma_buf:
569 dma_free_coherent(dma->chan_tx->device->dev,
570 dma_bufsize, dma->tx_dma_buf, dma->tx_dma_phys);
571err_tx_dma_buf:
572 dma_release_channel(dma->chan_tx);
573err_tx_channel:
574 dma_release_channel(dma->chan_rx);
575
576 devm_kfree(dev, dma);
577 dspi->dma = NULL;
578
579 return ret;
580}
581
582static void dspi_release_dma(struct fsl_dspi *dspi)
583{
584 int dma_bufsize = dspi->devtype_data->fifo_size * 2;
585 struct fsl_dspi_dma *dma = dspi->dma;
586
587 if (!dma)
588 return;
589
590 if (dma->chan_tx) {
591 dma_free_coherent(dma->chan_tx->device->dev, dma_bufsize,
592 dma->tx_dma_buf, dma->tx_dma_phys);
593 dma_release_channel(dma->chan_tx);
594 }
595
596 if (dma->chan_rx) {
597 dma_free_coherent(dma->chan_rx->device->dev, dma_bufsize,
598 dma->rx_dma_buf, dma->rx_dma_phys);
599 dma_release_channel(dma->chan_rx);
600 }
601}
602
603static void hz_to_spi_baud(char *pbr, char *br, int speed_hz,
604 unsigned long clkrate)
605{
606 /* Valid baud rate pre-scaler values */
607 int pbr_tbl[4] = {2, 3, 5, 7};
608 int brs[16] = { 2, 4, 6, 8,
609 16, 32, 64, 128,
610 256, 512, 1024, 2048,
611 4096, 8192, 16384, 32768 };
612 int scale_needed, scale, minscale = INT_MAX;
613 int i, j;
614
615 scale_needed = clkrate / speed_hz;
616 if (clkrate % speed_hz)
617 scale_needed++;
618
619 for (i = 0; i < ARRAY_SIZE(brs); i++)
620 for (j = 0; j < ARRAY_SIZE(pbr_tbl); j++) {
621 scale = brs[i] * pbr_tbl[j];
622 if (scale >= scale_needed) {
623 if (scale < minscale) {
624 minscale = scale;
625 *br = i;
626 *pbr = j;
627 }
628 break;
629 }
630 }
631
632 if (minscale == INT_MAX) {
633 pr_warn("Can not find valid baud rate,speed_hz is %d,clkrate is %ld, we use the max prescaler value.\n",
634 speed_hz, clkrate);
635 *pbr = ARRAY_SIZE(pbr_tbl) - 1;
636 *br = ARRAY_SIZE(brs) - 1;
637 }
638}
639
640static void ns_delay_scale(char *psc, char *sc, int delay_ns,
641 unsigned long clkrate)
642{
643 int scale_needed, scale, minscale = INT_MAX;
644 int pscale_tbl[4] = {1, 3, 5, 7};
645 u32 remainder;
646 int i, j;
647
648 scale_needed = div_u64_rem((u64)delay_ns * clkrate, NSEC_PER_SEC,
649 &remainder);
650 if (remainder)
651 scale_needed++;
652
653 for (i = 0; i < ARRAY_SIZE(pscale_tbl); i++)
654 for (j = 0; j <= SPI_CTAR_SCALE_BITS; j++) {
655 scale = pscale_tbl[i] * (2 << j);
656 if (scale >= scale_needed) {
657 if (scale < minscale) {
658 minscale = scale;
659 *psc = i;
660 *sc = j;
661 }
662 break;
663 }
664 }
665
666 if (minscale == INT_MAX) {
667 pr_warn("Cannot find correct scale values for %dns delay at clkrate %ld, using max prescaler value",
668 delay_ns, clkrate);
669 *psc = ARRAY_SIZE(pscale_tbl) - 1;
670 *sc = SPI_CTAR_SCALE_BITS;
671 }
672}
673
674static void dspi_pushr_write(struct fsl_dspi *dspi)
675{
676 regmap_write(dspi->regmap, SPI_PUSHR, dspi_pop_tx_pushr(dspi));
677}
678
679static void dspi_pushr_cmd_write(struct fsl_dspi *dspi, u16 cmd)
680{
681 /*
682 * The only time when the PCS doesn't need continuation after this word
683 * is when it's last. We need to look ahead, because we actually call
684 * dspi_pop_tx (the function that decrements dspi->len) _after_
685 * dspi_pushr_cmd_write with XSPI mode. As for how much in advance? One
686 * word is enough. If there's more to transmit than that,
687 * dspi_xspi_write will know to split the FIFO writes in 2, and
688 * generate a new PUSHR command with the final word that will have PCS
689 * deasserted (not continued) here.
690 */
691 if (dspi->len > dspi->oper_word_size)
692 cmd |= SPI_PUSHR_CMD_CONT;
693 regmap_write(dspi->regmap_pushr, dspi->pushr_cmd, cmd);
694}
695
696static void dspi_pushr_txdata_write(struct fsl_dspi *dspi, u16 txdata)
697{
698 regmap_write(dspi->regmap_pushr, dspi->pushr_tx, txdata);
699}
700
701static void dspi_xspi_fifo_write(struct fsl_dspi *dspi, int num_words)
702{
703 int num_bytes = num_words * dspi->oper_word_size;
704 u16 tx_cmd = dspi->tx_cmd;
705
706 /*
707 * If the PCS needs to de-assert (i.e. we're at the end of the buffer
708 * and cs_change does not want the PCS to stay on), then we need a new
709 * PUSHR command, since this one (for the body of the buffer)
710 * necessarily has the CONT bit set.
711 * So send one word less during this go, to force a split and a command
712 * with a single word next time, when CONT will be unset.
713 */
714 if (!(dspi->tx_cmd & SPI_PUSHR_CMD_CONT) && num_bytes == dspi->len)
715 tx_cmd |= SPI_PUSHR_CMD_EOQ;
716
717 /* Update CTARE */
718 regmap_write(dspi->regmap, SPI_CTARE(0),
719 SPI_FRAME_EBITS(dspi->oper_bits_per_word) |
720 SPI_CTARE_DTCP(num_words));
721
722 /*
723 * Write the CMD FIFO entry first, and then the two
724 * corresponding TX FIFO entries (or one...).
725 */
726 dspi_pushr_cmd_write(dspi, tx_cmd);
727
728 /* Fill TX FIFO with as many transfers as possible */
729 while (num_words--) {
730 u32 data = dspi_pop_tx(dspi);
731
732 dspi_pushr_txdata_write(dspi, data & 0xFFFF);
733 if (dspi->oper_bits_per_word > 16)
734 dspi_pushr_txdata_write(dspi, data >> 16);
735 }
736}
737
738static void dspi_eoq_fifo_write(struct fsl_dspi *dspi, int num_words)
739{
740 u16 xfer_cmd = dspi->tx_cmd;
741
742 /* Fill TX FIFO with as many transfers as possible */
743 while (num_words--) {
744 dspi->tx_cmd = xfer_cmd;
745 /* Request EOQF for last transfer in FIFO */
746 if (num_words == 0)
747 dspi->tx_cmd |= SPI_PUSHR_CMD_EOQ;
748 /* Write combined TX FIFO and CMD FIFO entry */
749 dspi_pushr_write(dspi);
750 }
751}
752
753static u32 dspi_popr_read(struct fsl_dspi *dspi)
754{
755 u32 rxdata = 0;
756
757 regmap_read(dspi->regmap, SPI_POPR, &rxdata);
758 return rxdata;
759}
760
761static void dspi_fifo_read(struct fsl_dspi *dspi)
762{
763 int num_fifo_entries = dspi->words_in_flight;
764
765 /* Read one FIFO entry and push to rx buffer */
766 while (num_fifo_entries--)
767 dspi_push_rx(dspi, dspi_popr_read(dspi));
768}
769
770static void dspi_setup_accel(struct fsl_dspi *dspi)
771{
772 struct spi_transfer *xfer = dspi->cur_transfer;
773 bool odd = !!(dspi->len & 1);
774
775 /* No accel for frames not multiple of 8 bits at the moment */
776 if (xfer->bits_per_word % 8)
777 goto no_accel;
778
779 if (!odd && dspi->len <= dspi->devtype_data->fifo_size * 2) {
780 dspi->oper_bits_per_word = 16;
781 } else if (odd && dspi->len <= dspi->devtype_data->fifo_size) {
782 dspi->oper_bits_per_word = 8;
783 } else {
784 /* Start off with maximum supported by hardware */
785 if (dspi->devtype_data->trans_mode == DSPI_XSPI_MODE)
786 dspi->oper_bits_per_word = 32;
787 else
788 dspi->oper_bits_per_word = 16;
789
790 /*
791 * And go down only if the buffer can't be sent with
792 * words this big
793 */
794 do {
795 if (dspi->len >= DIV_ROUND_UP(dspi->oper_bits_per_word, 8))
796 break;
797
798 dspi->oper_bits_per_word /= 2;
799 } while (dspi->oper_bits_per_word > 8);
800 }
801
802 if (xfer->bits_per_word == 8 && dspi->oper_bits_per_word == 32) {
803 dspi->dev_to_host = dspi_8on32_dev_to_host;
804 dspi->host_to_dev = dspi_8on32_host_to_dev;
805 } else if (xfer->bits_per_word == 8 && dspi->oper_bits_per_word == 16) {
806 dspi->dev_to_host = dspi_8on16_dev_to_host;
807 dspi->host_to_dev = dspi_8on16_host_to_dev;
808 } else if (xfer->bits_per_word == 16 && dspi->oper_bits_per_word == 32) {
809 dspi->dev_to_host = dspi_16on32_dev_to_host;
810 dspi->host_to_dev = dspi_16on32_host_to_dev;
811 } else {
812no_accel:
813 dspi->dev_to_host = dspi_native_dev_to_host;
814 dspi->host_to_dev = dspi_native_host_to_dev;
815 dspi->oper_bits_per_word = xfer->bits_per_word;
816 }
817
818 dspi->oper_word_size = DIV_ROUND_UP(dspi->oper_bits_per_word, 8);
819
820 /*
821 * Update CTAR here (code is common for EOQ, XSPI and DMA modes).
822 * We will update CTARE in the portion specific to XSPI, when we
823 * also know the preload value (DTCP).
824 */
825 regmap_write(dspi->regmap, SPI_CTAR(0),
826 dspi->cur_chip->ctar_val |
827 SPI_FRAME_BITS(dspi->oper_bits_per_word));
828}
829
830static void dspi_fifo_write(struct fsl_dspi *dspi)
831{
832 int num_fifo_entries = dspi->devtype_data->fifo_size;
833 struct spi_transfer *xfer = dspi->cur_transfer;
834 struct spi_message *msg = dspi->cur_msg;
835 int num_words, num_bytes;
836
837 dspi_setup_accel(dspi);
838
839 /* In XSPI mode each 32-bit word occupies 2 TX FIFO entries */
840 if (dspi->oper_word_size == 4)
841 num_fifo_entries /= 2;
842
843 /*
844 * Integer division intentionally trims off odd (or non-multiple of 4)
845 * numbers of bytes at the end of the buffer, which will be sent next
846 * time using a smaller oper_word_size.
847 */
848 num_words = dspi->len / dspi->oper_word_size;
849 if (num_words > num_fifo_entries)
850 num_words = num_fifo_entries;
851
852 /* Update total number of bytes that were transferred */
853 num_bytes = num_words * dspi->oper_word_size;
854 msg->actual_length += num_bytes;
855 dspi->progress += num_bytes / DIV_ROUND_UP(xfer->bits_per_word, 8);
856
857 /*
858 * Update shared variable for use in the next interrupt (both in
859 * dspi_fifo_read and in dspi_fifo_write).
860 */
861 dspi->words_in_flight = num_words;
862
863 spi_take_timestamp_pre(dspi->ctlr, xfer, dspi->progress, !dspi->irq);
864
865 if (dspi->devtype_data->trans_mode == DSPI_EOQ_MODE)
866 dspi_eoq_fifo_write(dspi, num_words);
867 else
868 dspi_xspi_fifo_write(dspi, num_words);
869 /*
870 * Everything after this point is in a potential race with the next
871 * interrupt, so we must never use dspi->words_in_flight again since it
872 * might already be modified by the next dspi_fifo_write.
873 */
874
875 spi_take_timestamp_post(dspi->ctlr, dspi->cur_transfer,
876 dspi->progress, !dspi->irq);
877}
878
879static int dspi_rxtx(struct fsl_dspi *dspi)
880{
881 dspi_fifo_read(dspi);
882
883 if (!dspi->len)
884 /* Success! */
885 return 0;
886
887 dspi_fifo_write(dspi);
888
889 return -EINPROGRESS;
890}
891
892static int dspi_poll(struct fsl_dspi *dspi)
893{
894 int tries = 1000;
895 u32 spi_sr;
896
897 do {
898 regmap_read(dspi->regmap, SPI_SR, &spi_sr);
899 regmap_write(dspi->regmap, SPI_SR, spi_sr);
900
901 if (spi_sr & (SPI_SR_EOQF | SPI_SR_CMDTCF))
902 break;
903 } while (--tries);
904
905 if (!tries)
906 return -ETIMEDOUT;
907
908 return dspi_rxtx(dspi);
909}
910
911static irqreturn_t dspi_interrupt(int irq, void *dev_id)
912{
913 struct fsl_dspi *dspi = (struct fsl_dspi *)dev_id;
914 u32 spi_sr;
915
916 regmap_read(dspi->regmap, SPI_SR, &spi_sr);
917 regmap_write(dspi->regmap, SPI_SR, spi_sr);
918
919 if (!(spi_sr & (SPI_SR_EOQF | SPI_SR_CMDTCF)))
920 return IRQ_NONE;
921
922 if (dspi_rxtx(dspi) == 0)
923 complete(&dspi->xfer_done);
924
925 return IRQ_HANDLED;
926}
927
928static int dspi_transfer_one_message(struct spi_controller *ctlr,
929 struct spi_message *message)
930{
931 struct fsl_dspi *dspi = spi_controller_get_devdata(ctlr);
932 struct spi_device *spi = message->spi;
933 struct spi_transfer *transfer;
934 int status = 0;
935
936 message->actual_length = 0;
937
938 list_for_each_entry(transfer, &message->transfers, transfer_list) {
939 dspi->cur_transfer = transfer;
940 dspi->cur_msg = message;
941 dspi->cur_chip = spi_get_ctldata(spi);
942 /* Prepare command word for CMD FIFO */
943 dspi->tx_cmd = SPI_PUSHR_CMD_CTAS(0) |
944 SPI_PUSHR_CMD_PCS(spi->chip_select);
945 if (list_is_last(&dspi->cur_transfer->transfer_list,
946 &dspi->cur_msg->transfers)) {
947 /* Leave PCS activated after last transfer when
948 * cs_change is set.
949 */
950 if (transfer->cs_change)
951 dspi->tx_cmd |= SPI_PUSHR_CMD_CONT;
952 } else {
953 /* Keep PCS active between transfers in same message
954 * when cs_change is not set, and de-activate PCS
955 * between transfers in the same message when
956 * cs_change is set.
957 */
958 if (!transfer->cs_change)
959 dspi->tx_cmd |= SPI_PUSHR_CMD_CONT;
960 }
961
962 dspi->tx = transfer->tx_buf;
963 dspi->rx = transfer->rx_buf;
964 dspi->len = transfer->len;
965 dspi->progress = 0;
966
967 regmap_update_bits(dspi->regmap, SPI_MCR,
968 SPI_MCR_CLR_TXF | SPI_MCR_CLR_RXF,
969 SPI_MCR_CLR_TXF | SPI_MCR_CLR_RXF);
970
971 spi_take_timestamp_pre(dspi->ctlr, dspi->cur_transfer,
972 dspi->progress, !dspi->irq);
973
974 if (dspi->devtype_data->trans_mode == DSPI_DMA_MODE) {
975 status = dspi_dma_xfer(dspi);
976 } else {
977 dspi_fifo_write(dspi);
978
979 if (dspi->irq) {
980 wait_for_completion(&dspi->xfer_done);
981 reinit_completion(&dspi->xfer_done);
982 } else {
983 do {
984 status = dspi_poll(dspi);
985 } while (status == -EINPROGRESS);
986 }
987 }
988 if (status)
989 break;
990
991 spi_transfer_delay_exec(transfer);
992 }
993
994 message->status = status;
995 spi_finalize_current_message(ctlr);
996
997 return status;
998}
999
1000static int dspi_setup(struct spi_device *spi)
1001{
1002 struct fsl_dspi *dspi = spi_controller_get_devdata(spi->controller);
1003 unsigned char br = 0, pbr = 0, pcssck = 0, cssck = 0;
1004 u32 cs_sck_delay = 0, sck_cs_delay = 0;
1005 struct fsl_dspi_platform_data *pdata;
1006 unsigned char pasc = 0, asc = 0;
1007 struct chip_data *chip;
1008 unsigned long clkrate;
1009
1010 /* Only alloc on first setup */
1011 chip = spi_get_ctldata(spi);
1012 if (chip == NULL) {
1013 chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL);
1014 if (!chip)
1015 return -ENOMEM;
1016 }
1017
1018 pdata = dev_get_platdata(&dspi->pdev->dev);
1019
1020 if (!pdata) {
1021 of_property_read_u32(spi->dev.of_node, "fsl,spi-cs-sck-delay",
1022 &cs_sck_delay);
1023
1024 of_property_read_u32(spi->dev.of_node, "fsl,spi-sck-cs-delay",
1025 &sck_cs_delay);
1026 } else {
1027 cs_sck_delay = pdata->cs_sck_delay;
1028 sck_cs_delay = pdata->sck_cs_delay;
1029 }
1030
1031 clkrate = clk_get_rate(dspi->clk);
1032 hz_to_spi_baud(&pbr, &br, spi->max_speed_hz, clkrate);
1033
1034 /* Set PCS to SCK delay scale values */
1035 ns_delay_scale(&pcssck, &cssck, cs_sck_delay, clkrate);
1036
1037 /* Set After SCK delay scale values */
1038 ns_delay_scale(&pasc, &asc, sck_cs_delay, clkrate);
1039
1040 chip->ctar_val = 0;
1041 if (spi->mode & SPI_CPOL)
1042 chip->ctar_val |= SPI_CTAR_CPOL;
1043 if (spi->mode & SPI_CPHA)
1044 chip->ctar_val |= SPI_CTAR_CPHA;
1045
1046 if (!spi_controller_is_slave(dspi->ctlr)) {
1047 chip->ctar_val |= SPI_CTAR_PCSSCK(pcssck) |
1048 SPI_CTAR_CSSCK(cssck) |
1049 SPI_CTAR_PASC(pasc) |
1050 SPI_CTAR_ASC(asc) |
1051 SPI_CTAR_PBR(pbr) |
1052 SPI_CTAR_BR(br);
1053
1054 if (spi->mode & SPI_LSB_FIRST)
1055 chip->ctar_val |= SPI_CTAR_LSBFE;
1056 }
1057
1058 spi_set_ctldata(spi, chip);
1059
1060 return 0;
1061}
1062
1063static void dspi_cleanup(struct spi_device *spi)
1064{
1065 struct chip_data *chip = spi_get_ctldata((struct spi_device *)spi);
1066
1067 dev_dbg(&spi->dev, "spi_device %u.%u cleanup\n",
1068 spi->controller->bus_num, spi->chip_select);
1069
1070 kfree(chip);
1071}
1072
1073static const struct of_device_id fsl_dspi_dt_ids[] = {
1074 {
1075 .compatible = "fsl,vf610-dspi",
1076 .data = &devtype_data[VF610],
1077 }, {
1078 .compatible = "fsl,ls1021a-v1.0-dspi",
1079 .data = &devtype_data[LS1021A],
1080 }, {
1081 .compatible = "fsl,ls1012a-dspi",
1082 .data = &devtype_data[LS1012A],
1083 }, {
1084 .compatible = "fsl,ls1028a-dspi",
1085 .data = &devtype_data[LS1028A],
1086 }, {
1087 .compatible = "fsl,ls1043a-dspi",
1088 .data = &devtype_data[LS1043A],
1089 }, {
1090 .compatible = "fsl,ls1046a-dspi",
1091 .data = &devtype_data[LS1046A],
1092 }, {
1093 .compatible = "fsl,ls2080a-dspi",
1094 .data = &devtype_data[LS2080A],
1095 }, {
1096 .compatible = "fsl,ls2085a-dspi",
1097 .data = &devtype_data[LS2085A],
1098 }, {
1099 .compatible = "fsl,lx2160a-dspi",
1100 .data = &devtype_data[LX2160A],
1101 },
1102 { /* sentinel */ }
1103};
1104MODULE_DEVICE_TABLE(of, fsl_dspi_dt_ids);
1105
1106#ifdef CONFIG_PM_SLEEP
1107static int dspi_suspend(struct device *dev)
1108{
1109 struct spi_controller *ctlr = dev_get_drvdata(dev);
1110 struct fsl_dspi *dspi = spi_controller_get_devdata(ctlr);
1111
1112 if (dspi->irq)
1113 disable_irq(dspi->irq);
1114 spi_controller_suspend(ctlr);
1115 clk_disable_unprepare(dspi->clk);
1116
1117 pinctrl_pm_select_sleep_state(dev);
1118
1119 return 0;
1120}
1121
1122static int dspi_resume(struct device *dev)
1123{
1124 struct spi_controller *ctlr = dev_get_drvdata(dev);
1125 struct fsl_dspi *dspi = spi_controller_get_devdata(ctlr);
1126 int ret;
1127
1128 pinctrl_pm_select_default_state(dev);
1129
1130 ret = clk_prepare_enable(dspi->clk);
1131 if (ret)
1132 return ret;
1133 spi_controller_resume(ctlr);
1134 if (dspi->irq)
1135 enable_irq(dspi->irq);
1136
1137 return 0;
1138}
1139#endif /* CONFIG_PM_SLEEP */
1140
1141static SIMPLE_DEV_PM_OPS(dspi_pm, dspi_suspend, dspi_resume);
1142
1143static const struct regmap_range dspi_volatile_ranges[] = {
1144 regmap_reg_range(SPI_MCR, SPI_TCR),
1145 regmap_reg_range(SPI_SR, SPI_SR),
1146 regmap_reg_range(SPI_PUSHR, SPI_RXFR3),
1147};
1148
1149static const struct regmap_access_table dspi_volatile_table = {
1150 .yes_ranges = dspi_volatile_ranges,
1151 .n_yes_ranges = ARRAY_SIZE(dspi_volatile_ranges),
1152};
1153
1154static const struct regmap_config dspi_regmap_config = {
1155 .reg_bits = 32,
1156 .val_bits = 32,
1157 .reg_stride = 4,
1158 .max_register = 0x88,
1159 .volatile_table = &dspi_volatile_table,
1160};
1161
1162static const struct regmap_range dspi_xspi_volatile_ranges[] = {
1163 regmap_reg_range(SPI_MCR, SPI_TCR),
1164 regmap_reg_range(SPI_SR, SPI_SR),
1165 regmap_reg_range(SPI_PUSHR, SPI_RXFR3),
1166 regmap_reg_range(SPI_SREX, SPI_SREX),
1167};
1168
1169static const struct regmap_access_table dspi_xspi_volatile_table = {
1170 .yes_ranges = dspi_xspi_volatile_ranges,
1171 .n_yes_ranges = ARRAY_SIZE(dspi_xspi_volatile_ranges),
1172};
1173
1174static const struct regmap_config dspi_xspi_regmap_config[] = {
1175 {
1176 .reg_bits = 32,
1177 .val_bits = 32,
1178 .reg_stride = 4,
1179 .max_register = 0x13c,
1180 .volatile_table = &dspi_xspi_volatile_table,
1181 },
1182 {
1183 .name = "pushr",
1184 .reg_bits = 16,
1185 .val_bits = 16,
1186 .reg_stride = 2,
1187 .max_register = 0x2,
1188 },
1189};
1190
1191static int dspi_init(struct fsl_dspi *dspi)
1192{
1193 unsigned int mcr;
1194
1195 /* Set idle states for all chip select signals to high */
1196 mcr = SPI_MCR_PCSIS(GENMASK(dspi->ctlr->num_chipselect - 1, 0));
1197
1198 if (dspi->devtype_data->trans_mode == DSPI_XSPI_MODE)
1199 mcr |= SPI_MCR_XSPI;
1200 if (!spi_controller_is_slave(dspi->ctlr))
1201 mcr |= SPI_MCR_MASTER;
1202
1203 regmap_write(dspi->regmap, SPI_MCR, mcr);
1204 regmap_write(dspi->regmap, SPI_SR, SPI_SR_CLEAR);
1205
1206 switch (dspi->devtype_data->trans_mode) {
1207 case DSPI_EOQ_MODE:
1208 regmap_write(dspi->regmap, SPI_RSER, SPI_RSER_EOQFE);
1209 break;
1210 case DSPI_XSPI_MODE:
1211 regmap_write(dspi->regmap, SPI_RSER, SPI_RSER_CMDTCFE);
1212 break;
1213 case DSPI_DMA_MODE:
1214 regmap_write(dspi->regmap, SPI_RSER,
1215 SPI_RSER_TFFFE | SPI_RSER_TFFFD |
1216 SPI_RSER_RFDFE | SPI_RSER_RFDFD);
1217 break;
1218 default:
1219 dev_err(&dspi->pdev->dev, "unsupported trans_mode %u\n",
1220 dspi->devtype_data->trans_mode);
1221 return -EINVAL;
1222 }
1223
1224 return 0;
1225}
1226
1227static int dspi_slave_abort(struct spi_master *master)
1228{
1229 struct fsl_dspi *dspi = spi_master_get_devdata(master);
1230
1231 /*
1232 * Terminate all pending DMA transactions for the SPI working
1233 * in SLAVE mode.
1234 */
1235 if (dspi->devtype_data->trans_mode == DSPI_DMA_MODE) {
1236 dmaengine_terminate_sync(dspi->dma->chan_rx);
1237 dmaengine_terminate_sync(dspi->dma->chan_tx);
1238 }
1239
1240 /* Clear the internal DSPI RX and TX FIFO buffers */
1241 regmap_update_bits(dspi->regmap, SPI_MCR,
1242 SPI_MCR_CLR_TXF | SPI_MCR_CLR_RXF,
1243 SPI_MCR_CLR_TXF | SPI_MCR_CLR_RXF);
1244
1245 return 0;
1246}
1247
1248/*
1249 * EOQ mode will inevitably deassert its PCS signal on last word in a queue
1250 * (hardware limitation), so we need to inform the spi_device that larger
1251 * buffers than the FIFO size are going to have the chip select randomly
1252 * toggling, so it has a chance to adapt its message sizes.
1253 */
1254static size_t dspi_max_message_size(struct spi_device *spi)
1255{
1256 struct fsl_dspi *dspi = spi_controller_get_devdata(spi->controller);
1257
1258 if (dspi->devtype_data->trans_mode == DSPI_EOQ_MODE)
1259 return dspi->devtype_data->fifo_size;
1260
1261 return SIZE_MAX;
1262}
1263
1264static int dspi_probe(struct platform_device *pdev)
1265{
1266 struct device_node *np = pdev->dev.of_node;
1267 const struct regmap_config *regmap_config;
1268 struct fsl_dspi_platform_data *pdata;
1269 struct spi_controller *ctlr;
1270 int ret, cs_num, bus_num = -1;
1271 struct fsl_dspi *dspi;
1272 struct resource *res;
1273 void __iomem *base;
1274 bool big_endian;
1275
1276 dspi = devm_kzalloc(&pdev->dev, sizeof(*dspi), GFP_KERNEL);
1277 if (!dspi)
1278 return -ENOMEM;
1279
1280 ctlr = spi_alloc_master(&pdev->dev, 0);
1281 if (!ctlr)
1282 return -ENOMEM;
1283
1284 spi_controller_set_devdata(ctlr, dspi);
1285 platform_set_drvdata(pdev, dspi);
1286
1287 dspi->pdev = pdev;
1288 dspi->ctlr = ctlr;
1289
1290 ctlr->setup = dspi_setup;
1291 ctlr->transfer_one_message = dspi_transfer_one_message;
1292 ctlr->max_message_size = dspi_max_message_size;
1293 ctlr->dev.of_node = pdev->dev.of_node;
1294
1295 ctlr->cleanup = dspi_cleanup;
1296 ctlr->slave_abort = dspi_slave_abort;
1297 ctlr->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST;
1298
1299 pdata = dev_get_platdata(&pdev->dev);
1300 if (pdata) {
1301 ctlr->num_chipselect = pdata->cs_num;
1302 ctlr->bus_num = pdata->bus_num;
1303
1304 /* Only Coldfire uses platform data */
1305 dspi->devtype_data = &devtype_data[MCF5441X];
1306 big_endian = true;
1307 } else {
1308
1309 ret = of_property_read_u32(np, "spi-num-chipselects", &cs_num);
1310 if (ret < 0) {
1311 dev_err(&pdev->dev, "can't get spi-num-chipselects\n");
1312 goto out_ctlr_put;
1313 }
1314 ctlr->num_chipselect = cs_num;
1315
1316 of_property_read_u32(np, "bus-num", &bus_num);
1317 ctlr->bus_num = bus_num;
1318
1319 if (of_property_read_bool(np, "spi-slave"))
1320 ctlr->slave = true;
1321
1322 dspi->devtype_data = of_device_get_match_data(&pdev->dev);
1323 if (!dspi->devtype_data) {
1324 dev_err(&pdev->dev, "can't get devtype_data\n");
1325 ret = -EFAULT;
1326 goto out_ctlr_put;
1327 }
1328
1329 big_endian = of_device_is_big_endian(np);
1330 }
1331 if (big_endian) {
1332 dspi->pushr_cmd = 0;
1333 dspi->pushr_tx = 2;
1334 } else {
1335 dspi->pushr_cmd = 2;
1336 dspi->pushr_tx = 0;
1337 }
1338
1339 if (dspi->devtype_data->trans_mode == DSPI_XSPI_MODE)
1340 ctlr->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32);
1341 else
1342 ctlr->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 16);
1343
1344 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1345 base = devm_ioremap_resource(&pdev->dev, res);
1346 if (IS_ERR(base)) {
1347 ret = PTR_ERR(base);
1348 goto out_ctlr_put;
1349 }
1350
1351 if (dspi->devtype_data->trans_mode == DSPI_XSPI_MODE)
1352 regmap_config = &dspi_xspi_regmap_config[0];
1353 else
1354 regmap_config = &dspi_regmap_config;
1355 dspi->regmap = devm_regmap_init_mmio(&pdev->dev, base, regmap_config);
1356 if (IS_ERR(dspi->regmap)) {
1357 dev_err(&pdev->dev, "failed to init regmap: %ld\n",
1358 PTR_ERR(dspi->regmap));
1359 ret = PTR_ERR(dspi->regmap);
1360 goto out_ctlr_put;
1361 }
1362
1363 if (dspi->devtype_data->trans_mode == DSPI_XSPI_MODE) {
1364 dspi->regmap_pushr = devm_regmap_init_mmio(
1365 &pdev->dev, base + SPI_PUSHR,
1366 &dspi_xspi_regmap_config[1]);
1367 if (IS_ERR(dspi->regmap_pushr)) {
1368 dev_err(&pdev->dev,
1369 "failed to init pushr regmap: %ld\n",
1370 PTR_ERR(dspi->regmap_pushr));
1371 ret = PTR_ERR(dspi->regmap_pushr);
1372 goto out_ctlr_put;
1373 }
1374 }
1375
1376 dspi->clk = devm_clk_get(&pdev->dev, "dspi");
1377 if (IS_ERR(dspi->clk)) {
1378 ret = PTR_ERR(dspi->clk);
1379 dev_err(&pdev->dev, "unable to get clock\n");
1380 goto out_ctlr_put;
1381 }
1382 ret = clk_prepare_enable(dspi->clk);
1383 if (ret)
1384 goto out_ctlr_put;
1385
1386 ret = dspi_init(dspi);
1387 if (ret)
1388 goto out_clk_put;
1389
1390 dspi->irq = platform_get_irq(pdev, 0);
1391 if (dspi->irq <= 0) {
1392 dev_info(&pdev->dev,
1393 "can't get platform irq, using poll mode\n");
1394 dspi->irq = 0;
1395 goto poll_mode;
1396 }
1397
1398 init_completion(&dspi->xfer_done);
1399
1400 ret = request_threaded_irq(dspi->irq, dspi_interrupt, NULL,
1401 IRQF_SHARED, pdev->name, dspi);
1402 if (ret < 0) {
1403 dev_err(&pdev->dev, "Unable to attach DSPI interrupt\n");
1404 goto out_clk_put;
1405 }
1406
1407poll_mode:
1408
1409 if (dspi->devtype_data->trans_mode == DSPI_DMA_MODE) {
1410 ret = dspi_request_dma(dspi, res->start);
1411 if (ret < 0) {
1412 dev_err(&pdev->dev, "can't get dma channels\n");
1413 goto out_free_irq;
1414 }
1415 }
1416
1417 ctlr->max_speed_hz =
1418 clk_get_rate(dspi->clk) / dspi->devtype_data->max_clock_factor;
1419
1420 if (dspi->devtype_data->trans_mode != DSPI_DMA_MODE)
1421 ctlr->ptp_sts_supported = true;
1422
1423 ret = spi_register_controller(ctlr);
1424 if (ret != 0) {
1425 dev_err(&pdev->dev, "Problem registering DSPI ctlr\n");
1426 goto out_free_irq;
1427 }
1428
1429 return ret;
1430
1431out_free_irq:
1432 if (dspi->irq)
1433 free_irq(dspi->irq, dspi);
1434out_clk_put:
1435 clk_disable_unprepare(dspi->clk);
1436out_ctlr_put:
1437 spi_controller_put(ctlr);
1438
1439 return ret;
1440}
1441
1442static int dspi_remove(struct platform_device *pdev)
1443{
1444 struct fsl_dspi *dspi = platform_get_drvdata(pdev);
1445
1446 /* Disconnect from the SPI framework */
1447 spi_unregister_controller(dspi->ctlr);
1448
1449 /* Disable RX and TX */
1450 regmap_update_bits(dspi->regmap, SPI_MCR,
1451 SPI_MCR_DIS_TXF | SPI_MCR_DIS_RXF,
1452 SPI_MCR_DIS_TXF | SPI_MCR_DIS_RXF);
1453
1454 /* Stop Running */
1455 regmap_update_bits(dspi->regmap, SPI_MCR, SPI_MCR_HALT, SPI_MCR_HALT);
1456
1457 dspi_release_dma(dspi);
1458 if (dspi->irq)
1459 free_irq(dspi->irq, dspi);
1460 clk_disable_unprepare(dspi->clk);
1461
1462 return 0;
1463}
1464
1465static void dspi_shutdown(struct platform_device *pdev)
1466{
1467 dspi_remove(pdev);
1468}
1469
1470static struct platform_driver fsl_dspi_driver = {
1471 .driver.name = DRIVER_NAME,
1472 .driver.of_match_table = fsl_dspi_dt_ids,
1473 .driver.owner = THIS_MODULE,
1474 .driver.pm = &dspi_pm,
1475 .probe = dspi_probe,
1476 .remove = dspi_remove,
1477 .shutdown = dspi_shutdown,
1478};
1479module_platform_driver(fsl_dspi_driver);
1480
1481MODULE_DESCRIPTION("Freescale DSPI Controller Driver");
1482MODULE_LICENSE("GPL");
1483MODULE_ALIAS("platform:" DRIVER_NAME);
1/*
2 * drivers/spi/spi-fsl-dspi.c
3 *
4 * Copyright 2013 Freescale Semiconductor, Inc.
5 *
6 * Freescale DSPI driver
7 * This file contains a driver for the Freescale DSPI
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 */
15
16#include <linux/kernel.h>
17#include <linux/module.h>
18#include <linux/interrupt.h>
19#include <linux/errno.h>
20#include <linux/platform_device.h>
21#include <linux/regmap.h>
22#include <linux/sched.h>
23#include <linux/delay.h>
24#include <linux/io.h>
25#include <linux/clk.h>
26#include <linux/err.h>
27#include <linux/spi/spi.h>
28#include <linux/spi/spi_bitbang.h>
29#include <linux/pm_runtime.h>
30#include <linux/of.h>
31#include <linux/of_device.h>
32
33#define DRIVER_NAME "fsl-dspi"
34
35#define TRAN_STATE_RX_VOID 0x01
36#define TRAN_STATE_TX_VOID 0x02
37#define TRAN_STATE_WORD_ODD_NUM 0x04
38
39#define DSPI_FIFO_SIZE 4
40
41#define SPI_MCR 0x00
42#define SPI_MCR_MASTER (1 << 31)
43#define SPI_MCR_PCSIS (0x3F << 16)
44#define SPI_MCR_CLR_TXF (1 << 11)
45#define SPI_MCR_CLR_RXF (1 << 10)
46
47#define SPI_TCR 0x08
48
49#define SPI_CTAR(x) (0x0c + (x * 4))
50#define SPI_CTAR_FMSZ(x) (((x) & 0x0000000f) << 27)
51#define SPI_CTAR_CPOL(x) ((x) << 26)
52#define SPI_CTAR_CPHA(x) ((x) << 25)
53#define SPI_CTAR_LSBFE(x) ((x) << 24)
54#define SPI_CTAR_PCSSCR(x) (((x) & 0x00000003) << 22)
55#define SPI_CTAR_PASC(x) (((x) & 0x00000003) << 20)
56#define SPI_CTAR_PDT(x) (((x) & 0x00000003) << 18)
57#define SPI_CTAR_PBR(x) (((x) & 0x00000003) << 16)
58#define SPI_CTAR_CSSCK(x) (((x) & 0x0000000f) << 12)
59#define SPI_CTAR_ASC(x) (((x) & 0x0000000f) << 8)
60#define SPI_CTAR_DT(x) (((x) & 0x0000000f) << 4)
61#define SPI_CTAR_BR(x) ((x) & 0x0000000f)
62
63#define SPI_CTAR0_SLAVE 0x0c
64
65#define SPI_SR 0x2c
66#define SPI_SR_EOQF 0x10000000
67
68#define SPI_RSER 0x30
69#define SPI_RSER_EOQFE 0x10000000
70
71#define SPI_PUSHR 0x34
72#define SPI_PUSHR_CONT (1 << 31)
73#define SPI_PUSHR_CTAS(x) (((x) & 0x00000007) << 28)
74#define SPI_PUSHR_EOQ (1 << 27)
75#define SPI_PUSHR_CTCNT (1 << 26)
76#define SPI_PUSHR_PCS(x) (((1 << x) & 0x0000003f) << 16)
77#define SPI_PUSHR_TXDATA(x) ((x) & 0x0000ffff)
78
79#define SPI_PUSHR_SLAVE 0x34
80
81#define SPI_POPR 0x38
82#define SPI_POPR_RXDATA(x) ((x) & 0x0000ffff)
83
84#define SPI_TXFR0 0x3c
85#define SPI_TXFR1 0x40
86#define SPI_TXFR2 0x44
87#define SPI_TXFR3 0x48
88#define SPI_RXFR0 0x7c
89#define SPI_RXFR1 0x80
90#define SPI_RXFR2 0x84
91#define SPI_RXFR3 0x88
92
93#define SPI_FRAME_BITS(bits) SPI_CTAR_FMSZ((bits) - 1)
94#define SPI_FRAME_BITS_MASK SPI_CTAR_FMSZ(0xf)
95#define SPI_FRAME_BITS_16 SPI_CTAR_FMSZ(0xf)
96#define SPI_FRAME_BITS_8 SPI_CTAR_FMSZ(0x7)
97
98#define SPI_CS_INIT 0x01
99#define SPI_CS_ASSERT 0x02
100#define SPI_CS_DROP 0x04
101
102struct chip_data {
103 u32 mcr_val;
104 u32 ctar_val;
105 u16 void_write_data;
106};
107
108struct fsl_dspi {
109 struct spi_bitbang bitbang;
110 struct platform_device *pdev;
111
112 struct regmap *regmap;
113 int irq;
114 struct clk *clk;
115
116 struct spi_transfer *cur_transfer;
117 struct chip_data *cur_chip;
118 size_t len;
119 void *tx;
120 void *tx_end;
121 void *rx;
122 void *rx_end;
123 char dataflags;
124 u8 cs;
125 u16 void_write_data;
126
127 wait_queue_head_t waitq;
128 u32 waitflags;
129};
130
131static inline int is_double_byte_mode(struct fsl_dspi *dspi)
132{
133 unsigned int val;
134
135 regmap_read(dspi->regmap, SPI_CTAR(dspi->cs), &val);
136
137 return ((val & SPI_FRAME_BITS_MASK) == SPI_FRAME_BITS(8)) ? 0 : 1;
138}
139
140static void hz_to_spi_baud(char *pbr, char *br, int speed_hz,
141 unsigned long clkrate)
142{
143 /* Valid baud rate pre-scaler values */
144 int pbr_tbl[4] = {2, 3, 5, 7};
145 int brs[16] = { 2, 4, 6, 8,
146 16, 32, 64, 128,
147 256, 512, 1024, 2048,
148 4096, 8192, 16384, 32768 };
149 int temp, i = 0, j = 0;
150
151 temp = clkrate / 2 / speed_hz;
152
153 for (i = 0; i < ARRAY_SIZE(pbr_tbl); i++)
154 for (j = 0; j < ARRAY_SIZE(brs); j++) {
155 if (pbr_tbl[i] * brs[j] >= temp) {
156 *pbr = i;
157 *br = j;
158 return;
159 }
160 }
161
162 pr_warn("Can not find valid baud rate,speed_hz is %d,clkrate is %ld\
163 ,we use the max prescaler value.\n", speed_hz, clkrate);
164 *pbr = ARRAY_SIZE(pbr_tbl) - 1;
165 *br = ARRAY_SIZE(brs) - 1;
166}
167
168static int dspi_transfer_write(struct fsl_dspi *dspi)
169{
170 int tx_count = 0;
171 int tx_word;
172 u16 d16;
173 u8 d8;
174 u32 dspi_pushr = 0;
175 int first = 1;
176
177 tx_word = is_double_byte_mode(dspi);
178
179 /* If we are in word mode, but only have a single byte to transfer
180 * then switch to byte mode temporarily. Will switch back at the
181 * end of the transfer.
182 */
183 if (tx_word && (dspi->len == 1)) {
184 dspi->dataflags |= TRAN_STATE_WORD_ODD_NUM;
185 regmap_update_bits(dspi->regmap, SPI_CTAR(dspi->cs),
186 SPI_FRAME_BITS_MASK, SPI_FRAME_BITS(8));
187 tx_word = 0;
188 }
189
190 while (dspi->len && (tx_count < DSPI_FIFO_SIZE)) {
191 if (tx_word) {
192 if (dspi->len == 1)
193 break;
194
195 if (!(dspi->dataflags & TRAN_STATE_TX_VOID)) {
196 d16 = *(u16 *)dspi->tx;
197 dspi->tx += 2;
198 } else {
199 d16 = dspi->void_write_data;
200 }
201
202 dspi_pushr = SPI_PUSHR_TXDATA(d16) |
203 SPI_PUSHR_PCS(dspi->cs) |
204 SPI_PUSHR_CTAS(dspi->cs) |
205 SPI_PUSHR_CONT;
206
207 dspi->len -= 2;
208 } else {
209 if (!(dspi->dataflags & TRAN_STATE_TX_VOID)) {
210
211 d8 = *(u8 *)dspi->tx;
212 dspi->tx++;
213 } else {
214 d8 = (u8)dspi->void_write_data;
215 }
216
217 dspi_pushr = SPI_PUSHR_TXDATA(d8) |
218 SPI_PUSHR_PCS(dspi->cs) |
219 SPI_PUSHR_CTAS(dspi->cs) |
220 SPI_PUSHR_CONT;
221
222 dspi->len--;
223 }
224
225 if (dspi->len == 0 || tx_count == DSPI_FIFO_SIZE - 1) {
226 /* last transfer in the transfer */
227 dspi_pushr |= SPI_PUSHR_EOQ;
228 } else if (tx_word && (dspi->len == 1))
229 dspi_pushr |= SPI_PUSHR_EOQ;
230
231 if (first) {
232 first = 0;
233 dspi_pushr |= SPI_PUSHR_CTCNT; /* clear counter */
234 }
235
236 regmap_write(dspi->regmap, SPI_PUSHR, dspi_pushr);
237
238 tx_count++;
239 }
240
241 return tx_count * (tx_word + 1);
242}
243
244static int dspi_transfer_read(struct fsl_dspi *dspi)
245{
246 int rx_count = 0;
247 int rx_word = is_double_byte_mode(dspi);
248 u16 d;
249 while ((dspi->rx < dspi->rx_end)
250 && (rx_count < DSPI_FIFO_SIZE)) {
251 if (rx_word) {
252 unsigned int val;
253
254 if ((dspi->rx_end - dspi->rx) == 1)
255 break;
256
257 regmap_read(dspi->regmap, SPI_POPR, &val);
258 d = SPI_POPR_RXDATA(val);
259
260 if (!(dspi->dataflags & TRAN_STATE_RX_VOID))
261 *(u16 *)dspi->rx = d;
262 dspi->rx += 2;
263
264 } else {
265 unsigned int val;
266
267 regmap_read(dspi->regmap, SPI_POPR, &val);
268 d = SPI_POPR_RXDATA(val);
269 if (!(dspi->dataflags & TRAN_STATE_RX_VOID))
270 *(u8 *)dspi->rx = d;
271 dspi->rx++;
272 }
273 rx_count++;
274 }
275
276 return rx_count;
277}
278
279static int dspi_txrx_transfer(struct spi_device *spi, struct spi_transfer *t)
280{
281 struct fsl_dspi *dspi = spi_master_get_devdata(spi->master);
282 dspi->cur_transfer = t;
283 dspi->cur_chip = spi_get_ctldata(spi);
284 dspi->cs = spi->chip_select;
285 dspi->void_write_data = dspi->cur_chip->void_write_data;
286
287 dspi->dataflags = 0;
288 dspi->tx = (void *)t->tx_buf;
289 dspi->tx_end = dspi->tx + t->len;
290 dspi->rx = t->rx_buf;
291 dspi->rx_end = dspi->rx + t->len;
292 dspi->len = t->len;
293
294 if (!dspi->rx)
295 dspi->dataflags |= TRAN_STATE_RX_VOID;
296
297 if (!dspi->tx)
298 dspi->dataflags |= TRAN_STATE_TX_VOID;
299
300 regmap_write(dspi->regmap, SPI_MCR, dspi->cur_chip->mcr_val);
301 regmap_write(dspi->regmap, SPI_CTAR(dspi->cs), dspi->cur_chip->ctar_val);
302 regmap_write(dspi->regmap, SPI_RSER, SPI_RSER_EOQFE);
303
304 if (t->speed_hz)
305 regmap_write(dspi->regmap, SPI_CTAR(dspi->cs),
306 dspi->cur_chip->ctar_val);
307
308 dspi_transfer_write(dspi);
309
310 if (wait_event_interruptible(dspi->waitq, dspi->waitflags))
311 dev_err(&dspi->pdev->dev, "wait transfer complete fail!\n");
312 dspi->waitflags = 0;
313
314 return t->len - dspi->len;
315}
316
317static void dspi_chipselect(struct spi_device *spi, int value)
318{
319 struct fsl_dspi *dspi = spi_master_get_devdata(spi->master);
320 unsigned int pushr;
321
322 regmap_read(dspi->regmap, SPI_PUSHR, &pushr);
323
324 switch (value) {
325 case BITBANG_CS_ACTIVE:
326 pushr |= SPI_PUSHR_CONT;
327 break;
328 case BITBANG_CS_INACTIVE:
329 pushr &= ~SPI_PUSHR_CONT;
330 break;
331 }
332
333 regmap_write(dspi->regmap, SPI_PUSHR, pushr);
334}
335
336static int dspi_setup_transfer(struct spi_device *spi, struct spi_transfer *t)
337{
338 struct chip_data *chip;
339 struct fsl_dspi *dspi = spi_master_get_devdata(spi->master);
340 unsigned char br = 0, pbr = 0, fmsz = 0;
341
342 /* Only alloc on first setup */
343 chip = spi_get_ctldata(spi);
344 if (chip == NULL) {
345 chip = devm_kzalloc(&spi->dev, sizeof(struct chip_data),
346 GFP_KERNEL);
347 if (!chip)
348 return -ENOMEM;
349 }
350
351 chip->mcr_val = SPI_MCR_MASTER | SPI_MCR_PCSIS |
352 SPI_MCR_CLR_TXF | SPI_MCR_CLR_RXF;
353 if ((spi->bits_per_word >= 4) && (spi->bits_per_word <= 16)) {
354 fmsz = spi->bits_per_word - 1;
355 } else {
356 pr_err("Invalid wordsize\n");
357 return -ENODEV;
358 }
359
360 chip->void_write_data = 0;
361
362 hz_to_spi_baud(&pbr, &br,
363 spi->max_speed_hz, clk_get_rate(dspi->clk));
364
365 chip->ctar_val = SPI_CTAR_FMSZ(fmsz)
366 | SPI_CTAR_CPOL(spi->mode & SPI_CPOL ? 1 : 0)
367 | SPI_CTAR_CPHA(spi->mode & SPI_CPHA ? 1 : 0)
368 | SPI_CTAR_LSBFE(spi->mode & SPI_LSB_FIRST ? 1 : 0)
369 | SPI_CTAR_PBR(pbr)
370 | SPI_CTAR_BR(br);
371
372 spi_set_ctldata(spi, chip);
373
374 return 0;
375}
376
377static int dspi_setup(struct spi_device *spi)
378{
379 if (!spi->max_speed_hz)
380 return -EINVAL;
381
382 return dspi_setup_transfer(spi, NULL);
383}
384
385static irqreturn_t dspi_interrupt(int irq, void *dev_id)
386{
387 struct fsl_dspi *dspi = (struct fsl_dspi *)dev_id;
388
389 regmap_write(dspi->regmap, SPI_SR, SPI_SR_EOQF);
390
391 dspi_transfer_read(dspi);
392
393 if (!dspi->len) {
394 if (dspi->dataflags & TRAN_STATE_WORD_ODD_NUM)
395 regmap_update_bits(dspi->regmap, SPI_CTAR(dspi->cs),
396 SPI_FRAME_BITS_MASK, SPI_FRAME_BITS(16));
397
398 dspi->waitflags = 1;
399 wake_up_interruptible(&dspi->waitq);
400 } else {
401 dspi_transfer_write(dspi);
402
403 return IRQ_HANDLED;
404 }
405
406 return IRQ_HANDLED;
407}
408
409static struct of_device_id fsl_dspi_dt_ids[] = {
410 { .compatible = "fsl,vf610-dspi", .data = NULL, },
411 { /* sentinel */ }
412};
413MODULE_DEVICE_TABLE(of, fsl_dspi_dt_ids);
414
415#ifdef CONFIG_PM_SLEEP
416static int dspi_suspend(struct device *dev)
417{
418 struct spi_master *master = dev_get_drvdata(dev);
419 struct fsl_dspi *dspi = spi_master_get_devdata(master);
420
421 spi_master_suspend(master);
422 clk_disable_unprepare(dspi->clk);
423
424 return 0;
425}
426
427static int dspi_resume(struct device *dev)
428{
429 struct spi_master *master = dev_get_drvdata(dev);
430 struct fsl_dspi *dspi = spi_master_get_devdata(master);
431
432 clk_prepare_enable(dspi->clk);
433 spi_master_resume(master);
434
435 return 0;
436}
437#endif /* CONFIG_PM_SLEEP */
438
439static SIMPLE_DEV_PM_OPS(dspi_pm, dspi_suspend, dspi_resume);
440
441static struct regmap_config dspi_regmap_config = {
442 .reg_bits = 32,
443 .val_bits = 32,
444 .reg_stride = 4,
445 .max_register = 0x88,
446};
447
448static int dspi_probe(struct platform_device *pdev)
449{
450 struct device_node *np = pdev->dev.of_node;
451 struct spi_master *master;
452 struct fsl_dspi *dspi;
453 struct resource *res;
454 void __iomem *base;
455 int ret = 0, cs_num, bus_num;
456
457 master = spi_alloc_master(&pdev->dev, sizeof(struct fsl_dspi));
458 if (!master)
459 return -ENOMEM;
460
461 dspi = spi_master_get_devdata(master);
462 dspi->pdev = pdev;
463 dspi->bitbang.master = master;
464 dspi->bitbang.chipselect = dspi_chipselect;
465 dspi->bitbang.setup_transfer = dspi_setup_transfer;
466 dspi->bitbang.txrx_bufs = dspi_txrx_transfer;
467 dspi->bitbang.master->setup = dspi_setup;
468 dspi->bitbang.master->dev.of_node = pdev->dev.of_node;
469
470 master->mode_bits = SPI_CPOL | SPI_CPHA;
471 master->bits_per_word_mask = SPI_BPW_MASK(4) | SPI_BPW_MASK(8) |
472 SPI_BPW_MASK(16);
473
474 ret = of_property_read_u32(np, "spi-num-chipselects", &cs_num);
475 if (ret < 0) {
476 dev_err(&pdev->dev, "can't get spi-num-chipselects\n");
477 goto out_master_put;
478 }
479 master->num_chipselect = cs_num;
480
481 ret = of_property_read_u32(np, "bus-num", &bus_num);
482 if (ret < 0) {
483 dev_err(&pdev->dev, "can't get bus-num\n");
484 goto out_master_put;
485 }
486 master->bus_num = bus_num;
487
488 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
489 base = devm_ioremap_resource(&pdev->dev, res);
490 if (IS_ERR(base)) {
491 ret = PTR_ERR(base);
492 goto out_master_put;
493 }
494
495 dspi_regmap_config.lock_arg = dspi;
496 dspi_regmap_config.val_format_endian =
497 of_property_read_bool(np, "big-endian")
498 ? REGMAP_ENDIAN_BIG : REGMAP_ENDIAN_DEFAULT;
499 dspi->regmap = devm_regmap_init_mmio_clk(&pdev->dev, "dspi", base,
500 &dspi_regmap_config);
501 if (IS_ERR(dspi->regmap)) {
502 dev_err(&pdev->dev, "failed to init regmap: %ld\n",
503 PTR_ERR(dspi->regmap));
504 return PTR_ERR(dspi->regmap);
505 }
506
507 dspi->irq = platform_get_irq(pdev, 0);
508 if (dspi->irq < 0) {
509 dev_err(&pdev->dev, "can't get platform irq\n");
510 ret = dspi->irq;
511 goto out_master_put;
512 }
513
514 ret = devm_request_irq(&pdev->dev, dspi->irq, dspi_interrupt, 0,
515 pdev->name, dspi);
516 if (ret < 0) {
517 dev_err(&pdev->dev, "Unable to attach DSPI interrupt\n");
518 goto out_master_put;
519 }
520
521 dspi->clk = devm_clk_get(&pdev->dev, "dspi");
522 if (IS_ERR(dspi->clk)) {
523 ret = PTR_ERR(dspi->clk);
524 dev_err(&pdev->dev, "unable to get clock\n");
525 goto out_master_put;
526 }
527 clk_prepare_enable(dspi->clk);
528
529 init_waitqueue_head(&dspi->waitq);
530 platform_set_drvdata(pdev, master);
531
532 ret = spi_bitbang_start(&dspi->bitbang);
533 if (ret != 0) {
534 dev_err(&pdev->dev, "Problem registering DSPI master\n");
535 goto out_clk_put;
536 }
537
538 pr_info(KERN_INFO "Freescale DSPI master initialized\n");
539 return ret;
540
541out_clk_put:
542 clk_disable_unprepare(dspi->clk);
543out_master_put:
544 spi_master_put(master);
545
546 return ret;
547}
548
549static int dspi_remove(struct platform_device *pdev)
550{
551 struct spi_master *master = platform_get_drvdata(pdev);
552 struct fsl_dspi *dspi = spi_master_get_devdata(master);
553
554 /* Disconnect from the SPI framework */
555 spi_bitbang_stop(&dspi->bitbang);
556 clk_disable_unprepare(dspi->clk);
557 spi_master_put(dspi->bitbang.master);
558
559 return 0;
560}
561
562static struct platform_driver fsl_dspi_driver = {
563 .driver.name = DRIVER_NAME,
564 .driver.of_match_table = fsl_dspi_dt_ids,
565 .driver.owner = THIS_MODULE,
566 .driver.pm = &dspi_pm,
567 .probe = dspi_probe,
568 .remove = dspi_remove,
569};
570module_platform_driver(fsl_dspi_driver);
571
572MODULE_DESCRIPTION("Freescale DSPI Controller Driver");
573MODULE_LICENSE("GPL");
574MODULE_ALIAS("platform:" DRIVER_NAME);