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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Watchdog driver for IMX2 and later processors
4 *
5 * Copyright (C) 2010 Wolfram Sang, Pengutronix e.K. <kernel@pengutronix.de>
6 * Copyright (C) 2014 Freescale Semiconductor, Inc.
7 *
8 * some parts adapted by similar drivers from Darius Augulis and Vladimir
9 * Zapolskiy, additional improvements by Wim Van Sebroeck.
10 *
11 * NOTE: MX1 has a slightly different Watchdog than MX2 and later:
12 *
13 * MX1: MX2+:
14 * ---- -----
15 * Registers: 32-bit 16-bit
16 * Stopable timer: Yes No
17 * Need to enable clk: No Yes
18 * Halt on suspend: Manual Can be automatic
19 */
20
21#include <linux/clk.h>
22#include <linux/delay.h>
23#include <linux/init.h>
24#include <linux/interrupt.h>
25#include <linux/io.h>
26#include <linux/kernel.h>
27#include <linux/module.h>
28#include <linux/moduleparam.h>
29#include <linux/of_address.h>
30#include <linux/platform_device.h>
31#include <linux/regmap.h>
32#include <linux/watchdog.h>
33
34#define DRIVER_NAME "imx2-wdt"
35
36#define IMX2_WDT_WCR 0x00 /* Control Register */
37#define IMX2_WDT_WCR_WT (0xFF << 8) /* -> Watchdog Timeout Field */
38#define IMX2_WDT_WCR_WDA BIT(5) /* -> External Reset WDOG_B */
39#define IMX2_WDT_WCR_SRS BIT(4) /* -> Software Reset Signal */
40#define IMX2_WDT_WCR_WRE BIT(3) /* -> WDOG Reset Enable */
41#define IMX2_WDT_WCR_WDE BIT(2) /* -> Watchdog Enable */
42#define IMX2_WDT_WCR_WDZST BIT(0) /* -> Watchdog timer Suspend */
43
44#define IMX2_WDT_WSR 0x02 /* Service Register */
45#define IMX2_WDT_SEQ1 0x5555 /* -> service sequence 1 */
46#define IMX2_WDT_SEQ2 0xAAAA /* -> service sequence 2 */
47
48#define IMX2_WDT_WRSR 0x04 /* Reset Status Register */
49#define IMX2_WDT_WRSR_TOUT BIT(1) /* -> Reset due to Timeout */
50
51#define IMX2_WDT_WICR 0x06 /* Interrupt Control Register */
52#define IMX2_WDT_WICR_WIE BIT(15) /* -> Interrupt Enable */
53#define IMX2_WDT_WICR_WTIS BIT(14) /* -> Interrupt Status */
54#define IMX2_WDT_WICR_WICT 0xFF /* -> Interrupt Count Timeout */
55
56#define IMX2_WDT_WMCR 0x08 /* Misc Register */
57
58#define IMX2_WDT_MAX_TIME 128U
59#define IMX2_WDT_DEFAULT_TIME 60 /* in seconds */
60
61#define WDOG_SEC_TO_COUNT(s) ((s * 2 - 1) << 8)
62
63struct imx2_wdt_device {
64 struct clk *clk;
65 struct regmap *regmap;
66 struct watchdog_device wdog;
67 bool ext_reset;
68};
69
70static bool nowayout = WATCHDOG_NOWAYOUT;
71module_param(nowayout, bool, 0);
72MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default="
73 __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
74
75static unsigned timeout;
76module_param(timeout, uint, 0);
77MODULE_PARM_DESC(timeout, "Watchdog timeout in seconds (default="
78 __MODULE_STRING(IMX2_WDT_DEFAULT_TIME) ")");
79
80static const struct watchdog_info imx2_wdt_info = {
81 .identity = "imx2+ watchdog",
82 .options = WDIOF_KEEPALIVEPING | WDIOF_SETTIMEOUT | WDIOF_MAGICCLOSE,
83};
84
85static const struct watchdog_info imx2_wdt_pretimeout_info = {
86 .identity = "imx2+ watchdog",
87 .options = WDIOF_KEEPALIVEPING | WDIOF_SETTIMEOUT | WDIOF_MAGICCLOSE |
88 WDIOF_PRETIMEOUT,
89};
90
91static int imx2_wdt_restart(struct watchdog_device *wdog, unsigned long action,
92 void *data)
93{
94 struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
95 unsigned int wcr_enable = IMX2_WDT_WCR_WDE;
96
97 /* Use internal reset or external - not both */
98 if (wdev->ext_reset)
99 wcr_enable |= IMX2_WDT_WCR_SRS; /* do not assert int reset */
100 else
101 wcr_enable |= IMX2_WDT_WCR_WDA; /* do not assert ext-reset */
102
103 /* Assert SRS signal */
104 regmap_write(wdev->regmap, IMX2_WDT_WCR, wcr_enable);
105 /*
106 * Due to imx6q errata ERR004346 (WDOG: WDOG SRS bit requires to be
107 * written twice), we add another two writes to ensure there must be at
108 * least two writes happen in the same one 32kHz clock period. We save
109 * the target check here, since the writes shouldn't be a huge burden
110 * for other platforms.
111 */
112 regmap_write(wdev->regmap, IMX2_WDT_WCR, wcr_enable);
113 regmap_write(wdev->regmap, IMX2_WDT_WCR, wcr_enable);
114
115 /* wait for reset to assert... */
116 mdelay(500);
117
118 return 0;
119}
120
121static inline void imx2_wdt_setup(struct watchdog_device *wdog)
122{
123 struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
124 u32 val;
125
126 regmap_read(wdev->regmap, IMX2_WDT_WCR, &val);
127
128 /* Suspend timer in low power mode, write once-only */
129 val |= IMX2_WDT_WCR_WDZST;
130 /* Strip the old watchdog Time-Out value */
131 val &= ~IMX2_WDT_WCR_WT;
132 /* Generate internal chip-level reset if WDOG times out */
133 if (!wdev->ext_reset)
134 val &= ~IMX2_WDT_WCR_WRE;
135 /* Or if external-reset assert WDOG_B reset only on time-out */
136 else
137 val |= IMX2_WDT_WCR_WRE;
138 /* Keep Watchdog Disabled */
139 val &= ~IMX2_WDT_WCR_WDE;
140 /* Set the watchdog's Time-Out value */
141 val |= WDOG_SEC_TO_COUNT(wdog->timeout);
142
143 regmap_write(wdev->regmap, IMX2_WDT_WCR, val);
144
145 /* enable the watchdog */
146 val |= IMX2_WDT_WCR_WDE;
147 regmap_write(wdev->regmap, IMX2_WDT_WCR, val);
148}
149
150static inline bool imx2_wdt_is_running(struct imx2_wdt_device *wdev)
151{
152 u32 val;
153
154 regmap_read(wdev->regmap, IMX2_WDT_WCR, &val);
155
156 return val & IMX2_WDT_WCR_WDE;
157}
158
159static int imx2_wdt_ping(struct watchdog_device *wdog)
160{
161 struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
162
163 regmap_write(wdev->regmap, IMX2_WDT_WSR, IMX2_WDT_SEQ1);
164 regmap_write(wdev->regmap, IMX2_WDT_WSR, IMX2_WDT_SEQ2);
165 return 0;
166}
167
168static void __imx2_wdt_set_timeout(struct watchdog_device *wdog,
169 unsigned int new_timeout)
170{
171 struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
172
173 regmap_update_bits(wdev->regmap, IMX2_WDT_WCR, IMX2_WDT_WCR_WT,
174 WDOG_SEC_TO_COUNT(new_timeout));
175}
176
177static int imx2_wdt_set_timeout(struct watchdog_device *wdog,
178 unsigned int new_timeout)
179{
180 unsigned int actual;
181
182 actual = min(new_timeout, IMX2_WDT_MAX_TIME);
183 __imx2_wdt_set_timeout(wdog, actual);
184 wdog->timeout = new_timeout;
185 return 0;
186}
187
188static int imx2_wdt_set_pretimeout(struct watchdog_device *wdog,
189 unsigned int new_pretimeout)
190{
191 struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
192
193 if (new_pretimeout >= IMX2_WDT_MAX_TIME)
194 return -EINVAL;
195
196 wdog->pretimeout = new_pretimeout;
197
198 regmap_update_bits(wdev->regmap, IMX2_WDT_WICR,
199 IMX2_WDT_WICR_WIE | IMX2_WDT_WICR_WICT,
200 IMX2_WDT_WICR_WIE | (new_pretimeout << 1));
201 return 0;
202}
203
204static irqreturn_t imx2_wdt_isr(int irq, void *wdog_arg)
205{
206 struct watchdog_device *wdog = wdog_arg;
207 struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
208
209 regmap_write_bits(wdev->regmap, IMX2_WDT_WICR,
210 IMX2_WDT_WICR_WTIS, IMX2_WDT_WICR_WTIS);
211
212 watchdog_notify_pretimeout(wdog);
213
214 return IRQ_HANDLED;
215}
216
217static int imx2_wdt_start(struct watchdog_device *wdog)
218{
219 struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
220
221 if (imx2_wdt_is_running(wdev))
222 imx2_wdt_set_timeout(wdog, wdog->timeout);
223 else
224 imx2_wdt_setup(wdog);
225
226 set_bit(WDOG_HW_RUNNING, &wdog->status);
227
228 return imx2_wdt_ping(wdog);
229}
230
231static const struct watchdog_ops imx2_wdt_ops = {
232 .owner = THIS_MODULE,
233 .start = imx2_wdt_start,
234 .ping = imx2_wdt_ping,
235 .set_timeout = imx2_wdt_set_timeout,
236 .set_pretimeout = imx2_wdt_set_pretimeout,
237 .restart = imx2_wdt_restart,
238};
239
240static const struct regmap_config imx2_wdt_regmap_config = {
241 .reg_bits = 16,
242 .reg_stride = 2,
243 .val_bits = 16,
244 .max_register = 0x8,
245};
246
247static void imx2_wdt_action(void *data)
248{
249 clk_disable_unprepare(data);
250}
251
252static int __init imx2_wdt_probe(struct platform_device *pdev)
253{
254 struct device *dev = &pdev->dev;
255 struct imx2_wdt_device *wdev;
256 struct watchdog_device *wdog;
257 void __iomem *base;
258 int ret;
259 u32 val;
260
261 wdev = devm_kzalloc(dev, sizeof(*wdev), GFP_KERNEL);
262 if (!wdev)
263 return -ENOMEM;
264
265 base = devm_platform_ioremap_resource(pdev, 0);
266 if (IS_ERR(base))
267 return PTR_ERR(base);
268
269 wdev->regmap = devm_regmap_init_mmio_clk(dev, NULL, base,
270 &imx2_wdt_regmap_config);
271 if (IS_ERR(wdev->regmap)) {
272 dev_err(dev, "regmap init failed\n");
273 return PTR_ERR(wdev->regmap);
274 }
275
276 wdev->clk = devm_clk_get(dev, NULL);
277 if (IS_ERR(wdev->clk)) {
278 dev_err(dev, "can't get Watchdog clock\n");
279 return PTR_ERR(wdev->clk);
280 }
281
282 wdog = &wdev->wdog;
283 wdog->info = &imx2_wdt_info;
284 wdog->ops = &imx2_wdt_ops;
285 wdog->min_timeout = 1;
286 wdog->timeout = IMX2_WDT_DEFAULT_TIME;
287 wdog->max_hw_heartbeat_ms = IMX2_WDT_MAX_TIME * 1000;
288 wdog->parent = dev;
289
290 ret = platform_get_irq(pdev, 0);
291 if (ret > 0)
292 if (!devm_request_irq(dev, ret, imx2_wdt_isr, 0,
293 dev_name(dev), wdog))
294 wdog->info = &imx2_wdt_pretimeout_info;
295
296 ret = clk_prepare_enable(wdev->clk);
297 if (ret)
298 return ret;
299
300 ret = devm_add_action_or_reset(dev, imx2_wdt_action, wdev->clk);
301 if (ret)
302 return ret;
303
304 regmap_read(wdev->regmap, IMX2_WDT_WRSR, &val);
305 wdog->bootstatus = val & IMX2_WDT_WRSR_TOUT ? WDIOF_CARDRESET : 0;
306
307 wdev->ext_reset = of_property_read_bool(dev->of_node,
308 "fsl,ext-reset-output");
309 platform_set_drvdata(pdev, wdog);
310 watchdog_set_drvdata(wdog, wdev);
311 watchdog_set_nowayout(wdog, nowayout);
312 watchdog_set_restart_priority(wdog, 128);
313 watchdog_init_timeout(wdog, timeout, dev);
314
315 if (imx2_wdt_is_running(wdev)) {
316 imx2_wdt_set_timeout(wdog, wdog->timeout);
317 set_bit(WDOG_HW_RUNNING, &wdog->status);
318 }
319
320 /*
321 * Disable the watchdog power down counter at boot. Otherwise the power
322 * down counter will pull down the #WDOG interrupt line for one clock
323 * cycle.
324 */
325 regmap_write(wdev->regmap, IMX2_WDT_WMCR, 0);
326
327 return devm_watchdog_register_device(dev, wdog);
328}
329
330static void imx2_wdt_shutdown(struct platform_device *pdev)
331{
332 struct watchdog_device *wdog = platform_get_drvdata(pdev);
333 struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
334
335 if (imx2_wdt_is_running(wdev)) {
336 /*
337 * We are running, configure max timeout before reboot
338 * will take place.
339 */
340 imx2_wdt_set_timeout(wdog, IMX2_WDT_MAX_TIME);
341 imx2_wdt_ping(wdog);
342 dev_crit(&pdev->dev, "Device shutdown: Expect reboot!\n");
343 }
344}
345
346/* Disable watchdog if it is active or non-active but still running */
347static int __maybe_unused imx2_wdt_suspend(struct device *dev)
348{
349 struct watchdog_device *wdog = dev_get_drvdata(dev);
350 struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
351
352 /* The watchdog IP block is running */
353 if (imx2_wdt_is_running(wdev)) {
354 /*
355 * Don't update wdog->timeout, we'll restore the current value
356 * during resume.
357 */
358 __imx2_wdt_set_timeout(wdog, IMX2_WDT_MAX_TIME);
359 imx2_wdt_ping(wdog);
360 }
361
362 clk_disable_unprepare(wdev->clk);
363
364 return 0;
365}
366
367/* Enable watchdog and configure it if necessary */
368static int __maybe_unused imx2_wdt_resume(struct device *dev)
369{
370 struct watchdog_device *wdog = dev_get_drvdata(dev);
371 struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
372 int ret;
373
374 ret = clk_prepare_enable(wdev->clk);
375 if (ret)
376 return ret;
377
378 if (watchdog_active(wdog) && !imx2_wdt_is_running(wdev)) {
379 /*
380 * If the watchdog is still active and resumes
381 * from deep sleep state, need to restart the
382 * watchdog again.
383 */
384 imx2_wdt_setup(wdog);
385 }
386 if (imx2_wdt_is_running(wdev)) {
387 imx2_wdt_set_timeout(wdog, wdog->timeout);
388 imx2_wdt_ping(wdog);
389 }
390
391 return 0;
392}
393
394static SIMPLE_DEV_PM_OPS(imx2_wdt_pm_ops, imx2_wdt_suspend,
395 imx2_wdt_resume);
396
397static const struct of_device_id imx2_wdt_dt_ids[] = {
398 { .compatible = "fsl,imx21-wdt", },
399 { /* sentinel */ }
400};
401MODULE_DEVICE_TABLE(of, imx2_wdt_dt_ids);
402
403static struct platform_driver imx2_wdt_driver = {
404 .shutdown = imx2_wdt_shutdown,
405 .driver = {
406 .name = DRIVER_NAME,
407 .pm = &imx2_wdt_pm_ops,
408 .of_match_table = imx2_wdt_dt_ids,
409 },
410};
411
412module_platform_driver_probe(imx2_wdt_driver, imx2_wdt_probe);
413
414MODULE_AUTHOR("Wolfram Sang");
415MODULE_DESCRIPTION("Watchdog driver for IMX2 and later");
416MODULE_LICENSE("GPL v2");
417MODULE_ALIAS("platform:" DRIVER_NAME);
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Watchdog driver for IMX2 and later processors
4 *
5 * Copyright (C) 2010 Wolfram Sang, Pengutronix e.K. <kernel@pengutronix.de>
6 * Copyright (C) 2014 Freescale Semiconductor, Inc.
7 *
8 * some parts adapted by similar drivers from Darius Augulis and Vladimir
9 * Zapolskiy, additional improvements by Wim Van Sebroeck.
10 *
11 * NOTE: MX1 has a slightly different Watchdog than MX2 and later:
12 *
13 * MX1: MX2+:
14 * ---- -----
15 * Registers: 32-bit 16-bit
16 * Stopable timer: Yes No
17 * Need to enable clk: No Yes
18 * Halt on suspend: Manual Can be automatic
19 */
20
21#include <linux/clk.h>
22#include <linux/delay.h>
23#include <linux/init.h>
24#include <linux/interrupt.h>
25#include <linux/io.h>
26#include <linux/kernel.h>
27#include <linux/module.h>
28#include <linux/moduleparam.h>
29#include <linux/of.h>
30#include <linux/platform_device.h>
31#include <linux/regmap.h>
32#include <linux/watchdog.h>
33
34#define DRIVER_NAME "imx2-wdt"
35
36#define IMX2_WDT_WCR 0x00 /* Control Register */
37#define IMX2_WDT_WCR_WT (0xFF << 8) /* -> Watchdog Timeout Field */
38#define IMX2_WDT_WCR_WDW BIT(7) /* -> Watchdog disable for WAIT */
39#define IMX2_WDT_WCR_WDA BIT(5) /* -> External Reset WDOG_B */
40#define IMX2_WDT_WCR_SRS BIT(4) /* -> Software Reset Signal */
41#define IMX2_WDT_WCR_WRE BIT(3) /* -> WDOG Reset Enable */
42#define IMX2_WDT_WCR_WDE BIT(2) /* -> Watchdog Enable */
43#define IMX2_WDT_WCR_WDZST BIT(0) /* -> Watchdog timer Suspend */
44
45#define IMX2_WDT_WSR 0x02 /* Service Register */
46#define IMX2_WDT_SEQ1 0x5555 /* -> service sequence 1 */
47#define IMX2_WDT_SEQ2 0xAAAA /* -> service sequence 2 */
48
49#define IMX2_WDT_WRSR 0x04 /* Reset Status Register */
50#define IMX2_WDT_WRSR_TOUT BIT(1) /* -> Reset due to Timeout */
51
52#define IMX2_WDT_WICR 0x06 /* Interrupt Control Register */
53#define IMX2_WDT_WICR_WIE BIT(15) /* -> Interrupt Enable */
54#define IMX2_WDT_WICR_WTIS BIT(14) /* -> Interrupt Status */
55#define IMX2_WDT_WICR_WICT 0xFF /* -> Interrupt Count Timeout */
56
57#define IMX2_WDT_WMCR 0x08 /* Misc Register */
58
59#define IMX2_WDT_MAX_TIME 128U
60#define IMX2_WDT_DEFAULT_TIME 60 /* in seconds */
61
62#define WDOG_SEC_TO_COUNT(s) ((s * 2 - 1) << 8)
63
64struct imx2_wdt_data {
65 bool wdw_supported;
66};
67
68struct imx2_wdt_device {
69 struct clk *clk;
70 struct regmap *regmap;
71 struct watchdog_device wdog;
72 const struct imx2_wdt_data *data;
73 bool ext_reset;
74 bool clk_is_on;
75 bool no_ping;
76 bool sleep_wait;
77};
78
79static bool nowayout = WATCHDOG_NOWAYOUT;
80module_param(nowayout, bool, 0);
81MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default="
82 __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
83
84static unsigned timeout;
85module_param(timeout, uint, 0);
86MODULE_PARM_DESC(timeout, "Watchdog timeout in seconds (default="
87 __MODULE_STRING(IMX2_WDT_DEFAULT_TIME) ")");
88
89static const struct watchdog_info imx2_wdt_info = {
90 .identity = "imx2+ watchdog",
91 .options = WDIOF_KEEPALIVEPING | WDIOF_SETTIMEOUT | WDIOF_MAGICCLOSE,
92};
93
94static const struct watchdog_info imx2_wdt_pretimeout_info = {
95 .identity = "imx2+ watchdog",
96 .options = WDIOF_KEEPALIVEPING | WDIOF_SETTIMEOUT | WDIOF_MAGICCLOSE |
97 WDIOF_PRETIMEOUT,
98};
99
100static int imx2_wdt_restart(struct watchdog_device *wdog, unsigned long action,
101 void *data)
102{
103 struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
104 unsigned int wcr_enable = IMX2_WDT_WCR_WDE;
105
106 /* Use internal reset or external - not both */
107 if (wdev->ext_reset)
108 wcr_enable |= IMX2_WDT_WCR_SRS; /* do not assert int reset */
109 else
110 wcr_enable |= IMX2_WDT_WCR_WDA; /* do not assert ext-reset */
111
112 /* Assert SRS signal */
113 regmap_write(wdev->regmap, IMX2_WDT_WCR, wcr_enable);
114 /*
115 * Due to imx6q errata ERR004346 (WDOG: WDOG SRS bit requires to be
116 * written twice), we add another two writes to ensure there must be at
117 * least two writes happen in the same one 32kHz clock period. We save
118 * the target check here, since the writes shouldn't be a huge burden
119 * for other platforms.
120 */
121 regmap_write(wdev->regmap, IMX2_WDT_WCR, wcr_enable);
122 regmap_write(wdev->regmap, IMX2_WDT_WCR, wcr_enable);
123
124 /* wait for reset to assert... */
125 mdelay(500);
126
127 return 0;
128}
129
130static inline void imx2_wdt_setup(struct watchdog_device *wdog)
131{
132 struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
133 u32 val;
134
135 regmap_read(wdev->regmap, IMX2_WDT_WCR, &val);
136
137 /* Suspend timer in low power mode, write once-only */
138 val |= IMX2_WDT_WCR_WDZST;
139 /* Suspend timer in low power WAIT mode, write once-only */
140 if (wdev->sleep_wait)
141 val |= IMX2_WDT_WCR_WDW;
142 /* Strip the old watchdog Time-Out value */
143 val &= ~IMX2_WDT_WCR_WT;
144 /* Generate internal chip-level reset if WDOG times out */
145 if (!wdev->ext_reset)
146 val &= ~IMX2_WDT_WCR_WRE;
147 /* Or if external-reset assert WDOG_B reset only on time-out */
148 else
149 val |= IMX2_WDT_WCR_WRE;
150 /* Keep Watchdog Disabled */
151 val &= ~IMX2_WDT_WCR_WDE;
152 /* Set the watchdog's Time-Out value */
153 val |= WDOG_SEC_TO_COUNT(wdog->timeout);
154
155 regmap_write(wdev->regmap, IMX2_WDT_WCR, val);
156
157 /* enable the watchdog */
158 val |= IMX2_WDT_WCR_WDE;
159 regmap_write(wdev->regmap, IMX2_WDT_WCR, val);
160}
161
162static inline bool imx2_wdt_is_running(struct imx2_wdt_device *wdev)
163{
164 u32 val;
165
166 regmap_read(wdev->regmap, IMX2_WDT_WCR, &val);
167
168 return val & IMX2_WDT_WCR_WDE;
169}
170
171static int imx2_wdt_ping(struct watchdog_device *wdog)
172{
173 struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
174
175 if (!wdev->clk_is_on)
176 return 0;
177
178 regmap_write(wdev->regmap, IMX2_WDT_WSR, IMX2_WDT_SEQ1);
179 regmap_write(wdev->regmap, IMX2_WDT_WSR, IMX2_WDT_SEQ2);
180 return 0;
181}
182
183static void __imx2_wdt_set_timeout(struct watchdog_device *wdog,
184 unsigned int new_timeout)
185{
186 struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
187
188 regmap_update_bits(wdev->regmap, IMX2_WDT_WCR, IMX2_WDT_WCR_WT,
189 WDOG_SEC_TO_COUNT(new_timeout));
190}
191
192static int imx2_wdt_set_timeout(struct watchdog_device *wdog,
193 unsigned int new_timeout)
194{
195 unsigned int actual;
196
197 actual = min(new_timeout, IMX2_WDT_MAX_TIME);
198 __imx2_wdt_set_timeout(wdog, actual);
199 wdog->timeout = new_timeout;
200 return 0;
201}
202
203static int imx2_wdt_set_pretimeout(struct watchdog_device *wdog,
204 unsigned int new_pretimeout)
205{
206 struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
207
208 if (new_pretimeout >= IMX2_WDT_MAX_TIME)
209 return -EINVAL;
210
211 wdog->pretimeout = new_pretimeout;
212
213 regmap_update_bits(wdev->regmap, IMX2_WDT_WICR,
214 IMX2_WDT_WICR_WIE | IMX2_WDT_WICR_WICT,
215 IMX2_WDT_WICR_WIE | (new_pretimeout << 1));
216 return 0;
217}
218
219static irqreturn_t imx2_wdt_isr(int irq, void *wdog_arg)
220{
221 struct watchdog_device *wdog = wdog_arg;
222 struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
223
224 regmap_write_bits(wdev->regmap, IMX2_WDT_WICR,
225 IMX2_WDT_WICR_WTIS, IMX2_WDT_WICR_WTIS);
226
227 watchdog_notify_pretimeout(wdog);
228
229 return IRQ_HANDLED;
230}
231
232static int imx2_wdt_start(struct watchdog_device *wdog)
233{
234 struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
235
236 if (imx2_wdt_is_running(wdev))
237 imx2_wdt_set_timeout(wdog, wdog->timeout);
238 else
239 imx2_wdt_setup(wdog);
240
241 set_bit(WDOG_HW_RUNNING, &wdog->status);
242
243 return imx2_wdt_ping(wdog);
244}
245
246static const struct watchdog_ops imx2_wdt_ops = {
247 .owner = THIS_MODULE,
248 .start = imx2_wdt_start,
249 .ping = imx2_wdt_ping,
250 .set_timeout = imx2_wdt_set_timeout,
251 .set_pretimeout = imx2_wdt_set_pretimeout,
252 .restart = imx2_wdt_restart,
253};
254
255static const struct regmap_config imx2_wdt_regmap_config = {
256 .reg_bits = 16,
257 .reg_stride = 2,
258 .val_bits = 16,
259 .max_register = 0x8,
260};
261
262static void imx2_wdt_action(void *data)
263{
264 clk_disable_unprepare(data);
265}
266
267static int __init imx2_wdt_probe(struct platform_device *pdev)
268{
269 struct device *dev = &pdev->dev;
270 struct imx2_wdt_device *wdev;
271 struct watchdog_device *wdog;
272 void __iomem *base;
273 int ret;
274 u32 val;
275
276 wdev = devm_kzalloc(dev, sizeof(*wdev), GFP_KERNEL);
277 if (!wdev)
278 return -ENOMEM;
279
280 base = devm_platform_ioremap_resource(pdev, 0);
281 if (IS_ERR(base))
282 return PTR_ERR(base);
283
284 wdev->regmap = devm_regmap_init_mmio_clk(dev, NULL, base,
285 &imx2_wdt_regmap_config);
286 if (IS_ERR(wdev->regmap)) {
287 dev_err(dev, "regmap init failed\n");
288 return PTR_ERR(wdev->regmap);
289 }
290
291 wdev->clk = devm_clk_get(dev, NULL);
292 if (IS_ERR(wdev->clk)) {
293 dev_err(dev, "can't get Watchdog clock\n");
294 return PTR_ERR(wdev->clk);
295 }
296
297 wdog = &wdev->wdog;
298 wdog->info = &imx2_wdt_info;
299 wdog->ops = &imx2_wdt_ops;
300 wdog->min_timeout = 1;
301 wdog->timeout = IMX2_WDT_DEFAULT_TIME;
302 wdog->max_hw_heartbeat_ms = IMX2_WDT_MAX_TIME * 1000;
303 wdog->parent = dev;
304
305 wdev->data = of_device_get_match_data(dev);
306
307 ret = platform_get_irq(pdev, 0);
308 if (ret > 0)
309 if (!devm_request_irq(dev, ret, imx2_wdt_isr, 0,
310 dev_name(dev), wdog))
311 wdog->info = &imx2_wdt_pretimeout_info;
312
313 ret = clk_prepare_enable(wdev->clk);
314 if (ret)
315 return ret;
316
317 ret = devm_add_action_or_reset(dev, imx2_wdt_action, wdev->clk);
318 if (ret)
319 return ret;
320
321 wdev->clk_is_on = true;
322
323 regmap_read(wdev->regmap, IMX2_WDT_WRSR, &val);
324 wdog->bootstatus = val & IMX2_WDT_WRSR_TOUT ? WDIOF_CARDRESET : 0;
325
326 wdev->ext_reset = of_property_read_bool(dev->of_node,
327 "fsl,ext-reset-output");
328
329 if (of_property_read_bool(dev->of_node, "fsl,suspend-in-wait")) {
330 if (!wdev->data->wdw_supported) {
331 dev_err(dev, "suspend-in-wait not supported\n");
332 return -EINVAL;
333 }
334 wdev->sleep_wait = true;
335 }
336
337 /*
338 * The i.MX7D doesn't support low power mode, so we need to ping the watchdog
339 * during suspend. Interaction with "fsl,suspend-in-wait" is unknown!
340 */
341 wdev->no_ping = !of_device_is_compatible(dev->of_node, "fsl,imx7d-wdt");
342 platform_set_drvdata(pdev, wdog);
343 watchdog_set_drvdata(wdog, wdev);
344 watchdog_set_nowayout(wdog, nowayout);
345 watchdog_set_restart_priority(wdog, 128);
346 watchdog_init_timeout(wdog, timeout, dev);
347 if (wdev->no_ping)
348 watchdog_stop_ping_on_suspend(wdog);
349
350 if (imx2_wdt_is_running(wdev)) {
351 imx2_wdt_set_timeout(wdog, wdog->timeout);
352 set_bit(WDOG_HW_RUNNING, &wdog->status);
353 }
354
355 /*
356 * Disable the watchdog power down counter at boot. Otherwise the power
357 * down counter will pull down the #WDOG interrupt line for one clock
358 * cycle.
359 */
360 regmap_write(wdev->regmap, IMX2_WDT_WMCR, 0);
361
362 return devm_watchdog_register_device(dev, wdog);
363}
364
365static void imx2_wdt_shutdown(struct platform_device *pdev)
366{
367 struct watchdog_device *wdog = platform_get_drvdata(pdev);
368 struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
369
370 if (imx2_wdt_is_running(wdev)) {
371 /*
372 * We are running, configure max timeout before reboot
373 * will take place.
374 */
375 imx2_wdt_set_timeout(wdog, IMX2_WDT_MAX_TIME);
376 imx2_wdt_ping(wdog);
377 dev_crit(&pdev->dev, "Device shutdown.\n");
378 }
379}
380
381/* Disable watchdog if it is active or non-active but still running */
382static int __maybe_unused imx2_wdt_suspend(struct device *dev)
383{
384 struct watchdog_device *wdog = dev_get_drvdata(dev);
385 struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
386
387 /* The watchdog IP block is running */
388 if (imx2_wdt_is_running(wdev)) {
389 /*
390 * Don't update wdog->timeout, we'll restore the current value
391 * during resume.
392 */
393 __imx2_wdt_set_timeout(wdog, IMX2_WDT_MAX_TIME);
394 imx2_wdt_ping(wdog);
395 }
396
397 if (wdev->no_ping) {
398 clk_disable_unprepare(wdev->clk);
399
400 wdev->clk_is_on = false;
401 }
402
403 return 0;
404}
405
406/* Enable watchdog and configure it if necessary */
407static int __maybe_unused imx2_wdt_resume(struct device *dev)
408{
409 struct watchdog_device *wdog = dev_get_drvdata(dev);
410 struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
411 int ret;
412
413 if (wdev->no_ping) {
414 ret = clk_prepare_enable(wdev->clk);
415
416 if (ret)
417 return ret;
418
419 wdev->clk_is_on = true;
420 }
421
422 if (watchdog_active(wdog) && !imx2_wdt_is_running(wdev)) {
423 /*
424 * If the watchdog is still active and resumes
425 * from deep sleep state, need to restart the
426 * watchdog again.
427 */
428 imx2_wdt_setup(wdog);
429 }
430 if (imx2_wdt_is_running(wdev)) {
431 imx2_wdt_set_timeout(wdog, wdog->timeout);
432 imx2_wdt_ping(wdog);
433 }
434
435 return 0;
436}
437
438static SIMPLE_DEV_PM_OPS(imx2_wdt_pm_ops, imx2_wdt_suspend,
439 imx2_wdt_resume);
440
441static struct imx2_wdt_data imx_wdt = {
442 .wdw_supported = true,
443};
444
445static struct imx2_wdt_data imx_wdt_legacy = {
446 .wdw_supported = false,
447};
448
449static const struct of_device_id imx2_wdt_dt_ids[] = {
450 { .compatible = "fsl,imx21-wdt", .data = &imx_wdt_legacy },
451 { .compatible = "fsl,imx25-wdt", .data = &imx_wdt },
452 { .compatible = "fsl,imx27-wdt", .data = &imx_wdt_legacy },
453 { .compatible = "fsl,imx31-wdt", .data = &imx_wdt_legacy },
454 { .compatible = "fsl,imx35-wdt", .data = &imx_wdt },
455 { .compatible = "fsl,imx50-wdt", .data = &imx_wdt },
456 { .compatible = "fsl,imx51-wdt", .data = &imx_wdt },
457 { .compatible = "fsl,imx53-wdt", .data = &imx_wdt },
458 { .compatible = "fsl,imx6q-wdt", .data = &imx_wdt },
459 { .compatible = "fsl,imx6sl-wdt", .data = &imx_wdt },
460 { .compatible = "fsl,imx6sll-wdt", .data = &imx_wdt },
461 { .compatible = "fsl,imx6sx-wdt", .data = &imx_wdt },
462 { .compatible = "fsl,imx6ul-wdt", .data = &imx_wdt },
463 { .compatible = "fsl,imx7d-wdt", .data = &imx_wdt },
464 { .compatible = "fsl,imx8mm-wdt", .data = &imx_wdt },
465 { .compatible = "fsl,imx8mn-wdt", .data = &imx_wdt },
466 { .compatible = "fsl,imx8mp-wdt", .data = &imx_wdt },
467 { .compatible = "fsl,imx8mq-wdt", .data = &imx_wdt },
468 { .compatible = "fsl,ls1012a-wdt", .data = &imx_wdt_legacy },
469 { .compatible = "fsl,ls1043a-wdt", .data = &imx_wdt_legacy },
470 { .compatible = "fsl,vf610-wdt", .data = &imx_wdt },
471 { /* sentinel */ }
472};
473MODULE_DEVICE_TABLE(of, imx2_wdt_dt_ids);
474
475static struct platform_driver imx2_wdt_driver = {
476 .shutdown = imx2_wdt_shutdown,
477 .driver = {
478 .name = DRIVER_NAME,
479 .pm = &imx2_wdt_pm_ops,
480 .of_match_table = imx2_wdt_dt_ids,
481 },
482};
483
484module_platform_driver_probe(imx2_wdt_driver, imx2_wdt_probe);
485
486MODULE_AUTHOR("Wolfram Sang");
487MODULE_DESCRIPTION("Watchdog driver for IMX2 and later");
488MODULE_LICENSE("GPL v2");
489MODULE_ALIAS("platform:" DRIVER_NAME);