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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Watchdog driver for IMX2 and later processors
4 *
5 * Copyright (C) 2010 Wolfram Sang, Pengutronix e.K. <kernel@pengutronix.de>
6 * Copyright (C) 2014 Freescale Semiconductor, Inc.
7 *
8 * some parts adapted by similar drivers from Darius Augulis and Vladimir
9 * Zapolskiy, additional improvements by Wim Van Sebroeck.
10 *
11 * NOTE: MX1 has a slightly different Watchdog than MX2 and later:
12 *
13 * MX1: MX2+:
14 * ---- -----
15 * Registers: 32-bit 16-bit
16 * Stopable timer: Yes No
17 * Need to enable clk: No Yes
18 * Halt on suspend: Manual Can be automatic
19 */
20
21#include <linux/clk.h>
22#include <linux/delay.h>
23#include <linux/init.h>
24#include <linux/interrupt.h>
25#include <linux/io.h>
26#include <linux/kernel.h>
27#include <linux/module.h>
28#include <linux/moduleparam.h>
29#include <linux/of_address.h>
30#include <linux/platform_device.h>
31#include <linux/regmap.h>
32#include <linux/watchdog.h>
33
34#define DRIVER_NAME "imx2-wdt"
35
36#define IMX2_WDT_WCR 0x00 /* Control Register */
37#define IMX2_WDT_WCR_WT (0xFF << 8) /* -> Watchdog Timeout Field */
38#define IMX2_WDT_WCR_WDA BIT(5) /* -> External Reset WDOG_B */
39#define IMX2_WDT_WCR_SRS BIT(4) /* -> Software Reset Signal */
40#define IMX2_WDT_WCR_WRE BIT(3) /* -> WDOG Reset Enable */
41#define IMX2_WDT_WCR_WDE BIT(2) /* -> Watchdog Enable */
42#define IMX2_WDT_WCR_WDZST BIT(0) /* -> Watchdog timer Suspend */
43
44#define IMX2_WDT_WSR 0x02 /* Service Register */
45#define IMX2_WDT_SEQ1 0x5555 /* -> service sequence 1 */
46#define IMX2_WDT_SEQ2 0xAAAA /* -> service sequence 2 */
47
48#define IMX2_WDT_WRSR 0x04 /* Reset Status Register */
49#define IMX2_WDT_WRSR_TOUT BIT(1) /* -> Reset due to Timeout */
50
51#define IMX2_WDT_WICR 0x06 /* Interrupt Control Register */
52#define IMX2_WDT_WICR_WIE BIT(15) /* -> Interrupt Enable */
53#define IMX2_WDT_WICR_WTIS BIT(14) /* -> Interrupt Status */
54#define IMX2_WDT_WICR_WICT 0xFF /* -> Interrupt Count Timeout */
55
56#define IMX2_WDT_WMCR 0x08 /* Misc Register */
57
58#define IMX2_WDT_MAX_TIME 128U
59#define IMX2_WDT_DEFAULT_TIME 60 /* in seconds */
60
61#define WDOG_SEC_TO_COUNT(s) ((s * 2 - 1) << 8)
62
63struct imx2_wdt_device {
64 struct clk *clk;
65 struct regmap *regmap;
66 struct watchdog_device wdog;
67 bool ext_reset;
68};
69
70static bool nowayout = WATCHDOG_NOWAYOUT;
71module_param(nowayout, bool, 0);
72MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default="
73 __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
74
75static unsigned timeout;
76module_param(timeout, uint, 0);
77MODULE_PARM_DESC(timeout, "Watchdog timeout in seconds (default="
78 __MODULE_STRING(IMX2_WDT_DEFAULT_TIME) ")");
79
80static const struct watchdog_info imx2_wdt_info = {
81 .identity = "imx2+ watchdog",
82 .options = WDIOF_KEEPALIVEPING | WDIOF_SETTIMEOUT | WDIOF_MAGICCLOSE,
83};
84
85static const struct watchdog_info imx2_wdt_pretimeout_info = {
86 .identity = "imx2+ watchdog",
87 .options = WDIOF_KEEPALIVEPING | WDIOF_SETTIMEOUT | WDIOF_MAGICCLOSE |
88 WDIOF_PRETIMEOUT,
89};
90
91static int imx2_wdt_restart(struct watchdog_device *wdog, unsigned long action,
92 void *data)
93{
94 struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
95 unsigned int wcr_enable = IMX2_WDT_WCR_WDE;
96
97 /* Use internal reset or external - not both */
98 if (wdev->ext_reset)
99 wcr_enable |= IMX2_WDT_WCR_SRS; /* do not assert int reset */
100 else
101 wcr_enable |= IMX2_WDT_WCR_WDA; /* do not assert ext-reset */
102
103 /* Assert SRS signal */
104 regmap_write(wdev->regmap, IMX2_WDT_WCR, wcr_enable);
105 /*
106 * Due to imx6q errata ERR004346 (WDOG: WDOG SRS bit requires to be
107 * written twice), we add another two writes to ensure there must be at
108 * least two writes happen in the same one 32kHz clock period. We save
109 * the target check here, since the writes shouldn't be a huge burden
110 * for other platforms.
111 */
112 regmap_write(wdev->regmap, IMX2_WDT_WCR, wcr_enable);
113 regmap_write(wdev->regmap, IMX2_WDT_WCR, wcr_enable);
114
115 /* wait for reset to assert... */
116 mdelay(500);
117
118 return 0;
119}
120
121static inline void imx2_wdt_setup(struct watchdog_device *wdog)
122{
123 struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
124 u32 val;
125
126 regmap_read(wdev->regmap, IMX2_WDT_WCR, &val);
127
128 /* Suspend timer in low power mode, write once-only */
129 val |= IMX2_WDT_WCR_WDZST;
130 /* Strip the old watchdog Time-Out value */
131 val &= ~IMX2_WDT_WCR_WT;
132 /* Generate internal chip-level reset if WDOG times out */
133 if (!wdev->ext_reset)
134 val &= ~IMX2_WDT_WCR_WRE;
135 /* Or if external-reset assert WDOG_B reset only on time-out */
136 else
137 val |= IMX2_WDT_WCR_WRE;
138 /* Keep Watchdog Disabled */
139 val &= ~IMX2_WDT_WCR_WDE;
140 /* Set the watchdog's Time-Out value */
141 val |= WDOG_SEC_TO_COUNT(wdog->timeout);
142
143 regmap_write(wdev->regmap, IMX2_WDT_WCR, val);
144
145 /* enable the watchdog */
146 val |= IMX2_WDT_WCR_WDE;
147 regmap_write(wdev->regmap, IMX2_WDT_WCR, val);
148}
149
150static inline bool imx2_wdt_is_running(struct imx2_wdt_device *wdev)
151{
152 u32 val;
153
154 regmap_read(wdev->regmap, IMX2_WDT_WCR, &val);
155
156 return val & IMX2_WDT_WCR_WDE;
157}
158
159static int imx2_wdt_ping(struct watchdog_device *wdog)
160{
161 struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
162
163 regmap_write(wdev->regmap, IMX2_WDT_WSR, IMX2_WDT_SEQ1);
164 regmap_write(wdev->regmap, IMX2_WDT_WSR, IMX2_WDT_SEQ2);
165 return 0;
166}
167
168static void __imx2_wdt_set_timeout(struct watchdog_device *wdog,
169 unsigned int new_timeout)
170{
171 struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
172
173 regmap_update_bits(wdev->regmap, IMX2_WDT_WCR, IMX2_WDT_WCR_WT,
174 WDOG_SEC_TO_COUNT(new_timeout));
175}
176
177static int imx2_wdt_set_timeout(struct watchdog_device *wdog,
178 unsigned int new_timeout)
179{
180 unsigned int actual;
181
182 actual = min(new_timeout, IMX2_WDT_MAX_TIME);
183 __imx2_wdt_set_timeout(wdog, actual);
184 wdog->timeout = new_timeout;
185 return 0;
186}
187
188static int imx2_wdt_set_pretimeout(struct watchdog_device *wdog,
189 unsigned int new_pretimeout)
190{
191 struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
192
193 if (new_pretimeout >= IMX2_WDT_MAX_TIME)
194 return -EINVAL;
195
196 wdog->pretimeout = new_pretimeout;
197
198 regmap_update_bits(wdev->regmap, IMX2_WDT_WICR,
199 IMX2_WDT_WICR_WIE | IMX2_WDT_WICR_WICT,
200 IMX2_WDT_WICR_WIE | (new_pretimeout << 1));
201 return 0;
202}
203
204static irqreturn_t imx2_wdt_isr(int irq, void *wdog_arg)
205{
206 struct watchdog_device *wdog = wdog_arg;
207 struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
208
209 regmap_write_bits(wdev->regmap, IMX2_WDT_WICR,
210 IMX2_WDT_WICR_WTIS, IMX2_WDT_WICR_WTIS);
211
212 watchdog_notify_pretimeout(wdog);
213
214 return IRQ_HANDLED;
215}
216
217static int imx2_wdt_start(struct watchdog_device *wdog)
218{
219 struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
220
221 if (imx2_wdt_is_running(wdev))
222 imx2_wdt_set_timeout(wdog, wdog->timeout);
223 else
224 imx2_wdt_setup(wdog);
225
226 set_bit(WDOG_HW_RUNNING, &wdog->status);
227
228 return imx2_wdt_ping(wdog);
229}
230
231static const struct watchdog_ops imx2_wdt_ops = {
232 .owner = THIS_MODULE,
233 .start = imx2_wdt_start,
234 .ping = imx2_wdt_ping,
235 .set_timeout = imx2_wdt_set_timeout,
236 .set_pretimeout = imx2_wdt_set_pretimeout,
237 .restart = imx2_wdt_restart,
238};
239
240static const struct regmap_config imx2_wdt_regmap_config = {
241 .reg_bits = 16,
242 .reg_stride = 2,
243 .val_bits = 16,
244 .max_register = 0x8,
245};
246
247static void imx2_wdt_action(void *data)
248{
249 clk_disable_unprepare(data);
250}
251
252static int __init imx2_wdt_probe(struct platform_device *pdev)
253{
254 struct device *dev = &pdev->dev;
255 struct imx2_wdt_device *wdev;
256 struct watchdog_device *wdog;
257 void __iomem *base;
258 int ret;
259 u32 val;
260
261 wdev = devm_kzalloc(dev, sizeof(*wdev), GFP_KERNEL);
262 if (!wdev)
263 return -ENOMEM;
264
265 base = devm_platform_ioremap_resource(pdev, 0);
266 if (IS_ERR(base))
267 return PTR_ERR(base);
268
269 wdev->regmap = devm_regmap_init_mmio_clk(dev, NULL, base,
270 &imx2_wdt_regmap_config);
271 if (IS_ERR(wdev->regmap)) {
272 dev_err(dev, "regmap init failed\n");
273 return PTR_ERR(wdev->regmap);
274 }
275
276 wdev->clk = devm_clk_get(dev, NULL);
277 if (IS_ERR(wdev->clk)) {
278 dev_err(dev, "can't get Watchdog clock\n");
279 return PTR_ERR(wdev->clk);
280 }
281
282 wdog = &wdev->wdog;
283 wdog->info = &imx2_wdt_info;
284 wdog->ops = &imx2_wdt_ops;
285 wdog->min_timeout = 1;
286 wdog->timeout = IMX2_WDT_DEFAULT_TIME;
287 wdog->max_hw_heartbeat_ms = IMX2_WDT_MAX_TIME * 1000;
288 wdog->parent = dev;
289
290 ret = platform_get_irq(pdev, 0);
291 if (ret > 0)
292 if (!devm_request_irq(dev, ret, imx2_wdt_isr, 0,
293 dev_name(dev), wdog))
294 wdog->info = &imx2_wdt_pretimeout_info;
295
296 ret = clk_prepare_enable(wdev->clk);
297 if (ret)
298 return ret;
299
300 ret = devm_add_action_or_reset(dev, imx2_wdt_action, wdev->clk);
301 if (ret)
302 return ret;
303
304 regmap_read(wdev->regmap, IMX2_WDT_WRSR, &val);
305 wdog->bootstatus = val & IMX2_WDT_WRSR_TOUT ? WDIOF_CARDRESET : 0;
306
307 wdev->ext_reset = of_property_read_bool(dev->of_node,
308 "fsl,ext-reset-output");
309 platform_set_drvdata(pdev, wdog);
310 watchdog_set_drvdata(wdog, wdev);
311 watchdog_set_nowayout(wdog, nowayout);
312 watchdog_set_restart_priority(wdog, 128);
313 watchdog_init_timeout(wdog, timeout, dev);
314
315 if (imx2_wdt_is_running(wdev)) {
316 imx2_wdt_set_timeout(wdog, wdog->timeout);
317 set_bit(WDOG_HW_RUNNING, &wdog->status);
318 }
319
320 /*
321 * Disable the watchdog power down counter at boot. Otherwise the power
322 * down counter will pull down the #WDOG interrupt line for one clock
323 * cycle.
324 */
325 regmap_write(wdev->regmap, IMX2_WDT_WMCR, 0);
326
327 return devm_watchdog_register_device(dev, wdog);
328}
329
330static void imx2_wdt_shutdown(struct platform_device *pdev)
331{
332 struct watchdog_device *wdog = platform_get_drvdata(pdev);
333 struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
334
335 if (imx2_wdt_is_running(wdev)) {
336 /*
337 * We are running, configure max timeout before reboot
338 * will take place.
339 */
340 imx2_wdt_set_timeout(wdog, IMX2_WDT_MAX_TIME);
341 imx2_wdt_ping(wdog);
342 dev_crit(&pdev->dev, "Device shutdown: Expect reboot!\n");
343 }
344}
345
346/* Disable watchdog if it is active or non-active but still running */
347static int __maybe_unused imx2_wdt_suspend(struct device *dev)
348{
349 struct watchdog_device *wdog = dev_get_drvdata(dev);
350 struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
351
352 /* The watchdog IP block is running */
353 if (imx2_wdt_is_running(wdev)) {
354 /*
355 * Don't update wdog->timeout, we'll restore the current value
356 * during resume.
357 */
358 __imx2_wdt_set_timeout(wdog, IMX2_WDT_MAX_TIME);
359 imx2_wdt_ping(wdog);
360 }
361
362 clk_disable_unprepare(wdev->clk);
363
364 return 0;
365}
366
367/* Enable watchdog and configure it if necessary */
368static int __maybe_unused imx2_wdt_resume(struct device *dev)
369{
370 struct watchdog_device *wdog = dev_get_drvdata(dev);
371 struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
372 int ret;
373
374 ret = clk_prepare_enable(wdev->clk);
375 if (ret)
376 return ret;
377
378 if (watchdog_active(wdog) && !imx2_wdt_is_running(wdev)) {
379 /*
380 * If the watchdog is still active and resumes
381 * from deep sleep state, need to restart the
382 * watchdog again.
383 */
384 imx2_wdt_setup(wdog);
385 }
386 if (imx2_wdt_is_running(wdev)) {
387 imx2_wdt_set_timeout(wdog, wdog->timeout);
388 imx2_wdt_ping(wdog);
389 }
390
391 return 0;
392}
393
394static SIMPLE_DEV_PM_OPS(imx2_wdt_pm_ops, imx2_wdt_suspend,
395 imx2_wdt_resume);
396
397static const struct of_device_id imx2_wdt_dt_ids[] = {
398 { .compatible = "fsl,imx21-wdt", },
399 { /* sentinel */ }
400};
401MODULE_DEVICE_TABLE(of, imx2_wdt_dt_ids);
402
403static struct platform_driver imx2_wdt_driver = {
404 .shutdown = imx2_wdt_shutdown,
405 .driver = {
406 .name = DRIVER_NAME,
407 .pm = &imx2_wdt_pm_ops,
408 .of_match_table = imx2_wdt_dt_ids,
409 },
410};
411
412module_platform_driver_probe(imx2_wdt_driver, imx2_wdt_probe);
413
414MODULE_AUTHOR("Wolfram Sang");
415MODULE_DESCRIPTION("Watchdog driver for IMX2 and later");
416MODULE_LICENSE("GPL v2");
417MODULE_ALIAS("platform:" DRIVER_NAME);
1/*
2 * Watchdog driver for IMX2 and later processors
3 *
4 * Copyright (C) 2010 Wolfram Sang, Pengutronix e.K. <w.sang@pengutronix.de>
5 *
6 * some parts adapted by similar drivers from Darius Augulis and Vladimir
7 * Zapolskiy, additional improvements by Wim Van Sebroeck.
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License version 2 as published by
11 * the Free Software Foundation.
12 *
13 * NOTE: MX1 has a slightly different Watchdog than MX2 and later:
14 *
15 * MX1: MX2+:
16 * ---- -----
17 * Registers: 32-bit 16-bit
18 * Stopable timer: Yes No
19 * Need to enable clk: No Yes
20 * Halt on suspend: Manual Can be automatic
21 */
22
23#include <linux/init.h>
24#include <linux/kernel.h>
25#include <linux/miscdevice.h>
26#include <linux/module.h>
27#include <linux/moduleparam.h>
28#include <linux/platform_device.h>
29#include <linux/watchdog.h>
30#include <linux/clk.h>
31#include <linux/fs.h>
32#include <linux/io.h>
33#include <linux/uaccess.h>
34#include <linux/timer.h>
35#include <linux/jiffies.h>
36#include <mach/hardware.h>
37
38#define DRIVER_NAME "imx2-wdt"
39
40#define IMX2_WDT_WCR 0x00 /* Control Register */
41#define IMX2_WDT_WCR_WT (0xFF << 8) /* -> Watchdog Timeout Field */
42#define IMX2_WDT_WCR_WRE (1 << 3) /* -> WDOG Reset Enable */
43#define IMX2_WDT_WCR_WDE (1 << 2) /* -> Watchdog Enable */
44
45#define IMX2_WDT_WSR 0x02 /* Service Register */
46#define IMX2_WDT_SEQ1 0x5555 /* -> service sequence 1 */
47#define IMX2_WDT_SEQ2 0xAAAA /* -> service sequence 2 */
48
49#define IMX2_WDT_WRSR 0x04 /* Reset Status Register */
50#define IMX2_WDT_WRSR_TOUT (1 << 1) /* -> Reset due to Timeout */
51
52#define IMX2_WDT_MAX_TIME 128
53#define IMX2_WDT_DEFAULT_TIME 60 /* in seconds */
54
55#define WDOG_SEC_TO_COUNT(s) ((s * 2 - 1) << 8)
56
57#define IMX2_WDT_STATUS_OPEN 0
58#define IMX2_WDT_STATUS_STARTED 1
59#define IMX2_WDT_EXPECT_CLOSE 2
60
61static struct {
62 struct clk *clk;
63 void __iomem *base;
64 unsigned timeout;
65 unsigned long status;
66 struct timer_list timer; /* Pings the watchdog when closed */
67} imx2_wdt;
68
69static struct miscdevice imx2_wdt_miscdev;
70
71static bool nowayout = WATCHDOG_NOWAYOUT;
72module_param(nowayout, bool, 0);
73MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default="
74 __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
75
76
77static unsigned timeout = IMX2_WDT_DEFAULT_TIME;
78module_param(timeout, uint, 0);
79MODULE_PARM_DESC(timeout, "Watchdog timeout in seconds (default="
80 __MODULE_STRING(IMX2_WDT_DEFAULT_TIME) ")");
81
82static const struct watchdog_info imx2_wdt_info = {
83 .identity = "imx2+ watchdog",
84 .options = WDIOF_KEEPALIVEPING | WDIOF_SETTIMEOUT | WDIOF_MAGICCLOSE,
85};
86
87static inline void imx2_wdt_setup(void)
88{
89 u16 val = __raw_readw(imx2_wdt.base + IMX2_WDT_WCR);
90
91 /* Strip the old watchdog Time-Out value */
92 val &= ~IMX2_WDT_WCR_WT;
93 /* Generate reset if WDOG times out */
94 val &= ~IMX2_WDT_WCR_WRE;
95 /* Keep Watchdog Disabled */
96 val &= ~IMX2_WDT_WCR_WDE;
97 /* Set the watchdog's Time-Out value */
98 val |= WDOG_SEC_TO_COUNT(imx2_wdt.timeout);
99
100 __raw_writew(val, imx2_wdt.base + IMX2_WDT_WCR);
101
102 /* enable the watchdog */
103 val |= IMX2_WDT_WCR_WDE;
104 __raw_writew(val, imx2_wdt.base + IMX2_WDT_WCR);
105}
106
107static inline void imx2_wdt_ping(void)
108{
109 __raw_writew(IMX2_WDT_SEQ1, imx2_wdt.base + IMX2_WDT_WSR);
110 __raw_writew(IMX2_WDT_SEQ2, imx2_wdt.base + IMX2_WDT_WSR);
111}
112
113static void imx2_wdt_timer_ping(unsigned long arg)
114{
115 /* ping it every imx2_wdt.timeout / 2 seconds to prevent reboot */
116 imx2_wdt_ping();
117 mod_timer(&imx2_wdt.timer, jiffies + imx2_wdt.timeout * HZ / 2);
118}
119
120static void imx2_wdt_start(void)
121{
122 if (!test_and_set_bit(IMX2_WDT_STATUS_STARTED, &imx2_wdt.status)) {
123 /* at our first start we enable clock and do initialisations */
124 clk_prepare_enable(imx2_wdt.clk);
125
126 imx2_wdt_setup();
127 } else /* delete the timer that pings the watchdog after close */
128 del_timer_sync(&imx2_wdt.timer);
129
130 /* Watchdog is enabled - time to reload the timeout value */
131 imx2_wdt_ping();
132}
133
134static void imx2_wdt_stop(void)
135{
136 /* we don't need a clk_disable, it cannot be disabled once started.
137 * We use a timer to ping the watchdog while /dev/watchdog is closed */
138 imx2_wdt_timer_ping(0);
139}
140
141static void imx2_wdt_set_timeout(int new_timeout)
142{
143 u16 val = __raw_readw(imx2_wdt.base + IMX2_WDT_WCR);
144
145 /* set the new timeout value in the WSR */
146 val &= ~IMX2_WDT_WCR_WT;
147 val |= WDOG_SEC_TO_COUNT(new_timeout);
148 __raw_writew(val, imx2_wdt.base + IMX2_WDT_WCR);
149}
150
151static int imx2_wdt_open(struct inode *inode, struct file *file)
152{
153 if (test_and_set_bit(IMX2_WDT_STATUS_OPEN, &imx2_wdt.status))
154 return -EBUSY;
155
156 imx2_wdt_start();
157 return nonseekable_open(inode, file);
158}
159
160static int imx2_wdt_close(struct inode *inode, struct file *file)
161{
162 if (test_bit(IMX2_WDT_EXPECT_CLOSE, &imx2_wdt.status) && !nowayout)
163 imx2_wdt_stop();
164 else {
165 dev_crit(imx2_wdt_miscdev.parent,
166 "Unexpected close: Expect reboot!\n");
167 imx2_wdt_ping();
168 }
169
170 clear_bit(IMX2_WDT_EXPECT_CLOSE, &imx2_wdt.status);
171 clear_bit(IMX2_WDT_STATUS_OPEN, &imx2_wdt.status);
172 return 0;
173}
174
175static long imx2_wdt_ioctl(struct file *file, unsigned int cmd,
176 unsigned long arg)
177{
178 void __user *argp = (void __user *)arg;
179 int __user *p = argp;
180 int new_value;
181 u16 val;
182
183 switch (cmd) {
184 case WDIOC_GETSUPPORT:
185 return copy_to_user(argp, &imx2_wdt_info,
186 sizeof(struct watchdog_info)) ? -EFAULT : 0;
187
188 case WDIOC_GETSTATUS:
189 return put_user(0, p);
190
191 case WDIOC_GETBOOTSTATUS:
192 val = __raw_readw(imx2_wdt.base + IMX2_WDT_WRSR);
193 new_value = val & IMX2_WDT_WRSR_TOUT ? WDIOF_CARDRESET : 0;
194 return put_user(new_value, p);
195
196 case WDIOC_KEEPALIVE:
197 imx2_wdt_ping();
198 return 0;
199
200 case WDIOC_SETTIMEOUT:
201 if (get_user(new_value, p))
202 return -EFAULT;
203 if ((new_value < 1) || (new_value > IMX2_WDT_MAX_TIME))
204 return -EINVAL;
205 imx2_wdt_set_timeout(new_value);
206 imx2_wdt.timeout = new_value;
207 imx2_wdt_ping();
208
209 /* Fallthrough to return current value */
210 case WDIOC_GETTIMEOUT:
211 return put_user(imx2_wdt.timeout, p);
212
213 default:
214 return -ENOTTY;
215 }
216}
217
218static ssize_t imx2_wdt_write(struct file *file, const char __user *data,
219 size_t len, loff_t *ppos)
220{
221 size_t i;
222 char c;
223
224 if (len == 0) /* Can we see this even ? */
225 return 0;
226
227 clear_bit(IMX2_WDT_EXPECT_CLOSE, &imx2_wdt.status);
228 /* scan to see whether or not we got the magic character */
229 for (i = 0; i != len; i++) {
230 if (get_user(c, data + i))
231 return -EFAULT;
232 if (c == 'V')
233 set_bit(IMX2_WDT_EXPECT_CLOSE, &imx2_wdt.status);
234 }
235
236 imx2_wdt_ping();
237 return len;
238}
239
240static const struct file_operations imx2_wdt_fops = {
241 .owner = THIS_MODULE,
242 .llseek = no_llseek,
243 .unlocked_ioctl = imx2_wdt_ioctl,
244 .open = imx2_wdt_open,
245 .release = imx2_wdt_close,
246 .write = imx2_wdt_write,
247};
248
249static struct miscdevice imx2_wdt_miscdev = {
250 .minor = WATCHDOG_MINOR,
251 .name = "watchdog",
252 .fops = &imx2_wdt_fops,
253};
254
255static int __init imx2_wdt_probe(struct platform_device *pdev)
256{
257 int ret;
258 struct resource *res;
259
260 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
261 if (!res) {
262 dev_err(&pdev->dev, "can't get device resources\n");
263 return -ENODEV;
264 }
265
266 imx2_wdt.base = devm_request_and_ioremap(&pdev->dev, res);
267 if (!imx2_wdt.base) {
268 dev_err(&pdev->dev, "ioremap failed\n");
269 return -ENOMEM;
270 }
271
272 imx2_wdt.clk = clk_get(&pdev->dev, NULL);
273 if (IS_ERR(imx2_wdt.clk)) {
274 dev_err(&pdev->dev, "can't get Watchdog clock\n");
275 return PTR_ERR(imx2_wdt.clk);
276 }
277
278 imx2_wdt.timeout = clamp_t(unsigned, timeout, 1, IMX2_WDT_MAX_TIME);
279 if (imx2_wdt.timeout != timeout)
280 dev_warn(&pdev->dev, "Initial timeout out of range! "
281 "Clamped from %u to %u\n", timeout, imx2_wdt.timeout);
282
283 setup_timer(&imx2_wdt.timer, imx2_wdt_timer_ping, 0);
284
285 imx2_wdt_miscdev.parent = &pdev->dev;
286 ret = misc_register(&imx2_wdt_miscdev);
287 if (ret)
288 goto fail;
289
290 dev_info(&pdev->dev,
291 "IMX2+ Watchdog Timer enabled. timeout=%ds (nowayout=%d)\n",
292 imx2_wdt.timeout, nowayout);
293 return 0;
294
295fail:
296 imx2_wdt_miscdev.parent = NULL;
297 clk_put(imx2_wdt.clk);
298 return ret;
299}
300
301static int __exit imx2_wdt_remove(struct platform_device *pdev)
302{
303 misc_deregister(&imx2_wdt_miscdev);
304
305 if (test_bit(IMX2_WDT_STATUS_STARTED, &imx2_wdt.status)) {
306 del_timer_sync(&imx2_wdt.timer);
307
308 dev_crit(imx2_wdt_miscdev.parent,
309 "Device removed: Expect reboot!\n");
310 } else
311 clk_put(imx2_wdt.clk);
312
313 imx2_wdt_miscdev.parent = NULL;
314 return 0;
315}
316
317static void imx2_wdt_shutdown(struct platform_device *pdev)
318{
319 if (test_bit(IMX2_WDT_STATUS_STARTED, &imx2_wdt.status)) {
320 /* we are running, we need to delete the timer but will give
321 * max timeout before reboot will take place */
322 del_timer_sync(&imx2_wdt.timer);
323 imx2_wdt_set_timeout(IMX2_WDT_MAX_TIME);
324 imx2_wdt_ping();
325
326 dev_crit(imx2_wdt_miscdev.parent,
327 "Device shutdown: Expect reboot!\n");
328 }
329}
330
331static const struct of_device_id imx2_wdt_dt_ids[] = {
332 { .compatible = "fsl,imx21-wdt", },
333 { /* sentinel */ }
334};
335
336static struct platform_driver imx2_wdt_driver = {
337 .remove = __exit_p(imx2_wdt_remove),
338 .shutdown = imx2_wdt_shutdown,
339 .driver = {
340 .name = DRIVER_NAME,
341 .owner = THIS_MODULE,
342 .of_match_table = imx2_wdt_dt_ids,
343 },
344};
345
346static int __init imx2_wdt_init(void)
347{
348 return platform_driver_probe(&imx2_wdt_driver, imx2_wdt_probe);
349}
350module_init(imx2_wdt_init);
351
352static void __exit imx2_wdt_exit(void)
353{
354 platform_driver_unregister(&imx2_wdt_driver);
355}
356module_exit(imx2_wdt_exit);
357
358MODULE_AUTHOR("Wolfram Sang");
359MODULE_DESCRIPTION("Watchdog driver for IMX2 and later");
360MODULE_LICENSE("GPL v2");
361MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR);
362MODULE_ALIAS("platform:" DRIVER_NAME);