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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (c) 2015, The Linux Foundation. All rights reserved.
4 */
5
6#include <linux/platform_device.h>
7
8#include "dsi_phy.h"
9
10#define S_DIV_ROUND_UP(n, d) \
11 (((n) >= 0) ? (((n) + (d) - 1) / (d)) : (((n) - (d) + 1) / (d)))
12
13static inline s32 linear_inter(s32 tmax, s32 tmin, s32 percent,
14 s32 min_result, bool even)
15{
16 s32 v;
17
18 v = (tmax - tmin) * percent;
19 v = S_DIV_ROUND_UP(v, 100) + tmin;
20 if (even && (v & 0x1))
21 return max_t(s32, min_result, v - 1);
22 else
23 return max_t(s32, min_result, v);
24}
25
26static void dsi_dphy_timing_calc_clk_zero(struct msm_dsi_dphy_timing *timing,
27 s32 ui, s32 coeff, s32 pcnt)
28{
29 s32 tmax, tmin, clk_z;
30 s32 temp;
31
32 /* reset */
33 temp = 300 * coeff - ((timing->clk_prepare >> 1) + 1) * 2 * ui;
34 tmin = S_DIV_ROUND_UP(temp, ui) - 2;
35 if (tmin > 255) {
36 tmax = 511;
37 clk_z = linear_inter(2 * tmin, tmin, pcnt, 0, true);
38 } else {
39 tmax = 255;
40 clk_z = linear_inter(tmax, tmin, pcnt, 0, true);
41 }
42
43 /* adjust */
44 temp = (timing->hs_rqst + timing->clk_prepare + clk_z) & 0x7;
45 timing->clk_zero = clk_z + 8 - temp;
46}
47
48int msm_dsi_dphy_timing_calc(struct msm_dsi_dphy_timing *timing,
49 struct msm_dsi_phy_clk_request *clk_req)
50{
51 const unsigned long bit_rate = clk_req->bitclk_rate;
52 const unsigned long esc_rate = clk_req->escclk_rate;
53 s32 ui, lpx;
54 s32 tmax, tmin;
55 s32 pcnt0 = 10;
56 s32 pcnt1 = (bit_rate > 1200000000) ? 15 : 10;
57 s32 pcnt2 = 10;
58 s32 pcnt3 = (bit_rate > 180000000) ? 10 : 40;
59 s32 coeff = 1000; /* Precision, should avoid overflow */
60 s32 temp;
61
62 if (!bit_rate || !esc_rate)
63 return -EINVAL;
64
65 ui = mult_frac(NSEC_PER_MSEC, coeff, bit_rate / 1000);
66 lpx = mult_frac(NSEC_PER_MSEC, coeff, esc_rate / 1000);
67
68 tmax = S_DIV_ROUND_UP(95 * coeff, ui) - 2;
69 tmin = S_DIV_ROUND_UP(38 * coeff, ui) - 2;
70 timing->clk_prepare = linear_inter(tmax, tmin, pcnt0, 0, true);
71
72 temp = lpx / ui;
73 if (temp & 0x1)
74 timing->hs_rqst = temp;
75 else
76 timing->hs_rqst = max_t(s32, 0, temp - 2);
77
78 /* Calculate clk_zero after clk_prepare and hs_rqst */
79 dsi_dphy_timing_calc_clk_zero(timing, ui, coeff, pcnt2);
80
81 temp = 105 * coeff + 12 * ui - 20 * coeff;
82 tmax = S_DIV_ROUND_UP(temp, ui) - 2;
83 tmin = S_DIV_ROUND_UP(60 * coeff, ui) - 2;
84 timing->clk_trail = linear_inter(tmax, tmin, pcnt3, 0, true);
85
86 temp = 85 * coeff + 6 * ui;
87 tmax = S_DIV_ROUND_UP(temp, ui) - 2;
88 temp = 40 * coeff + 4 * ui;
89 tmin = S_DIV_ROUND_UP(temp, ui) - 2;
90 timing->hs_prepare = linear_inter(tmax, tmin, pcnt1, 0, true);
91
92 tmax = 255;
93 temp = ((timing->hs_prepare >> 1) + 1) * 2 * ui + 2 * ui;
94 temp = 145 * coeff + 10 * ui - temp;
95 tmin = S_DIV_ROUND_UP(temp, ui) - 2;
96 timing->hs_zero = linear_inter(tmax, tmin, pcnt2, 24, true);
97
98 temp = 105 * coeff + 12 * ui - 20 * coeff;
99 tmax = S_DIV_ROUND_UP(temp, ui) - 2;
100 temp = 60 * coeff + 4 * ui;
101 tmin = DIV_ROUND_UP(temp, ui) - 2;
102 timing->hs_trail = linear_inter(tmax, tmin, pcnt3, 0, true);
103
104 tmax = 255;
105 tmin = S_DIV_ROUND_UP(100 * coeff, ui) - 2;
106 timing->hs_exit = linear_inter(tmax, tmin, pcnt2, 0, true);
107
108 tmax = 63;
109 temp = ((timing->hs_exit >> 1) + 1) * 2 * ui;
110 temp = 60 * coeff + 52 * ui - 24 * ui - temp;
111 tmin = S_DIV_ROUND_UP(temp, 8 * ui) - 1;
112 timing->shared_timings.clk_post = linear_inter(tmax, tmin, pcnt2, 0,
113 false);
114 tmax = 63;
115 temp = ((timing->clk_prepare >> 1) + 1) * 2 * ui;
116 temp += ((timing->clk_zero >> 1) + 1) * 2 * ui;
117 temp += 8 * ui + lpx;
118 tmin = S_DIV_ROUND_UP(temp, 8 * ui) - 1;
119 if (tmin > tmax) {
120 temp = linear_inter(2 * tmax, tmin, pcnt2, 0, false);
121 timing->shared_timings.clk_pre = temp >> 1;
122 timing->shared_timings.clk_pre_inc_by_2 = true;
123 } else {
124 timing->shared_timings.clk_pre =
125 linear_inter(tmax, tmin, pcnt2, 0, false);
126 timing->shared_timings.clk_pre_inc_by_2 = false;
127 }
128
129 timing->ta_go = 3;
130 timing->ta_sure = 0;
131 timing->ta_get = 4;
132
133 DBG("PHY timings: %d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d",
134 timing->shared_timings.clk_pre, timing->shared_timings.clk_post,
135 timing->shared_timings.clk_pre_inc_by_2, timing->clk_zero,
136 timing->clk_trail, timing->clk_prepare, timing->hs_exit,
137 timing->hs_zero, timing->hs_prepare, timing->hs_trail,
138 timing->hs_rqst);
139
140 return 0;
141}
142
143int msm_dsi_dphy_timing_calc_v2(struct msm_dsi_dphy_timing *timing,
144 struct msm_dsi_phy_clk_request *clk_req)
145{
146 const unsigned long bit_rate = clk_req->bitclk_rate;
147 const unsigned long esc_rate = clk_req->escclk_rate;
148 s32 ui, ui_x8;
149 s32 tmax, tmin;
150 s32 pcnt0 = 50;
151 s32 pcnt1 = 50;
152 s32 pcnt2 = 10;
153 s32 pcnt3 = 30;
154 s32 pcnt4 = 10;
155 s32 pcnt5 = 2;
156 s32 coeff = 1000; /* Precision, should avoid overflow */
157 s32 hb_en, hb_en_ckln, pd_ckln, pd;
158 s32 val, val_ckln;
159 s32 temp;
160
161 if (!bit_rate || !esc_rate)
162 return -EINVAL;
163
164 timing->hs_halfbyte_en = 0;
165 hb_en = 0;
166 timing->hs_halfbyte_en_ckln = 0;
167 hb_en_ckln = 0;
168 timing->hs_prep_dly_ckln = (bit_rate > 100000000) ? 0 : 3;
169 pd_ckln = timing->hs_prep_dly_ckln;
170 timing->hs_prep_dly = (bit_rate > 120000000) ? 0 : 1;
171 pd = timing->hs_prep_dly;
172
173 val = (hb_en << 2) + (pd << 1);
174 val_ckln = (hb_en_ckln << 2) + (pd_ckln << 1);
175
176 ui = mult_frac(NSEC_PER_MSEC, coeff, bit_rate / 1000);
177 ui_x8 = ui << 3;
178
179 temp = S_DIV_ROUND_UP(38 * coeff - val_ckln * ui, ui_x8);
180 tmin = max_t(s32, temp, 0);
181 temp = (95 * coeff - val_ckln * ui) / ui_x8;
182 tmax = max_t(s32, temp, 0);
183 timing->clk_prepare = linear_inter(tmax, tmin, pcnt0, 0, false);
184
185 temp = 300 * coeff - ((timing->clk_prepare << 3) + val_ckln) * ui;
186 tmin = S_DIV_ROUND_UP(temp - 11 * ui, ui_x8) - 3;
187 tmax = (tmin > 255) ? 511 : 255;
188 timing->clk_zero = linear_inter(tmax, tmin, pcnt5, 0, false);
189
190 tmin = DIV_ROUND_UP(60 * coeff + 3 * ui, ui_x8);
191 temp = 105 * coeff + 12 * ui - 20 * coeff;
192 tmax = (temp + 3 * ui) / ui_x8;
193 timing->clk_trail = linear_inter(tmax, tmin, pcnt3, 0, false);
194
195 temp = S_DIV_ROUND_UP(40 * coeff + 4 * ui - val * ui, ui_x8);
196 tmin = max_t(s32, temp, 0);
197 temp = (85 * coeff + 6 * ui - val * ui) / ui_x8;
198 tmax = max_t(s32, temp, 0);
199 timing->hs_prepare = linear_inter(tmax, tmin, pcnt1, 0, false);
200
201 temp = 145 * coeff + 10 * ui - ((timing->hs_prepare << 3) + val) * ui;
202 tmin = S_DIV_ROUND_UP(temp - 11 * ui, ui_x8) - 3;
203 tmax = 255;
204 timing->hs_zero = linear_inter(tmax, tmin, pcnt4, 0, false);
205
206 tmin = DIV_ROUND_UP(60 * coeff + 4 * ui + 3 * ui, ui_x8);
207 temp = 105 * coeff + 12 * ui - 20 * coeff;
208 tmax = (temp + 3 * ui) / ui_x8;
209 timing->hs_trail = linear_inter(tmax, tmin, pcnt3, 0, false);
210
211 temp = 50 * coeff + ((hb_en << 2) - 8) * ui;
212 timing->hs_rqst = S_DIV_ROUND_UP(temp, ui_x8);
213
214 tmin = DIV_ROUND_UP(100 * coeff, ui_x8) - 1;
215 tmax = 255;
216 timing->hs_exit = linear_inter(tmax, tmin, pcnt2, 0, false);
217
218 temp = 50 * coeff + ((hb_en_ckln << 2) - 8) * ui;
219 timing->hs_rqst_ckln = S_DIV_ROUND_UP(temp, ui_x8);
220
221 temp = 60 * coeff + 52 * ui - 43 * ui;
222 tmin = DIV_ROUND_UP(temp, ui_x8) - 1;
223 tmax = 63;
224 timing->shared_timings.clk_post =
225 linear_inter(tmax, tmin, pcnt2, 0, false);
226
227 temp = 8 * ui + ((timing->clk_prepare << 3) + val_ckln) * ui;
228 temp += (((timing->clk_zero + 3) << 3) + 11 - (pd_ckln << 1)) * ui;
229 temp += hb_en_ckln ? (((timing->hs_rqst_ckln << 3) + 4) * ui) :
230 (((timing->hs_rqst_ckln << 3) + 8) * ui);
231 tmin = S_DIV_ROUND_UP(temp, ui_x8) - 1;
232 tmax = 63;
233 if (tmin > tmax) {
234 temp = linear_inter(tmax << 1, tmin, pcnt2, 0, false);
235 timing->shared_timings.clk_pre = temp >> 1;
236 timing->shared_timings.clk_pre_inc_by_2 = 1;
237 } else {
238 timing->shared_timings.clk_pre =
239 linear_inter(tmax, tmin, pcnt2, 0, false);
240 timing->shared_timings.clk_pre_inc_by_2 = 0;
241 }
242
243 timing->ta_go = 3;
244 timing->ta_sure = 0;
245 timing->ta_get = 4;
246
247 DBG("%d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d",
248 timing->shared_timings.clk_pre, timing->shared_timings.clk_post,
249 timing->shared_timings.clk_pre_inc_by_2, timing->clk_zero,
250 timing->clk_trail, timing->clk_prepare, timing->hs_exit,
251 timing->hs_zero, timing->hs_prepare, timing->hs_trail,
252 timing->hs_rqst, timing->hs_rqst_ckln, timing->hs_halfbyte_en,
253 timing->hs_halfbyte_en_ckln, timing->hs_prep_dly,
254 timing->hs_prep_dly_ckln);
255
256 return 0;
257}
258
259int msm_dsi_dphy_timing_calc_v3(struct msm_dsi_dphy_timing *timing,
260 struct msm_dsi_phy_clk_request *clk_req)
261{
262 const unsigned long bit_rate = clk_req->bitclk_rate;
263 const unsigned long esc_rate = clk_req->escclk_rate;
264 s32 ui, ui_x8;
265 s32 tmax, tmin;
266 s32 pcnt0 = 50;
267 s32 pcnt1 = 50;
268 s32 pcnt2 = 10;
269 s32 pcnt3 = 30;
270 s32 pcnt4 = 10;
271 s32 pcnt5 = 2;
272 s32 coeff = 1000; /* Precision, should avoid overflow */
273 s32 hb_en, hb_en_ckln;
274 s32 temp;
275
276 if (!bit_rate || !esc_rate)
277 return -EINVAL;
278
279 timing->hs_halfbyte_en = 0;
280 hb_en = 0;
281 timing->hs_halfbyte_en_ckln = 0;
282 hb_en_ckln = 0;
283
284 ui = mult_frac(NSEC_PER_MSEC, coeff, bit_rate / 1000);
285 ui_x8 = ui << 3;
286
287 temp = S_DIV_ROUND_UP(38 * coeff, ui_x8);
288 tmin = max_t(s32, temp, 0);
289 temp = (95 * coeff) / ui_x8;
290 tmax = max_t(s32, temp, 0);
291 timing->clk_prepare = linear_inter(tmax, tmin, pcnt0, 0, false);
292
293 temp = 300 * coeff - (timing->clk_prepare << 3) * ui;
294 tmin = S_DIV_ROUND_UP(temp, ui_x8) - 1;
295 tmax = (tmin > 255) ? 511 : 255;
296 timing->clk_zero = linear_inter(tmax, tmin, pcnt5, 0, false);
297
298 tmin = DIV_ROUND_UP(60 * coeff + 3 * ui, ui_x8);
299 temp = 105 * coeff + 12 * ui - 20 * coeff;
300 tmax = (temp + 3 * ui) / ui_x8;
301 timing->clk_trail = linear_inter(tmax, tmin, pcnt3, 0, false);
302
303 temp = S_DIV_ROUND_UP(40 * coeff + 4 * ui, ui_x8);
304 tmin = max_t(s32, temp, 0);
305 temp = (85 * coeff + 6 * ui) / ui_x8;
306 tmax = max_t(s32, temp, 0);
307 timing->hs_prepare = linear_inter(tmax, tmin, pcnt1, 0, false);
308
309 temp = 145 * coeff + 10 * ui - (timing->hs_prepare << 3) * ui;
310 tmin = S_DIV_ROUND_UP(temp, ui_x8) - 1;
311 tmax = 255;
312 timing->hs_zero = linear_inter(tmax, tmin, pcnt4, 0, false);
313
314 tmin = DIV_ROUND_UP(60 * coeff + 4 * ui, ui_x8) - 1;
315 temp = 105 * coeff + 12 * ui - 20 * coeff;
316 tmax = (temp / ui_x8) - 1;
317 timing->hs_trail = linear_inter(tmax, tmin, pcnt3, 0, false);
318
319 temp = 50 * coeff + ((hb_en << 2) - 8) * ui;
320 timing->hs_rqst = S_DIV_ROUND_UP(temp, ui_x8);
321
322 tmin = DIV_ROUND_UP(100 * coeff, ui_x8) - 1;
323 tmax = 255;
324 timing->hs_exit = linear_inter(tmax, tmin, pcnt2, 0, false);
325
326 temp = 50 * coeff + ((hb_en_ckln << 2) - 8) * ui;
327 timing->hs_rqst_ckln = S_DIV_ROUND_UP(temp, ui_x8);
328
329 temp = 60 * coeff + 52 * ui - 43 * ui;
330 tmin = DIV_ROUND_UP(temp, ui_x8) - 1;
331 tmax = 63;
332 timing->shared_timings.clk_post =
333 linear_inter(tmax, tmin, pcnt2, 0, false);
334
335 temp = 8 * ui + (timing->clk_prepare << 3) * ui;
336 temp += (((timing->clk_zero + 3) << 3) + 11) * ui;
337 temp += hb_en_ckln ? (((timing->hs_rqst_ckln << 3) + 4) * ui) :
338 (((timing->hs_rqst_ckln << 3) + 8) * ui);
339 tmin = S_DIV_ROUND_UP(temp, ui_x8) - 1;
340 tmax = 63;
341 if (tmin > tmax) {
342 temp = linear_inter(tmax << 1, tmin, pcnt2, 0, false);
343 timing->shared_timings.clk_pre = temp >> 1;
344 timing->shared_timings.clk_pre_inc_by_2 = 1;
345 } else {
346 timing->shared_timings.clk_pre =
347 linear_inter(tmax, tmin, pcnt2, 0, false);
348 timing->shared_timings.clk_pre_inc_by_2 = 0;
349 }
350
351 timing->ta_go = 3;
352 timing->ta_sure = 0;
353 timing->ta_get = 4;
354
355 DBG("%d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d",
356 timing->shared_timings.clk_pre, timing->shared_timings.clk_post,
357 timing->shared_timings.clk_pre_inc_by_2, timing->clk_zero,
358 timing->clk_trail, timing->clk_prepare, timing->hs_exit,
359 timing->hs_zero, timing->hs_prepare, timing->hs_trail,
360 timing->hs_rqst, timing->hs_rqst_ckln, timing->hs_halfbyte_en,
361 timing->hs_halfbyte_en_ckln, timing->hs_prep_dly,
362 timing->hs_prep_dly_ckln);
363
364 return 0;
365}
366
367void msm_dsi_phy_set_src_pll(struct msm_dsi_phy *phy, int pll_id, u32 reg,
368 u32 bit_mask)
369{
370 int phy_id = phy->id;
371 u32 val;
372
373 if ((phy_id >= DSI_MAX) || (pll_id >= DSI_MAX))
374 return;
375
376 val = dsi_phy_read(phy->base + reg);
377
378 if (phy->cfg->src_pll_truthtable[phy_id][pll_id])
379 dsi_phy_write(phy->base + reg, val | bit_mask);
380 else
381 dsi_phy_write(phy->base + reg, val & (~bit_mask));
382}
383
384static int dsi_phy_regulator_init(struct msm_dsi_phy *phy)
385{
386 struct regulator_bulk_data *s = phy->supplies;
387 const struct dsi_reg_entry *regs = phy->cfg->reg_cfg.regs;
388 struct device *dev = &phy->pdev->dev;
389 int num = phy->cfg->reg_cfg.num;
390 int i, ret;
391
392 for (i = 0; i < num; i++)
393 s[i].supply = regs[i].name;
394
395 ret = devm_regulator_bulk_get(dev, num, s);
396 if (ret < 0) {
397 if (ret != -EPROBE_DEFER) {
398 DRM_DEV_ERROR(dev,
399 "%s: failed to init regulator, ret=%d\n",
400 __func__, ret);
401 }
402
403 return ret;
404 }
405
406 return 0;
407}
408
409static void dsi_phy_regulator_disable(struct msm_dsi_phy *phy)
410{
411 struct regulator_bulk_data *s = phy->supplies;
412 const struct dsi_reg_entry *regs = phy->cfg->reg_cfg.regs;
413 int num = phy->cfg->reg_cfg.num;
414 int i;
415
416 DBG("");
417 for (i = num - 1; i >= 0; i--)
418 if (regs[i].disable_load >= 0)
419 regulator_set_load(s[i].consumer, regs[i].disable_load);
420
421 regulator_bulk_disable(num, s);
422}
423
424static int dsi_phy_regulator_enable(struct msm_dsi_phy *phy)
425{
426 struct regulator_bulk_data *s = phy->supplies;
427 const struct dsi_reg_entry *regs = phy->cfg->reg_cfg.regs;
428 struct device *dev = &phy->pdev->dev;
429 int num = phy->cfg->reg_cfg.num;
430 int ret, i;
431
432 DBG("");
433 for (i = 0; i < num; i++) {
434 if (regs[i].enable_load >= 0) {
435 ret = regulator_set_load(s[i].consumer,
436 regs[i].enable_load);
437 if (ret < 0) {
438 DRM_DEV_ERROR(dev,
439 "regulator %d set op mode failed, %d\n",
440 i, ret);
441 goto fail;
442 }
443 }
444 }
445
446 ret = regulator_bulk_enable(num, s);
447 if (ret < 0) {
448 DRM_DEV_ERROR(dev, "regulator enable failed, %d\n", ret);
449 goto fail;
450 }
451
452 return 0;
453
454fail:
455 for (i--; i >= 0; i--)
456 regulator_set_load(s[i].consumer, regs[i].disable_load);
457 return ret;
458}
459
460static int dsi_phy_enable_resource(struct msm_dsi_phy *phy)
461{
462 struct device *dev = &phy->pdev->dev;
463 int ret;
464
465 pm_runtime_get_sync(dev);
466
467 ret = clk_prepare_enable(phy->ahb_clk);
468 if (ret) {
469 DRM_DEV_ERROR(dev, "%s: can't enable ahb clk, %d\n", __func__, ret);
470 pm_runtime_put_sync(dev);
471 }
472
473 return ret;
474}
475
476static void dsi_phy_disable_resource(struct msm_dsi_phy *phy)
477{
478 clk_disable_unprepare(phy->ahb_clk);
479 pm_runtime_put_autosuspend(&phy->pdev->dev);
480}
481
482static const struct of_device_id dsi_phy_dt_match[] = {
483#ifdef CONFIG_DRM_MSM_DSI_28NM_PHY
484 { .compatible = "qcom,dsi-phy-28nm-hpm",
485 .data = &dsi_phy_28nm_hpm_cfgs },
486 { .compatible = "qcom,dsi-phy-28nm-hpm-fam-b",
487 .data = &dsi_phy_28nm_hpm_famb_cfgs },
488 { .compatible = "qcom,dsi-phy-28nm-lp",
489 .data = &dsi_phy_28nm_lp_cfgs },
490#endif
491#ifdef CONFIG_DRM_MSM_DSI_20NM_PHY
492 { .compatible = "qcom,dsi-phy-20nm",
493 .data = &dsi_phy_20nm_cfgs },
494#endif
495#ifdef CONFIG_DRM_MSM_DSI_28NM_8960_PHY
496 { .compatible = "qcom,dsi-phy-28nm-8960",
497 .data = &dsi_phy_28nm_8960_cfgs },
498#endif
499#ifdef CONFIG_DRM_MSM_DSI_14NM_PHY
500 { .compatible = "qcom,dsi-phy-14nm",
501 .data = &dsi_phy_14nm_cfgs },
502 { .compatible = "qcom,dsi-phy-14nm-660",
503 .data = &dsi_phy_14nm_660_cfgs },
504#endif
505#ifdef CONFIG_DRM_MSM_DSI_10NM_PHY
506 { .compatible = "qcom,dsi-phy-10nm",
507 .data = &dsi_phy_10nm_cfgs },
508 { .compatible = "qcom,dsi-phy-10nm-8998",
509 .data = &dsi_phy_10nm_8998_cfgs },
510#endif
511 {}
512};
513
514/*
515 * Currently, we only support one SoC for each PHY type. When we have multiple
516 * SoCs for the same PHY, we can try to make the index searching a bit more
517 * clever.
518 */
519static int dsi_phy_get_id(struct msm_dsi_phy *phy)
520{
521 struct platform_device *pdev = phy->pdev;
522 const struct msm_dsi_phy_cfg *cfg = phy->cfg;
523 struct resource *res;
524 int i;
525
526 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dsi_phy");
527 if (!res)
528 return -EINVAL;
529
530 for (i = 0; i < cfg->num_dsi_phy; i++) {
531 if (cfg->io_start[i] == res->start)
532 return i;
533 }
534
535 return -EINVAL;
536}
537
538int msm_dsi_phy_init_common(struct msm_dsi_phy *phy)
539{
540 struct platform_device *pdev = phy->pdev;
541 int ret = 0;
542
543 phy->reg_base = msm_ioremap(pdev, "dsi_phy_regulator",
544 "DSI_PHY_REG");
545 if (IS_ERR(phy->reg_base)) {
546 DRM_DEV_ERROR(&pdev->dev, "%s: failed to map phy regulator base\n",
547 __func__);
548 ret = -ENOMEM;
549 goto fail;
550 }
551
552fail:
553 return ret;
554}
555
556static int dsi_phy_driver_probe(struct platform_device *pdev)
557{
558 struct msm_dsi_phy *phy;
559 struct device *dev = &pdev->dev;
560 const struct of_device_id *match;
561 int ret;
562
563 phy = devm_kzalloc(dev, sizeof(*phy), GFP_KERNEL);
564 if (!phy)
565 return -ENOMEM;
566
567 match = of_match_node(dsi_phy_dt_match, dev->of_node);
568 if (!match)
569 return -ENODEV;
570
571 phy->cfg = match->data;
572 phy->pdev = pdev;
573
574 phy->id = dsi_phy_get_id(phy);
575 if (phy->id < 0) {
576 ret = phy->id;
577 DRM_DEV_ERROR(dev, "%s: couldn't identify PHY index, %d\n",
578 __func__, ret);
579 goto fail;
580 }
581
582 phy->regulator_ldo_mode = of_property_read_bool(dev->of_node,
583 "qcom,dsi-phy-regulator-ldo-mode");
584
585 phy->base = msm_ioremap(pdev, "dsi_phy", "DSI_PHY");
586 if (IS_ERR(phy->base)) {
587 DRM_DEV_ERROR(dev, "%s: failed to map phy base\n", __func__);
588 ret = -ENOMEM;
589 goto fail;
590 }
591
592 ret = dsi_phy_regulator_init(phy);
593 if (ret)
594 goto fail;
595
596 phy->ahb_clk = msm_clk_get(pdev, "iface");
597 if (IS_ERR(phy->ahb_clk)) {
598 DRM_DEV_ERROR(dev, "%s: Unable to get ahb clk\n", __func__);
599 ret = PTR_ERR(phy->ahb_clk);
600 goto fail;
601 }
602
603 if (phy->cfg->ops.init) {
604 ret = phy->cfg->ops.init(phy);
605 if (ret)
606 goto fail;
607 }
608
609 /* PLL init will call into clk_register which requires
610 * register access, so we need to enable power and ahb clock.
611 */
612 ret = dsi_phy_enable_resource(phy);
613 if (ret)
614 goto fail;
615
616 phy->pll = msm_dsi_pll_init(pdev, phy->cfg->type, phy->id);
617 if (IS_ERR_OR_NULL(phy->pll)) {
618 DRM_DEV_INFO(dev,
619 "%s: pll init failed: %ld, need separate pll clk driver\n",
620 __func__, PTR_ERR(phy->pll));
621 phy->pll = NULL;
622 }
623
624 dsi_phy_disable_resource(phy);
625
626 platform_set_drvdata(pdev, phy);
627
628 return 0;
629
630fail:
631 return ret;
632}
633
634static int dsi_phy_driver_remove(struct platform_device *pdev)
635{
636 struct msm_dsi_phy *phy = platform_get_drvdata(pdev);
637
638 if (phy && phy->pll) {
639 msm_dsi_pll_destroy(phy->pll);
640 phy->pll = NULL;
641 }
642
643 platform_set_drvdata(pdev, NULL);
644
645 return 0;
646}
647
648static struct platform_driver dsi_phy_platform_driver = {
649 .probe = dsi_phy_driver_probe,
650 .remove = dsi_phy_driver_remove,
651 .driver = {
652 .name = "msm_dsi_phy",
653 .of_match_table = dsi_phy_dt_match,
654 },
655};
656
657void __init msm_dsi_phy_driver_register(void)
658{
659 platform_driver_register(&dsi_phy_platform_driver);
660}
661
662void __exit msm_dsi_phy_driver_unregister(void)
663{
664 platform_driver_unregister(&dsi_phy_platform_driver);
665}
666
667int msm_dsi_phy_enable(struct msm_dsi_phy *phy, int src_pll_id,
668 struct msm_dsi_phy_clk_request *clk_req)
669{
670 struct device *dev = &phy->pdev->dev;
671 int ret;
672
673 if (!phy || !phy->cfg->ops.enable)
674 return -EINVAL;
675
676 ret = dsi_phy_enable_resource(phy);
677 if (ret) {
678 DRM_DEV_ERROR(dev, "%s: resource enable failed, %d\n",
679 __func__, ret);
680 goto res_en_fail;
681 }
682
683 ret = dsi_phy_regulator_enable(phy);
684 if (ret) {
685 DRM_DEV_ERROR(dev, "%s: regulator enable failed, %d\n",
686 __func__, ret);
687 goto reg_en_fail;
688 }
689
690 ret = phy->cfg->ops.enable(phy, src_pll_id, clk_req);
691 if (ret) {
692 DRM_DEV_ERROR(dev, "%s: phy enable failed, %d\n", __func__, ret);
693 goto phy_en_fail;
694 }
695
696 /*
697 * Resetting DSI PHY silently changes its PLL registers to reset status,
698 * which will confuse clock driver and result in wrong output rate of
699 * link clocks. Restore PLL status if its PLL is being used as clock
700 * source.
701 */
702 if (phy->usecase != MSM_DSI_PHY_SLAVE) {
703 ret = msm_dsi_pll_restore_state(phy->pll);
704 if (ret) {
705 DRM_DEV_ERROR(dev, "%s: failed to restore pll state, %d\n",
706 __func__, ret);
707 goto pll_restor_fail;
708 }
709 }
710
711 return 0;
712
713pll_restor_fail:
714 if (phy->cfg->ops.disable)
715 phy->cfg->ops.disable(phy);
716phy_en_fail:
717 dsi_phy_regulator_disable(phy);
718reg_en_fail:
719 dsi_phy_disable_resource(phy);
720res_en_fail:
721 return ret;
722}
723
724void msm_dsi_phy_disable(struct msm_dsi_phy *phy)
725{
726 if (!phy || !phy->cfg->ops.disable)
727 return;
728
729 phy->cfg->ops.disable(phy);
730
731 dsi_phy_regulator_disable(phy);
732 dsi_phy_disable_resource(phy);
733}
734
735void msm_dsi_phy_get_shared_timings(struct msm_dsi_phy *phy,
736 struct msm_dsi_phy_shared_timings *shared_timings)
737{
738 memcpy(shared_timings, &phy->timing.shared_timings,
739 sizeof(*shared_timings));
740}
741
742struct msm_dsi_pll *msm_dsi_phy_get_pll(struct msm_dsi_phy *phy)
743{
744 if (!phy)
745 return NULL;
746
747 return phy->pll;
748}
749
750void msm_dsi_phy_set_usecase(struct msm_dsi_phy *phy,
751 enum msm_dsi_phy_usecase uc)
752{
753 if (phy)
754 phy->usecase = uc;
755}
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (c) 2015, The Linux Foundation. All rights reserved.
4 */
5
6#include <linux/clk-provider.h>
7#include <linux/platform_device.h>
8#include <dt-bindings/phy/phy.h>
9
10#include "dsi_phy.h"
11
12#define S_DIV_ROUND_UP(n, d) \
13 (((n) >= 0) ? (((n) + (d) - 1) / (d)) : (((n) - (d) + 1) / (d)))
14
15static inline s32 linear_inter(s32 tmax, s32 tmin, s32 percent,
16 s32 min_result, bool even)
17{
18 s32 v;
19
20 v = (tmax - tmin) * percent;
21 v = S_DIV_ROUND_UP(v, 100) + tmin;
22 if (even && (v & 0x1))
23 return max_t(s32, min_result, v - 1);
24 else
25 return max_t(s32, min_result, v);
26}
27
28static void dsi_dphy_timing_calc_clk_zero(struct msm_dsi_dphy_timing *timing,
29 s32 ui, s32 coeff, s32 pcnt)
30{
31 s32 tmax, tmin, clk_z;
32 s32 temp;
33
34 /* reset */
35 temp = 300 * coeff - ((timing->clk_prepare >> 1) + 1) * 2 * ui;
36 tmin = S_DIV_ROUND_UP(temp, ui) - 2;
37 if (tmin > 255) {
38 tmax = 511;
39 clk_z = linear_inter(2 * tmin, tmin, pcnt, 0, true);
40 } else {
41 tmax = 255;
42 clk_z = linear_inter(tmax, tmin, pcnt, 0, true);
43 }
44
45 /* adjust */
46 temp = (timing->hs_rqst + timing->clk_prepare + clk_z) & 0x7;
47 timing->clk_zero = clk_z + 8 - temp;
48}
49
50int msm_dsi_dphy_timing_calc(struct msm_dsi_dphy_timing *timing,
51 struct msm_dsi_phy_clk_request *clk_req)
52{
53 const unsigned long bit_rate = clk_req->bitclk_rate;
54 const unsigned long esc_rate = clk_req->escclk_rate;
55 s32 ui, lpx;
56 s32 tmax, tmin;
57 s32 pcnt0 = 10;
58 s32 pcnt1 = (bit_rate > 1200000000) ? 15 : 10;
59 s32 pcnt2 = 10;
60 s32 pcnt3 = (bit_rate > 180000000) ? 10 : 40;
61 s32 coeff = 1000; /* Precision, should avoid overflow */
62 s32 temp;
63
64 if (!bit_rate || !esc_rate)
65 return -EINVAL;
66
67 ui = mult_frac(NSEC_PER_MSEC, coeff, bit_rate / 1000);
68 lpx = mult_frac(NSEC_PER_MSEC, coeff, esc_rate / 1000);
69
70 tmax = S_DIV_ROUND_UP(95 * coeff, ui) - 2;
71 tmin = S_DIV_ROUND_UP(38 * coeff, ui) - 2;
72 timing->clk_prepare = linear_inter(tmax, tmin, pcnt0, 0, true);
73
74 temp = lpx / ui;
75 if (temp & 0x1)
76 timing->hs_rqst = temp;
77 else
78 timing->hs_rqst = max_t(s32, 0, temp - 2);
79
80 /* Calculate clk_zero after clk_prepare and hs_rqst */
81 dsi_dphy_timing_calc_clk_zero(timing, ui, coeff, pcnt2);
82
83 temp = 105 * coeff + 12 * ui - 20 * coeff;
84 tmax = S_DIV_ROUND_UP(temp, ui) - 2;
85 tmin = S_DIV_ROUND_UP(60 * coeff, ui) - 2;
86 timing->clk_trail = linear_inter(tmax, tmin, pcnt3, 0, true);
87
88 temp = 85 * coeff + 6 * ui;
89 tmax = S_DIV_ROUND_UP(temp, ui) - 2;
90 temp = 40 * coeff + 4 * ui;
91 tmin = S_DIV_ROUND_UP(temp, ui) - 2;
92 timing->hs_prepare = linear_inter(tmax, tmin, pcnt1, 0, true);
93
94 tmax = 255;
95 temp = ((timing->hs_prepare >> 1) + 1) * 2 * ui + 2 * ui;
96 temp = 145 * coeff + 10 * ui - temp;
97 tmin = S_DIV_ROUND_UP(temp, ui) - 2;
98 timing->hs_zero = linear_inter(tmax, tmin, pcnt2, 24, true);
99
100 temp = 105 * coeff + 12 * ui - 20 * coeff;
101 tmax = S_DIV_ROUND_UP(temp, ui) - 2;
102 temp = 60 * coeff + 4 * ui;
103 tmin = DIV_ROUND_UP(temp, ui) - 2;
104 timing->hs_trail = linear_inter(tmax, tmin, pcnt3, 0, true);
105
106 tmax = 255;
107 tmin = S_DIV_ROUND_UP(100 * coeff, ui) - 2;
108 timing->hs_exit = linear_inter(tmax, tmin, pcnt2, 0, true);
109
110 tmax = 63;
111 temp = ((timing->hs_exit >> 1) + 1) * 2 * ui;
112 temp = 60 * coeff + 52 * ui - 24 * ui - temp;
113 tmin = S_DIV_ROUND_UP(temp, 8 * ui) - 1;
114 timing->shared_timings.clk_post = linear_inter(tmax, tmin, pcnt2, 0,
115 false);
116 tmax = 63;
117 temp = ((timing->clk_prepare >> 1) + 1) * 2 * ui;
118 temp += ((timing->clk_zero >> 1) + 1) * 2 * ui;
119 temp += 8 * ui + lpx;
120 tmin = S_DIV_ROUND_UP(temp, 8 * ui) - 1;
121 if (tmin > tmax) {
122 temp = linear_inter(2 * tmax, tmin, pcnt2, 0, false);
123 timing->shared_timings.clk_pre = temp >> 1;
124 timing->shared_timings.clk_pre_inc_by_2 = true;
125 } else {
126 timing->shared_timings.clk_pre =
127 linear_inter(tmax, tmin, pcnt2, 0, false);
128 timing->shared_timings.clk_pre_inc_by_2 = false;
129 }
130
131 timing->ta_go = 3;
132 timing->ta_sure = 0;
133 timing->ta_get = 4;
134
135 DBG("PHY timings: %d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d",
136 timing->shared_timings.clk_pre, timing->shared_timings.clk_post,
137 timing->shared_timings.clk_pre_inc_by_2, timing->clk_zero,
138 timing->clk_trail, timing->clk_prepare, timing->hs_exit,
139 timing->hs_zero, timing->hs_prepare, timing->hs_trail,
140 timing->hs_rqst);
141
142 return 0;
143}
144
145int msm_dsi_dphy_timing_calc_v2(struct msm_dsi_dphy_timing *timing,
146 struct msm_dsi_phy_clk_request *clk_req)
147{
148 const unsigned long bit_rate = clk_req->bitclk_rate;
149 const unsigned long esc_rate = clk_req->escclk_rate;
150 s32 ui, ui_x8;
151 s32 tmax, tmin;
152 s32 pcnt0 = 50;
153 s32 pcnt1 = 50;
154 s32 pcnt2 = 10;
155 s32 pcnt3 = 30;
156 s32 pcnt4 = 10;
157 s32 pcnt5 = 2;
158 s32 coeff = 1000; /* Precision, should avoid overflow */
159 s32 hb_en, hb_en_ckln, pd_ckln, pd;
160 s32 val, val_ckln;
161 s32 temp;
162
163 if (!bit_rate || !esc_rate)
164 return -EINVAL;
165
166 timing->hs_halfbyte_en = 0;
167 hb_en = 0;
168 timing->hs_halfbyte_en_ckln = 0;
169 hb_en_ckln = 0;
170 timing->hs_prep_dly_ckln = (bit_rate > 100000000) ? 0 : 3;
171 pd_ckln = timing->hs_prep_dly_ckln;
172 timing->hs_prep_dly = (bit_rate > 120000000) ? 0 : 1;
173 pd = timing->hs_prep_dly;
174
175 val = (hb_en << 2) + (pd << 1);
176 val_ckln = (hb_en_ckln << 2) + (pd_ckln << 1);
177
178 ui = mult_frac(NSEC_PER_MSEC, coeff, bit_rate / 1000);
179 ui_x8 = ui << 3;
180
181 temp = S_DIV_ROUND_UP(38 * coeff - val_ckln * ui, ui_x8);
182 tmin = max_t(s32, temp, 0);
183 temp = (95 * coeff - val_ckln * ui) / ui_x8;
184 tmax = max_t(s32, temp, 0);
185 timing->clk_prepare = linear_inter(tmax, tmin, pcnt0, 0, false);
186
187 temp = 300 * coeff - ((timing->clk_prepare << 3) + val_ckln) * ui;
188 tmin = S_DIV_ROUND_UP(temp - 11 * ui, ui_x8) - 3;
189 tmax = (tmin > 255) ? 511 : 255;
190 timing->clk_zero = linear_inter(tmax, tmin, pcnt5, 0, false);
191
192 tmin = DIV_ROUND_UP(60 * coeff + 3 * ui, ui_x8);
193 temp = 105 * coeff + 12 * ui - 20 * coeff;
194 tmax = (temp + 3 * ui) / ui_x8;
195 timing->clk_trail = linear_inter(tmax, tmin, pcnt3, 0, false);
196
197 temp = S_DIV_ROUND_UP(40 * coeff + 4 * ui - val * ui, ui_x8);
198 tmin = max_t(s32, temp, 0);
199 temp = (85 * coeff + 6 * ui - val * ui) / ui_x8;
200 tmax = max_t(s32, temp, 0);
201 timing->hs_prepare = linear_inter(tmax, tmin, pcnt1, 0, false);
202
203 temp = 145 * coeff + 10 * ui - ((timing->hs_prepare << 3) + val) * ui;
204 tmin = S_DIV_ROUND_UP(temp - 11 * ui, ui_x8) - 3;
205 tmax = 255;
206 timing->hs_zero = linear_inter(tmax, tmin, pcnt4, 0, false);
207
208 tmin = DIV_ROUND_UP(60 * coeff + 4 * ui + 3 * ui, ui_x8);
209 temp = 105 * coeff + 12 * ui - 20 * coeff;
210 tmax = (temp + 3 * ui) / ui_x8;
211 timing->hs_trail = linear_inter(tmax, tmin, pcnt3, 0, false);
212
213 temp = 50 * coeff + ((hb_en << 2) - 8) * ui;
214 timing->hs_rqst = S_DIV_ROUND_UP(temp, ui_x8);
215
216 tmin = DIV_ROUND_UP(100 * coeff, ui_x8) - 1;
217 tmax = 255;
218 timing->hs_exit = linear_inter(tmax, tmin, pcnt2, 0, false);
219
220 temp = 50 * coeff + ((hb_en_ckln << 2) - 8) * ui;
221 timing->hs_rqst_ckln = S_DIV_ROUND_UP(temp, ui_x8);
222
223 temp = 60 * coeff + 52 * ui - 43 * ui;
224 tmin = DIV_ROUND_UP(temp, ui_x8) - 1;
225 tmax = 63;
226 timing->shared_timings.clk_post =
227 linear_inter(tmax, tmin, pcnt2, 0, false);
228
229 temp = 8 * ui + ((timing->clk_prepare << 3) + val_ckln) * ui;
230 temp += (((timing->clk_zero + 3) << 3) + 11 - (pd_ckln << 1)) * ui;
231 temp += hb_en_ckln ? (((timing->hs_rqst_ckln << 3) + 4) * ui) :
232 (((timing->hs_rqst_ckln << 3) + 8) * ui);
233 tmin = S_DIV_ROUND_UP(temp, ui_x8) - 1;
234 tmax = 63;
235 if (tmin > tmax) {
236 temp = linear_inter(tmax << 1, tmin, pcnt2, 0, false);
237 timing->shared_timings.clk_pre = temp >> 1;
238 timing->shared_timings.clk_pre_inc_by_2 = 1;
239 } else {
240 timing->shared_timings.clk_pre =
241 linear_inter(tmax, tmin, pcnt2, 0, false);
242 timing->shared_timings.clk_pre_inc_by_2 = 0;
243 }
244
245 timing->ta_go = 3;
246 timing->ta_sure = 0;
247 timing->ta_get = 4;
248
249 DBG("%d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d",
250 timing->shared_timings.clk_pre, timing->shared_timings.clk_post,
251 timing->shared_timings.clk_pre_inc_by_2, timing->clk_zero,
252 timing->clk_trail, timing->clk_prepare, timing->hs_exit,
253 timing->hs_zero, timing->hs_prepare, timing->hs_trail,
254 timing->hs_rqst, timing->hs_rqst_ckln, timing->hs_halfbyte_en,
255 timing->hs_halfbyte_en_ckln, timing->hs_prep_dly,
256 timing->hs_prep_dly_ckln);
257
258 return 0;
259}
260
261int msm_dsi_dphy_timing_calc_v3(struct msm_dsi_dphy_timing *timing,
262 struct msm_dsi_phy_clk_request *clk_req)
263{
264 const unsigned long bit_rate = clk_req->bitclk_rate;
265 const unsigned long esc_rate = clk_req->escclk_rate;
266 s32 ui, ui_x8;
267 s32 tmax, tmin;
268 s32 pcnt0 = 50;
269 s32 pcnt1 = 50;
270 s32 pcnt2 = 10;
271 s32 pcnt3 = 30;
272 s32 pcnt4 = 10;
273 s32 pcnt5 = 2;
274 s32 coeff = 1000; /* Precision, should avoid overflow */
275 s32 hb_en, hb_en_ckln;
276 s32 temp;
277
278 if (!bit_rate || !esc_rate)
279 return -EINVAL;
280
281 timing->hs_halfbyte_en = 0;
282 hb_en = 0;
283 timing->hs_halfbyte_en_ckln = 0;
284 hb_en_ckln = 0;
285
286 ui = mult_frac(NSEC_PER_MSEC, coeff, bit_rate / 1000);
287 ui_x8 = ui << 3;
288
289 temp = S_DIV_ROUND_UP(38 * coeff, ui_x8);
290 tmin = max_t(s32, temp, 0);
291 temp = (95 * coeff) / ui_x8;
292 tmax = max_t(s32, temp, 0);
293 timing->clk_prepare = linear_inter(tmax, tmin, pcnt0, 0, false);
294
295 temp = 300 * coeff - (timing->clk_prepare << 3) * ui;
296 tmin = S_DIV_ROUND_UP(temp, ui_x8) - 1;
297 tmax = (tmin > 255) ? 511 : 255;
298 timing->clk_zero = linear_inter(tmax, tmin, pcnt5, 0, false);
299
300 tmin = DIV_ROUND_UP(60 * coeff + 3 * ui, ui_x8);
301 temp = 105 * coeff + 12 * ui - 20 * coeff;
302 tmax = (temp + 3 * ui) / ui_x8;
303 timing->clk_trail = linear_inter(tmax, tmin, pcnt3, 0, false);
304
305 temp = S_DIV_ROUND_UP(40 * coeff + 4 * ui, ui_x8);
306 tmin = max_t(s32, temp, 0);
307 temp = (85 * coeff + 6 * ui) / ui_x8;
308 tmax = max_t(s32, temp, 0);
309 timing->hs_prepare = linear_inter(tmax, tmin, pcnt1, 0, false);
310
311 temp = 145 * coeff + 10 * ui - (timing->hs_prepare << 3) * ui;
312 tmin = S_DIV_ROUND_UP(temp, ui_x8) - 1;
313 tmax = 255;
314 timing->hs_zero = linear_inter(tmax, tmin, pcnt4, 0, false);
315
316 tmin = DIV_ROUND_UP(60 * coeff + 4 * ui, ui_x8) - 1;
317 temp = 105 * coeff + 12 * ui - 20 * coeff;
318 tmax = (temp / ui_x8) - 1;
319 timing->hs_trail = linear_inter(tmax, tmin, pcnt3, 0, false);
320
321 temp = 50 * coeff + ((hb_en << 2) - 8) * ui;
322 timing->hs_rqst = S_DIV_ROUND_UP(temp, ui_x8);
323
324 tmin = DIV_ROUND_UP(100 * coeff, ui_x8) - 1;
325 tmax = 255;
326 timing->hs_exit = linear_inter(tmax, tmin, pcnt2, 0, false);
327
328 temp = 50 * coeff + ((hb_en_ckln << 2) - 8) * ui;
329 timing->hs_rqst_ckln = S_DIV_ROUND_UP(temp, ui_x8);
330
331 temp = 60 * coeff + 52 * ui - 43 * ui;
332 tmin = DIV_ROUND_UP(temp, ui_x8) - 1;
333 tmax = 63;
334 timing->shared_timings.clk_post =
335 linear_inter(tmax, tmin, pcnt2, 0, false);
336
337 temp = 8 * ui + (timing->clk_prepare << 3) * ui;
338 temp += (((timing->clk_zero + 3) << 3) + 11) * ui;
339 temp += hb_en_ckln ? (((timing->hs_rqst_ckln << 3) + 4) * ui) :
340 (((timing->hs_rqst_ckln << 3) + 8) * ui);
341 tmin = S_DIV_ROUND_UP(temp, ui_x8) - 1;
342 tmax = 63;
343 if (tmin > tmax) {
344 temp = linear_inter(tmax << 1, tmin, pcnt2, 0, false);
345 timing->shared_timings.clk_pre = temp >> 1;
346 timing->shared_timings.clk_pre_inc_by_2 = 1;
347 } else {
348 timing->shared_timings.clk_pre =
349 linear_inter(tmax, tmin, pcnt2, 0, false);
350 timing->shared_timings.clk_pre_inc_by_2 = 0;
351 }
352
353 timing->shared_timings.byte_intf_clk_div_2 = true;
354
355 timing->ta_go = 3;
356 timing->ta_sure = 0;
357 timing->ta_get = 4;
358
359 DBG("%d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d",
360 timing->shared_timings.clk_pre, timing->shared_timings.clk_post,
361 timing->shared_timings.clk_pre_inc_by_2, timing->clk_zero,
362 timing->clk_trail, timing->clk_prepare, timing->hs_exit,
363 timing->hs_zero, timing->hs_prepare, timing->hs_trail,
364 timing->hs_rqst, timing->hs_rqst_ckln, timing->hs_halfbyte_en,
365 timing->hs_halfbyte_en_ckln, timing->hs_prep_dly,
366 timing->hs_prep_dly_ckln);
367
368 return 0;
369}
370
371int msm_dsi_dphy_timing_calc_v4(struct msm_dsi_dphy_timing *timing,
372 struct msm_dsi_phy_clk_request *clk_req)
373{
374 const unsigned long bit_rate = clk_req->bitclk_rate;
375 const unsigned long esc_rate = clk_req->escclk_rate;
376 s32 ui, ui_x8;
377 s32 tmax, tmin;
378 s32 pcnt_clk_prep = 50;
379 s32 pcnt_clk_zero = 2;
380 s32 pcnt_clk_trail = 30;
381 s32 pcnt_hs_prep = 50;
382 s32 pcnt_hs_zero = 10;
383 s32 pcnt_hs_trail = 30;
384 s32 pcnt_hs_exit = 10;
385 s32 coeff = 1000; /* Precision, should avoid overflow */
386 s32 hb_en;
387 s32 temp;
388
389 if (!bit_rate || !esc_rate)
390 return -EINVAL;
391
392 hb_en = 0;
393
394 ui = mult_frac(NSEC_PER_MSEC, coeff, bit_rate / 1000);
395 ui_x8 = ui << 3;
396
397 /* TODO: verify these calculations against latest downstream driver
398 * everything except clk_post/clk_pre uses calculations from v3 based
399 * on the downstream driver having the same calculations for v3 and v4
400 */
401
402 temp = S_DIV_ROUND_UP(38 * coeff, ui_x8);
403 tmin = max_t(s32, temp, 0);
404 temp = (95 * coeff) / ui_x8;
405 tmax = max_t(s32, temp, 0);
406 timing->clk_prepare = linear_inter(tmax, tmin, pcnt_clk_prep, 0, false);
407
408 temp = 300 * coeff - (timing->clk_prepare << 3) * ui;
409 tmin = S_DIV_ROUND_UP(temp, ui_x8) - 1;
410 tmax = (tmin > 255) ? 511 : 255;
411 timing->clk_zero = linear_inter(tmax, tmin, pcnt_clk_zero, 0, false);
412
413 tmin = DIV_ROUND_UP(60 * coeff + 3 * ui, ui_x8);
414 temp = 105 * coeff + 12 * ui - 20 * coeff;
415 tmax = (temp + 3 * ui) / ui_x8;
416 timing->clk_trail = linear_inter(tmax, tmin, pcnt_clk_trail, 0, false);
417
418 temp = S_DIV_ROUND_UP(40 * coeff + 4 * ui, ui_x8);
419 tmin = max_t(s32, temp, 0);
420 temp = (85 * coeff + 6 * ui) / ui_x8;
421 tmax = max_t(s32, temp, 0);
422 timing->hs_prepare = linear_inter(tmax, tmin, pcnt_hs_prep, 0, false);
423
424 temp = 145 * coeff + 10 * ui - (timing->hs_prepare << 3) * ui;
425 tmin = S_DIV_ROUND_UP(temp, ui_x8) - 1;
426 tmax = 255;
427 timing->hs_zero = linear_inter(tmax, tmin, pcnt_hs_zero, 0, false);
428
429 tmin = DIV_ROUND_UP(60 * coeff + 4 * ui, ui_x8) - 1;
430 temp = 105 * coeff + 12 * ui - 20 * coeff;
431 tmax = (temp / ui_x8) - 1;
432 timing->hs_trail = linear_inter(tmax, tmin, pcnt_hs_trail, 0, false);
433
434 temp = 50 * coeff + ((hb_en << 2) - 8) * ui;
435 timing->hs_rqst = S_DIV_ROUND_UP(temp, ui_x8);
436
437 tmin = DIV_ROUND_UP(100 * coeff, ui_x8) - 1;
438 tmax = 255;
439 timing->hs_exit = linear_inter(tmax, tmin, pcnt_hs_exit, 0, false);
440
441 /* recommended min
442 * = roundup((mipi_min_ns + t_hs_trail_ns)/(16*bit_clk_ns), 0) - 1
443 */
444 temp = 60 * coeff + 52 * ui + + (timing->hs_trail + 1) * ui_x8;
445 tmin = DIV_ROUND_UP(temp, 16 * ui) - 1;
446 tmax = 255;
447 timing->shared_timings.clk_post = linear_inter(tmax, tmin, 5, 0, false);
448
449 /* recommended min
450 * val1 = (tlpx_ns + clk_prepare_ns + clk_zero_ns + hs_rqst_ns)
451 * val2 = (16 * bit_clk_ns)
452 * final = roundup(val1/val2, 0) - 1
453 */
454 temp = 52 * coeff + (timing->clk_prepare + timing->clk_zero + 1) * ui_x8 + 54 * coeff;
455 tmin = DIV_ROUND_UP(temp, 16 * ui) - 1;
456 tmax = 255;
457 timing->shared_timings.clk_pre = DIV_ROUND_UP((tmax - tmin) * 125, 10000) + tmin;
458
459 timing->shared_timings.byte_intf_clk_div_2 = true;
460
461 DBG("%d, %d, %d, %d, %d, %d, %d, %d, %d, %d",
462 timing->shared_timings.clk_pre, timing->shared_timings.clk_post,
463 timing->clk_zero, timing->clk_trail, timing->clk_prepare, timing->hs_exit,
464 timing->hs_zero, timing->hs_prepare, timing->hs_trail, timing->hs_rqst);
465
466 return 0;
467}
468
469int msm_dsi_cphy_timing_calc_v4(struct msm_dsi_dphy_timing *timing,
470 struct msm_dsi_phy_clk_request *clk_req)
471{
472 const unsigned long bit_rate = clk_req->bitclk_rate;
473 const unsigned long esc_rate = clk_req->escclk_rate;
474 s32 ui, ui_x7;
475 s32 tmax, tmin;
476 s32 coeff = 1000; /* Precision, should avoid overflow */
477 s32 temp;
478
479 if (!bit_rate || !esc_rate)
480 return -EINVAL;
481
482 ui = mult_frac(NSEC_PER_MSEC, coeff, bit_rate / 1000);
483 ui_x7 = ui * 7;
484
485 temp = S_DIV_ROUND_UP(38 * coeff, ui_x7);
486 tmin = max_t(s32, temp, 0);
487 temp = (95 * coeff) / ui_x7;
488 tmax = max_t(s32, temp, 0);
489 timing->clk_prepare = linear_inter(tmax, tmin, 50, 0, false);
490
491 tmin = DIV_ROUND_UP(50 * coeff, ui_x7);
492 tmax = 255;
493 timing->hs_rqst = linear_inter(tmax, tmin, 1, 0, false);
494
495 tmin = DIV_ROUND_UP(100 * coeff, ui_x7) - 1;
496 tmax = 255;
497 timing->hs_exit = linear_inter(tmax, tmin, 10, 0, false);
498
499 tmin = 1;
500 tmax = 32;
501 timing->shared_timings.clk_post = linear_inter(tmax, tmin, 80, 0, false);
502
503 tmin = min_t(s32, 64, S_DIV_ROUND_UP(262 * coeff, ui_x7) - 1);
504 tmax = 64;
505 timing->shared_timings.clk_pre = linear_inter(tmax, tmin, 20, 0, false);
506
507 DBG("%d, %d, %d, %d, %d",
508 timing->shared_timings.clk_pre, timing->shared_timings.clk_post,
509 timing->clk_prepare, timing->hs_exit, timing->hs_rqst);
510
511 return 0;
512}
513
514static int dsi_phy_enable_resource(struct msm_dsi_phy *phy)
515{
516 struct device *dev = &phy->pdev->dev;
517 int ret;
518
519 ret = pm_runtime_resume_and_get(dev);
520 if (ret)
521 return ret;
522
523 ret = clk_prepare_enable(phy->ahb_clk);
524 if (ret) {
525 DRM_DEV_ERROR(dev, "%s: can't enable ahb clk, %d\n", __func__, ret);
526 pm_runtime_put_sync(dev);
527 }
528
529 return ret;
530}
531
532static void dsi_phy_disable_resource(struct msm_dsi_phy *phy)
533{
534 clk_disable_unprepare(phy->ahb_clk);
535 pm_runtime_put(&phy->pdev->dev);
536}
537
538static const struct of_device_id dsi_phy_dt_match[] = {
539#ifdef CONFIG_DRM_MSM_DSI_28NM_PHY
540 { .compatible = "qcom,dsi-phy-28nm-hpm",
541 .data = &dsi_phy_28nm_hpm_cfgs },
542 { .compatible = "qcom,dsi-phy-28nm-hpm-fam-b",
543 .data = &dsi_phy_28nm_hpm_famb_cfgs },
544 { .compatible = "qcom,dsi-phy-28nm-lp",
545 .data = &dsi_phy_28nm_lp_cfgs },
546 { .compatible = "qcom,dsi-phy-28nm-8226",
547 .data = &dsi_phy_28nm_8226_cfgs },
548#endif
549#ifdef CONFIG_DRM_MSM_DSI_20NM_PHY
550 { .compatible = "qcom,dsi-phy-20nm",
551 .data = &dsi_phy_20nm_cfgs },
552#endif
553#ifdef CONFIG_DRM_MSM_DSI_28NM_8960_PHY
554 { .compatible = "qcom,dsi-phy-28nm-8960",
555 .data = &dsi_phy_28nm_8960_cfgs },
556#endif
557#ifdef CONFIG_DRM_MSM_DSI_14NM_PHY
558 { .compatible = "qcom,dsi-phy-14nm",
559 .data = &dsi_phy_14nm_cfgs },
560 { .compatible = "qcom,dsi-phy-14nm-2290",
561 .data = &dsi_phy_14nm_2290_cfgs },
562 { .compatible = "qcom,dsi-phy-14nm-660",
563 .data = &dsi_phy_14nm_660_cfgs },
564 { .compatible = "qcom,dsi-phy-14nm-8953",
565 .data = &dsi_phy_14nm_8953_cfgs },
566 { .compatible = "qcom,sm6125-dsi-phy-14nm",
567 .data = &dsi_phy_14nm_2290_cfgs },
568#endif
569#ifdef CONFIG_DRM_MSM_DSI_10NM_PHY
570 { .compatible = "qcom,dsi-phy-10nm",
571 .data = &dsi_phy_10nm_cfgs },
572 { .compatible = "qcom,dsi-phy-10nm-8998",
573 .data = &dsi_phy_10nm_8998_cfgs },
574#endif
575#ifdef CONFIG_DRM_MSM_DSI_7NM_PHY
576 { .compatible = "qcom,dsi-phy-7nm",
577 .data = &dsi_phy_7nm_cfgs },
578 { .compatible = "qcom,dsi-phy-7nm-8150",
579 .data = &dsi_phy_7nm_8150_cfgs },
580 { .compatible = "qcom,sc7280-dsi-phy-7nm",
581 .data = &dsi_phy_7nm_7280_cfgs },
582 { .compatible = "qcom,sm6375-dsi-phy-7nm",
583 .data = &dsi_phy_7nm_6375_cfgs },
584 { .compatible = "qcom,sm8350-dsi-phy-5nm",
585 .data = &dsi_phy_5nm_8350_cfgs },
586 { .compatible = "qcom,sm8450-dsi-phy-5nm",
587 .data = &dsi_phy_5nm_8450_cfgs },
588 { .compatible = "qcom,sm8550-dsi-phy-4nm",
589 .data = &dsi_phy_4nm_8550_cfgs },
590 { .compatible = "qcom,sm8650-dsi-phy-4nm",
591 .data = &dsi_phy_4nm_8650_cfgs },
592#endif
593 {}
594};
595
596/*
597 * Currently, we only support one SoC for each PHY type. When we have multiple
598 * SoCs for the same PHY, we can try to make the index searching a bit more
599 * clever.
600 */
601static int dsi_phy_get_id(struct msm_dsi_phy *phy)
602{
603 struct platform_device *pdev = phy->pdev;
604 const struct msm_dsi_phy_cfg *cfg = phy->cfg;
605 struct resource *res;
606 int i;
607
608 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dsi_phy");
609 if (!res)
610 return -EINVAL;
611
612 for (i = 0; i < cfg->num_dsi_phy; i++) {
613 if (cfg->io_start[i] == res->start)
614 return i;
615 }
616
617 return -EINVAL;
618}
619
620static int dsi_phy_driver_probe(struct platform_device *pdev)
621{
622 struct msm_dsi_phy *phy;
623 struct device *dev = &pdev->dev;
624 u32 phy_type;
625 int ret;
626
627 phy = devm_kzalloc(dev, sizeof(*phy), GFP_KERNEL);
628 if (!phy)
629 return -ENOMEM;
630
631 phy->provided_clocks = devm_kzalloc(dev,
632 struct_size(phy->provided_clocks, hws, NUM_PROVIDED_CLKS),
633 GFP_KERNEL);
634 if (!phy->provided_clocks)
635 return -ENOMEM;
636
637 phy->provided_clocks->num = NUM_PROVIDED_CLKS;
638
639 phy->cfg = of_device_get_match_data(&pdev->dev);
640 if (!phy->cfg)
641 return -ENODEV;
642
643 phy->pdev = pdev;
644
645 phy->id = dsi_phy_get_id(phy);
646 if (phy->id < 0)
647 return dev_err_probe(dev, phy->id,
648 "Couldn't identify PHY index\n");
649
650 phy->regulator_ldo_mode = of_property_read_bool(dev->of_node,
651 "qcom,dsi-phy-regulator-ldo-mode");
652 if (!of_property_read_u32(dev->of_node, "phy-type", &phy_type))
653 phy->cphy_mode = (phy_type == PHY_TYPE_CPHY);
654
655 phy->base = msm_ioremap_size(pdev, "dsi_phy", &phy->base_size);
656 if (IS_ERR(phy->base))
657 return dev_err_probe(dev, PTR_ERR(phy->base),
658 "Failed to map phy base\n");
659
660 phy->pll_base = msm_ioremap_size(pdev, "dsi_pll", &phy->pll_size);
661 if (IS_ERR(phy->pll_base))
662 return dev_err_probe(dev, PTR_ERR(phy->pll_base),
663 "Failed to map pll base\n");
664
665 if (phy->cfg->has_phy_lane) {
666 phy->lane_base = msm_ioremap_size(pdev, "dsi_phy_lane", &phy->lane_size);
667 if (IS_ERR(phy->lane_base))
668 return dev_err_probe(dev, PTR_ERR(phy->lane_base),
669 "Failed to map phy lane base\n");
670 }
671
672 if (phy->cfg->has_phy_regulator) {
673 phy->reg_base = msm_ioremap_size(pdev, "dsi_phy_regulator", &phy->reg_size);
674 if (IS_ERR(phy->reg_base))
675 return dev_err_probe(dev, PTR_ERR(phy->reg_base),
676 "Failed to map phy regulator base\n");
677 }
678
679 if (phy->cfg->ops.parse_dt_properties) {
680 ret = phy->cfg->ops.parse_dt_properties(phy);
681 if (ret)
682 return ret;
683 }
684
685 ret = devm_regulator_bulk_get_const(dev, phy->cfg->num_regulators,
686 phy->cfg->regulator_data,
687 &phy->supplies);
688 if (ret)
689 return ret;
690
691 phy->ahb_clk = msm_clk_get(pdev, "iface");
692 if (IS_ERR(phy->ahb_clk))
693 return dev_err_probe(dev, PTR_ERR(phy->ahb_clk),
694 "Unable to get ahb clk\n");
695
696 ret = devm_pm_runtime_enable(&pdev->dev);
697 if (ret)
698 return ret;
699
700 /* PLL init will call into clk_register which requires
701 * register access, so we need to enable power and ahb clock.
702 */
703 ret = dsi_phy_enable_resource(phy);
704 if (ret)
705 return ret;
706
707 if (phy->cfg->ops.pll_init) {
708 ret = phy->cfg->ops.pll_init(phy);
709 if (ret)
710 return dev_err_probe(dev, ret,
711 "PLL init failed; need separate clk driver\n");
712 }
713
714 ret = devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get,
715 phy->provided_clocks);
716 if (ret)
717 return dev_err_probe(dev, ret,
718 "Failed to register clk provider\n");
719
720 dsi_phy_disable_resource(phy);
721
722 platform_set_drvdata(pdev, phy);
723
724 return 0;
725}
726
727static struct platform_driver dsi_phy_platform_driver = {
728 .probe = dsi_phy_driver_probe,
729 .driver = {
730 .name = "msm_dsi_phy",
731 .of_match_table = dsi_phy_dt_match,
732 },
733};
734
735void __init msm_dsi_phy_driver_register(void)
736{
737 platform_driver_register(&dsi_phy_platform_driver);
738}
739
740void __exit msm_dsi_phy_driver_unregister(void)
741{
742 platform_driver_unregister(&dsi_phy_platform_driver);
743}
744
745int msm_dsi_phy_enable(struct msm_dsi_phy *phy,
746 struct msm_dsi_phy_clk_request *clk_req,
747 struct msm_dsi_phy_shared_timings *shared_timings)
748{
749 struct device *dev;
750 int ret;
751
752 if (!phy || !phy->cfg->ops.enable)
753 return -EINVAL;
754
755 dev = &phy->pdev->dev;
756
757 ret = dsi_phy_enable_resource(phy);
758 if (ret) {
759 DRM_DEV_ERROR(dev, "%s: resource enable failed, %d\n",
760 __func__, ret);
761 goto res_en_fail;
762 }
763
764 ret = regulator_bulk_enable(phy->cfg->num_regulators, phy->supplies);
765 if (ret) {
766 DRM_DEV_ERROR(dev, "%s: regulator enable failed, %d\n",
767 __func__, ret);
768 goto reg_en_fail;
769 }
770
771 ret = phy->cfg->ops.enable(phy, clk_req);
772 if (ret) {
773 DRM_DEV_ERROR(dev, "%s: phy enable failed, %d\n", __func__, ret);
774 goto phy_en_fail;
775 }
776
777 memcpy(shared_timings, &phy->timing.shared_timings,
778 sizeof(*shared_timings));
779
780 /*
781 * Resetting DSI PHY silently changes its PLL registers to reset status,
782 * which will confuse clock driver and result in wrong output rate of
783 * link clocks. Restore PLL status if its PLL is being used as clock
784 * source.
785 */
786 if (phy->usecase != MSM_DSI_PHY_SLAVE) {
787 ret = msm_dsi_phy_pll_restore_state(phy);
788 if (ret) {
789 DRM_DEV_ERROR(dev, "%s: failed to restore phy state, %d\n",
790 __func__, ret);
791 goto pll_restor_fail;
792 }
793 }
794
795 return 0;
796
797pll_restor_fail:
798 if (phy->cfg->ops.disable)
799 phy->cfg->ops.disable(phy);
800phy_en_fail:
801 regulator_bulk_disable(phy->cfg->num_regulators, phy->supplies);
802reg_en_fail:
803 dsi_phy_disable_resource(phy);
804res_en_fail:
805 return ret;
806}
807
808void msm_dsi_phy_disable(struct msm_dsi_phy *phy)
809{
810 if (!phy || !phy->cfg->ops.disable)
811 return;
812
813 phy->cfg->ops.disable(phy);
814
815 regulator_bulk_disable(phy->cfg->num_regulators, phy->supplies);
816 dsi_phy_disable_resource(phy);
817}
818
819void msm_dsi_phy_set_usecase(struct msm_dsi_phy *phy,
820 enum msm_dsi_phy_usecase uc)
821{
822 if (phy)
823 phy->usecase = uc;
824}
825
826/* Returns true if we have to clear DSI_LANE_CTRL.HS_REQ_SEL_PHY */
827bool msm_dsi_phy_set_continuous_clock(struct msm_dsi_phy *phy, bool enable)
828{
829 if (!phy || !phy->cfg->ops.set_continuous_clock)
830 return false;
831
832 return phy->cfg->ops.set_continuous_clock(phy, enable);
833}
834
835void msm_dsi_phy_pll_save_state(struct msm_dsi_phy *phy)
836{
837 if (phy->cfg->ops.save_pll_state) {
838 phy->cfg->ops.save_pll_state(phy);
839 phy->state_saved = true;
840 }
841}
842
843int msm_dsi_phy_pll_restore_state(struct msm_dsi_phy *phy)
844{
845 int ret;
846
847 if (phy->cfg->ops.restore_pll_state && phy->state_saved) {
848 ret = phy->cfg->ops.restore_pll_state(phy);
849 if (ret)
850 return ret;
851
852 phy->state_saved = false;
853 }
854
855 return 0;
856}
857
858void msm_dsi_phy_snapshot(struct msm_disp_state *disp_state, struct msm_dsi_phy *phy)
859{
860 msm_disp_snapshot_add_block(disp_state,
861 phy->base_size, phy->base,
862 "dsi%d_phy", phy->id);
863
864 /* Do not try accessing PLL registers if it is switched off */
865 if (phy->pll_on)
866 msm_disp_snapshot_add_block(disp_state,
867 phy->pll_size, phy->pll_base,
868 "dsi%d_pll", phy->id);
869
870 if (phy->lane_base)
871 msm_disp_snapshot_add_block(disp_state,
872 phy->lane_size, phy->lane_base,
873 "dsi%d_lane", phy->id);
874
875 if (phy->reg_base)
876 msm_disp_snapshot_add_block(disp_state,
877 phy->reg_size, phy->reg_base,
878 "dsi%d_reg", phy->id);
879}