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1/*
2 * Copyright (c) 2006 Luc Verhaegen (quirks list)
3 * Copyright (c) 2007-2008 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
5 * Copyright 2010 Red Hat, Inc.
6 *
7 * DDC probing routines (drm_ddc_read & drm_do_probe_ddc_edid) originally from
8 * FB layer.
9 * Copyright (C) 2006 Dennis Munsie <dmunsie@cecropia.com>
10 *
11 * Permission is hereby granted, free of charge, to any person obtaining a
12 * copy of this software and associated documentation files (the "Software"),
13 * to deal in the Software without restriction, including without limitation
14 * the rights to use, copy, modify, merge, publish, distribute, sub license,
15 * and/or sell copies of the Software, and to permit persons to whom the
16 * Software is furnished to do so, subject to the following conditions:
17 *
18 * The above copyright notice and this permission notice (including the
19 * next paragraph) shall be included in all copies or substantial portions
20 * of the Software.
21 *
22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
23 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
24 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
25 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
26 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
27 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
28 * DEALINGS IN THE SOFTWARE.
29 */
30
31#include <linux/hdmi.h>
32#include <linux/i2c.h>
33#include <linux/kernel.h>
34#include <linux/module.h>
35#include <linux/slab.h>
36#include <linux/vga_switcheroo.h>
37
38#include <drm/drm_displayid.h>
39#include <drm/drm_drv.h>
40#include <drm/drm_edid.h>
41#include <drm/drm_encoder.h>
42#include <drm/drm_print.h>
43#include <drm/drm_scdc_helper.h>
44
45#include "drm_crtc_internal.h"
46
47#define version_greater(edid, maj, min) \
48 (((edid)->version > (maj)) || \
49 ((edid)->version == (maj) && (edid)->revision > (min)))
50
51#define EDID_EST_TIMINGS 16
52#define EDID_STD_TIMINGS 8
53#define EDID_DETAILED_TIMINGS 4
54
55/*
56 * EDID blocks out in the wild have a variety of bugs, try to collect
57 * them here (note that userspace may work around broken monitors first,
58 * but fixes should make their way here so that the kernel "just works"
59 * on as many displays as possible).
60 */
61
62/* First detailed mode wrong, use largest 60Hz mode */
63#define EDID_QUIRK_PREFER_LARGE_60 (1 << 0)
64/* Reported 135MHz pixel clock is too high, needs adjustment */
65#define EDID_QUIRK_135_CLOCK_TOO_HIGH (1 << 1)
66/* Prefer the largest mode at 75 Hz */
67#define EDID_QUIRK_PREFER_LARGE_75 (1 << 2)
68/* Detail timing is in cm not mm */
69#define EDID_QUIRK_DETAILED_IN_CM (1 << 3)
70/* Detailed timing descriptors have bogus size values, so just take the
71 * maximum size and use that.
72 */
73#define EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE (1 << 4)
74/* use +hsync +vsync for detailed mode */
75#define EDID_QUIRK_DETAILED_SYNC_PP (1 << 6)
76/* Force reduced-blanking timings for detailed modes */
77#define EDID_QUIRK_FORCE_REDUCED_BLANKING (1 << 7)
78/* Force 8bpc */
79#define EDID_QUIRK_FORCE_8BPC (1 << 8)
80/* Force 12bpc */
81#define EDID_QUIRK_FORCE_12BPC (1 << 9)
82/* Force 6bpc */
83#define EDID_QUIRK_FORCE_6BPC (1 << 10)
84/* Force 10bpc */
85#define EDID_QUIRK_FORCE_10BPC (1 << 11)
86/* Non desktop display (i.e. HMD) */
87#define EDID_QUIRK_NON_DESKTOP (1 << 12)
88
89struct detailed_mode_closure {
90 struct drm_connector *connector;
91 struct edid *edid;
92 bool preferred;
93 u32 quirks;
94 int modes;
95};
96
97#define LEVEL_DMT 0
98#define LEVEL_GTF 1
99#define LEVEL_GTF2 2
100#define LEVEL_CVT 3
101
102static const struct edid_quirk {
103 char vendor[4];
104 int product_id;
105 u32 quirks;
106} edid_quirk_list[] = {
107 /* Acer AL1706 */
108 { "ACR", 44358, EDID_QUIRK_PREFER_LARGE_60 },
109 /* Acer F51 */
110 { "API", 0x7602, EDID_QUIRK_PREFER_LARGE_60 },
111
112 /* AEO model 0 reports 8 bpc, but is a 6 bpc panel */
113 { "AEO", 0, EDID_QUIRK_FORCE_6BPC },
114
115 /* BOE model on HP Pavilion 15-n233sl reports 8 bpc, but is a 6 bpc panel */
116 { "BOE", 0x78b, EDID_QUIRK_FORCE_6BPC },
117
118 /* CPT panel of Asus UX303LA reports 8 bpc, but is a 6 bpc panel */
119 { "CPT", 0x17df, EDID_QUIRK_FORCE_6BPC },
120
121 /* SDC panel of Lenovo B50-80 reports 8 bpc, but is a 6 bpc panel */
122 { "SDC", 0x3652, EDID_QUIRK_FORCE_6BPC },
123
124 /* BOE model 0x0771 reports 8 bpc, but is a 6 bpc panel */
125 { "BOE", 0x0771, EDID_QUIRK_FORCE_6BPC },
126
127 /* Belinea 10 15 55 */
128 { "MAX", 1516, EDID_QUIRK_PREFER_LARGE_60 },
129 { "MAX", 0x77e, EDID_QUIRK_PREFER_LARGE_60 },
130
131 /* Envision Peripherals, Inc. EN-7100e */
132 { "EPI", 59264, EDID_QUIRK_135_CLOCK_TOO_HIGH },
133 /* Envision EN2028 */
134 { "EPI", 8232, EDID_QUIRK_PREFER_LARGE_60 },
135
136 /* Funai Electronics PM36B */
137 { "FCM", 13600, EDID_QUIRK_PREFER_LARGE_75 |
138 EDID_QUIRK_DETAILED_IN_CM },
139
140 /* LGD panel of HP zBook 17 G2, eDP 10 bpc, but reports unknown bpc */
141 { "LGD", 764, EDID_QUIRK_FORCE_10BPC },
142
143 /* LG Philips LCD LP154W01-A5 */
144 { "LPL", 0, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE },
145 { "LPL", 0x2a00, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE },
146
147 /* Samsung SyncMaster 205BW. Note: irony */
148 { "SAM", 541, EDID_QUIRK_DETAILED_SYNC_PP },
149 /* Samsung SyncMaster 22[5-6]BW */
150 { "SAM", 596, EDID_QUIRK_PREFER_LARGE_60 },
151 { "SAM", 638, EDID_QUIRK_PREFER_LARGE_60 },
152
153 /* Sony PVM-2541A does up to 12 bpc, but only reports max 8 bpc */
154 { "SNY", 0x2541, EDID_QUIRK_FORCE_12BPC },
155
156 /* ViewSonic VA2026w */
157 { "VSC", 5020, EDID_QUIRK_FORCE_REDUCED_BLANKING },
158
159 /* Medion MD 30217 PG */
160 { "MED", 0x7b8, EDID_QUIRK_PREFER_LARGE_75 },
161
162 /* Lenovo G50 */
163 { "SDC", 18514, EDID_QUIRK_FORCE_6BPC },
164
165 /* Panel in Samsung NP700G7A-S01PL notebook reports 6bpc */
166 { "SEC", 0xd033, EDID_QUIRK_FORCE_8BPC },
167
168 /* Rotel RSX-1058 forwards sink's EDID but only does HDMI 1.1*/
169 { "ETR", 13896, EDID_QUIRK_FORCE_8BPC },
170
171 /* Valve Index Headset */
172 { "VLV", 0x91a8, EDID_QUIRK_NON_DESKTOP },
173 { "VLV", 0x91b0, EDID_QUIRK_NON_DESKTOP },
174 { "VLV", 0x91b1, EDID_QUIRK_NON_DESKTOP },
175 { "VLV", 0x91b2, EDID_QUIRK_NON_DESKTOP },
176 { "VLV", 0x91b3, EDID_QUIRK_NON_DESKTOP },
177 { "VLV", 0x91b4, EDID_QUIRK_NON_DESKTOP },
178 { "VLV", 0x91b5, EDID_QUIRK_NON_DESKTOP },
179 { "VLV", 0x91b6, EDID_QUIRK_NON_DESKTOP },
180 { "VLV", 0x91b7, EDID_QUIRK_NON_DESKTOP },
181 { "VLV", 0x91b8, EDID_QUIRK_NON_DESKTOP },
182 { "VLV", 0x91b9, EDID_QUIRK_NON_DESKTOP },
183 { "VLV", 0x91ba, EDID_QUIRK_NON_DESKTOP },
184 { "VLV", 0x91bb, EDID_QUIRK_NON_DESKTOP },
185 { "VLV", 0x91bc, EDID_QUIRK_NON_DESKTOP },
186 { "VLV", 0x91bd, EDID_QUIRK_NON_DESKTOP },
187 { "VLV", 0x91be, EDID_QUIRK_NON_DESKTOP },
188 { "VLV", 0x91bf, EDID_QUIRK_NON_DESKTOP },
189
190 /* HTC Vive and Vive Pro VR Headsets */
191 { "HVR", 0xaa01, EDID_QUIRK_NON_DESKTOP },
192 { "HVR", 0xaa02, EDID_QUIRK_NON_DESKTOP },
193
194 /* Oculus Rift DK1, DK2, CV1 and Rift S VR Headsets */
195 { "OVR", 0x0001, EDID_QUIRK_NON_DESKTOP },
196 { "OVR", 0x0003, EDID_QUIRK_NON_DESKTOP },
197 { "OVR", 0x0004, EDID_QUIRK_NON_DESKTOP },
198 { "OVR", 0x0012, EDID_QUIRK_NON_DESKTOP },
199
200 /* Windows Mixed Reality Headsets */
201 { "ACR", 0x7fce, EDID_QUIRK_NON_DESKTOP },
202 { "HPN", 0x3515, EDID_QUIRK_NON_DESKTOP },
203 { "LEN", 0x0408, EDID_QUIRK_NON_DESKTOP },
204 { "LEN", 0xb800, EDID_QUIRK_NON_DESKTOP },
205 { "FUJ", 0x1970, EDID_QUIRK_NON_DESKTOP },
206 { "DEL", 0x7fce, EDID_QUIRK_NON_DESKTOP },
207 { "SEC", 0x144a, EDID_QUIRK_NON_DESKTOP },
208 { "AUS", 0xc102, EDID_QUIRK_NON_DESKTOP },
209
210 /* Sony PlayStation VR Headset */
211 { "SNY", 0x0704, EDID_QUIRK_NON_DESKTOP },
212
213 /* Sensics VR Headsets */
214 { "SEN", 0x1019, EDID_QUIRK_NON_DESKTOP },
215
216 /* OSVR HDK and HDK2 VR Headsets */
217 { "SVR", 0x1019, EDID_QUIRK_NON_DESKTOP },
218};
219
220/*
221 * Autogenerated from the DMT spec.
222 * This table is copied from xfree86/modes/xf86EdidModes.c.
223 */
224static const struct drm_display_mode drm_dmt_modes[] = {
225 /* 0x01 - 640x350@85Hz */
226 { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 31500, 640, 672,
227 736, 832, 0, 350, 382, 385, 445, 0,
228 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
229 /* 0x02 - 640x400@85Hz */
230 { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 31500, 640, 672,
231 736, 832, 0, 400, 401, 404, 445, 0,
232 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
233 /* 0x03 - 720x400@85Hz */
234 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 756,
235 828, 936, 0, 400, 401, 404, 446, 0,
236 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
237 /* 0x04 - 640x480@60Hz */
238 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
239 752, 800, 0, 480, 490, 492, 525, 0,
240 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
241 /* 0x05 - 640x480@72Hz */
242 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664,
243 704, 832, 0, 480, 489, 492, 520, 0,
244 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
245 /* 0x06 - 640x480@75Hz */
246 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656,
247 720, 840, 0, 480, 481, 484, 500, 0,
248 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
249 /* 0x07 - 640x480@85Hz */
250 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 36000, 640, 696,
251 752, 832, 0, 480, 481, 484, 509, 0,
252 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
253 /* 0x08 - 800x600@56Hz */
254 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824,
255 896, 1024, 0, 600, 601, 603, 625, 0,
256 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
257 /* 0x09 - 800x600@60Hz */
258 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840,
259 968, 1056, 0, 600, 601, 605, 628, 0,
260 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
261 /* 0x0a - 800x600@72Hz */
262 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856,
263 976, 1040, 0, 600, 637, 643, 666, 0,
264 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
265 /* 0x0b - 800x600@75Hz */
266 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816,
267 896, 1056, 0, 600, 601, 604, 625, 0,
268 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
269 /* 0x0c - 800x600@85Hz */
270 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 56250, 800, 832,
271 896, 1048, 0, 600, 601, 604, 631, 0,
272 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
273 /* 0x0d - 800x600@120Hz RB */
274 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 73250, 800, 848,
275 880, 960, 0, 600, 603, 607, 636, 0,
276 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
277 /* 0x0e - 848x480@60Hz */
278 { DRM_MODE("848x480", DRM_MODE_TYPE_DRIVER, 33750, 848, 864,
279 976, 1088, 0, 480, 486, 494, 517, 0,
280 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
281 /* 0x0f - 1024x768@43Hz, interlace */
282 { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER, 44900, 1024, 1032,
283 1208, 1264, 0, 768, 768, 776, 817, 0,
284 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
285 DRM_MODE_FLAG_INTERLACE) },
286 /* 0x10 - 1024x768@60Hz */
287 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048,
288 1184, 1344, 0, 768, 771, 777, 806, 0,
289 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
290 /* 0x11 - 1024x768@70Hz */
291 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048,
292 1184, 1328, 0, 768, 771, 777, 806, 0,
293 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
294 /* 0x12 - 1024x768@75Hz */
295 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040,
296 1136, 1312, 0, 768, 769, 772, 800, 0,
297 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
298 /* 0x13 - 1024x768@85Hz */
299 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 94500, 1024, 1072,
300 1168, 1376, 0, 768, 769, 772, 808, 0,
301 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
302 /* 0x14 - 1024x768@120Hz RB */
303 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 115500, 1024, 1072,
304 1104, 1184, 0, 768, 771, 775, 813, 0,
305 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
306 /* 0x15 - 1152x864@75Hz */
307 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216,
308 1344, 1600, 0, 864, 865, 868, 900, 0,
309 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
310 /* 0x55 - 1280x720@60Hz */
311 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390,
312 1430, 1650, 0, 720, 725, 730, 750, 0,
313 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
314 /* 0x16 - 1280x768@60Hz RB */
315 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 68250, 1280, 1328,
316 1360, 1440, 0, 768, 771, 778, 790, 0,
317 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
318 /* 0x17 - 1280x768@60Hz */
319 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 79500, 1280, 1344,
320 1472, 1664, 0, 768, 771, 778, 798, 0,
321 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
322 /* 0x18 - 1280x768@75Hz */
323 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 102250, 1280, 1360,
324 1488, 1696, 0, 768, 771, 778, 805, 0,
325 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
326 /* 0x19 - 1280x768@85Hz */
327 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 117500, 1280, 1360,
328 1496, 1712, 0, 768, 771, 778, 809, 0,
329 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
330 /* 0x1a - 1280x768@120Hz RB */
331 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 140250, 1280, 1328,
332 1360, 1440, 0, 768, 771, 778, 813, 0,
333 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
334 /* 0x1b - 1280x800@60Hz RB */
335 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 71000, 1280, 1328,
336 1360, 1440, 0, 800, 803, 809, 823, 0,
337 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
338 /* 0x1c - 1280x800@60Hz */
339 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 83500, 1280, 1352,
340 1480, 1680, 0, 800, 803, 809, 831, 0,
341 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
342 /* 0x1d - 1280x800@75Hz */
343 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 106500, 1280, 1360,
344 1488, 1696, 0, 800, 803, 809, 838, 0,
345 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
346 /* 0x1e - 1280x800@85Hz */
347 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 122500, 1280, 1360,
348 1496, 1712, 0, 800, 803, 809, 843, 0,
349 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
350 /* 0x1f - 1280x800@120Hz RB */
351 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 146250, 1280, 1328,
352 1360, 1440, 0, 800, 803, 809, 847, 0,
353 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
354 /* 0x20 - 1280x960@60Hz */
355 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1376,
356 1488, 1800, 0, 960, 961, 964, 1000, 0,
357 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
358 /* 0x21 - 1280x960@85Hz */
359 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1344,
360 1504, 1728, 0, 960, 961, 964, 1011, 0,
361 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
362 /* 0x22 - 1280x960@120Hz RB */
363 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 175500, 1280, 1328,
364 1360, 1440, 0, 960, 963, 967, 1017, 0,
365 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
366 /* 0x23 - 1280x1024@60Hz */
367 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1328,
368 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
369 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
370 /* 0x24 - 1280x1024@75Hz */
371 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296,
372 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
373 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
374 /* 0x25 - 1280x1024@85Hz */
375 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 157500, 1280, 1344,
376 1504, 1728, 0, 1024, 1025, 1028, 1072, 0,
377 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
378 /* 0x26 - 1280x1024@120Hz RB */
379 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 187250, 1280, 1328,
380 1360, 1440, 0, 1024, 1027, 1034, 1084, 0,
381 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
382 /* 0x27 - 1360x768@60Hz */
383 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 85500, 1360, 1424,
384 1536, 1792, 0, 768, 771, 777, 795, 0,
385 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
386 /* 0x28 - 1360x768@120Hz RB */
387 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 148250, 1360, 1408,
388 1440, 1520, 0, 768, 771, 776, 813, 0,
389 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
390 /* 0x51 - 1366x768@60Hz */
391 { DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 85500, 1366, 1436,
392 1579, 1792, 0, 768, 771, 774, 798, 0,
393 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
394 /* 0x56 - 1366x768@60Hz */
395 { DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 72000, 1366, 1380,
396 1436, 1500, 0, 768, 769, 772, 800, 0,
397 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
398 /* 0x29 - 1400x1050@60Hz RB */
399 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 101000, 1400, 1448,
400 1480, 1560, 0, 1050, 1053, 1057, 1080, 0,
401 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
402 /* 0x2a - 1400x1050@60Hz */
403 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 121750, 1400, 1488,
404 1632, 1864, 0, 1050, 1053, 1057, 1089, 0,
405 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
406 /* 0x2b - 1400x1050@75Hz */
407 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 156000, 1400, 1504,
408 1648, 1896, 0, 1050, 1053, 1057, 1099, 0,
409 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
410 /* 0x2c - 1400x1050@85Hz */
411 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 179500, 1400, 1504,
412 1656, 1912, 0, 1050, 1053, 1057, 1105, 0,
413 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
414 /* 0x2d - 1400x1050@120Hz RB */
415 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 208000, 1400, 1448,
416 1480, 1560, 0, 1050, 1053, 1057, 1112, 0,
417 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
418 /* 0x2e - 1440x900@60Hz RB */
419 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 88750, 1440, 1488,
420 1520, 1600, 0, 900, 903, 909, 926, 0,
421 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
422 /* 0x2f - 1440x900@60Hz */
423 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 106500, 1440, 1520,
424 1672, 1904, 0, 900, 903, 909, 934, 0,
425 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
426 /* 0x30 - 1440x900@75Hz */
427 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 136750, 1440, 1536,
428 1688, 1936, 0, 900, 903, 909, 942, 0,
429 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
430 /* 0x31 - 1440x900@85Hz */
431 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 157000, 1440, 1544,
432 1696, 1952, 0, 900, 903, 909, 948, 0,
433 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
434 /* 0x32 - 1440x900@120Hz RB */
435 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 182750, 1440, 1488,
436 1520, 1600, 0, 900, 903, 909, 953, 0,
437 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
438 /* 0x53 - 1600x900@60Hz */
439 { DRM_MODE("1600x900", DRM_MODE_TYPE_DRIVER, 108000, 1600, 1624,
440 1704, 1800, 0, 900, 901, 904, 1000, 0,
441 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
442 /* 0x33 - 1600x1200@60Hz */
443 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 162000, 1600, 1664,
444 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
445 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
446 /* 0x34 - 1600x1200@65Hz */
447 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 175500, 1600, 1664,
448 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
449 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
450 /* 0x35 - 1600x1200@70Hz */
451 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 189000, 1600, 1664,
452 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
453 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
454 /* 0x36 - 1600x1200@75Hz */
455 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 202500, 1600, 1664,
456 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
457 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
458 /* 0x37 - 1600x1200@85Hz */
459 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 229500, 1600, 1664,
460 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
461 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
462 /* 0x38 - 1600x1200@120Hz RB */
463 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 268250, 1600, 1648,
464 1680, 1760, 0, 1200, 1203, 1207, 1271, 0,
465 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
466 /* 0x39 - 1680x1050@60Hz RB */
467 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 119000, 1680, 1728,
468 1760, 1840, 0, 1050, 1053, 1059, 1080, 0,
469 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
470 /* 0x3a - 1680x1050@60Hz */
471 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 146250, 1680, 1784,
472 1960, 2240, 0, 1050, 1053, 1059, 1089, 0,
473 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
474 /* 0x3b - 1680x1050@75Hz */
475 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 187000, 1680, 1800,
476 1976, 2272, 0, 1050, 1053, 1059, 1099, 0,
477 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
478 /* 0x3c - 1680x1050@85Hz */
479 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 214750, 1680, 1808,
480 1984, 2288, 0, 1050, 1053, 1059, 1105, 0,
481 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
482 /* 0x3d - 1680x1050@120Hz RB */
483 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 245500, 1680, 1728,
484 1760, 1840, 0, 1050, 1053, 1059, 1112, 0,
485 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
486 /* 0x3e - 1792x1344@60Hz */
487 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 204750, 1792, 1920,
488 2120, 2448, 0, 1344, 1345, 1348, 1394, 0,
489 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
490 /* 0x3f - 1792x1344@75Hz */
491 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 261000, 1792, 1888,
492 2104, 2456, 0, 1344, 1345, 1348, 1417, 0,
493 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
494 /* 0x40 - 1792x1344@120Hz RB */
495 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 333250, 1792, 1840,
496 1872, 1952, 0, 1344, 1347, 1351, 1423, 0,
497 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
498 /* 0x41 - 1856x1392@60Hz */
499 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 218250, 1856, 1952,
500 2176, 2528, 0, 1392, 1393, 1396, 1439, 0,
501 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
502 /* 0x42 - 1856x1392@75Hz */
503 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 288000, 1856, 1984,
504 2208, 2560, 0, 1392, 1393, 1396, 1500, 0,
505 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
506 /* 0x43 - 1856x1392@120Hz RB */
507 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 356500, 1856, 1904,
508 1936, 2016, 0, 1392, 1395, 1399, 1474, 0,
509 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
510 /* 0x52 - 1920x1080@60Hz */
511 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
512 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
513 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
514 /* 0x44 - 1920x1200@60Hz RB */
515 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 154000, 1920, 1968,
516 2000, 2080, 0, 1200, 1203, 1209, 1235, 0,
517 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
518 /* 0x45 - 1920x1200@60Hz */
519 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 193250, 1920, 2056,
520 2256, 2592, 0, 1200, 1203, 1209, 1245, 0,
521 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
522 /* 0x46 - 1920x1200@75Hz */
523 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 245250, 1920, 2056,
524 2264, 2608, 0, 1200, 1203, 1209, 1255, 0,
525 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
526 /* 0x47 - 1920x1200@85Hz */
527 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 281250, 1920, 2064,
528 2272, 2624, 0, 1200, 1203, 1209, 1262, 0,
529 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
530 /* 0x48 - 1920x1200@120Hz RB */
531 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 317000, 1920, 1968,
532 2000, 2080, 0, 1200, 1203, 1209, 1271, 0,
533 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
534 /* 0x49 - 1920x1440@60Hz */
535 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 234000, 1920, 2048,
536 2256, 2600, 0, 1440, 1441, 1444, 1500, 0,
537 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
538 /* 0x4a - 1920x1440@75Hz */
539 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2064,
540 2288, 2640, 0, 1440, 1441, 1444, 1500, 0,
541 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
542 /* 0x4b - 1920x1440@120Hz RB */
543 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 380500, 1920, 1968,
544 2000, 2080, 0, 1440, 1443, 1447, 1525, 0,
545 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
546 /* 0x54 - 2048x1152@60Hz */
547 { DRM_MODE("2048x1152", DRM_MODE_TYPE_DRIVER, 162000, 2048, 2074,
548 2154, 2250, 0, 1152, 1153, 1156, 1200, 0,
549 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
550 /* 0x4c - 2560x1600@60Hz RB */
551 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 268500, 2560, 2608,
552 2640, 2720, 0, 1600, 1603, 1609, 1646, 0,
553 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
554 /* 0x4d - 2560x1600@60Hz */
555 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 348500, 2560, 2752,
556 3032, 3504, 0, 1600, 1603, 1609, 1658, 0,
557 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
558 /* 0x4e - 2560x1600@75Hz */
559 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 443250, 2560, 2768,
560 3048, 3536, 0, 1600, 1603, 1609, 1672, 0,
561 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
562 /* 0x4f - 2560x1600@85Hz */
563 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 505250, 2560, 2768,
564 3048, 3536, 0, 1600, 1603, 1609, 1682, 0,
565 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
566 /* 0x50 - 2560x1600@120Hz RB */
567 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 552750, 2560, 2608,
568 2640, 2720, 0, 1600, 1603, 1609, 1694, 0,
569 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
570 /* 0x57 - 4096x2160@60Hz RB */
571 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 556744, 4096, 4104,
572 4136, 4176, 0, 2160, 2208, 2216, 2222, 0,
573 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
574 /* 0x58 - 4096x2160@59.94Hz RB */
575 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 556188, 4096, 4104,
576 4136, 4176, 0, 2160, 2208, 2216, 2222, 0,
577 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
578};
579
580/*
581 * These more or less come from the DMT spec. The 720x400 modes are
582 * inferred from historical 80x25 practice. The 640x480@67 and 832x624@75
583 * modes are old-school Mac modes. The EDID spec says the 1152x864@75 mode
584 * should be 1152x870, again for the Mac, but instead we use the x864 DMT
585 * mode.
586 *
587 * The DMT modes have been fact-checked; the rest are mild guesses.
588 */
589static const struct drm_display_mode edid_est_modes[] = {
590 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840,
591 968, 1056, 0, 600, 601, 605, 628, 0,
592 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@60Hz */
593 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824,
594 896, 1024, 0, 600, 601, 603, 625, 0,
595 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@56Hz */
596 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656,
597 720, 840, 0, 480, 481, 484, 500, 0,
598 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@75Hz */
599 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664,
600 704, 832, 0, 480, 489, 492, 520, 0,
601 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@72Hz */
602 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 30240, 640, 704,
603 768, 864, 0, 480, 483, 486, 525, 0,
604 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@67Hz */
605 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
606 752, 800, 0, 480, 490, 492, 525, 0,
607 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@60Hz */
608 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 738,
609 846, 900, 0, 400, 421, 423, 449, 0,
610 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 720x400@88Hz */
611 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 28320, 720, 738,
612 846, 900, 0, 400, 412, 414, 449, 0,
613 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 720x400@70Hz */
614 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296,
615 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
616 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1280x1024@75Hz */
617 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040,
618 1136, 1312, 0, 768, 769, 772, 800, 0,
619 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1024x768@75Hz */
620 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048,
621 1184, 1328, 0, 768, 771, 777, 806, 0,
622 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@70Hz */
623 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048,
624 1184, 1344, 0, 768, 771, 777, 806, 0,
625 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@60Hz */
626 { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER,44900, 1024, 1032,
627 1208, 1264, 0, 768, 768, 776, 817, 0,
628 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_INTERLACE) }, /* 1024x768@43Hz */
629 { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 57284, 832, 864,
630 928, 1152, 0, 624, 625, 628, 667, 0,
631 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 832x624@75Hz */
632 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816,
633 896, 1056, 0, 600, 601, 604, 625, 0,
634 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@75Hz */
635 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856,
636 976, 1040, 0, 600, 637, 643, 666, 0,
637 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@72Hz */
638 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216,
639 1344, 1600, 0, 864, 865, 868, 900, 0,
640 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1152x864@75Hz */
641};
642
643struct minimode {
644 short w;
645 short h;
646 short r;
647 short rb;
648};
649
650static const struct minimode est3_modes[] = {
651 /* byte 6 */
652 { 640, 350, 85, 0 },
653 { 640, 400, 85, 0 },
654 { 720, 400, 85, 0 },
655 { 640, 480, 85, 0 },
656 { 848, 480, 60, 0 },
657 { 800, 600, 85, 0 },
658 { 1024, 768, 85, 0 },
659 { 1152, 864, 75, 0 },
660 /* byte 7 */
661 { 1280, 768, 60, 1 },
662 { 1280, 768, 60, 0 },
663 { 1280, 768, 75, 0 },
664 { 1280, 768, 85, 0 },
665 { 1280, 960, 60, 0 },
666 { 1280, 960, 85, 0 },
667 { 1280, 1024, 60, 0 },
668 { 1280, 1024, 85, 0 },
669 /* byte 8 */
670 { 1360, 768, 60, 0 },
671 { 1440, 900, 60, 1 },
672 { 1440, 900, 60, 0 },
673 { 1440, 900, 75, 0 },
674 { 1440, 900, 85, 0 },
675 { 1400, 1050, 60, 1 },
676 { 1400, 1050, 60, 0 },
677 { 1400, 1050, 75, 0 },
678 /* byte 9 */
679 { 1400, 1050, 85, 0 },
680 { 1680, 1050, 60, 1 },
681 { 1680, 1050, 60, 0 },
682 { 1680, 1050, 75, 0 },
683 { 1680, 1050, 85, 0 },
684 { 1600, 1200, 60, 0 },
685 { 1600, 1200, 65, 0 },
686 { 1600, 1200, 70, 0 },
687 /* byte 10 */
688 { 1600, 1200, 75, 0 },
689 { 1600, 1200, 85, 0 },
690 { 1792, 1344, 60, 0 },
691 { 1792, 1344, 75, 0 },
692 { 1856, 1392, 60, 0 },
693 { 1856, 1392, 75, 0 },
694 { 1920, 1200, 60, 1 },
695 { 1920, 1200, 60, 0 },
696 /* byte 11 */
697 { 1920, 1200, 75, 0 },
698 { 1920, 1200, 85, 0 },
699 { 1920, 1440, 60, 0 },
700 { 1920, 1440, 75, 0 },
701};
702
703static const struct minimode extra_modes[] = {
704 { 1024, 576, 60, 0 },
705 { 1366, 768, 60, 0 },
706 { 1600, 900, 60, 0 },
707 { 1680, 945, 60, 0 },
708 { 1920, 1080, 60, 0 },
709 { 2048, 1152, 60, 0 },
710 { 2048, 1536, 60, 0 },
711};
712
713/*
714 * From CEA/CTA-861 spec.
715 *
716 * Do not access directly, instead always use cea_mode_for_vic().
717 */
718static const struct drm_display_mode edid_cea_modes_1[] = {
719 /* 1 - 640x480@60Hz 4:3 */
720 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
721 752, 800, 0, 480, 490, 492, 525, 0,
722 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
723 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
724 /* 2 - 720x480@60Hz 4:3 */
725 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736,
726 798, 858, 0, 480, 489, 495, 525, 0,
727 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
728 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
729 /* 3 - 720x480@60Hz 16:9 */
730 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736,
731 798, 858, 0, 480, 489, 495, 525, 0,
732 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
733 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
734 /* 4 - 1280x720@60Hz 16:9 */
735 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390,
736 1430, 1650, 0, 720, 725, 730, 750, 0,
737 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
738 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
739 /* 5 - 1920x1080i@60Hz 16:9 */
740 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008,
741 2052, 2200, 0, 1080, 1084, 1094, 1125, 0,
742 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
743 DRM_MODE_FLAG_INTERLACE),
744 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
745 /* 6 - 720(1440)x480i@60Hz 4:3 */
746 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
747 801, 858, 0, 480, 488, 494, 525, 0,
748 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
749 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
750 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
751 /* 7 - 720(1440)x480i@60Hz 16:9 */
752 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
753 801, 858, 0, 480, 488, 494, 525, 0,
754 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
755 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
756 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
757 /* 8 - 720(1440)x240@60Hz 4:3 */
758 { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
759 801, 858, 0, 240, 244, 247, 262, 0,
760 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
761 DRM_MODE_FLAG_DBLCLK),
762 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
763 /* 9 - 720(1440)x240@60Hz 16:9 */
764 { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
765 801, 858, 0, 240, 244, 247, 262, 0,
766 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
767 DRM_MODE_FLAG_DBLCLK),
768 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
769 /* 10 - 2880x480i@60Hz 4:3 */
770 { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
771 3204, 3432, 0, 480, 488, 494, 525, 0,
772 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
773 DRM_MODE_FLAG_INTERLACE),
774 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
775 /* 11 - 2880x480i@60Hz 16:9 */
776 { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
777 3204, 3432, 0, 480, 488, 494, 525, 0,
778 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
779 DRM_MODE_FLAG_INTERLACE),
780 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
781 /* 12 - 2880x240@60Hz 4:3 */
782 { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
783 3204, 3432, 0, 240, 244, 247, 262, 0,
784 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
785 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
786 /* 13 - 2880x240@60Hz 16:9 */
787 { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
788 3204, 3432, 0, 240, 244, 247, 262, 0,
789 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
790 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
791 /* 14 - 1440x480@60Hz 4:3 */
792 { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472,
793 1596, 1716, 0, 480, 489, 495, 525, 0,
794 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
795 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
796 /* 15 - 1440x480@60Hz 16:9 */
797 { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472,
798 1596, 1716, 0, 480, 489, 495, 525, 0,
799 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
800 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
801 /* 16 - 1920x1080@60Hz 16:9 */
802 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
803 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
804 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
805 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
806 /* 17 - 720x576@50Hz 4:3 */
807 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
808 796, 864, 0, 576, 581, 586, 625, 0,
809 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
810 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
811 /* 18 - 720x576@50Hz 16:9 */
812 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
813 796, 864, 0, 576, 581, 586, 625, 0,
814 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
815 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
816 /* 19 - 1280x720@50Hz 16:9 */
817 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720,
818 1760, 1980, 0, 720, 725, 730, 750, 0,
819 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
820 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
821 /* 20 - 1920x1080i@50Hz 16:9 */
822 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448,
823 2492, 2640, 0, 1080, 1084, 1094, 1125, 0,
824 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
825 DRM_MODE_FLAG_INTERLACE),
826 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
827 /* 21 - 720(1440)x576i@50Hz 4:3 */
828 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
829 795, 864, 0, 576, 580, 586, 625, 0,
830 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
831 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
832 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
833 /* 22 - 720(1440)x576i@50Hz 16:9 */
834 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
835 795, 864, 0, 576, 580, 586, 625, 0,
836 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
837 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
838 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
839 /* 23 - 720(1440)x288@50Hz 4:3 */
840 { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
841 795, 864, 0, 288, 290, 293, 312, 0,
842 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
843 DRM_MODE_FLAG_DBLCLK),
844 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
845 /* 24 - 720(1440)x288@50Hz 16:9 */
846 { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
847 795, 864, 0, 288, 290, 293, 312, 0,
848 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
849 DRM_MODE_FLAG_DBLCLK),
850 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
851 /* 25 - 2880x576i@50Hz 4:3 */
852 { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
853 3180, 3456, 0, 576, 580, 586, 625, 0,
854 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
855 DRM_MODE_FLAG_INTERLACE),
856 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
857 /* 26 - 2880x576i@50Hz 16:9 */
858 { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
859 3180, 3456, 0, 576, 580, 586, 625, 0,
860 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
861 DRM_MODE_FLAG_INTERLACE),
862 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
863 /* 27 - 2880x288@50Hz 4:3 */
864 { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
865 3180, 3456, 0, 288, 290, 293, 312, 0,
866 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
867 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
868 /* 28 - 2880x288@50Hz 16:9 */
869 { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
870 3180, 3456, 0, 288, 290, 293, 312, 0,
871 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
872 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
873 /* 29 - 1440x576@50Hz 4:3 */
874 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464,
875 1592, 1728, 0, 576, 581, 586, 625, 0,
876 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
877 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
878 /* 30 - 1440x576@50Hz 16:9 */
879 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464,
880 1592, 1728, 0, 576, 581, 586, 625, 0,
881 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
882 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
883 /* 31 - 1920x1080@50Hz 16:9 */
884 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448,
885 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
886 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
887 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
888 /* 32 - 1920x1080@24Hz 16:9 */
889 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558,
890 2602, 2750, 0, 1080, 1084, 1089, 1125, 0,
891 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
892 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
893 /* 33 - 1920x1080@25Hz 16:9 */
894 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448,
895 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
896 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
897 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
898 /* 34 - 1920x1080@30Hz 16:9 */
899 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008,
900 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
901 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
902 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
903 /* 35 - 2880x480@60Hz 4:3 */
904 { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944,
905 3192, 3432, 0, 480, 489, 495, 525, 0,
906 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
907 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
908 /* 36 - 2880x480@60Hz 16:9 */
909 { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944,
910 3192, 3432, 0, 480, 489, 495, 525, 0,
911 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
912 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
913 /* 37 - 2880x576@50Hz 4:3 */
914 { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928,
915 3184, 3456, 0, 576, 581, 586, 625, 0,
916 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
917 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
918 /* 38 - 2880x576@50Hz 16:9 */
919 { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928,
920 3184, 3456, 0, 576, 581, 586, 625, 0,
921 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
922 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
923 /* 39 - 1920x1080i@50Hz 16:9 */
924 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 72000, 1920, 1952,
925 2120, 2304, 0, 1080, 1126, 1136, 1250, 0,
926 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC |
927 DRM_MODE_FLAG_INTERLACE),
928 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
929 /* 40 - 1920x1080i@100Hz 16:9 */
930 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448,
931 2492, 2640, 0, 1080, 1084, 1094, 1125, 0,
932 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
933 DRM_MODE_FLAG_INTERLACE),
934 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
935 /* 41 - 1280x720@100Hz 16:9 */
936 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720,
937 1760, 1980, 0, 720, 725, 730, 750, 0,
938 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
939 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
940 /* 42 - 720x576@100Hz 4:3 */
941 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
942 796, 864, 0, 576, 581, 586, 625, 0,
943 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
944 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
945 /* 43 - 720x576@100Hz 16:9 */
946 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
947 796, 864, 0, 576, 581, 586, 625, 0,
948 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
949 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
950 /* 44 - 720(1440)x576i@100Hz 4:3 */
951 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
952 795, 864, 0, 576, 580, 586, 625, 0,
953 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
954 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
955 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
956 /* 45 - 720(1440)x576i@100Hz 16:9 */
957 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
958 795, 864, 0, 576, 580, 586, 625, 0,
959 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
960 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
961 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
962 /* 46 - 1920x1080i@120Hz 16:9 */
963 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
964 2052, 2200, 0, 1080, 1084, 1094, 1125, 0,
965 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
966 DRM_MODE_FLAG_INTERLACE),
967 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
968 /* 47 - 1280x720@120Hz 16:9 */
969 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390,
970 1430, 1650, 0, 720, 725, 730, 750, 0,
971 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
972 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
973 /* 48 - 720x480@120Hz 4:3 */
974 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736,
975 798, 858, 0, 480, 489, 495, 525, 0,
976 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
977 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
978 /* 49 - 720x480@120Hz 16:9 */
979 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736,
980 798, 858, 0, 480, 489, 495, 525, 0,
981 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
982 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
983 /* 50 - 720(1440)x480i@120Hz 4:3 */
984 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739,
985 801, 858, 0, 480, 488, 494, 525, 0,
986 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
987 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
988 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
989 /* 51 - 720(1440)x480i@120Hz 16:9 */
990 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739,
991 801, 858, 0, 480, 488, 494, 525, 0,
992 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
993 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
994 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
995 /* 52 - 720x576@200Hz 4:3 */
996 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732,
997 796, 864, 0, 576, 581, 586, 625, 0,
998 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
999 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
1000 /* 53 - 720x576@200Hz 16:9 */
1001 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732,
1002 796, 864, 0, 576, 581, 586, 625, 0,
1003 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
1004 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1005 /* 54 - 720(1440)x576i@200Hz 4:3 */
1006 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
1007 795, 864, 0, 576, 580, 586, 625, 0,
1008 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
1009 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
1010 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
1011 /* 55 - 720(1440)x576i@200Hz 16:9 */
1012 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
1013 795, 864, 0, 576, 580, 586, 625, 0,
1014 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
1015 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
1016 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1017 /* 56 - 720x480@240Hz 4:3 */
1018 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736,
1019 798, 858, 0, 480, 489, 495, 525, 0,
1020 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
1021 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
1022 /* 57 - 720x480@240Hz 16:9 */
1023 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736,
1024 798, 858, 0, 480, 489, 495, 525, 0,
1025 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
1026 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1027 /* 58 - 720(1440)x480i@240Hz 4:3 */
1028 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739,
1029 801, 858, 0, 480, 488, 494, 525, 0,
1030 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
1031 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
1032 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
1033 /* 59 - 720(1440)x480i@240Hz 16:9 */
1034 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739,
1035 801, 858, 0, 480, 488, 494, 525, 0,
1036 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
1037 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
1038 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1039 /* 60 - 1280x720@24Hz 16:9 */
1040 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040,
1041 3080, 3300, 0, 720, 725, 730, 750, 0,
1042 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1043 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1044 /* 61 - 1280x720@25Hz 16:9 */
1045 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700,
1046 3740, 3960, 0, 720, 725, 730, 750, 0,
1047 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1048 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1049 /* 62 - 1280x720@30Hz 16:9 */
1050 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040,
1051 3080, 3300, 0, 720, 725, 730, 750, 0,
1052 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1053 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1054 /* 63 - 1920x1080@120Hz 16:9 */
1055 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008,
1056 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
1057 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1058 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1059 /* 64 - 1920x1080@100Hz 16:9 */
1060 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448,
1061 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
1062 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1063 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1064 /* 65 - 1280x720@24Hz 64:27 */
1065 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040,
1066 3080, 3300, 0, 720, 725, 730, 750, 0,
1067 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1068 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1069 /* 66 - 1280x720@25Hz 64:27 */
1070 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700,
1071 3740, 3960, 0, 720, 725, 730, 750, 0,
1072 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1073 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1074 /* 67 - 1280x720@30Hz 64:27 */
1075 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040,
1076 3080, 3300, 0, 720, 725, 730, 750, 0,
1077 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1078 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1079 /* 68 - 1280x720@50Hz 64:27 */
1080 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720,
1081 1760, 1980, 0, 720, 725, 730, 750, 0,
1082 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1083 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1084 /* 69 - 1280x720@60Hz 64:27 */
1085 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390,
1086 1430, 1650, 0, 720, 725, 730, 750, 0,
1087 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1088 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1089 /* 70 - 1280x720@100Hz 64:27 */
1090 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720,
1091 1760, 1980, 0, 720, 725, 730, 750, 0,
1092 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1093 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1094 /* 71 - 1280x720@120Hz 64:27 */
1095 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390,
1096 1430, 1650, 0, 720, 725, 730, 750, 0,
1097 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1098 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1099 /* 72 - 1920x1080@24Hz 64:27 */
1100 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558,
1101 2602, 2750, 0, 1080, 1084, 1089, 1125, 0,
1102 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1103 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1104 /* 73 - 1920x1080@25Hz 64:27 */
1105 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448,
1106 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
1107 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1108 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1109 /* 74 - 1920x1080@30Hz 64:27 */
1110 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008,
1111 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
1112 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1113 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1114 /* 75 - 1920x1080@50Hz 64:27 */
1115 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448,
1116 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
1117 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1118 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1119 /* 76 - 1920x1080@60Hz 64:27 */
1120 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
1121 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
1122 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1123 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1124 /* 77 - 1920x1080@100Hz 64:27 */
1125 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448,
1126 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
1127 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1128 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1129 /* 78 - 1920x1080@120Hz 64:27 */
1130 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008,
1131 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
1132 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1133 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1134 /* 79 - 1680x720@24Hz 64:27 */
1135 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 3040,
1136 3080, 3300, 0, 720, 725, 730, 750, 0,
1137 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1138 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1139 /* 80 - 1680x720@25Hz 64:27 */
1140 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 2908,
1141 2948, 3168, 0, 720, 725, 730, 750, 0,
1142 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1143 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1144 /* 81 - 1680x720@30Hz 64:27 */
1145 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 2380,
1146 2420, 2640, 0, 720, 725, 730, 750, 0,
1147 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1148 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1149 /* 82 - 1680x720@50Hz 64:27 */
1150 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 82500, 1680, 1940,
1151 1980, 2200, 0, 720, 725, 730, 750, 0,
1152 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1153 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1154 /* 83 - 1680x720@60Hz 64:27 */
1155 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 99000, 1680, 1940,
1156 1980, 2200, 0, 720, 725, 730, 750, 0,
1157 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1158 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1159 /* 84 - 1680x720@100Hz 64:27 */
1160 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 165000, 1680, 1740,
1161 1780, 2000, 0, 720, 725, 730, 825, 0,
1162 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1163 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1164 /* 85 - 1680x720@120Hz 64:27 */
1165 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 198000, 1680, 1740,
1166 1780, 2000, 0, 720, 725, 730, 825, 0,
1167 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1168 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1169 /* 86 - 2560x1080@24Hz 64:27 */
1170 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 99000, 2560, 3558,
1171 3602, 3750, 0, 1080, 1084, 1089, 1100, 0,
1172 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1173 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1174 /* 87 - 2560x1080@25Hz 64:27 */
1175 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 90000, 2560, 3008,
1176 3052, 3200, 0, 1080, 1084, 1089, 1125, 0,
1177 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1178 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1179 /* 88 - 2560x1080@30Hz 64:27 */
1180 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 118800, 2560, 3328,
1181 3372, 3520, 0, 1080, 1084, 1089, 1125, 0,
1182 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1183 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1184 /* 89 - 2560x1080@50Hz 64:27 */
1185 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 185625, 2560, 3108,
1186 3152, 3300, 0, 1080, 1084, 1089, 1125, 0,
1187 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1188 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1189 /* 90 - 2560x1080@60Hz 64:27 */
1190 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 198000, 2560, 2808,
1191 2852, 3000, 0, 1080, 1084, 1089, 1100, 0,
1192 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1193 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1194 /* 91 - 2560x1080@100Hz 64:27 */
1195 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 371250, 2560, 2778,
1196 2822, 2970, 0, 1080, 1084, 1089, 1250, 0,
1197 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1198 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1199 /* 92 - 2560x1080@120Hz 64:27 */
1200 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 495000, 2560, 3108,
1201 3152, 3300, 0, 1080, 1084, 1089, 1250, 0,
1202 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1203 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1204 /* 93 - 3840x2160@24Hz 16:9 */
1205 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 5116,
1206 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1207 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1208 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1209 /* 94 - 3840x2160@25Hz 16:9 */
1210 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4896,
1211 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1212 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1213 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1214 /* 95 - 3840x2160@30Hz 16:9 */
1215 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4016,
1216 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1217 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1218 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1219 /* 96 - 3840x2160@50Hz 16:9 */
1220 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4896,
1221 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1222 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1223 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1224 /* 97 - 3840x2160@60Hz 16:9 */
1225 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4016,
1226 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1227 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1228 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1229 /* 98 - 4096x2160@24Hz 256:135 */
1230 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 5116,
1231 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1232 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1233 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1234 /* 99 - 4096x2160@25Hz 256:135 */
1235 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 5064,
1236 5152, 5280, 0, 2160, 2168, 2178, 2250, 0,
1237 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1238 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1239 /* 100 - 4096x2160@30Hz 256:135 */
1240 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 4184,
1241 4272, 4400, 0, 2160, 2168, 2178, 2250, 0,
1242 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1243 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1244 /* 101 - 4096x2160@50Hz 256:135 */
1245 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 5064,
1246 5152, 5280, 0, 2160, 2168, 2178, 2250, 0,
1247 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1248 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1249 /* 102 - 4096x2160@60Hz 256:135 */
1250 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 4184,
1251 4272, 4400, 0, 2160, 2168, 2178, 2250, 0,
1252 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1253 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1254 /* 103 - 3840x2160@24Hz 64:27 */
1255 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 5116,
1256 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1257 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1258 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1259 /* 104 - 3840x2160@25Hz 64:27 */
1260 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4896,
1261 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1262 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1263 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1264 /* 105 - 3840x2160@30Hz 64:27 */
1265 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4016,
1266 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1267 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1268 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1269 /* 106 - 3840x2160@50Hz 64:27 */
1270 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4896,
1271 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1272 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1273 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1274 /* 107 - 3840x2160@60Hz 64:27 */
1275 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4016,
1276 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1277 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1278 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1279 /* 108 - 1280x720@48Hz 16:9 */
1280 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 90000, 1280, 2240,
1281 2280, 2500, 0, 720, 725, 730, 750, 0,
1282 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1283 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1284 /* 109 - 1280x720@48Hz 64:27 */
1285 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 90000, 1280, 2240,
1286 2280, 2500, 0, 720, 725, 730, 750, 0,
1287 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1288 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1289 /* 110 - 1680x720@48Hz 64:27 */
1290 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 99000, 1680, 2490,
1291 2530, 2750, 0, 720, 725, 730, 750, 0,
1292 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1293 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1294 /* 111 - 1920x1080@48Hz 16:9 */
1295 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2558,
1296 2602, 2750, 0, 1080, 1084, 1089, 1125, 0,
1297 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1298 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1299 /* 112 - 1920x1080@48Hz 64:27 */
1300 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2558,
1301 2602, 2750, 0, 1080, 1084, 1089, 1125, 0,
1302 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1303 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1304 /* 113 - 2560x1080@48Hz 64:27 */
1305 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 198000, 2560, 3558,
1306 3602, 3750, 0, 1080, 1084, 1089, 1100, 0,
1307 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1308 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1309 /* 114 - 3840x2160@48Hz 16:9 */
1310 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 5116,
1311 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1312 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1313 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1314 /* 115 - 4096x2160@48Hz 256:135 */
1315 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 5116,
1316 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1317 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1318 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1319 /* 116 - 3840x2160@48Hz 64:27 */
1320 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 5116,
1321 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1322 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1323 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1324 /* 117 - 3840x2160@100Hz 16:9 */
1325 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4896,
1326 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1327 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1328 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1329 /* 118 - 3840x2160@120Hz 16:9 */
1330 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4016,
1331 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1332 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1333 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1334 /* 119 - 3840x2160@100Hz 64:27 */
1335 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4896,
1336 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1337 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1338 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1339 /* 120 - 3840x2160@120Hz 64:27 */
1340 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4016,
1341 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1342 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1343 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1344 /* 121 - 5120x2160@24Hz 64:27 */
1345 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 396000, 5120, 7116,
1346 7204, 7500, 0, 2160, 2168, 2178, 2200, 0,
1347 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1348 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1349 /* 122 - 5120x2160@25Hz 64:27 */
1350 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 396000, 5120, 6816,
1351 6904, 7200, 0, 2160, 2168, 2178, 2200, 0,
1352 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1353 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1354 /* 123 - 5120x2160@30Hz 64:27 */
1355 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 396000, 5120, 5784,
1356 5872, 6000, 0, 2160, 2168, 2178, 2200, 0,
1357 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1358 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1359 /* 124 - 5120x2160@48Hz 64:27 */
1360 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 742500, 5120, 5866,
1361 5954, 6250, 0, 2160, 2168, 2178, 2475, 0,
1362 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1363 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1364 /* 125 - 5120x2160@50Hz 64:27 */
1365 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 742500, 5120, 6216,
1366 6304, 6600, 0, 2160, 2168, 2178, 2250, 0,
1367 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1368 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1369 /* 126 - 5120x2160@60Hz 64:27 */
1370 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 742500, 5120, 5284,
1371 5372, 5500, 0, 2160, 2168, 2178, 2250, 0,
1372 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1373 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1374 /* 127 - 5120x2160@100Hz 64:27 */
1375 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 1485000, 5120, 6216,
1376 6304, 6600, 0, 2160, 2168, 2178, 2250, 0,
1377 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1378 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1379};
1380
1381/*
1382 * From CEA/CTA-861 spec.
1383 *
1384 * Do not access directly, instead always use cea_mode_for_vic().
1385 */
1386static const struct drm_display_mode edid_cea_modes_193[] = {
1387 /* 193 - 5120x2160@120Hz 64:27 */
1388 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 1485000, 5120, 5284,
1389 5372, 5500, 0, 2160, 2168, 2178, 2250, 0,
1390 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1391 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1392 /* 194 - 7680x4320@24Hz 16:9 */
1393 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10232,
1394 10408, 11000, 0, 4320, 4336, 4356, 4500, 0,
1395 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1396 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1397 /* 195 - 7680x4320@25Hz 16:9 */
1398 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10032,
1399 10208, 10800, 0, 4320, 4336, 4356, 4400, 0,
1400 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1401 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1402 /* 196 - 7680x4320@30Hz 16:9 */
1403 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 8232,
1404 8408, 9000, 0, 4320, 4336, 4356, 4400, 0,
1405 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1406 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1407 /* 197 - 7680x4320@48Hz 16:9 */
1408 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10232,
1409 10408, 11000, 0, 4320, 4336, 4356, 4500, 0,
1410 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1411 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1412 /* 198 - 7680x4320@50Hz 16:9 */
1413 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10032,
1414 10208, 10800, 0, 4320, 4336, 4356, 4400, 0,
1415 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1416 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1417 /* 199 - 7680x4320@60Hz 16:9 */
1418 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 8232,
1419 8408, 9000, 0, 4320, 4336, 4356, 4400, 0,
1420 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1421 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1422 /* 200 - 7680x4320@100Hz 16:9 */
1423 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 9792,
1424 9968, 10560, 0, 4320, 4336, 4356, 4500, 0,
1425 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1426 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1427 /* 201 - 7680x4320@120Hz 16:9 */
1428 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 8032,
1429 8208, 8800, 0, 4320, 4336, 4356, 4500, 0,
1430 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1431 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1432 /* 202 - 7680x4320@24Hz 64:27 */
1433 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10232,
1434 10408, 11000, 0, 4320, 4336, 4356, 4500, 0,
1435 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1436 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1437 /* 203 - 7680x4320@25Hz 64:27 */
1438 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10032,
1439 10208, 10800, 0, 4320, 4336, 4356, 4400, 0,
1440 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1441 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1442 /* 204 - 7680x4320@30Hz 64:27 */
1443 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 8232,
1444 8408, 9000, 0, 4320, 4336, 4356, 4400, 0,
1445 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1446 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1447 /* 205 - 7680x4320@48Hz 64:27 */
1448 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10232,
1449 10408, 11000, 0, 4320, 4336, 4356, 4500, 0,
1450 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1451 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1452 /* 206 - 7680x4320@50Hz 64:27 */
1453 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10032,
1454 10208, 10800, 0, 4320, 4336, 4356, 4400, 0,
1455 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1456 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1457 /* 207 - 7680x4320@60Hz 64:27 */
1458 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 8232,
1459 8408, 9000, 0, 4320, 4336, 4356, 4400, 0,
1460 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1461 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1462 /* 208 - 7680x4320@100Hz 64:27 */
1463 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 9792,
1464 9968, 10560, 0, 4320, 4336, 4356, 4500, 0,
1465 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1466 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1467 /* 209 - 7680x4320@120Hz 64:27 */
1468 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 8032,
1469 8208, 8800, 0, 4320, 4336, 4356, 4500, 0,
1470 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1471 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1472 /* 210 - 10240x4320@24Hz 64:27 */
1473 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 1485000, 10240, 11732,
1474 11908, 12500, 0, 4320, 4336, 4356, 4950, 0,
1475 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1476 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1477 /* 211 - 10240x4320@25Hz 64:27 */
1478 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 1485000, 10240, 12732,
1479 12908, 13500, 0, 4320, 4336, 4356, 4400, 0,
1480 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1481 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1482 /* 212 - 10240x4320@30Hz 64:27 */
1483 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 1485000, 10240, 10528,
1484 10704, 11000, 0, 4320, 4336, 4356, 4500, 0,
1485 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1486 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1487 /* 213 - 10240x4320@48Hz 64:27 */
1488 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 2970000, 10240, 11732,
1489 11908, 12500, 0, 4320, 4336, 4356, 4950, 0,
1490 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1491 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1492 /* 214 - 10240x4320@50Hz 64:27 */
1493 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 2970000, 10240, 12732,
1494 12908, 13500, 0, 4320, 4336, 4356, 4400, 0,
1495 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1496 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1497 /* 215 - 10240x4320@60Hz 64:27 */
1498 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 2970000, 10240, 10528,
1499 10704, 11000, 0, 4320, 4336, 4356, 4500, 0,
1500 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1501 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1502 /* 216 - 10240x4320@100Hz 64:27 */
1503 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 5940000, 10240, 12432,
1504 12608, 13200, 0, 4320, 4336, 4356, 4500, 0,
1505 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1506 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1507 /* 217 - 10240x4320@120Hz 64:27 */
1508 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 5940000, 10240, 10528,
1509 10704, 11000, 0, 4320, 4336, 4356, 4500, 0,
1510 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1511 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1512 /* 218 - 4096x2160@100Hz 256:135 */
1513 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 1188000, 4096, 4896,
1514 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1515 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1516 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1517 /* 219 - 4096x2160@120Hz 256:135 */
1518 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 1188000, 4096, 4184,
1519 4272, 4400, 0, 2160, 2168, 2178, 2250, 0,
1520 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1521 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1522};
1523
1524/*
1525 * HDMI 1.4 4k modes. Index using the VIC.
1526 */
1527static const struct drm_display_mode edid_4k_modes[] = {
1528 /* 0 - dummy, VICs start at 1 */
1529 { },
1530 /* 1 - 3840x2160@30Hz */
1531 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000,
1532 3840, 4016, 4104, 4400, 0,
1533 2160, 2168, 2178, 2250, 0,
1534 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1535 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1536 /* 2 - 3840x2160@25Hz */
1537 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000,
1538 3840, 4896, 4984, 5280, 0,
1539 2160, 2168, 2178, 2250, 0,
1540 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1541 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1542 /* 3 - 3840x2160@24Hz */
1543 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000,
1544 3840, 5116, 5204, 5500, 0,
1545 2160, 2168, 2178, 2250, 0,
1546 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1547 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1548 /* 4 - 4096x2160@24Hz (SMPTE) */
1549 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000,
1550 4096, 5116, 5204, 5500, 0,
1551 2160, 2168, 2178, 2250, 0,
1552 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1553 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1554};
1555
1556/*** DDC fetch and block validation ***/
1557
1558static const u8 edid_header[] = {
1559 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00
1560};
1561
1562/**
1563 * drm_edid_header_is_valid - sanity check the header of the base EDID block
1564 * @raw_edid: pointer to raw base EDID block
1565 *
1566 * Sanity check the header of the base EDID block.
1567 *
1568 * Return: 8 if the header is perfect, down to 0 if it's totally wrong.
1569 */
1570int drm_edid_header_is_valid(const u8 *raw_edid)
1571{
1572 int i, score = 0;
1573
1574 for (i = 0; i < sizeof(edid_header); i++)
1575 if (raw_edid[i] == edid_header[i])
1576 score++;
1577
1578 return score;
1579}
1580EXPORT_SYMBOL(drm_edid_header_is_valid);
1581
1582static int edid_fixup __read_mostly = 6;
1583module_param_named(edid_fixup, edid_fixup, int, 0400);
1584MODULE_PARM_DESC(edid_fixup,
1585 "Minimum number of valid EDID header bytes (0-8, default 6)");
1586
1587static int validate_displayid(u8 *displayid, int length, int idx);
1588
1589static int drm_edid_block_checksum(const u8 *raw_edid)
1590{
1591 int i;
1592 u8 csum = 0, crc = 0;
1593
1594 for (i = 0; i < EDID_LENGTH - 1; i++)
1595 csum += raw_edid[i];
1596
1597 crc = 0x100 - csum;
1598
1599 return crc;
1600}
1601
1602static bool drm_edid_block_checksum_diff(const u8 *raw_edid, u8 real_checksum)
1603{
1604 if (raw_edid[EDID_LENGTH - 1] != real_checksum)
1605 return true;
1606 else
1607 return false;
1608}
1609
1610static bool drm_edid_is_zero(const u8 *in_edid, int length)
1611{
1612 if (memchr_inv(in_edid, 0, length))
1613 return false;
1614
1615 return true;
1616}
1617
1618/**
1619 * drm_edid_are_equal - compare two edid blobs.
1620 * @edid1: pointer to first blob
1621 * @edid2: pointer to second blob
1622 * This helper can be used during probing to determine if
1623 * edid had changed.
1624 */
1625bool drm_edid_are_equal(const struct edid *edid1, const struct edid *edid2)
1626{
1627 int edid1_len, edid2_len;
1628 bool edid1_present = edid1 != NULL;
1629 bool edid2_present = edid2 != NULL;
1630
1631 if (edid1_present != edid2_present)
1632 return false;
1633
1634 if (edid1) {
1635 edid1_len = EDID_LENGTH * (1 + edid1->extensions);
1636 edid2_len = EDID_LENGTH * (1 + edid2->extensions);
1637
1638 if (edid1_len != edid2_len)
1639 return false;
1640
1641 if (memcmp(edid1, edid2, edid1_len))
1642 return false;
1643 }
1644
1645 return true;
1646}
1647EXPORT_SYMBOL(drm_edid_are_equal);
1648
1649/**
1650 * drm_edid_block_valid - Sanity check the EDID block (base or extension)
1651 * @raw_edid: pointer to raw EDID block
1652 * @block: type of block to validate (0 for base, extension otherwise)
1653 * @print_bad_edid: if true, dump bad EDID blocks to the console
1654 * @edid_corrupt: if true, the header or checksum is invalid
1655 *
1656 * Validate a base or extension EDID block and optionally dump bad blocks to
1657 * the console.
1658 *
1659 * Return: True if the block is valid, false otherwise.
1660 */
1661bool drm_edid_block_valid(u8 *raw_edid, int block, bool print_bad_edid,
1662 bool *edid_corrupt)
1663{
1664 u8 csum;
1665 struct edid *edid = (struct edid *)raw_edid;
1666
1667 if (WARN_ON(!raw_edid))
1668 return false;
1669
1670 if (edid_fixup > 8 || edid_fixup < 0)
1671 edid_fixup = 6;
1672
1673 if (block == 0) {
1674 int score = drm_edid_header_is_valid(raw_edid);
1675
1676 if (score == 8) {
1677 if (edid_corrupt)
1678 *edid_corrupt = false;
1679 } else if (score >= edid_fixup) {
1680 /* Displayport Link CTS Core 1.2 rev1.1 test 4.2.2.6
1681 * The corrupt flag needs to be set here otherwise, the
1682 * fix-up code here will correct the problem, the
1683 * checksum is correct and the test fails
1684 */
1685 if (edid_corrupt)
1686 *edid_corrupt = true;
1687 DRM_DEBUG("Fixing EDID header, your hardware may be failing\n");
1688 memcpy(raw_edid, edid_header, sizeof(edid_header));
1689 } else {
1690 if (edid_corrupt)
1691 *edid_corrupt = true;
1692 goto bad;
1693 }
1694 }
1695
1696 csum = drm_edid_block_checksum(raw_edid);
1697 if (drm_edid_block_checksum_diff(raw_edid, csum)) {
1698 if (edid_corrupt)
1699 *edid_corrupt = true;
1700
1701 /* allow CEA to slide through, switches mangle this */
1702 if (raw_edid[0] == CEA_EXT) {
1703 DRM_DEBUG("EDID checksum is invalid, remainder is %d\n", csum);
1704 DRM_DEBUG("Assuming a KVM switch modified the CEA block but left the original checksum\n");
1705 } else {
1706 if (print_bad_edid)
1707 DRM_NOTE("EDID checksum is invalid, remainder is %d\n", csum);
1708
1709 goto bad;
1710 }
1711 }
1712
1713 /* per-block-type checks */
1714 switch (raw_edid[0]) {
1715 case 0: /* base */
1716 if (edid->version != 1) {
1717 DRM_NOTE("EDID has major version %d, instead of 1\n", edid->version);
1718 goto bad;
1719 }
1720
1721 if (edid->revision > 4)
1722 DRM_DEBUG("EDID minor > 4, assuming backward compatibility\n");
1723 break;
1724
1725 default:
1726 break;
1727 }
1728
1729 return true;
1730
1731bad:
1732 if (print_bad_edid) {
1733 if (drm_edid_is_zero(raw_edid, EDID_LENGTH)) {
1734 pr_notice("EDID block is all zeroes\n");
1735 } else {
1736 pr_notice("Raw EDID:\n");
1737 print_hex_dump(KERN_NOTICE,
1738 " \t", DUMP_PREFIX_NONE, 16, 1,
1739 raw_edid, EDID_LENGTH, false);
1740 }
1741 }
1742 return false;
1743}
1744EXPORT_SYMBOL(drm_edid_block_valid);
1745
1746/**
1747 * drm_edid_is_valid - sanity check EDID data
1748 * @edid: EDID data
1749 *
1750 * Sanity-check an entire EDID record (including extensions)
1751 *
1752 * Return: True if the EDID data is valid, false otherwise.
1753 */
1754bool drm_edid_is_valid(struct edid *edid)
1755{
1756 int i;
1757 u8 *raw = (u8 *)edid;
1758
1759 if (!edid)
1760 return false;
1761
1762 for (i = 0; i <= edid->extensions; i++)
1763 if (!drm_edid_block_valid(raw + i * EDID_LENGTH, i, true, NULL))
1764 return false;
1765
1766 return true;
1767}
1768EXPORT_SYMBOL(drm_edid_is_valid);
1769
1770#define DDC_SEGMENT_ADDR 0x30
1771/**
1772 * drm_do_probe_ddc_edid() - get EDID information via I2C
1773 * @data: I2C device adapter
1774 * @buf: EDID data buffer to be filled
1775 * @block: 128 byte EDID block to start fetching from
1776 * @len: EDID data buffer length to fetch
1777 *
1778 * Try to fetch EDID information by calling I2C driver functions.
1779 *
1780 * Return: 0 on success or -1 on failure.
1781 */
1782static int
1783drm_do_probe_ddc_edid(void *data, u8 *buf, unsigned int block, size_t len)
1784{
1785 struct i2c_adapter *adapter = data;
1786 unsigned char start = block * EDID_LENGTH;
1787 unsigned char segment = block >> 1;
1788 unsigned char xfers = segment ? 3 : 2;
1789 int ret, retries = 5;
1790
1791 /*
1792 * The core I2C driver will automatically retry the transfer if the
1793 * adapter reports EAGAIN. However, we find that bit-banging transfers
1794 * are susceptible to errors under a heavily loaded machine and
1795 * generate spurious NAKs and timeouts. Retrying the transfer
1796 * of the individual block a few times seems to overcome this.
1797 */
1798 do {
1799 struct i2c_msg msgs[] = {
1800 {
1801 .addr = DDC_SEGMENT_ADDR,
1802 .flags = 0,
1803 .len = 1,
1804 .buf = &segment,
1805 }, {
1806 .addr = DDC_ADDR,
1807 .flags = 0,
1808 .len = 1,
1809 .buf = &start,
1810 }, {
1811 .addr = DDC_ADDR,
1812 .flags = I2C_M_RD,
1813 .len = len,
1814 .buf = buf,
1815 }
1816 };
1817
1818 /*
1819 * Avoid sending the segment addr to not upset non-compliant
1820 * DDC monitors.
1821 */
1822 ret = i2c_transfer(adapter, &msgs[3 - xfers], xfers);
1823
1824 if (ret == -ENXIO) {
1825 DRM_DEBUG_KMS("drm: skipping non-existent adapter %s\n",
1826 adapter->name);
1827 break;
1828 }
1829 } while (ret != xfers && --retries);
1830
1831 return ret == xfers ? 0 : -1;
1832}
1833
1834static void connector_bad_edid(struct drm_connector *connector,
1835 u8 *edid, int num_blocks)
1836{
1837 int i;
1838 u8 num_of_ext = edid[0x7e];
1839
1840 /* Calculate real checksum for the last edid extension block data */
1841 connector->real_edid_checksum =
1842 drm_edid_block_checksum(edid + num_of_ext * EDID_LENGTH);
1843
1844 if (connector->bad_edid_counter++ && !drm_debug_enabled(DRM_UT_KMS))
1845 return;
1846
1847 drm_warn(connector->dev, "%s: EDID is invalid:\n", connector->name);
1848 for (i = 0; i < num_blocks; i++) {
1849 u8 *block = edid + i * EDID_LENGTH;
1850 char prefix[20];
1851
1852 if (drm_edid_is_zero(block, EDID_LENGTH))
1853 sprintf(prefix, "\t[%02x] ZERO ", i);
1854 else if (!drm_edid_block_valid(block, i, false, NULL))
1855 sprintf(prefix, "\t[%02x] BAD ", i);
1856 else
1857 sprintf(prefix, "\t[%02x] GOOD ", i);
1858
1859 print_hex_dump(KERN_WARNING,
1860 prefix, DUMP_PREFIX_NONE, 16, 1,
1861 block, EDID_LENGTH, false);
1862 }
1863}
1864
1865/* Get override or firmware EDID */
1866static struct edid *drm_get_override_edid(struct drm_connector *connector)
1867{
1868 struct edid *override = NULL;
1869
1870 if (connector->override_edid)
1871 override = drm_edid_duplicate(connector->edid_blob_ptr->data);
1872
1873 if (!override)
1874 override = drm_load_edid_firmware(connector);
1875
1876 return IS_ERR(override) ? NULL : override;
1877}
1878
1879/**
1880 * drm_add_override_edid_modes - add modes from override/firmware EDID
1881 * @connector: connector we're probing
1882 *
1883 * Add modes from the override/firmware EDID, if available. Only to be used from
1884 * drm_helper_probe_single_connector_modes() as a fallback for when DDC probe
1885 * failed during drm_get_edid() and caused the override/firmware EDID to be
1886 * skipped.
1887 *
1888 * Return: The number of modes added or 0 if we couldn't find any.
1889 */
1890int drm_add_override_edid_modes(struct drm_connector *connector)
1891{
1892 struct edid *override;
1893 int num_modes = 0;
1894
1895 override = drm_get_override_edid(connector);
1896 if (override) {
1897 drm_connector_update_edid_property(connector, override);
1898 num_modes = drm_add_edid_modes(connector, override);
1899 kfree(override);
1900
1901 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] adding %d modes via fallback override/firmware EDID\n",
1902 connector->base.id, connector->name, num_modes);
1903 }
1904
1905 return num_modes;
1906}
1907EXPORT_SYMBOL(drm_add_override_edid_modes);
1908
1909/**
1910 * drm_do_get_edid - get EDID data using a custom EDID block read function
1911 * @connector: connector we're probing
1912 * @get_edid_block: EDID block read function
1913 * @data: private data passed to the block read function
1914 *
1915 * When the I2C adapter connected to the DDC bus is hidden behind a device that
1916 * exposes a different interface to read EDID blocks this function can be used
1917 * to get EDID data using a custom block read function.
1918 *
1919 * As in the general case the DDC bus is accessible by the kernel at the I2C
1920 * level, drivers must make all reasonable efforts to expose it as an I2C
1921 * adapter and use drm_get_edid() instead of abusing this function.
1922 *
1923 * The EDID may be overridden using debugfs override_edid or firmare EDID
1924 * (drm_load_edid_firmware() and drm.edid_firmware parameter), in this priority
1925 * order. Having either of them bypasses actual EDID reads.
1926 *
1927 * Return: Pointer to valid EDID or NULL if we couldn't find any.
1928 */
1929struct edid *drm_do_get_edid(struct drm_connector *connector,
1930 int (*get_edid_block)(void *data, u8 *buf, unsigned int block,
1931 size_t len),
1932 void *data)
1933{
1934 int i, j = 0, valid_extensions = 0;
1935 u8 *edid, *new;
1936 struct edid *override;
1937
1938 override = drm_get_override_edid(connector);
1939 if (override)
1940 return override;
1941
1942 if ((edid = kmalloc(EDID_LENGTH, GFP_KERNEL)) == NULL)
1943 return NULL;
1944
1945 /* base block fetch */
1946 for (i = 0; i < 4; i++) {
1947 if (get_edid_block(data, edid, 0, EDID_LENGTH))
1948 goto out;
1949 if (drm_edid_block_valid(edid, 0, false,
1950 &connector->edid_corrupt))
1951 break;
1952 if (i == 0 && drm_edid_is_zero(edid, EDID_LENGTH)) {
1953 connector->null_edid_counter++;
1954 goto carp;
1955 }
1956 }
1957 if (i == 4)
1958 goto carp;
1959
1960 /* if there's no extensions, we're done */
1961 valid_extensions = edid[0x7e];
1962 if (valid_extensions == 0)
1963 return (struct edid *)edid;
1964
1965 new = krealloc(edid, (valid_extensions + 1) * EDID_LENGTH, GFP_KERNEL);
1966 if (!new)
1967 goto out;
1968 edid = new;
1969
1970 for (j = 1; j <= edid[0x7e]; j++) {
1971 u8 *block = edid + j * EDID_LENGTH;
1972
1973 for (i = 0; i < 4; i++) {
1974 if (get_edid_block(data, block, j, EDID_LENGTH))
1975 goto out;
1976 if (drm_edid_block_valid(block, j, false, NULL))
1977 break;
1978 }
1979
1980 if (i == 4)
1981 valid_extensions--;
1982 }
1983
1984 if (valid_extensions != edid[0x7e]) {
1985 u8 *base;
1986
1987 connector_bad_edid(connector, edid, edid[0x7e] + 1);
1988
1989 edid[EDID_LENGTH-1] += edid[0x7e] - valid_extensions;
1990 edid[0x7e] = valid_extensions;
1991
1992 new = kmalloc_array(valid_extensions + 1, EDID_LENGTH,
1993 GFP_KERNEL);
1994 if (!new)
1995 goto out;
1996
1997 base = new;
1998 for (i = 0; i <= edid[0x7e]; i++) {
1999 u8 *block = edid + i * EDID_LENGTH;
2000
2001 if (!drm_edid_block_valid(block, i, false, NULL))
2002 continue;
2003
2004 memcpy(base, block, EDID_LENGTH);
2005 base += EDID_LENGTH;
2006 }
2007
2008 kfree(edid);
2009 edid = new;
2010 }
2011
2012 return (struct edid *)edid;
2013
2014carp:
2015 connector_bad_edid(connector, edid, 1);
2016out:
2017 kfree(edid);
2018 return NULL;
2019}
2020EXPORT_SYMBOL_GPL(drm_do_get_edid);
2021
2022/**
2023 * drm_probe_ddc() - probe DDC presence
2024 * @adapter: I2C adapter to probe
2025 *
2026 * Return: True on success, false on failure.
2027 */
2028bool
2029drm_probe_ddc(struct i2c_adapter *adapter)
2030{
2031 unsigned char out;
2032
2033 return (drm_do_probe_ddc_edid(adapter, &out, 0, 1) == 0);
2034}
2035EXPORT_SYMBOL(drm_probe_ddc);
2036
2037/**
2038 * drm_get_edid - get EDID data, if available
2039 * @connector: connector we're probing
2040 * @adapter: I2C adapter to use for DDC
2041 *
2042 * Poke the given I2C channel to grab EDID data if possible. If found,
2043 * attach it to the connector.
2044 *
2045 * Return: Pointer to valid EDID or NULL if we couldn't find any.
2046 */
2047struct edid *drm_get_edid(struct drm_connector *connector,
2048 struct i2c_adapter *adapter)
2049{
2050 struct edid *edid;
2051
2052 if (connector->force == DRM_FORCE_OFF)
2053 return NULL;
2054
2055 if (connector->force == DRM_FORCE_UNSPECIFIED && !drm_probe_ddc(adapter))
2056 return NULL;
2057
2058 edid = drm_do_get_edid(connector, drm_do_probe_ddc_edid, adapter);
2059 drm_connector_update_edid_property(connector, edid);
2060 return edid;
2061}
2062EXPORT_SYMBOL(drm_get_edid);
2063
2064/**
2065 * drm_get_edid_switcheroo - get EDID data for a vga_switcheroo output
2066 * @connector: connector we're probing
2067 * @adapter: I2C adapter to use for DDC
2068 *
2069 * Wrapper around drm_get_edid() for laptops with dual GPUs using one set of
2070 * outputs. The wrapper adds the requisite vga_switcheroo calls to temporarily
2071 * switch DDC to the GPU which is retrieving EDID.
2072 *
2073 * Return: Pointer to valid EDID or %NULL if we couldn't find any.
2074 */
2075struct edid *drm_get_edid_switcheroo(struct drm_connector *connector,
2076 struct i2c_adapter *adapter)
2077{
2078 struct pci_dev *pdev = connector->dev->pdev;
2079 struct edid *edid;
2080
2081 vga_switcheroo_lock_ddc(pdev);
2082 edid = drm_get_edid(connector, adapter);
2083 vga_switcheroo_unlock_ddc(pdev);
2084
2085 return edid;
2086}
2087EXPORT_SYMBOL(drm_get_edid_switcheroo);
2088
2089/**
2090 * drm_edid_duplicate - duplicate an EDID and the extensions
2091 * @edid: EDID to duplicate
2092 *
2093 * Return: Pointer to duplicated EDID or NULL on allocation failure.
2094 */
2095struct edid *drm_edid_duplicate(const struct edid *edid)
2096{
2097 return kmemdup(edid, (edid->extensions + 1) * EDID_LENGTH, GFP_KERNEL);
2098}
2099EXPORT_SYMBOL(drm_edid_duplicate);
2100
2101/*** EDID parsing ***/
2102
2103/**
2104 * edid_vendor - match a string against EDID's obfuscated vendor field
2105 * @edid: EDID to match
2106 * @vendor: vendor string
2107 *
2108 * Returns true if @vendor is in @edid, false otherwise
2109 */
2110static bool edid_vendor(const struct edid *edid, const char *vendor)
2111{
2112 char edid_vendor[3];
2113
2114 edid_vendor[0] = ((edid->mfg_id[0] & 0x7c) >> 2) + '@';
2115 edid_vendor[1] = (((edid->mfg_id[0] & 0x3) << 3) |
2116 ((edid->mfg_id[1] & 0xe0) >> 5)) + '@';
2117 edid_vendor[2] = (edid->mfg_id[1] & 0x1f) + '@';
2118
2119 return !strncmp(edid_vendor, vendor, 3);
2120}
2121
2122/**
2123 * edid_get_quirks - return quirk flags for a given EDID
2124 * @edid: EDID to process
2125 *
2126 * This tells subsequent routines what fixes they need to apply.
2127 */
2128static u32 edid_get_quirks(const struct edid *edid)
2129{
2130 const struct edid_quirk *quirk;
2131 int i;
2132
2133 for (i = 0; i < ARRAY_SIZE(edid_quirk_list); i++) {
2134 quirk = &edid_quirk_list[i];
2135
2136 if (edid_vendor(edid, quirk->vendor) &&
2137 (EDID_PRODUCT_ID(edid) == quirk->product_id))
2138 return quirk->quirks;
2139 }
2140
2141 return 0;
2142}
2143
2144#define MODE_SIZE(m) ((m)->hdisplay * (m)->vdisplay)
2145#define MODE_REFRESH_DIFF(c,t) (abs((c) - (t)))
2146
2147/**
2148 * edid_fixup_preferred - set preferred modes based on quirk list
2149 * @connector: has mode list to fix up
2150 * @quirks: quirks list
2151 *
2152 * Walk the mode list for @connector, clearing the preferred status
2153 * on existing modes and setting it anew for the right mode ala @quirks.
2154 */
2155static void edid_fixup_preferred(struct drm_connector *connector,
2156 u32 quirks)
2157{
2158 struct drm_display_mode *t, *cur_mode, *preferred_mode;
2159 int target_refresh = 0;
2160 int cur_vrefresh, preferred_vrefresh;
2161
2162 if (list_empty(&connector->probed_modes))
2163 return;
2164
2165 if (quirks & EDID_QUIRK_PREFER_LARGE_60)
2166 target_refresh = 60;
2167 if (quirks & EDID_QUIRK_PREFER_LARGE_75)
2168 target_refresh = 75;
2169
2170 preferred_mode = list_first_entry(&connector->probed_modes,
2171 struct drm_display_mode, head);
2172
2173 list_for_each_entry_safe(cur_mode, t, &connector->probed_modes, head) {
2174 cur_mode->type &= ~DRM_MODE_TYPE_PREFERRED;
2175
2176 if (cur_mode == preferred_mode)
2177 continue;
2178
2179 /* Largest mode is preferred */
2180 if (MODE_SIZE(cur_mode) > MODE_SIZE(preferred_mode))
2181 preferred_mode = cur_mode;
2182
2183 cur_vrefresh = drm_mode_vrefresh(cur_mode);
2184 preferred_vrefresh = drm_mode_vrefresh(preferred_mode);
2185 /* At a given size, try to get closest to target refresh */
2186 if ((MODE_SIZE(cur_mode) == MODE_SIZE(preferred_mode)) &&
2187 MODE_REFRESH_DIFF(cur_vrefresh, target_refresh) <
2188 MODE_REFRESH_DIFF(preferred_vrefresh, target_refresh)) {
2189 preferred_mode = cur_mode;
2190 }
2191 }
2192
2193 preferred_mode->type |= DRM_MODE_TYPE_PREFERRED;
2194}
2195
2196static bool
2197mode_is_rb(const struct drm_display_mode *mode)
2198{
2199 return (mode->htotal - mode->hdisplay == 160) &&
2200 (mode->hsync_end - mode->hdisplay == 80) &&
2201 (mode->hsync_end - mode->hsync_start == 32) &&
2202 (mode->vsync_start - mode->vdisplay == 3);
2203}
2204
2205/*
2206 * drm_mode_find_dmt - Create a copy of a mode if present in DMT
2207 * @dev: Device to duplicate against
2208 * @hsize: Mode width
2209 * @vsize: Mode height
2210 * @fresh: Mode refresh rate
2211 * @rb: Mode reduced-blanking-ness
2212 *
2213 * Walk the DMT mode list looking for a match for the given parameters.
2214 *
2215 * Return: A newly allocated copy of the mode, or NULL if not found.
2216 */
2217struct drm_display_mode *drm_mode_find_dmt(struct drm_device *dev,
2218 int hsize, int vsize, int fresh,
2219 bool rb)
2220{
2221 int i;
2222
2223 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) {
2224 const struct drm_display_mode *ptr = &drm_dmt_modes[i];
2225
2226 if (hsize != ptr->hdisplay)
2227 continue;
2228 if (vsize != ptr->vdisplay)
2229 continue;
2230 if (fresh != drm_mode_vrefresh(ptr))
2231 continue;
2232 if (rb != mode_is_rb(ptr))
2233 continue;
2234
2235 return drm_mode_duplicate(dev, ptr);
2236 }
2237
2238 return NULL;
2239}
2240EXPORT_SYMBOL(drm_mode_find_dmt);
2241
2242static bool is_display_descriptor(const u8 d[18], u8 tag)
2243{
2244 return d[0] == 0x00 && d[1] == 0x00 &&
2245 d[2] == 0x00 && d[3] == tag;
2246}
2247
2248static bool is_detailed_timing_descriptor(const u8 d[18])
2249{
2250 return d[0] != 0x00 || d[1] != 0x00;
2251}
2252
2253typedef void detailed_cb(struct detailed_timing *timing, void *closure);
2254
2255static void
2256cea_for_each_detailed_block(u8 *ext, detailed_cb *cb, void *closure)
2257{
2258 int i, n;
2259 u8 d = ext[0x02];
2260 u8 *det_base = ext + d;
2261
2262 if (d < 4 || d > 127)
2263 return;
2264
2265 n = (127 - d) / 18;
2266 for (i = 0; i < n; i++)
2267 cb((struct detailed_timing *)(det_base + 18 * i), closure);
2268}
2269
2270static void
2271vtb_for_each_detailed_block(u8 *ext, detailed_cb *cb, void *closure)
2272{
2273 unsigned int i, n = min((int)ext[0x02], 6);
2274 u8 *det_base = ext + 5;
2275
2276 if (ext[0x01] != 1)
2277 return; /* unknown version */
2278
2279 for (i = 0; i < n; i++)
2280 cb((struct detailed_timing *)(det_base + 18 * i), closure);
2281}
2282
2283static void
2284drm_for_each_detailed_block(u8 *raw_edid, detailed_cb *cb, void *closure)
2285{
2286 int i;
2287 struct edid *edid = (struct edid *)raw_edid;
2288
2289 if (edid == NULL)
2290 return;
2291
2292 for (i = 0; i < EDID_DETAILED_TIMINGS; i++)
2293 cb(&(edid->detailed_timings[i]), closure);
2294
2295 for (i = 1; i <= raw_edid[0x7e]; i++) {
2296 u8 *ext = raw_edid + (i * EDID_LENGTH);
2297
2298 switch (*ext) {
2299 case CEA_EXT:
2300 cea_for_each_detailed_block(ext, cb, closure);
2301 break;
2302 case VTB_EXT:
2303 vtb_for_each_detailed_block(ext, cb, closure);
2304 break;
2305 default:
2306 break;
2307 }
2308 }
2309}
2310
2311static void
2312is_rb(struct detailed_timing *t, void *data)
2313{
2314 u8 *r = (u8 *)t;
2315
2316 if (!is_display_descriptor(r, EDID_DETAIL_MONITOR_RANGE))
2317 return;
2318
2319 if (r[15] & 0x10)
2320 *(bool *)data = true;
2321}
2322
2323/* EDID 1.4 defines this explicitly. For EDID 1.3, we guess, badly. */
2324static bool
2325drm_monitor_supports_rb(struct edid *edid)
2326{
2327 if (edid->revision >= 4) {
2328 bool ret = false;
2329
2330 drm_for_each_detailed_block((u8 *)edid, is_rb, &ret);
2331 return ret;
2332 }
2333
2334 return ((edid->input & DRM_EDID_INPUT_DIGITAL) != 0);
2335}
2336
2337static void
2338find_gtf2(struct detailed_timing *t, void *data)
2339{
2340 u8 *r = (u8 *)t;
2341
2342 if (!is_display_descriptor(r, EDID_DETAIL_MONITOR_RANGE))
2343 return;
2344
2345 if (r[10] == 0x02)
2346 *(u8 **)data = r;
2347}
2348
2349/* Secondary GTF curve kicks in above some break frequency */
2350static int
2351drm_gtf2_hbreak(struct edid *edid)
2352{
2353 u8 *r = NULL;
2354
2355 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
2356 return r ? (r[12] * 2) : 0;
2357}
2358
2359static int
2360drm_gtf2_2c(struct edid *edid)
2361{
2362 u8 *r = NULL;
2363
2364 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
2365 return r ? r[13] : 0;
2366}
2367
2368static int
2369drm_gtf2_m(struct edid *edid)
2370{
2371 u8 *r = NULL;
2372
2373 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
2374 return r ? (r[15] << 8) + r[14] : 0;
2375}
2376
2377static int
2378drm_gtf2_k(struct edid *edid)
2379{
2380 u8 *r = NULL;
2381
2382 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
2383 return r ? r[16] : 0;
2384}
2385
2386static int
2387drm_gtf2_2j(struct edid *edid)
2388{
2389 u8 *r = NULL;
2390
2391 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
2392 return r ? r[17] : 0;
2393}
2394
2395/**
2396 * standard_timing_level - get std. timing level(CVT/GTF/DMT)
2397 * @edid: EDID block to scan
2398 */
2399static int standard_timing_level(struct edid *edid)
2400{
2401 if (edid->revision >= 2) {
2402 if (edid->revision >= 4 && (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF))
2403 return LEVEL_CVT;
2404 if (drm_gtf2_hbreak(edid))
2405 return LEVEL_GTF2;
2406 if (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF)
2407 return LEVEL_GTF;
2408 }
2409 return LEVEL_DMT;
2410}
2411
2412/*
2413 * 0 is reserved. The spec says 0x01 fill for unused timings. Some old
2414 * monitors fill with ascii space (0x20) instead.
2415 */
2416static int
2417bad_std_timing(u8 a, u8 b)
2418{
2419 return (a == 0x00 && b == 0x00) ||
2420 (a == 0x01 && b == 0x01) ||
2421 (a == 0x20 && b == 0x20);
2422}
2423
2424static int drm_mode_hsync(const struct drm_display_mode *mode)
2425{
2426 if (mode->htotal <= 0)
2427 return 0;
2428
2429 return DIV_ROUND_CLOSEST(mode->clock, mode->htotal);
2430}
2431
2432/**
2433 * drm_mode_std - convert standard mode info (width, height, refresh) into mode
2434 * @connector: connector of for the EDID block
2435 * @edid: EDID block to scan
2436 * @t: standard timing params
2437 *
2438 * Take the standard timing params (in this case width, aspect, and refresh)
2439 * and convert them into a real mode using CVT/GTF/DMT.
2440 */
2441static struct drm_display_mode *
2442drm_mode_std(struct drm_connector *connector, struct edid *edid,
2443 struct std_timing *t)
2444{
2445 struct drm_device *dev = connector->dev;
2446 struct drm_display_mode *m, *mode = NULL;
2447 int hsize, vsize;
2448 int vrefresh_rate;
2449 unsigned aspect_ratio = (t->vfreq_aspect & EDID_TIMING_ASPECT_MASK)
2450 >> EDID_TIMING_ASPECT_SHIFT;
2451 unsigned vfreq = (t->vfreq_aspect & EDID_TIMING_VFREQ_MASK)
2452 >> EDID_TIMING_VFREQ_SHIFT;
2453 int timing_level = standard_timing_level(edid);
2454
2455 if (bad_std_timing(t->hsize, t->vfreq_aspect))
2456 return NULL;
2457
2458 /* According to the EDID spec, the hdisplay = hsize * 8 + 248 */
2459 hsize = t->hsize * 8 + 248;
2460 /* vrefresh_rate = vfreq + 60 */
2461 vrefresh_rate = vfreq + 60;
2462 /* the vdisplay is calculated based on the aspect ratio */
2463 if (aspect_ratio == 0) {
2464 if (edid->revision < 3)
2465 vsize = hsize;
2466 else
2467 vsize = (hsize * 10) / 16;
2468 } else if (aspect_ratio == 1)
2469 vsize = (hsize * 3) / 4;
2470 else if (aspect_ratio == 2)
2471 vsize = (hsize * 4) / 5;
2472 else
2473 vsize = (hsize * 9) / 16;
2474
2475 /* HDTV hack, part 1 */
2476 if (vrefresh_rate == 60 &&
2477 ((hsize == 1360 && vsize == 765) ||
2478 (hsize == 1368 && vsize == 769))) {
2479 hsize = 1366;
2480 vsize = 768;
2481 }
2482
2483 /*
2484 * If this connector already has a mode for this size and refresh
2485 * rate (because it came from detailed or CVT info), use that
2486 * instead. This way we don't have to guess at interlace or
2487 * reduced blanking.
2488 */
2489 list_for_each_entry(m, &connector->probed_modes, head)
2490 if (m->hdisplay == hsize && m->vdisplay == vsize &&
2491 drm_mode_vrefresh(m) == vrefresh_rate)
2492 return NULL;
2493
2494 /* HDTV hack, part 2 */
2495 if (hsize == 1366 && vsize == 768 && vrefresh_rate == 60) {
2496 mode = drm_cvt_mode(dev, 1366, 768, vrefresh_rate, 0, 0,
2497 false);
2498 if (!mode)
2499 return NULL;
2500 mode->hdisplay = 1366;
2501 mode->hsync_start = mode->hsync_start - 1;
2502 mode->hsync_end = mode->hsync_end - 1;
2503 return mode;
2504 }
2505
2506 /* check whether it can be found in default mode table */
2507 if (drm_monitor_supports_rb(edid)) {
2508 mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate,
2509 true);
2510 if (mode)
2511 return mode;
2512 }
2513 mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate, false);
2514 if (mode)
2515 return mode;
2516
2517 /* okay, generate it */
2518 switch (timing_level) {
2519 case LEVEL_DMT:
2520 break;
2521 case LEVEL_GTF:
2522 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0);
2523 break;
2524 case LEVEL_GTF2:
2525 /*
2526 * This is potentially wrong if there's ever a monitor with
2527 * more than one ranges section, each claiming a different
2528 * secondary GTF curve. Please don't do that.
2529 */
2530 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0);
2531 if (!mode)
2532 return NULL;
2533 if (drm_mode_hsync(mode) > drm_gtf2_hbreak(edid)) {
2534 drm_mode_destroy(dev, mode);
2535 mode = drm_gtf_mode_complex(dev, hsize, vsize,
2536 vrefresh_rate, 0, 0,
2537 drm_gtf2_m(edid),
2538 drm_gtf2_2c(edid),
2539 drm_gtf2_k(edid),
2540 drm_gtf2_2j(edid));
2541 }
2542 break;
2543 case LEVEL_CVT:
2544 mode = drm_cvt_mode(dev, hsize, vsize, vrefresh_rate, 0, 0,
2545 false);
2546 break;
2547 }
2548 return mode;
2549}
2550
2551/*
2552 * EDID is delightfully ambiguous about how interlaced modes are to be
2553 * encoded. Our internal representation is of frame height, but some
2554 * HDTV detailed timings are encoded as field height.
2555 *
2556 * The format list here is from CEA, in frame size. Technically we
2557 * should be checking refresh rate too. Whatever.
2558 */
2559static void
2560drm_mode_do_interlace_quirk(struct drm_display_mode *mode,
2561 struct detailed_pixel_timing *pt)
2562{
2563 int i;
2564 static const struct {
2565 int w, h;
2566 } cea_interlaced[] = {
2567 { 1920, 1080 },
2568 { 720, 480 },
2569 { 1440, 480 },
2570 { 2880, 480 },
2571 { 720, 576 },
2572 { 1440, 576 },
2573 { 2880, 576 },
2574 };
2575
2576 if (!(pt->misc & DRM_EDID_PT_INTERLACED))
2577 return;
2578
2579 for (i = 0; i < ARRAY_SIZE(cea_interlaced); i++) {
2580 if ((mode->hdisplay == cea_interlaced[i].w) &&
2581 (mode->vdisplay == cea_interlaced[i].h / 2)) {
2582 mode->vdisplay *= 2;
2583 mode->vsync_start *= 2;
2584 mode->vsync_end *= 2;
2585 mode->vtotal *= 2;
2586 mode->vtotal |= 1;
2587 }
2588 }
2589
2590 mode->flags |= DRM_MODE_FLAG_INTERLACE;
2591}
2592
2593/**
2594 * drm_mode_detailed - create a new mode from an EDID detailed timing section
2595 * @dev: DRM device (needed to create new mode)
2596 * @edid: EDID block
2597 * @timing: EDID detailed timing info
2598 * @quirks: quirks to apply
2599 *
2600 * An EDID detailed timing block contains enough info for us to create and
2601 * return a new struct drm_display_mode.
2602 */
2603static struct drm_display_mode *drm_mode_detailed(struct drm_device *dev,
2604 struct edid *edid,
2605 struct detailed_timing *timing,
2606 u32 quirks)
2607{
2608 struct drm_display_mode *mode;
2609 struct detailed_pixel_timing *pt = &timing->data.pixel_data;
2610 unsigned hactive = (pt->hactive_hblank_hi & 0xf0) << 4 | pt->hactive_lo;
2611 unsigned vactive = (pt->vactive_vblank_hi & 0xf0) << 4 | pt->vactive_lo;
2612 unsigned hblank = (pt->hactive_hblank_hi & 0xf) << 8 | pt->hblank_lo;
2613 unsigned vblank = (pt->vactive_vblank_hi & 0xf) << 8 | pt->vblank_lo;
2614 unsigned hsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc0) << 2 | pt->hsync_offset_lo;
2615 unsigned hsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x30) << 4 | pt->hsync_pulse_width_lo;
2616 unsigned vsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc) << 2 | pt->vsync_offset_pulse_width_lo >> 4;
2617 unsigned vsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x3) << 4 | (pt->vsync_offset_pulse_width_lo & 0xf);
2618
2619 /* ignore tiny modes */
2620 if (hactive < 64 || vactive < 64)
2621 return NULL;
2622
2623 if (pt->misc & DRM_EDID_PT_STEREO) {
2624 DRM_DEBUG_KMS("stereo mode not supported\n");
2625 return NULL;
2626 }
2627 if (!(pt->misc & DRM_EDID_PT_SEPARATE_SYNC)) {
2628 DRM_DEBUG_KMS("composite sync not supported\n");
2629 }
2630
2631 /* it is incorrect if hsync/vsync width is zero */
2632 if (!hsync_pulse_width || !vsync_pulse_width) {
2633 DRM_DEBUG_KMS("Incorrect Detailed timing. "
2634 "Wrong Hsync/Vsync pulse width\n");
2635 return NULL;
2636 }
2637
2638 if (quirks & EDID_QUIRK_FORCE_REDUCED_BLANKING) {
2639 mode = drm_cvt_mode(dev, hactive, vactive, 60, true, false, false);
2640 if (!mode)
2641 return NULL;
2642
2643 goto set_size;
2644 }
2645
2646 mode = drm_mode_create(dev);
2647 if (!mode)
2648 return NULL;
2649
2650 if (quirks & EDID_QUIRK_135_CLOCK_TOO_HIGH)
2651 timing->pixel_clock = cpu_to_le16(1088);
2652
2653 mode->clock = le16_to_cpu(timing->pixel_clock) * 10;
2654
2655 mode->hdisplay = hactive;
2656 mode->hsync_start = mode->hdisplay + hsync_offset;
2657 mode->hsync_end = mode->hsync_start + hsync_pulse_width;
2658 mode->htotal = mode->hdisplay + hblank;
2659
2660 mode->vdisplay = vactive;
2661 mode->vsync_start = mode->vdisplay + vsync_offset;
2662 mode->vsync_end = mode->vsync_start + vsync_pulse_width;
2663 mode->vtotal = mode->vdisplay + vblank;
2664
2665 /* Some EDIDs have bogus h/vtotal values */
2666 if (mode->hsync_end > mode->htotal)
2667 mode->htotal = mode->hsync_end + 1;
2668 if (mode->vsync_end > mode->vtotal)
2669 mode->vtotal = mode->vsync_end + 1;
2670
2671 drm_mode_do_interlace_quirk(mode, pt);
2672
2673 if (quirks & EDID_QUIRK_DETAILED_SYNC_PP) {
2674 pt->misc |= DRM_EDID_PT_HSYNC_POSITIVE | DRM_EDID_PT_VSYNC_POSITIVE;
2675 }
2676
2677 mode->flags |= (pt->misc & DRM_EDID_PT_HSYNC_POSITIVE) ?
2678 DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC;
2679 mode->flags |= (pt->misc & DRM_EDID_PT_VSYNC_POSITIVE) ?
2680 DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC;
2681
2682set_size:
2683 mode->width_mm = pt->width_mm_lo | (pt->width_height_mm_hi & 0xf0) << 4;
2684 mode->height_mm = pt->height_mm_lo | (pt->width_height_mm_hi & 0xf) << 8;
2685
2686 if (quirks & EDID_QUIRK_DETAILED_IN_CM) {
2687 mode->width_mm *= 10;
2688 mode->height_mm *= 10;
2689 }
2690
2691 if (quirks & EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE) {
2692 mode->width_mm = edid->width_cm * 10;
2693 mode->height_mm = edid->height_cm * 10;
2694 }
2695
2696 mode->type = DRM_MODE_TYPE_DRIVER;
2697 drm_mode_set_name(mode);
2698
2699 return mode;
2700}
2701
2702static bool
2703mode_in_hsync_range(const struct drm_display_mode *mode,
2704 struct edid *edid, u8 *t)
2705{
2706 int hsync, hmin, hmax;
2707
2708 hmin = t[7];
2709 if (edid->revision >= 4)
2710 hmin += ((t[4] & 0x04) ? 255 : 0);
2711 hmax = t[8];
2712 if (edid->revision >= 4)
2713 hmax += ((t[4] & 0x08) ? 255 : 0);
2714 hsync = drm_mode_hsync(mode);
2715
2716 return (hsync <= hmax && hsync >= hmin);
2717}
2718
2719static bool
2720mode_in_vsync_range(const struct drm_display_mode *mode,
2721 struct edid *edid, u8 *t)
2722{
2723 int vsync, vmin, vmax;
2724
2725 vmin = t[5];
2726 if (edid->revision >= 4)
2727 vmin += ((t[4] & 0x01) ? 255 : 0);
2728 vmax = t[6];
2729 if (edid->revision >= 4)
2730 vmax += ((t[4] & 0x02) ? 255 : 0);
2731 vsync = drm_mode_vrefresh(mode);
2732
2733 return (vsync <= vmax && vsync >= vmin);
2734}
2735
2736static u32
2737range_pixel_clock(struct edid *edid, u8 *t)
2738{
2739 /* unspecified */
2740 if (t[9] == 0 || t[9] == 255)
2741 return 0;
2742
2743 /* 1.4 with CVT support gives us real precision, yay */
2744 if (edid->revision >= 4 && t[10] == 0x04)
2745 return (t[9] * 10000) - ((t[12] >> 2) * 250);
2746
2747 /* 1.3 is pathetic, so fuzz up a bit */
2748 return t[9] * 10000 + 5001;
2749}
2750
2751static bool
2752mode_in_range(const struct drm_display_mode *mode, struct edid *edid,
2753 struct detailed_timing *timing)
2754{
2755 u32 max_clock;
2756 u8 *t = (u8 *)timing;
2757
2758 if (!mode_in_hsync_range(mode, edid, t))
2759 return false;
2760
2761 if (!mode_in_vsync_range(mode, edid, t))
2762 return false;
2763
2764 if ((max_clock = range_pixel_clock(edid, t)))
2765 if (mode->clock > max_clock)
2766 return false;
2767
2768 /* 1.4 max horizontal check */
2769 if (edid->revision >= 4 && t[10] == 0x04)
2770 if (t[13] && mode->hdisplay > 8 * (t[13] + (256 * (t[12]&0x3))))
2771 return false;
2772
2773 if (mode_is_rb(mode) && !drm_monitor_supports_rb(edid))
2774 return false;
2775
2776 return true;
2777}
2778
2779static bool valid_inferred_mode(const struct drm_connector *connector,
2780 const struct drm_display_mode *mode)
2781{
2782 const struct drm_display_mode *m;
2783 bool ok = false;
2784
2785 list_for_each_entry(m, &connector->probed_modes, head) {
2786 if (mode->hdisplay == m->hdisplay &&
2787 mode->vdisplay == m->vdisplay &&
2788 drm_mode_vrefresh(mode) == drm_mode_vrefresh(m))
2789 return false; /* duplicated */
2790 if (mode->hdisplay <= m->hdisplay &&
2791 mode->vdisplay <= m->vdisplay)
2792 ok = true;
2793 }
2794 return ok;
2795}
2796
2797static int
2798drm_dmt_modes_for_range(struct drm_connector *connector, struct edid *edid,
2799 struct detailed_timing *timing)
2800{
2801 int i, modes = 0;
2802 struct drm_display_mode *newmode;
2803 struct drm_device *dev = connector->dev;
2804
2805 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) {
2806 if (mode_in_range(drm_dmt_modes + i, edid, timing) &&
2807 valid_inferred_mode(connector, drm_dmt_modes + i)) {
2808 newmode = drm_mode_duplicate(dev, &drm_dmt_modes[i]);
2809 if (newmode) {
2810 drm_mode_probed_add(connector, newmode);
2811 modes++;
2812 }
2813 }
2814 }
2815
2816 return modes;
2817}
2818
2819/* fix up 1366x768 mode from 1368x768;
2820 * GFT/CVT can't express 1366 width which isn't dividable by 8
2821 */
2822void drm_mode_fixup_1366x768(struct drm_display_mode *mode)
2823{
2824 if (mode->hdisplay == 1368 && mode->vdisplay == 768) {
2825 mode->hdisplay = 1366;
2826 mode->hsync_start--;
2827 mode->hsync_end--;
2828 drm_mode_set_name(mode);
2829 }
2830}
2831
2832static int
2833drm_gtf_modes_for_range(struct drm_connector *connector, struct edid *edid,
2834 struct detailed_timing *timing)
2835{
2836 int i, modes = 0;
2837 struct drm_display_mode *newmode;
2838 struct drm_device *dev = connector->dev;
2839
2840 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) {
2841 const struct minimode *m = &extra_modes[i];
2842
2843 newmode = drm_gtf_mode(dev, m->w, m->h, m->r, 0, 0);
2844 if (!newmode)
2845 return modes;
2846
2847 drm_mode_fixup_1366x768(newmode);
2848 if (!mode_in_range(newmode, edid, timing) ||
2849 !valid_inferred_mode(connector, newmode)) {
2850 drm_mode_destroy(dev, newmode);
2851 continue;
2852 }
2853
2854 drm_mode_probed_add(connector, newmode);
2855 modes++;
2856 }
2857
2858 return modes;
2859}
2860
2861static int
2862drm_cvt_modes_for_range(struct drm_connector *connector, struct edid *edid,
2863 struct detailed_timing *timing)
2864{
2865 int i, modes = 0;
2866 struct drm_display_mode *newmode;
2867 struct drm_device *dev = connector->dev;
2868 bool rb = drm_monitor_supports_rb(edid);
2869
2870 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) {
2871 const struct minimode *m = &extra_modes[i];
2872
2873 newmode = drm_cvt_mode(dev, m->w, m->h, m->r, rb, 0, 0);
2874 if (!newmode)
2875 return modes;
2876
2877 drm_mode_fixup_1366x768(newmode);
2878 if (!mode_in_range(newmode, edid, timing) ||
2879 !valid_inferred_mode(connector, newmode)) {
2880 drm_mode_destroy(dev, newmode);
2881 continue;
2882 }
2883
2884 drm_mode_probed_add(connector, newmode);
2885 modes++;
2886 }
2887
2888 return modes;
2889}
2890
2891static void
2892do_inferred_modes(struct detailed_timing *timing, void *c)
2893{
2894 struct detailed_mode_closure *closure = c;
2895 struct detailed_non_pixel *data = &timing->data.other_data;
2896 struct detailed_data_monitor_range *range = &data->data.range;
2897
2898 if (!is_display_descriptor((const u8 *)timing, EDID_DETAIL_MONITOR_RANGE))
2899 return;
2900
2901 closure->modes += drm_dmt_modes_for_range(closure->connector,
2902 closure->edid,
2903 timing);
2904
2905 if (!version_greater(closure->edid, 1, 1))
2906 return; /* GTF not defined yet */
2907
2908 switch (range->flags) {
2909 case 0x02: /* secondary gtf, XXX could do more */
2910 case 0x00: /* default gtf */
2911 closure->modes += drm_gtf_modes_for_range(closure->connector,
2912 closure->edid,
2913 timing);
2914 break;
2915 case 0x04: /* cvt, only in 1.4+ */
2916 if (!version_greater(closure->edid, 1, 3))
2917 break;
2918
2919 closure->modes += drm_cvt_modes_for_range(closure->connector,
2920 closure->edid,
2921 timing);
2922 break;
2923 case 0x01: /* just the ranges, no formula */
2924 default:
2925 break;
2926 }
2927}
2928
2929static int
2930add_inferred_modes(struct drm_connector *connector, struct edid *edid)
2931{
2932 struct detailed_mode_closure closure = {
2933 .connector = connector,
2934 .edid = edid,
2935 };
2936
2937 if (version_greater(edid, 1, 0))
2938 drm_for_each_detailed_block((u8 *)edid, do_inferred_modes,
2939 &closure);
2940
2941 return closure.modes;
2942}
2943
2944static int
2945drm_est3_modes(struct drm_connector *connector, struct detailed_timing *timing)
2946{
2947 int i, j, m, modes = 0;
2948 struct drm_display_mode *mode;
2949 u8 *est = ((u8 *)timing) + 6;
2950
2951 for (i = 0; i < 6; i++) {
2952 for (j = 7; j >= 0; j--) {
2953 m = (i * 8) + (7 - j);
2954 if (m >= ARRAY_SIZE(est3_modes))
2955 break;
2956 if (est[i] & (1 << j)) {
2957 mode = drm_mode_find_dmt(connector->dev,
2958 est3_modes[m].w,
2959 est3_modes[m].h,
2960 est3_modes[m].r,
2961 est3_modes[m].rb);
2962 if (mode) {
2963 drm_mode_probed_add(connector, mode);
2964 modes++;
2965 }
2966 }
2967 }
2968 }
2969
2970 return modes;
2971}
2972
2973static void
2974do_established_modes(struct detailed_timing *timing, void *c)
2975{
2976 struct detailed_mode_closure *closure = c;
2977
2978 if (!is_display_descriptor((const u8 *)timing, EDID_DETAIL_EST_TIMINGS))
2979 return;
2980
2981 closure->modes += drm_est3_modes(closure->connector, timing);
2982}
2983
2984/**
2985 * add_established_modes - get est. modes from EDID and add them
2986 * @connector: connector to add mode(s) to
2987 * @edid: EDID block to scan
2988 *
2989 * Each EDID block contains a bitmap of the supported "established modes" list
2990 * (defined above). Tease them out and add them to the global modes list.
2991 */
2992static int
2993add_established_modes(struct drm_connector *connector, struct edid *edid)
2994{
2995 struct drm_device *dev = connector->dev;
2996 unsigned long est_bits = edid->established_timings.t1 |
2997 (edid->established_timings.t2 << 8) |
2998 ((edid->established_timings.mfg_rsvd & 0x80) << 9);
2999 int i, modes = 0;
3000 struct detailed_mode_closure closure = {
3001 .connector = connector,
3002 .edid = edid,
3003 };
3004
3005 for (i = 0; i <= EDID_EST_TIMINGS; i++) {
3006 if (est_bits & (1<<i)) {
3007 struct drm_display_mode *newmode;
3008
3009 newmode = drm_mode_duplicate(dev, &edid_est_modes[i]);
3010 if (newmode) {
3011 drm_mode_probed_add(connector, newmode);
3012 modes++;
3013 }
3014 }
3015 }
3016
3017 if (version_greater(edid, 1, 0))
3018 drm_for_each_detailed_block((u8 *)edid,
3019 do_established_modes, &closure);
3020
3021 return modes + closure.modes;
3022}
3023
3024static void
3025do_standard_modes(struct detailed_timing *timing, void *c)
3026{
3027 struct detailed_mode_closure *closure = c;
3028 struct detailed_non_pixel *data = &timing->data.other_data;
3029 struct drm_connector *connector = closure->connector;
3030 struct edid *edid = closure->edid;
3031 int i;
3032
3033 if (!is_display_descriptor((const u8 *)timing, EDID_DETAIL_STD_MODES))
3034 return;
3035
3036 for (i = 0; i < 6; i++) {
3037 struct std_timing *std = &data->data.timings[i];
3038 struct drm_display_mode *newmode;
3039
3040 newmode = drm_mode_std(connector, edid, std);
3041 if (newmode) {
3042 drm_mode_probed_add(connector, newmode);
3043 closure->modes++;
3044 }
3045 }
3046}
3047
3048/**
3049 * add_standard_modes - get std. modes from EDID and add them
3050 * @connector: connector to add mode(s) to
3051 * @edid: EDID block to scan
3052 *
3053 * Standard modes can be calculated using the appropriate standard (DMT,
3054 * GTF or CVT. Grab them from @edid and add them to the list.
3055 */
3056static int
3057add_standard_modes(struct drm_connector *connector, struct edid *edid)
3058{
3059 int i, modes = 0;
3060 struct detailed_mode_closure closure = {
3061 .connector = connector,
3062 .edid = edid,
3063 };
3064
3065 for (i = 0; i < EDID_STD_TIMINGS; i++) {
3066 struct drm_display_mode *newmode;
3067
3068 newmode = drm_mode_std(connector, edid,
3069 &edid->standard_timings[i]);
3070 if (newmode) {
3071 drm_mode_probed_add(connector, newmode);
3072 modes++;
3073 }
3074 }
3075
3076 if (version_greater(edid, 1, 0))
3077 drm_for_each_detailed_block((u8 *)edid, do_standard_modes,
3078 &closure);
3079
3080 /* XXX should also look for standard codes in VTB blocks */
3081
3082 return modes + closure.modes;
3083}
3084
3085static int drm_cvt_modes(struct drm_connector *connector,
3086 struct detailed_timing *timing)
3087{
3088 int i, j, modes = 0;
3089 struct drm_display_mode *newmode;
3090 struct drm_device *dev = connector->dev;
3091 struct cvt_timing *cvt;
3092 const int rates[] = { 60, 85, 75, 60, 50 };
3093 const u8 empty[3] = { 0, 0, 0 };
3094
3095 for (i = 0; i < 4; i++) {
3096 int width, height;
3097
3098 cvt = &(timing->data.other_data.data.cvt[i]);
3099
3100 if (!memcmp(cvt->code, empty, 3))
3101 continue;
3102
3103 height = (cvt->code[0] + ((cvt->code[1] & 0xf0) << 4) + 1) * 2;
3104 switch (cvt->code[1] & 0x0c) {
3105 case 0x00:
3106 width = height * 4 / 3;
3107 break;
3108 case 0x04:
3109 width = height * 16 / 9;
3110 break;
3111 case 0x08:
3112 width = height * 16 / 10;
3113 break;
3114 case 0x0c:
3115 width = height * 15 / 9;
3116 break;
3117 }
3118
3119 for (j = 1; j < 5; j++) {
3120 if (cvt->code[2] & (1 << j)) {
3121 newmode = drm_cvt_mode(dev, width, height,
3122 rates[j], j == 0,
3123 false, false);
3124 if (newmode) {
3125 drm_mode_probed_add(connector, newmode);
3126 modes++;
3127 }
3128 }
3129 }
3130 }
3131
3132 return modes;
3133}
3134
3135static void
3136do_cvt_mode(struct detailed_timing *timing, void *c)
3137{
3138 struct detailed_mode_closure *closure = c;
3139
3140 if (!is_display_descriptor((const u8 *)timing, EDID_DETAIL_CVT_3BYTE))
3141 return;
3142
3143 closure->modes += drm_cvt_modes(closure->connector, timing);
3144}
3145
3146static int
3147add_cvt_modes(struct drm_connector *connector, struct edid *edid)
3148{
3149 struct detailed_mode_closure closure = {
3150 .connector = connector,
3151 .edid = edid,
3152 };
3153
3154 if (version_greater(edid, 1, 2))
3155 drm_for_each_detailed_block((u8 *)edid, do_cvt_mode, &closure);
3156
3157 /* XXX should also look for CVT codes in VTB blocks */
3158
3159 return closure.modes;
3160}
3161
3162static void fixup_detailed_cea_mode_clock(struct drm_display_mode *mode);
3163
3164static void
3165do_detailed_mode(struct detailed_timing *timing, void *c)
3166{
3167 struct detailed_mode_closure *closure = c;
3168 struct drm_display_mode *newmode;
3169
3170 if (!is_detailed_timing_descriptor((const u8 *)timing))
3171 return;
3172
3173 newmode = drm_mode_detailed(closure->connector->dev,
3174 closure->edid, timing,
3175 closure->quirks);
3176 if (!newmode)
3177 return;
3178
3179 if (closure->preferred)
3180 newmode->type |= DRM_MODE_TYPE_PREFERRED;
3181
3182 /*
3183 * Detailed modes are limited to 10kHz pixel clock resolution,
3184 * so fix up anything that looks like CEA/HDMI mode, but the clock
3185 * is just slightly off.
3186 */
3187 fixup_detailed_cea_mode_clock(newmode);
3188
3189 drm_mode_probed_add(closure->connector, newmode);
3190 closure->modes++;
3191 closure->preferred = false;
3192}
3193
3194/*
3195 * add_detailed_modes - Add modes from detailed timings
3196 * @connector: attached connector
3197 * @edid: EDID block to scan
3198 * @quirks: quirks to apply
3199 */
3200static int
3201add_detailed_modes(struct drm_connector *connector, struct edid *edid,
3202 u32 quirks)
3203{
3204 struct detailed_mode_closure closure = {
3205 .connector = connector,
3206 .edid = edid,
3207 .preferred = true,
3208 .quirks = quirks,
3209 };
3210
3211 if (closure.preferred && !version_greater(edid, 1, 3))
3212 closure.preferred =
3213 (edid->features & DRM_EDID_FEATURE_PREFERRED_TIMING);
3214
3215 drm_for_each_detailed_block((u8 *)edid, do_detailed_mode, &closure);
3216
3217 return closure.modes;
3218}
3219
3220#define AUDIO_BLOCK 0x01
3221#define VIDEO_BLOCK 0x02
3222#define VENDOR_BLOCK 0x03
3223#define SPEAKER_BLOCK 0x04
3224#define HDR_STATIC_METADATA_BLOCK 0x6
3225#define USE_EXTENDED_TAG 0x07
3226#define EXT_VIDEO_CAPABILITY_BLOCK 0x00
3227#define EXT_VIDEO_DATA_BLOCK_420 0x0E
3228#define EXT_VIDEO_CAP_BLOCK_Y420CMDB 0x0F
3229#define EDID_BASIC_AUDIO (1 << 6)
3230#define EDID_CEA_YCRCB444 (1 << 5)
3231#define EDID_CEA_YCRCB422 (1 << 4)
3232#define EDID_CEA_VCDB_QS (1 << 6)
3233
3234/*
3235 * Search EDID for CEA extension block.
3236 */
3237static u8 *drm_find_edid_extension(const struct edid *edid,
3238 int ext_id, int *ext_index)
3239{
3240 u8 *edid_ext = NULL;
3241 int i;
3242
3243 /* No EDID or EDID extensions */
3244 if (edid == NULL || edid->extensions == 0)
3245 return NULL;
3246
3247 /* Find CEA extension */
3248 for (i = *ext_index; i < edid->extensions; i++) {
3249 edid_ext = (u8 *)edid + EDID_LENGTH * (i + 1);
3250 if (edid_ext[0] == ext_id)
3251 break;
3252 }
3253
3254 if (i >= edid->extensions)
3255 return NULL;
3256
3257 *ext_index = i + 1;
3258
3259 return edid_ext;
3260}
3261
3262
3263static u8 *drm_find_displayid_extension(const struct edid *edid,
3264 int *length, int *idx,
3265 int *ext_index)
3266{
3267 u8 *displayid = drm_find_edid_extension(edid, DISPLAYID_EXT, ext_index);
3268 struct displayid_hdr *base;
3269 int ret;
3270
3271 if (!displayid)
3272 return NULL;
3273
3274 /* EDID extensions block checksum isn't for us */
3275 *length = EDID_LENGTH - 1;
3276 *idx = 1;
3277
3278 ret = validate_displayid(displayid, *length, *idx);
3279 if (ret)
3280 return NULL;
3281
3282 base = (struct displayid_hdr *)&displayid[*idx];
3283 *length = *idx + sizeof(*base) + base->bytes;
3284
3285 return displayid;
3286}
3287
3288static u8 *drm_find_cea_extension(const struct edid *edid)
3289{
3290 int length, idx;
3291 struct displayid_block *block;
3292 u8 *cea;
3293 u8 *displayid;
3294 int ext_index;
3295
3296 /* Look for a top level CEA extension block */
3297 /* FIXME: make callers iterate through multiple CEA ext blocks? */
3298 ext_index = 0;
3299 cea = drm_find_edid_extension(edid, CEA_EXT, &ext_index);
3300 if (cea)
3301 return cea;
3302
3303 /* CEA blocks can also be found embedded in a DisplayID block */
3304 ext_index = 0;
3305 for (;;) {
3306 displayid = drm_find_displayid_extension(edid, &length, &idx,
3307 &ext_index);
3308 if (!displayid)
3309 return NULL;
3310
3311 idx += sizeof(struct displayid_hdr);
3312 for_each_displayid_db(displayid, block, idx, length) {
3313 if (block->tag == DATA_BLOCK_CTA)
3314 return (u8 *)block;
3315 }
3316 }
3317
3318 return NULL;
3319}
3320
3321static __always_inline const struct drm_display_mode *cea_mode_for_vic(u8 vic)
3322{
3323 BUILD_BUG_ON(1 + ARRAY_SIZE(edid_cea_modes_1) - 1 != 127);
3324 BUILD_BUG_ON(193 + ARRAY_SIZE(edid_cea_modes_193) - 1 != 219);
3325
3326 if (vic >= 1 && vic < 1 + ARRAY_SIZE(edid_cea_modes_1))
3327 return &edid_cea_modes_1[vic - 1];
3328 if (vic >= 193 && vic < 193 + ARRAY_SIZE(edid_cea_modes_193))
3329 return &edid_cea_modes_193[vic - 193];
3330 return NULL;
3331}
3332
3333static u8 cea_num_vics(void)
3334{
3335 return 193 + ARRAY_SIZE(edid_cea_modes_193);
3336}
3337
3338static u8 cea_next_vic(u8 vic)
3339{
3340 if (++vic == 1 + ARRAY_SIZE(edid_cea_modes_1))
3341 vic = 193;
3342 return vic;
3343}
3344
3345/*
3346 * Calculate the alternate clock for the CEA mode
3347 * (60Hz vs. 59.94Hz etc.)
3348 */
3349static unsigned int
3350cea_mode_alternate_clock(const struct drm_display_mode *cea_mode)
3351{
3352 unsigned int clock = cea_mode->clock;
3353
3354 if (drm_mode_vrefresh(cea_mode) % 6 != 0)
3355 return clock;
3356
3357 /*
3358 * edid_cea_modes contains the 59.94Hz
3359 * variant for 240 and 480 line modes,
3360 * and the 60Hz variant otherwise.
3361 */
3362 if (cea_mode->vdisplay == 240 || cea_mode->vdisplay == 480)
3363 clock = DIV_ROUND_CLOSEST(clock * 1001, 1000);
3364 else
3365 clock = DIV_ROUND_CLOSEST(clock * 1000, 1001);
3366
3367 return clock;
3368}
3369
3370static bool
3371cea_mode_alternate_timings(u8 vic, struct drm_display_mode *mode)
3372{
3373 /*
3374 * For certain VICs the spec allows the vertical
3375 * front porch to vary by one or two lines.
3376 *
3377 * cea_modes[] stores the variant with the shortest
3378 * vertical front porch. We can adjust the mode to
3379 * get the other variants by simply increasing the
3380 * vertical front porch length.
3381 */
3382 BUILD_BUG_ON(cea_mode_for_vic(8)->vtotal != 262 ||
3383 cea_mode_for_vic(9)->vtotal != 262 ||
3384 cea_mode_for_vic(12)->vtotal != 262 ||
3385 cea_mode_for_vic(13)->vtotal != 262 ||
3386 cea_mode_for_vic(23)->vtotal != 312 ||
3387 cea_mode_for_vic(24)->vtotal != 312 ||
3388 cea_mode_for_vic(27)->vtotal != 312 ||
3389 cea_mode_for_vic(28)->vtotal != 312);
3390
3391 if (((vic == 8 || vic == 9 ||
3392 vic == 12 || vic == 13) && mode->vtotal < 263) ||
3393 ((vic == 23 || vic == 24 ||
3394 vic == 27 || vic == 28) && mode->vtotal < 314)) {
3395 mode->vsync_start++;
3396 mode->vsync_end++;
3397 mode->vtotal++;
3398
3399 return true;
3400 }
3401
3402 return false;
3403}
3404
3405static u8 drm_match_cea_mode_clock_tolerance(const struct drm_display_mode *to_match,
3406 unsigned int clock_tolerance)
3407{
3408 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS;
3409 u8 vic;
3410
3411 if (!to_match->clock)
3412 return 0;
3413
3414 if (to_match->picture_aspect_ratio)
3415 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO;
3416
3417 for (vic = 1; vic < cea_num_vics(); vic = cea_next_vic(vic)) {
3418 struct drm_display_mode cea_mode = *cea_mode_for_vic(vic);
3419 unsigned int clock1, clock2;
3420
3421 /* Check both 60Hz and 59.94Hz */
3422 clock1 = cea_mode.clock;
3423 clock2 = cea_mode_alternate_clock(&cea_mode);
3424
3425 if (abs(to_match->clock - clock1) > clock_tolerance &&
3426 abs(to_match->clock - clock2) > clock_tolerance)
3427 continue;
3428
3429 do {
3430 if (drm_mode_match(to_match, &cea_mode, match_flags))
3431 return vic;
3432 } while (cea_mode_alternate_timings(vic, &cea_mode));
3433 }
3434
3435 return 0;
3436}
3437
3438/**
3439 * drm_match_cea_mode - look for a CEA mode matching given mode
3440 * @to_match: display mode
3441 *
3442 * Return: The CEA Video ID (VIC) of the mode or 0 if it isn't a CEA-861
3443 * mode.
3444 */
3445u8 drm_match_cea_mode(const struct drm_display_mode *to_match)
3446{
3447 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS;
3448 u8 vic;
3449
3450 if (!to_match->clock)
3451 return 0;
3452
3453 if (to_match->picture_aspect_ratio)
3454 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO;
3455
3456 for (vic = 1; vic < cea_num_vics(); vic = cea_next_vic(vic)) {
3457 struct drm_display_mode cea_mode = *cea_mode_for_vic(vic);
3458 unsigned int clock1, clock2;
3459
3460 /* Check both 60Hz and 59.94Hz */
3461 clock1 = cea_mode.clock;
3462 clock2 = cea_mode_alternate_clock(&cea_mode);
3463
3464 if (KHZ2PICOS(to_match->clock) != KHZ2PICOS(clock1) &&
3465 KHZ2PICOS(to_match->clock) != KHZ2PICOS(clock2))
3466 continue;
3467
3468 do {
3469 if (drm_mode_match(to_match, &cea_mode, match_flags))
3470 return vic;
3471 } while (cea_mode_alternate_timings(vic, &cea_mode));
3472 }
3473
3474 return 0;
3475}
3476EXPORT_SYMBOL(drm_match_cea_mode);
3477
3478static bool drm_valid_cea_vic(u8 vic)
3479{
3480 return cea_mode_for_vic(vic) != NULL;
3481}
3482
3483static enum hdmi_picture_aspect drm_get_cea_aspect_ratio(const u8 video_code)
3484{
3485 const struct drm_display_mode *mode = cea_mode_for_vic(video_code);
3486
3487 if (mode)
3488 return mode->picture_aspect_ratio;
3489
3490 return HDMI_PICTURE_ASPECT_NONE;
3491}
3492
3493static enum hdmi_picture_aspect drm_get_hdmi_aspect_ratio(const u8 video_code)
3494{
3495 return edid_4k_modes[video_code].picture_aspect_ratio;
3496}
3497
3498/*
3499 * Calculate the alternate clock for HDMI modes (those from the HDMI vendor
3500 * specific block).
3501 */
3502static unsigned int
3503hdmi_mode_alternate_clock(const struct drm_display_mode *hdmi_mode)
3504{
3505 return cea_mode_alternate_clock(hdmi_mode);
3506}
3507
3508static u8 drm_match_hdmi_mode_clock_tolerance(const struct drm_display_mode *to_match,
3509 unsigned int clock_tolerance)
3510{
3511 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS;
3512 u8 vic;
3513
3514 if (!to_match->clock)
3515 return 0;
3516
3517 if (to_match->picture_aspect_ratio)
3518 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO;
3519
3520 for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) {
3521 const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic];
3522 unsigned int clock1, clock2;
3523
3524 /* Make sure to also match alternate clocks */
3525 clock1 = hdmi_mode->clock;
3526 clock2 = hdmi_mode_alternate_clock(hdmi_mode);
3527
3528 if (abs(to_match->clock - clock1) > clock_tolerance &&
3529 abs(to_match->clock - clock2) > clock_tolerance)
3530 continue;
3531
3532 if (drm_mode_match(to_match, hdmi_mode, match_flags))
3533 return vic;
3534 }
3535
3536 return 0;
3537}
3538
3539/*
3540 * drm_match_hdmi_mode - look for a HDMI mode matching given mode
3541 * @to_match: display mode
3542 *
3543 * An HDMI mode is one defined in the HDMI vendor specific block.
3544 *
3545 * Returns the HDMI Video ID (VIC) of the mode or 0 if it isn't one.
3546 */
3547static u8 drm_match_hdmi_mode(const struct drm_display_mode *to_match)
3548{
3549 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS;
3550 u8 vic;
3551
3552 if (!to_match->clock)
3553 return 0;
3554
3555 if (to_match->picture_aspect_ratio)
3556 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO;
3557
3558 for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) {
3559 const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic];
3560 unsigned int clock1, clock2;
3561
3562 /* Make sure to also match alternate clocks */
3563 clock1 = hdmi_mode->clock;
3564 clock2 = hdmi_mode_alternate_clock(hdmi_mode);
3565
3566 if ((KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock1) ||
3567 KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock2)) &&
3568 drm_mode_match(to_match, hdmi_mode, match_flags))
3569 return vic;
3570 }
3571 return 0;
3572}
3573
3574static bool drm_valid_hdmi_vic(u8 vic)
3575{
3576 return vic > 0 && vic < ARRAY_SIZE(edid_4k_modes);
3577}
3578
3579static int
3580add_alternate_cea_modes(struct drm_connector *connector, struct edid *edid)
3581{
3582 struct drm_device *dev = connector->dev;
3583 struct drm_display_mode *mode, *tmp;
3584 LIST_HEAD(list);
3585 int modes = 0;
3586
3587 /* Don't add CEA modes if the CEA extension block is missing */
3588 if (!drm_find_cea_extension(edid))
3589 return 0;
3590
3591 /*
3592 * Go through all probed modes and create a new mode
3593 * with the alternate clock for certain CEA modes.
3594 */
3595 list_for_each_entry(mode, &connector->probed_modes, head) {
3596 const struct drm_display_mode *cea_mode = NULL;
3597 struct drm_display_mode *newmode;
3598 u8 vic = drm_match_cea_mode(mode);
3599 unsigned int clock1, clock2;
3600
3601 if (drm_valid_cea_vic(vic)) {
3602 cea_mode = cea_mode_for_vic(vic);
3603 clock2 = cea_mode_alternate_clock(cea_mode);
3604 } else {
3605 vic = drm_match_hdmi_mode(mode);
3606 if (drm_valid_hdmi_vic(vic)) {
3607 cea_mode = &edid_4k_modes[vic];
3608 clock2 = hdmi_mode_alternate_clock(cea_mode);
3609 }
3610 }
3611
3612 if (!cea_mode)
3613 continue;
3614
3615 clock1 = cea_mode->clock;
3616
3617 if (clock1 == clock2)
3618 continue;
3619
3620 if (mode->clock != clock1 && mode->clock != clock2)
3621 continue;
3622
3623 newmode = drm_mode_duplicate(dev, cea_mode);
3624 if (!newmode)
3625 continue;
3626
3627 /* Carry over the stereo flags */
3628 newmode->flags |= mode->flags & DRM_MODE_FLAG_3D_MASK;
3629
3630 /*
3631 * The current mode could be either variant. Make
3632 * sure to pick the "other" clock for the new mode.
3633 */
3634 if (mode->clock != clock1)
3635 newmode->clock = clock1;
3636 else
3637 newmode->clock = clock2;
3638
3639 list_add_tail(&newmode->head, &list);
3640 }
3641
3642 list_for_each_entry_safe(mode, tmp, &list, head) {
3643 list_del(&mode->head);
3644 drm_mode_probed_add(connector, mode);
3645 modes++;
3646 }
3647
3648 return modes;
3649}
3650
3651static u8 svd_to_vic(u8 svd)
3652{
3653 /* 0-6 bit vic, 7th bit native mode indicator */
3654 if ((svd >= 1 && svd <= 64) || (svd >= 129 && svd <= 192))
3655 return svd & 127;
3656
3657 return svd;
3658}
3659
3660static struct drm_display_mode *
3661drm_display_mode_from_vic_index(struct drm_connector *connector,
3662 const u8 *video_db, u8 video_len,
3663 u8 video_index)
3664{
3665 struct drm_device *dev = connector->dev;
3666 struct drm_display_mode *newmode;
3667 u8 vic;
3668
3669 if (video_db == NULL || video_index >= video_len)
3670 return NULL;
3671
3672 /* CEA modes are numbered 1..127 */
3673 vic = svd_to_vic(video_db[video_index]);
3674 if (!drm_valid_cea_vic(vic))
3675 return NULL;
3676
3677 newmode = drm_mode_duplicate(dev, cea_mode_for_vic(vic));
3678 if (!newmode)
3679 return NULL;
3680
3681 return newmode;
3682}
3683
3684/*
3685 * do_y420vdb_modes - Parse YCBCR 420 only modes
3686 * @connector: connector corresponding to the HDMI sink
3687 * @svds: start of the data block of CEA YCBCR 420 VDB
3688 * @len: length of the CEA YCBCR 420 VDB
3689 *
3690 * Parse the CEA-861-F YCBCR 420 Video Data Block (Y420VDB)
3691 * which contains modes which can be supported in YCBCR 420
3692 * output format only.
3693 */
3694static int do_y420vdb_modes(struct drm_connector *connector,
3695 const u8 *svds, u8 svds_len)
3696{
3697 int modes = 0, i;
3698 struct drm_device *dev = connector->dev;
3699 struct drm_display_info *info = &connector->display_info;
3700 struct drm_hdmi_info *hdmi = &info->hdmi;
3701
3702 for (i = 0; i < svds_len; i++) {
3703 u8 vic = svd_to_vic(svds[i]);
3704 struct drm_display_mode *newmode;
3705
3706 if (!drm_valid_cea_vic(vic))
3707 continue;
3708
3709 newmode = drm_mode_duplicate(dev, cea_mode_for_vic(vic));
3710 if (!newmode)
3711 break;
3712 bitmap_set(hdmi->y420_vdb_modes, vic, 1);
3713 drm_mode_probed_add(connector, newmode);
3714 modes++;
3715 }
3716
3717 if (modes > 0)
3718 info->color_formats |= DRM_COLOR_FORMAT_YCRCB420;
3719 return modes;
3720}
3721
3722/*
3723 * drm_add_cmdb_modes - Add a YCBCR 420 mode into bitmap
3724 * @connector: connector corresponding to the HDMI sink
3725 * @vic: CEA vic for the video mode to be added in the map
3726 *
3727 * Makes an entry for a videomode in the YCBCR 420 bitmap
3728 */
3729static void
3730drm_add_cmdb_modes(struct drm_connector *connector, u8 svd)
3731{
3732 u8 vic = svd_to_vic(svd);
3733 struct drm_hdmi_info *hdmi = &connector->display_info.hdmi;
3734
3735 if (!drm_valid_cea_vic(vic))
3736 return;
3737
3738 bitmap_set(hdmi->y420_cmdb_modes, vic, 1);
3739}
3740
3741static int
3742do_cea_modes(struct drm_connector *connector, const u8 *db, u8 len)
3743{
3744 int i, modes = 0;
3745 struct drm_hdmi_info *hdmi = &connector->display_info.hdmi;
3746
3747 for (i = 0; i < len; i++) {
3748 struct drm_display_mode *mode;
3749
3750 mode = drm_display_mode_from_vic_index(connector, db, len, i);
3751 if (mode) {
3752 /*
3753 * YCBCR420 capability block contains a bitmap which
3754 * gives the index of CEA modes from CEA VDB, which
3755 * can support YCBCR 420 sampling output also (apart
3756 * from RGB/YCBCR444 etc).
3757 * For example, if the bit 0 in bitmap is set,
3758 * first mode in VDB can support YCBCR420 output too.
3759 * Add YCBCR420 modes only if sink is HDMI 2.0 capable.
3760 */
3761 if (i < 64 && hdmi->y420_cmdb_map & (1ULL << i))
3762 drm_add_cmdb_modes(connector, db[i]);
3763
3764 drm_mode_probed_add(connector, mode);
3765 modes++;
3766 }
3767 }
3768
3769 return modes;
3770}
3771
3772struct stereo_mandatory_mode {
3773 int width, height, vrefresh;
3774 unsigned int flags;
3775};
3776
3777static const struct stereo_mandatory_mode stereo_mandatory_modes[] = {
3778 { 1920, 1080, 24, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM },
3779 { 1920, 1080, 24, DRM_MODE_FLAG_3D_FRAME_PACKING },
3780 { 1920, 1080, 50,
3781 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF },
3782 { 1920, 1080, 60,
3783 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF },
3784 { 1280, 720, 50, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM },
3785 { 1280, 720, 50, DRM_MODE_FLAG_3D_FRAME_PACKING },
3786 { 1280, 720, 60, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM },
3787 { 1280, 720, 60, DRM_MODE_FLAG_3D_FRAME_PACKING }
3788};
3789
3790static bool
3791stereo_match_mandatory(const struct drm_display_mode *mode,
3792 const struct stereo_mandatory_mode *stereo_mode)
3793{
3794 unsigned int interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE;
3795
3796 return mode->hdisplay == stereo_mode->width &&
3797 mode->vdisplay == stereo_mode->height &&
3798 interlaced == (stereo_mode->flags & DRM_MODE_FLAG_INTERLACE) &&
3799 drm_mode_vrefresh(mode) == stereo_mode->vrefresh;
3800}
3801
3802static int add_hdmi_mandatory_stereo_modes(struct drm_connector *connector)
3803{
3804 struct drm_device *dev = connector->dev;
3805 const struct drm_display_mode *mode;
3806 struct list_head stereo_modes;
3807 int modes = 0, i;
3808
3809 INIT_LIST_HEAD(&stereo_modes);
3810
3811 list_for_each_entry(mode, &connector->probed_modes, head) {
3812 for (i = 0; i < ARRAY_SIZE(stereo_mandatory_modes); i++) {
3813 const struct stereo_mandatory_mode *mandatory;
3814 struct drm_display_mode *new_mode;
3815
3816 if (!stereo_match_mandatory(mode,
3817 &stereo_mandatory_modes[i]))
3818 continue;
3819
3820 mandatory = &stereo_mandatory_modes[i];
3821 new_mode = drm_mode_duplicate(dev, mode);
3822 if (!new_mode)
3823 continue;
3824
3825 new_mode->flags |= mandatory->flags;
3826 list_add_tail(&new_mode->head, &stereo_modes);
3827 modes++;
3828 }
3829 }
3830
3831 list_splice_tail(&stereo_modes, &connector->probed_modes);
3832
3833 return modes;
3834}
3835
3836static int add_hdmi_mode(struct drm_connector *connector, u8 vic)
3837{
3838 struct drm_device *dev = connector->dev;
3839 struct drm_display_mode *newmode;
3840
3841 if (!drm_valid_hdmi_vic(vic)) {
3842 DRM_ERROR("Unknown HDMI VIC: %d\n", vic);
3843 return 0;
3844 }
3845
3846 newmode = drm_mode_duplicate(dev, &edid_4k_modes[vic]);
3847 if (!newmode)
3848 return 0;
3849
3850 drm_mode_probed_add(connector, newmode);
3851
3852 return 1;
3853}
3854
3855static int add_3d_struct_modes(struct drm_connector *connector, u16 structure,
3856 const u8 *video_db, u8 video_len, u8 video_index)
3857{
3858 struct drm_display_mode *newmode;
3859 int modes = 0;
3860
3861 if (structure & (1 << 0)) {
3862 newmode = drm_display_mode_from_vic_index(connector, video_db,
3863 video_len,
3864 video_index);
3865 if (newmode) {
3866 newmode->flags |= DRM_MODE_FLAG_3D_FRAME_PACKING;
3867 drm_mode_probed_add(connector, newmode);
3868 modes++;
3869 }
3870 }
3871 if (structure & (1 << 6)) {
3872 newmode = drm_display_mode_from_vic_index(connector, video_db,
3873 video_len,
3874 video_index);
3875 if (newmode) {
3876 newmode->flags |= DRM_MODE_FLAG_3D_TOP_AND_BOTTOM;
3877 drm_mode_probed_add(connector, newmode);
3878 modes++;
3879 }
3880 }
3881 if (structure & (1 << 8)) {
3882 newmode = drm_display_mode_from_vic_index(connector, video_db,
3883 video_len,
3884 video_index);
3885 if (newmode) {
3886 newmode->flags |= DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF;
3887 drm_mode_probed_add(connector, newmode);
3888 modes++;
3889 }
3890 }
3891
3892 return modes;
3893}
3894
3895/*
3896 * do_hdmi_vsdb_modes - Parse the HDMI Vendor Specific data block
3897 * @connector: connector corresponding to the HDMI sink
3898 * @db: start of the CEA vendor specific block
3899 * @len: length of the CEA block payload, ie. one can access up to db[len]
3900 *
3901 * Parses the HDMI VSDB looking for modes to add to @connector. This function
3902 * also adds the stereo 3d modes when applicable.
3903 */
3904static int
3905do_hdmi_vsdb_modes(struct drm_connector *connector, const u8 *db, u8 len,
3906 const u8 *video_db, u8 video_len)
3907{
3908 struct drm_display_info *info = &connector->display_info;
3909 int modes = 0, offset = 0, i, multi_present = 0, multi_len;
3910 u8 vic_len, hdmi_3d_len = 0;
3911 u16 mask;
3912 u16 structure_all;
3913
3914 if (len < 8)
3915 goto out;
3916
3917 /* no HDMI_Video_Present */
3918 if (!(db[8] & (1 << 5)))
3919 goto out;
3920
3921 /* Latency_Fields_Present */
3922 if (db[8] & (1 << 7))
3923 offset += 2;
3924
3925 /* I_Latency_Fields_Present */
3926 if (db[8] & (1 << 6))
3927 offset += 2;
3928
3929 /* the declared length is not long enough for the 2 first bytes
3930 * of additional video format capabilities */
3931 if (len < (8 + offset + 2))
3932 goto out;
3933
3934 /* 3D_Present */
3935 offset++;
3936 if (db[8 + offset] & (1 << 7)) {
3937 modes += add_hdmi_mandatory_stereo_modes(connector);
3938
3939 /* 3D_Multi_present */
3940 multi_present = (db[8 + offset] & 0x60) >> 5;
3941 }
3942
3943 offset++;
3944 vic_len = db[8 + offset] >> 5;
3945 hdmi_3d_len = db[8 + offset] & 0x1f;
3946
3947 for (i = 0; i < vic_len && len >= (9 + offset + i); i++) {
3948 u8 vic;
3949
3950 vic = db[9 + offset + i];
3951 modes += add_hdmi_mode(connector, vic);
3952 }
3953 offset += 1 + vic_len;
3954
3955 if (multi_present == 1)
3956 multi_len = 2;
3957 else if (multi_present == 2)
3958 multi_len = 4;
3959 else
3960 multi_len = 0;
3961
3962 if (len < (8 + offset + hdmi_3d_len - 1))
3963 goto out;
3964
3965 if (hdmi_3d_len < multi_len)
3966 goto out;
3967
3968 if (multi_present == 1 || multi_present == 2) {
3969 /* 3D_Structure_ALL */
3970 structure_all = (db[8 + offset] << 8) | db[9 + offset];
3971
3972 /* check if 3D_MASK is present */
3973 if (multi_present == 2)
3974 mask = (db[10 + offset] << 8) | db[11 + offset];
3975 else
3976 mask = 0xffff;
3977
3978 for (i = 0; i < 16; i++) {
3979 if (mask & (1 << i))
3980 modes += add_3d_struct_modes(connector,
3981 structure_all,
3982 video_db,
3983 video_len, i);
3984 }
3985 }
3986
3987 offset += multi_len;
3988
3989 for (i = 0; i < (hdmi_3d_len - multi_len); i++) {
3990 int vic_index;
3991 struct drm_display_mode *newmode = NULL;
3992 unsigned int newflag = 0;
3993 bool detail_present;
3994
3995 detail_present = ((db[8 + offset + i] & 0x0f) > 7);
3996
3997 if (detail_present && (i + 1 == hdmi_3d_len - multi_len))
3998 break;
3999
4000 /* 2D_VIC_order_X */
4001 vic_index = db[8 + offset + i] >> 4;
4002
4003 /* 3D_Structure_X */
4004 switch (db[8 + offset + i] & 0x0f) {
4005 case 0:
4006 newflag = DRM_MODE_FLAG_3D_FRAME_PACKING;
4007 break;
4008 case 6:
4009 newflag = DRM_MODE_FLAG_3D_TOP_AND_BOTTOM;
4010 break;
4011 case 8:
4012 /* 3D_Detail_X */
4013 if ((db[9 + offset + i] >> 4) == 1)
4014 newflag = DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF;
4015 break;
4016 }
4017
4018 if (newflag != 0) {
4019 newmode = drm_display_mode_from_vic_index(connector,
4020 video_db,
4021 video_len,
4022 vic_index);
4023
4024 if (newmode) {
4025 newmode->flags |= newflag;
4026 drm_mode_probed_add(connector, newmode);
4027 modes++;
4028 }
4029 }
4030
4031 if (detail_present)
4032 i++;
4033 }
4034
4035out:
4036 if (modes > 0)
4037 info->has_hdmi_infoframe = true;
4038 return modes;
4039}
4040
4041static int
4042cea_db_payload_len(const u8 *db)
4043{
4044 return db[0] & 0x1f;
4045}
4046
4047static int
4048cea_db_extended_tag(const u8 *db)
4049{
4050 return db[1];
4051}
4052
4053static int
4054cea_db_tag(const u8 *db)
4055{
4056 return db[0] >> 5;
4057}
4058
4059static int
4060cea_revision(const u8 *cea)
4061{
4062 /*
4063 * FIXME is this correct for the DispID variant?
4064 * The DispID spec doesn't really specify whether
4065 * this is the revision of the CEA extension or
4066 * the DispID CEA data block. And the only value
4067 * given as an example is 0.
4068 */
4069 return cea[1];
4070}
4071
4072static int
4073cea_db_offsets(const u8 *cea, int *start, int *end)
4074{
4075 /* DisplayID CTA extension blocks and top-level CEA EDID
4076 * block header definitions differ in the following bytes:
4077 * 1) Byte 2 of the header specifies length differently,
4078 * 2) Byte 3 is only present in the CEA top level block.
4079 *
4080 * The different definitions for byte 2 follow.
4081 *
4082 * DisplayID CTA extension block defines byte 2 as:
4083 * Number of payload bytes
4084 *
4085 * CEA EDID block defines byte 2 as:
4086 * Byte number (decimal) within this block where the 18-byte
4087 * DTDs begin. If no non-DTD data is present in this extension
4088 * block, the value should be set to 04h (the byte after next).
4089 * If set to 00h, there are no DTDs present in this block and
4090 * no non-DTD data.
4091 */
4092 if (cea[0] == DATA_BLOCK_CTA) {
4093 /*
4094 * for_each_displayid_db() has already verified
4095 * that these stay within expected bounds.
4096 */
4097 *start = 3;
4098 *end = *start + cea[2];
4099 } else if (cea[0] == CEA_EXT) {
4100 /* Data block offset in CEA extension block */
4101 *start = 4;
4102 *end = cea[2];
4103 if (*end == 0)
4104 *end = 127;
4105 if (*end < 4 || *end > 127)
4106 return -ERANGE;
4107 } else {
4108 return -EOPNOTSUPP;
4109 }
4110
4111 return 0;
4112}
4113
4114static bool cea_db_is_hdmi_vsdb(const u8 *db)
4115{
4116 int hdmi_id;
4117
4118 if (cea_db_tag(db) != VENDOR_BLOCK)
4119 return false;
4120
4121 if (cea_db_payload_len(db) < 5)
4122 return false;
4123
4124 hdmi_id = db[1] | (db[2] << 8) | (db[3] << 16);
4125
4126 return hdmi_id == HDMI_IEEE_OUI;
4127}
4128
4129static bool cea_db_is_hdmi_forum_vsdb(const u8 *db)
4130{
4131 unsigned int oui;
4132
4133 if (cea_db_tag(db) != VENDOR_BLOCK)
4134 return false;
4135
4136 if (cea_db_payload_len(db) < 7)
4137 return false;
4138
4139 oui = db[3] << 16 | db[2] << 8 | db[1];
4140
4141 return oui == HDMI_FORUM_IEEE_OUI;
4142}
4143
4144static bool cea_db_is_vcdb(const u8 *db)
4145{
4146 if (cea_db_tag(db) != USE_EXTENDED_TAG)
4147 return false;
4148
4149 if (cea_db_payload_len(db) != 2)
4150 return false;
4151
4152 if (cea_db_extended_tag(db) != EXT_VIDEO_CAPABILITY_BLOCK)
4153 return false;
4154
4155 return true;
4156}
4157
4158static bool cea_db_is_y420cmdb(const u8 *db)
4159{
4160 if (cea_db_tag(db) != USE_EXTENDED_TAG)
4161 return false;
4162
4163 if (!cea_db_payload_len(db))
4164 return false;
4165
4166 if (cea_db_extended_tag(db) != EXT_VIDEO_CAP_BLOCK_Y420CMDB)
4167 return false;
4168
4169 return true;
4170}
4171
4172static bool cea_db_is_y420vdb(const u8 *db)
4173{
4174 if (cea_db_tag(db) != USE_EXTENDED_TAG)
4175 return false;
4176
4177 if (!cea_db_payload_len(db))
4178 return false;
4179
4180 if (cea_db_extended_tag(db) != EXT_VIDEO_DATA_BLOCK_420)
4181 return false;
4182
4183 return true;
4184}
4185
4186#define for_each_cea_db(cea, i, start, end) \
4187 for ((i) = (start); (i) < (end) && (i) + cea_db_payload_len(&(cea)[(i)]) < (end); (i) += cea_db_payload_len(&(cea)[(i)]) + 1)
4188
4189static void drm_parse_y420cmdb_bitmap(struct drm_connector *connector,
4190 const u8 *db)
4191{
4192 struct drm_display_info *info = &connector->display_info;
4193 struct drm_hdmi_info *hdmi = &info->hdmi;
4194 u8 map_len = cea_db_payload_len(db) - 1;
4195 u8 count;
4196 u64 map = 0;
4197
4198 if (map_len == 0) {
4199 /* All CEA modes support ycbcr420 sampling also.*/
4200 hdmi->y420_cmdb_map = U64_MAX;
4201 info->color_formats |= DRM_COLOR_FORMAT_YCRCB420;
4202 return;
4203 }
4204
4205 /*
4206 * This map indicates which of the existing CEA block modes
4207 * from VDB can support YCBCR420 output too. So if bit=0 is
4208 * set, first mode from VDB can support YCBCR420 output too.
4209 * We will parse and keep this map, before parsing VDB itself
4210 * to avoid going through the same block again and again.
4211 *
4212 * Spec is not clear about max possible size of this block.
4213 * Clamping max bitmap block size at 8 bytes. Every byte can
4214 * address 8 CEA modes, in this way this map can address
4215 * 8*8 = first 64 SVDs.
4216 */
4217 if (WARN_ON_ONCE(map_len > 8))
4218 map_len = 8;
4219
4220 for (count = 0; count < map_len; count++)
4221 map |= (u64)db[2 + count] << (8 * count);
4222
4223 if (map)
4224 info->color_formats |= DRM_COLOR_FORMAT_YCRCB420;
4225
4226 hdmi->y420_cmdb_map = map;
4227}
4228
4229static int
4230add_cea_modes(struct drm_connector *connector, struct edid *edid)
4231{
4232 const u8 *cea = drm_find_cea_extension(edid);
4233 const u8 *db, *hdmi = NULL, *video = NULL;
4234 u8 dbl, hdmi_len, video_len = 0;
4235 int modes = 0;
4236
4237 if (cea && cea_revision(cea) >= 3) {
4238 int i, start, end;
4239
4240 if (cea_db_offsets(cea, &start, &end))
4241 return 0;
4242
4243 for_each_cea_db(cea, i, start, end) {
4244 db = &cea[i];
4245 dbl = cea_db_payload_len(db);
4246
4247 if (cea_db_tag(db) == VIDEO_BLOCK) {
4248 video = db + 1;
4249 video_len = dbl;
4250 modes += do_cea_modes(connector, video, dbl);
4251 } else if (cea_db_is_hdmi_vsdb(db)) {
4252 hdmi = db;
4253 hdmi_len = dbl;
4254 } else if (cea_db_is_y420vdb(db)) {
4255 const u8 *vdb420 = &db[2];
4256
4257 /* Add 4:2:0(only) modes present in EDID */
4258 modes += do_y420vdb_modes(connector,
4259 vdb420,
4260 dbl - 1);
4261 }
4262 }
4263 }
4264
4265 /*
4266 * We parse the HDMI VSDB after having added the cea modes as we will
4267 * be patching their flags when the sink supports stereo 3D.
4268 */
4269 if (hdmi)
4270 modes += do_hdmi_vsdb_modes(connector, hdmi, hdmi_len, video,
4271 video_len);
4272
4273 return modes;
4274}
4275
4276static void fixup_detailed_cea_mode_clock(struct drm_display_mode *mode)
4277{
4278 const struct drm_display_mode *cea_mode;
4279 int clock1, clock2, clock;
4280 u8 vic;
4281 const char *type;
4282
4283 /*
4284 * allow 5kHz clock difference either way to account for
4285 * the 10kHz clock resolution limit of detailed timings.
4286 */
4287 vic = drm_match_cea_mode_clock_tolerance(mode, 5);
4288 if (drm_valid_cea_vic(vic)) {
4289 type = "CEA";
4290 cea_mode = cea_mode_for_vic(vic);
4291 clock1 = cea_mode->clock;
4292 clock2 = cea_mode_alternate_clock(cea_mode);
4293 } else {
4294 vic = drm_match_hdmi_mode_clock_tolerance(mode, 5);
4295 if (drm_valid_hdmi_vic(vic)) {
4296 type = "HDMI";
4297 cea_mode = &edid_4k_modes[vic];
4298 clock1 = cea_mode->clock;
4299 clock2 = hdmi_mode_alternate_clock(cea_mode);
4300 } else {
4301 return;
4302 }
4303 }
4304
4305 /* pick whichever is closest */
4306 if (abs(mode->clock - clock1) < abs(mode->clock - clock2))
4307 clock = clock1;
4308 else
4309 clock = clock2;
4310
4311 if (mode->clock == clock)
4312 return;
4313
4314 DRM_DEBUG("detailed mode matches %s VIC %d, adjusting clock %d -> %d\n",
4315 type, vic, mode->clock, clock);
4316 mode->clock = clock;
4317}
4318
4319static bool cea_db_is_hdmi_hdr_metadata_block(const u8 *db)
4320{
4321 if (cea_db_tag(db) != USE_EXTENDED_TAG)
4322 return false;
4323
4324 if (db[1] != HDR_STATIC_METADATA_BLOCK)
4325 return false;
4326
4327 if (cea_db_payload_len(db) < 3)
4328 return false;
4329
4330 return true;
4331}
4332
4333static uint8_t eotf_supported(const u8 *edid_ext)
4334{
4335 return edid_ext[2] &
4336 (BIT(HDMI_EOTF_TRADITIONAL_GAMMA_SDR) |
4337 BIT(HDMI_EOTF_TRADITIONAL_GAMMA_HDR) |
4338 BIT(HDMI_EOTF_SMPTE_ST2084) |
4339 BIT(HDMI_EOTF_BT_2100_HLG));
4340}
4341
4342static uint8_t hdr_metadata_type(const u8 *edid_ext)
4343{
4344 return edid_ext[3] &
4345 BIT(HDMI_STATIC_METADATA_TYPE1);
4346}
4347
4348static void
4349drm_parse_hdr_metadata_block(struct drm_connector *connector, const u8 *db)
4350{
4351 u16 len;
4352
4353 len = cea_db_payload_len(db);
4354
4355 connector->hdr_sink_metadata.hdmi_type1.eotf =
4356 eotf_supported(db);
4357 connector->hdr_sink_metadata.hdmi_type1.metadata_type =
4358 hdr_metadata_type(db);
4359
4360 if (len >= 4)
4361 connector->hdr_sink_metadata.hdmi_type1.max_cll = db[4];
4362 if (len >= 5)
4363 connector->hdr_sink_metadata.hdmi_type1.max_fall = db[5];
4364 if (len >= 6)
4365 connector->hdr_sink_metadata.hdmi_type1.min_cll = db[6];
4366}
4367
4368static void
4369drm_parse_hdmi_vsdb_audio(struct drm_connector *connector, const u8 *db)
4370{
4371 u8 len = cea_db_payload_len(db);
4372
4373 if (len >= 6 && (db[6] & (1 << 7)))
4374 connector->eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_SUPPORTS_AI;
4375 if (len >= 8) {
4376 connector->latency_present[0] = db[8] >> 7;
4377 connector->latency_present[1] = (db[8] >> 6) & 1;
4378 }
4379 if (len >= 9)
4380 connector->video_latency[0] = db[9];
4381 if (len >= 10)
4382 connector->audio_latency[0] = db[10];
4383 if (len >= 11)
4384 connector->video_latency[1] = db[11];
4385 if (len >= 12)
4386 connector->audio_latency[1] = db[12];
4387
4388 DRM_DEBUG_KMS("HDMI: latency present %d %d, "
4389 "video latency %d %d, "
4390 "audio latency %d %d\n",
4391 connector->latency_present[0],
4392 connector->latency_present[1],
4393 connector->video_latency[0],
4394 connector->video_latency[1],
4395 connector->audio_latency[0],
4396 connector->audio_latency[1]);
4397}
4398
4399static void
4400monitor_name(struct detailed_timing *t, void *data)
4401{
4402 if (!is_display_descriptor((const u8 *)t, EDID_DETAIL_MONITOR_NAME))
4403 return;
4404
4405 *(u8 **)data = t->data.other_data.data.str.str;
4406}
4407
4408static int get_monitor_name(struct edid *edid, char name[13])
4409{
4410 char *edid_name = NULL;
4411 int mnl;
4412
4413 if (!edid || !name)
4414 return 0;
4415
4416 drm_for_each_detailed_block((u8 *)edid, monitor_name, &edid_name);
4417 for (mnl = 0; edid_name && mnl < 13; mnl++) {
4418 if (edid_name[mnl] == 0x0a)
4419 break;
4420
4421 name[mnl] = edid_name[mnl];
4422 }
4423
4424 return mnl;
4425}
4426
4427/**
4428 * drm_edid_get_monitor_name - fetch the monitor name from the edid
4429 * @edid: monitor EDID information
4430 * @name: pointer to a character array to hold the name of the monitor
4431 * @bufsize: The size of the name buffer (should be at least 14 chars.)
4432 *
4433 */
4434void drm_edid_get_monitor_name(struct edid *edid, char *name, int bufsize)
4435{
4436 int name_length;
4437 char buf[13];
4438
4439 if (bufsize <= 0)
4440 return;
4441
4442 name_length = min(get_monitor_name(edid, buf), bufsize - 1);
4443 memcpy(name, buf, name_length);
4444 name[name_length] = '\0';
4445}
4446EXPORT_SYMBOL(drm_edid_get_monitor_name);
4447
4448static void clear_eld(struct drm_connector *connector)
4449{
4450 memset(connector->eld, 0, sizeof(connector->eld));
4451
4452 connector->latency_present[0] = false;
4453 connector->latency_present[1] = false;
4454 connector->video_latency[0] = 0;
4455 connector->audio_latency[0] = 0;
4456 connector->video_latency[1] = 0;
4457 connector->audio_latency[1] = 0;
4458}
4459
4460/*
4461 * drm_edid_to_eld - build ELD from EDID
4462 * @connector: connector corresponding to the HDMI/DP sink
4463 * @edid: EDID to parse
4464 *
4465 * Fill the ELD (EDID-Like Data) buffer for passing to the audio driver. The
4466 * HDCP and Port_ID ELD fields are left for the graphics driver to fill in.
4467 */
4468static void drm_edid_to_eld(struct drm_connector *connector, struct edid *edid)
4469{
4470 uint8_t *eld = connector->eld;
4471 u8 *cea;
4472 u8 *db;
4473 int total_sad_count = 0;
4474 int mnl;
4475 int dbl;
4476
4477 clear_eld(connector);
4478
4479 if (!edid)
4480 return;
4481
4482 cea = drm_find_cea_extension(edid);
4483 if (!cea) {
4484 DRM_DEBUG_KMS("ELD: no CEA Extension found\n");
4485 return;
4486 }
4487
4488 mnl = get_monitor_name(edid, &eld[DRM_ELD_MONITOR_NAME_STRING]);
4489 DRM_DEBUG_KMS("ELD monitor %s\n", &eld[DRM_ELD_MONITOR_NAME_STRING]);
4490
4491 eld[DRM_ELD_CEA_EDID_VER_MNL] = cea[1] << DRM_ELD_CEA_EDID_VER_SHIFT;
4492 eld[DRM_ELD_CEA_EDID_VER_MNL] |= mnl;
4493
4494 eld[DRM_ELD_VER] = DRM_ELD_VER_CEA861D;
4495
4496 eld[DRM_ELD_MANUFACTURER_NAME0] = edid->mfg_id[0];
4497 eld[DRM_ELD_MANUFACTURER_NAME1] = edid->mfg_id[1];
4498 eld[DRM_ELD_PRODUCT_CODE0] = edid->prod_code[0];
4499 eld[DRM_ELD_PRODUCT_CODE1] = edid->prod_code[1];
4500
4501 if (cea_revision(cea) >= 3) {
4502 int i, start, end;
4503 int sad_count;
4504
4505 if (cea_db_offsets(cea, &start, &end)) {
4506 start = 0;
4507 end = 0;
4508 }
4509
4510 for_each_cea_db(cea, i, start, end) {
4511 db = &cea[i];
4512 dbl = cea_db_payload_len(db);
4513
4514 switch (cea_db_tag(db)) {
4515 case AUDIO_BLOCK:
4516 /* Audio Data Block, contains SADs */
4517 sad_count = min(dbl / 3, 15 - total_sad_count);
4518 if (sad_count >= 1)
4519 memcpy(&eld[DRM_ELD_CEA_SAD(mnl, total_sad_count)],
4520 &db[1], sad_count * 3);
4521 total_sad_count += sad_count;
4522 break;
4523 case SPEAKER_BLOCK:
4524 /* Speaker Allocation Data Block */
4525 if (dbl >= 1)
4526 eld[DRM_ELD_SPEAKER] = db[1];
4527 break;
4528 case VENDOR_BLOCK:
4529 /* HDMI Vendor-Specific Data Block */
4530 if (cea_db_is_hdmi_vsdb(db))
4531 drm_parse_hdmi_vsdb_audio(connector, db);
4532 break;
4533 default:
4534 break;
4535 }
4536 }
4537 }
4538 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= total_sad_count << DRM_ELD_SAD_COUNT_SHIFT;
4539
4540 if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
4541 connector->connector_type == DRM_MODE_CONNECTOR_eDP)
4542 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_CONN_TYPE_DP;
4543 else
4544 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_CONN_TYPE_HDMI;
4545
4546 eld[DRM_ELD_BASELINE_ELD_LEN] =
4547 DIV_ROUND_UP(drm_eld_calc_baseline_block_size(eld), 4);
4548
4549 DRM_DEBUG_KMS("ELD size %d, SAD count %d\n",
4550 drm_eld_size(eld), total_sad_count);
4551}
4552
4553/**
4554 * drm_edid_to_sad - extracts SADs from EDID
4555 * @edid: EDID to parse
4556 * @sads: pointer that will be set to the extracted SADs
4557 *
4558 * Looks for CEA EDID block and extracts SADs (Short Audio Descriptors) from it.
4559 *
4560 * Note: The returned pointer needs to be freed using kfree().
4561 *
4562 * Return: The number of found SADs or negative number on error.
4563 */
4564int drm_edid_to_sad(struct edid *edid, struct cea_sad **sads)
4565{
4566 int count = 0;
4567 int i, start, end, dbl;
4568 u8 *cea;
4569
4570 cea = drm_find_cea_extension(edid);
4571 if (!cea) {
4572 DRM_DEBUG_KMS("SAD: no CEA Extension found\n");
4573 return 0;
4574 }
4575
4576 if (cea_revision(cea) < 3) {
4577 DRM_DEBUG_KMS("SAD: wrong CEA revision\n");
4578 return 0;
4579 }
4580
4581 if (cea_db_offsets(cea, &start, &end)) {
4582 DRM_DEBUG_KMS("SAD: invalid data block offsets\n");
4583 return -EPROTO;
4584 }
4585
4586 for_each_cea_db(cea, i, start, end) {
4587 u8 *db = &cea[i];
4588
4589 if (cea_db_tag(db) == AUDIO_BLOCK) {
4590 int j;
4591
4592 dbl = cea_db_payload_len(db);
4593
4594 count = dbl / 3; /* SAD is 3B */
4595 *sads = kcalloc(count, sizeof(**sads), GFP_KERNEL);
4596 if (!*sads)
4597 return -ENOMEM;
4598 for (j = 0; j < count; j++) {
4599 u8 *sad = &db[1 + j * 3];
4600
4601 (*sads)[j].format = (sad[0] & 0x78) >> 3;
4602 (*sads)[j].channels = sad[0] & 0x7;
4603 (*sads)[j].freq = sad[1] & 0x7F;
4604 (*sads)[j].byte2 = sad[2];
4605 }
4606 break;
4607 }
4608 }
4609
4610 return count;
4611}
4612EXPORT_SYMBOL(drm_edid_to_sad);
4613
4614/**
4615 * drm_edid_to_speaker_allocation - extracts Speaker Allocation Data Blocks from EDID
4616 * @edid: EDID to parse
4617 * @sadb: pointer to the speaker block
4618 *
4619 * Looks for CEA EDID block and extracts the Speaker Allocation Data Block from it.
4620 *
4621 * Note: The returned pointer needs to be freed using kfree().
4622 *
4623 * Return: The number of found Speaker Allocation Blocks or negative number on
4624 * error.
4625 */
4626int drm_edid_to_speaker_allocation(struct edid *edid, u8 **sadb)
4627{
4628 int count = 0;
4629 int i, start, end, dbl;
4630 const u8 *cea;
4631
4632 cea = drm_find_cea_extension(edid);
4633 if (!cea) {
4634 DRM_DEBUG_KMS("SAD: no CEA Extension found\n");
4635 return 0;
4636 }
4637
4638 if (cea_revision(cea) < 3) {
4639 DRM_DEBUG_KMS("SAD: wrong CEA revision\n");
4640 return 0;
4641 }
4642
4643 if (cea_db_offsets(cea, &start, &end)) {
4644 DRM_DEBUG_KMS("SAD: invalid data block offsets\n");
4645 return -EPROTO;
4646 }
4647
4648 for_each_cea_db(cea, i, start, end) {
4649 const u8 *db = &cea[i];
4650
4651 if (cea_db_tag(db) == SPEAKER_BLOCK) {
4652 dbl = cea_db_payload_len(db);
4653
4654 /* Speaker Allocation Data Block */
4655 if (dbl == 3) {
4656 *sadb = kmemdup(&db[1], dbl, GFP_KERNEL);
4657 if (!*sadb)
4658 return -ENOMEM;
4659 count = dbl;
4660 break;
4661 }
4662 }
4663 }
4664
4665 return count;
4666}
4667EXPORT_SYMBOL(drm_edid_to_speaker_allocation);
4668
4669/**
4670 * drm_av_sync_delay - compute the HDMI/DP sink audio-video sync delay
4671 * @connector: connector associated with the HDMI/DP sink
4672 * @mode: the display mode
4673 *
4674 * Return: The HDMI/DP sink's audio-video sync delay in milliseconds or 0 if
4675 * the sink doesn't support audio or video.
4676 */
4677int drm_av_sync_delay(struct drm_connector *connector,
4678 const struct drm_display_mode *mode)
4679{
4680 int i = !!(mode->flags & DRM_MODE_FLAG_INTERLACE);
4681 int a, v;
4682
4683 if (!connector->latency_present[0])
4684 return 0;
4685 if (!connector->latency_present[1])
4686 i = 0;
4687
4688 a = connector->audio_latency[i];
4689 v = connector->video_latency[i];
4690
4691 /*
4692 * HDMI/DP sink doesn't support audio or video?
4693 */
4694 if (a == 255 || v == 255)
4695 return 0;
4696
4697 /*
4698 * Convert raw EDID values to millisecond.
4699 * Treat unknown latency as 0ms.
4700 */
4701 if (a)
4702 a = min(2 * (a - 1), 500);
4703 if (v)
4704 v = min(2 * (v - 1), 500);
4705
4706 return max(v - a, 0);
4707}
4708EXPORT_SYMBOL(drm_av_sync_delay);
4709
4710/**
4711 * drm_detect_hdmi_monitor - detect whether monitor is HDMI
4712 * @edid: monitor EDID information
4713 *
4714 * Parse the CEA extension according to CEA-861-B.
4715 *
4716 * Drivers that have added the modes parsed from EDID to drm_display_info
4717 * should use &drm_display_info.is_hdmi instead of calling this function.
4718 *
4719 * Return: True if the monitor is HDMI, false if not or unknown.
4720 */
4721bool drm_detect_hdmi_monitor(struct edid *edid)
4722{
4723 u8 *edid_ext;
4724 int i;
4725 int start_offset, end_offset;
4726
4727 edid_ext = drm_find_cea_extension(edid);
4728 if (!edid_ext)
4729 return false;
4730
4731 if (cea_db_offsets(edid_ext, &start_offset, &end_offset))
4732 return false;
4733
4734 /*
4735 * Because HDMI identifier is in Vendor Specific Block,
4736 * search it from all data blocks of CEA extension.
4737 */
4738 for_each_cea_db(edid_ext, i, start_offset, end_offset) {
4739 if (cea_db_is_hdmi_vsdb(&edid_ext[i]))
4740 return true;
4741 }
4742
4743 return false;
4744}
4745EXPORT_SYMBOL(drm_detect_hdmi_monitor);
4746
4747/**
4748 * drm_detect_monitor_audio - check monitor audio capability
4749 * @edid: EDID block to scan
4750 *
4751 * Monitor should have CEA extension block.
4752 * If monitor has 'basic audio', but no CEA audio blocks, it's 'basic
4753 * audio' only. If there is any audio extension block and supported
4754 * audio format, assume at least 'basic audio' support, even if 'basic
4755 * audio' is not defined in EDID.
4756 *
4757 * Return: True if the monitor supports audio, false otherwise.
4758 */
4759bool drm_detect_monitor_audio(struct edid *edid)
4760{
4761 u8 *edid_ext;
4762 int i, j;
4763 bool has_audio = false;
4764 int start_offset, end_offset;
4765
4766 edid_ext = drm_find_cea_extension(edid);
4767 if (!edid_ext)
4768 goto end;
4769
4770 has_audio = ((edid_ext[3] & EDID_BASIC_AUDIO) != 0);
4771
4772 if (has_audio) {
4773 DRM_DEBUG_KMS("Monitor has basic audio support\n");
4774 goto end;
4775 }
4776
4777 if (cea_db_offsets(edid_ext, &start_offset, &end_offset))
4778 goto end;
4779
4780 for_each_cea_db(edid_ext, i, start_offset, end_offset) {
4781 if (cea_db_tag(&edid_ext[i]) == AUDIO_BLOCK) {
4782 has_audio = true;
4783 for (j = 1; j < cea_db_payload_len(&edid_ext[i]) + 1; j += 3)
4784 DRM_DEBUG_KMS("CEA audio format %d\n",
4785 (edid_ext[i + j] >> 3) & 0xf);
4786 goto end;
4787 }
4788 }
4789end:
4790 return has_audio;
4791}
4792EXPORT_SYMBOL(drm_detect_monitor_audio);
4793
4794
4795/**
4796 * drm_default_rgb_quant_range - default RGB quantization range
4797 * @mode: display mode
4798 *
4799 * Determine the default RGB quantization range for the mode,
4800 * as specified in CEA-861.
4801 *
4802 * Return: The default RGB quantization range for the mode
4803 */
4804enum hdmi_quantization_range
4805drm_default_rgb_quant_range(const struct drm_display_mode *mode)
4806{
4807 /* All CEA modes other than VIC 1 use limited quantization range. */
4808 return drm_match_cea_mode(mode) > 1 ?
4809 HDMI_QUANTIZATION_RANGE_LIMITED :
4810 HDMI_QUANTIZATION_RANGE_FULL;
4811}
4812EXPORT_SYMBOL(drm_default_rgb_quant_range);
4813
4814static void drm_parse_vcdb(struct drm_connector *connector, const u8 *db)
4815{
4816 struct drm_display_info *info = &connector->display_info;
4817
4818 DRM_DEBUG_KMS("CEA VCDB 0x%02x\n", db[2]);
4819
4820 if (db[2] & EDID_CEA_VCDB_QS)
4821 info->rgb_quant_range_selectable = true;
4822}
4823
4824static void drm_parse_ycbcr420_deep_color_info(struct drm_connector *connector,
4825 const u8 *db)
4826{
4827 u8 dc_mask;
4828 struct drm_hdmi_info *hdmi = &connector->display_info.hdmi;
4829
4830 dc_mask = db[7] & DRM_EDID_YCBCR420_DC_MASK;
4831 hdmi->y420_dc_modes = dc_mask;
4832}
4833
4834static void drm_parse_hdmi_forum_vsdb(struct drm_connector *connector,
4835 const u8 *hf_vsdb)
4836{
4837 struct drm_display_info *display = &connector->display_info;
4838 struct drm_hdmi_info *hdmi = &display->hdmi;
4839
4840 display->has_hdmi_infoframe = true;
4841
4842 if (hf_vsdb[6] & 0x80) {
4843 hdmi->scdc.supported = true;
4844 if (hf_vsdb[6] & 0x40)
4845 hdmi->scdc.read_request = true;
4846 }
4847
4848 /*
4849 * All HDMI 2.0 monitors must support scrambling at rates > 340 MHz.
4850 * And as per the spec, three factors confirm this:
4851 * * Availability of a HF-VSDB block in EDID (check)
4852 * * Non zero Max_TMDS_Char_Rate filed in HF-VSDB (let's check)
4853 * * SCDC support available (let's check)
4854 * Lets check it out.
4855 */
4856
4857 if (hf_vsdb[5]) {
4858 /* max clock is 5000 KHz times block value */
4859 u32 max_tmds_clock = hf_vsdb[5] * 5000;
4860 struct drm_scdc *scdc = &hdmi->scdc;
4861
4862 if (max_tmds_clock > 340000) {
4863 display->max_tmds_clock = max_tmds_clock;
4864 DRM_DEBUG_KMS("HF-VSDB: max TMDS clock %d kHz\n",
4865 display->max_tmds_clock);
4866 }
4867
4868 if (scdc->supported) {
4869 scdc->scrambling.supported = true;
4870
4871 /* Few sinks support scrambling for clocks < 340M */
4872 if ((hf_vsdb[6] & 0x8))
4873 scdc->scrambling.low_rates = true;
4874 }
4875 }
4876
4877 drm_parse_ycbcr420_deep_color_info(connector, hf_vsdb);
4878}
4879
4880static void drm_parse_hdmi_deep_color_info(struct drm_connector *connector,
4881 const u8 *hdmi)
4882{
4883 struct drm_display_info *info = &connector->display_info;
4884 unsigned int dc_bpc = 0;
4885
4886 /* HDMI supports at least 8 bpc */
4887 info->bpc = 8;
4888
4889 if (cea_db_payload_len(hdmi) < 6)
4890 return;
4891
4892 if (hdmi[6] & DRM_EDID_HDMI_DC_30) {
4893 dc_bpc = 10;
4894 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_30;
4895 DRM_DEBUG("%s: HDMI sink does deep color 30.\n",
4896 connector->name);
4897 }
4898
4899 if (hdmi[6] & DRM_EDID_HDMI_DC_36) {
4900 dc_bpc = 12;
4901 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_36;
4902 DRM_DEBUG("%s: HDMI sink does deep color 36.\n",
4903 connector->name);
4904 }
4905
4906 if (hdmi[6] & DRM_EDID_HDMI_DC_48) {
4907 dc_bpc = 16;
4908 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_48;
4909 DRM_DEBUG("%s: HDMI sink does deep color 48.\n",
4910 connector->name);
4911 }
4912
4913 if (dc_bpc == 0) {
4914 DRM_DEBUG("%s: No deep color support on this HDMI sink.\n",
4915 connector->name);
4916 return;
4917 }
4918
4919 DRM_DEBUG("%s: Assigning HDMI sink color depth as %d bpc.\n",
4920 connector->name, dc_bpc);
4921 info->bpc = dc_bpc;
4922
4923 /*
4924 * Deep color support mandates RGB444 support for all video
4925 * modes and forbids YCRCB422 support for all video modes per
4926 * HDMI 1.3 spec.
4927 */
4928 info->color_formats = DRM_COLOR_FORMAT_RGB444;
4929
4930 /* YCRCB444 is optional according to spec. */
4931 if (hdmi[6] & DRM_EDID_HDMI_DC_Y444) {
4932 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444;
4933 DRM_DEBUG("%s: HDMI sink does YCRCB444 in deep color.\n",
4934 connector->name);
4935 }
4936
4937 /*
4938 * Spec says that if any deep color mode is supported at all,
4939 * then deep color 36 bit must be supported.
4940 */
4941 if (!(hdmi[6] & DRM_EDID_HDMI_DC_36)) {
4942 DRM_DEBUG("%s: HDMI sink should do DC_36, but does not!\n",
4943 connector->name);
4944 }
4945}
4946
4947static void
4948drm_parse_hdmi_vsdb_video(struct drm_connector *connector, const u8 *db)
4949{
4950 struct drm_display_info *info = &connector->display_info;
4951 u8 len = cea_db_payload_len(db);
4952
4953 info->is_hdmi = true;
4954
4955 if (len >= 6)
4956 info->dvi_dual = db[6] & 1;
4957 if (len >= 7)
4958 info->max_tmds_clock = db[7] * 5000;
4959
4960 DRM_DEBUG_KMS("HDMI: DVI dual %d, "
4961 "max TMDS clock %d kHz\n",
4962 info->dvi_dual,
4963 info->max_tmds_clock);
4964
4965 drm_parse_hdmi_deep_color_info(connector, db);
4966}
4967
4968static void drm_parse_cea_ext(struct drm_connector *connector,
4969 const struct edid *edid)
4970{
4971 struct drm_display_info *info = &connector->display_info;
4972 const u8 *edid_ext;
4973 int i, start, end;
4974
4975 edid_ext = drm_find_cea_extension(edid);
4976 if (!edid_ext)
4977 return;
4978
4979 info->cea_rev = edid_ext[1];
4980
4981 /* The existence of a CEA block should imply RGB support */
4982 info->color_formats = DRM_COLOR_FORMAT_RGB444;
4983 if (edid_ext[3] & EDID_CEA_YCRCB444)
4984 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444;
4985 if (edid_ext[3] & EDID_CEA_YCRCB422)
4986 info->color_formats |= DRM_COLOR_FORMAT_YCRCB422;
4987
4988 if (cea_db_offsets(edid_ext, &start, &end))
4989 return;
4990
4991 for_each_cea_db(edid_ext, i, start, end) {
4992 const u8 *db = &edid_ext[i];
4993
4994 if (cea_db_is_hdmi_vsdb(db))
4995 drm_parse_hdmi_vsdb_video(connector, db);
4996 if (cea_db_is_hdmi_forum_vsdb(db))
4997 drm_parse_hdmi_forum_vsdb(connector, db);
4998 if (cea_db_is_y420cmdb(db))
4999 drm_parse_y420cmdb_bitmap(connector, db);
5000 if (cea_db_is_vcdb(db))
5001 drm_parse_vcdb(connector, db);
5002 if (cea_db_is_hdmi_hdr_metadata_block(db))
5003 drm_parse_hdr_metadata_block(connector, db);
5004 }
5005}
5006
5007static
5008void get_monitor_range(struct detailed_timing *timing,
5009 void *info_monitor_range)
5010{
5011 struct drm_monitor_range_info *monitor_range = info_monitor_range;
5012 const struct detailed_non_pixel *data = &timing->data.other_data;
5013 const struct detailed_data_monitor_range *range = &data->data.range;
5014
5015 if (!is_display_descriptor((const u8 *)timing, EDID_DETAIL_MONITOR_RANGE))
5016 return;
5017
5018 /*
5019 * Check for flag range limits only. If flag == 1 then
5020 * no additional timing information provided.
5021 * Default GTF, GTF Secondary curve and CVT are not
5022 * supported
5023 */
5024 if (range->flags != DRM_EDID_RANGE_LIMITS_ONLY_FLAG)
5025 return;
5026
5027 monitor_range->min_vfreq = range->min_vfreq;
5028 monitor_range->max_vfreq = range->max_vfreq;
5029}
5030
5031static
5032void drm_get_monitor_range(struct drm_connector *connector,
5033 const struct edid *edid)
5034{
5035 struct drm_display_info *info = &connector->display_info;
5036
5037 if (!version_greater(edid, 1, 1))
5038 return;
5039
5040 drm_for_each_detailed_block((u8 *)edid, get_monitor_range,
5041 &info->monitor_range);
5042
5043 DRM_DEBUG_KMS("Supported Monitor Refresh rate range is %d Hz - %d Hz\n",
5044 info->monitor_range.min_vfreq,
5045 info->monitor_range.max_vfreq);
5046}
5047
5048/* A connector has no EDID information, so we've got no EDID to compute quirks from. Reset
5049 * all of the values which would have been set from EDID
5050 */
5051void
5052drm_reset_display_info(struct drm_connector *connector)
5053{
5054 struct drm_display_info *info = &connector->display_info;
5055
5056 info->width_mm = 0;
5057 info->height_mm = 0;
5058
5059 info->bpc = 0;
5060 info->color_formats = 0;
5061 info->cea_rev = 0;
5062 info->max_tmds_clock = 0;
5063 info->dvi_dual = false;
5064 info->is_hdmi = false;
5065 info->has_hdmi_infoframe = false;
5066 info->rgb_quant_range_selectable = false;
5067 memset(&info->hdmi, 0, sizeof(info->hdmi));
5068
5069 info->non_desktop = 0;
5070 memset(&info->monitor_range, 0, sizeof(info->monitor_range));
5071}
5072
5073u32 drm_add_display_info(struct drm_connector *connector, const struct edid *edid)
5074{
5075 struct drm_display_info *info = &connector->display_info;
5076
5077 u32 quirks = edid_get_quirks(edid);
5078
5079 drm_reset_display_info(connector);
5080
5081 info->width_mm = edid->width_cm * 10;
5082 info->height_mm = edid->height_cm * 10;
5083
5084 info->non_desktop = !!(quirks & EDID_QUIRK_NON_DESKTOP);
5085
5086 drm_get_monitor_range(connector, edid);
5087
5088 DRM_DEBUG_KMS("non_desktop set to %d\n", info->non_desktop);
5089
5090 if (edid->revision < 3)
5091 return quirks;
5092
5093 if (!(edid->input & DRM_EDID_INPUT_DIGITAL))
5094 return quirks;
5095
5096 drm_parse_cea_ext(connector, edid);
5097
5098 /*
5099 * Digital sink with "DFP 1.x compliant TMDS" according to EDID 1.3?
5100 *
5101 * For such displays, the DFP spec 1.0, section 3.10 "EDID support"
5102 * tells us to assume 8 bpc color depth if the EDID doesn't have
5103 * extensions which tell otherwise.
5104 */
5105 if (info->bpc == 0 && edid->revision == 3 &&
5106 edid->input & DRM_EDID_DIGITAL_DFP_1_X) {
5107 info->bpc = 8;
5108 DRM_DEBUG("%s: Assigning DFP sink color depth as %d bpc.\n",
5109 connector->name, info->bpc);
5110 }
5111
5112 /* Only defined for 1.4 with digital displays */
5113 if (edid->revision < 4)
5114 return quirks;
5115
5116 switch (edid->input & DRM_EDID_DIGITAL_DEPTH_MASK) {
5117 case DRM_EDID_DIGITAL_DEPTH_6:
5118 info->bpc = 6;
5119 break;
5120 case DRM_EDID_DIGITAL_DEPTH_8:
5121 info->bpc = 8;
5122 break;
5123 case DRM_EDID_DIGITAL_DEPTH_10:
5124 info->bpc = 10;
5125 break;
5126 case DRM_EDID_DIGITAL_DEPTH_12:
5127 info->bpc = 12;
5128 break;
5129 case DRM_EDID_DIGITAL_DEPTH_14:
5130 info->bpc = 14;
5131 break;
5132 case DRM_EDID_DIGITAL_DEPTH_16:
5133 info->bpc = 16;
5134 break;
5135 case DRM_EDID_DIGITAL_DEPTH_UNDEF:
5136 default:
5137 info->bpc = 0;
5138 break;
5139 }
5140
5141 DRM_DEBUG("%s: Assigning EDID-1.4 digital sink color depth as %d bpc.\n",
5142 connector->name, info->bpc);
5143
5144 info->color_formats |= DRM_COLOR_FORMAT_RGB444;
5145 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB444)
5146 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444;
5147 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB422)
5148 info->color_formats |= DRM_COLOR_FORMAT_YCRCB422;
5149 return quirks;
5150}
5151
5152static int validate_displayid(u8 *displayid, int length, int idx)
5153{
5154 int i, dispid_length;
5155 u8 csum = 0;
5156 struct displayid_hdr *base;
5157
5158 base = (struct displayid_hdr *)&displayid[idx];
5159
5160 DRM_DEBUG_KMS("base revision 0x%x, length %d, %d %d\n",
5161 base->rev, base->bytes, base->prod_id, base->ext_count);
5162
5163 /* +1 for DispID checksum */
5164 dispid_length = sizeof(*base) + base->bytes + 1;
5165 if (dispid_length > length - idx)
5166 return -EINVAL;
5167
5168 for (i = 0; i < dispid_length; i++)
5169 csum += displayid[idx + i];
5170 if (csum) {
5171 DRM_NOTE("DisplayID checksum invalid, remainder is %d\n", csum);
5172 return -EINVAL;
5173 }
5174
5175 return 0;
5176}
5177
5178static struct drm_display_mode *drm_mode_displayid_detailed(struct drm_device *dev,
5179 struct displayid_detailed_timings_1 *timings)
5180{
5181 struct drm_display_mode *mode;
5182 unsigned pixel_clock = (timings->pixel_clock[0] |
5183 (timings->pixel_clock[1] << 8) |
5184 (timings->pixel_clock[2] << 16)) + 1;
5185 unsigned hactive = (timings->hactive[0] | timings->hactive[1] << 8) + 1;
5186 unsigned hblank = (timings->hblank[0] | timings->hblank[1] << 8) + 1;
5187 unsigned hsync = (timings->hsync[0] | (timings->hsync[1] & 0x7f) << 8) + 1;
5188 unsigned hsync_width = (timings->hsw[0] | timings->hsw[1] << 8) + 1;
5189 unsigned vactive = (timings->vactive[0] | timings->vactive[1] << 8) + 1;
5190 unsigned vblank = (timings->vblank[0] | timings->vblank[1] << 8) + 1;
5191 unsigned vsync = (timings->vsync[0] | (timings->vsync[1] & 0x7f) << 8) + 1;
5192 unsigned vsync_width = (timings->vsw[0] | timings->vsw[1] << 8) + 1;
5193 bool hsync_positive = (timings->hsync[1] >> 7) & 0x1;
5194 bool vsync_positive = (timings->vsync[1] >> 7) & 0x1;
5195
5196 mode = drm_mode_create(dev);
5197 if (!mode)
5198 return NULL;
5199
5200 mode->clock = pixel_clock * 10;
5201 mode->hdisplay = hactive;
5202 mode->hsync_start = mode->hdisplay + hsync;
5203 mode->hsync_end = mode->hsync_start + hsync_width;
5204 mode->htotal = mode->hdisplay + hblank;
5205
5206 mode->vdisplay = vactive;
5207 mode->vsync_start = mode->vdisplay + vsync;
5208 mode->vsync_end = mode->vsync_start + vsync_width;
5209 mode->vtotal = mode->vdisplay + vblank;
5210
5211 mode->flags = 0;
5212 mode->flags |= hsync_positive ? DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC;
5213 mode->flags |= vsync_positive ? DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC;
5214 mode->type = DRM_MODE_TYPE_DRIVER;
5215
5216 if (timings->flags & 0x80)
5217 mode->type |= DRM_MODE_TYPE_PREFERRED;
5218 drm_mode_set_name(mode);
5219
5220 return mode;
5221}
5222
5223static int add_displayid_detailed_1_modes(struct drm_connector *connector,
5224 struct displayid_block *block)
5225{
5226 struct displayid_detailed_timing_block *det = (struct displayid_detailed_timing_block *)block;
5227 int i;
5228 int num_timings;
5229 struct drm_display_mode *newmode;
5230 int num_modes = 0;
5231 /* blocks must be multiple of 20 bytes length */
5232 if (block->num_bytes % 20)
5233 return 0;
5234
5235 num_timings = block->num_bytes / 20;
5236 for (i = 0; i < num_timings; i++) {
5237 struct displayid_detailed_timings_1 *timings = &det->timings[i];
5238
5239 newmode = drm_mode_displayid_detailed(connector->dev, timings);
5240 if (!newmode)
5241 continue;
5242
5243 drm_mode_probed_add(connector, newmode);
5244 num_modes++;
5245 }
5246 return num_modes;
5247}
5248
5249static int add_displayid_detailed_modes(struct drm_connector *connector,
5250 struct edid *edid)
5251{
5252 u8 *displayid;
5253 int length, idx;
5254 struct displayid_block *block;
5255 int num_modes = 0;
5256 int ext_index = 0;
5257
5258 for (;;) {
5259 displayid = drm_find_displayid_extension(edid, &length, &idx,
5260 &ext_index);
5261 if (!displayid)
5262 break;
5263
5264 idx += sizeof(struct displayid_hdr);
5265 for_each_displayid_db(displayid, block, idx, length) {
5266 switch (block->tag) {
5267 case DATA_BLOCK_TYPE_1_DETAILED_TIMING:
5268 num_modes += add_displayid_detailed_1_modes(connector, block);
5269 break;
5270 }
5271 }
5272 }
5273
5274 return num_modes;
5275}
5276
5277/**
5278 * drm_add_edid_modes - add modes from EDID data, if available
5279 * @connector: connector we're probing
5280 * @edid: EDID data
5281 *
5282 * Add the specified modes to the connector's mode list. Also fills out the
5283 * &drm_display_info structure and ELD in @connector with any information which
5284 * can be derived from the edid.
5285 *
5286 * Return: The number of modes added or 0 if we couldn't find any.
5287 */
5288int drm_add_edid_modes(struct drm_connector *connector, struct edid *edid)
5289{
5290 int num_modes = 0;
5291 u32 quirks;
5292
5293 if (edid == NULL) {
5294 clear_eld(connector);
5295 return 0;
5296 }
5297 if (!drm_edid_is_valid(edid)) {
5298 clear_eld(connector);
5299 drm_warn(connector->dev, "%s: EDID invalid.\n",
5300 connector->name);
5301 return 0;
5302 }
5303
5304 drm_edid_to_eld(connector, edid);
5305
5306 /*
5307 * CEA-861-F adds ycbcr capability map block, for HDMI 2.0 sinks.
5308 * To avoid multiple parsing of same block, lets parse that map
5309 * from sink info, before parsing CEA modes.
5310 */
5311 quirks = drm_add_display_info(connector, edid);
5312
5313 /*
5314 * EDID spec says modes should be preferred in this order:
5315 * - preferred detailed mode
5316 * - other detailed modes from base block
5317 * - detailed modes from extension blocks
5318 * - CVT 3-byte code modes
5319 * - standard timing codes
5320 * - established timing codes
5321 * - modes inferred from GTF or CVT range information
5322 *
5323 * We get this pretty much right.
5324 *
5325 * XXX order for additional mode types in extension blocks?
5326 */
5327 num_modes += add_detailed_modes(connector, edid, quirks);
5328 num_modes += add_cvt_modes(connector, edid);
5329 num_modes += add_standard_modes(connector, edid);
5330 num_modes += add_established_modes(connector, edid);
5331 num_modes += add_cea_modes(connector, edid);
5332 num_modes += add_alternate_cea_modes(connector, edid);
5333 num_modes += add_displayid_detailed_modes(connector, edid);
5334 if (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF)
5335 num_modes += add_inferred_modes(connector, edid);
5336
5337 if (quirks & (EDID_QUIRK_PREFER_LARGE_60 | EDID_QUIRK_PREFER_LARGE_75))
5338 edid_fixup_preferred(connector, quirks);
5339
5340 if (quirks & EDID_QUIRK_FORCE_6BPC)
5341 connector->display_info.bpc = 6;
5342
5343 if (quirks & EDID_QUIRK_FORCE_8BPC)
5344 connector->display_info.bpc = 8;
5345
5346 if (quirks & EDID_QUIRK_FORCE_10BPC)
5347 connector->display_info.bpc = 10;
5348
5349 if (quirks & EDID_QUIRK_FORCE_12BPC)
5350 connector->display_info.bpc = 12;
5351
5352 return num_modes;
5353}
5354EXPORT_SYMBOL(drm_add_edid_modes);
5355
5356/**
5357 * drm_add_modes_noedid - add modes for the connectors without EDID
5358 * @connector: connector we're probing
5359 * @hdisplay: the horizontal display limit
5360 * @vdisplay: the vertical display limit
5361 *
5362 * Add the specified modes to the connector's mode list. Only when the
5363 * hdisplay/vdisplay is not beyond the given limit, it will be added.
5364 *
5365 * Return: The number of modes added or 0 if we couldn't find any.
5366 */
5367int drm_add_modes_noedid(struct drm_connector *connector,
5368 int hdisplay, int vdisplay)
5369{
5370 int i, count, num_modes = 0;
5371 struct drm_display_mode *mode;
5372 struct drm_device *dev = connector->dev;
5373
5374 count = ARRAY_SIZE(drm_dmt_modes);
5375 if (hdisplay < 0)
5376 hdisplay = 0;
5377 if (vdisplay < 0)
5378 vdisplay = 0;
5379
5380 for (i = 0; i < count; i++) {
5381 const struct drm_display_mode *ptr = &drm_dmt_modes[i];
5382
5383 if (hdisplay && vdisplay) {
5384 /*
5385 * Only when two are valid, they will be used to check
5386 * whether the mode should be added to the mode list of
5387 * the connector.
5388 */
5389 if (ptr->hdisplay > hdisplay ||
5390 ptr->vdisplay > vdisplay)
5391 continue;
5392 }
5393 if (drm_mode_vrefresh(ptr) > 61)
5394 continue;
5395 mode = drm_mode_duplicate(dev, ptr);
5396 if (mode) {
5397 drm_mode_probed_add(connector, mode);
5398 num_modes++;
5399 }
5400 }
5401 return num_modes;
5402}
5403EXPORT_SYMBOL(drm_add_modes_noedid);
5404
5405/**
5406 * drm_set_preferred_mode - Sets the preferred mode of a connector
5407 * @connector: connector whose mode list should be processed
5408 * @hpref: horizontal resolution of preferred mode
5409 * @vpref: vertical resolution of preferred mode
5410 *
5411 * Marks a mode as preferred if it matches the resolution specified by @hpref
5412 * and @vpref.
5413 */
5414void drm_set_preferred_mode(struct drm_connector *connector,
5415 int hpref, int vpref)
5416{
5417 struct drm_display_mode *mode;
5418
5419 list_for_each_entry(mode, &connector->probed_modes, head) {
5420 if (mode->hdisplay == hpref &&
5421 mode->vdisplay == vpref)
5422 mode->type |= DRM_MODE_TYPE_PREFERRED;
5423 }
5424}
5425EXPORT_SYMBOL(drm_set_preferred_mode);
5426
5427static bool is_hdmi2_sink(const struct drm_connector *connector)
5428{
5429 /*
5430 * FIXME: sil-sii8620 doesn't have a connector around when
5431 * we need one, so we have to be prepared for a NULL connector.
5432 */
5433 if (!connector)
5434 return true;
5435
5436 return connector->display_info.hdmi.scdc.supported ||
5437 connector->display_info.color_formats & DRM_COLOR_FORMAT_YCRCB420;
5438}
5439
5440static inline bool is_eotf_supported(u8 output_eotf, u8 sink_eotf)
5441{
5442 return sink_eotf & BIT(output_eotf);
5443}
5444
5445/**
5446 * drm_hdmi_infoframe_set_hdr_metadata() - fill an HDMI DRM infoframe with
5447 * HDR metadata from userspace
5448 * @frame: HDMI DRM infoframe
5449 * @conn_state: Connector state containing HDR metadata
5450 *
5451 * Return: 0 on success or a negative error code on failure.
5452 */
5453int
5454drm_hdmi_infoframe_set_hdr_metadata(struct hdmi_drm_infoframe *frame,
5455 const struct drm_connector_state *conn_state)
5456{
5457 struct drm_connector *connector;
5458 struct hdr_output_metadata *hdr_metadata;
5459 int err;
5460
5461 if (!frame || !conn_state)
5462 return -EINVAL;
5463
5464 connector = conn_state->connector;
5465
5466 if (!conn_state->hdr_output_metadata)
5467 return -EINVAL;
5468
5469 hdr_metadata = conn_state->hdr_output_metadata->data;
5470
5471 if (!hdr_metadata || !connector)
5472 return -EINVAL;
5473
5474 /* Sink EOTF is Bit map while infoframe is absolute values */
5475 if (!is_eotf_supported(hdr_metadata->hdmi_metadata_type1.eotf,
5476 connector->hdr_sink_metadata.hdmi_type1.eotf)) {
5477 DRM_DEBUG_KMS("EOTF Not Supported\n");
5478 return -EINVAL;
5479 }
5480
5481 err = hdmi_drm_infoframe_init(frame);
5482 if (err < 0)
5483 return err;
5484
5485 frame->eotf = hdr_metadata->hdmi_metadata_type1.eotf;
5486 frame->metadata_type = hdr_metadata->hdmi_metadata_type1.metadata_type;
5487
5488 BUILD_BUG_ON(sizeof(frame->display_primaries) !=
5489 sizeof(hdr_metadata->hdmi_metadata_type1.display_primaries));
5490 BUILD_BUG_ON(sizeof(frame->white_point) !=
5491 sizeof(hdr_metadata->hdmi_metadata_type1.white_point));
5492
5493 memcpy(&frame->display_primaries,
5494 &hdr_metadata->hdmi_metadata_type1.display_primaries,
5495 sizeof(frame->display_primaries));
5496
5497 memcpy(&frame->white_point,
5498 &hdr_metadata->hdmi_metadata_type1.white_point,
5499 sizeof(frame->white_point));
5500
5501 frame->max_display_mastering_luminance =
5502 hdr_metadata->hdmi_metadata_type1.max_display_mastering_luminance;
5503 frame->min_display_mastering_luminance =
5504 hdr_metadata->hdmi_metadata_type1.min_display_mastering_luminance;
5505 frame->max_fall = hdr_metadata->hdmi_metadata_type1.max_fall;
5506 frame->max_cll = hdr_metadata->hdmi_metadata_type1.max_cll;
5507
5508 return 0;
5509}
5510EXPORT_SYMBOL(drm_hdmi_infoframe_set_hdr_metadata);
5511
5512static u8 drm_mode_hdmi_vic(const struct drm_connector *connector,
5513 const struct drm_display_mode *mode)
5514{
5515 bool has_hdmi_infoframe = connector ?
5516 connector->display_info.has_hdmi_infoframe : false;
5517
5518 if (!has_hdmi_infoframe)
5519 return 0;
5520
5521 /* No HDMI VIC when signalling 3D video format */
5522 if (mode->flags & DRM_MODE_FLAG_3D_MASK)
5523 return 0;
5524
5525 return drm_match_hdmi_mode(mode);
5526}
5527
5528static u8 drm_mode_cea_vic(const struct drm_connector *connector,
5529 const struct drm_display_mode *mode)
5530{
5531 u8 vic;
5532
5533 /*
5534 * HDMI spec says if a mode is found in HDMI 1.4b 4K modes
5535 * we should send its VIC in vendor infoframes, else send the
5536 * VIC in AVI infoframes. Lets check if this mode is present in
5537 * HDMI 1.4b 4K modes
5538 */
5539 if (drm_mode_hdmi_vic(connector, mode))
5540 return 0;
5541
5542 vic = drm_match_cea_mode(mode);
5543
5544 /*
5545 * HDMI 1.4 VIC range: 1 <= VIC <= 64 (CEA-861-D) but
5546 * HDMI 2.0 VIC range: 1 <= VIC <= 107 (CEA-861-F). So we
5547 * have to make sure we dont break HDMI 1.4 sinks.
5548 */
5549 if (!is_hdmi2_sink(connector) && vic > 64)
5550 return 0;
5551
5552 return vic;
5553}
5554
5555/**
5556 * drm_hdmi_avi_infoframe_from_display_mode() - fill an HDMI AVI infoframe with
5557 * data from a DRM display mode
5558 * @frame: HDMI AVI infoframe
5559 * @connector: the connector
5560 * @mode: DRM display mode
5561 *
5562 * Return: 0 on success or a negative error code on failure.
5563 */
5564int
5565drm_hdmi_avi_infoframe_from_display_mode(struct hdmi_avi_infoframe *frame,
5566 const struct drm_connector *connector,
5567 const struct drm_display_mode *mode)
5568{
5569 enum hdmi_picture_aspect picture_aspect;
5570 u8 vic, hdmi_vic;
5571
5572 if (!frame || !mode)
5573 return -EINVAL;
5574
5575 hdmi_avi_infoframe_init(frame);
5576
5577 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
5578 frame->pixel_repeat = 1;
5579
5580 vic = drm_mode_cea_vic(connector, mode);
5581 hdmi_vic = drm_mode_hdmi_vic(connector, mode);
5582
5583 frame->picture_aspect = HDMI_PICTURE_ASPECT_NONE;
5584
5585 /*
5586 * As some drivers don't support atomic, we can't use connector state.
5587 * So just initialize the frame with default values, just the same way
5588 * as it's done with other properties here.
5589 */
5590 frame->content_type = HDMI_CONTENT_TYPE_GRAPHICS;
5591 frame->itc = 0;
5592
5593 /*
5594 * Populate picture aspect ratio from either
5595 * user input (if specified) or from the CEA/HDMI mode lists.
5596 */
5597 picture_aspect = mode->picture_aspect_ratio;
5598 if (picture_aspect == HDMI_PICTURE_ASPECT_NONE) {
5599 if (vic)
5600 picture_aspect = drm_get_cea_aspect_ratio(vic);
5601 else if (hdmi_vic)
5602 picture_aspect = drm_get_hdmi_aspect_ratio(hdmi_vic);
5603 }
5604
5605 /*
5606 * The infoframe can't convey anything but none, 4:3
5607 * and 16:9, so if the user has asked for anything else
5608 * we can only satisfy it by specifying the right VIC.
5609 */
5610 if (picture_aspect > HDMI_PICTURE_ASPECT_16_9) {
5611 if (vic) {
5612 if (picture_aspect != drm_get_cea_aspect_ratio(vic))
5613 return -EINVAL;
5614 } else if (hdmi_vic) {
5615 if (picture_aspect != drm_get_hdmi_aspect_ratio(hdmi_vic))
5616 return -EINVAL;
5617 } else {
5618 return -EINVAL;
5619 }
5620
5621 picture_aspect = HDMI_PICTURE_ASPECT_NONE;
5622 }
5623
5624 frame->video_code = vic;
5625 frame->picture_aspect = picture_aspect;
5626 frame->active_aspect = HDMI_ACTIVE_ASPECT_PICTURE;
5627 frame->scan_mode = HDMI_SCAN_MODE_UNDERSCAN;
5628
5629 return 0;
5630}
5631EXPORT_SYMBOL(drm_hdmi_avi_infoframe_from_display_mode);
5632
5633/* HDMI Colorspace Spec Definitions */
5634#define FULL_COLORIMETRY_MASK 0x1FF
5635#define NORMAL_COLORIMETRY_MASK 0x3
5636#define EXTENDED_COLORIMETRY_MASK 0x7
5637#define EXTENDED_ACE_COLORIMETRY_MASK 0xF
5638
5639#define C(x) ((x) << 0)
5640#define EC(x) ((x) << 2)
5641#define ACE(x) ((x) << 5)
5642
5643#define HDMI_COLORIMETRY_NO_DATA 0x0
5644#define HDMI_COLORIMETRY_SMPTE_170M_YCC (C(1) | EC(0) | ACE(0))
5645#define HDMI_COLORIMETRY_BT709_YCC (C(2) | EC(0) | ACE(0))
5646#define HDMI_COLORIMETRY_XVYCC_601 (C(3) | EC(0) | ACE(0))
5647#define HDMI_COLORIMETRY_XVYCC_709 (C(3) | EC(1) | ACE(0))
5648#define HDMI_COLORIMETRY_SYCC_601 (C(3) | EC(2) | ACE(0))
5649#define HDMI_COLORIMETRY_OPYCC_601 (C(3) | EC(3) | ACE(0))
5650#define HDMI_COLORIMETRY_OPRGB (C(3) | EC(4) | ACE(0))
5651#define HDMI_COLORIMETRY_BT2020_CYCC (C(3) | EC(5) | ACE(0))
5652#define HDMI_COLORIMETRY_BT2020_RGB (C(3) | EC(6) | ACE(0))
5653#define HDMI_COLORIMETRY_BT2020_YCC (C(3) | EC(6) | ACE(0))
5654#define HDMI_COLORIMETRY_DCI_P3_RGB_D65 (C(3) | EC(7) | ACE(0))
5655#define HDMI_COLORIMETRY_DCI_P3_RGB_THEATER (C(3) | EC(7) | ACE(1))
5656
5657static const u32 hdmi_colorimetry_val[] = {
5658 [DRM_MODE_COLORIMETRY_NO_DATA] = HDMI_COLORIMETRY_NO_DATA,
5659 [DRM_MODE_COLORIMETRY_SMPTE_170M_YCC] = HDMI_COLORIMETRY_SMPTE_170M_YCC,
5660 [DRM_MODE_COLORIMETRY_BT709_YCC] = HDMI_COLORIMETRY_BT709_YCC,
5661 [DRM_MODE_COLORIMETRY_XVYCC_601] = HDMI_COLORIMETRY_XVYCC_601,
5662 [DRM_MODE_COLORIMETRY_XVYCC_709] = HDMI_COLORIMETRY_XVYCC_709,
5663 [DRM_MODE_COLORIMETRY_SYCC_601] = HDMI_COLORIMETRY_SYCC_601,
5664 [DRM_MODE_COLORIMETRY_OPYCC_601] = HDMI_COLORIMETRY_OPYCC_601,
5665 [DRM_MODE_COLORIMETRY_OPRGB] = HDMI_COLORIMETRY_OPRGB,
5666 [DRM_MODE_COLORIMETRY_BT2020_CYCC] = HDMI_COLORIMETRY_BT2020_CYCC,
5667 [DRM_MODE_COLORIMETRY_BT2020_RGB] = HDMI_COLORIMETRY_BT2020_RGB,
5668 [DRM_MODE_COLORIMETRY_BT2020_YCC] = HDMI_COLORIMETRY_BT2020_YCC,
5669};
5670
5671#undef C
5672#undef EC
5673#undef ACE
5674
5675/**
5676 * drm_hdmi_avi_infoframe_colorspace() - fill the HDMI AVI infoframe
5677 * colorspace information
5678 * @frame: HDMI AVI infoframe
5679 * @conn_state: connector state
5680 */
5681void
5682drm_hdmi_avi_infoframe_colorspace(struct hdmi_avi_infoframe *frame,
5683 const struct drm_connector_state *conn_state)
5684{
5685 u32 colorimetry_val;
5686 u32 colorimetry_index = conn_state->colorspace & FULL_COLORIMETRY_MASK;
5687
5688 if (colorimetry_index >= ARRAY_SIZE(hdmi_colorimetry_val))
5689 colorimetry_val = HDMI_COLORIMETRY_NO_DATA;
5690 else
5691 colorimetry_val = hdmi_colorimetry_val[colorimetry_index];
5692
5693 frame->colorimetry = colorimetry_val & NORMAL_COLORIMETRY_MASK;
5694 /*
5695 * ToDo: Extend it for ACE formats as well. Modify the infoframe
5696 * structure and extend it in drivers/video/hdmi
5697 */
5698 frame->extended_colorimetry = (colorimetry_val >> 2) &
5699 EXTENDED_COLORIMETRY_MASK;
5700}
5701EXPORT_SYMBOL(drm_hdmi_avi_infoframe_colorspace);
5702
5703/**
5704 * drm_hdmi_avi_infoframe_quant_range() - fill the HDMI AVI infoframe
5705 * quantization range information
5706 * @frame: HDMI AVI infoframe
5707 * @connector: the connector
5708 * @mode: DRM display mode
5709 * @rgb_quant_range: RGB quantization range (Q)
5710 */
5711void
5712drm_hdmi_avi_infoframe_quant_range(struct hdmi_avi_infoframe *frame,
5713 const struct drm_connector *connector,
5714 const struct drm_display_mode *mode,
5715 enum hdmi_quantization_range rgb_quant_range)
5716{
5717 const struct drm_display_info *info = &connector->display_info;
5718
5719 /*
5720 * CEA-861:
5721 * "A Source shall not send a non-zero Q value that does not correspond
5722 * to the default RGB Quantization Range for the transmitted Picture
5723 * unless the Sink indicates support for the Q bit in a Video
5724 * Capabilities Data Block."
5725 *
5726 * HDMI 2.0 recommends sending non-zero Q when it does match the
5727 * default RGB quantization range for the mode, even when QS=0.
5728 */
5729 if (info->rgb_quant_range_selectable ||
5730 rgb_quant_range == drm_default_rgb_quant_range(mode))
5731 frame->quantization_range = rgb_quant_range;
5732 else
5733 frame->quantization_range = HDMI_QUANTIZATION_RANGE_DEFAULT;
5734
5735 /*
5736 * CEA-861-F:
5737 * "When transmitting any RGB colorimetry, the Source should set the
5738 * YQ-field to match the RGB Quantization Range being transmitted
5739 * (e.g., when Limited Range RGB, set YQ=0 or when Full Range RGB,
5740 * set YQ=1) and the Sink shall ignore the YQ-field."
5741 *
5742 * Unfortunate certain sinks (eg. VIZ Model 67/E261VA) get confused
5743 * by non-zero YQ when receiving RGB. There doesn't seem to be any
5744 * good way to tell which version of CEA-861 the sink supports, so
5745 * we limit non-zero YQ to HDMI 2.0 sinks only as HDMI 2.0 is based
5746 * on on CEA-861-F.
5747 */
5748 if (!is_hdmi2_sink(connector) ||
5749 rgb_quant_range == HDMI_QUANTIZATION_RANGE_LIMITED)
5750 frame->ycc_quantization_range =
5751 HDMI_YCC_QUANTIZATION_RANGE_LIMITED;
5752 else
5753 frame->ycc_quantization_range =
5754 HDMI_YCC_QUANTIZATION_RANGE_FULL;
5755}
5756EXPORT_SYMBOL(drm_hdmi_avi_infoframe_quant_range);
5757
5758/**
5759 * drm_hdmi_avi_infoframe_bars() - fill the HDMI AVI infoframe
5760 * bar information
5761 * @frame: HDMI AVI infoframe
5762 * @conn_state: connector state
5763 */
5764void
5765drm_hdmi_avi_infoframe_bars(struct hdmi_avi_infoframe *frame,
5766 const struct drm_connector_state *conn_state)
5767{
5768 frame->right_bar = conn_state->tv.margins.right;
5769 frame->left_bar = conn_state->tv.margins.left;
5770 frame->top_bar = conn_state->tv.margins.top;
5771 frame->bottom_bar = conn_state->tv.margins.bottom;
5772}
5773EXPORT_SYMBOL(drm_hdmi_avi_infoframe_bars);
5774
5775static enum hdmi_3d_structure
5776s3d_structure_from_display_mode(const struct drm_display_mode *mode)
5777{
5778 u32 layout = mode->flags & DRM_MODE_FLAG_3D_MASK;
5779
5780 switch (layout) {
5781 case DRM_MODE_FLAG_3D_FRAME_PACKING:
5782 return HDMI_3D_STRUCTURE_FRAME_PACKING;
5783 case DRM_MODE_FLAG_3D_FIELD_ALTERNATIVE:
5784 return HDMI_3D_STRUCTURE_FIELD_ALTERNATIVE;
5785 case DRM_MODE_FLAG_3D_LINE_ALTERNATIVE:
5786 return HDMI_3D_STRUCTURE_LINE_ALTERNATIVE;
5787 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_FULL:
5788 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_FULL;
5789 case DRM_MODE_FLAG_3D_L_DEPTH:
5790 return HDMI_3D_STRUCTURE_L_DEPTH;
5791 case DRM_MODE_FLAG_3D_L_DEPTH_GFX_GFX_DEPTH:
5792 return HDMI_3D_STRUCTURE_L_DEPTH_GFX_GFX_DEPTH;
5793 case DRM_MODE_FLAG_3D_TOP_AND_BOTTOM:
5794 return HDMI_3D_STRUCTURE_TOP_AND_BOTTOM;
5795 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF:
5796 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_HALF;
5797 default:
5798 return HDMI_3D_STRUCTURE_INVALID;
5799 }
5800}
5801
5802/**
5803 * drm_hdmi_vendor_infoframe_from_display_mode() - fill an HDMI infoframe with
5804 * data from a DRM display mode
5805 * @frame: HDMI vendor infoframe
5806 * @connector: the connector
5807 * @mode: DRM display mode
5808 *
5809 * Note that there's is a need to send HDMI vendor infoframes only when using a
5810 * 4k or stereoscopic 3D mode. So when giving any other mode as input this
5811 * function will return -EINVAL, error that can be safely ignored.
5812 *
5813 * Return: 0 on success or a negative error code on failure.
5814 */
5815int
5816drm_hdmi_vendor_infoframe_from_display_mode(struct hdmi_vendor_infoframe *frame,
5817 const struct drm_connector *connector,
5818 const struct drm_display_mode *mode)
5819{
5820 /*
5821 * FIXME: sil-sii8620 doesn't have a connector around when
5822 * we need one, so we have to be prepared for a NULL connector.
5823 */
5824 bool has_hdmi_infoframe = connector ?
5825 connector->display_info.has_hdmi_infoframe : false;
5826 int err;
5827
5828 if (!frame || !mode)
5829 return -EINVAL;
5830
5831 if (!has_hdmi_infoframe)
5832 return -EINVAL;
5833
5834 err = hdmi_vendor_infoframe_init(frame);
5835 if (err < 0)
5836 return err;
5837
5838 /*
5839 * Even if it's not absolutely necessary to send the infoframe
5840 * (ie.vic==0 and s3d_struct==0) we will still send it if we
5841 * know that the sink can handle it. This is based on a
5842 * suggestion in HDMI 2.0 Appendix F. Apparently some sinks
5843 * have trouble realizing that they shuld switch from 3D to 2D
5844 * mode if the source simply stops sending the infoframe when
5845 * it wants to switch from 3D to 2D.
5846 */
5847 frame->vic = drm_mode_hdmi_vic(connector, mode);
5848 frame->s3d_struct = s3d_structure_from_display_mode(mode);
5849
5850 return 0;
5851}
5852EXPORT_SYMBOL(drm_hdmi_vendor_infoframe_from_display_mode);
5853
5854static void drm_parse_tiled_block(struct drm_connector *connector,
5855 const struct displayid_block *block)
5856{
5857 const struct displayid_tiled_block *tile = (struct displayid_tiled_block *)block;
5858 u16 w, h;
5859 u8 tile_v_loc, tile_h_loc;
5860 u8 num_v_tile, num_h_tile;
5861 struct drm_tile_group *tg;
5862
5863 w = tile->tile_size[0] | tile->tile_size[1] << 8;
5864 h = tile->tile_size[2] | tile->tile_size[3] << 8;
5865
5866 num_v_tile = (tile->topo[0] & 0xf) | (tile->topo[2] & 0x30);
5867 num_h_tile = (tile->topo[0] >> 4) | ((tile->topo[2] >> 2) & 0x30);
5868 tile_v_loc = (tile->topo[1] & 0xf) | ((tile->topo[2] & 0x3) << 4);
5869 tile_h_loc = (tile->topo[1] >> 4) | (((tile->topo[2] >> 2) & 0x3) << 4);
5870
5871 connector->has_tile = true;
5872 if (tile->tile_cap & 0x80)
5873 connector->tile_is_single_monitor = true;
5874
5875 connector->num_h_tile = num_h_tile + 1;
5876 connector->num_v_tile = num_v_tile + 1;
5877 connector->tile_h_loc = tile_h_loc;
5878 connector->tile_v_loc = tile_v_loc;
5879 connector->tile_h_size = w + 1;
5880 connector->tile_v_size = h + 1;
5881
5882 DRM_DEBUG_KMS("tile cap 0x%x\n", tile->tile_cap);
5883 DRM_DEBUG_KMS("tile_size %d x %d\n", w + 1, h + 1);
5884 DRM_DEBUG_KMS("topo num tiles %dx%d, location %dx%d\n",
5885 num_h_tile + 1, num_v_tile + 1, tile_h_loc, tile_v_loc);
5886 DRM_DEBUG_KMS("vend %c%c%c\n", tile->topology_id[0], tile->topology_id[1], tile->topology_id[2]);
5887
5888 tg = drm_mode_get_tile_group(connector->dev, tile->topology_id);
5889 if (!tg)
5890 tg = drm_mode_create_tile_group(connector->dev, tile->topology_id);
5891 if (!tg)
5892 return;
5893
5894 if (connector->tile_group != tg) {
5895 /* if we haven't got a pointer,
5896 take the reference, drop ref to old tile group */
5897 if (connector->tile_group)
5898 drm_mode_put_tile_group(connector->dev, connector->tile_group);
5899 connector->tile_group = tg;
5900 } else {
5901 /* if same tile group, then release the ref we just took. */
5902 drm_mode_put_tile_group(connector->dev, tg);
5903 }
5904}
5905
5906static void drm_displayid_parse_tiled(struct drm_connector *connector,
5907 const u8 *displayid, int length, int idx)
5908{
5909 const struct displayid_block *block;
5910
5911 idx += sizeof(struct displayid_hdr);
5912 for_each_displayid_db(displayid, block, idx, length) {
5913 DRM_DEBUG_KMS("block id 0x%x, rev %d, len %d\n",
5914 block->tag, block->rev, block->num_bytes);
5915
5916 switch (block->tag) {
5917 case DATA_BLOCK_TILED_DISPLAY:
5918 drm_parse_tiled_block(connector, block);
5919 break;
5920 default:
5921 DRM_DEBUG_KMS("found DisplayID tag 0x%x, unhandled\n", block->tag);
5922 break;
5923 }
5924 }
5925}
5926
5927void drm_update_tile_info(struct drm_connector *connector,
5928 const struct edid *edid)
5929{
5930 const void *displayid = NULL;
5931 int ext_index = 0;
5932 int length, idx;
5933
5934 connector->has_tile = false;
5935 for (;;) {
5936 displayid = drm_find_displayid_extension(edid, &length, &idx,
5937 &ext_index);
5938 if (!displayid)
5939 break;
5940
5941 drm_displayid_parse_tiled(connector, displayid, length, idx);
5942 }
5943
5944 if (!connector->has_tile && connector->tile_group) {
5945 drm_mode_put_tile_group(connector->dev, connector->tile_group);
5946 connector->tile_group = NULL;
5947 }
5948}
1/*
2 * Copyright (c) 2006 Luc Verhaegen (quirks list)
3 * Copyright (c) 2007-2008 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
5 * Copyright 2010 Red Hat, Inc.
6 *
7 * DDC probing routines (drm_ddc_read & drm_do_probe_ddc_edid) originally from
8 * FB layer.
9 * Copyright (C) 2006 Dennis Munsie <dmunsie@cecropia.com>
10 *
11 * Permission is hereby granted, free of charge, to any person obtaining a
12 * copy of this software and associated documentation files (the "Software"),
13 * to deal in the Software without restriction, including without limitation
14 * the rights to use, copy, modify, merge, publish, distribute, sub license,
15 * and/or sell copies of the Software, and to permit persons to whom the
16 * Software is furnished to do so, subject to the following conditions:
17 *
18 * The above copyright notice and this permission notice (including the
19 * next paragraph) shall be included in all copies or substantial portions
20 * of the Software.
21 *
22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
23 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
24 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
25 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
26 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
27 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
28 * DEALINGS IN THE SOFTWARE.
29 */
30
31#include <linux/bitfield.h>
32#include <linux/cec.h>
33#include <linux/hdmi.h>
34#include <linux/i2c.h>
35#include <linux/kernel.h>
36#include <linux/module.h>
37#include <linux/pci.h>
38#include <linux/slab.h>
39#include <linux/vga_switcheroo.h>
40
41#include <drm/drm_displayid.h>
42#include <drm/drm_drv.h>
43#include <drm/drm_edid.h>
44#include <drm/drm_eld.h>
45#include <drm/drm_encoder.h>
46#include <drm/drm_print.h>
47
48#include "drm_crtc_internal.h"
49#include "drm_internal.h"
50
51static int oui(u8 first, u8 second, u8 third)
52{
53 return (first << 16) | (second << 8) | third;
54}
55
56#define EDID_EST_TIMINGS 16
57#define EDID_STD_TIMINGS 8
58#define EDID_DETAILED_TIMINGS 4
59
60/*
61 * EDID blocks out in the wild have a variety of bugs, try to collect
62 * them here (note that userspace may work around broken monitors first,
63 * but fixes should make their way here so that the kernel "just works"
64 * on as many displays as possible).
65 */
66
67/* First detailed mode wrong, use largest 60Hz mode */
68#define EDID_QUIRK_PREFER_LARGE_60 (1 << 0)
69/* Reported 135MHz pixel clock is too high, needs adjustment */
70#define EDID_QUIRK_135_CLOCK_TOO_HIGH (1 << 1)
71/* Prefer the largest mode at 75 Hz */
72#define EDID_QUIRK_PREFER_LARGE_75 (1 << 2)
73/* Detail timing is in cm not mm */
74#define EDID_QUIRK_DETAILED_IN_CM (1 << 3)
75/* Detailed timing descriptors have bogus size values, so just take the
76 * maximum size and use that.
77 */
78#define EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE (1 << 4)
79/* use +hsync +vsync for detailed mode */
80#define EDID_QUIRK_DETAILED_SYNC_PP (1 << 6)
81/* Force reduced-blanking timings for detailed modes */
82#define EDID_QUIRK_FORCE_REDUCED_BLANKING (1 << 7)
83/* Force 8bpc */
84#define EDID_QUIRK_FORCE_8BPC (1 << 8)
85/* Force 12bpc */
86#define EDID_QUIRK_FORCE_12BPC (1 << 9)
87/* Force 6bpc */
88#define EDID_QUIRK_FORCE_6BPC (1 << 10)
89/* Force 10bpc */
90#define EDID_QUIRK_FORCE_10BPC (1 << 11)
91/* Non desktop display (i.e. HMD) */
92#define EDID_QUIRK_NON_DESKTOP (1 << 12)
93/* Cap the DSC target bitrate to 15bpp */
94#define EDID_QUIRK_CAP_DSC_15BPP (1 << 13)
95
96#define MICROSOFT_IEEE_OUI 0xca125c
97
98struct detailed_mode_closure {
99 struct drm_connector *connector;
100 const struct drm_edid *drm_edid;
101 bool preferred;
102 int modes;
103};
104
105#define LEVEL_DMT 0
106#define LEVEL_GTF 1
107#define LEVEL_GTF2 2
108#define LEVEL_CVT 3
109
110#define EDID_QUIRK(vend_chr_0, vend_chr_1, vend_chr_2, product_id, _quirks) \
111{ \
112 .panel_id = drm_edid_encode_panel_id(vend_chr_0, vend_chr_1, vend_chr_2, \
113 product_id), \
114 .quirks = _quirks \
115}
116
117static const struct edid_quirk {
118 u32 panel_id;
119 u32 quirks;
120} edid_quirk_list[] = {
121 /* Acer AL1706 */
122 EDID_QUIRK('A', 'C', 'R', 44358, EDID_QUIRK_PREFER_LARGE_60),
123 /* Acer F51 */
124 EDID_QUIRK('A', 'P', 'I', 0x7602, EDID_QUIRK_PREFER_LARGE_60),
125
126 /* AEO model 0 reports 8 bpc, but is a 6 bpc panel */
127 EDID_QUIRK('A', 'E', 'O', 0, EDID_QUIRK_FORCE_6BPC),
128
129 /* BenQ GW2765 */
130 EDID_QUIRK('B', 'N', 'Q', 0x78d6, EDID_QUIRK_FORCE_8BPC),
131
132 /* BOE model on HP Pavilion 15-n233sl reports 8 bpc, but is a 6 bpc panel */
133 EDID_QUIRK('B', 'O', 'E', 0x78b, EDID_QUIRK_FORCE_6BPC),
134
135 /* CPT panel of Asus UX303LA reports 8 bpc, but is a 6 bpc panel */
136 EDID_QUIRK('C', 'P', 'T', 0x17df, EDID_QUIRK_FORCE_6BPC),
137
138 /* SDC panel of Lenovo B50-80 reports 8 bpc, but is a 6 bpc panel */
139 EDID_QUIRK('S', 'D', 'C', 0x3652, EDID_QUIRK_FORCE_6BPC),
140
141 /* BOE model 0x0771 reports 8 bpc, but is a 6 bpc panel */
142 EDID_QUIRK('B', 'O', 'E', 0x0771, EDID_QUIRK_FORCE_6BPC),
143
144 /* Belinea 10 15 55 */
145 EDID_QUIRK('M', 'A', 'X', 1516, EDID_QUIRK_PREFER_LARGE_60),
146 EDID_QUIRK('M', 'A', 'X', 0x77e, EDID_QUIRK_PREFER_LARGE_60),
147
148 /* Envision Peripherals, Inc. EN-7100e */
149 EDID_QUIRK('E', 'P', 'I', 59264, EDID_QUIRK_135_CLOCK_TOO_HIGH),
150 /* Envision EN2028 */
151 EDID_QUIRK('E', 'P', 'I', 8232, EDID_QUIRK_PREFER_LARGE_60),
152
153 /* Funai Electronics PM36B */
154 EDID_QUIRK('F', 'C', 'M', 13600, EDID_QUIRK_PREFER_LARGE_75 |
155 EDID_QUIRK_DETAILED_IN_CM),
156
157 /* LG 27GP950 */
158 EDID_QUIRK('G', 'S', 'M', 0x5bbf, EDID_QUIRK_CAP_DSC_15BPP),
159
160 /* LG 27GN950 */
161 EDID_QUIRK('G', 'S', 'M', 0x5b9a, EDID_QUIRK_CAP_DSC_15BPP),
162
163 /* LGD panel of HP zBook 17 G2, eDP 10 bpc, but reports unknown bpc */
164 EDID_QUIRK('L', 'G', 'D', 764, EDID_QUIRK_FORCE_10BPC),
165
166 /* LG Philips LCD LP154W01-A5 */
167 EDID_QUIRK('L', 'P', 'L', 0, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE),
168 EDID_QUIRK('L', 'P', 'L', 0x2a00, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE),
169
170 /* Samsung SyncMaster 205BW. Note: irony */
171 EDID_QUIRK('S', 'A', 'M', 541, EDID_QUIRK_DETAILED_SYNC_PP),
172 /* Samsung SyncMaster 22[5-6]BW */
173 EDID_QUIRK('S', 'A', 'M', 596, EDID_QUIRK_PREFER_LARGE_60),
174 EDID_QUIRK('S', 'A', 'M', 638, EDID_QUIRK_PREFER_LARGE_60),
175
176 /* Sony PVM-2541A does up to 12 bpc, but only reports max 8 bpc */
177 EDID_QUIRK('S', 'N', 'Y', 0x2541, EDID_QUIRK_FORCE_12BPC),
178
179 /* ViewSonic VA2026w */
180 EDID_QUIRK('V', 'S', 'C', 5020, EDID_QUIRK_FORCE_REDUCED_BLANKING),
181
182 /* Medion MD 30217 PG */
183 EDID_QUIRK('M', 'E', 'D', 0x7b8, EDID_QUIRK_PREFER_LARGE_75),
184
185 /* Lenovo G50 */
186 EDID_QUIRK('S', 'D', 'C', 18514, EDID_QUIRK_FORCE_6BPC),
187
188 /* Panel in Samsung NP700G7A-S01PL notebook reports 6bpc */
189 EDID_QUIRK('S', 'E', 'C', 0xd033, EDID_QUIRK_FORCE_8BPC),
190
191 /* Rotel RSX-1058 forwards sink's EDID but only does HDMI 1.1*/
192 EDID_QUIRK('E', 'T', 'R', 13896, EDID_QUIRK_FORCE_8BPC),
193
194 /* Valve Index Headset */
195 EDID_QUIRK('V', 'L', 'V', 0x91a8, EDID_QUIRK_NON_DESKTOP),
196 EDID_QUIRK('V', 'L', 'V', 0x91b0, EDID_QUIRK_NON_DESKTOP),
197 EDID_QUIRK('V', 'L', 'V', 0x91b1, EDID_QUIRK_NON_DESKTOP),
198 EDID_QUIRK('V', 'L', 'V', 0x91b2, EDID_QUIRK_NON_DESKTOP),
199 EDID_QUIRK('V', 'L', 'V', 0x91b3, EDID_QUIRK_NON_DESKTOP),
200 EDID_QUIRK('V', 'L', 'V', 0x91b4, EDID_QUIRK_NON_DESKTOP),
201 EDID_QUIRK('V', 'L', 'V', 0x91b5, EDID_QUIRK_NON_DESKTOP),
202 EDID_QUIRK('V', 'L', 'V', 0x91b6, EDID_QUIRK_NON_DESKTOP),
203 EDID_QUIRK('V', 'L', 'V', 0x91b7, EDID_QUIRK_NON_DESKTOP),
204 EDID_QUIRK('V', 'L', 'V', 0x91b8, EDID_QUIRK_NON_DESKTOP),
205 EDID_QUIRK('V', 'L', 'V', 0x91b9, EDID_QUIRK_NON_DESKTOP),
206 EDID_QUIRK('V', 'L', 'V', 0x91ba, EDID_QUIRK_NON_DESKTOP),
207 EDID_QUIRK('V', 'L', 'V', 0x91bb, EDID_QUIRK_NON_DESKTOP),
208 EDID_QUIRK('V', 'L', 'V', 0x91bc, EDID_QUIRK_NON_DESKTOP),
209 EDID_QUIRK('V', 'L', 'V', 0x91bd, EDID_QUIRK_NON_DESKTOP),
210 EDID_QUIRK('V', 'L', 'V', 0x91be, EDID_QUIRK_NON_DESKTOP),
211 EDID_QUIRK('V', 'L', 'V', 0x91bf, EDID_QUIRK_NON_DESKTOP),
212
213 /* HTC Vive and Vive Pro VR Headsets */
214 EDID_QUIRK('H', 'V', 'R', 0xaa01, EDID_QUIRK_NON_DESKTOP),
215 EDID_QUIRK('H', 'V', 'R', 0xaa02, EDID_QUIRK_NON_DESKTOP),
216
217 /* Oculus Rift DK1, DK2, CV1 and Rift S VR Headsets */
218 EDID_QUIRK('O', 'V', 'R', 0x0001, EDID_QUIRK_NON_DESKTOP),
219 EDID_QUIRK('O', 'V', 'R', 0x0003, EDID_QUIRK_NON_DESKTOP),
220 EDID_QUIRK('O', 'V', 'R', 0x0004, EDID_QUIRK_NON_DESKTOP),
221 EDID_QUIRK('O', 'V', 'R', 0x0012, EDID_QUIRK_NON_DESKTOP),
222
223 /* Windows Mixed Reality Headsets */
224 EDID_QUIRK('A', 'C', 'R', 0x7fce, EDID_QUIRK_NON_DESKTOP),
225 EDID_QUIRK('L', 'E', 'N', 0x0408, EDID_QUIRK_NON_DESKTOP),
226 EDID_QUIRK('F', 'U', 'J', 0x1970, EDID_QUIRK_NON_DESKTOP),
227 EDID_QUIRK('D', 'E', 'L', 0x7fce, EDID_QUIRK_NON_DESKTOP),
228 EDID_QUIRK('S', 'E', 'C', 0x144a, EDID_QUIRK_NON_DESKTOP),
229 EDID_QUIRK('A', 'U', 'S', 0xc102, EDID_QUIRK_NON_DESKTOP),
230
231 /* Sony PlayStation VR Headset */
232 EDID_QUIRK('S', 'N', 'Y', 0x0704, EDID_QUIRK_NON_DESKTOP),
233
234 /* Sensics VR Headsets */
235 EDID_QUIRK('S', 'E', 'N', 0x1019, EDID_QUIRK_NON_DESKTOP),
236
237 /* OSVR HDK and HDK2 VR Headsets */
238 EDID_QUIRK('S', 'V', 'R', 0x1019, EDID_QUIRK_NON_DESKTOP),
239 EDID_QUIRK('A', 'U', 'O', 0x1111, EDID_QUIRK_NON_DESKTOP),
240};
241
242/*
243 * Autogenerated from the DMT spec.
244 * This table is copied from xfree86/modes/xf86EdidModes.c.
245 */
246static const struct drm_display_mode drm_dmt_modes[] = {
247 /* 0x01 - 640x350@85Hz */
248 { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 31500, 640, 672,
249 736, 832, 0, 350, 382, 385, 445, 0,
250 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
251 /* 0x02 - 640x400@85Hz */
252 { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 31500, 640, 672,
253 736, 832, 0, 400, 401, 404, 445, 0,
254 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
255 /* 0x03 - 720x400@85Hz */
256 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 756,
257 828, 936, 0, 400, 401, 404, 446, 0,
258 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
259 /* 0x04 - 640x480@60Hz */
260 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
261 752, 800, 0, 480, 490, 492, 525, 0,
262 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
263 /* 0x05 - 640x480@72Hz */
264 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664,
265 704, 832, 0, 480, 489, 492, 520, 0,
266 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
267 /* 0x06 - 640x480@75Hz */
268 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656,
269 720, 840, 0, 480, 481, 484, 500, 0,
270 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
271 /* 0x07 - 640x480@85Hz */
272 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 36000, 640, 696,
273 752, 832, 0, 480, 481, 484, 509, 0,
274 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
275 /* 0x08 - 800x600@56Hz */
276 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824,
277 896, 1024, 0, 600, 601, 603, 625, 0,
278 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
279 /* 0x09 - 800x600@60Hz */
280 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840,
281 968, 1056, 0, 600, 601, 605, 628, 0,
282 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
283 /* 0x0a - 800x600@72Hz */
284 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856,
285 976, 1040, 0, 600, 637, 643, 666, 0,
286 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
287 /* 0x0b - 800x600@75Hz */
288 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816,
289 896, 1056, 0, 600, 601, 604, 625, 0,
290 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
291 /* 0x0c - 800x600@85Hz */
292 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 56250, 800, 832,
293 896, 1048, 0, 600, 601, 604, 631, 0,
294 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
295 /* 0x0d - 800x600@120Hz RB */
296 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 73250, 800, 848,
297 880, 960, 0, 600, 603, 607, 636, 0,
298 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
299 /* 0x0e - 848x480@60Hz */
300 { DRM_MODE("848x480", DRM_MODE_TYPE_DRIVER, 33750, 848, 864,
301 976, 1088, 0, 480, 486, 494, 517, 0,
302 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
303 /* 0x0f - 1024x768@43Hz, interlace */
304 { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER, 44900, 1024, 1032,
305 1208, 1264, 0, 768, 768, 776, 817, 0,
306 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
307 DRM_MODE_FLAG_INTERLACE) },
308 /* 0x10 - 1024x768@60Hz */
309 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048,
310 1184, 1344, 0, 768, 771, 777, 806, 0,
311 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
312 /* 0x11 - 1024x768@70Hz */
313 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048,
314 1184, 1328, 0, 768, 771, 777, 806, 0,
315 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
316 /* 0x12 - 1024x768@75Hz */
317 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040,
318 1136, 1312, 0, 768, 769, 772, 800, 0,
319 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
320 /* 0x13 - 1024x768@85Hz */
321 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 94500, 1024, 1072,
322 1168, 1376, 0, 768, 769, 772, 808, 0,
323 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
324 /* 0x14 - 1024x768@120Hz RB */
325 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 115500, 1024, 1072,
326 1104, 1184, 0, 768, 771, 775, 813, 0,
327 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
328 /* 0x15 - 1152x864@75Hz */
329 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216,
330 1344, 1600, 0, 864, 865, 868, 900, 0,
331 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
332 /* 0x55 - 1280x720@60Hz */
333 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390,
334 1430, 1650, 0, 720, 725, 730, 750, 0,
335 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
336 /* 0x16 - 1280x768@60Hz RB */
337 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 68250, 1280, 1328,
338 1360, 1440, 0, 768, 771, 778, 790, 0,
339 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
340 /* 0x17 - 1280x768@60Hz */
341 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 79500, 1280, 1344,
342 1472, 1664, 0, 768, 771, 778, 798, 0,
343 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
344 /* 0x18 - 1280x768@75Hz */
345 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 102250, 1280, 1360,
346 1488, 1696, 0, 768, 771, 778, 805, 0,
347 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
348 /* 0x19 - 1280x768@85Hz */
349 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 117500, 1280, 1360,
350 1496, 1712, 0, 768, 771, 778, 809, 0,
351 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
352 /* 0x1a - 1280x768@120Hz RB */
353 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 140250, 1280, 1328,
354 1360, 1440, 0, 768, 771, 778, 813, 0,
355 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
356 /* 0x1b - 1280x800@60Hz RB */
357 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 71000, 1280, 1328,
358 1360, 1440, 0, 800, 803, 809, 823, 0,
359 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
360 /* 0x1c - 1280x800@60Hz */
361 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 83500, 1280, 1352,
362 1480, 1680, 0, 800, 803, 809, 831, 0,
363 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
364 /* 0x1d - 1280x800@75Hz */
365 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 106500, 1280, 1360,
366 1488, 1696, 0, 800, 803, 809, 838, 0,
367 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
368 /* 0x1e - 1280x800@85Hz */
369 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 122500, 1280, 1360,
370 1496, 1712, 0, 800, 803, 809, 843, 0,
371 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
372 /* 0x1f - 1280x800@120Hz RB */
373 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 146250, 1280, 1328,
374 1360, 1440, 0, 800, 803, 809, 847, 0,
375 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
376 /* 0x20 - 1280x960@60Hz */
377 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1376,
378 1488, 1800, 0, 960, 961, 964, 1000, 0,
379 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
380 /* 0x21 - 1280x960@85Hz */
381 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1344,
382 1504, 1728, 0, 960, 961, 964, 1011, 0,
383 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
384 /* 0x22 - 1280x960@120Hz RB */
385 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 175500, 1280, 1328,
386 1360, 1440, 0, 960, 963, 967, 1017, 0,
387 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
388 /* 0x23 - 1280x1024@60Hz */
389 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1328,
390 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
391 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
392 /* 0x24 - 1280x1024@75Hz */
393 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296,
394 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
395 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
396 /* 0x25 - 1280x1024@85Hz */
397 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 157500, 1280, 1344,
398 1504, 1728, 0, 1024, 1025, 1028, 1072, 0,
399 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
400 /* 0x26 - 1280x1024@120Hz RB */
401 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 187250, 1280, 1328,
402 1360, 1440, 0, 1024, 1027, 1034, 1084, 0,
403 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
404 /* 0x27 - 1360x768@60Hz */
405 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 85500, 1360, 1424,
406 1536, 1792, 0, 768, 771, 777, 795, 0,
407 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
408 /* 0x28 - 1360x768@120Hz RB */
409 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 148250, 1360, 1408,
410 1440, 1520, 0, 768, 771, 776, 813, 0,
411 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
412 /* 0x51 - 1366x768@60Hz */
413 { DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 85500, 1366, 1436,
414 1579, 1792, 0, 768, 771, 774, 798, 0,
415 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
416 /* 0x56 - 1366x768@60Hz */
417 { DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 72000, 1366, 1380,
418 1436, 1500, 0, 768, 769, 772, 800, 0,
419 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
420 /* 0x29 - 1400x1050@60Hz RB */
421 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 101000, 1400, 1448,
422 1480, 1560, 0, 1050, 1053, 1057, 1080, 0,
423 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
424 /* 0x2a - 1400x1050@60Hz */
425 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 121750, 1400, 1488,
426 1632, 1864, 0, 1050, 1053, 1057, 1089, 0,
427 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
428 /* 0x2b - 1400x1050@75Hz */
429 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 156000, 1400, 1504,
430 1648, 1896, 0, 1050, 1053, 1057, 1099, 0,
431 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
432 /* 0x2c - 1400x1050@85Hz */
433 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 179500, 1400, 1504,
434 1656, 1912, 0, 1050, 1053, 1057, 1105, 0,
435 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
436 /* 0x2d - 1400x1050@120Hz RB */
437 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 208000, 1400, 1448,
438 1480, 1560, 0, 1050, 1053, 1057, 1112, 0,
439 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
440 /* 0x2e - 1440x900@60Hz RB */
441 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 88750, 1440, 1488,
442 1520, 1600, 0, 900, 903, 909, 926, 0,
443 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
444 /* 0x2f - 1440x900@60Hz */
445 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 106500, 1440, 1520,
446 1672, 1904, 0, 900, 903, 909, 934, 0,
447 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
448 /* 0x30 - 1440x900@75Hz */
449 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 136750, 1440, 1536,
450 1688, 1936, 0, 900, 903, 909, 942, 0,
451 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
452 /* 0x31 - 1440x900@85Hz */
453 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 157000, 1440, 1544,
454 1696, 1952, 0, 900, 903, 909, 948, 0,
455 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
456 /* 0x32 - 1440x900@120Hz RB */
457 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 182750, 1440, 1488,
458 1520, 1600, 0, 900, 903, 909, 953, 0,
459 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
460 /* 0x53 - 1600x900@60Hz */
461 { DRM_MODE("1600x900", DRM_MODE_TYPE_DRIVER, 108000, 1600, 1624,
462 1704, 1800, 0, 900, 901, 904, 1000, 0,
463 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
464 /* 0x33 - 1600x1200@60Hz */
465 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 162000, 1600, 1664,
466 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
467 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
468 /* 0x34 - 1600x1200@65Hz */
469 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 175500, 1600, 1664,
470 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
471 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
472 /* 0x35 - 1600x1200@70Hz */
473 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 189000, 1600, 1664,
474 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
475 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
476 /* 0x36 - 1600x1200@75Hz */
477 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 202500, 1600, 1664,
478 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
479 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
480 /* 0x37 - 1600x1200@85Hz */
481 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 229500, 1600, 1664,
482 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
483 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
484 /* 0x38 - 1600x1200@120Hz RB */
485 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 268250, 1600, 1648,
486 1680, 1760, 0, 1200, 1203, 1207, 1271, 0,
487 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
488 /* 0x39 - 1680x1050@60Hz RB */
489 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 119000, 1680, 1728,
490 1760, 1840, 0, 1050, 1053, 1059, 1080, 0,
491 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
492 /* 0x3a - 1680x1050@60Hz */
493 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 146250, 1680, 1784,
494 1960, 2240, 0, 1050, 1053, 1059, 1089, 0,
495 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
496 /* 0x3b - 1680x1050@75Hz */
497 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 187000, 1680, 1800,
498 1976, 2272, 0, 1050, 1053, 1059, 1099, 0,
499 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
500 /* 0x3c - 1680x1050@85Hz */
501 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 214750, 1680, 1808,
502 1984, 2288, 0, 1050, 1053, 1059, 1105, 0,
503 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
504 /* 0x3d - 1680x1050@120Hz RB */
505 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 245500, 1680, 1728,
506 1760, 1840, 0, 1050, 1053, 1059, 1112, 0,
507 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
508 /* 0x3e - 1792x1344@60Hz */
509 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 204750, 1792, 1920,
510 2120, 2448, 0, 1344, 1345, 1348, 1394, 0,
511 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
512 /* 0x3f - 1792x1344@75Hz */
513 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 261000, 1792, 1888,
514 2104, 2456, 0, 1344, 1345, 1348, 1417, 0,
515 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
516 /* 0x40 - 1792x1344@120Hz RB */
517 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 333250, 1792, 1840,
518 1872, 1952, 0, 1344, 1347, 1351, 1423, 0,
519 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
520 /* 0x41 - 1856x1392@60Hz */
521 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 218250, 1856, 1952,
522 2176, 2528, 0, 1392, 1393, 1396, 1439, 0,
523 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
524 /* 0x42 - 1856x1392@75Hz */
525 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 288000, 1856, 1984,
526 2208, 2560, 0, 1392, 1393, 1396, 1500, 0,
527 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
528 /* 0x43 - 1856x1392@120Hz RB */
529 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 356500, 1856, 1904,
530 1936, 2016, 0, 1392, 1395, 1399, 1474, 0,
531 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
532 /* 0x52 - 1920x1080@60Hz */
533 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
534 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
535 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
536 /* 0x44 - 1920x1200@60Hz RB */
537 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 154000, 1920, 1968,
538 2000, 2080, 0, 1200, 1203, 1209, 1235, 0,
539 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
540 /* 0x45 - 1920x1200@60Hz */
541 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 193250, 1920, 2056,
542 2256, 2592, 0, 1200, 1203, 1209, 1245, 0,
543 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
544 /* 0x46 - 1920x1200@75Hz */
545 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 245250, 1920, 2056,
546 2264, 2608, 0, 1200, 1203, 1209, 1255, 0,
547 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
548 /* 0x47 - 1920x1200@85Hz */
549 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 281250, 1920, 2064,
550 2272, 2624, 0, 1200, 1203, 1209, 1262, 0,
551 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
552 /* 0x48 - 1920x1200@120Hz RB */
553 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 317000, 1920, 1968,
554 2000, 2080, 0, 1200, 1203, 1209, 1271, 0,
555 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
556 /* 0x49 - 1920x1440@60Hz */
557 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 234000, 1920, 2048,
558 2256, 2600, 0, 1440, 1441, 1444, 1500, 0,
559 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
560 /* 0x4a - 1920x1440@75Hz */
561 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2064,
562 2288, 2640, 0, 1440, 1441, 1444, 1500, 0,
563 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
564 /* 0x4b - 1920x1440@120Hz RB */
565 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 380500, 1920, 1968,
566 2000, 2080, 0, 1440, 1443, 1447, 1525, 0,
567 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
568 /* 0x54 - 2048x1152@60Hz */
569 { DRM_MODE("2048x1152", DRM_MODE_TYPE_DRIVER, 162000, 2048, 2074,
570 2154, 2250, 0, 1152, 1153, 1156, 1200, 0,
571 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
572 /* 0x4c - 2560x1600@60Hz RB */
573 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 268500, 2560, 2608,
574 2640, 2720, 0, 1600, 1603, 1609, 1646, 0,
575 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
576 /* 0x4d - 2560x1600@60Hz */
577 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 348500, 2560, 2752,
578 3032, 3504, 0, 1600, 1603, 1609, 1658, 0,
579 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
580 /* 0x4e - 2560x1600@75Hz */
581 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 443250, 2560, 2768,
582 3048, 3536, 0, 1600, 1603, 1609, 1672, 0,
583 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
584 /* 0x4f - 2560x1600@85Hz */
585 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 505250, 2560, 2768,
586 3048, 3536, 0, 1600, 1603, 1609, 1682, 0,
587 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
588 /* 0x50 - 2560x1600@120Hz RB */
589 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 552750, 2560, 2608,
590 2640, 2720, 0, 1600, 1603, 1609, 1694, 0,
591 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
592 /* 0x57 - 4096x2160@60Hz RB */
593 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 556744, 4096, 4104,
594 4136, 4176, 0, 2160, 2208, 2216, 2222, 0,
595 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
596 /* 0x58 - 4096x2160@59.94Hz RB */
597 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 556188, 4096, 4104,
598 4136, 4176, 0, 2160, 2208, 2216, 2222, 0,
599 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
600};
601
602/*
603 * These more or less come from the DMT spec. The 720x400 modes are
604 * inferred from historical 80x25 practice. The 640x480@67 and 832x624@75
605 * modes are old-school Mac modes. The EDID spec says the 1152x864@75 mode
606 * should be 1152x870, again for the Mac, but instead we use the x864 DMT
607 * mode.
608 *
609 * The DMT modes have been fact-checked; the rest are mild guesses.
610 */
611static const struct drm_display_mode edid_est_modes[] = {
612 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840,
613 968, 1056, 0, 600, 601, 605, 628, 0,
614 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@60Hz */
615 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824,
616 896, 1024, 0, 600, 601, 603, 625, 0,
617 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@56Hz */
618 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656,
619 720, 840, 0, 480, 481, 484, 500, 0,
620 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@75Hz */
621 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664,
622 704, 832, 0, 480, 489, 492, 520, 0,
623 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@72Hz */
624 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 30240, 640, 704,
625 768, 864, 0, 480, 483, 486, 525, 0,
626 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@67Hz */
627 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
628 752, 800, 0, 480, 490, 492, 525, 0,
629 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@60Hz */
630 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 738,
631 846, 900, 0, 400, 421, 423, 449, 0,
632 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 720x400@88Hz */
633 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 28320, 720, 738,
634 846, 900, 0, 400, 412, 414, 449, 0,
635 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 720x400@70Hz */
636 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296,
637 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
638 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1280x1024@75Hz */
639 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040,
640 1136, 1312, 0, 768, 769, 772, 800, 0,
641 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1024x768@75Hz */
642 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048,
643 1184, 1328, 0, 768, 771, 777, 806, 0,
644 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@70Hz */
645 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048,
646 1184, 1344, 0, 768, 771, 777, 806, 0,
647 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@60Hz */
648 { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER,44900, 1024, 1032,
649 1208, 1264, 0, 768, 768, 776, 817, 0,
650 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_INTERLACE) }, /* 1024x768@43Hz */
651 { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 57284, 832, 864,
652 928, 1152, 0, 624, 625, 628, 667, 0,
653 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 832x624@75Hz */
654 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816,
655 896, 1056, 0, 600, 601, 604, 625, 0,
656 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@75Hz */
657 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856,
658 976, 1040, 0, 600, 637, 643, 666, 0,
659 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@72Hz */
660 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216,
661 1344, 1600, 0, 864, 865, 868, 900, 0,
662 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1152x864@75Hz */
663};
664
665struct minimode {
666 short w;
667 short h;
668 short r;
669 short rb;
670};
671
672static const struct minimode est3_modes[] = {
673 /* byte 6 */
674 { 640, 350, 85, 0 },
675 { 640, 400, 85, 0 },
676 { 720, 400, 85, 0 },
677 { 640, 480, 85, 0 },
678 { 848, 480, 60, 0 },
679 { 800, 600, 85, 0 },
680 { 1024, 768, 85, 0 },
681 { 1152, 864, 75, 0 },
682 /* byte 7 */
683 { 1280, 768, 60, 1 },
684 { 1280, 768, 60, 0 },
685 { 1280, 768, 75, 0 },
686 { 1280, 768, 85, 0 },
687 { 1280, 960, 60, 0 },
688 { 1280, 960, 85, 0 },
689 { 1280, 1024, 60, 0 },
690 { 1280, 1024, 85, 0 },
691 /* byte 8 */
692 { 1360, 768, 60, 0 },
693 { 1440, 900, 60, 1 },
694 { 1440, 900, 60, 0 },
695 { 1440, 900, 75, 0 },
696 { 1440, 900, 85, 0 },
697 { 1400, 1050, 60, 1 },
698 { 1400, 1050, 60, 0 },
699 { 1400, 1050, 75, 0 },
700 /* byte 9 */
701 { 1400, 1050, 85, 0 },
702 { 1680, 1050, 60, 1 },
703 { 1680, 1050, 60, 0 },
704 { 1680, 1050, 75, 0 },
705 { 1680, 1050, 85, 0 },
706 { 1600, 1200, 60, 0 },
707 { 1600, 1200, 65, 0 },
708 { 1600, 1200, 70, 0 },
709 /* byte 10 */
710 { 1600, 1200, 75, 0 },
711 { 1600, 1200, 85, 0 },
712 { 1792, 1344, 60, 0 },
713 { 1792, 1344, 75, 0 },
714 { 1856, 1392, 60, 0 },
715 { 1856, 1392, 75, 0 },
716 { 1920, 1200, 60, 1 },
717 { 1920, 1200, 60, 0 },
718 /* byte 11 */
719 { 1920, 1200, 75, 0 },
720 { 1920, 1200, 85, 0 },
721 { 1920, 1440, 60, 0 },
722 { 1920, 1440, 75, 0 },
723};
724
725static const struct minimode extra_modes[] = {
726 { 1024, 576, 60, 0 },
727 { 1366, 768, 60, 0 },
728 { 1600, 900, 60, 0 },
729 { 1680, 945, 60, 0 },
730 { 1920, 1080, 60, 0 },
731 { 2048, 1152, 60, 0 },
732 { 2048, 1536, 60, 0 },
733};
734
735/*
736 * From CEA/CTA-861 spec.
737 *
738 * Do not access directly, instead always use cea_mode_for_vic().
739 */
740static const struct drm_display_mode edid_cea_modes_1[] = {
741 /* 1 - 640x480@60Hz 4:3 */
742 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
743 752, 800, 0, 480, 490, 492, 525, 0,
744 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
745 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
746 /* 2 - 720x480@60Hz 4:3 */
747 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736,
748 798, 858, 0, 480, 489, 495, 525, 0,
749 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
750 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
751 /* 3 - 720x480@60Hz 16:9 */
752 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736,
753 798, 858, 0, 480, 489, 495, 525, 0,
754 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
755 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
756 /* 4 - 1280x720@60Hz 16:9 */
757 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390,
758 1430, 1650, 0, 720, 725, 730, 750, 0,
759 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
760 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
761 /* 5 - 1920x1080i@60Hz 16:9 */
762 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008,
763 2052, 2200, 0, 1080, 1084, 1094, 1125, 0,
764 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
765 DRM_MODE_FLAG_INTERLACE),
766 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
767 /* 6 - 720(1440)x480i@60Hz 4:3 */
768 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
769 801, 858, 0, 480, 488, 494, 525, 0,
770 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
771 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
772 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
773 /* 7 - 720(1440)x480i@60Hz 16:9 */
774 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
775 801, 858, 0, 480, 488, 494, 525, 0,
776 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
777 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
778 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
779 /* 8 - 720(1440)x240@60Hz 4:3 */
780 { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
781 801, 858, 0, 240, 244, 247, 262, 0,
782 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
783 DRM_MODE_FLAG_DBLCLK),
784 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
785 /* 9 - 720(1440)x240@60Hz 16:9 */
786 { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
787 801, 858, 0, 240, 244, 247, 262, 0,
788 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
789 DRM_MODE_FLAG_DBLCLK),
790 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
791 /* 10 - 2880x480i@60Hz 4:3 */
792 { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
793 3204, 3432, 0, 480, 488, 494, 525, 0,
794 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
795 DRM_MODE_FLAG_INTERLACE),
796 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
797 /* 11 - 2880x480i@60Hz 16:9 */
798 { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
799 3204, 3432, 0, 480, 488, 494, 525, 0,
800 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
801 DRM_MODE_FLAG_INTERLACE),
802 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
803 /* 12 - 2880x240@60Hz 4:3 */
804 { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
805 3204, 3432, 0, 240, 244, 247, 262, 0,
806 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
807 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
808 /* 13 - 2880x240@60Hz 16:9 */
809 { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
810 3204, 3432, 0, 240, 244, 247, 262, 0,
811 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
812 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
813 /* 14 - 1440x480@60Hz 4:3 */
814 { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472,
815 1596, 1716, 0, 480, 489, 495, 525, 0,
816 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
817 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
818 /* 15 - 1440x480@60Hz 16:9 */
819 { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472,
820 1596, 1716, 0, 480, 489, 495, 525, 0,
821 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
822 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
823 /* 16 - 1920x1080@60Hz 16:9 */
824 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
825 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
826 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
827 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
828 /* 17 - 720x576@50Hz 4:3 */
829 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
830 796, 864, 0, 576, 581, 586, 625, 0,
831 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
832 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
833 /* 18 - 720x576@50Hz 16:9 */
834 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
835 796, 864, 0, 576, 581, 586, 625, 0,
836 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
837 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
838 /* 19 - 1280x720@50Hz 16:9 */
839 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720,
840 1760, 1980, 0, 720, 725, 730, 750, 0,
841 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
842 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
843 /* 20 - 1920x1080i@50Hz 16:9 */
844 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448,
845 2492, 2640, 0, 1080, 1084, 1094, 1125, 0,
846 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
847 DRM_MODE_FLAG_INTERLACE),
848 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
849 /* 21 - 720(1440)x576i@50Hz 4:3 */
850 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
851 795, 864, 0, 576, 580, 586, 625, 0,
852 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
853 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
854 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
855 /* 22 - 720(1440)x576i@50Hz 16:9 */
856 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
857 795, 864, 0, 576, 580, 586, 625, 0,
858 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
859 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
860 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
861 /* 23 - 720(1440)x288@50Hz 4:3 */
862 { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
863 795, 864, 0, 288, 290, 293, 312, 0,
864 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
865 DRM_MODE_FLAG_DBLCLK),
866 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
867 /* 24 - 720(1440)x288@50Hz 16:9 */
868 { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
869 795, 864, 0, 288, 290, 293, 312, 0,
870 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
871 DRM_MODE_FLAG_DBLCLK),
872 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
873 /* 25 - 2880x576i@50Hz 4:3 */
874 { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
875 3180, 3456, 0, 576, 580, 586, 625, 0,
876 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
877 DRM_MODE_FLAG_INTERLACE),
878 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
879 /* 26 - 2880x576i@50Hz 16:9 */
880 { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
881 3180, 3456, 0, 576, 580, 586, 625, 0,
882 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
883 DRM_MODE_FLAG_INTERLACE),
884 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
885 /* 27 - 2880x288@50Hz 4:3 */
886 { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
887 3180, 3456, 0, 288, 290, 293, 312, 0,
888 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
889 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
890 /* 28 - 2880x288@50Hz 16:9 */
891 { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
892 3180, 3456, 0, 288, 290, 293, 312, 0,
893 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
894 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
895 /* 29 - 1440x576@50Hz 4:3 */
896 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464,
897 1592, 1728, 0, 576, 581, 586, 625, 0,
898 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
899 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
900 /* 30 - 1440x576@50Hz 16:9 */
901 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464,
902 1592, 1728, 0, 576, 581, 586, 625, 0,
903 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
904 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
905 /* 31 - 1920x1080@50Hz 16:9 */
906 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448,
907 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
908 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
909 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
910 /* 32 - 1920x1080@24Hz 16:9 */
911 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558,
912 2602, 2750, 0, 1080, 1084, 1089, 1125, 0,
913 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
914 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
915 /* 33 - 1920x1080@25Hz 16:9 */
916 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448,
917 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
918 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
919 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
920 /* 34 - 1920x1080@30Hz 16:9 */
921 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008,
922 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
923 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
924 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
925 /* 35 - 2880x480@60Hz 4:3 */
926 { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944,
927 3192, 3432, 0, 480, 489, 495, 525, 0,
928 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
929 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
930 /* 36 - 2880x480@60Hz 16:9 */
931 { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944,
932 3192, 3432, 0, 480, 489, 495, 525, 0,
933 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
934 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
935 /* 37 - 2880x576@50Hz 4:3 */
936 { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928,
937 3184, 3456, 0, 576, 581, 586, 625, 0,
938 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
939 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
940 /* 38 - 2880x576@50Hz 16:9 */
941 { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928,
942 3184, 3456, 0, 576, 581, 586, 625, 0,
943 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
944 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
945 /* 39 - 1920x1080i@50Hz 16:9 */
946 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 72000, 1920, 1952,
947 2120, 2304, 0, 1080, 1126, 1136, 1250, 0,
948 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC |
949 DRM_MODE_FLAG_INTERLACE),
950 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
951 /* 40 - 1920x1080i@100Hz 16:9 */
952 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448,
953 2492, 2640, 0, 1080, 1084, 1094, 1125, 0,
954 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
955 DRM_MODE_FLAG_INTERLACE),
956 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
957 /* 41 - 1280x720@100Hz 16:9 */
958 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720,
959 1760, 1980, 0, 720, 725, 730, 750, 0,
960 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
961 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
962 /* 42 - 720x576@100Hz 4:3 */
963 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
964 796, 864, 0, 576, 581, 586, 625, 0,
965 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
966 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
967 /* 43 - 720x576@100Hz 16:9 */
968 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
969 796, 864, 0, 576, 581, 586, 625, 0,
970 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
971 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
972 /* 44 - 720(1440)x576i@100Hz 4:3 */
973 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
974 795, 864, 0, 576, 580, 586, 625, 0,
975 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
976 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
977 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
978 /* 45 - 720(1440)x576i@100Hz 16:9 */
979 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
980 795, 864, 0, 576, 580, 586, 625, 0,
981 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
982 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
983 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
984 /* 46 - 1920x1080i@120Hz 16:9 */
985 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
986 2052, 2200, 0, 1080, 1084, 1094, 1125, 0,
987 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
988 DRM_MODE_FLAG_INTERLACE),
989 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
990 /* 47 - 1280x720@120Hz 16:9 */
991 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390,
992 1430, 1650, 0, 720, 725, 730, 750, 0,
993 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
994 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
995 /* 48 - 720x480@120Hz 4:3 */
996 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736,
997 798, 858, 0, 480, 489, 495, 525, 0,
998 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
999 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
1000 /* 49 - 720x480@120Hz 16:9 */
1001 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736,
1002 798, 858, 0, 480, 489, 495, 525, 0,
1003 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
1004 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1005 /* 50 - 720(1440)x480i@120Hz 4:3 */
1006 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739,
1007 801, 858, 0, 480, 488, 494, 525, 0,
1008 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
1009 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
1010 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
1011 /* 51 - 720(1440)x480i@120Hz 16:9 */
1012 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739,
1013 801, 858, 0, 480, 488, 494, 525, 0,
1014 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
1015 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
1016 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1017 /* 52 - 720x576@200Hz 4:3 */
1018 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732,
1019 796, 864, 0, 576, 581, 586, 625, 0,
1020 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
1021 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
1022 /* 53 - 720x576@200Hz 16:9 */
1023 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732,
1024 796, 864, 0, 576, 581, 586, 625, 0,
1025 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
1026 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1027 /* 54 - 720(1440)x576i@200Hz 4:3 */
1028 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
1029 795, 864, 0, 576, 580, 586, 625, 0,
1030 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
1031 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
1032 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
1033 /* 55 - 720(1440)x576i@200Hz 16:9 */
1034 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
1035 795, 864, 0, 576, 580, 586, 625, 0,
1036 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
1037 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
1038 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1039 /* 56 - 720x480@240Hz 4:3 */
1040 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736,
1041 798, 858, 0, 480, 489, 495, 525, 0,
1042 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
1043 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
1044 /* 57 - 720x480@240Hz 16:9 */
1045 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736,
1046 798, 858, 0, 480, 489, 495, 525, 0,
1047 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
1048 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1049 /* 58 - 720(1440)x480i@240Hz 4:3 */
1050 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739,
1051 801, 858, 0, 480, 488, 494, 525, 0,
1052 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
1053 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
1054 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
1055 /* 59 - 720(1440)x480i@240Hz 16:9 */
1056 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739,
1057 801, 858, 0, 480, 488, 494, 525, 0,
1058 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
1059 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
1060 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1061 /* 60 - 1280x720@24Hz 16:9 */
1062 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040,
1063 3080, 3300, 0, 720, 725, 730, 750, 0,
1064 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1065 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1066 /* 61 - 1280x720@25Hz 16:9 */
1067 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700,
1068 3740, 3960, 0, 720, 725, 730, 750, 0,
1069 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1070 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1071 /* 62 - 1280x720@30Hz 16:9 */
1072 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040,
1073 3080, 3300, 0, 720, 725, 730, 750, 0,
1074 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1075 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1076 /* 63 - 1920x1080@120Hz 16:9 */
1077 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008,
1078 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
1079 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1080 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1081 /* 64 - 1920x1080@100Hz 16:9 */
1082 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448,
1083 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
1084 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1085 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1086 /* 65 - 1280x720@24Hz 64:27 */
1087 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040,
1088 3080, 3300, 0, 720, 725, 730, 750, 0,
1089 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1090 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1091 /* 66 - 1280x720@25Hz 64:27 */
1092 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700,
1093 3740, 3960, 0, 720, 725, 730, 750, 0,
1094 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1095 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1096 /* 67 - 1280x720@30Hz 64:27 */
1097 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040,
1098 3080, 3300, 0, 720, 725, 730, 750, 0,
1099 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1100 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1101 /* 68 - 1280x720@50Hz 64:27 */
1102 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720,
1103 1760, 1980, 0, 720, 725, 730, 750, 0,
1104 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1105 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1106 /* 69 - 1280x720@60Hz 64:27 */
1107 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390,
1108 1430, 1650, 0, 720, 725, 730, 750, 0,
1109 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1110 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1111 /* 70 - 1280x720@100Hz 64:27 */
1112 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720,
1113 1760, 1980, 0, 720, 725, 730, 750, 0,
1114 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1115 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1116 /* 71 - 1280x720@120Hz 64:27 */
1117 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390,
1118 1430, 1650, 0, 720, 725, 730, 750, 0,
1119 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1120 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1121 /* 72 - 1920x1080@24Hz 64:27 */
1122 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558,
1123 2602, 2750, 0, 1080, 1084, 1089, 1125, 0,
1124 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1125 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1126 /* 73 - 1920x1080@25Hz 64:27 */
1127 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448,
1128 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
1129 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1130 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1131 /* 74 - 1920x1080@30Hz 64:27 */
1132 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008,
1133 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
1134 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1135 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1136 /* 75 - 1920x1080@50Hz 64:27 */
1137 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448,
1138 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
1139 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1140 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1141 /* 76 - 1920x1080@60Hz 64:27 */
1142 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
1143 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
1144 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1145 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1146 /* 77 - 1920x1080@100Hz 64:27 */
1147 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448,
1148 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
1149 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1150 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1151 /* 78 - 1920x1080@120Hz 64:27 */
1152 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008,
1153 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
1154 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1155 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1156 /* 79 - 1680x720@24Hz 64:27 */
1157 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 3040,
1158 3080, 3300, 0, 720, 725, 730, 750, 0,
1159 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1160 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1161 /* 80 - 1680x720@25Hz 64:27 */
1162 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 2908,
1163 2948, 3168, 0, 720, 725, 730, 750, 0,
1164 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1165 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1166 /* 81 - 1680x720@30Hz 64:27 */
1167 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 2380,
1168 2420, 2640, 0, 720, 725, 730, 750, 0,
1169 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1170 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1171 /* 82 - 1680x720@50Hz 64:27 */
1172 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 82500, 1680, 1940,
1173 1980, 2200, 0, 720, 725, 730, 750, 0,
1174 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1175 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1176 /* 83 - 1680x720@60Hz 64:27 */
1177 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 99000, 1680, 1940,
1178 1980, 2200, 0, 720, 725, 730, 750, 0,
1179 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1180 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1181 /* 84 - 1680x720@100Hz 64:27 */
1182 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 165000, 1680, 1740,
1183 1780, 2000, 0, 720, 725, 730, 825, 0,
1184 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1185 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1186 /* 85 - 1680x720@120Hz 64:27 */
1187 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 198000, 1680, 1740,
1188 1780, 2000, 0, 720, 725, 730, 825, 0,
1189 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1190 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1191 /* 86 - 2560x1080@24Hz 64:27 */
1192 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 99000, 2560, 3558,
1193 3602, 3750, 0, 1080, 1084, 1089, 1100, 0,
1194 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1195 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1196 /* 87 - 2560x1080@25Hz 64:27 */
1197 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 90000, 2560, 3008,
1198 3052, 3200, 0, 1080, 1084, 1089, 1125, 0,
1199 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1200 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1201 /* 88 - 2560x1080@30Hz 64:27 */
1202 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 118800, 2560, 3328,
1203 3372, 3520, 0, 1080, 1084, 1089, 1125, 0,
1204 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1205 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1206 /* 89 - 2560x1080@50Hz 64:27 */
1207 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 185625, 2560, 3108,
1208 3152, 3300, 0, 1080, 1084, 1089, 1125, 0,
1209 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1210 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1211 /* 90 - 2560x1080@60Hz 64:27 */
1212 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 198000, 2560, 2808,
1213 2852, 3000, 0, 1080, 1084, 1089, 1100, 0,
1214 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1215 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1216 /* 91 - 2560x1080@100Hz 64:27 */
1217 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 371250, 2560, 2778,
1218 2822, 2970, 0, 1080, 1084, 1089, 1250, 0,
1219 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1220 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1221 /* 92 - 2560x1080@120Hz 64:27 */
1222 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 495000, 2560, 3108,
1223 3152, 3300, 0, 1080, 1084, 1089, 1250, 0,
1224 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1225 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1226 /* 93 - 3840x2160@24Hz 16:9 */
1227 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 5116,
1228 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1229 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1230 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1231 /* 94 - 3840x2160@25Hz 16:9 */
1232 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4896,
1233 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1234 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1235 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1236 /* 95 - 3840x2160@30Hz 16:9 */
1237 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4016,
1238 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1239 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1240 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1241 /* 96 - 3840x2160@50Hz 16:9 */
1242 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4896,
1243 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1244 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1245 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1246 /* 97 - 3840x2160@60Hz 16:9 */
1247 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4016,
1248 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1249 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1250 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1251 /* 98 - 4096x2160@24Hz 256:135 */
1252 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 5116,
1253 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1254 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1255 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1256 /* 99 - 4096x2160@25Hz 256:135 */
1257 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 5064,
1258 5152, 5280, 0, 2160, 2168, 2178, 2250, 0,
1259 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1260 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1261 /* 100 - 4096x2160@30Hz 256:135 */
1262 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 4184,
1263 4272, 4400, 0, 2160, 2168, 2178, 2250, 0,
1264 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1265 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1266 /* 101 - 4096x2160@50Hz 256:135 */
1267 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 5064,
1268 5152, 5280, 0, 2160, 2168, 2178, 2250, 0,
1269 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1270 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1271 /* 102 - 4096x2160@60Hz 256:135 */
1272 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 4184,
1273 4272, 4400, 0, 2160, 2168, 2178, 2250, 0,
1274 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1275 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1276 /* 103 - 3840x2160@24Hz 64:27 */
1277 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 5116,
1278 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1279 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1280 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1281 /* 104 - 3840x2160@25Hz 64:27 */
1282 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4896,
1283 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1284 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1285 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1286 /* 105 - 3840x2160@30Hz 64:27 */
1287 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4016,
1288 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1289 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1290 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1291 /* 106 - 3840x2160@50Hz 64:27 */
1292 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4896,
1293 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1294 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1295 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1296 /* 107 - 3840x2160@60Hz 64:27 */
1297 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4016,
1298 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1299 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1300 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1301 /* 108 - 1280x720@48Hz 16:9 */
1302 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 90000, 1280, 2240,
1303 2280, 2500, 0, 720, 725, 730, 750, 0,
1304 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1305 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1306 /* 109 - 1280x720@48Hz 64:27 */
1307 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 90000, 1280, 2240,
1308 2280, 2500, 0, 720, 725, 730, 750, 0,
1309 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1310 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1311 /* 110 - 1680x720@48Hz 64:27 */
1312 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 99000, 1680, 2490,
1313 2530, 2750, 0, 720, 725, 730, 750, 0,
1314 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1315 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1316 /* 111 - 1920x1080@48Hz 16:9 */
1317 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2558,
1318 2602, 2750, 0, 1080, 1084, 1089, 1125, 0,
1319 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1320 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1321 /* 112 - 1920x1080@48Hz 64:27 */
1322 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2558,
1323 2602, 2750, 0, 1080, 1084, 1089, 1125, 0,
1324 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1325 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1326 /* 113 - 2560x1080@48Hz 64:27 */
1327 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 198000, 2560, 3558,
1328 3602, 3750, 0, 1080, 1084, 1089, 1100, 0,
1329 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1330 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1331 /* 114 - 3840x2160@48Hz 16:9 */
1332 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 5116,
1333 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1334 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1335 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1336 /* 115 - 4096x2160@48Hz 256:135 */
1337 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 5116,
1338 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1339 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1340 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1341 /* 116 - 3840x2160@48Hz 64:27 */
1342 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 5116,
1343 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1344 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1345 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1346 /* 117 - 3840x2160@100Hz 16:9 */
1347 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4896,
1348 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1349 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1350 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1351 /* 118 - 3840x2160@120Hz 16:9 */
1352 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4016,
1353 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1354 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1355 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1356 /* 119 - 3840x2160@100Hz 64:27 */
1357 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4896,
1358 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1359 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1360 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1361 /* 120 - 3840x2160@120Hz 64:27 */
1362 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4016,
1363 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1364 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1365 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1366 /* 121 - 5120x2160@24Hz 64:27 */
1367 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 396000, 5120, 7116,
1368 7204, 7500, 0, 2160, 2168, 2178, 2200, 0,
1369 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1370 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1371 /* 122 - 5120x2160@25Hz 64:27 */
1372 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 396000, 5120, 6816,
1373 6904, 7200, 0, 2160, 2168, 2178, 2200, 0,
1374 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1375 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1376 /* 123 - 5120x2160@30Hz 64:27 */
1377 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 396000, 5120, 5784,
1378 5872, 6000, 0, 2160, 2168, 2178, 2200, 0,
1379 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1380 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1381 /* 124 - 5120x2160@48Hz 64:27 */
1382 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 742500, 5120, 5866,
1383 5954, 6250, 0, 2160, 2168, 2178, 2475, 0,
1384 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1385 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1386 /* 125 - 5120x2160@50Hz 64:27 */
1387 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 742500, 5120, 6216,
1388 6304, 6600, 0, 2160, 2168, 2178, 2250, 0,
1389 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1390 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1391 /* 126 - 5120x2160@60Hz 64:27 */
1392 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 742500, 5120, 5284,
1393 5372, 5500, 0, 2160, 2168, 2178, 2250, 0,
1394 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1395 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1396 /* 127 - 5120x2160@100Hz 64:27 */
1397 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 1485000, 5120, 6216,
1398 6304, 6600, 0, 2160, 2168, 2178, 2250, 0,
1399 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1400 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1401};
1402
1403/*
1404 * From CEA/CTA-861 spec.
1405 *
1406 * Do not access directly, instead always use cea_mode_for_vic().
1407 */
1408static const struct drm_display_mode edid_cea_modes_193[] = {
1409 /* 193 - 5120x2160@120Hz 64:27 */
1410 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 1485000, 5120, 5284,
1411 5372, 5500, 0, 2160, 2168, 2178, 2250, 0,
1412 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1413 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1414 /* 194 - 7680x4320@24Hz 16:9 */
1415 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10232,
1416 10408, 11000, 0, 4320, 4336, 4356, 4500, 0,
1417 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1418 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1419 /* 195 - 7680x4320@25Hz 16:9 */
1420 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10032,
1421 10208, 10800, 0, 4320, 4336, 4356, 4400, 0,
1422 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1423 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1424 /* 196 - 7680x4320@30Hz 16:9 */
1425 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 8232,
1426 8408, 9000, 0, 4320, 4336, 4356, 4400, 0,
1427 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1428 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1429 /* 197 - 7680x4320@48Hz 16:9 */
1430 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10232,
1431 10408, 11000, 0, 4320, 4336, 4356, 4500, 0,
1432 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1433 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1434 /* 198 - 7680x4320@50Hz 16:9 */
1435 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10032,
1436 10208, 10800, 0, 4320, 4336, 4356, 4400, 0,
1437 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1438 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1439 /* 199 - 7680x4320@60Hz 16:9 */
1440 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 8232,
1441 8408, 9000, 0, 4320, 4336, 4356, 4400, 0,
1442 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1443 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1444 /* 200 - 7680x4320@100Hz 16:9 */
1445 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 9792,
1446 9968, 10560, 0, 4320, 4336, 4356, 4500, 0,
1447 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1448 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1449 /* 201 - 7680x4320@120Hz 16:9 */
1450 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 8032,
1451 8208, 8800, 0, 4320, 4336, 4356, 4500, 0,
1452 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1453 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1454 /* 202 - 7680x4320@24Hz 64:27 */
1455 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10232,
1456 10408, 11000, 0, 4320, 4336, 4356, 4500, 0,
1457 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1458 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1459 /* 203 - 7680x4320@25Hz 64:27 */
1460 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10032,
1461 10208, 10800, 0, 4320, 4336, 4356, 4400, 0,
1462 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1463 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1464 /* 204 - 7680x4320@30Hz 64:27 */
1465 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 8232,
1466 8408, 9000, 0, 4320, 4336, 4356, 4400, 0,
1467 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1468 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1469 /* 205 - 7680x4320@48Hz 64:27 */
1470 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10232,
1471 10408, 11000, 0, 4320, 4336, 4356, 4500, 0,
1472 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1473 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1474 /* 206 - 7680x4320@50Hz 64:27 */
1475 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10032,
1476 10208, 10800, 0, 4320, 4336, 4356, 4400, 0,
1477 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1478 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1479 /* 207 - 7680x4320@60Hz 64:27 */
1480 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 8232,
1481 8408, 9000, 0, 4320, 4336, 4356, 4400, 0,
1482 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1483 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1484 /* 208 - 7680x4320@100Hz 64:27 */
1485 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 9792,
1486 9968, 10560, 0, 4320, 4336, 4356, 4500, 0,
1487 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1488 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1489 /* 209 - 7680x4320@120Hz 64:27 */
1490 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 8032,
1491 8208, 8800, 0, 4320, 4336, 4356, 4500, 0,
1492 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1493 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1494 /* 210 - 10240x4320@24Hz 64:27 */
1495 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 1485000, 10240, 11732,
1496 11908, 12500, 0, 4320, 4336, 4356, 4950, 0,
1497 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1498 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1499 /* 211 - 10240x4320@25Hz 64:27 */
1500 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 1485000, 10240, 12732,
1501 12908, 13500, 0, 4320, 4336, 4356, 4400, 0,
1502 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1503 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1504 /* 212 - 10240x4320@30Hz 64:27 */
1505 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 1485000, 10240, 10528,
1506 10704, 11000, 0, 4320, 4336, 4356, 4500, 0,
1507 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1508 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1509 /* 213 - 10240x4320@48Hz 64:27 */
1510 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 2970000, 10240, 11732,
1511 11908, 12500, 0, 4320, 4336, 4356, 4950, 0,
1512 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1513 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1514 /* 214 - 10240x4320@50Hz 64:27 */
1515 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 2970000, 10240, 12732,
1516 12908, 13500, 0, 4320, 4336, 4356, 4400, 0,
1517 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1518 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1519 /* 215 - 10240x4320@60Hz 64:27 */
1520 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 2970000, 10240, 10528,
1521 10704, 11000, 0, 4320, 4336, 4356, 4500, 0,
1522 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1523 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1524 /* 216 - 10240x4320@100Hz 64:27 */
1525 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 5940000, 10240, 12432,
1526 12608, 13200, 0, 4320, 4336, 4356, 4500, 0,
1527 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1528 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1529 /* 217 - 10240x4320@120Hz 64:27 */
1530 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 5940000, 10240, 10528,
1531 10704, 11000, 0, 4320, 4336, 4356, 4500, 0,
1532 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1533 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1534 /* 218 - 4096x2160@100Hz 256:135 */
1535 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 1188000, 4096, 4896,
1536 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1537 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1538 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1539 /* 219 - 4096x2160@120Hz 256:135 */
1540 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 1188000, 4096, 4184,
1541 4272, 4400, 0, 2160, 2168, 2178, 2250, 0,
1542 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1543 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1544};
1545
1546/*
1547 * HDMI 1.4 4k modes. Index using the VIC.
1548 */
1549static const struct drm_display_mode edid_4k_modes[] = {
1550 /* 0 - dummy, VICs start at 1 */
1551 { },
1552 /* 1 - 3840x2160@30Hz */
1553 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000,
1554 3840, 4016, 4104, 4400, 0,
1555 2160, 2168, 2178, 2250, 0,
1556 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1557 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1558 /* 2 - 3840x2160@25Hz */
1559 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000,
1560 3840, 4896, 4984, 5280, 0,
1561 2160, 2168, 2178, 2250, 0,
1562 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1563 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1564 /* 3 - 3840x2160@24Hz */
1565 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000,
1566 3840, 5116, 5204, 5500, 0,
1567 2160, 2168, 2178, 2250, 0,
1568 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1569 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1570 /* 4 - 4096x2160@24Hz (SMPTE) */
1571 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000,
1572 4096, 5116, 5204, 5500, 0,
1573 2160, 2168, 2178, 2250, 0,
1574 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1575 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1576};
1577
1578/*** DDC fetch and block validation ***/
1579
1580/*
1581 * The opaque EDID type, internal to drm_edid.c.
1582 */
1583struct drm_edid {
1584 /* Size allocated for edid */
1585 size_t size;
1586 const struct edid *edid;
1587};
1588
1589static int edid_hfeeodb_extension_block_count(const struct edid *edid);
1590
1591static int edid_hfeeodb_block_count(const struct edid *edid)
1592{
1593 int eeodb = edid_hfeeodb_extension_block_count(edid);
1594
1595 return eeodb ? eeodb + 1 : 0;
1596}
1597
1598static int edid_extension_block_count(const struct edid *edid)
1599{
1600 return edid->extensions;
1601}
1602
1603static int edid_block_count(const struct edid *edid)
1604{
1605 return edid_extension_block_count(edid) + 1;
1606}
1607
1608static int edid_size_by_blocks(int num_blocks)
1609{
1610 return num_blocks * EDID_LENGTH;
1611}
1612
1613static int edid_size(const struct edid *edid)
1614{
1615 return edid_size_by_blocks(edid_block_count(edid));
1616}
1617
1618static const void *edid_block_data(const struct edid *edid, int index)
1619{
1620 BUILD_BUG_ON(sizeof(*edid) != EDID_LENGTH);
1621
1622 return edid + index;
1623}
1624
1625static const void *edid_extension_block_data(const struct edid *edid, int index)
1626{
1627 return edid_block_data(edid, index + 1);
1628}
1629
1630/* EDID block count indicated in EDID, may exceed allocated size */
1631static int __drm_edid_block_count(const struct drm_edid *drm_edid)
1632{
1633 int num_blocks;
1634
1635 /* Starting point */
1636 num_blocks = edid_block_count(drm_edid->edid);
1637
1638 /* HF-EEODB override */
1639 if (drm_edid->size >= edid_size_by_blocks(2)) {
1640 int eeodb;
1641
1642 /*
1643 * Note: HF-EEODB may specify a smaller extension count than the
1644 * regular one. Unlike in buffer allocation, here we can use it.
1645 */
1646 eeodb = edid_hfeeodb_block_count(drm_edid->edid);
1647 if (eeodb)
1648 num_blocks = eeodb;
1649 }
1650
1651 return num_blocks;
1652}
1653
1654/* EDID block count, limited by allocated size */
1655static int drm_edid_block_count(const struct drm_edid *drm_edid)
1656{
1657 /* Limit by allocated size */
1658 return min(__drm_edid_block_count(drm_edid),
1659 (int)drm_edid->size / EDID_LENGTH);
1660}
1661
1662/* EDID extension block count, limited by allocated size */
1663static int drm_edid_extension_block_count(const struct drm_edid *drm_edid)
1664{
1665 return drm_edid_block_count(drm_edid) - 1;
1666}
1667
1668static const void *drm_edid_block_data(const struct drm_edid *drm_edid, int index)
1669{
1670 return edid_block_data(drm_edid->edid, index);
1671}
1672
1673static const void *drm_edid_extension_block_data(const struct drm_edid *drm_edid,
1674 int index)
1675{
1676 return edid_extension_block_data(drm_edid->edid, index);
1677}
1678
1679/*
1680 * Initializer helper for legacy interfaces, where we have no choice but to
1681 * trust edid size. Not for general purpose use.
1682 */
1683static const struct drm_edid *drm_edid_legacy_init(struct drm_edid *drm_edid,
1684 const struct edid *edid)
1685{
1686 if (!edid)
1687 return NULL;
1688
1689 memset(drm_edid, 0, sizeof(*drm_edid));
1690
1691 drm_edid->edid = edid;
1692 drm_edid->size = edid_size(edid);
1693
1694 return drm_edid;
1695}
1696
1697/*
1698 * EDID base and extension block iterator.
1699 *
1700 * struct drm_edid_iter iter;
1701 * const u8 *block;
1702 *
1703 * drm_edid_iter_begin(drm_edid, &iter);
1704 * drm_edid_iter_for_each(block, &iter) {
1705 * // do stuff with block
1706 * }
1707 * drm_edid_iter_end(&iter);
1708 */
1709struct drm_edid_iter {
1710 const struct drm_edid *drm_edid;
1711
1712 /* Current block index. */
1713 int index;
1714};
1715
1716static void drm_edid_iter_begin(const struct drm_edid *drm_edid,
1717 struct drm_edid_iter *iter)
1718{
1719 memset(iter, 0, sizeof(*iter));
1720
1721 iter->drm_edid = drm_edid;
1722}
1723
1724static const void *__drm_edid_iter_next(struct drm_edid_iter *iter)
1725{
1726 const void *block = NULL;
1727
1728 if (!iter->drm_edid)
1729 return NULL;
1730
1731 if (iter->index < drm_edid_block_count(iter->drm_edid))
1732 block = drm_edid_block_data(iter->drm_edid, iter->index++);
1733
1734 return block;
1735}
1736
1737#define drm_edid_iter_for_each(__block, __iter) \
1738 while (((__block) = __drm_edid_iter_next(__iter)))
1739
1740static void drm_edid_iter_end(struct drm_edid_iter *iter)
1741{
1742 memset(iter, 0, sizeof(*iter));
1743}
1744
1745static const u8 edid_header[] = {
1746 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00
1747};
1748
1749static void edid_header_fix(void *edid)
1750{
1751 memcpy(edid, edid_header, sizeof(edid_header));
1752}
1753
1754/**
1755 * drm_edid_header_is_valid - sanity check the header of the base EDID block
1756 * @_edid: pointer to raw base EDID block
1757 *
1758 * Sanity check the header of the base EDID block.
1759 *
1760 * Return: 8 if the header is perfect, down to 0 if it's totally wrong.
1761 */
1762int drm_edid_header_is_valid(const void *_edid)
1763{
1764 const struct edid *edid = _edid;
1765 int i, score = 0;
1766
1767 for (i = 0; i < sizeof(edid_header); i++) {
1768 if (edid->header[i] == edid_header[i])
1769 score++;
1770 }
1771
1772 return score;
1773}
1774EXPORT_SYMBOL(drm_edid_header_is_valid);
1775
1776static int edid_fixup __read_mostly = 6;
1777module_param_named(edid_fixup, edid_fixup, int, 0400);
1778MODULE_PARM_DESC(edid_fixup,
1779 "Minimum number of valid EDID header bytes (0-8, default 6)");
1780
1781static int edid_block_compute_checksum(const void *_block)
1782{
1783 const u8 *block = _block;
1784 int i;
1785 u8 csum = 0, crc = 0;
1786
1787 for (i = 0; i < EDID_LENGTH - 1; i++)
1788 csum += block[i];
1789
1790 crc = 0x100 - csum;
1791
1792 return crc;
1793}
1794
1795static int edid_block_get_checksum(const void *_block)
1796{
1797 const struct edid *block = _block;
1798
1799 return block->checksum;
1800}
1801
1802static int edid_block_tag(const void *_block)
1803{
1804 const u8 *block = _block;
1805
1806 return block[0];
1807}
1808
1809static bool edid_block_is_zero(const void *edid)
1810{
1811 return !memchr_inv(edid, 0, EDID_LENGTH);
1812}
1813
1814/**
1815 * drm_edid_are_equal - compare two edid blobs.
1816 * @edid1: pointer to first blob
1817 * @edid2: pointer to second blob
1818 * This helper can be used during probing to determine if
1819 * edid had changed.
1820 */
1821bool drm_edid_are_equal(const struct edid *edid1, const struct edid *edid2)
1822{
1823 int edid1_len, edid2_len;
1824 bool edid1_present = edid1 != NULL;
1825 bool edid2_present = edid2 != NULL;
1826
1827 if (edid1_present != edid2_present)
1828 return false;
1829
1830 if (edid1) {
1831 edid1_len = edid_size(edid1);
1832 edid2_len = edid_size(edid2);
1833
1834 if (edid1_len != edid2_len)
1835 return false;
1836
1837 if (memcmp(edid1, edid2, edid1_len))
1838 return false;
1839 }
1840
1841 return true;
1842}
1843EXPORT_SYMBOL(drm_edid_are_equal);
1844
1845enum edid_block_status {
1846 EDID_BLOCK_OK = 0,
1847 EDID_BLOCK_READ_FAIL,
1848 EDID_BLOCK_NULL,
1849 EDID_BLOCK_ZERO,
1850 EDID_BLOCK_HEADER_CORRUPT,
1851 EDID_BLOCK_HEADER_REPAIR,
1852 EDID_BLOCK_HEADER_FIXED,
1853 EDID_BLOCK_CHECKSUM,
1854 EDID_BLOCK_VERSION,
1855};
1856
1857static enum edid_block_status edid_block_check(const void *_block,
1858 bool is_base_block)
1859{
1860 const struct edid *block = _block;
1861
1862 if (!block)
1863 return EDID_BLOCK_NULL;
1864
1865 if (is_base_block) {
1866 int score = drm_edid_header_is_valid(block);
1867
1868 if (score < clamp(edid_fixup, 0, 8)) {
1869 if (edid_block_is_zero(block))
1870 return EDID_BLOCK_ZERO;
1871 else
1872 return EDID_BLOCK_HEADER_CORRUPT;
1873 }
1874
1875 if (score < 8)
1876 return EDID_BLOCK_HEADER_REPAIR;
1877 }
1878
1879 if (edid_block_compute_checksum(block) != edid_block_get_checksum(block)) {
1880 if (edid_block_is_zero(block))
1881 return EDID_BLOCK_ZERO;
1882 else
1883 return EDID_BLOCK_CHECKSUM;
1884 }
1885
1886 if (is_base_block) {
1887 if (block->version != 1)
1888 return EDID_BLOCK_VERSION;
1889 }
1890
1891 return EDID_BLOCK_OK;
1892}
1893
1894static bool edid_block_status_valid(enum edid_block_status status, int tag)
1895{
1896 return status == EDID_BLOCK_OK ||
1897 status == EDID_BLOCK_HEADER_FIXED ||
1898 (status == EDID_BLOCK_CHECKSUM && tag == CEA_EXT);
1899}
1900
1901static bool edid_block_valid(const void *block, bool base)
1902{
1903 return edid_block_status_valid(edid_block_check(block, base),
1904 edid_block_tag(block));
1905}
1906
1907static void edid_block_status_print(enum edid_block_status status,
1908 const struct edid *block,
1909 int block_num)
1910{
1911 switch (status) {
1912 case EDID_BLOCK_OK:
1913 break;
1914 case EDID_BLOCK_READ_FAIL:
1915 pr_debug("EDID block %d read failed\n", block_num);
1916 break;
1917 case EDID_BLOCK_NULL:
1918 pr_debug("EDID block %d pointer is NULL\n", block_num);
1919 break;
1920 case EDID_BLOCK_ZERO:
1921 pr_notice("EDID block %d is all zeroes\n", block_num);
1922 break;
1923 case EDID_BLOCK_HEADER_CORRUPT:
1924 pr_notice("EDID has corrupt header\n");
1925 break;
1926 case EDID_BLOCK_HEADER_REPAIR:
1927 pr_debug("EDID corrupt header needs repair\n");
1928 break;
1929 case EDID_BLOCK_HEADER_FIXED:
1930 pr_debug("EDID corrupt header fixed\n");
1931 break;
1932 case EDID_BLOCK_CHECKSUM:
1933 if (edid_block_status_valid(status, edid_block_tag(block))) {
1934 pr_debug("EDID block %d (tag 0x%02x) checksum is invalid, remainder is %d, ignoring\n",
1935 block_num, edid_block_tag(block),
1936 edid_block_compute_checksum(block));
1937 } else {
1938 pr_notice("EDID block %d (tag 0x%02x) checksum is invalid, remainder is %d\n",
1939 block_num, edid_block_tag(block),
1940 edid_block_compute_checksum(block));
1941 }
1942 break;
1943 case EDID_BLOCK_VERSION:
1944 pr_notice("EDID has major version %d, instead of 1\n",
1945 block->version);
1946 break;
1947 default:
1948 WARN(1, "EDID block %d unknown edid block status code %d\n",
1949 block_num, status);
1950 break;
1951 }
1952}
1953
1954static void edid_block_dump(const char *level, const void *block, int block_num)
1955{
1956 enum edid_block_status status;
1957 char prefix[20];
1958
1959 status = edid_block_check(block, block_num == 0);
1960 if (status == EDID_BLOCK_ZERO)
1961 sprintf(prefix, "\t[%02x] ZERO ", block_num);
1962 else if (!edid_block_status_valid(status, edid_block_tag(block)))
1963 sprintf(prefix, "\t[%02x] BAD ", block_num);
1964 else
1965 sprintf(prefix, "\t[%02x] GOOD ", block_num);
1966
1967 print_hex_dump(level, prefix, DUMP_PREFIX_NONE, 16, 1,
1968 block, EDID_LENGTH, false);
1969}
1970
1971/**
1972 * drm_edid_block_valid - Sanity check the EDID block (base or extension)
1973 * @_block: pointer to raw EDID block
1974 * @block_num: type of block to validate (0 for base, extension otherwise)
1975 * @print_bad_edid: if true, dump bad EDID blocks to the console
1976 * @edid_corrupt: if true, the header or checksum is invalid
1977 *
1978 * Validate a base or extension EDID block and optionally dump bad blocks to
1979 * the console.
1980 *
1981 * Return: True if the block is valid, false otherwise.
1982 */
1983bool drm_edid_block_valid(u8 *_block, int block_num, bool print_bad_edid,
1984 bool *edid_corrupt)
1985{
1986 struct edid *block = (struct edid *)_block;
1987 enum edid_block_status status;
1988 bool is_base_block = block_num == 0;
1989 bool valid;
1990
1991 if (WARN_ON(!block))
1992 return false;
1993
1994 status = edid_block_check(block, is_base_block);
1995 if (status == EDID_BLOCK_HEADER_REPAIR) {
1996 DRM_DEBUG_KMS("Fixing EDID header, your hardware may be failing\n");
1997 edid_header_fix(block);
1998
1999 /* Retry with fixed header, update status if that worked. */
2000 status = edid_block_check(block, is_base_block);
2001 if (status == EDID_BLOCK_OK)
2002 status = EDID_BLOCK_HEADER_FIXED;
2003 }
2004
2005 if (edid_corrupt) {
2006 /*
2007 * Unknown major version isn't corrupt but we can't use it. Only
2008 * the base block can reset edid_corrupt to false.
2009 */
2010 if (is_base_block &&
2011 (status == EDID_BLOCK_OK || status == EDID_BLOCK_VERSION))
2012 *edid_corrupt = false;
2013 else if (status != EDID_BLOCK_OK)
2014 *edid_corrupt = true;
2015 }
2016
2017 edid_block_status_print(status, block, block_num);
2018
2019 /* Determine whether we can use this block with this status. */
2020 valid = edid_block_status_valid(status, edid_block_tag(block));
2021
2022 if (!valid && print_bad_edid && status != EDID_BLOCK_ZERO) {
2023 pr_notice("Raw EDID:\n");
2024 edid_block_dump(KERN_NOTICE, block, block_num);
2025 }
2026
2027 return valid;
2028}
2029EXPORT_SYMBOL(drm_edid_block_valid);
2030
2031/**
2032 * drm_edid_is_valid - sanity check EDID data
2033 * @edid: EDID data
2034 *
2035 * Sanity-check an entire EDID record (including extensions)
2036 *
2037 * Return: True if the EDID data is valid, false otherwise.
2038 */
2039bool drm_edid_is_valid(struct edid *edid)
2040{
2041 int i;
2042
2043 if (!edid)
2044 return false;
2045
2046 for (i = 0; i < edid_block_count(edid); i++) {
2047 void *block = (void *)edid_block_data(edid, i);
2048
2049 if (!drm_edid_block_valid(block, i, true, NULL))
2050 return false;
2051 }
2052
2053 return true;
2054}
2055EXPORT_SYMBOL(drm_edid_is_valid);
2056
2057/**
2058 * drm_edid_valid - sanity check EDID data
2059 * @drm_edid: EDID data
2060 *
2061 * Sanity check an EDID. Cross check block count against allocated size and
2062 * checksum the blocks.
2063 *
2064 * Return: True if the EDID data is valid, false otherwise.
2065 */
2066bool drm_edid_valid(const struct drm_edid *drm_edid)
2067{
2068 int i;
2069
2070 if (!drm_edid)
2071 return false;
2072
2073 if (edid_size_by_blocks(__drm_edid_block_count(drm_edid)) != drm_edid->size)
2074 return false;
2075
2076 for (i = 0; i < drm_edid_block_count(drm_edid); i++) {
2077 const void *block = drm_edid_block_data(drm_edid, i);
2078
2079 if (!edid_block_valid(block, i == 0))
2080 return false;
2081 }
2082
2083 return true;
2084}
2085EXPORT_SYMBOL(drm_edid_valid);
2086
2087static struct edid *edid_filter_invalid_blocks(struct edid *edid,
2088 size_t *alloc_size)
2089{
2090 struct edid *new;
2091 int i, valid_blocks = 0;
2092
2093 /*
2094 * Note: If the EDID uses HF-EEODB, but has invalid blocks, we'll revert
2095 * back to regular extension count here. We don't want to start
2096 * modifying the HF-EEODB extension too.
2097 */
2098 for (i = 0; i < edid_block_count(edid); i++) {
2099 const void *src_block = edid_block_data(edid, i);
2100
2101 if (edid_block_valid(src_block, i == 0)) {
2102 void *dst_block = (void *)edid_block_data(edid, valid_blocks);
2103
2104 memmove(dst_block, src_block, EDID_LENGTH);
2105 valid_blocks++;
2106 }
2107 }
2108
2109 /* We already trusted the base block to be valid here... */
2110 if (WARN_ON(!valid_blocks)) {
2111 kfree(edid);
2112 return NULL;
2113 }
2114
2115 edid->extensions = valid_blocks - 1;
2116 edid->checksum = edid_block_compute_checksum(edid);
2117
2118 *alloc_size = edid_size_by_blocks(valid_blocks);
2119
2120 new = krealloc(edid, *alloc_size, GFP_KERNEL);
2121 if (!new)
2122 kfree(edid);
2123
2124 return new;
2125}
2126
2127#define DDC_SEGMENT_ADDR 0x30
2128/**
2129 * drm_do_probe_ddc_edid() - get EDID information via I2C
2130 * @data: I2C device adapter
2131 * @buf: EDID data buffer to be filled
2132 * @block: 128 byte EDID block to start fetching from
2133 * @len: EDID data buffer length to fetch
2134 *
2135 * Try to fetch EDID information by calling I2C driver functions.
2136 *
2137 * Return: 0 on success or -1 on failure.
2138 */
2139static int
2140drm_do_probe_ddc_edid(void *data, u8 *buf, unsigned int block, size_t len)
2141{
2142 struct i2c_adapter *adapter = data;
2143 unsigned char start = block * EDID_LENGTH;
2144 unsigned char segment = block >> 1;
2145 unsigned char xfers = segment ? 3 : 2;
2146 int ret, retries = 5;
2147
2148 /*
2149 * The core I2C driver will automatically retry the transfer if the
2150 * adapter reports EAGAIN. However, we find that bit-banging transfers
2151 * are susceptible to errors under a heavily loaded machine and
2152 * generate spurious NAKs and timeouts. Retrying the transfer
2153 * of the individual block a few times seems to overcome this.
2154 */
2155 do {
2156 struct i2c_msg msgs[] = {
2157 {
2158 .addr = DDC_SEGMENT_ADDR,
2159 .flags = 0,
2160 .len = 1,
2161 .buf = &segment,
2162 }, {
2163 .addr = DDC_ADDR,
2164 .flags = 0,
2165 .len = 1,
2166 .buf = &start,
2167 }, {
2168 .addr = DDC_ADDR,
2169 .flags = I2C_M_RD,
2170 .len = len,
2171 .buf = buf,
2172 }
2173 };
2174
2175 /*
2176 * Avoid sending the segment addr to not upset non-compliant
2177 * DDC monitors.
2178 */
2179 ret = i2c_transfer(adapter, &msgs[3 - xfers], xfers);
2180
2181 if (ret == -ENXIO) {
2182 DRM_DEBUG_KMS("drm: skipping non-existent adapter %s\n",
2183 adapter->name);
2184 break;
2185 }
2186 } while (ret != xfers && --retries);
2187
2188 return ret == xfers ? 0 : -1;
2189}
2190
2191static void connector_bad_edid(struct drm_connector *connector,
2192 const struct edid *edid, int num_blocks)
2193{
2194 int i;
2195 u8 last_block;
2196
2197 /*
2198 * 0x7e in the EDID is the number of extension blocks. The EDID
2199 * is 1 (base block) + num_ext_blocks big. That means we can think
2200 * of 0x7e in the EDID of the _index_ of the last block in the
2201 * combined chunk of memory.
2202 */
2203 last_block = edid->extensions;
2204
2205 /* Calculate real checksum for the last edid extension block data */
2206 if (last_block < num_blocks)
2207 connector->real_edid_checksum =
2208 edid_block_compute_checksum(edid + last_block);
2209
2210 if (connector->bad_edid_counter++ && !drm_debug_enabled(DRM_UT_KMS))
2211 return;
2212
2213 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] EDID is invalid:\n",
2214 connector->base.id, connector->name);
2215 for (i = 0; i < num_blocks; i++)
2216 edid_block_dump(KERN_DEBUG, edid + i, i);
2217}
2218
2219/* Get override or firmware EDID */
2220static const struct drm_edid *drm_edid_override_get(struct drm_connector *connector)
2221{
2222 const struct drm_edid *override = NULL;
2223
2224 mutex_lock(&connector->edid_override_mutex);
2225
2226 if (connector->edid_override)
2227 override = drm_edid_dup(connector->edid_override);
2228
2229 mutex_unlock(&connector->edid_override_mutex);
2230
2231 if (!override)
2232 override = drm_edid_load_firmware(connector);
2233
2234 return IS_ERR(override) ? NULL : override;
2235}
2236
2237/* For debugfs edid_override implementation */
2238int drm_edid_override_show(struct drm_connector *connector, struct seq_file *m)
2239{
2240 const struct drm_edid *drm_edid;
2241
2242 mutex_lock(&connector->edid_override_mutex);
2243
2244 drm_edid = connector->edid_override;
2245 if (drm_edid)
2246 seq_write(m, drm_edid->edid, drm_edid->size);
2247
2248 mutex_unlock(&connector->edid_override_mutex);
2249
2250 return 0;
2251}
2252
2253/* For debugfs edid_override implementation */
2254int drm_edid_override_set(struct drm_connector *connector, const void *edid,
2255 size_t size)
2256{
2257 const struct drm_edid *drm_edid;
2258
2259 drm_edid = drm_edid_alloc(edid, size);
2260 if (!drm_edid_valid(drm_edid)) {
2261 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] EDID override invalid\n",
2262 connector->base.id, connector->name);
2263 drm_edid_free(drm_edid);
2264 return -EINVAL;
2265 }
2266
2267 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] EDID override set\n",
2268 connector->base.id, connector->name);
2269
2270 mutex_lock(&connector->edid_override_mutex);
2271
2272 drm_edid_free(connector->edid_override);
2273 connector->edid_override = drm_edid;
2274
2275 mutex_unlock(&connector->edid_override_mutex);
2276
2277 return 0;
2278}
2279
2280/* For debugfs edid_override implementation */
2281int drm_edid_override_reset(struct drm_connector *connector)
2282{
2283 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] EDID override reset\n",
2284 connector->base.id, connector->name);
2285
2286 mutex_lock(&connector->edid_override_mutex);
2287
2288 drm_edid_free(connector->edid_override);
2289 connector->edid_override = NULL;
2290
2291 mutex_unlock(&connector->edid_override_mutex);
2292
2293 return 0;
2294}
2295
2296/**
2297 * drm_edid_override_connector_update - add modes from override/firmware EDID
2298 * @connector: connector we're probing
2299 *
2300 * Add modes from the override/firmware EDID, if available. Only to be used from
2301 * drm_helper_probe_single_connector_modes() as a fallback for when DDC probe
2302 * failed during drm_get_edid() and caused the override/firmware EDID to be
2303 * skipped.
2304 *
2305 * Return: The number of modes added or 0 if we couldn't find any.
2306 */
2307int drm_edid_override_connector_update(struct drm_connector *connector)
2308{
2309 const struct drm_edid *override;
2310 int num_modes = 0;
2311
2312 override = drm_edid_override_get(connector);
2313 if (override) {
2314 if (drm_edid_connector_update(connector, override) == 0)
2315 num_modes = drm_edid_connector_add_modes(connector);
2316
2317 drm_edid_free(override);
2318
2319 drm_dbg_kms(connector->dev,
2320 "[CONNECTOR:%d:%s] adding %d modes via fallback override/firmware EDID\n",
2321 connector->base.id, connector->name, num_modes);
2322 }
2323
2324 return num_modes;
2325}
2326EXPORT_SYMBOL(drm_edid_override_connector_update);
2327
2328typedef int read_block_fn(void *context, u8 *buf, unsigned int block, size_t len);
2329
2330static enum edid_block_status edid_block_read(void *block, unsigned int block_num,
2331 read_block_fn read_block,
2332 void *context)
2333{
2334 enum edid_block_status status;
2335 bool is_base_block = block_num == 0;
2336 int try;
2337
2338 for (try = 0; try < 4; try++) {
2339 if (read_block(context, block, block_num, EDID_LENGTH))
2340 return EDID_BLOCK_READ_FAIL;
2341
2342 status = edid_block_check(block, is_base_block);
2343 if (status == EDID_BLOCK_HEADER_REPAIR) {
2344 edid_header_fix(block);
2345
2346 /* Retry with fixed header, update status if that worked. */
2347 status = edid_block_check(block, is_base_block);
2348 if (status == EDID_BLOCK_OK)
2349 status = EDID_BLOCK_HEADER_FIXED;
2350 }
2351
2352 if (edid_block_status_valid(status, edid_block_tag(block)))
2353 break;
2354
2355 /* Fail early for unrepairable base block all zeros. */
2356 if (try == 0 && is_base_block && status == EDID_BLOCK_ZERO)
2357 break;
2358 }
2359
2360 return status;
2361}
2362
2363static struct edid *_drm_do_get_edid(struct drm_connector *connector,
2364 read_block_fn read_block, void *context,
2365 size_t *size)
2366{
2367 enum edid_block_status status;
2368 int i, num_blocks, invalid_blocks = 0;
2369 const struct drm_edid *override;
2370 struct edid *edid, *new;
2371 size_t alloc_size = EDID_LENGTH;
2372
2373 override = drm_edid_override_get(connector);
2374 if (override) {
2375 alloc_size = override->size;
2376 edid = kmemdup(override->edid, alloc_size, GFP_KERNEL);
2377 drm_edid_free(override);
2378 if (!edid)
2379 return NULL;
2380 goto ok;
2381 }
2382
2383 edid = kmalloc(alloc_size, GFP_KERNEL);
2384 if (!edid)
2385 return NULL;
2386
2387 status = edid_block_read(edid, 0, read_block, context);
2388
2389 edid_block_status_print(status, edid, 0);
2390
2391 if (status == EDID_BLOCK_READ_FAIL)
2392 goto fail;
2393
2394 /* FIXME: Clarify what a corrupt EDID actually means. */
2395 if (status == EDID_BLOCK_OK || status == EDID_BLOCK_VERSION)
2396 connector->edid_corrupt = false;
2397 else
2398 connector->edid_corrupt = true;
2399
2400 if (!edid_block_status_valid(status, edid_block_tag(edid))) {
2401 if (status == EDID_BLOCK_ZERO)
2402 connector->null_edid_counter++;
2403
2404 connector_bad_edid(connector, edid, 1);
2405 goto fail;
2406 }
2407
2408 if (!edid_extension_block_count(edid))
2409 goto ok;
2410
2411 alloc_size = edid_size(edid);
2412 new = krealloc(edid, alloc_size, GFP_KERNEL);
2413 if (!new)
2414 goto fail;
2415 edid = new;
2416
2417 num_blocks = edid_block_count(edid);
2418 for (i = 1; i < num_blocks; i++) {
2419 void *block = (void *)edid_block_data(edid, i);
2420
2421 status = edid_block_read(block, i, read_block, context);
2422
2423 edid_block_status_print(status, block, i);
2424
2425 if (!edid_block_status_valid(status, edid_block_tag(block))) {
2426 if (status == EDID_BLOCK_READ_FAIL)
2427 goto fail;
2428 invalid_blocks++;
2429 } else if (i == 1) {
2430 /*
2431 * If the first EDID extension is a CTA extension, and
2432 * the first Data Block is HF-EEODB, override the
2433 * extension block count.
2434 *
2435 * Note: HF-EEODB could specify a smaller extension
2436 * count too, but we can't risk allocating a smaller
2437 * amount.
2438 */
2439 int eeodb = edid_hfeeodb_block_count(edid);
2440
2441 if (eeodb > num_blocks) {
2442 num_blocks = eeodb;
2443 alloc_size = edid_size_by_blocks(num_blocks);
2444 new = krealloc(edid, alloc_size, GFP_KERNEL);
2445 if (!new)
2446 goto fail;
2447 edid = new;
2448 }
2449 }
2450 }
2451
2452 if (invalid_blocks) {
2453 connector_bad_edid(connector, edid, num_blocks);
2454
2455 edid = edid_filter_invalid_blocks(edid, &alloc_size);
2456 }
2457
2458ok:
2459 if (size)
2460 *size = alloc_size;
2461
2462 return edid;
2463
2464fail:
2465 kfree(edid);
2466 return NULL;
2467}
2468
2469/**
2470 * drm_do_get_edid - get EDID data using a custom EDID block read function
2471 * @connector: connector we're probing
2472 * @read_block: EDID block read function
2473 * @context: private data passed to the block read function
2474 *
2475 * When the I2C adapter connected to the DDC bus is hidden behind a device that
2476 * exposes a different interface to read EDID blocks this function can be used
2477 * to get EDID data using a custom block read function.
2478 *
2479 * As in the general case the DDC bus is accessible by the kernel at the I2C
2480 * level, drivers must make all reasonable efforts to expose it as an I2C
2481 * adapter and use drm_get_edid() instead of abusing this function.
2482 *
2483 * The EDID may be overridden using debugfs override_edid or firmware EDID
2484 * (drm_edid_load_firmware() and drm.edid_firmware parameter), in this priority
2485 * order. Having either of them bypasses actual EDID reads.
2486 *
2487 * Return: Pointer to valid EDID or NULL if we couldn't find any.
2488 */
2489struct edid *drm_do_get_edid(struct drm_connector *connector,
2490 read_block_fn read_block,
2491 void *context)
2492{
2493 return _drm_do_get_edid(connector, read_block, context, NULL);
2494}
2495EXPORT_SYMBOL_GPL(drm_do_get_edid);
2496
2497/**
2498 * drm_edid_raw - Get a pointer to the raw EDID data.
2499 * @drm_edid: drm_edid container
2500 *
2501 * Get a pointer to the raw EDID data.
2502 *
2503 * This is for transition only. Avoid using this like the plague.
2504 *
2505 * Return: Pointer to raw EDID data.
2506 */
2507const struct edid *drm_edid_raw(const struct drm_edid *drm_edid)
2508{
2509 if (!drm_edid || !drm_edid->size)
2510 return NULL;
2511
2512 /*
2513 * Do not return pointers where relying on EDID extension count would
2514 * lead to buffer overflow.
2515 */
2516 if (WARN_ON(edid_size(drm_edid->edid) > drm_edid->size))
2517 return NULL;
2518
2519 return drm_edid->edid;
2520}
2521EXPORT_SYMBOL(drm_edid_raw);
2522
2523/* Allocate struct drm_edid container *without* duplicating the edid data */
2524static const struct drm_edid *_drm_edid_alloc(const void *edid, size_t size)
2525{
2526 struct drm_edid *drm_edid;
2527
2528 if (!edid || !size || size < EDID_LENGTH)
2529 return NULL;
2530
2531 drm_edid = kzalloc(sizeof(*drm_edid), GFP_KERNEL);
2532 if (drm_edid) {
2533 drm_edid->edid = edid;
2534 drm_edid->size = size;
2535 }
2536
2537 return drm_edid;
2538}
2539
2540/**
2541 * drm_edid_alloc - Allocate a new drm_edid container
2542 * @edid: Pointer to raw EDID data
2543 * @size: Size of memory allocated for EDID
2544 *
2545 * Allocate a new drm_edid container. Do not calculate edid size from edid, pass
2546 * the actual size that has been allocated for the data. There is no validation
2547 * of the raw EDID data against the size, but at least the EDID base block must
2548 * fit in the buffer.
2549 *
2550 * The returned pointer must be freed using drm_edid_free().
2551 *
2552 * Return: drm_edid container, or NULL on errors
2553 */
2554const struct drm_edid *drm_edid_alloc(const void *edid, size_t size)
2555{
2556 const struct drm_edid *drm_edid;
2557
2558 if (!edid || !size || size < EDID_LENGTH)
2559 return NULL;
2560
2561 edid = kmemdup(edid, size, GFP_KERNEL);
2562 if (!edid)
2563 return NULL;
2564
2565 drm_edid = _drm_edid_alloc(edid, size);
2566 if (!drm_edid)
2567 kfree(edid);
2568
2569 return drm_edid;
2570}
2571EXPORT_SYMBOL(drm_edid_alloc);
2572
2573/**
2574 * drm_edid_dup - Duplicate a drm_edid container
2575 * @drm_edid: EDID to duplicate
2576 *
2577 * The returned pointer must be freed using drm_edid_free().
2578 *
2579 * Returns: drm_edid container copy, or NULL on errors
2580 */
2581const struct drm_edid *drm_edid_dup(const struct drm_edid *drm_edid)
2582{
2583 if (!drm_edid)
2584 return NULL;
2585
2586 return drm_edid_alloc(drm_edid->edid, drm_edid->size);
2587}
2588EXPORT_SYMBOL(drm_edid_dup);
2589
2590/**
2591 * drm_edid_free - Free the drm_edid container
2592 * @drm_edid: EDID to free
2593 */
2594void drm_edid_free(const struct drm_edid *drm_edid)
2595{
2596 if (!drm_edid)
2597 return;
2598
2599 kfree(drm_edid->edid);
2600 kfree(drm_edid);
2601}
2602EXPORT_SYMBOL(drm_edid_free);
2603
2604/**
2605 * drm_probe_ddc() - probe DDC presence
2606 * @adapter: I2C adapter to probe
2607 *
2608 * Return: True on success, false on failure.
2609 */
2610bool
2611drm_probe_ddc(struct i2c_adapter *adapter)
2612{
2613 unsigned char out;
2614
2615 return (drm_do_probe_ddc_edid(adapter, &out, 0, 1) == 0);
2616}
2617EXPORT_SYMBOL(drm_probe_ddc);
2618
2619/**
2620 * drm_get_edid - get EDID data, if available
2621 * @connector: connector we're probing
2622 * @adapter: I2C adapter to use for DDC
2623 *
2624 * Poke the given I2C channel to grab EDID data if possible. If found,
2625 * attach it to the connector.
2626 *
2627 * Return: Pointer to valid EDID or NULL if we couldn't find any.
2628 */
2629struct edid *drm_get_edid(struct drm_connector *connector,
2630 struct i2c_adapter *adapter)
2631{
2632 struct edid *edid;
2633
2634 if (connector->force == DRM_FORCE_OFF)
2635 return NULL;
2636
2637 if (connector->force == DRM_FORCE_UNSPECIFIED && !drm_probe_ddc(adapter))
2638 return NULL;
2639
2640 edid = _drm_do_get_edid(connector, drm_do_probe_ddc_edid, adapter, NULL);
2641 drm_connector_update_edid_property(connector, edid);
2642 return edid;
2643}
2644EXPORT_SYMBOL(drm_get_edid);
2645
2646/**
2647 * drm_edid_read_custom - Read EDID data using given EDID block read function
2648 * @connector: Connector to use
2649 * @read_block: EDID block read function
2650 * @context: Private data passed to the block read function
2651 *
2652 * When the I2C adapter connected to the DDC bus is hidden behind a device that
2653 * exposes a different interface to read EDID blocks this function can be used
2654 * to get EDID data using a custom block read function.
2655 *
2656 * As in the general case the DDC bus is accessible by the kernel at the I2C
2657 * level, drivers must make all reasonable efforts to expose it as an I2C
2658 * adapter and use drm_edid_read() or drm_edid_read_ddc() instead of abusing
2659 * this function.
2660 *
2661 * The EDID may be overridden using debugfs override_edid or firmware EDID
2662 * (drm_edid_load_firmware() and drm.edid_firmware parameter), in this priority
2663 * order. Having either of them bypasses actual EDID reads.
2664 *
2665 * The returned pointer must be freed using drm_edid_free().
2666 *
2667 * Return: Pointer to EDID, or NULL if probe/read failed.
2668 */
2669const struct drm_edid *drm_edid_read_custom(struct drm_connector *connector,
2670 read_block_fn read_block,
2671 void *context)
2672{
2673 const struct drm_edid *drm_edid;
2674 struct edid *edid;
2675 size_t size = 0;
2676
2677 edid = _drm_do_get_edid(connector, read_block, context, &size);
2678 if (!edid)
2679 return NULL;
2680
2681 /* Sanity check for now */
2682 drm_WARN_ON(connector->dev, !size);
2683
2684 drm_edid = _drm_edid_alloc(edid, size);
2685 if (!drm_edid)
2686 kfree(edid);
2687
2688 return drm_edid;
2689}
2690EXPORT_SYMBOL(drm_edid_read_custom);
2691
2692/**
2693 * drm_edid_read_ddc - Read EDID data using given I2C adapter
2694 * @connector: Connector to use
2695 * @adapter: I2C adapter to use for DDC
2696 *
2697 * Read EDID using the given I2C adapter.
2698 *
2699 * The EDID may be overridden using debugfs override_edid or firmware EDID
2700 * (drm_edid_load_firmware() and drm.edid_firmware parameter), in this priority
2701 * order. Having either of them bypasses actual EDID reads.
2702 *
2703 * Prefer initializing connector->ddc with drm_connector_init_with_ddc() and
2704 * using drm_edid_read() instead of this function.
2705 *
2706 * The returned pointer must be freed using drm_edid_free().
2707 *
2708 * Return: Pointer to EDID, or NULL if probe/read failed.
2709 */
2710const struct drm_edid *drm_edid_read_ddc(struct drm_connector *connector,
2711 struct i2c_adapter *adapter)
2712{
2713 const struct drm_edid *drm_edid;
2714
2715 if (connector->force == DRM_FORCE_OFF)
2716 return NULL;
2717
2718 if (connector->force == DRM_FORCE_UNSPECIFIED && !drm_probe_ddc(adapter))
2719 return NULL;
2720
2721 drm_edid = drm_edid_read_custom(connector, drm_do_probe_ddc_edid, adapter);
2722
2723 /* Note: Do *not* call connector updates here. */
2724
2725 return drm_edid;
2726}
2727EXPORT_SYMBOL(drm_edid_read_ddc);
2728
2729/**
2730 * drm_edid_read - Read EDID data using connector's I2C adapter
2731 * @connector: Connector to use
2732 *
2733 * Read EDID using the connector's I2C adapter.
2734 *
2735 * The EDID may be overridden using debugfs override_edid or firmware EDID
2736 * (drm_edid_load_firmware() and drm.edid_firmware parameter), in this priority
2737 * order. Having either of them bypasses actual EDID reads.
2738 *
2739 * The returned pointer must be freed using drm_edid_free().
2740 *
2741 * Return: Pointer to EDID, or NULL if probe/read failed.
2742 */
2743const struct drm_edid *drm_edid_read(struct drm_connector *connector)
2744{
2745 if (drm_WARN_ON(connector->dev, !connector->ddc))
2746 return NULL;
2747
2748 return drm_edid_read_ddc(connector, connector->ddc);
2749}
2750EXPORT_SYMBOL(drm_edid_read);
2751
2752static u32 edid_extract_panel_id(const struct edid *edid)
2753{
2754 /*
2755 * We represent the ID as a 32-bit number so it can easily be compared
2756 * with "==".
2757 *
2758 * NOTE that we deal with endianness differently for the top half
2759 * of this ID than for the bottom half. The bottom half (the product
2760 * id) gets decoded as little endian by the EDID_PRODUCT_ID because
2761 * that's how everyone seems to interpret it. The top half (the mfg_id)
2762 * gets stored as big endian because that makes
2763 * drm_edid_encode_panel_id() and drm_edid_decode_panel_id() easier
2764 * to write (it's easier to extract the ASCII). It doesn't really
2765 * matter, though, as long as the number here is unique.
2766 */
2767 return (u32)edid->mfg_id[0] << 24 |
2768 (u32)edid->mfg_id[1] << 16 |
2769 (u32)EDID_PRODUCT_ID(edid);
2770}
2771
2772/**
2773 * drm_edid_get_panel_id - Get a panel's ID through DDC
2774 * @adapter: I2C adapter to use for DDC
2775 *
2776 * This function reads the first block of the EDID of a panel and (assuming
2777 * that the EDID is valid) extracts the ID out of it. The ID is a 32-bit value
2778 * (16 bits of manufacturer ID and 16 bits of per-manufacturer ID) that's
2779 * supposed to be different for each different modem of panel.
2780 *
2781 * This function is intended to be used during early probing on devices where
2782 * more than one panel might be present. Because of its intended use it must
2783 * assume that the EDID of the panel is correct, at least as far as the ID
2784 * is concerned (in other words, we don't process any overrides here).
2785 *
2786 * NOTE: it's expected that this function and drm_do_get_edid() will both
2787 * be read the EDID, but there is no caching between them. Since we're only
2788 * reading the first block, hopefully this extra overhead won't be too big.
2789 *
2790 * Return: A 32-bit ID that should be different for each make/model of panel.
2791 * See the functions drm_edid_encode_panel_id() and
2792 * drm_edid_decode_panel_id() for some details on the structure of this
2793 * ID.
2794 */
2795
2796u32 drm_edid_get_panel_id(struct i2c_adapter *adapter)
2797{
2798 enum edid_block_status status;
2799 void *base_block;
2800 u32 panel_id = 0;
2801
2802 /*
2803 * There are no manufacturer IDs of 0, so if there is a problem reading
2804 * the EDID then we'll just return 0.
2805 */
2806
2807 base_block = kzalloc(EDID_LENGTH, GFP_KERNEL);
2808 if (!base_block)
2809 return 0;
2810
2811 status = edid_block_read(base_block, 0, drm_do_probe_ddc_edid, adapter);
2812
2813 edid_block_status_print(status, base_block, 0);
2814
2815 if (edid_block_status_valid(status, edid_block_tag(base_block)))
2816 panel_id = edid_extract_panel_id(base_block);
2817 else
2818 edid_block_dump(KERN_NOTICE, base_block, 0);
2819
2820 kfree(base_block);
2821
2822 return panel_id;
2823}
2824EXPORT_SYMBOL(drm_edid_get_panel_id);
2825
2826/**
2827 * drm_get_edid_switcheroo - get EDID data for a vga_switcheroo output
2828 * @connector: connector we're probing
2829 * @adapter: I2C adapter to use for DDC
2830 *
2831 * Wrapper around drm_get_edid() for laptops with dual GPUs using one set of
2832 * outputs. The wrapper adds the requisite vga_switcheroo calls to temporarily
2833 * switch DDC to the GPU which is retrieving EDID.
2834 *
2835 * Return: Pointer to valid EDID or %NULL if we couldn't find any.
2836 */
2837struct edid *drm_get_edid_switcheroo(struct drm_connector *connector,
2838 struct i2c_adapter *adapter)
2839{
2840 struct drm_device *dev = connector->dev;
2841 struct pci_dev *pdev = to_pci_dev(dev->dev);
2842 struct edid *edid;
2843
2844 if (drm_WARN_ON_ONCE(dev, !dev_is_pci(dev->dev)))
2845 return NULL;
2846
2847 vga_switcheroo_lock_ddc(pdev);
2848 edid = drm_get_edid(connector, adapter);
2849 vga_switcheroo_unlock_ddc(pdev);
2850
2851 return edid;
2852}
2853EXPORT_SYMBOL(drm_get_edid_switcheroo);
2854
2855/**
2856 * drm_edid_read_switcheroo - get EDID data for a vga_switcheroo output
2857 * @connector: connector we're probing
2858 * @adapter: I2C adapter to use for DDC
2859 *
2860 * Wrapper around drm_edid_read_ddc() for laptops with dual GPUs using one set
2861 * of outputs. The wrapper adds the requisite vga_switcheroo calls to
2862 * temporarily switch DDC to the GPU which is retrieving EDID.
2863 *
2864 * Return: Pointer to valid EDID or %NULL if we couldn't find any.
2865 */
2866const struct drm_edid *drm_edid_read_switcheroo(struct drm_connector *connector,
2867 struct i2c_adapter *adapter)
2868{
2869 struct drm_device *dev = connector->dev;
2870 struct pci_dev *pdev = to_pci_dev(dev->dev);
2871 const struct drm_edid *drm_edid;
2872
2873 if (drm_WARN_ON_ONCE(dev, !dev_is_pci(dev->dev)))
2874 return NULL;
2875
2876 vga_switcheroo_lock_ddc(pdev);
2877 drm_edid = drm_edid_read_ddc(connector, adapter);
2878 vga_switcheroo_unlock_ddc(pdev);
2879
2880 return drm_edid;
2881}
2882EXPORT_SYMBOL(drm_edid_read_switcheroo);
2883
2884/**
2885 * drm_edid_duplicate - duplicate an EDID and the extensions
2886 * @edid: EDID to duplicate
2887 *
2888 * Return: Pointer to duplicated EDID or NULL on allocation failure.
2889 */
2890struct edid *drm_edid_duplicate(const struct edid *edid)
2891{
2892 if (!edid)
2893 return NULL;
2894
2895 return kmemdup(edid, edid_size(edid), GFP_KERNEL);
2896}
2897EXPORT_SYMBOL(drm_edid_duplicate);
2898
2899/*** EDID parsing ***/
2900
2901/**
2902 * edid_get_quirks - return quirk flags for a given EDID
2903 * @drm_edid: EDID to process
2904 *
2905 * This tells subsequent routines what fixes they need to apply.
2906 */
2907static u32 edid_get_quirks(const struct drm_edid *drm_edid)
2908{
2909 u32 panel_id = edid_extract_panel_id(drm_edid->edid);
2910 const struct edid_quirk *quirk;
2911 int i;
2912
2913 for (i = 0; i < ARRAY_SIZE(edid_quirk_list); i++) {
2914 quirk = &edid_quirk_list[i];
2915 if (quirk->panel_id == panel_id)
2916 return quirk->quirks;
2917 }
2918
2919 return 0;
2920}
2921
2922#define MODE_SIZE(m) ((m)->hdisplay * (m)->vdisplay)
2923#define MODE_REFRESH_DIFF(c,t) (abs((c) - (t)))
2924
2925/*
2926 * Walk the mode list for connector, clearing the preferred status on existing
2927 * modes and setting it anew for the right mode ala quirks.
2928 */
2929static void edid_fixup_preferred(struct drm_connector *connector)
2930{
2931 const struct drm_display_info *info = &connector->display_info;
2932 struct drm_display_mode *t, *cur_mode, *preferred_mode;
2933 int target_refresh = 0;
2934 int cur_vrefresh, preferred_vrefresh;
2935
2936 if (list_empty(&connector->probed_modes))
2937 return;
2938
2939 if (info->quirks & EDID_QUIRK_PREFER_LARGE_60)
2940 target_refresh = 60;
2941 if (info->quirks & EDID_QUIRK_PREFER_LARGE_75)
2942 target_refresh = 75;
2943
2944 preferred_mode = list_first_entry(&connector->probed_modes,
2945 struct drm_display_mode, head);
2946
2947 list_for_each_entry_safe(cur_mode, t, &connector->probed_modes, head) {
2948 cur_mode->type &= ~DRM_MODE_TYPE_PREFERRED;
2949
2950 if (cur_mode == preferred_mode)
2951 continue;
2952
2953 /* Largest mode is preferred */
2954 if (MODE_SIZE(cur_mode) > MODE_SIZE(preferred_mode))
2955 preferred_mode = cur_mode;
2956
2957 cur_vrefresh = drm_mode_vrefresh(cur_mode);
2958 preferred_vrefresh = drm_mode_vrefresh(preferred_mode);
2959 /* At a given size, try to get closest to target refresh */
2960 if ((MODE_SIZE(cur_mode) == MODE_SIZE(preferred_mode)) &&
2961 MODE_REFRESH_DIFF(cur_vrefresh, target_refresh) <
2962 MODE_REFRESH_DIFF(preferred_vrefresh, target_refresh)) {
2963 preferred_mode = cur_mode;
2964 }
2965 }
2966
2967 preferred_mode->type |= DRM_MODE_TYPE_PREFERRED;
2968}
2969
2970static bool
2971mode_is_rb(const struct drm_display_mode *mode)
2972{
2973 return (mode->htotal - mode->hdisplay == 160) &&
2974 (mode->hsync_end - mode->hdisplay == 80) &&
2975 (mode->hsync_end - mode->hsync_start == 32) &&
2976 (mode->vsync_start - mode->vdisplay == 3);
2977}
2978
2979/*
2980 * drm_mode_find_dmt - Create a copy of a mode if present in DMT
2981 * @dev: Device to duplicate against
2982 * @hsize: Mode width
2983 * @vsize: Mode height
2984 * @fresh: Mode refresh rate
2985 * @rb: Mode reduced-blanking-ness
2986 *
2987 * Walk the DMT mode list looking for a match for the given parameters.
2988 *
2989 * Return: A newly allocated copy of the mode, or NULL if not found.
2990 */
2991struct drm_display_mode *drm_mode_find_dmt(struct drm_device *dev,
2992 int hsize, int vsize, int fresh,
2993 bool rb)
2994{
2995 int i;
2996
2997 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) {
2998 const struct drm_display_mode *ptr = &drm_dmt_modes[i];
2999
3000 if (hsize != ptr->hdisplay)
3001 continue;
3002 if (vsize != ptr->vdisplay)
3003 continue;
3004 if (fresh != drm_mode_vrefresh(ptr))
3005 continue;
3006 if (rb != mode_is_rb(ptr))
3007 continue;
3008
3009 return drm_mode_duplicate(dev, ptr);
3010 }
3011
3012 return NULL;
3013}
3014EXPORT_SYMBOL(drm_mode_find_dmt);
3015
3016static bool is_display_descriptor(const struct detailed_timing *descriptor, u8 type)
3017{
3018 BUILD_BUG_ON(offsetof(typeof(*descriptor), pixel_clock) != 0);
3019 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.pad1) != 2);
3020 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.type) != 3);
3021
3022 return descriptor->pixel_clock == 0 &&
3023 descriptor->data.other_data.pad1 == 0 &&
3024 descriptor->data.other_data.type == type;
3025}
3026
3027static bool is_detailed_timing_descriptor(const struct detailed_timing *descriptor)
3028{
3029 BUILD_BUG_ON(offsetof(typeof(*descriptor), pixel_clock) != 0);
3030
3031 return descriptor->pixel_clock != 0;
3032}
3033
3034typedef void detailed_cb(const struct detailed_timing *timing, void *closure);
3035
3036static void
3037cea_for_each_detailed_block(const u8 *ext, detailed_cb *cb, void *closure)
3038{
3039 int i, n;
3040 u8 d = ext[0x02];
3041 const u8 *det_base = ext + d;
3042
3043 if (d < 4 || d > 127)
3044 return;
3045
3046 n = (127 - d) / 18;
3047 for (i = 0; i < n; i++)
3048 cb((const struct detailed_timing *)(det_base + 18 * i), closure);
3049}
3050
3051static void
3052vtb_for_each_detailed_block(const u8 *ext, detailed_cb *cb, void *closure)
3053{
3054 unsigned int i, n = min((int)ext[0x02], 6);
3055 const u8 *det_base = ext + 5;
3056
3057 if (ext[0x01] != 1)
3058 return; /* unknown version */
3059
3060 for (i = 0; i < n; i++)
3061 cb((const struct detailed_timing *)(det_base + 18 * i), closure);
3062}
3063
3064static void drm_for_each_detailed_block(const struct drm_edid *drm_edid,
3065 detailed_cb *cb, void *closure)
3066{
3067 struct drm_edid_iter edid_iter;
3068 const u8 *ext;
3069 int i;
3070
3071 if (!drm_edid)
3072 return;
3073
3074 for (i = 0; i < EDID_DETAILED_TIMINGS; i++)
3075 cb(&drm_edid->edid->detailed_timings[i], closure);
3076
3077 drm_edid_iter_begin(drm_edid, &edid_iter);
3078 drm_edid_iter_for_each(ext, &edid_iter) {
3079 switch (*ext) {
3080 case CEA_EXT:
3081 cea_for_each_detailed_block(ext, cb, closure);
3082 break;
3083 case VTB_EXT:
3084 vtb_for_each_detailed_block(ext, cb, closure);
3085 break;
3086 default:
3087 break;
3088 }
3089 }
3090 drm_edid_iter_end(&edid_iter);
3091}
3092
3093static void
3094is_rb(const struct detailed_timing *descriptor, void *data)
3095{
3096 bool *res = data;
3097
3098 if (!is_display_descriptor(descriptor, EDID_DETAIL_MONITOR_RANGE))
3099 return;
3100
3101 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.flags) != 10);
3102 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.cvt.flags) != 15);
3103
3104 if (descriptor->data.other_data.data.range.flags == DRM_EDID_CVT_SUPPORT_FLAG &&
3105 descriptor->data.other_data.data.range.formula.cvt.flags & DRM_EDID_CVT_FLAGS_REDUCED_BLANKING)
3106 *res = true;
3107}
3108
3109/* EDID 1.4 defines this explicitly. For EDID 1.3, we guess, badly. */
3110static bool
3111drm_monitor_supports_rb(const struct drm_edid *drm_edid)
3112{
3113 if (drm_edid->edid->revision >= 4) {
3114 bool ret = false;
3115
3116 drm_for_each_detailed_block(drm_edid, is_rb, &ret);
3117 return ret;
3118 }
3119
3120 return drm_edid_is_digital(drm_edid);
3121}
3122
3123static void
3124find_gtf2(const struct detailed_timing *descriptor, void *data)
3125{
3126 const struct detailed_timing **res = data;
3127
3128 if (!is_display_descriptor(descriptor, EDID_DETAIL_MONITOR_RANGE))
3129 return;
3130
3131 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.flags) != 10);
3132
3133 if (descriptor->data.other_data.data.range.flags == DRM_EDID_SECONDARY_GTF_SUPPORT_FLAG)
3134 *res = descriptor;
3135}
3136
3137/* Secondary GTF curve kicks in above some break frequency */
3138static int
3139drm_gtf2_hbreak(const struct drm_edid *drm_edid)
3140{
3141 const struct detailed_timing *descriptor = NULL;
3142
3143 drm_for_each_detailed_block(drm_edid, find_gtf2, &descriptor);
3144
3145 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.gtf2.hfreq_start_khz) != 12);
3146
3147 return descriptor ? descriptor->data.other_data.data.range.formula.gtf2.hfreq_start_khz * 2 : 0;
3148}
3149
3150static int
3151drm_gtf2_2c(const struct drm_edid *drm_edid)
3152{
3153 const struct detailed_timing *descriptor = NULL;
3154
3155 drm_for_each_detailed_block(drm_edid, find_gtf2, &descriptor);
3156
3157 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.gtf2.c) != 13);
3158
3159 return descriptor ? descriptor->data.other_data.data.range.formula.gtf2.c : 0;
3160}
3161
3162static int
3163drm_gtf2_m(const struct drm_edid *drm_edid)
3164{
3165 const struct detailed_timing *descriptor = NULL;
3166
3167 drm_for_each_detailed_block(drm_edid, find_gtf2, &descriptor);
3168
3169 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.gtf2.m) != 14);
3170
3171 return descriptor ? le16_to_cpu(descriptor->data.other_data.data.range.formula.gtf2.m) : 0;
3172}
3173
3174static int
3175drm_gtf2_k(const struct drm_edid *drm_edid)
3176{
3177 const struct detailed_timing *descriptor = NULL;
3178
3179 drm_for_each_detailed_block(drm_edid, find_gtf2, &descriptor);
3180
3181 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.gtf2.k) != 16);
3182
3183 return descriptor ? descriptor->data.other_data.data.range.formula.gtf2.k : 0;
3184}
3185
3186static int
3187drm_gtf2_2j(const struct drm_edid *drm_edid)
3188{
3189 const struct detailed_timing *descriptor = NULL;
3190
3191 drm_for_each_detailed_block(drm_edid, find_gtf2, &descriptor);
3192
3193 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.gtf2.j) != 17);
3194
3195 return descriptor ? descriptor->data.other_data.data.range.formula.gtf2.j : 0;
3196}
3197
3198static void
3199get_timing_level(const struct detailed_timing *descriptor, void *data)
3200{
3201 int *res = data;
3202
3203 if (!is_display_descriptor(descriptor, EDID_DETAIL_MONITOR_RANGE))
3204 return;
3205
3206 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.flags) != 10);
3207
3208 switch (descriptor->data.other_data.data.range.flags) {
3209 case DRM_EDID_DEFAULT_GTF_SUPPORT_FLAG:
3210 *res = LEVEL_GTF;
3211 break;
3212 case DRM_EDID_SECONDARY_GTF_SUPPORT_FLAG:
3213 *res = LEVEL_GTF2;
3214 break;
3215 case DRM_EDID_CVT_SUPPORT_FLAG:
3216 *res = LEVEL_CVT;
3217 break;
3218 default:
3219 break;
3220 }
3221}
3222
3223/* Get standard timing level (CVT/GTF/DMT). */
3224static int standard_timing_level(const struct drm_edid *drm_edid)
3225{
3226 const struct edid *edid = drm_edid->edid;
3227
3228 if (edid->revision >= 4) {
3229 /*
3230 * If the range descriptor doesn't
3231 * indicate otherwise default to CVT
3232 */
3233 int ret = LEVEL_CVT;
3234
3235 drm_for_each_detailed_block(drm_edid, get_timing_level, &ret);
3236
3237 return ret;
3238 } else if (edid->revision >= 3 && drm_gtf2_hbreak(drm_edid)) {
3239 return LEVEL_GTF2;
3240 } else if (edid->revision >= 2) {
3241 return LEVEL_GTF;
3242 } else {
3243 return LEVEL_DMT;
3244 }
3245}
3246
3247/*
3248 * 0 is reserved. The spec says 0x01 fill for unused timings. Some old
3249 * monitors fill with ascii space (0x20) instead.
3250 */
3251static int
3252bad_std_timing(u8 a, u8 b)
3253{
3254 return (a == 0x00 && b == 0x00) ||
3255 (a == 0x01 && b == 0x01) ||
3256 (a == 0x20 && b == 0x20);
3257}
3258
3259static int drm_mode_hsync(const struct drm_display_mode *mode)
3260{
3261 if (mode->htotal <= 0)
3262 return 0;
3263
3264 return DIV_ROUND_CLOSEST(mode->clock, mode->htotal);
3265}
3266
3267static struct drm_display_mode *
3268drm_gtf2_mode(struct drm_device *dev,
3269 const struct drm_edid *drm_edid,
3270 int hsize, int vsize, int vrefresh_rate)
3271{
3272 struct drm_display_mode *mode;
3273
3274 /*
3275 * This is potentially wrong if there's ever a monitor with
3276 * more than one ranges section, each claiming a different
3277 * secondary GTF curve. Please don't do that.
3278 */
3279 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0);
3280 if (!mode)
3281 return NULL;
3282
3283 if (drm_mode_hsync(mode) > drm_gtf2_hbreak(drm_edid)) {
3284 drm_mode_destroy(dev, mode);
3285 mode = drm_gtf_mode_complex(dev, hsize, vsize,
3286 vrefresh_rate, 0, 0,
3287 drm_gtf2_m(drm_edid),
3288 drm_gtf2_2c(drm_edid),
3289 drm_gtf2_k(drm_edid),
3290 drm_gtf2_2j(drm_edid));
3291 }
3292
3293 return mode;
3294}
3295
3296/*
3297 * Take the standard timing params (in this case width, aspect, and refresh)
3298 * and convert them into a real mode using CVT/GTF/DMT.
3299 */
3300static struct drm_display_mode *drm_mode_std(struct drm_connector *connector,
3301 const struct drm_edid *drm_edid,
3302 const struct std_timing *t)
3303{
3304 struct drm_device *dev = connector->dev;
3305 struct drm_display_mode *m, *mode = NULL;
3306 int hsize, vsize;
3307 int vrefresh_rate;
3308 unsigned aspect_ratio = (t->vfreq_aspect & EDID_TIMING_ASPECT_MASK)
3309 >> EDID_TIMING_ASPECT_SHIFT;
3310 unsigned vfreq = (t->vfreq_aspect & EDID_TIMING_VFREQ_MASK)
3311 >> EDID_TIMING_VFREQ_SHIFT;
3312 int timing_level = standard_timing_level(drm_edid);
3313
3314 if (bad_std_timing(t->hsize, t->vfreq_aspect))
3315 return NULL;
3316
3317 /* According to the EDID spec, the hdisplay = hsize * 8 + 248 */
3318 hsize = t->hsize * 8 + 248;
3319 /* vrefresh_rate = vfreq + 60 */
3320 vrefresh_rate = vfreq + 60;
3321 /* the vdisplay is calculated based on the aspect ratio */
3322 if (aspect_ratio == 0) {
3323 if (drm_edid->edid->revision < 3)
3324 vsize = hsize;
3325 else
3326 vsize = (hsize * 10) / 16;
3327 } else if (aspect_ratio == 1)
3328 vsize = (hsize * 3) / 4;
3329 else if (aspect_ratio == 2)
3330 vsize = (hsize * 4) / 5;
3331 else
3332 vsize = (hsize * 9) / 16;
3333
3334 /* HDTV hack, part 1 */
3335 if (vrefresh_rate == 60 &&
3336 ((hsize == 1360 && vsize == 765) ||
3337 (hsize == 1368 && vsize == 769))) {
3338 hsize = 1366;
3339 vsize = 768;
3340 }
3341
3342 /*
3343 * If this connector already has a mode for this size and refresh
3344 * rate (because it came from detailed or CVT info), use that
3345 * instead. This way we don't have to guess at interlace or
3346 * reduced blanking.
3347 */
3348 list_for_each_entry(m, &connector->probed_modes, head)
3349 if (m->hdisplay == hsize && m->vdisplay == vsize &&
3350 drm_mode_vrefresh(m) == vrefresh_rate)
3351 return NULL;
3352
3353 /* HDTV hack, part 2 */
3354 if (hsize == 1366 && vsize == 768 && vrefresh_rate == 60) {
3355 mode = drm_cvt_mode(dev, 1366, 768, vrefresh_rate, 0, 0,
3356 false);
3357 if (!mode)
3358 return NULL;
3359 mode->hdisplay = 1366;
3360 mode->hsync_start = mode->hsync_start - 1;
3361 mode->hsync_end = mode->hsync_end - 1;
3362 return mode;
3363 }
3364
3365 /* check whether it can be found in default mode table */
3366 if (drm_monitor_supports_rb(drm_edid)) {
3367 mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate,
3368 true);
3369 if (mode)
3370 return mode;
3371 }
3372 mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate, false);
3373 if (mode)
3374 return mode;
3375
3376 /* okay, generate it */
3377 switch (timing_level) {
3378 case LEVEL_DMT:
3379 break;
3380 case LEVEL_GTF:
3381 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0);
3382 break;
3383 case LEVEL_GTF2:
3384 mode = drm_gtf2_mode(dev, drm_edid, hsize, vsize, vrefresh_rate);
3385 break;
3386 case LEVEL_CVT:
3387 mode = drm_cvt_mode(dev, hsize, vsize, vrefresh_rate, 0, 0,
3388 false);
3389 break;
3390 }
3391 return mode;
3392}
3393
3394/*
3395 * EDID is delightfully ambiguous about how interlaced modes are to be
3396 * encoded. Our internal representation is of frame height, but some
3397 * HDTV detailed timings are encoded as field height.
3398 *
3399 * The format list here is from CEA, in frame size. Technically we
3400 * should be checking refresh rate too. Whatever.
3401 */
3402static void
3403drm_mode_do_interlace_quirk(struct drm_display_mode *mode,
3404 const struct detailed_pixel_timing *pt)
3405{
3406 int i;
3407 static const struct {
3408 int w, h;
3409 } cea_interlaced[] = {
3410 { 1920, 1080 },
3411 { 720, 480 },
3412 { 1440, 480 },
3413 { 2880, 480 },
3414 { 720, 576 },
3415 { 1440, 576 },
3416 { 2880, 576 },
3417 };
3418
3419 if (!(pt->misc & DRM_EDID_PT_INTERLACED))
3420 return;
3421
3422 for (i = 0; i < ARRAY_SIZE(cea_interlaced); i++) {
3423 if ((mode->hdisplay == cea_interlaced[i].w) &&
3424 (mode->vdisplay == cea_interlaced[i].h / 2)) {
3425 mode->vdisplay *= 2;
3426 mode->vsync_start *= 2;
3427 mode->vsync_end *= 2;
3428 mode->vtotal *= 2;
3429 mode->vtotal |= 1;
3430 }
3431 }
3432
3433 mode->flags |= DRM_MODE_FLAG_INTERLACE;
3434}
3435
3436/*
3437 * Create a new mode from an EDID detailed timing section. An EDID detailed
3438 * timing block contains enough info for us to create and return a new struct
3439 * drm_display_mode.
3440 */
3441static struct drm_display_mode *drm_mode_detailed(struct drm_connector *connector,
3442 const struct drm_edid *drm_edid,
3443 const struct detailed_timing *timing)
3444{
3445 const struct drm_display_info *info = &connector->display_info;
3446 struct drm_device *dev = connector->dev;
3447 struct drm_display_mode *mode;
3448 const struct detailed_pixel_timing *pt = &timing->data.pixel_data;
3449 unsigned hactive = (pt->hactive_hblank_hi & 0xf0) << 4 | pt->hactive_lo;
3450 unsigned vactive = (pt->vactive_vblank_hi & 0xf0) << 4 | pt->vactive_lo;
3451 unsigned hblank = (pt->hactive_hblank_hi & 0xf) << 8 | pt->hblank_lo;
3452 unsigned vblank = (pt->vactive_vblank_hi & 0xf) << 8 | pt->vblank_lo;
3453 unsigned hsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc0) << 2 | pt->hsync_offset_lo;
3454 unsigned hsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x30) << 4 | pt->hsync_pulse_width_lo;
3455 unsigned vsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc) << 2 | pt->vsync_offset_pulse_width_lo >> 4;
3456 unsigned vsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x3) << 4 | (pt->vsync_offset_pulse_width_lo & 0xf);
3457
3458 /* ignore tiny modes */
3459 if (hactive < 64 || vactive < 64)
3460 return NULL;
3461
3462 if (pt->misc & DRM_EDID_PT_STEREO) {
3463 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] Stereo mode not supported\n",
3464 connector->base.id, connector->name);
3465 return NULL;
3466 }
3467 if (!(pt->misc & DRM_EDID_PT_SEPARATE_SYNC)) {
3468 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] Composite sync not supported\n",
3469 connector->base.id, connector->name);
3470 }
3471
3472 /* it is incorrect if hsync/vsync width is zero */
3473 if (!hsync_pulse_width || !vsync_pulse_width) {
3474 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] Incorrect Detailed timing. Wrong Hsync/Vsync pulse width\n",
3475 connector->base.id, connector->name);
3476 return NULL;
3477 }
3478
3479 if (info->quirks & EDID_QUIRK_FORCE_REDUCED_BLANKING) {
3480 mode = drm_cvt_mode(dev, hactive, vactive, 60, true, false, false);
3481 if (!mode)
3482 return NULL;
3483
3484 goto set_size;
3485 }
3486
3487 mode = drm_mode_create(dev);
3488 if (!mode)
3489 return NULL;
3490
3491 if (info->quirks & EDID_QUIRK_135_CLOCK_TOO_HIGH)
3492 mode->clock = 1088 * 10;
3493 else
3494 mode->clock = le16_to_cpu(timing->pixel_clock) * 10;
3495
3496 mode->hdisplay = hactive;
3497 mode->hsync_start = mode->hdisplay + hsync_offset;
3498 mode->hsync_end = mode->hsync_start + hsync_pulse_width;
3499 mode->htotal = mode->hdisplay + hblank;
3500
3501 mode->vdisplay = vactive;
3502 mode->vsync_start = mode->vdisplay + vsync_offset;
3503 mode->vsync_end = mode->vsync_start + vsync_pulse_width;
3504 mode->vtotal = mode->vdisplay + vblank;
3505
3506 /* Some EDIDs have bogus h/vsync_end values */
3507 if (mode->hsync_end > mode->htotal) {
3508 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] reducing hsync_end %d->%d\n",
3509 connector->base.id, connector->name,
3510 mode->hsync_end, mode->htotal);
3511 mode->hsync_end = mode->htotal;
3512 }
3513 if (mode->vsync_end > mode->vtotal) {
3514 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] reducing vsync_end %d->%d\n",
3515 connector->base.id, connector->name,
3516 mode->vsync_end, mode->vtotal);
3517 mode->vsync_end = mode->vtotal;
3518 }
3519
3520 drm_mode_do_interlace_quirk(mode, pt);
3521
3522 if (info->quirks & EDID_QUIRK_DETAILED_SYNC_PP) {
3523 mode->flags |= DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC;
3524 } else {
3525 mode->flags |= (pt->misc & DRM_EDID_PT_HSYNC_POSITIVE) ?
3526 DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC;
3527 mode->flags |= (pt->misc & DRM_EDID_PT_VSYNC_POSITIVE) ?
3528 DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC;
3529 }
3530
3531set_size:
3532 mode->width_mm = pt->width_mm_lo | (pt->width_height_mm_hi & 0xf0) << 4;
3533 mode->height_mm = pt->height_mm_lo | (pt->width_height_mm_hi & 0xf) << 8;
3534
3535 if (info->quirks & EDID_QUIRK_DETAILED_IN_CM) {
3536 mode->width_mm *= 10;
3537 mode->height_mm *= 10;
3538 }
3539
3540 if (info->quirks & EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE) {
3541 mode->width_mm = drm_edid->edid->width_cm * 10;
3542 mode->height_mm = drm_edid->edid->height_cm * 10;
3543 }
3544
3545 mode->type = DRM_MODE_TYPE_DRIVER;
3546 drm_mode_set_name(mode);
3547
3548 return mode;
3549}
3550
3551static bool
3552mode_in_hsync_range(const struct drm_display_mode *mode,
3553 const struct edid *edid, const u8 *t)
3554{
3555 int hsync, hmin, hmax;
3556
3557 hmin = t[7];
3558 if (edid->revision >= 4)
3559 hmin += ((t[4] & 0x04) ? 255 : 0);
3560 hmax = t[8];
3561 if (edid->revision >= 4)
3562 hmax += ((t[4] & 0x08) ? 255 : 0);
3563 hsync = drm_mode_hsync(mode);
3564
3565 return (hsync <= hmax && hsync >= hmin);
3566}
3567
3568static bool
3569mode_in_vsync_range(const struct drm_display_mode *mode,
3570 const struct edid *edid, const u8 *t)
3571{
3572 int vsync, vmin, vmax;
3573
3574 vmin = t[5];
3575 if (edid->revision >= 4)
3576 vmin += ((t[4] & 0x01) ? 255 : 0);
3577 vmax = t[6];
3578 if (edid->revision >= 4)
3579 vmax += ((t[4] & 0x02) ? 255 : 0);
3580 vsync = drm_mode_vrefresh(mode);
3581
3582 return (vsync <= vmax && vsync >= vmin);
3583}
3584
3585static u32
3586range_pixel_clock(const struct edid *edid, const u8 *t)
3587{
3588 /* unspecified */
3589 if (t[9] == 0 || t[9] == 255)
3590 return 0;
3591
3592 /* 1.4 with CVT support gives us real precision, yay */
3593 if (edid->revision >= 4 && t[10] == DRM_EDID_CVT_SUPPORT_FLAG)
3594 return (t[9] * 10000) - ((t[12] >> 2) * 250);
3595
3596 /* 1.3 is pathetic, so fuzz up a bit */
3597 return t[9] * 10000 + 5001;
3598}
3599
3600static bool mode_in_range(const struct drm_display_mode *mode,
3601 const struct drm_edid *drm_edid,
3602 const struct detailed_timing *timing)
3603{
3604 const struct edid *edid = drm_edid->edid;
3605 u32 max_clock;
3606 const u8 *t = (const u8 *)timing;
3607
3608 if (!mode_in_hsync_range(mode, edid, t))
3609 return false;
3610
3611 if (!mode_in_vsync_range(mode, edid, t))
3612 return false;
3613
3614 if ((max_clock = range_pixel_clock(edid, t)))
3615 if (mode->clock > max_clock)
3616 return false;
3617
3618 /* 1.4 max horizontal check */
3619 if (edid->revision >= 4 && t[10] == DRM_EDID_CVT_SUPPORT_FLAG)
3620 if (t[13] && mode->hdisplay > 8 * (t[13] + (256 * (t[12]&0x3))))
3621 return false;
3622
3623 if (mode_is_rb(mode) && !drm_monitor_supports_rb(drm_edid))
3624 return false;
3625
3626 return true;
3627}
3628
3629static bool valid_inferred_mode(const struct drm_connector *connector,
3630 const struct drm_display_mode *mode)
3631{
3632 const struct drm_display_mode *m;
3633 bool ok = false;
3634
3635 list_for_each_entry(m, &connector->probed_modes, head) {
3636 if (mode->hdisplay == m->hdisplay &&
3637 mode->vdisplay == m->vdisplay &&
3638 drm_mode_vrefresh(mode) == drm_mode_vrefresh(m))
3639 return false; /* duplicated */
3640 if (mode->hdisplay <= m->hdisplay &&
3641 mode->vdisplay <= m->vdisplay)
3642 ok = true;
3643 }
3644 return ok;
3645}
3646
3647static int drm_dmt_modes_for_range(struct drm_connector *connector,
3648 const struct drm_edid *drm_edid,
3649 const struct detailed_timing *timing)
3650{
3651 int i, modes = 0;
3652 struct drm_display_mode *newmode;
3653 struct drm_device *dev = connector->dev;
3654
3655 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) {
3656 if (mode_in_range(drm_dmt_modes + i, drm_edid, timing) &&
3657 valid_inferred_mode(connector, drm_dmt_modes + i)) {
3658 newmode = drm_mode_duplicate(dev, &drm_dmt_modes[i]);
3659 if (newmode) {
3660 drm_mode_probed_add(connector, newmode);
3661 modes++;
3662 }
3663 }
3664 }
3665
3666 return modes;
3667}
3668
3669/* fix up 1366x768 mode from 1368x768;
3670 * GFT/CVT can't express 1366 width which isn't dividable by 8
3671 */
3672void drm_mode_fixup_1366x768(struct drm_display_mode *mode)
3673{
3674 if (mode->hdisplay == 1368 && mode->vdisplay == 768) {
3675 mode->hdisplay = 1366;
3676 mode->hsync_start--;
3677 mode->hsync_end--;
3678 drm_mode_set_name(mode);
3679 }
3680}
3681
3682static int drm_gtf_modes_for_range(struct drm_connector *connector,
3683 const struct drm_edid *drm_edid,
3684 const struct detailed_timing *timing)
3685{
3686 int i, modes = 0;
3687 struct drm_display_mode *newmode;
3688 struct drm_device *dev = connector->dev;
3689
3690 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) {
3691 const struct minimode *m = &extra_modes[i];
3692
3693 newmode = drm_gtf_mode(dev, m->w, m->h, m->r, 0, 0);
3694 if (!newmode)
3695 return modes;
3696
3697 drm_mode_fixup_1366x768(newmode);
3698 if (!mode_in_range(newmode, drm_edid, timing) ||
3699 !valid_inferred_mode(connector, newmode)) {
3700 drm_mode_destroy(dev, newmode);
3701 continue;
3702 }
3703
3704 drm_mode_probed_add(connector, newmode);
3705 modes++;
3706 }
3707
3708 return modes;
3709}
3710
3711static int drm_gtf2_modes_for_range(struct drm_connector *connector,
3712 const struct drm_edid *drm_edid,
3713 const struct detailed_timing *timing)
3714{
3715 int i, modes = 0;
3716 struct drm_display_mode *newmode;
3717 struct drm_device *dev = connector->dev;
3718
3719 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) {
3720 const struct minimode *m = &extra_modes[i];
3721
3722 newmode = drm_gtf2_mode(dev, drm_edid, m->w, m->h, m->r);
3723 if (!newmode)
3724 return modes;
3725
3726 drm_mode_fixup_1366x768(newmode);
3727 if (!mode_in_range(newmode, drm_edid, timing) ||
3728 !valid_inferred_mode(connector, newmode)) {
3729 drm_mode_destroy(dev, newmode);
3730 continue;
3731 }
3732
3733 drm_mode_probed_add(connector, newmode);
3734 modes++;
3735 }
3736
3737 return modes;
3738}
3739
3740static int drm_cvt_modes_for_range(struct drm_connector *connector,
3741 const struct drm_edid *drm_edid,
3742 const struct detailed_timing *timing)
3743{
3744 int i, modes = 0;
3745 struct drm_display_mode *newmode;
3746 struct drm_device *dev = connector->dev;
3747 bool rb = drm_monitor_supports_rb(drm_edid);
3748
3749 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) {
3750 const struct minimode *m = &extra_modes[i];
3751
3752 newmode = drm_cvt_mode(dev, m->w, m->h, m->r, rb, 0, 0);
3753 if (!newmode)
3754 return modes;
3755
3756 drm_mode_fixup_1366x768(newmode);
3757 if (!mode_in_range(newmode, drm_edid, timing) ||
3758 !valid_inferred_mode(connector, newmode)) {
3759 drm_mode_destroy(dev, newmode);
3760 continue;
3761 }
3762
3763 drm_mode_probed_add(connector, newmode);
3764 modes++;
3765 }
3766
3767 return modes;
3768}
3769
3770static void
3771do_inferred_modes(const struct detailed_timing *timing, void *c)
3772{
3773 struct detailed_mode_closure *closure = c;
3774 const struct detailed_non_pixel *data = &timing->data.other_data;
3775 const struct detailed_data_monitor_range *range = &data->data.range;
3776
3777 if (!is_display_descriptor(timing, EDID_DETAIL_MONITOR_RANGE))
3778 return;
3779
3780 closure->modes += drm_dmt_modes_for_range(closure->connector,
3781 closure->drm_edid,
3782 timing);
3783
3784 if (closure->drm_edid->edid->revision < 2)
3785 return; /* GTF not defined yet */
3786
3787 switch (range->flags) {
3788 case DRM_EDID_SECONDARY_GTF_SUPPORT_FLAG:
3789 closure->modes += drm_gtf2_modes_for_range(closure->connector,
3790 closure->drm_edid,
3791 timing);
3792 break;
3793 case DRM_EDID_DEFAULT_GTF_SUPPORT_FLAG:
3794 closure->modes += drm_gtf_modes_for_range(closure->connector,
3795 closure->drm_edid,
3796 timing);
3797 break;
3798 case DRM_EDID_CVT_SUPPORT_FLAG:
3799 if (closure->drm_edid->edid->revision < 4)
3800 break;
3801
3802 closure->modes += drm_cvt_modes_for_range(closure->connector,
3803 closure->drm_edid,
3804 timing);
3805 break;
3806 case DRM_EDID_RANGE_LIMITS_ONLY_FLAG:
3807 default:
3808 break;
3809 }
3810}
3811
3812static int add_inferred_modes(struct drm_connector *connector,
3813 const struct drm_edid *drm_edid)
3814{
3815 struct detailed_mode_closure closure = {
3816 .connector = connector,
3817 .drm_edid = drm_edid,
3818 };
3819
3820 if (drm_edid->edid->revision >= 1)
3821 drm_for_each_detailed_block(drm_edid, do_inferred_modes, &closure);
3822
3823 return closure.modes;
3824}
3825
3826static int
3827drm_est3_modes(struct drm_connector *connector, const struct detailed_timing *timing)
3828{
3829 int i, j, m, modes = 0;
3830 struct drm_display_mode *mode;
3831 const u8 *est = ((const u8 *)timing) + 6;
3832
3833 for (i = 0; i < 6; i++) {
3834 for (j = 7; j >= 0; j--) {
3835 m = (i * 8) + (7 - j);
3836 if (m >= ARRAY_SIZE(est3_modes))
3837 break;
3838 if (est[i] & (1 << j)) {
3839 mode = drm_mode_find_dmt(connector->dev,
3840 est3_modes[m].w,
3841 est3_modes[m].h,
3842 est3_modes[m].r,
3843 est3_modes[m].rb);
3844 if (mode) {
3845 drm_mode_probed_add(connector, mode);
3846 modes++;
3847 }
3848 }
3849 }
3850 }
3851
3852 return modes;
3853}
3854
3855static void
3856do_established_modes(const struct detailed_timing *timing, void *c)
3857{
3858 struct detailed_mode_closure *closure = c;
3859
3860 if (!is_display_descriptor(timing, EDID_DETAIL_EST_TIMINGS))
3861 return;
3862
3863 closure->modes += drm_est3_modes(closure->connector, timing);
3864}
3865
3866/*
3867 * Get established modes from EDID and add them. Each EDID block contains a
3868 * bitmap of the supported "established modes" list (defined above). Tease them
3869 * out and add them to the global modes list.
3870 */
3871static int add_established_modes(struct drm_connector *connector,
3872 const struct drm_edid *drm_edid)
3873{
3874 struct drm_device *dev = connector->dev;
3875 const struct edid *edid = drm_edid->edid;
3876 unsigned long est_bits = edid->established_timings.t1 |
3877 (edid->established_timings.t2 << 8) |
3878 ((edid->established_timings.mfg_rsvd & 0x80) << 9);
3879 int i, modes = 0;
3880 struct detailed_mode_closure closure = {
3881 .connector = connector,
3882 .drm_edid = drm_edid,
3883 };
3884
3885 for (i = 0; i <= EDID_EST_TIMINGS; i++) {
3886 if (est_bits & (1<<i)) {
3887 struct drm_display_mode *newmode;
3888
3889 newmode = drm_mode_duplicate(dev, &edid_est_modes[i]);
3890 if (newmode) {
3891 drm_mode_probed_add(connector, newmode);
3892 modes++;
3893 }
3894 }
3895 }
3896
3897 if (edid->revision >= 1)
3898 drm_for_each_detailed_block(drm_edid, do_established_modes,
3899 &closure);
3900
3901 return modes + closure.modes;
3902}
3903
3904static void
3905do_standard_modes(const struct detailed_timing *timing, void *c)
3906{
3907 struct detailed_mode_closure *closure = c;
3908 const struct detailed_non_pixel *data = &timing->data.other_data;
3909 struct drm_connector *connector = closure->connector;
3910 int i;
3911
3912 if (!is_display_descriptor(timing, EDID_DETAIL_STD_MODES))
3913 return;
3914
3915 for (i = 0; i < 6; i++) {
3916 const struct std_timing *std = &data->data.timings[i];
3917 struct drm_display_mode *newmode;
3918
3919 newmode = drm_mode_std(connector, closure->drm_edid, std);
3920 if (newmode) {
3921 drm_mode_probed_add(connector, newmode);
3922 closure->modes++;
3923 }
3924 }
3925}
3926
3927/*
3928 * Get standard modes from EDID and add them. Standard modes can be calculated
3929 * using the appropriate standard (DMT, GTF, or CVT). Grab them from EDID and
3930 * add them to the list.
3931 */
3932static int add_standard_modes(struct drm_connector *connector,
3933 const struct drm_edid *drm_edid)
3934{
3935 int i, modes = 0;
3936 struct detailed_mode_closure closure = {
3937 .connector = connector,
3938 .drm_edid = drm_edid,
3939 };
3940
3941 for (i = 0; i < EDID_STD_TIMINGS; i++) {
3942 struct drm_display_mode *newmode;
3943
3944 newmode = drm_mode_std(connector, drm_edid,
3945 &drm_edid->edid->standard_timings[i]);
3946 if (newmode) {
3947 drm_mode_probed_add(connector, newmode);
3948 modes++;
3949 }
3950 }
3951
3952 if (drm_edid->edid->revision >= 1)
3953 drm_for_each_detailed_block(drm_edid, do_standard_modes,
3954 &closure);
3955
3956 /* XXX should also look for standard codes in VTB blocks */
3957
3958 return modes + closure.modes;
3959}
3960
3961static int drm_cvt_modes(struct drm_connector *connector,
3962 const struct detailed_timing *timing)
3963{
3964 int i, j, modes = 0;
3965 struct drm_display_mode *newmode;
3966 struct drm_device *dev = connector->dev;
3967 const struct cvt_timing *cvt;
3968 static const int rates[] = { 60, 85, 75, 60, 50 };
3969 const u8 empty[3] = { 0, 0, 0 };
3970
3971 for (i = 0; i < 4; i++) {
3972 int width, height;
3973
3974 cvt = &(timing->data.other_data.data.cvt[i]);
3975
3976 if (!memcmp(cvt->code, empty, 3))
3977 continue;
3978
3979 height = (cvt->code[0] + ((cvt->code[1] & 0xf0) << 4) + 1) * 2;
3980 switch (cvt->code[1] & 0x0c) {
3981 /* default - because compiler doesn't see that we've enumerated all cases */
3982 default:
3983 case 0x00:
3984 width = height * 4 / 3;
3985 break;
3986 case 0x04:
3987 width = height * 16 / 9;
3988 break;
3989 case 0x08:
3990 width = height * 16 / 10;
3991 break;
3992 case 0x0c:
3993 width = height * 15 / 9;
3994 break;
3995 }
3996
3997 for (j = 1; j < 5; j++) {
3998 if (cvt->code[2] & (1 << j)) {
3999 newmode = drm_cvt_mode(dev, width, height,
4000 rates[j], j == 0,
4001 false, false);
4002 if (newmode) {
4003 drm_mode_probed_add(connector, newmode);
4004 modes++;
4005 }
4006 }
4007 }
4008 }
4009
4010 return modes;
4011}
4012
4013static void
4014do_cvt_mode(const struct detailed_timing *timing, void *c)
4015{
4016 struct detailed_mode_closure *closure = c;
4017
4018 if (!is_display_descriptor(timing, EDID_DETAIL_CVT_3BYTE))
4019 return;
4020
4021 closure->modes += drm_cvt_modes(closure->connector, timing);
4022}
4023
4024static int
4025add_cvt_modes(struct drm_connector *connector, const struct drm_edid *drm_edid)
4026{
4027 struct detailed_mode_closure closure = {
4028 .connector = connector,
4029 .drm_edid = drm_edid,
4030 };
4031
4032 if (drm_edid->edid->revision >= 3)
4033 drm_for_each_detailed_block(drm_edid, do_cvt_mode, &closure);
4034
4035 /* XXX should also look for CVT codes in VTB blocks */
4036
4037 return closure.modes;
4038}
4039
4040static void fixup_detailed_cea_mode_clock(struct drm_connector *connector,
4041 struct drm_display_mode *mode);
4042
4043static void
4044do_detailed_mode(const struct detailed_timing *timing, void *c)
4045{
4046 struct detailed_mode_closure *closure = c;
4047 struct drm_display_mode *newmode;
4048
4049 if (!is_detailed_timing_descriptor(timing))
4050 return;
4051
4052 newmode = drm_mode_detailed(closure->connector,
4053 closure->drm_edid, timing);
4054 if (!newmode)
4055 return;
4056
4057 if (closure->preferred)
4058 newmode->type |= DRM_MODE_TYPE_PREFERRED;
4059
4060 /*
4061 * Detailed modes are limited to 10kHz pixel clock resolution,
4062 * so fix up anything that looks like CEA/HDMI mode, but the clock
4063 * is just slightly off.
4064 */
4065 fixup_detailed_cea_mode_clock(closure->connector, newmode);
4066
4067 drm_mode_probed_add(closure->connector, newmode);
4068 closure->modes++;
4069 closure->preferred = false;
4070}
4071
4072/*
4073 * add_detailed_modes - Add modes from detailed timings
4074 * @connector: attached connector
4075 * @drm_edid: EDID block to scan
4076 */
4077static int add_detailed_modes(struct drm_connector *connector,
4078 const struct drm_edid *drm_edid)
4079{
4080 struct detailed_mode_closure closure = {
4081 .connector = connector,
4082 .drm_edid = drm_edid,
4083 };
4084
4085 if (drm_edid->edid->revision >= 4)
4086 closure.preferred = true; /* first detailed timing is always preferred */
4087 else
4088 closure.preferred =
4089 drm_edid->edid->features & DRM_EDID_FEATURE_PREFERRED_TIMING;
4090
4091 drm_for_each_detailed_block(drm_edid, do_detailed_mode, &closure);
4092
4093 return closure.modes;
4094}
4095
4096/* CTA-861-H Table 60 - CTA Tag Codes */
4097#define CTA_DB_AUDIO 1
4098#define CTA_DB_VIDEO 2
4099#define CTA_DB_VENDOR 3
4100#define CTA_DB_SPEAKER 4
4101#define CTA_DB_EXTENDED_TAG 7
4102
4103/* CTA-861-H Table 62 - CTA Extended Tag Codes */
4104#define CTA_EXT_DB_VIDEO_CAP 0
4105#define CTA_EXT_DB_VENDOR 1
4106#define CTA_EXT_DB_HDR_STATIC_METADATA 6
4107#define CTA_EXT_DB_420_VIDEO_DATA 14
4108#define CTA_EXT_DB_420_VIDEO_CAP_MAP 15
4109#define CTA_EXT_DB_HF_EEODB 0x78
4110#define CTA_EXT_DB_HF_SCDB 0x79
4111
4112#define EDID_BASIC_AUDIO (1 << 6)
4113#define EDID_CEA_YCRCB444 (1 << 5)
4114#define EDID_CEA_YCRCB422 (1 << 4)
4115#define EDID_CEA_VCDB_QS (1 << 6)
4116
4117/*
4118 * Search EDID for CEA extension block.
4119 *
4120 * FIXME: Prefer not returning pointers to raw EDID data.
4121 */
4122const u8 *drm_find_edid_extension(const struct drm_edid *drm_edid,
4123 int ext_id, int *ext_index)
4124{
4125 const u8 *edid_ext = NULL;
4126 int i;
4127
4128 /* No EDID or EDID extensions */
4129 if (!drm_edid || !drm_edid_extension_block_count(drm_edid))
4130 return NULL;
4131
4132 /* Find CEA extension */
4133 for (i = *ext_index; i < drm_edid_extension_block_count(drm_edid); i++) {
4134 edid_ext = drm_edid_extension_block_data(drm_edid, i);
4135 if (edid_block_tag(edid_ext) == ext_id)
4136 break;
4137 }
4138
4139 if (i >= drm_edid_extension_block_count(drm_edid))
4140 return NULL;
4141
4142 *ext_index = i + 1;
4143
4144 return edid_ext;
4145}
4146
4147/* Return true if the EDID has a CTA extension or a DisplayID CTA data block */
4148static bool drm_edid_has_cta_extension(const struct drm_edid *drm_edid)
4149{
4150 const struct displayid_block *block;
4151 struct displayid_iter iter;
4152 int ext_index = 0;
4153 bool found = false;
4154
4155 /* Look for a top level CEA extension block */
4156 if (drm_find_edid_extension(drm_edid, CEA_EXT, &ext_index))
4157 return true;
4158
4159 /* CEA blocks can also be found embedded in a DisplayID block */
4160 displayid_iter_edid_begin(drm_edid, &iter);
4161 displayid_iter_for_each(block, &iter) {
4162 if (block->tag == DATA_BLOCK_CTA) {
4163 found = true;
4164 break;
4165 }
4166 }
4167 displayid_iter_end(&iter);
4168
4169 return found;
4170}
4171
4172static __always_inline const struct drm_display_mode *cea_mode_for_vic(u8 vic)
4173{
4174 BUILD_BUG_ON(1 + ARRAY_SIZE(edid_cea_modes_1) - 1 != 127);
4175 BUILD_BUG_ON(193 + ARRAY_SIZE(edid_cea_modes_193) - 1 != 219);
4176
4177 if (vic >= 1 && vic < 1 + ARRAY_SIZE(edid_cea_modes_1))
4178 return &edid_cea_modes_1[vic - 1];
4179 if (vic >= 193 && vic < 193 + ARRAY_SIZE(edid_cea_modes_193))
4180 return &edid_cea_modes_193[vic - 193];
4181 return NULL;
4182}
4183
4184static u8 cea_num_vics(void)
4185{
4186 return 193 + ARRAY_SIZE(edid_cea_modes_193);
4187}
4188
4189static u8 cea_next_vic(u8 vic)
4190{
4191 if (++vic == 1 + ARRAY_SIZE(edid_cea_modes_1))
4192 vic = 193;
4193 return vic;
4194}
4195
4196/*
4197 * Calculate the alternate clock for the CEA mode
4198 * (60Hz vs. 59.94Hz etc.)
4199 */
4200static unsigned int
4201cea_mode_alternate_clock(const struct drm_display_mode *cea_mode)
4202{
4203 unsigned int clock = cea_mode->clock;
4204
4205 if (drm_mode_vrefresh(cea_mode) % 6 != 0)
4206 return clock;
4207
4208 /*
4209 * edid_cea_modes contains the 59.94Hz
4210 * variant for 240 and 480 line modes,
4211 * and the 60Hz variant otherwise.
4212 */
4213 if (cea_mode->vdisplay == 240 || cea_mode->vdisplay == 480)
4214 clock = DIV_ROUND_CLOSEST(clock * 1001, 1000);
4215 else
4216 clock = DIV_ROUND_CLOSEST(clock * 1000, 1001);
4217
4218 return clock;
4219}
4220
4221static bool
4222cea_mode_alternate_timings(u8 vic, struct drm_display_mode *mode)
4223{
4224 /*
4225 * For certain VICs the spec allows the vertical
4226 * front porch to vary by one or two lines.
4227 *
4228 * cea_modes[] stores the variant with the shortest
4229 * vertical front porch. We can adjust the mode to
4230 * get the other variants by simply increasing the
4231 * vertical front porch length.
4232 */
4233 BUILD_BUG_ON(cea_mode_for_vic(8)->vtotal != 262 ||
4234 cea_mode_for_vic(9)->vtotal != 262 ||
4235 cea_mode_for_vic(12)->vtotal != 262 ||
4236 cea_mode_for_vic(13)->vtotal != 262 ||
4237 cea_mode_for_vic(23)->vtotal != 312 ||
4238 cea_mode_for_vic(24)->vtotal != 312 ||
4239 cea_mode_for_vic(27)->vtotal != 312 ||
4240 cea_mode_for_vic(28)->vtotal != 312);
4241
4242 if (((vic == 8 || vic == 9 ||
4243 vic == 12 || vic == 13) && mode->vtotal < 263) ||
4244 ((vic == 23 || vic == 24 ||
4245 vic == 27 || vic == 28) && mode->vtotal < 314)) {
4246 mode->vsync_start++;
4247 mode->vsync_end++;
4248 mode->vtotal++;
4249
4250 return true;
4251 }
4252
4253 return false;
4254}
4255
4256static u8 drm_match_cea_mode_clock_tolerance(const struct drm_display_mode *to_match,
4257 unsigned int clock_tolerance)
4258{
4259 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS;
4260 u8 vic;
4261
4262 if (!to_match->clock)
4263 return 0;
4264
4265 if (to_match->picture_aspect_ratio)
4266 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO;
4267
4268 for (vic = 1; vic < cea_num_vics(); vic = cea_next_vic(vic)) {
4269 struct drm_display_mode cea_mode;
4270 unsigned int clock1, clock2;
4271
4272 drm_mode_init(&cea_mode, cea_mode_for_vic(vic));
4273
4274 /* Check both 60Hz and 59.94Hz */
4275 clock1 = cea_mode.clock;
4276 clock2 = cea_mode_alternate_clock(&cea_mode);
4277
4278 if (abs(to_match->clock - clock1) > clock_tolerance &&
4279 abs(to_match->clock - clock2) > clock_tolerance)
4280 continue;
4281
4282 do {
4283 if (drm_mode_match(to_match, &cea_mode, match_flags))
4284 return vic;
4285 } while (cea_mode_alternate_timings(vic, &cea_mode));
4286 }
4287
4288 return 0;
4289}
4290
4291/**
4292 * drm_match_cea_mode - look for a CEA mode matching given mode
4293 * @to_match: display mode
4294 *
4295 * Return: The CEA Video ID (VIC) of the mode or 0 if it isn't a CEA-861
4296 * mode.
4297 */
4298u8 drm_match_cea_mode(const struct drm_display_mode *to_match)
4299{
4300 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS;
4301 u8 vic;
4302
4303 if (!to_match->clock)
4304 return 0;
4305
4306 if (to_match->picture_aspect_ratio)
4307 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO;
4308
4309 for (vic = 1; vic < cea_num_vics(); vic = cea_next_vic(vic)) {
4310 struct drm_display_mode cea_mode;
4311 unsigned int clock1, clock2;
4312
4313 drm_mode_init(&cea_mode, cea_mode_for_vic(vic));
4314
4315 /* Check both 60Hz and 59.94Hz */
4316 clock1 = cea_mode.clock;
4317 clock2 = cea_mode_alternate_clock(&cea_mode);
4318
4319 if (KHZ2PICOS(to_match->clock) != KHZ2PICOS(clock1) &&
4320 KHZ2PICOS(to_match->clock) != KHZ2PICOS(clock2))
4321 continue;
4322
4323 do {
4324 if (drm_mode_match(to_match, &cea_mode, match_flags))
4325 return vic;
4326 } while (cea_mode_alternate_timings(vic, &cea_mode));
4327 }
4328
4329 return 0;
4330}
4331EXPORT_SYMBOL(drm_match_cea_mode);
4332
4333static bool drm_valid_cea_vic(u8 vic)
4334{
4335 return cea_mode_for_vic(vic) != NULL;
4336}
4337
4338static enum hdmi_picture_aspect drm_get_cea_aspect_ratio(const u8 video_code)
4339{
4340 const struct drm_display_mode *mode = cea_mode_for_vic(video_code);
4341
4342 if (mode)
4343 return mode->picture_aspect_ratio;
4344
4345 return HDMI_PICTURE_ASPECT_NONE;
4346}
4347
4348static enum hdmi_picture_aspect drm_get_hdmi_aspect_ratio(const u8 video_code)
4349{
4350 return edid_4k_modes[video_code].picture_aspect_ratio;
4351}
4352
4353/*
4354 * Calculate the alternate clock for HDMI modes (those from the HDMI vendor
4355 * specific block).
4356 */
4357static unsigned int
4358hdmi_mode_alternate_clock(const struct drm_display_mode *hdmi_mode)
4359{
4360 return cea_mode_alternate_clock(hdmi_mode);
4361}
4362
4363static u8 drm_match_hdmi_mode_clock_tolerance(const struct drm_display_mode *to_match,
4364 unsigned int clock_tolerance)
4365{
4366 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS;
4367 u8 vic;
4368
4369 if (!to_match->clock)
4370 return 0;
4371
4372 if (to_match->picture_aspect_ratio)
4373 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO;
4374
4375 for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) {
4376 const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic];
4377 unsigned int clock1, clock2;
4378
4379 /* Make sure to also match alternate clocks */
4380 clock1 = hdmi_mode->clock;
4381 clock2 = hdmi_mode_alternate_clock(hdmi_mode);
4382
4383 if (abs(to_match->clock - clock1) > clock_tolerance &&
4384 abs(to_match->clock - clock2) > clock_tolerance)
4385 continue;
4386
4387 if (drm_mode_match(to_match, hdmi_mode, match_flags))
4388 return vic;
4389 }
4390
4391 return 0;
4392}
4393
4394/*
4395 * drm_match_hdmi_mode - look for a HDMI mode matching given mode
4396 * @to_match: display mode
4397 *
4398 * An HDMI mode is one defined in the HDMI vendor specific block.
4399 *
4400 * Returns the HDMI Video ID (VIC) of the mode or 0 if it isn't one.
4401 */
4402static u8 drm_match_hdmi_mode(const struct drm_display_mode *to_match)
4403{
4404 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS;
4405 u8 vic;
4406
4407 if (!to_match->clock)
4408 return 0;
4409
4410 if (to_match->picture_aspect_ratio)
4411 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO;
4412
4413 for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) {
4414 const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic];
4415 unsigned int clock1, clock2;
4416
4417 /* Make sure to also match alternate clocks */
4418 clock1 = hdmi_mode->clock;
4419 clock2 = hdmi_mode_alternate_clock(hdmi_mode);
4420
4421 if ((KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock1) ||
4422 KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock2)) &&
4423 drm_mode_match(to_match, hdmi_mode, match_flags))
4424 return vic;
4425 }
4426 return 0;
4427}
4428
4429static bool drm_valid_hdmi_vic(u8 vic)
4430{
4431 return vic > 0 && vic < ARRAY_SIZE(edid_4k_modes);
4432}
4433
4434static int add_alternate_cea_modes(struct drm_connector *connector,
4435 const struct drm_edid *drm_edid)
4436{
4437 struct drm_device *dev = connector->dev;
4438 struct drm_display_mode *mode, *tmp;
4439 LIST_HEAD(list);
4440 int modes = 0;
4441
4442 /* Don't add CTA modes if the CTA extension block is missing */
4443 if (!drm_edid_has_cta_extension(drm_edid))
4444 return 0;
4445
4446 /*
4447 * Go through all probed modes and create a new mode
4448 * with the alternate clock for certain CEA modes.
4449 */
4450 list_for_each_entry(mode, &connector->probed_modes, head) {
4451 const struct drm_display_mode *cea_mode = NULL;
4452 struct drm_display_mode *newmode;
4453 u8 vic = drm_match_cea_mode(mode);
4454 unsigned int clock1, clock2;
4455
4456 if (drm_valid_cea_vic(vic)) {
4457 cea_mode = cea_mode_for_vic(vic);
4458 clock2 = cea_mode_alternate_clock(cea_mode);
4459 } else {
4460 vic = drm_match_hdmi_mode(mode);
4461 if (drm_valid_hdmi_vic(vic)) {
4462 cea_mode = &edid_4k_modes[vic];
4463 clock2 = hdmi_mode_alternate_clock(cea_mode);
4464 }
4465 }
4466
4467 if (!cea_mode)
4468 continue;
4469
4470 clock1 = cea_mode->clock;
4471
4472 if (clock1 == clock2)
4473 continue;
4474
4475 if (mode->clock != clock1 && mode->clock != clock2)
4476 continue;
4477
4478 newmode = drm_mode_duplicate(dev, cea_mode);
4479 if (!newmode)
4480 continue;
4481
4482 /* Carry over the stereo flags */
4483 newmode->flags |= mode->flags & DRM_MODE_FLAG_3D_MASK;
4484
4485 /*
4486 * The current mode could be either variant. Make
4487 * sure to pick the "other" clock for the new mode.
4488 */
4489 if (mode->clock != clock1)
4490 newmode->clock = clock1;
4491 else
4492 newmode->clock = clock2;
4493
4494 list_add_tail(&newmode->head, &list);
4495 }
4496
4497 list_for_each_entry_safe(mode, tmp, &list, head) {
4498 list_del(&mode->head);
4499 drm_mode_probed_add(connector, mode);
4500 modes++;
4501 }
4502
4503 return modes;
4504}
4505
4506static u8 svd_to_vic(u8 svd)
4507{
4508 /* 0-6 bit vic, 7th bit native mode indicator */
4509 if ((svd >= 1 && svd <= 64) || (svd >= 129 && svd <= 192))
4510 return svd & 127;
4511
4512 return svd;
4513}
4514
4515/*
4516 * Return a display mode for the 0-based vic_index'th VIC across all CTA VDBs in
4517 * the EDID, or NULL on errors.
4518 */
4519static struct drm_display_mode *
4520drm_display_mode_from_vic_index(struct drm_connector *connector, int vic_index)
4521{
4522 const struct drm_display_info *info = &connector->display_info;
4523 struct drm_device *dev = connector->dev;
4524
4525 if (!info->vics || vic_index >= info->vics_len || !info->vics[vic_index])
4526 return NULL;
4527
4528 return drm_display_mode_from_cea_vic(dev, info->vics[vic_index]);
4529}
4530
4531/*
4532 * do_y420vdb_modes - Parse YCBCR 420 only modes
4533 * @connector: connector corresponding to the HDMI sink
4534 * @svds: start of the data block of CEA YCBCR 420 VDB
4535 * @len: length of the CEA YCBCR 420 VDB
4536 *
4537 * Parse the CEA-861-F YCBCR 420 Video Data Block (Y420VDB)
4538 * which contains modes which can be supported in YCBCR 420
4539 * output format only.
4540 */
4541static int do_y420vdb_modes(struct drm_connector *connector,
4542 const u8 *svds, u8 svds_len)
4543{
4544 struct drm_device *dev = connector->dev;
4545 int modes = 0, i;
4546
4547 for (i = 0; i < svds_len; i++) {
4548 u8 vic = svd_to_vic(svds[i]);
4549 struct drm_display_mode *newmode;
4550
4551 if (!drm_valid_cea_vic(vic))
4552 continue;
4553
4554 newmode = drm_mode_duplicate(dev, cea_mode_for_vic(vic));
4555 if (!newmode)
4556 break;
4557 drm_mode_probed_add(connector, newmode);
4558 modes++;
4559 }
4560
4561 return modes;
4562}
4563
4564/**
4565 * drm_display_mode_from_cea_vic() - return a mode for CEA VIC
4566 * @dev: DRM device
4567 * @video_code: CEA VIC of the mode
4568 *
4569 * Creates a new mode matching the specified CEA VIC.
4570 *
4571 * Returns: A new drm_display_mode on success or NULL on failure
4572 */
4573struct drm_display_mode *
4574drm_display_mode_from_cea_vic(struct drm_device *dev,
4575 u8 video_code)
4576{
4577 const struct drm_display_mode *cea_mode;
4578 struct drm_display_mode *newmode;
4579
4580 cea_mode = cea_mode_for_vic(video_code);
4581 if (!cea_mode)
4582 return NULL;
4583
4584 newmode = drm_mode_duplicate(dev, cea_mode);
4585 if (!newmode)
4586 return NULL;
4587
4588 return newmode;
4589}
4590EXPORT_SYMBOL(drm_display_mode_from_cea_vic);
4591
4592/* Add modes based on VICs parsed in parse_cta_vdb() */
4593static int add_cta_vdb_modes(struct drm_connector *connector)
4594{
4595 const struct drm_display_info *info = &connector->display_info;
4596 int i, modes = 0;
4597
4598 if (!info->vics)
4599 return 0;
4600
4601 for (i = 0; i < info->vics_len; i++) {
4602 struct drm_display_mode *mode;
4603
4604 mode = drm_display_mode_from_vic_index(connector, i);
4605 if (mode) {
4606 drm_mode_probed_add(connector, mode);
4607 modes++;
4608 }
4609 }
4610
4611 return modes;
4612}
4613
4614struct stereo_mandatory_mode {
4615 int width, height, vrefresh;
4616 unsigned int flags;
4617};
4618
4619static const struct stereo_mandatory_mode stereo_mandatory_modes[] = {
4620 { 1920, 1080, 24, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM },
4621 { 1920, 1080, 24, DRM_MODE_FLAG_3D_FRAME_PACKING },
4622 { 1920, 1080, 50,
4623 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF },
4624 { 1920, 1080, 60,
4625 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF },
4626 { 1280, 720, 50, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM },
4627 { 1280, 720, 50, DRM_MODE_FLAG_3D_FRAME_PACKING },
4628 { 1280, 720, 60, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM },
4629 { 1280, 720, 60, DRM_MODE_FLAG_3D_FRAME_PACKING }
4630};
4631
4632static bool
4633stereo_match_mandatory(const struct drm_display_mode *mode,
4634 const struct stereo_mandatory_mode *stereo_mode)
4635{
4636 unsigned int interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE;
4637
4638 return mode->hdisplay == stereo_mode->width &&
4639 mode->vdisplay == stereo_mode->height &&
4640 interlaced == (stereo_mode->flags & DRM_MODE_FLAG_INTERLACE) &&
4641 drm_mode_vrefresh(mode) == stereo_mode->vrefresh;
4642}
4643
4644static int add_hdmi_mandatory_stereo_modes(struct drm_connector *connector)
4645{
4646 struct drm_device *dev = connector->dev;
4647 const struct drm_display_mode *mode;
4648 struct list_head stereo_modes;
4649 int modes = 0, i;
4650
4651 INIT_LIST_HEAD(&stereo_modes);
4652
4653 list_for_each_entry(mode, &connector->probed_modes, head) {
4654 for (i = 0; i < ARRAY_SIZE(stereo_mandatory_modes); i++) {
4655 const struct stereo_mandatory_mode *mandatory;
4656 struct drm_display_mode *new_mode;
4657
4658 if (!stereo_match_mandatory(mode,
4659 &stereo_mandatory_modes[i]))
4660 continue;
4661
4662 mandatory = &stereo_mandatory_modes[i];
4663 new_mode = drm_mode_duplicate(dev, mode);
4664 if (!new_mode)
4665 continue;
4666
4667 new_mode->flags |= mandatory->flags;
4668 list_add_tail(&new_mode->head, &stereo_modes);
4669 modes++;
4670 }
4671 }
4672
4673 list_splice_tail(&stereo_modes, &connector->probed_modes);
4674
4675 return modes;
4676}
4677
4678static int add_hdmi_mode(struct drm_connector *connector, u8 vic)
4679{
4680 struct drm_device *dev = connector->dev;
4681 struct drm_display_mode *newmode;
4682
4683 if (!drm_valid_hdmi_vic(vic)) {
4684 drm_err(connector->dev, "[CONNECTOR:%d:%s] Unknown HDMI VIC: %d\n",
4685 connector->base.id, connector->name, vic);
4686 return 0;
4687 }
4688
4689 newmode = drm_mode_duplicate(dev, &edid_4k_modes[vic]);
4690 if (!newmode)
4691 return 0;
4692
4693 drm_mode_probed_add(connector, newmode);
4694
4695 return 1;
4696}
4697
4698static int add_3d_struct_modes(struct drm_connector *connector, u16 structure,
4699 int vic_index)
4700{
4701 struct drm_display_mode *newmode;
4702 int modes = 0;
4703
4704 if (structure & (1 << 0)) {
4705 newmode = drm_display_mode_from_vic_index(connector, vic_index);
4706 if (newmode) {
4707 newmode->flags |= DRM_MODE_FLAG_3D_FRAME_PACKING;
4708 drm_mode_probed_add(connector, newmode);
4709 modes++;
4710 }
4711 }
4712 if (structure & (1 << 6)) {
4713 newmode = drm_display_mode_from_vic_index(connector, vic_index);
4714 if (newmode) {
4715 newmode->flags |= DRM_MODE_FLAG_3D_TOP_AND_BOTTOM;
4716 drm_mode_probed_add(connector, newmode);
4717 modes++;
4718 }
4719 }
4720 if (structure & (1 << 8)) {
4721 newmode = drm_display_mode_from_vic_index(connector, vic_index);
4722 if (newmode) {
4723 newmode->flags |= DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF;
4724 drm_mode_probed_add(connector, newmode);
4725 modes++;
4726 }
4727 }
4728
4729 return modes;
4730}
4731
4732static bool hdmi_vsdb_latency_present(const u8 *db)
4733{
4734 return db[8] & BIT(7);
4735}
4736
4737static bool hdmi_vsdb_i_latency_present(const u8 *db)
4738{
4739 return hdmi_vsdb_latency_present(db) && db[8] & BIT(6);
4740}
4741
4742static int hdmi_vsdb_latency_length(const u8 *db)
4743{
4744 if (hdmi_vsdb_i_latency_present(db))
4745 return 4;
4746 else if (hdmi_vsdb_latency_present(db))
4747 return 2;
4748 else
4749 return 0;
4750}
4751
4752/*
4753 * do_hdmi_vsdb_modes - Parse the HDMI Vendor Specific data block
4754 * @connector: connector corresponding to the HDMI sink
4755 * @db: start of the CEA vendor specific block
4756 * @len: length of the CEA block payload, ie. one can access up to db[len]
4757 *
4758 * Parses the HDMI VSDB looking for modes to add to @connector. This function
4759 * also adds the stereo 3d modes when applicable.
4760 */
4761static int
4762do_hdmi_vsdb_modes(struct drm_connector *connector, const u8 *db, u8 len)
4763{
4764 int modes = 0, offset = 0, i, multi_present = 0, multi_len;
4765 u8 vic_len, hdmi_3d_len = 0;
4766 u16 mask;
4767 u16 structure_all;
4768
4769 if (len < 8)
4770 goto out;
4771
4772 /* no HDMI_Video_Present */
4773 if (!(db[8] & (1 << 5)))
4774 goto out;
4775
4776 offset += hdmi_vsdb_latency_length(db);
4777
4778 /* the declared length is not long enough for the 2 first bytes
4779 * of additional video format capabilities */
4780 if (len < (8 + offset + 2))
4781 goto out;
4782
4783 /* 3D_Present */
4784 offset++;
4785 if (db[8 + offset] & (1 << 7)) {
4786 modes += add_hdmi_mandatory_stereo_modes(connector);
4787
4788 /* 3D_Multi_present */
4789 multi_present = (db[8 + offset] & 0x60) >> 5;
4790 }
4791
4792 offset++;
4793 vic_len = db[8 + offset] >> 5;
4794 hdmi_3d_len = db[8 + offset] & 0x1f;
4795
4796 for (i = 0; i < vic_len && len >= (9 + offset + i); i++) {
4797 u8 vic;
4798
4799 vic = db[9 + offset + i];
4800 modes += add_hdmi_mode(connector, vic);
4801 }
4802 offset += 1 + vic_len;
4803
4804 if (multi_present == 1)
4805 multi_len = 2;
4806 else if (multi_present == 2)
4807 multi_len = 4;
4808 else
4809 multi_len = 0;
4810
4811 if (len < (8 + offset + hdmi_3d_len - 1))
4812 goto out;
4813
4814 if (hdmi_3d_len < multi_len)
4815 goto out;
4816
4817 if (multi_present == 1 || multi_present == 2) {
4818 /* 3D_Structure_ALL */
4819 structure_all = (db[8 + offset] << 8) | db[9 + offset];
4820
4821 /* check if 3D_MASK is present */
4822 if (multi_present == 2)
4823 mask = (db[10 + offset] << 8) | db[11 + offset];
4824 else
4825 mask = 0xffff;
4826
4827 for (i = 0; i < 16; i++) {
4828 if (mask & (1 << i))
4829 modes += add_3d_struct_modes(connector,
4830 structure_all, i);
4831 }
4832 }
4833
4834 offset += multi_len;
4835
4836 for (i = 0; i < (hdmi_3d_len - multi_len); i++) {
4837 int vic_index;
4838 struct drm_display_mode *newmode = NULL;
4839 unsigned int newflag = 0;
4840 bool detail_present;
4841
4842 detail_present = ((db[8 + offset + i] & 0x0f) > 7);
4843
4844 if (detail_present && (i + 1 == hdmi_3d_len - multi_len))
4845 break;
4846
4847 /* 2D_VIC_order_X */
4848 vic_index = db[8 + offset + i] >> 4;
4849
4850 /* 3D_Structure_X */
4851 switch (db[8 + offset + i] & 0x0f) {
4852 case 0:
4853 newflag = DRM_MODE_FLAG_3D_FRAME_PACKING;
4854 break;
4855 case 6:
4856 newflag = DRM_MODE_FLAG_3D_TOP_AND_BOTTOM;
4857 break;
4858 case 8:
4859 /* 3D_Detail_X */
4860 if ((db[9 + offset + i] >> 4) == 1)
4861 newflag = DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF;
4862 break;
4863 }
4864
4865 if (newflag != 0) {
4866 newmode = drm_display_mode_from_vic_index(connector,
4867 vic_index);
4868
4869 if (newmode) {
4870 newmode->flags |= newflag;
4871 drm_mode_probed_add(connector, newmode);
4872 modes++;
4873 }
4874 }
4875
4876 if (detail_present)
4877 i++;
4878 }
4879
4880out:
4881 return modes;
4882}
4883
4884static int
4885cea_revision(const u8 *cea)
4886{
4887 /*
4888 * FIXME is this correct for the DispID variant?
4889 * The DispID spec doesn't really specify whether
4890 * this is the revision of the CEA extension or
4891 * the DispID CEA data block. And the only value
4892 * given as an example is 0.
4893 */
4894 return cea[1];
4895}
4896
4897/*
4898 * CTA Data Block iterator.
4899 *
4900 * Iterate through all CTA Data Blocks in both EDID CTA Extensions and DisplayID
4901 * CTA Data Blocks.
4902 *
4903 * struct cea_db *db:
4904 * struct cea_db_iter iter;
4905 *
4906 * cea_db_iter_edid_begin(edid, &iter);
4907 * cea_db_iter_for_each(db, &iter) {
4908 * // do stuff with db
4909 * }
4910 * cea_db_iter_end(&iter);
4911 */
4912struct cea_db_iter {
4913 struct drm_edid_iter edid_iter;
4914 struct displayid_iter displayid_iter;
4915
4916 /* Current Data Block Collection. */
4917 const u8 *collection;
4918
4919 /* Current Data Block index in current collection. */
4920 int index;
4921
4922 /* End index in current collection. */
4923 int end;
4924};
4925
4926/* CTA-861-H section 7.4 CTA Data BLock Collection */
4927struct cea_db {
4928 u8 tag_length;
4929 u8 data[];
4930} __packed;
4931
4932static int cea_db_tag(const struct cea_db *db)
4933{
4934 return db->tag_length >> 5;
4935}
4936
4937static int cea_db_payload_len(const void *_db)
4938{
4939 /* FIXME: Transition to passing struct cea_db * everywhere. */
4940 const struct cea_db *db = _db;
4941
4942 return db->tag_length & 0x1f;
4943}
4944
4945static const void *cea_db_data(const struct cea_db *db)
4946{
4947 return db->data;
4948}
4949
4950static bool cea_db_is_extended_tag(const struct cea_db *db, int tag)
4951{
4952 return cea_db_tag(db) == CTA_DB_EXTENDED_TAG &&
4953 cea_db_payload_len(db) >= 1 &&
4954 db->data[0] == tag;
4955}
4956
4957static bool cea_db_is_vendor(const struct cea_db *db, int vendor_oui)
4958{
4959 const u8 *data = cea_db_data(db);
4960
4961 return cea_db_tag(db) == CTA_DB_VENDOR &&
4962 cea_db_payload_len(db) >= 3 &&
4963 oui(data[2], data[1], data[0]) == vendor_oui;
4964}
4965
4966static void cea_db_iter_edid_begin(const struct drm_edid *drm_edid,
4967 struct cea_db_iter *iter)
4968{
4969 memset(iter, 0, sizeof(*iter));
4970
4971 drm_edid_iter_begin(drm_edid, &iter->edid_iter);
4972 displayid_iter_edid_begin(drm_edid, &iter->displayid_iter);
4973}
4974
4975static const struct cea_db *
4976__cea_db_iter_current_block(const struct cea_db_iter *iter)
4977{
4978 const struct cea_db *db;
4979
4980 if (!iter->collection)
4981 return NULL;
4982
4983 db = (const struct cea_db *)&iter->collection[iter->index];
4984
4985 if (iter->index + sizeof(*db) <= iter->end &&
4986 iter->index + sizeof(*db) + cea_db_payload_len(db) <= iter->end)
4987 return db;
4988
4989 return NULL;
4990}
4991
4992/*
4993 * References:
4994 * - CTA-861-H section 7.3.3 CTA Extension Version 3
4995 */
4996static int cea_db_collection_size(const u8 *cta)
4997{
4998 u8 d = cta[2];
4999
5000 if (d < 4 || d > 127)
5001 return 0;
5002
5003 return d - 4;
5004}
5005
5006/*
5007 * References:
5008 * - VESA E-EDID v1.4
5009 * - CTA-861-H section 7.3.3 CTA Extension Version 3
5010 */
5011static const void *__cea_db_iter_edid_next(struct cea_db_iter *iter)
5012{
5013 const u8 *ext;
5014
5015 drm_edid_iter_for_each(ext, &iter->edid_iter) {
5016 int size;
5017
5018 /* Only support CTA Extension revision 3+ */
5019 if (ext[0] != CEA_EXT || cea_revision(ext) < 3)
5020 continue;
5021
5022 size = cea_db_collection_size(ext);
5023 if (!size)
5024 continue;
5025
5026 iter->index = 4;
5027 iter->end = iter->index + size;
5028
5029 return ext;
5030 }
5031
5032 return NULL;
5033}
5034
5035/*
5036 * References:
5037 * - DisplayID v1.3 Appendix C: CEA Data Block within a DisplayID Data Block
5038 * - DisplayID v2.0 section 4.10 CTA DisplayID Data Block
5039 *
5040 * Note that the above do not specify any connection between DisplayID Data
5041 * Block revision and CTA Extension versions.
5042 */
5043static const void *__cea_db_iter_displayid_next(struct cea_db_iter *iter)
5044{
5045 const struct displayid_block *block;
5046
5047 displayid_iter_for_each(block, &iter->displayid_iter) {
5048 if (block->tag != DATA_BLOCK_CTA)
5049 continue;
5050
5051 /*
5052 * The displayid iterator has already verified the block bounds
5053 * in displayid_iter_block().
5054 */
5055 iter->index = sizeof(*block);
5056 iter->end = iter->index + block->num_bytes;
5057
5058 return block;
5059 }
5060
5061 return NULL;
5062}
5063
5064static const struct cea_db *__cea_db_iter_next(struct cea_db_iter *iter)
5065{
5066 const struct cea_db *db;
5067
5068 if (iter->collection) {
5069 /* Current collection should always be valid. */
5070 db = __cea_db_iter_current_block(iter);
5071 if (WARN_ON(!db)) {
5072 iter->collection = NULL;
5073 return NULL;
5074 }
5075
5076 /* Next block in CTA Data Block Collection */
5077 iter->index += sizeof(*db) + cea_db_payload_len(db);
5078
5079 db = __cea_db_iter_current_block(iter);
5080 if (db)
5081 return db;
5082 }
5083
5084 for (;;) {
5085 /*
5086 * Find the next CTA Data Block Collection. First iterate all
5087 * the EDID CTA Extensions, then all the DisplayID CTA blocks.
5088 *
5089 * Per DisplayID v1.3 Appendix B: DisplayID as an EDID
5090 * Extension, it's recommended that DisplayID extensions are
5091 * exposed after all of the CTA Extensions.
5092 */
5093 iter->collection = __cea_db_iter_edid_next(iter);
5094 if (!iter->collection)
5095 iter->collection = __cea_db_iter_displayid_next(iter);
5096
5097 if (!iter->collection)
5098 return NULL;
5099
5100 db = __cea_db_iter_current_block(iter);
5101 if (db)
5102 return db;
5103 }
5104}
5105
5106#define cea_db_iter_for_each(__db, __iter) \
5107 while (((__db) = __cea_db_iter_next(__iter)))
5108
5109static void cea_db_iter_end(struct cea_db_iter *iter)
5110{
5111 displayid_iter_end(&iter->displayid_iter);
5112 drm_edid_iter_end(&iter->edid_iter);
5113
5114 memset(iter, 0, sizeof(*iter));
5115}
5116
5117static bool cea_db_is_hdmi_vsdb(const struct cea_db *db)
5118{
5119 return cea_db_is_vendor(db, HDMI_IEEE_OUI) &&
5120 cea_db_payload_len(db) >= 5;
5121}
5122
5123static bool cea_db_is_hdmi_forum_vsdb(const struct cea_db *db)
5124{
5125 return cea_db_is_vendor(db, HDMI_FORUM_IEEE_OUI) &&
5126 cea_db_payload_len(db) >= 7;
5127}
5128
5129static bool cea_db_is_hdmi_forum_eeodb(const void *db)
5130{
5131 return cea_db_is_extended_tag(db, CTA_EXT_DB_HF_EEODB) &&
5132 cea_db_payload_len(db) >= 2;
5133}
5134
5135static bool cea_db_is_microsoft_vsdb(const struct cea_db *db)
5136{
5137 return cea_db_is_vendor(db, MICROSOFT_IEEE_OUI) &&
5138 cea_db_payload_len(db) == 21;
5139}
5140
5141static bool cea_db_is_vcdb(const struct cea_db *db)
5142{
5143 return cea_db_is_extended_tag(db, CTA_EXT_DB_VIDEO_CAP) &&
5144 cea_db_payload_len(db) == 2;
5145}
5146
5147static bool cea_db_is_hdmi_forum_scdb(const struct cea_db *db)
5148{
5149 return cea_db_is_extended_tag(db, CTA_EXT_DB_HF_SCDB) &&
5150 cea_db_payload_len(db) >= 7;
5151}
5152
5153static bool cea_db_is_y420cmdb(const struct cea_db *db)
5154{
5155 return cea_db_is_extended_tag(db, CTA_EXT_DB_420_VIDEO_CAP_MAP);
5156}
5157
5158static bool cea_db_is_y420vdb(const struct cea_db *db)
5159{
5160 return cea_db_is_extended_tag(db, CTA_EXT_DB_420_VIDEO_DATA);
5161}
5162
5163static bool cea_db_is_hdmi_hdr_metadata_block(const struct cea_db *db)
5164{
5165 return cea_db_is_extended_tag(db, CTA_EXT_DB_HDR_STATIC_METADATA) &&
5166 cea_db_payload_len(db) >= 3;
5167}
5168
5169/*
5170 * Get the HF-EEODB override extension block count from EDID.
5171 *
5172 * The passed in EDID may be partially read, as long as it has at least two
5173 * blocks (base block and one extension block) if EDID extension count is > 0.
5174 *
5175 * Note that this is *not* how you should parse CTA Data Blocks in general; this
5176 * is only to handle partially read EDIDs. Normally, use the CTA Data Block
5177 * iterators instead.
5178 *
5179 * References:
5180 * - HDMI 2.1 section 10.3.6 HDMI Forum EDID Extension Override Data Block
5181 */
5182static int edid_hfeeodb_extension_block_count(const struct edid *edid)
5183{
5184 const u8 *cta;
5185
5186 /* No extensions according to base block, no HF-EEODB. */
5187 if (!edid_extension_block_count(edid))
5188 return 0;
5189
5190 /* HF-EEODB is always in the first EDID extension block only */
5191 cta = edid_extension_block_data(edid, 0);
5192 if (edid_block_tag(cta) != CEA_EXT || cea_revision(cta) < 3)
5193 return 0;
5194
5195 /* Need to have the data block collection, and at least 3 bytes. */
5196 if (cea_db_collection_size(cta) < 3)
5197 return 0;
5198
5199 /*
5200 * Sinks that include the HF-EEODB in their E-EDID shall include one and
5201 * only one instance of the HF-EEODB in the E-EDID, occupying bytes 4
5202 * through 6 of Block 1 of the E-EDID.
5203 */
5204 if (!cea_db_is_hdmi_forum_eeodb(&cta[4]))
5205 return 0;
5206
5207 return cta[4 + 2];
5208}
5209
5210/*
5211 * CTA-861 YCbCr 4:2:0 Capability Map Data Block (CTA Y420CMDB)
5212 *
5213 * Y420CMDB contains a bitmap which gives the index of CTA modes from CTA VDB,
5214 * which can support YCBCR 420 sampling output also (apart from RGB/YCBCR444
5215 * etc). For example, if the bit 0 in bitmap is set, first mode in VDB can
5216 * support YCBCR420 output too.
5217 */
5218static void parse_cta_y420cmdb(struct drm_connector *connector,
5219 const struct cea_db *db, u64 *y420cmdb_map)
5220{
5221 struct drm_display_info *info = &connector->display_info;
5222 int i, map_len = cea_db_payload_len(db) - 1;
5223 const u8 *data = cea_db_data(db) + 1;
5224 u64 map = 0;
5225
5226 if (map_len == 0) {
5227 /* All CEA modes support ycbcr420 sampling also.*/
5228 map = U64_MAX;
5229 goto out;
5230 }
5231
5232 /*
5233 * This map indicates which of the existing CEA block modes
5234 * from VDB can support YCBCR420 output too. So if bit=0 is
5235 * set, first mode from VDB can support YCBCR420 output too.
5236 * We will parse and keep this map, before parsing VDB itself
5237 * to avoid going through the same block again and again.
5238 *
5239 * Spec is not clear about max possible size of this block.
5240 * Clamping max bitmap block size at 8 bytes. Every byte can
5241 * address 8 CEA modes, in this way this map can address
5242 * 8*8 = first 64 SVDs.
5243 */
5244 if (WARN_ON_ONCE(map_len > 8))
5245 map_len = 8;
5246
5247 for (i = 0; i < map_len; i++)
5248 map |= (u64)data[i] << (8 * i);
5249
5250out:
5251 if (map)
5252 info->color_formats |= DRM_COLOR_FORMAT_YCBCR420;
5253
5254 *y420cmdb_map = map;
5255}
5256
5257static int add_cea_modes(struct drm_connector *connector,
5258 const struct drm_edid *drm_edid)
5259{
5260 const struct cea_db *db;
5261 struct cea_db_iter iter;
5262 int modes;
5263
5264 /* CTA VDB block VICs parsed earlier */
5265 modes = add_cta_vdb_modes(connector);
5266
5267 cea_db_iter_edid_begin(drm_edid, &iter);
5268 cea_db_iter_for_each(db, &iter) {
5269 if (cea_db_is_hdmi_vsdb(db)) {
5270 modes += do_hdmi_vsdb_modes(connector, (const u8 *)db,
5271 cea_db_payload_len(db));
5272 } else if (cea_db_is_y420vdb(db)) {
5273 const u8 *vdb420 = cea_db_data(db) + 1;
5274
5275 /* Add 4:2:0(only) modes present in EDID */
5276 modes += do_y420vdb_modes(connector, vdb420,
5277 cea_db_payload_len(db) - 1);
5278 }
5279 }
5280 cea_db_iter_end(&iter);
5281
5282 return modes;
5283}
5284
5285static void fixup_detailed_cea_mode_clock(struct drm_connector *connector,
5286 struct drm_display_mode *mode)
5287{
5288 const struct drm_display_mode *cea_mode;
5289 int clock1, clock2, clock;
5290 u8 vic;
5291 const char *type;
5292
5293 /*
5294 * allow 5kHz clock difference either way to account for
5295 * the 10kHz clock resolution limit of detailed timings.
5296 */
5297 vic = drm_match_cea_mode_clock_tolerance(mode, 5);
5298 if (drm_valid_cea_vic(vic)) {
5299 type = "CEA";
5300 cea_mode = cea_mode_for_vic(vic);
5301 clock1 = cea_mode->clock;
5302 clock2 = cea_mode_alternate_clock(cea_mode);
5303 } else {
5304 vic = drm_match_hdmi_mode_clock_tolerance(mode, 5);
5305 if (drm_valid_hdmi_vic(vic)) {
5306 type = "HDMI";
5307 cea_mode = &edid_4k_modes[vic];
5308 clock1 = cea_mode->clock;
5309 clock2 = hdmi_mode_alternate_clock(cea_mode);
5310 } else {
5311 return;
5312 }
5313 }
5314
5315 /* pick whichever is closest */
5316 if (abs(mode->clock - clock1) < abs(mode->clock - clock2))
5317 clock = clock1;
5318 else
5319 clock = clock2;
5320
5321 if (mode->clock == clock)
5322 return;
5323
5324 drm_dbg_kms(connector->dev,
5325 "[CONNECTOR:%d:%s] detailed mode matches %s VIC %d, adjusting clock %d -> %d\n",
5326 connector->base.id, connector->name,
5327 type, vic, mode->clock, clock);
5328 mode->clock = clock;
5329}
5330
5331static void drm_calculate_luminance_range(struct drm_connector *connector)
5332{
5333 struct hdr_static_metadata *hdr_metadata = &connector->hdr_sink_metadata.hdmi_type1;
5334 struct drm_luminance_range_info *luminance_range =
5335 &connector->display_info.luminance_range;
5336 static const u8 pre_computed_values[] = {
5337 50, 51, 52, 53, 55, 56, 57, 58, 59, 61, 62, 63, 65, 66, 68, 69,
5338 71, 72, 74, 75, 77, 79, 81, 82, 84, 86, 88, 90, 92, 94, 96, 98
5339 };
5340 u32 max_avg, min_cll, max, min, q, r;
5341
5342 if (!(hdr_metadata->metadata_type & BIT(HDMI_STATIC_METADATA_TYPE1)))
5343 return;
5344
5345 max_avg = hdr_metadata->max_fall;
5346 min_cll = hdr_metadata->min_cll;
5347
5348 /*
5349 * From the specification (CTA-861-G), for calculating the maximum
5350 * luminance we need to use:
5351 * Luminance = 50*2**(CV/32)
5352 * Where CV is a one-byte value.
5353 * For calculating this expression we may need float point precision;
5354 * to avoid this complexity level, we take advantage that CV is divided
5355 * by a constant. From the Euclids division algorithm, we know that CV
5356 * can be written as: CV = 32*q + r. Next, we replace CV in the
5357 * Luminance expression and get 50*(2**q)*(2**(r/32)), hence we just
5358 * need to pre-compute the value of r/32. For pre-computing the values
5359 * We just used the following Ruby line:
5360 * (0...32).each {|cv| puts (50*2**(cv/32.0)).round}
5361 * The results of the above expressions can be verified at
5362 * pre_computed_values.
5363 */
5364 q = max_avg >> 5;
5365 r = max_avg % 32;
5366 max = (1 << q) * pre_computed_values[r];
5367
5368 /* min luminance: maxLum * (CV/255)^2 / 100 */
5369 q = DIV_ROUND_CLOSEST(min_cll, 255);
5370 min = max * DIV_ROUND_CLOSEST((q * q), 100);
5371
5372 luminance_range->min_luminance = min;
5373 luminance_range->max_luminance = max;
5374}
5375
5376static uint8_t eotf_supported(const u8 *edid_ext)
5377{
5378 return edid_ext[2] &
5379 (BIT(HDMI_EOTF_TRADITIONAL_GAMMA_SDR) |
5380 BIT(HDMI_EOTF_TRADITIONAL_GAMMA_HDR) |
5381 BIT(HDMI_EOTF_SMPTE_ST2084) |
5382 BIT(HDMI_EOTF_BT_2100_HLG));
5383}
5384
5385static uint8_t hdr_metadata_type(const u8 *edid_ext)
5386{
5387 return edid_ext[3] &
5388 BIT(HDMI_STATIC_METADATA_TYPE1);
5389}
5390
5391static void
5392drm_parse_hdr_metadata_block(struct drm_connector *connector, const u8 *db)
5393{
5394 u16 len;
5395
5396 len = cea_db_payload_len(db);
5397
5398 connector->hdr_sink_metadata.hdmi_type1.eotf =
5399 eotf_supported(db);
5400 connector->hdr_sink_metadata.hdmi_type1.metadata_type =
5401 hdr_metadata_type(db);
5402
5403 if (len >= 4)
5404 connector->hdr_sink_metadata.hdmi_type1.max_cll = db[4];
5405 if (len >= 5)
5406 connector->hdr_sink_metadata.hdmi_type1.max_fall = db[5];
5407 if (len >= 6) {
5408 connector->hdr_sink_metadata.hdmi_type1.min_cll = db[6];
5409
5410 /* Calculate only when all values are available */
5411 drm_calculate_luminance_range(connector);
5412 }
5413}
5414
5415/* HDMI Vendor-Specific Data Block (HDMI VSDB, H14b-VSDB) */
5416static void
5417drm_parse_hdmi_vsdb_audio(struct drm_connector *connector, const u8 *db)
5418{
5419 u8 len = cea_db_payload_len(db);
5420
5421 if (len >= 6 && (db[6] & (1 << 7)))
5422 connector->eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_SUPPORTS_AI;
5423
5424 if (len >= 10 && hdmi_vsdb_latency_present(db)) {
5425 connector->latency_present[0] = true;
5426 connector->video_latency[0] = db[9];
5427 connector->audio_latency[0] = db[10];
5428 }
5429
5430 if (len >= 12 && hdmi_vsdb_i_latency_present(db)) {
5431 connector->latency_present[1] = true;
5432 connector->video_latency[1] = db[11];
5433 connector->audio_latency[1] = db[12];
5434 }
5435
5436 drm_dbg_kms(connector->dev,
5437 "[CONNECTOR:%d:%s] HDMI: latency present %d %d, video latency %d %d, audio latency %d %d\n",
5438 connector->base.id, connector->name,
5439 connector->latency_present[0], connector->latency_present[1],
5440 connector->video_latency[0], connector->video_latency[1],
5441 connector->audio_latency[0], connector->audio_latency[1]);
5442}
5443
5444static void
5445monitor_name(const struct detailed_timing *timing, void *data)
5446{
5447 const char **res = data;
5448
5449 if (!is_display_descriptor(timing, EDID_DETAIL_MONITOR_NAME))
5450 return;
5451
5452 *res = timing->data.other_data.data.str.str;
5453}
5454
5455static int get_monitor_name(const struct drm_edid *drm_edid, char name[13])
5456{
5457 const char *edid_name = NULL;
5458 int mnl;
5459
5460 if (!drm_edid || !name)
5461 return 0;
5462
5463 drm_for_each_detailed_block(drm_edid, monitor_name, &edid_name);
5464 for (mnl = 0; edid_name && mnl < 13; mnl++) {
5465 if (edid_name[mnl] == 0x0a)
5466 break;
5467
5468 name[mnl] = edid_name[mnl];
5469 }
5470
5471 return mnl;
5472}
5473
5474/**
5475 * drm_edid_get_monitor_name - fetch the monitor name from the edid
5476 * @edid: monitor EDID information
5477 * @name: pointer to a character array to hold the name of the monitor
5478 * @bufsize: The size of the name buffer (should be at least 14 chars.)
5479 *
5480 */
5481void drm_edid_get_monitor_name(const struct edid *edid, char *name, int bufsize)
5482{
5483 int name_length = 0;
5484
5485 if (bufsize <= 0)
5486 return;
5487
5488 if (edid) {
5489 char buf[13];
5490 struct drm_edid drm_edid = {
5491 .edid = edid,
5492 .size = edid_size(edid),
5493 };
5494
5495 name_length = min(get_monitor_name(&drm_edid, buf), bufsize - 1);
5496 memcpy(name, buf, name_length);
5497 }
5498
5499 name[name_length] = '\0';
5500}
5501EXPORT_SYMBOL(drm_edid_get_monitor_name);
5502
5503static void clear_eld(struct drm_connector *connector)
5504{
5505 memset(connector->eld, 0, sizeof(connector->eld));
5506
5507 connector->latency_present[0] = false;
5508 connector->latency_present[1] = false;
5509 connector->video_latency[0] = 0;
5510 connector->audio_latency[0] = 0;
5511 connector->video_latency[1] = 0;
5512 connector->audio_latency[1] = 0;
5513}
5514
5515/*
5516 * Get 3-byte SAD buffer from struct cea_sad.
5517 */
5518void drm_edid_cta_sad_get(const struct cea_sad *cta_sad, u8 *sad)
5519{
5520 sad[0] = cta_sad->format << 3 | cta_sad->channels;
5521 sad[1] = cta_sad->freq;
5522 sad[2] = cta_sad->byte2;
5523}
5524
5525/*
5526 * Set struct cea_sad from 3-byte SAD buffer.
5527 */
5528void drm_edid_cta_sad_set(struct cea_sad *cta_sad, const u8 *sad)
5529{
5530 cta_sad->format = (sad[0] & 0x78) >> 3;
5531 cta_sad->channels = sad[0] & 0x07;
5532 cta_sad->freq = sad[1] & 0x7f;
5533 cta_sad->byte2 = sad[2];
5534}
5535
5536/*
5537 * drm_edid_to_eld - build ELD from EDID
5538 * @connector: connector corresponding to the HDMI/DP sink
5539 * @drm_edid: EDID to parse
5540 *
5541 * Fill the ELD (EDID-Like Data) buffer for passing to the audio driver. The
5542 * HDCP and Port_ID ELD fields are left for the graphics driver to fill in.
5543 */
5544static void drm_edid_to_eld(struct drm_connector *connector,
5545 const struct drm_edid *drm_edid)
5546{
5547 const struct drm_display_info *info = &connector->display_info;
5548 const struct cea_db *db;
5549 struct cea_db_iter iter;
5550 uint8_t *eld = connector->eld;
5551 int total_sad_count = 0;
5552 int mnl;
5553
5554 if (!drm_edid)
5555 return;
5556
5557 mnl = get_monitor_name(drm_edid, &eld[DRM_ELD_MONITOR_NAME_STRING]);
5558 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] ELD monitor %s\n",
5559 connector->base.id, connector->name,
5560 &eld[DRM_ELD_MONITOR_NAME_STRING]);
5561
5562 eld[DRM_ELD_CEA_EDID_VER_MNL] = info->cea_rev << DRM_ELD_CEA_EDID_VER_SHIFT;
5563 eld[DRM_ELD_CEA_EDID_VER_MNL] |= mnl;
5564
5565 eld[DRM_ELD_VER] = DRM_ELD_VER_CEA861D;
5566
5567 eld[DRM_ELD_MANUFACTURER_NAME0] = drm_edid->edid->mfg_id[0];
5568 eld[DRM_ELD_MANUFACTURER_NAME1] = drm_edid->edid->mfg_id[1];
5569 eld[DRM_ELD_PRODUCT_CODE0] = drm_edid->edid->prod_code[0];
5570 eld[DRM_ELD_PRODUCT_CODE1] = drm_edid->edid->prod_code[1];
5571
5572 cea_db_iter_edid_begin(drm_edid, &iter);
5573 cea_db_iter_for_each(db, &iter) {
5574 const u8 *data = cea_db_data(db);
5575 int len = cea_db_payload_len(db);
5576 int sad_count;
5577
5578 switch (cea_db_tag(db)) {
5579 case CTA_DB_AUDIO:
5580 /* Audio Data Block, contains SADs */
5581 sad_count = min(len / 3, 15 - total_sad_count);
5582 if (sad_count >= 1)
5583 memcpy(&eld[DRM_ELD_CEA_SAD(mnl, total_sad_count)],
5584 data, sad_count * 3);
5585 total_sad_count += sad_count;
5586 break;
5587 case CTA_DB_SPEAKER:
5588 /* Speaker Allocation Data Block */
5589 if (len >= 1)
5590 eld[DRM_ELD_SPEAKER] = data[0];
5591 break;
5592 case CTA_DB_VENDOR:
5593 /* HDMI Vendor-Specific Data Block */
5594 if (cea_db_is_hdmi_vsdb(db))
5595 drm_parse_hdmi_vsdb_audio(connector, (const u8 *)db);
5596 break;
5597 default:
5598 break;
5599 }
5600 }
5601 cea_db_iter_end(&iter);
5602
5603 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= total_sad_count << DRM_ELD_SAD_COUNT_SHIFT;
5604
5605 if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
5606 connector->connector_type == DRM_MODE_CONNECTOR_eDP)
5607 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_CONN_TYPE_DP;
5608 else
5609 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_CONN_TYPE_HDMI;
5610
5611 eld[DRM_ELD_BASELINE_ELD_LEN] =
5612 DIV_ROUND_UP(drm_eld_calc_baseline_block_size(eld), 4);
5613
5614 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] ELD size %d, SAD count %d\n",
5615 connector->base.id, connector->name,
5616 drm_eld_size(eld), total_sad_count);
5617}
5618
5619static int _drm_edid_to_sad(const struct drm_edid *drm_edid,
5620 struct cea_sad **psads)
5621{
5622 const struct cea_db *db;
5623 struct cea_db_iter iter;
5624 int count = 0;
5625
5626 cea_db_iter_edid_begin(drm_edid, &iter);
5627 cea_db_iter_for_each(db, &iter) {
5628 if (cea_db_tag(db) == CTA_DB_AUDIO) {
5629 struct cea_sad *sads;
5630 int i;
5631
5632 count = cea_db_payload_len(db) / 3; /* SAD is 3B */
5633 sads = kcalloc(count, sizeof(*sads), GFP_KERNEL);
5634 *psads = sads;
5635 if (!sads)
5636 return -ENOMEM;
5637 for (i = 0; i < count; i++)
5638 drm_edid_cta_sad_set(&sads[i], &db->data[i * 3]);
5639 break;
5640 }
5641 }
5642 cea_db_iter_end(&iter);
5643
5644 DRM_DEBUG_KMS("Found %d Short Audio Descriptors\n", count);
5645
5646 return count;
5647}
5648
5649/**
5650 * drm_edid_to_sad - extracts SADs from EDID
5651 * @edid: EDID to parse
5652 * @sads: pointer that will be set to the extracted SADs
5653 *
5654 * Looks for CEA EDID block and extracts SADs (Short Audio Descriptors) from it.
5655 *
5656 * Note: The returned pointer needs to be freed using kfree().
5657 *
5658 * Return: The number of found SADs or negative number on error.
5659 */
5660int drm_edid_to_sad(const struct edid *edid, struct cea_sad **sads)
5661{
5662 struct drm_edid drm_edid;
5663
5664 return _drm_edid_to_sad(drm_edid_legacy_init(&drm_edid, edid), sads);
5665}
5666EXPORT_SYMBOL(drm_edid_to_sad);
5667
5668static int _drm_edid_to_speaker_allocation(const struct drm_edid *drm_edid,
5669 u8 **sadb)
5670{
5671 const struct cea_db *db;
5672 struct cea_db_iter iter;
5673 int count = 0;
5674
5675 cea_db_iter_edid_begin(drm_edid, &iter);
5676 cea_db_iter_for_each(db, &iter) {
5677 if (cea_db_tag(db) == CTA_DB_SPEAKER &&
5678 cea_db_payload_len(db) == 3) {
5679 *sadb = kmemdup(db->data, cea_db_payload_len(db),
5680 GFP_KERNEL);
5681 if (!*sadb)
5682 return -ENOMEM;
5683 count = cea_db_payload_len(db);
5684 break;
5685 }
5686 }
5687 cea_db_iter_end(&iter);
5688
5689 DRM_DEBUG_KMS("Found %d Speaker Allocation Data Blocks\n", count);
5690
5691 return count;
5692}
5693
5694/**
5695 * drm_edid_to_speaker_allocation - extracts Speaker Allocation Data Blocks from EDID
5696 * @edid: EDID to parse
5697 * @sadb: pointer to the speaker block
5698 *
5699 * Looks for CEA EDID block and extracts the Speaker Allocation Data Block from it.
5700 *
5701 * Note: The returned pointer needs to be freed using kfree().
5702 *
5703 * Return: The number of found Speaker Allocation Blocks or negative number on
5704 * error.
5705 */
5706int drm_edid_to_speaker_allocation(const struct edid *edid, u8 **sadb)
5707{
5708 struct drm_edid drm_edid;
5709
5710 return _drm_edid_to_speaker_allocation(drm_edid_legacy_init(&drm_edid, edid),
5711 sadb);
5712}
5713EXPORT_SYMBOL(drm_edid_to_speaker_allocation);
5714
5715/**
5716 * drm_av_sync_delay - compute the HDMI/DP sink audio-video sync delay
5717 * @connector: connector associated with the HDMI/DP sink
5718 * @mode: the display mode
5719 *
5720 * Return: The HDMI/DP sink's audio-video sync delay in milliseconds or 0 if
5721 * the sink doesn't support audio or video.
5722 */
5723int drm_av_sync_delay(struct drm_connector *connector,
5724 const struct drm_display_mode *mode)
5725{
5726 int i = !!(mode->flags & DRM_MODE_FLAG_INTERLACE);
5727 int a, v;
5728
5729 if (!connector->latency_present[0])
5730 return 0;
5731 if (!connector->latency_present[1])
5732 i = 0;
5733
5734 a = connector->audio_latency[i];
5735 v = connector->video_latency[i];
5736
5737 /*
5738 * HDMI/DP sink doesn't support audio or video?
5739 */
5740 if (a == 255 || v == 255)
5741 return 0;
5742
5743 /*
5744 * Convert raw EDID values to millisecond.
5745 * Treat unknown latency as 0ms.
5746 */
5747 if (a)
5748 a = min(2 * (a - 1), 500);
5749 if (v)
5750 v = min(2 * (v - 1), 500);
5751
5752 return max(v - a, 0);
5753}
5754EXPORT_SYMBOL(drm_av_sync_delay);
5755
5756static bool _drm_detect_hdmi_monitor(const struct drm_edid *drm_edid)
5757{
5758 const struct cea_db *db;
5759 struct cea_db_iter iter;
5760 bool hdmi = false;
5761
5762 /*
5763 * Because HDMI identifier is in Vendor Specific Block,
5764 * search it from all data blocks of CEA extension.
5765 */
5766 cea_db_iter_edid_begin(drm_edid, &iter);
5767 cea_db_iter_for_each(db, &iter) {
5768 if (cea_db_is_hdmi_vsdb(db)) {
5769 hdmi = true;
5770 break;
5771 }
5772 }
5773 cea_db_iter_end(&iter);
5774
5775 return hdmi;
5776}
5777
5778/**
5779 * drm_detect_hdmi_monitor - detect whether monitor is HDMI
5780 * @edid: monitor EDID information
5781 *
5782 * Parse the CEA extension according to CEA-861-B.
5783 *
5784 * Drivers that have added the modes parsed from EDID to drm_display_info
5785 * should use &drm_display_info.is_hdmi instead of calling this function.
5786 *
5787 * Return: True if the monitor is HDMI, false if not or unknown.
5788 */
5789bool drm_detect_hdmi_monitor(const struct edid *edid)
5790{
5791 struct drm_edid drm_edid;
5792
5793 return _drm_detect_hdmi_monitor(drm_edid_legacy_init(&drm_edid, edid));
5794}
5795EXPORT_SYMBOL(drm_detect_hdmi_monitor);
5796
5797static bool _drm_detect_monitor_audio(const struct drm_edid *drm_edid)
5798{
5799 struct drm_edid_iter edid_iter;
5800 const struct cea_db *db;
5801 struct cea_db_iter iter;
5802 const u8 *edid_ext;
5803 bool has_audio = false;
5804
5805 drm_edid_iter_begin(drm_edid, &edid_iter);
5806 drm_edid_iter_for_each(edid_ext, &edid_iter) {
5807 if (edid_ext[0] == CEA_EXT) {
5808 has_audio = edid_ext[3] & EDID_BASIC_AUDIO;
5809 if (has_audio)
5810 break;
5811 }
5812 }
5813 drm_edid_iter_end(&edid_iter);
5814
5815 if (has_audio) {
5816 DRM_DEBUG_KMS("Monitor has basic audio support\n");
5817 goto end;
5818 }
5819
5820 cea_db_iter_edid_begin(drm_edid, &iter);
5821 cea_db_iter_for_each(db, &iter) {
5822 if (cea_db_tag(db) == CTA_DB_AUDIO) {
5823 const u8 *data = cea_db_data(db);
5824 int i;
5825
5826 for (i = 0; i < cea_db_payload_len(db); i += 3)
5827 DRM_DEBUG_KMS("CEA audio format %d\n",
5828 (data[i] >> 3) & 0xf);
5829 has_audio = true;
5830 break;
5831 }
5832 }
5833 cea_db_iter_end(&iter);
5834
5835end:
5836 return has_audio;
5837}
5838
5839/**
5840 * drm_detect_monitor_audio - check monitor audio capability
5841 * @edid: EDID block to scan
5842 *
5843 * Monitor should have CEA extension block.
5844 * If monitor has 'basic audio', but no CEA audio blocks, it's 'basic
5845 * audio' only. If there is any audio extension block and supported
5846 * audio format, assume at least 'basic audio' support, even if 'basic
5847 * audio' is not defined in EDID.
5848 *
5849 * Return: True if the monitor supports audio, false otherwise.
5850 */
5851bool drm_detect_monitor_audio(const struct edid *edid)
5852{
5853 struct drm_edid drm_edid;
5854
5855 return _drm_detect_monitor_audio(drm_edid_legacy_init(&drm_edid, edid));
5856}
5857EXPORT_SYMBOL(drm_detect_monitor_audio);
5858
5859
5860/**
5861 * drm_default_rgb_quant_range - default RGB quantization range
5862 * @mode: display mode
5863 *
5864 * Determine the default RGB quantization range for the mode,
5865 * as specified in CEA-861.
5866 *
5867 * Return: The default RGB quantization range for the mode
5868 */
5869enum hdmi_quantization_range
5870drm_default_rgb_quant_range(const struct drm_display_mode *mode)
5871{
5872 /* All CEA modes other than VIC 1 use limited quantization range. */
5873 return drm_match_cea_mode(mode) > 1 ?
5874 HDMI_QUANTIZATION_RANGE_LIMITED :
5875 HDMI_QUANTIZATION_RANGE_FULL;
5876}
5877EXPORT_SYMBOL(drm_default_rgb_quant_range);
5878
5879/* CTA-861 Video Data Block (CTA VDB) */
5880static void parse_cta_vdb(struct drm_connector *connector, const struct cea_db *db)
5881{
5882 struct drm_display_info *info = &connector->display_info;
5883 int i, vic_index, len = cea_db_payload_len(db);
5884 const u8 *svds = cea_db_data(db);
5885 u8 *vics;
5886
5887 if (!len)
5888 return;
5889
5890 /* Gracefully handle multiple VDBs, however unlikely that is */
5891 vics = krealloc(info->vics, info->vics_len + len, GFP_KERNEL);
5892 if (!vics)
5893 return;
5894
5895 vic_index = info->vics_len;
5896 info->vics_len += len;
5897 info->vics = vics;
5898
5899 for (i = 0; i < len; i++) {
5900 u8 vic = svd_to_vic(svds[i]);
5901
5902 if (!drm_valid_cea_vic(vic))
5903 vic = 0;
5904
5905 info->vics[vic_index++] = vic;
5906 }
5907}
5908
5909/*
5910 * Update y420_cmdb_modes based on previously parsed CTA VDB and Y420CMDB.
5911 *
5912 * Translate the y420cmdb_map based on VIC indexes to y420_cmdb_modes indexed
5913 * using the VICs themselves.
5914 */
5915static void update_cta_y420cmdb(struct drm_connector *connector, u64 y420cmdb_map)
5916{
5917 struct drm_display_info *info = &connector->display_info;
5918 struct drm_hdmi_info *hdmi = &info->hdmi;
5919 int i, len = min_t(int, info->vics_len, BITS_PER_TYPE(y420cmdb_map));
5920
5921 for (i = 0; i < len; i++) {
5922 u8 vic = info->vics[i];
5923
5924 if (vic && y420cmdb_map & BIT_ULL(i))
5925 bitmap_set(hdmi->y420_cmdb_modes, vic, 1);
5926 }
5927}
5928
5929static bool cta_vdb_has_vic(const struct drm_connector *connector, u8 vic)
5930{
5931 const struct drm_display_info *info = &connector->display_info;
5932 int i;
5933
5934 if (!vic || !info->vics)
5935 return false;
5936
5937 for (i = 0; i < info->vics_len; i++) {
5938 if (info->vics[i] == vic)
5939 return true;
5940 }
5941
5942 return false;
5943}
5944
5945/* CTA-861-H YCbCr 4:2:0 Video Data Block (CTA Y420VDB) */
5946static void parse_cta_y420vdb(struct drm_connector *connector,
5947 const struct cea_db *db)
5948{
5949 struct drm_display_info *info = &connector->display_info;
5950 struct drm_hdmi_info *hdmi = &info->hdmi;
5951 const u8 *svds = cea_db_data(db) + 1;
5952 int i;
5953
5954 for (i = 0; i < cea_db_payload_len(db) - 1; i++) {
5955 u8 vic = svd_to_vic(svds[i]);
5956
5957 if (!drm_valid_cea_vic(vic))
5958 continue;
5959
5960 bitmap_set(hdmi->y420_vdb_modes, vic, 1);
5961 info->color_formats |= DRM_COLOR_FORMAT_YCBCR420;
5962 }
5963}
5964
5965static void drm_parse_vcdb(struct drm_connector *connector, const u8 *db)
5966{
5967 struct drm_display_info *info = &connector->display_info;
5968
5969 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] CEA VCDB 0x%02x\n",
5970 connector->base.id, connector->name, db[2]);
5971
5972 if (db[2] & EDID_CEA_VCDB_QS)
5973 info->rgb_quant_range_selectable = true;
5974}
5975
5976static
5977void drm_get_max_frl_rate(int max_frl_rate, u8 *max_lanes, u8 *max_rate_per_lane)
5978{
5979 switch (max_frl_rate) {
5980 case 1:
5981 *max_lanes = 3;
5982 *max_rate_per_lane = 3;
5983 break;
5984 case 2:
5985 *max_lanes = 3;
5986 *max_rate_per_lane = 6;
5987 break;
5988 case 3:
5989 *max_lanes = 4;
5990 *max_rate_per_lane = 6;
5991 break;
5992 case 4:
5993 *max_lanes = 4;
5994 *max_rate_per_lane = 8;
5995 break;
5996 case 5:
5997 *max_lanes = 4;
5998 *max_rate_per_lane = 10;
5999 break;
6000 case 6:
6001 *max_lanes = 4;
6002 *max_rate_per_lane = 12;
6003 break;
6004 case 0:
6005 default:
6006 *max_lanes = 0;
6007 *max_rate_per_lane = 0;
6008 }
6009}
6010
6011static void drm_parse_ycbcr420_deep_color_info(struct drm_connector *connector,
6012 const u8 *db)
6013{
6014 u8 dc_mask;
6015 struct drm_hdmi_info *hdmi = &connector->display_info.hdmi;
6016
6017 dc_mask = db[7] & DRM_EDID_YCBCR420_DC_MASK;
6018 hdmi->y420_dc_modes = dc_mask;
6019}
6020
6021static void drm_parse_dsc_info(struct drm_hdmi_dsc_cap *hdmi_dsc,
6022 const u8 *hf_scds)
6023{
6024 hdmi_dsc->v_1p2 = hf_scds[11] & DRM_EDID_DSC_1P2;
6025
6026 if (!hdmi_dsc->v_1p2)
6027 return;
6028
6029 hdmi_dsc->native_420 = hf_scds[11] & DRM_EDID_DSC_NATIVE_420;
6030 hdmi_dsc->all_bpp = hf_scds[11] & DRM_EDID_DSC_ALL_BPP;
6031
6032 if (hf_scds[11] & DRM_EDID_DSC_16BPC)
6033 hdmi_dsc->bpc_supported = 16;
6034 else if (hf_scds[11] & DRM_EDID_DSC_12BPC)
6035 hdmi_dsc->bpc_supported = 12;
6036 else if (hf_scds[11] & DRM_EDID_DSC_10BPC)
6037 hdmi_dsc->bpc_supported = 10;
6038 else
6039 /* Supports min 8 BPC if DSC 1.2 is supported*/
6040 hdmi_dsc->bpc_supported = 8;
6041
6042 if (cea_db_payload_len(hf_scds) >= 12 && hf_scds[12]) {
6043 u8 dsc_max_slices;
6044 u8 dsc_max_frl_rate;
6045
6046 dsc_max_frl_rate = (hf_scds[12] & DRM_EDID_DSC_MAX_FRL_RATE_MASK) >> 4;
6047 drm_get_max_frl_rate(dsc_max_frl_rate, &hdmi_dsc->max_lanes,
6048 &hdmi_dsc->max_frl_rate_per_lane);
6049
6050 dsc_max_slices = hf_scds[12] & DRM_EDID_DSC_MAX_SLICES;
6051
6052 switch (dsc_max_slices) {
6053 case 1:
6054 hdmi_dsc->max_slices = 1;
6055 hdmi_dsc->clk_per_slice = 340;
6056 break;
6057 case 2:
6058 hdmi_dsc->max_slices = 2;
6059 hdmi_dsc->clk_per_slice = 340;
6060 break;
6061 case 3:
6062 hdmi_dsc->max_slices = 4;
6063 hdmi_dsc->clk_per_slice = 340;
6064 break;
6065 case 4:
6066 hdmi_dsc->max_slices = 8;
6067 hdmi_dsc->clk_per_slice = 340;
6068 break;
6069 case 5:
6070 hdmi_dsc->max_slices = 8;
6071 hdmi_dsc->clk_per_slice = 400;
6072 break;
6073 case 6:
6074 hdmi_dsc->max_slices = 12;
6075 hdmi_dsc->clk_per_slice = 400;
6076 break;
6077 case 7:
6078 hdmi_dsc->max_slices = 16;
6079 hdmi_dsc->clk_per_slice = 400;
6080 break;
6081 case 0:
6082 default:
6083 hdmi_dsc->max_slices = 0;
6084 hdmi_dsc->clk_per_slice = 0;
6085 }
6086 }
6087
6088 if (cea_db_payload_len(hf_scds) >= 13 && hf_scds[13])
6089 hdmi_dsc->total_chunk_kbytes = hf_scds[13] & DRM_EDID_DSC_TOTAL_CHUNK_KBYTES;
6090}
6091
6092/* Sink Capability Data Structure */
6093static void drm_parse_hdmi_forum_scds(struct drm_connector *connector,
6094 const u8 *hf_scds)
6095{
6096 struct drm_display_info *info = &connector->display_info;
6097 struct drm_hdmi_info *hdmi = &info->hdmi;
6098 struct drm_hdmi_dsc_cap *hdmi_dsc = &hdmi->dsc_cap;
6099 int max_tmds_clock = 0;
6100 u8 max_frl_rate = 0;
6101 bool dsc_support = false;
6102
6103 info->has_hdmi_infoframe = true;
6104
6105 if (hf_scds[6] & 0x80) {
6106 hdmi->scdc.supported = true;
6107 if (hf_scds[6] & 0x40)
6108 hdmi->scdc.read_request = true;
6109 }
6110
6111 /*
6112 * All HDMI 2.0 monitors must support scrambling at rates > 340 MHz.
6113 * And as per the spec, three factors confirm this:
6114 * * Availability of a HF-VSDB block in EDID (check)
6115 * * Non zero Max_TMDS_Char_Rate filed in HF-VSDB (let's check)
6116 * * SCDC support available (let's check)
6117 * Lets check it out.
6118 */
6119
6120 if (hf_scds[5]) {
6121 struct drm_scdc *scdc = &hdmi->scdc;
6122
6123 /* max clock is 5000 KHz times block value */
6124 max_tmds_clock = hf_scds[5] * 5000;
6125
6126 if (max_tmds_clock > 340000) {
6127 info->max_tmds_clock = max_tmds_clock;
6128 }
6129
6130 if (scdc->supported) {
6131 scdc->scrambling.supported = true;
6132
6133 /* Few sinks support scrambling for clocks < 340M */
6134 if ((hf_scds[6] & 0x8))
6135 scdc->scrambling.low_rates = true;
6136 }
6137 }
6138
6139 if (hf_scds[7]) {
6140 max_frl_rate = (hf_scds[7] & DRM_EDID_MAX_FRL_RATE_MASK) >> 4;
6141 drm_get_max_frl_rate(max_frl_rate, &hdmi->max_lanes,
6142 &hdmi->max_frl_rate_per_lane);
6143 }
6144
6145 drm_parse_ycbcr420_deep_color_info(connector, hf_scds);
6146
6147 if (cea_db_payload_len(hf_scds) >= 11 && hf_scds[11]) {
6148 drm_parse_dsc_info(hdmi_dsc, hf_scds);
6149 dsc_support = true;
6150 }
6151
6152 drm_dbg_kms(connector->dev,
6153 "[CONNECTOR:%d:%s] HF-VSDB: max TMDS clock: %d KHz, HDMI 2.1 support: %s, DSC 1.2 support: %s\n",
6154 connector->base.id, connector->name,
6155 max_tmds_clock, str_yes_no(max_frl_rate), str_yes_no(dsc_support));
6156}
6157
6158static void drm_parse_hdmi_deep_color_info(struct drm_connector *connector,
6159 const u8 *hdmi)
6160{
6161 struct drm_display_info *info = &connector->display_info;
6162 unsigned int dc_bpc = 0;
6163
6164 /* HDMI supports at least 8 bpc */
6165 info->bpc = 8;
6166
6167 if (cea_db_payload_len(hdmi) < 6)
6168 return;
6169
6170 if (hdmi[6] & DRM_EDID_HDMI_DC_30) {
6171 dc_bpc = 10;
6172 info->edid_hdmi_rgb444_dc_modes |= DRM_EDID_HDMI_DC_30;
6173 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] HDMI sink does deep color 30.\n",
6174 connector->base.id, connector->name);
6175 }
6176
6177 if (hdmi[6] & DRM_EDID_HDMI_DC_36) {
6178 dc_bpc = 12;
6179 info->edid_hdmi_rgb444_dc_modes |= DRM_EDID_HDMI_DC_36;
6180 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] HDMI sink does deep color 36.\n",
6181 connector->base.id, connector->name);
6182 }
6183
6184 if (hdmi[6] & DRM_EDID_HDMI_DC_48) {
6185 dc_bpc = 16;
6186 info->edid_hdmi_rgb444_dc_modes |= DRM_EDID_HDMI_DC_48;
6187 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] HDMI sink does deep color 48.\n",
6188 connector->base.id, connector->name);
6189 }
6190
6191 if (dc_bpc == 0) {
6192 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] No deep color support on this HDMI sink.\n",
6193 connector->base.id, connector->name);
6194 return;
6195 }
6196
6197 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] Assigning HDMI sink color depth as %d bpc.\n",
6198 connector->base.id, connector->name, dc_bpc);
6199 info->bpc = dc_bpc;
6200
6201 /* YCRCB444 is optional according to spec. */
6202 if (hdmi[6] & DRM_EDID_HDMI_DC_Y444) {
6203 info->edid_hdmi_ycbcr444_dc_modes = info->edid_hdmi_rgb444_dc_modes;
6204 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] HDMI sink does YCRCB444 in deep color.\n",
6205 connector->base.id, connector->name);
6206 }
6207
6208 /*
6209 * Spec says that if any deep color mode is supported at all,
6210 * then deep color 36 bit must be supported.
6211 */
6212 if (!(hdmi[6] & DRM_EDID_HDMI_DC_36)) {
6213 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] HDMI sink should do DC_36, but does not!\n",
6214 connector->base.id, connector->name);
6215 }
6216}
6217
6218/* HDMI Vendor-Specific Data Block (HDMI VSDB, H14b-VSDB) */
6219static void
6220drm_parse_hdmi_vsdb_video(struct drm_connector *connector, const u8 *db)
6221{
6222 struct drm_display_info *info = &connector->display_info;
6223 u8 len = cea_db_payload_len(db);
6224
6225 info->is_hdmi = true;
6226
6227 info->source_physical_address = (db[4] << 8) | db[5];
6228
6229 if (len >= 6)
6230 info->dvi_dual = db[6] & 1;
6231 if (len >= 7)
6232 info->max_tmds_clock = db[7] * 5000;
6233
6234 /*
6235 * Try to infer whether the sink supports HDMI infoframes.
6236 *
6237 * HDMI infoframe support was first added in HDMI 1.4. Assume the sink
6238 * supports infoframes if HDMI_Video_present is set.
6239 */
6240 if (len >= 8 && db[8] & BIT(5))
6241 info->has_hdmi_infoframe = true;
6242
6243 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] HDMI: DVI dual %d, max TMDS clock %d kHz\n",
6244 connector->base.id, connector->name,
6245 info->dvi_dual, info->max_tmds_clock);
6246
6247 drm_parse_hdmi_deep_color_info(connector, db);
6248}
6249
6250/*
6251 * See EDID extension for head-mounted and specialized monitors, specified at:
6252 * https://docs.microsoft.com/en-us/windows-hardware/drivers/display/specialized-monitors-edid-extension
6253 */
6254static void drm_parse_microsoft_vsdb(struct drm_connector *connector,
6255 const u8 *db)
6256{
6257 struct drm_display_info *info = &connector->display_info;
6258 u8 version = db[4];
6259 bool desktop_usage = db[5] & BIT(6);
6260
6261 /* Version 1 and 2 for HMDs, version 3 flags desktop usage explicitly */
6262 if (version == 1 || version == 2 || (version == 3 && !desktop_usage))
6263 info->non_desktop = true;
6264
6265 drm_dbg_kms(connector->dev,
6266 "[CONNECTOR:%d:%s] HMD or specialized display VSDB version %u: 0x%02x\n",
6267 connector->base.id, connector->name, version, db[5]);
6268}
6269
6270static void drm_parse_cea_ext(struct drm_connector *connector,
6271 const struct drm_edid *drm_edid)
6272{
6273 struct drm_display_info *info = &connector->display_info;
6274 struct drm_edid_iter edid_iter;
6275 const struct cea_db *db;
6276 struct cea_db_iter iter;
6277 const u8 *edid_ext;
6278 u64 y420cmdb_map = 0;
6279
6280 drm_edid_iter_begin(drm_edid, &edid_iter);
6281 drm_edid_iter_for_each(edid_ext, &edid_iter) {
6282 if (edid_ext[0] != CEA_EXT)
6283 continue;
6284
6285 if (!info->cea_rev)
6286 info->cea_rev = edid_ext[1];
6287
6288 if (info->cea_rev != edid_ext[1])
6289 drm_dbg_kms(connector->dev,
6290 "[CONNECTOR:%d:%s] CEA extension version mismatch %u != %u\n",
6291 connector->base.id, connector->name,
6292 info->cea_rev, edid_ext[1]);
6293
6294 /* The existence of a CTA extension should imply RGB support */
6295 info->color_formats = DRM_COLOR_FORMAT_RGB444;
6296 if (edid_ext[3] & EDID_CEA_YCRCB444)
6297 info->color_formats |= DRM_COLOR_FORMAT_YCBCR444;
6298 if (edid_ext[3] & EDID_CEA_YCRCB422)
6299 info->color_formats |= DRM_COLOR_FORMAT_YCBCR422;
6300 if (edid_ext[3] & EDID_BASIC_AUDIO)
6301 info->has_audio = true;
6302
6303 }
6304 drm_edid_iter_end(&edid_iter);
6305
6306 cea_db_iter_edid_begin(drm_edid, &iter);
6307 cea_db_iter_for_each(db, &iter) {
6308 /* FIXME: convert parsers to use struct cea_db */
6309 const u8 *data = (const u8 *)db;
6310
6311 if (cea_db_is_hdmi_vsdb(db))
6312 drm_parse_hdmi_vsdb_video(connector, data);
6313 else if (cea_db_is_hdmi_forum_vsdb(db) ||
6314 cea_db_is_hdmi_forum_scdb(db))
6315 drm_parse_hdmi_forum_scds(connector, data);
6316 else if (cea_db_is_microsoft_vsdb(db))
6317 drm_parse_microsoft_vsdb(connector, data);
6318 else if (cea_db_is_y420cmdb(db))
6319 parse_cta_y420cmdb(connector, db, &y420cmdb_map);
6320 else if (cea_db_is_y420vdb(db))
6321 parse_cta_y420vdb(connector, db);
6322 else if (cea_db_is_vcdb(db))
6323 drm_parse_vcdb(connector, data);
6324 else if (cea_db_is_hdmi_hdr_metadata_block(db))
6325 drm_parse_hdr_metadata_block(connector, data);
6326 else if (cea_db_tag(db) == CTA_DB_VIDEO)
6327 parse_cta_vdb(connector, db);
6328 else if (cea_db_tag(db) == CTA_DB_AUDIO)
6329 info->has_audio = true;
6330 }
6331 cea_db_iter_end(&iter);
6332
6333 if (y420cmdb_map)
6334 update_cta_y420cmdb(connector, y420cmdb_map);
6335}
6336
6337static
6338void get_monitor_range(const struct detailed_timing *timing, void *c)
6339{
6340 struct detailed_mode_closure *closure = c;
6341 struct drm_display_info *info = &closure->connector->display_info;
6342 struct drm_monitor_range_info *monitor_range = &info->monitor_range;
6343 const struct detailed_non_pixel *data = &timing->data.other_data;
6344 const struct detailed_data_monitor_range *range = &data->data.range;
6345 const struct edid *edid = closure->drm_edid->edid;
6346
6347 if (!is_display_descriptor(timing, EDID_DETAIL_MONITOR_RANGE))
6348 return;
6349
6350 /*
6351 * These limits are used to determine the VRR refresh
6352 * rate range. Only the "range limits only" variant
6353 * of the range descriptor seems to guarantee that
6354 * any and all timings are accepted by the sink, as
6355 * opposed to just timings conforming to the indicated
6356 * formula (GTF/GTF2/CVT). Thus other variants of the
6357 * range descriptor are not accepted here.
6358 */
6359 if (range->flags != DRM_EDID_RANGE_LIMITS_ONLY_FLAG)
6360 return;
6361
6362 monitor_range->min_vfreq = range->min_vfreq;
6363 monitor_range->max_vfreq = range->max_vfreq;
6364
6365 if (edid->revision >= 4) {
6366 if (data->pad2 & DRM_EDID_RANGE_OFFSET_MIN_VFREQ)
6367 monitor_range->min_vfreq += 255;
6368 if (data->pad2 & DRM_EDID_RANGE_OFFSET_MAX_VFREQ)
6369 monitor_range->max_vfreq += 255;
6370 }
6371}
6372
6373static void drm_get_monitor_range(struct drm_connector *connector,
6374 const struct drm_edid *drm_edid)
6375{
6376 const struct drm_display_info *info = &connector->display_info;
6377 struct detailed_mode_closure closure = {
6378 .connector = connector,
6379 .drm_edid = drm_edid,
6380 };
6381
6382 if (drm_edid->edid->revision < 4)
6383 return;
6384
6385 if (!(drm_edid->edid->features & DRM_EDID_FEATURE_CONTINUOUS_FREQ))
6386 return;
6387
6388 drm_for_each_detailed_block(drm_edid, get_monitor_range, &closure);
6389
6390 drm_dbg_kms(connector->dev,
6391 "[CONNECTOR:%d:%s] Supported Monitor Refresh rate range is %d Hz - %d Hz\n",
6392 connector->base.id, connector->name,
6393 info->monitor_range.min_vfreq, info->monitor_range.max_vfreq);
6394}
6395
6396static void drm_parse_vesa_mso_data(struct drm_connector *connector,
6397 const struct displayid_block *block)
6398{
6399 struct displayid_vesa_vendor_specific_block *vesa =
6400 (struct displayid_vesa_vendor_specific_block *)block;
6401 struct drm_display_info *info = &connector->display_info;
6402
6403 if (block->num_bytes < 3) {
6404 drm_dbg_kms(connector->dev,
6405 "[CONNECTOR:%d:%s] Unexpected vendor block size %u\n",
6406 connector->base.id, connector->name, block->num_bytes);
6407 return;
6408 }
6409
6410 if (oui(vesa->oui[0], vesa->oui[1], vesa->oui[2]) != VESA_IEEE_OUI)
6411 return;
6412
6413 if (sizeof(*vesa) != sizeof(*block) + block->num_bytes) {
6414 drm_dbg_kms(connector->dev,
6415 "[CONNECTOR:%d:%s] Unexpected VESA vendor block size\n",
6416 connector->base.id, connector->name);
6417 return;
6418 }
6419
6420 switch (FIELD_GET(DISPLAYID_VESA_MSO_MODE, vesa->mso)) {
6421 default:
6422 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] Reserved MSO mode value\n",
6423 connector->base.id, connector->name);
6424 fallthrough;
6425 case 0:
6426 info->mso_stream_count = 0;
6427 break;
6428 case 1:
6429 info->mso_stream_count = 2; /* 2 or 4 links */
6430 break;
6431 case 2:
6432 info->mso_stream_count = 4; /* 4 links */
6433 break;
6434 }
6435
6436 if (!info->mso_stream_count) {
6437 info->mso_pixel_overlap = 0;
6438 return;
6439 }
6440
6441 info->mso_pixel_overlap = FIELD_GET(DISPLAYID_VESA_MSO_OVERLAP, vesa->mso);
6442 if (info->mso_pixel_overlap > 8) {
6443 drm_dbg_kms(connector->dev,
6444 "[CONNECTOR:%d:%s] Reserved MSO pixel overlap value %u\n",
6445 connector->base.id, connector->name,
6446 info->mso_pixel_overlap);
6447 info->mso_pixel_overlap = 8;
6448 }
6449
6450 drm_dbg_kms(connector->dev,
6451 "[CONNECTOR:%d:%s] MSO stream count %u, pixel overlap %u\n",
6452 connector->base.id, connector->name,
6453 info->mso_stream_count, info->mso_pixel_overlap);
6454}
6455
6456static void drm_update_mso(struct drm_connector *connector,
6457 const struct drm_edid *drm_edid)
6458{
6459 const struct displayid_block *block;
6460 struct displayid_iter iter;
6461
6462 displayid_iter_edid_begin(drm_edid, &iter);
6463 displayid_iter_for_each(block, &iter) {
6464 if (block->tag == DATA_BLOCK_2_VENDOR_SPECIFIC)
6465 drm_parse_vesa_mso_data(connector, block);
6466 }
6467 displayid_iter_end(&iter);
6468}
6469
6470/* A connector has no EDID information, so we've got no EDID to compute quirks from. Reset
6471 * all of the values which would have been set from EDID
6472 */
6473static void drm_reset_display_info(struct drm_connector *connector)
6474{
6475 struct drm_display_info *info = &connector->display_info;
6476
6477 info->width_mm = 0;
6478 info->height_mm = 0;
6479
6480 info->bpc = 0;
6481 info->color_formats = 0;
6482 info->cea_rev = 0;
6483 info->max_tmds_clock = 0;
6484 info->dvi_dual = false;
6485 info->is_hdmi = false;
6486 info->has_audio = false;
6487 info->has_hdmi_infoframe = false;
6488 info->rgb_quant_range_selectable = false;
6489 memset(&info->hdmi, 0, sizeof(info->hdmi));
6490
6491 info->edid_hdmi_rgb444_dc_modes = 0;
6492 info->edid_hdmi_ycbcr444_dc_modes = 0;
6493
6494 info->non_desktop = 0;
6495 memset(&info->monitor_range, 0, sizeof(info->monitor_range));
6496 memset(&info->luminance_range, 0, sizeof(info->luminance_range));
6497
6498 info->mso_stream_count = 0;
6499 info->mso_pixel_overlap = 0;
6500 info->max_dsc_bpp = 0;
6501
6502 kfree(info->vics);
6503 info->vics = NULL;
6504 info->vics_len = 0;
6505
6506 info->quirks = 0;
6507
6508 info->source_physical_address = CEC_PHYS_ADDR_INVALID;
6509}
6510
6511static void update_displayid_info(struct drm_connector *connector,
6512 const struct drm_edid *drm_edid)
6513{
6514 struct drm_display_info *info = &connector->display_info;
6515 const struct displayid_block *block;
6516 struct displayid_iter iter;
6517
6518 displayid_iter_edid_begin(drm_edid, &iter);
6519 displayid_iter_for_each(block, &iter) {
6520 if (displayid_version(&iter) == DISPLAY_ID_STRUCTURE_VER_20 &&
6521 (displayid_primary_use(&iter) == PRIMARY_USE_HEAD_MOUNTED_VR ||
6522 displayid_primary_use(&iter) == PRIMARY_USE_HEAD_MOUNTED_AR))
6523 info->non_desktop = true;
6524
6525 /*
6526 * We're only interested in the base section here, no need to
6527 * iterate further.
6528 */
6529 break;
6530 }
6531 displayid_iter_end(&iter);
6532}
6533
6534static void update_display_info(struct drm_connector *connector,
6535 const struct drm_edid *drm_edid)
6536{
6537 struct drm_display_info *info = &connector->display_info;
6538 const struct edid *edid;
6539
6540 drm_reset_display_info(connector);
6541 clear_eld(connector);
6542
6543 if (!drm_edid)
6544 return;
6545
6546 edid = drm_edid->edid;
6547
6548 info->quirks = edid_get_quirks(drm_edid);
6549
6550 info->width_mm = edid->width_cm * 10;
6551 info->height_mm = edid->height_cm * 10;
6552
6553 drm_get_monitor_range(connector, drm_edid);
6554
6555 if (edid->revision < 3)
6556 goto out;
6557
6558 if (!drm_edid_is_digital(drm_edid))
6559 goto out;
6560
6561 info->color_formats |= DRM_COLOR_FORMAT_RGB444;
6562 drm_parse_cea_ext(connector, drm_edid);
6563
6564 update_displayid_info(connector, drm_edid);
6565
6566 /*
6567 * Digital sink with "DFP 1.x compliant TMDS" according to EDID 1.3?
6568 *
6569 * For such displays, the DFP spec 1.0, section 3.10 "EDID support"
6570 * tells us to assume 8 bpc color depth if the EDID doesn't have
6571 * extensions which tell otherwise.
6572 */
6573 if (info->bpc == 0 && edid->revision == 3 &&
6574 edid->input & DRM_EDID_DIGITAL_DFP_1_X) {
6575 info->bpc = 8;
6576 drm_dbg_kms(connector->dev,
6577 "[CONNECTOR:%d:%s] Assigning DFP sink color depth as %d bpc.\n",
6578 connector->base.id, connector->name, info->bpc);
6579 }
6580
6581 /* Only defined for 1.4 with digital displays */
6582 if (edid->revision < 4)
6583 goto out;
6584
6585 switch (edid->input & DRM_EDID_DIGITAL_DEPTH_MASK) {
6586 case DRM_EDID_DIGITAL_DEPTH_6:
6587 info->bpc = 6;
6588 break;
6589 case DRM_EDID_DIGITAL_DEPTH_8:
6590 info->bpc = 8;
6591 break;
6592 case DRM_EDID_DIGITAL_DEPTH_10:
6593 info->bpc = 10;
6594 break;
6595 case DRM_EDID_DIGITAL_DEPTH_12:
6596 info->bpc = 12;
6597 break;
6598 case DRM_EDID_DIGITAL_DEPTH_14:
6599 info->bpc = 14;
6600 break;
6601 case DRM_EDID_DIGITAL_DEPTH_16:
6602 info->bpc = 16;
6603 break;
6604 case DRM_EDID_DIGITAL_DEPTH_UNDEF:
6605 default:
6606 info->bpc = 0;
6607 break;
6608 }
6609
6610 drm_dbg_kms(connector->dev,
6611 "[CONNECTOR:%d:%s] Assigning EDID-1.4 digital sink color depth as %d bpc.\n",
6612 connector->base.id, connector->name, info->bpc);
6613
6614 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB444)
6615 info->color_formats |= DRM_COLOR_FORMAT_YCBCR444;
6616 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB422)
6617 info->color_formats |= DRM_COLOR_FORMAT_YCBCR422;
6618
6619 drm_update_mso(connector, drm_edid);
6620
6621out:
6622 if (info->quirks & EDID_QUIRK_NON_DESKTOP) {
6623 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] Non-desktop display%s\n",
6624 connector->base.id, connector->name,
6625 info->non_desktop ? " (redundant quirk)" : "");
6626 info->non_desktop = true;
6627 }
6628
6629 if (info->quirks & EDID_QUIRK_CAP_DSC_15BPP)
6630 info->max_dsc_bpp = 15;
6631
6632 if (info->quirks & EDID_QUIRK_FORCE_6BPC)
6633 info->bpc = 6;
6634
6635 if (info->quirks & EDID_QUIRK_FORCE_8BPC)
6636 info->bpc = 8;
6637
6638 if (info->quirks & EDID_QUIRK_FORCE_10BPC)
6639 info->bpc = 10;
6640
6641 if (info->quirks & EDID_QUIRK_FORCE_12BPC)
6642 info->bpc = 12;
6643
6644 /* Depends on info->cea_rev set by drm_parse_cea_ext() above */
6645 drm_edid_to_eld(connector, drm_edid);
6646}
6647
6648static struct drm_display_mode *drm_mode_displayid_detailed(struct drm_device *dev,
6649 struct displayid_detailed_timings_1 *timings,
6650 bool type_7)
6651{
6652 struct drm_display_mode *mode;
6653 unsigned pixel_clock = (timings->pixel_clock[0] |
6654 (timings->pixel_clock[1] << 8) |
6655 (timings->pixel_clock[2] << 16)) + 1;
6656 unsigned hactive = (timings->hactive[0] | timings->hactive[1] << 8) + 1;
6657 unsigned hblank = (timings->hblank[0] | timings->hblank[1] << 8) + 1;
6658 unsigned hsync = (timings->hsync[0] | (timings->hsync[1] & 0x7f) << 8) + 1;
6659 unsigned hsync_width = (timings->hsw[0] | timings->hsw[1] << 8) + 1;
6660 unsigned vactive = (timings->vactive[0] | timings->vactive[1] << 8) + 1;
6661 unsigned vblank = (timings->vblank[0] | timings->vblank[1] << 8) + 1;
6662 unsigned vsync = (timings->vsync[0] | (timings->vsync[1] & 0x7f) << 8) + 1;
6663 unsigned vsync_width = (timings->vsw[0] | timings->vsw[1] << 8) + 1;
6664 bool hsync_positive = (timings->hsync[1] >> 7) & 0x1;
6665 bool vsync_positive = (timings->vsync[1] >> 7) & 0x1;
6666
6667 mode = drm_mode_create(dev);
6668 if (!mode)
6669 return NULL;
6670
6671 /* resolution is kHz for type VII, and 10 kHz for type I */
6672 mode->clock = type_7 ? pixel_clock : pixel_clock * 10;
6673 mode->hdisplay = hactive;
6674 mode->hsync_start = mode->hdisplay + hsync;
6675 mode->hsync_end = mode->hsync_start + hsync_width;
6676 mode->htotal = mode->hdisplay + hblank;
6677
6678 mode->vdisplay = vactive;
6679 mode->vsync_start = mode->vdisplay + vsync;
6680 mode->vsync_end = mode->vsync_start + vsync_width;
6681 mode->vtotal = mode->vdisplay + vblank;
6682
6683 mode->flags = 0;
6684 mode->flags |= hsync_positive ? DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC;
6685 mode->flags |= vsync_positive ? DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC;
6686 mode->type = DRM_MODE_TYPE_DRIVER;
6687
6688 if (timings->flags & 0x80)
6689 mode->type |= DRM_MODE_TYPE_PREFERRED;
6690 drm_mode_set_name(mode);
6691
6692 return mode;
6693}
6694
6695static int add_displayid_detailed_1_modes(struct drm_connector *connector,
6696 const struct displayid_block *block)
6697{
6698 struct displayid_detailed_timing_block *det = (struct displayid_detailed_timing_block *)block;
6699 int i;
6700 int num_timings;
6701 struct drm_display_mode *newmode;
6702 int num_modes = 0;
6703 bool type_7 = block->tag == DATA_BLOCK_2_TYPE_7_DETAILED_TIMING;
6704 /* blocks must be multiple of 20 bytes length */
6705 if (block->num_bytes % 20)
6706 return 0;
6707
6708 num_timings = block->num_bytes / 20;
6709 for (i = 0; i < num_timings; i++) {
6710 struct displayid_detailed_timings_1 *timings = &det->timings[i];
6711
6712 newmode = drm_mode_displayid_detailed(connector->dev, timings, type_7);
6713 if (!newmode)
6714 continue;
6715
6716 drm_mode_probed_add(connector, newmode);
6717 num_modes++;
6718 }
6719 return num_modes;
6720}
6721
6722static int add_displayid_detailed_modes(struct drm_connector *connector,
6723 const struct drm_edid *drm_edid)
6724{
6725 const struct displayid_block *block;
6726 struct displayid_iter iter;
6727 int num_modes = 0;
6728
6729 displayid_iter_edid_begin(drm_edid, &iter);
6730 displayid_iter_for_each(block, &iter) {
6731 if (block->tag == DATA_BLOCK_TYPE_1_DETAILED_TIMING ||
6732 block->tag == DATA_BLOCK_2_TYPE_7_DETAILED_TIMING)
6733 num_modes += add_displayid_detailed_1_modes(connector, block);
6734 }
6735 displayid_iter_end(&iter);
6736
6737 return num_modes;
6738}
6739
6740static int _drm_edid_connector_add_modes(struct drm_connector *connector,
6741 const struct drm_edid *drm_edid)
6742{
6743 const struct drm_display_info *info = &connector->display_info;
6744 int num_modes = 0;
6745
6746 if (!drm_edid)
6747 return 0;
6748
6749 /*
6750 * EDID spec says modes should be preferred in this order:
6751 * - preferred detailed mode
6752 * - other detailed modes from base block
6753 * - detailed modes from extension blocks
6754 * - CVT 3-byte code modes
6755 * - standard timing codes
6756 * - established timing codes
6757 * - modes inferred from GTF or CVT range information
6758 *
6759 * We get this pretty much right.
6760 *
6761 * XXX order for additional mode types in extension blocks?
6762 */
6763 num_modes += add_detailed_modes(connector, drm_edid);
6764 num_modes += add_cvt_modes(connector, drm_edid);
6765 num_modes += add_standard_modes(connector, drm_edid);
6766 num_modes += add_established_modes(connector, drm_edid);
6767 num_modes += add_cea_modes(connector, drm_edid);
6768 num_modes += add_alternate_cea_modes(connector, drm_edid);
6769 num_modes += add_displayid_detailed_modes(connector, drm_edid);
6770 if (drm_edid->edid->features & DRM_EDID_FEATURE_CONTINUOUS_FREQ)
6771 num_modes += add_inferred_modes(connector, drm_edid);
6772
6773 if (info->quirks & (EDID_QUIRK_PREFER_LARGE_60 | EDID_QUIRK_PREFER_LARGE_75))
6774 edid_fixup_preferred(connector);
6775
6776 return num_modes;
6777}
6778
6779static void _drm_update_tile_info(struct drm_connector *connector,
6780 const struct drm_edid *drm_edid);
6781
6782static int _drm_edid_connector_property_update(struct drm_connector *connector,
6783 const struct drm_edid *drm_edid)
6784{
6785 struct drm_device *dev = connector->dev;
6786 int ret;
6787
6788 if (connector->edid_blob_ptr) {
6789 const struct edid *old_edid = connector->edid_blob_ptr->data;
6790
6791 if (old_edid) {
6792 if (!drm_edid_are_equal(drm_edid ? drm_edid->edid : NULL, old_edid)) {
6793 connector->epoch_counter++;
6794 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] EDID changed, epoch counter %llu\n",
6795 connector->base.id, connector->name,
6796 connector->epoch_counter);
6797 }
6798 }
6799 }
6800
6801 ret = drm_property_replace_global_blob(dev,
6802 &connector->edid_blob_ptr,
6803 drm_edid ? drm_edid->size : 0,
6804 drm_edid ? drm_edid->edid : NULL,
6805 &connector->base,
6806 dev->mode_config.edid_property);
6807 if (ret) {
6808 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] EDID property update failed (%d)\n",
6809 connector->base.id, connector->name, ret);
6810 goto out;
6811 }
6812
6813 ret = drm_object_property_set_value(&connector->base,
6814 dev->mode_config.non_desktop_property,
6815 connector->display_info.non_desktop);
6816 if (ret) {
6817 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] Non-desktop property update failed (%d)\n",
6818 connector->base.id, connector->name, ret);
6819 goto out;
6820 }
6821
6822 ret = drm_connector_set_tile_property(connector);
6823 if (ret) {
6824 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] Tile property update failed (%d)\n",
6825 connector->base.id, connector->name, ret);
6826 goto out;
6827 }
6828
6829out:
6830 return ret;
6831}
6832
6833/**
6834 * drm_edid_connector_update - Update connector information from EDID
6835 * @connector: Connector
6836 * @drm_edid: EDID
6837 *
6838 * Update the connector display info, ELD, HDR metadata, relevant properties,
6839 * etc. from the passed in EDID.
6840 *
6841 * If EDID is NULL, reset the information.
6842 *
6843 * Must be called before calling drm_edid_connector_add_modes().
6844 *
6845 * Return: 0 on success, negative error on errors.
6846 */
6847int drm_edid_connector_update(struct drm_connector *connector,
6848 const struct drm_edid *drm_edid)
6849{
6850 update_display_info(connector, drm_edid);
6851
6852 _drm_update_tile_info(connector, drm_edid);
6853
6854 return _drm_edid_connector_property_update(connector, drm_edid);
6855}
6856EXPORT_SYMBOL(drm_edid_connector_update);
6857
6858/**
6859 * drm_edid_connector_add_modes - Update probed modes from the EDID property
6860 * @connector: Connector
6861 *
6862 * Add the modes from the previously updated EDID property to the connector
6863 * probed modes list.
6864 *
6865 * drm_edid_connector_update() must have been called before this to update the
6866 * EDID property.
6867 *
6868 * Return: The number of modes added, or 0 if we couldn't find any.
6869 */
6870int drm_edid_connector_add_modes(struct drm_connector *connector)
6871{
6872 const struct drm_edid *drm_edid = NULL;
6873 int count;
6874
6875 if (connector->edid_blob_ptr)
6876 drm_edid = drm_edid_alloc(connector->edid_blob_ptr->data,
6877 connector->edid_blob_ptr->length);
6878
6879 count = _drm_edid_connector_add_modes(connector, drm_edid);
6880
6881 drm_edid_free(drm_edid);
6882
6883 return count;
6884}
6885EXPORT_SYMBOL(drm_edid_connector_add_modes);
6886
6887/**
6888 * drm_connector_update_edid_property - update the edid property of a connector
6889 * @connector: drm connector
6890 * @edid: new value of the edid property
6891 *
6892 * This function creates a new blob modeset object and assigns its id to the
6893 * connector's edid property.
6894 * Since we also parse tile information from EDID's displayID block, we also
6895 * set the connector's tile property here. See drm_connector_set_tile_property()
6896 * for more details.
6897 *
6898 * This function is deprecated. Use drm_edid_connector_update() instead.
6899 *
6900 * Returns:
6901 * Zero on success, negative errno on failure.
6902 */
6903int drm_connector_update_edid_property(struct drm_connector *connector,
6904 const struct edid *edid)
6905{
6906 struct drm_edid drm_edid;
6907
6908 return drm_edid_connector_update(connector, drm_edid_legacy_init(&drm_edid, edid));
6909}
6910EXPORT_SYMBOL(drm_connector_update_edid_property);
6911
6912/**
6913 * drm_add_edid_modes - add modes from EDID data, if available
6914 * @connector: connector we're probing
6915 * @edid: EDID data
6916 *
6917 * Add the specified modes to the connector's mode list. Also fills out the
6918 * &drm_display_info structure and ELD in @connector with any information which
6919 * can be derived from the edid.
6920 *
6921 * This function is deprecated. Use drm_edid_connector_add_modes() instead.
6922 *
6923 * Return: The number of modes added or 0 if we couldn't find any.
6924 */
6925int drm_add_edid_modes(struct drm_connector *connector, struct edid *edid)
6926{
6927 struct drm_edid _drm_edid;
6928 const struct drm_edid *drm_edid;
6929
6930 if (edid && !drm_edid_is_valid(edid)) {
6931 drm_warn(connector->dev, "[CONNECTOR:%d:%s] EDID invalid.\n",
6932 connector->base.id, connector->name);
6933 edid = NULL;
6934 }
6935
6936 drm_edid = drm_edid_legacy_init(&_drm_edid, edid);
6937
6938 update_display_info(connector, drm_edid);
6939
6940 return _drm_edid_connector_add_modes(connector, drm_edid);
6941}
6942EXPORT_SYMBOL(drm_add_edid_modes);
6943
6944/**
6945 * drm_add_modes_noedid - add modes for the connectors without EDID
6946 * @connector: connector we're probing
6947 * @hdisplay: the horizontal display limit
6948 * @vdisplay: the vertical display limit
6949 *
6950 * Add the specified modes to the connector's mode list. Only when the
6951 * hdisplay/vdisplay is not beyond the given limit, it will be added.
6952 *
6953 * Return: The number of modes added or 0 if we couldn't find any.
6954 */
6955int drm_add_modes_noedid(struct drm_connector *connector,
6956 int hdisplay, int vdisplay)
6957{
6958 int i, count, num_modes = 0;
6959 struct drm_display_mode *mode;
6960 struct drm_device *dev = connector->dev;
6961
6962 count = ARRAY_SIZE(drm_dmt_modes);
6963 if (hdisplay < 0)
6964 hdisplay = 0;
6965 if (vdisplay < 0)
6966 vdisplay = 0;
6967
6968 for (i = 0; i < count; i++) {
6969 const struct drm_display_mode *ptr = &drm_dmt_modes[i];
6970
6971 if (hdisplay && vdisplay) {
6972 /*
6973 * Only when two are valid, they will be used to check
6974 * whether the mode should be added to the mode list of
6975 * the connector.
6976 */
6977 if (ptr->hdisplay > hdisplay ||
6978 ptr->vdisplay > vdisplay)
6979 continue;
6980 }
6981 if (drm_mode_vrefresh(ptr) > 61)
6982 continue;
6983 mode = drm_mode_duplicate(dev, ptr);
6984 if (mode) {
6985 drm_mode_probed_add(connector, mode);
6986 num_modes++;
6987 }
6988 }
6989 return num_modes;
6990}
6991EXPORT_SYMBOL(drm_add_modes_noedid);
6992
6993/**
6994 * drm_set_preferred_mode - Sets the preferred mode of a connector
6995 * @connector: connector whose mode list should be processed
6996 * @hpref: horizontal resolution of preferred mode
6997 * @vpref: vertical resolution of preferred mode
6998 *
6999 * Marks a mode as preferred if it matches the resolution specified by @hpref
7000 * and @vpref.
7001 */
7002void drm_set_preferred_mode(struct drm_connector *connector,
7003 int hpref, int vpref)
7004{
7005 struct drm_display_mode *mode;
7006
7007 list_for_each_entry(mode, &connector->probed_modes, head) {
7008 if (mode->hdisplay == hpref &&
7009 mode->vdisplay == vpref)
7010 mode->type |= DRM_MODE_TYPE_PREFERRED;
7011 }
7012}
7013EXPORT_SYMBOL(drm_set_preferred_mode);
7014
7015static bool is_hdmi2_sink(const struct drm_connector *connector)
7016{
7017 /*
7018 * FIXME: sil-sii8620 doesn't have a connector around when
7019 * we need one, so we have to be prepared for a NULL connector.
7020 */
7021 if (!connector)
7022 return true;
7023
7024 return connector->display_info.hdmi.scdc.supported ||
7025 connector->display_info.color_formats & DRM_COLOR_FORMAT_YCBCR420;
7026}
7027
7028static u8 drm_mode_hdmi_vic(const struct drm_connector *connector,
7029 const struct drm_display_mode *mode)
7030{
7031 bool has_hdmi_infoframe = connector ?
7032 connector->display_info.has_hdmi_infoframe : false;
7033
7034 if (!has_hdmi_infoframe)
7035 return 0;
7036
7037 /* No HDMI VIC when signalling 3D video format */
7038 if (mode->flags & DRM_MODE_FLAG_3D_MASK)
7039 return 0;
7040
7041 return drm_match_hdmi_mode(mode);
7042}
7043
7044static u8 drm_mode_cea_vic(const struct drm_connector *connector,
7045 const struct drm_display_mode *mode)
7046{
7047 /*
7048 * HDMI spec says if a mode is found in HDMI 1.4b 4K modes
7049 * we should send its VIC in vendor infoframes, else send the
7050 * VIC in AVI infoframes. Lets check if this mode is present in
7051 * HDMI 1.4b 4K modes
7052 */
7053 if (drm_mode_hdmi_vic(connector, mode))
7054 return 0;
7055
7056 return drm_match_cea_mode(mode);
7057}
7058
7059/*
7060 * Avoid sending VICs defined in HDMI 2.0 in AVI infoframes to sinks that
7061 * conform to HDMI 1.4.
7062 *
7063 * HDMI 1.4 (CTA-861-D) VIC range: [1..64]
7064 * HDMI 2.0 (CTA-861-F) VIC range: [1..107]
7065 *
7066 * If the sink lists the VIC in CTA VDB, assume it's fine, regardless of HDMI
7067 * version.
7068 */
7069static u8 vic_for_avi_infoframe(const struct drm_connector *connector, u8 vic)
7070{
7071 if (!is_hdmi2_sink(connector) && vic > 64 &&
7072 !cta_vdb_has_vic(connector, vic))
7073 return 0;
7074
7075 return vic;
7076}
7077
7078/**
7079 * drm_hdmi_avi_infoframe_from_display_mode() - fill an HDMI AVI infoframe with
7080 * data from a DRM display mode
7081 * @frame: HDMI AVI infoframe
7082 * @connector: the connector
7083 * @mode: DRM display mode
7084 *
7085 * Return: 0 on success or a negative error code on failure.
7086 */
7087int
7088drm_hdmi_avi_infoframe_from_display_mode(struct hdmi_avi_infoframe *frame,
7089 const struct drm_connector *connector,
7090 const struct drm_display_mode *mode)
7091{
7092 enum hdmi_picture_aspect picture_aspect;
7093 u8 vic, hdmi_vic;
7094
7095 if (!frame || !mode)
7096 return -EINVAL;
7097
7098 hdmi_avi_infoframe_init(frame);
7099
7100 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
7101 frame->pixel_repeat = 1;
7102
7103 vic = drm_mode_cea_vic(connector, mode);
7104 hdmi_vic = drm_mode_hdmi_vic(connector, mode);
7105
7106 frame->picture_aspect = HDMI_PICTURE_ASPECT_NONE;
7107
7108 /*
7109 * As some drivers don't support atomic, we can't use connector state.
7110 * So just initialize the frame with default values, just the same way
7111 * as it's done with other properties here.
7112 */
7113 frame->content_type = HDMI_CONTENT_TYPE_GRAPHICS;
7114 frame->itc = 0;
7115
7116 /*
7117 * Populate picture aspect ratio from either
7118 * user input (if specified) or from the CEA/HDMI mode lists.
7119 */
7120 picture_aspect = mode->picture_aspect_ratio;
7121 if (picture_aspect == HDMI_PICTURE_ASPECT_NONE) {
7122 if (vic)
7123 picture_aspect = drm_get_cea_aspect_ratio(vic);
7124 else if (hdmi_vic)
7125 picture_aspect = drm_get_hdmi_aspect_ratio(hdmi_vic);
7126 }
7127
7128 /*
7129 * The infoframe can't convey anything but none, 4:3
7130 * and 16:9, so if the user has asked for anything else
7131 * we can only satisfy it by specifying the right VIC.
7132 */
7133 if (picture_aspect > HDMI_PICTURE_ASPECT_16_9) {
7134 if (vic) {
7135 if (picture_aspect != drm_get_cea_aspect_ratio(vic))
7136 return -EINVAL;
7137 } else if (hdmi_vic) {
7138 if (picture_aspect != drm_get_hdmi_aspect_ratio(hdmi_vic))
7139 return -EINVAL;
7140 } else {
7141 return -EINVAL;
7142 }
7143
7144 picture_aspect = HDMI_PICTURE_ASPECT_NONE;
7145 }
7146
7147 frame->video_code = vic_for_avi_infoframe(connector, vic);
7148 frame->picture_aspect = picture_aspect;
7149 frame->active_aspect = HDMI_ACTIVE_ASPECT_PICTURE;
7150 frame->scan_mode = HDMI_SCAN_MODE_UNDERSCAN;
7151
7152 return 0;
7153}
7154EXPORT_SYMBOL(drm_hdmi_avi_infoframe_from_display_mode);
7155
7156/**
7157 * drm_hdmi_avi_infoframe_quant_range() - fill the HDMI AVI infoframe
7158 * quantization range information
7159 * @frame: HDMI AVI infoframe
7160 * @connector: the connector
7161 * @mode: DRM display mode
7162 * @rgb_quant_range: RGB quantization range (Q)
7163 */
7164void
7165drm_hdmi_avi_infoframe_quant_range(struct hdmi_avi_infoframe *frame,
7166 const struct drm_connector *connector,
7167 const struct drm_display_mode *mode,
7168 enum hdmi_quantization_range rgb_quant_range)
7169{
7170 const struct drm_display_info *info = &connector->display_info;
7171
7172 /*
7173 * CEA-861:
7174 * "A Source shall not send a non-zero Q value that does not correspond
7175 * to the default RGB Quantization Range for the transmitted Picture
7176 * unless the Sink indicates support for the Q bit in a Video
7177 * Capabilities Data Block."
7178 *
7179 * HDMI 2.0 recommends sending non-zero Q when it does match the
7180 * default RGB quantization range for the mode, even when QS=0.
7181 */
7182 if (info->rgb_quant_range_selectable ||
7183 rgb_quant_range == drm_default_rgb_quant_range(mode))
7184 frame->quantization_range = rgb_quant_range;
7185 else
7186 frame->quantization_range = HDMI_QUANTIZATION_RANGE_DEFAULT;
7187
7188 /*
7189 * CEA-861-F:
7190 * "When transmitting any RGB colorimetry, the Source should set the
7191 * YQ-field to match the RGB Quantization Range being transmitted
7192 * (e.g., when Limited Range RGB, set YQ=0 or when Full Range RGB,
7193 * set YQ=1) and the Sink shall ignore the YQ-field."
7194 *
7195 * Unfortunate certain sinks (eg. VIZ Model 67/E261VA) get confused
7196 * by non-zero YQ when receiving RGB. There doesn't seem to be any
7197 * good way to tell which version of CEA-861 the sink supports, so
7198 * we limit non-zero YQ to HDMI 2.0 sinks only as HDMI 2.0 is based
7199 * on CEA-861-F.
7200 */
7201 if (!is_hdmi2_sink(connector) ||
7202 rgb_quant_range == HDMI_QUANTIZATION_RANGE_LIMITED)
7203 frame->ycc_quantization_range =
7204 HDMI_YCC_QUANTIZATION_RANGE_LIMITED;
7205 else
7206 frame->ycc_quantization_range =
7207 HDMI_YCC_QUANTIZATION_RANGE_FULL;
7208}
7209EXPORT_SYMBOL(drm_hdmi_avi_infoframe_quant_range);
7210
7211static enum hdmi_3d_structure
7212s3d_structure_from_display_mode(const struct drm_display_mode *mode)
7213{
7214 u32 layout = mode->flags & DRM_MODE_FLAG_3D_MASK;
7215
7216 switch (layout) {
7217 case DRM_MODE_FLAG_3D_FRAME_PACKING:
7218 return HDMI_3D_STRUCTURE_FRAME_PACKING;
7219 case DRM_MODE_FLAG_3D_FIELD_ALTERNATIVE:
7220 return HDMI_3D_STRUCTURE_FIELD_ALTERNATIVE;
7221 case DRM_MODE_FLAG_3D_LINE_ALTERNATIVE:
7222 return HDMI_3D_STRUCTURE_LINE_ALTERNATIVE;
7223 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_FULL:
7224 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_FULL;
7225 case DRM_MODE_FLAG_3D_L_DEPTH:
7226 return HDMI_3D_STRUCTURE_L_DEPTH;
7227 case DRM_MODE_FLAG_3D_L_DEPTH_GFX_GFX_DEPTH:
7228 return HDMI_3D_STRUCTURE_L_DEPTH_GFX_GFX_DEPTH;
7229 case DRM_MODE_FLAG_3D_TOP_AND_BOTTOM:
7230 return HDMI_3D_STRUCTURE_TOP_AND_BOTTOM;
7231 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF:
7232 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_HALF;
7233 default:
7234 return HDMI_3D_STRUCTURE_INVALID;
7235 }
7236}
7237
7238/**
7239 * drm_hdmi_vendor_infoframe_from_display_mode() - fill an HDMI infoframe with
7240 * data from a DRM display mode
7241 * @frame: HDMI vendor infoframe
7242 * @connector: the connector
7243 * @mode: DRM display mode
7244 *
7245 * Note that there's is a need to send HDMI vendor infoframes only when using a
7246 * 4k or stereoscopic 3D mode. So when giving any other mode as input this
7247 * function will return -EINVAL, error that can be safely ignored.
7248 *
7249 * Return: 0 on success or a negative error code on failure.
7250 */
7251int
7252drm_hdmi_vendor_infoframe_from_display_mode(struct hdmi_vendor_infoframe *frame,
7253 const struct drm_connector *connector,
7254 const struct drm_display_mode *mode)
7255{
7256 /*
7257 * FIXME: sil-sii8620 doesn't have a connector around when
7258 * we need one, so we have to be prepared for a NULL connector.
7259 */
7260 bool has_hdmi_infoframe = connector ?
7261 connector->display_info.has_hdmi_infoframe : false;
7262 int err;
7263
7264 if (!frame || !mode)
7265 return -EINVAL;
7266
7267 if (!has_hdmi_infoframe)
7268 return -EINVAL;
7269
7270 err = hdmi_vendor_infoframe_init(frame);
7271 if (err < 0)
7272 return err;
7273
7274 /*
7275 * Even if it's not absolutely necessary to send the infoframe
7276 * (ie.vic==0 and s3d_struct==0) we will still send it if we
7277 * know that the sink can handle it. This is based on a
7278 * suggestion in HDMI 2.0 Appendix F. Apparently some sinks
7279 * have trouble realizing that they should switch from 3D to 2D
7280 * mode if the source simply stops sending the infoframe when
7281 * it wants to switch from 3D to 2D.
7282 */
7283 frame->vic = drm_mode_hdmi_vic(connector, mode);
7284 frame->s3d_struct = s3d_structure_from_display_mode(mode);
7285
7286 return 0;
7287}
7288EXPORT_SYMBOL(drm_hdmi_vendor_infoframe_from_display_mode);
7289
7290static void drm_parse_tiled_block(struct drm_connector *connector,
7291 const struct displayid_block *block)
7292{
7293 const struct displayid_tiled_block *tile = (struct displayid_tiled_block *)block;
7294 u16 w, h;
7295 u8 tile_v_loc, tile_h_loc;
7296 u8 num_v_tile, num_h_tile;
7297 struct drm_tile_group *tg;
7298
7299 w = tile->tile_size[0] | tile->tile_size[1] << 8;
7300 h = tile->tile_size[2] | tile->tile_size[3] << 8;
7301
7302 num_v_tile = (tile->topo[0] & 0xf) | (tile->topo[2] & 0x30);
7303 num_h_tile = (tile->topo[0] >> 4) | ((tile->topo[2] >> 2) & 0x30);
7304 tile_v_loc = (tile->topo[1] & 0xf) | ((tile->topo[2] & 0x3) << 4);
7305 tile_h_loc = (tile->topo[1] >> 4) | (((tile->topo[2] >> 2) & 0x3) << 4);
7306
7307 connector->has_tile = true;
7308 if (tile->tile_cap & 0x80)
7309 connector->tile_is_single_monitor = true;
7310
7311 connector->num_h_tile = num_h_tile + 1;
7312 connector->num_v_tile = num_v_tile + 1;
7313 connector->tile_h_loc = tile_h_loc;
7314 connector->tile_v_loc = tile_v_loc;
7315 connector->tile_h_size = w + 1;
7316 connector->tile_v_size = h + 1;
7317
7318 drm_dbg_kms(connector->dev,
7319 "[CONNECTOR:%d:%s] tile cap 0x%x, size %dx%d, num tiles %dx%d, location %dx%d, vend %c%c%c",
7320 connector->base.id, connector->name,
7321 tile->tile_cap,
7322 connector->tile_h_size, connector->tile_v_size,
7323 connector->num_h_tile, connector->num_v_tile,
7324 connector->tile_h_loc, connector->tile_v_loc,
7325 tile->topology_id[0], tile->topology_id[1], tile->topology_id[2]);
7326
7327 tg = drm_mode_get_tile_group(connector->dev, tile->topology_id);
7328 if (!tg)
7329 tg = drm_mode_create_tile_group(connector->dev, tile->topology_id);
7330 if (!tg)
7331 return;
7332
7333 if (connector->tile_group != tg) {
7334 /* if we haven't got a pointer,
7335 take the reference, drop ref to old tile group */
7336 if (connector->tile_group)
7337 drm_mode_put_tile_group(connector->dev, connector->tile_group);
7338 connector->tile_group = tg;
7339 } else {
7340 /* if same tile group, then release the ref we just took. */
7341 drm_mode_put_tile_group(connector->dev, tg);
7342 }
7343}
7344
7345static bool displayid_is_tiled_block(const struct displayid_iter *iter,
7346 const struct displayid_block *block)
7347{
7348 return (displayid_version(iter) == DISPLAY_ID_STRUCTURE_VER_12 &&
7349 block->tag == DATA_BLOCK_TILED_DISPLAY) ||
7350 (displayid_version(iter) == DISPLAY_ID_STRUCTURE_VER_20 &&
7351 block->tag == DATA_BLOCK_2_TILED_DISPLAY_TOPOLOGY);
7352}
7353
7354static void _drm_update_tile_info(struct drm_connector *connector,
7355 const struct drm_edid *drm_edid)
7356{
7357 const struct displayid_block *block;
7358 struct displayid_iter iter;
7359
7360 connector->has_tile = false;
7361
7362 displayid_iter_edid_begin(drm_edid, &iter);
7363 displayid_iter_for_each(block, &iter) {
7364 if (displayid_is_tiled_block(&iter, block))
7365 drm_parse_tiled_block(connector, block);
7366 }
7367 displayid_iter_end(&iter);
7368
7369 if (!connector->has_tile && connector->tile_group) {
7370 drm_mode_put_tile_group(connector->dev, connector->tile_group);
7371 connector->tile_group = NULL;
7372 }
7373}
7374
7375/**
7376 * drm_edid_is_digital - is digital?
7377 * @drm_edid: The EDID
7378 *
7379 * Return true if input is digital.
7380 */
7381bool drm_edid_is_digital(const struct drm_edid *drm_edid)
7382{
7383 return drm_edid && drm_edid->edid &&
7384 drm_edid->edid->input & DRM_EDID_INPUT_DIGITAL;
7385}
7386EXPORT_SYMBOL(drm_edid_is_digital);