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1/*
2 * Copyright 2016 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24#include <linux/firmware.h>
25#include <linux/pci.h>
26
27#include <drm/drm_cache.h>
28
29#include "amdgpu.h"
30#include "gmc_v9_0.h"
31#include "amdgpu_atomfirmware.h"
32#include "amdgpu_gem.h"
33
34#include "hdp/hdp_4_0_offset.h"
35#include "hdp/hdp_4_0_sh_mask.h"
36#include "gc/gc_9_0_sh_mask.h"
37#include "dce/dce_12_0_offset.h"
38#include "dce/dce_12_0_sh_mask.h"
39#include "vega10_enum.h"
40#include "mmhub/mmhub_1_0_offset.h"
41#include "athub/athub_1_0_sh_mask.h"
42#include "athub/athub_1_0_offset.h"
43#include "oss/osssys_4_0_offset.h"
44
45#include "soc15.h"
46#include "soc15d.h"
47#include "soc15_common.h"
48#include "umc/umc_6_0_sh_mask.h"
49
50#include "gfxhub_v1_0.h"
51#include "mmhub_v1_0.h"
52#include "athub_v1_0.h"
53#include "gfxhub_v1_1.h"
54#include "mmhub_v9_4.h"
55#include "umc_v6_1.h"
56#include "umc_v6_0.h"
57
58#include "ivsrcid/vmc/irqsrcs_vmc_1_0.h"
59
60#include "amdgpu_ras.h"
61#include "amdgpu_xgmi.h"
62
63/* add these here since we already include dce12 headers and these are for DCN */
64#define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION 0x055d
65#define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX 2
66#define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH__SHIFT 0x0
67#define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT__SHIFT 0x10
68#define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH_MASK 0x00003FFFL
69#define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT_MASK 0x3FFF0000L
70
71static const u32 golden_settings_vega10_hdp[] =
72{
73 0xf64, 0x0fffffff, 0x00000000,
74 0xf65, 0x0fffffff, 0x00000000,
75 0xf66, 0x0fffffff, 0x00000000,
76 0xf67, 0x0fffffff, 0x00000000,
77 0xf68, 0x0fffffff, 0x00000000,
78 0xf6a, 0x0fffffff, 0x00000000,
79 0xf6b, 0x0fffffff, 0x00000000,
80 0xf6c, 0x0fffffff, 0x00000000,
81 0xf6d, 0x0fffffff, 0x00000000,
82 0xf6e, 0x0fffffff, 0x00000000,
83};
84
85static const struct soc15_reg_golden golden_settings_mmhub_1_0_0[] =
86{
87 SOC15_REG_GOLDEN_VALUE(MMHUB, 0, mmDAGB1_WRCLI2, 0x00000007, 0xfe5fe0fa),
88 SOC15_REG_GOLDEN_VALUE(MMHUB, 0, mmMMEA1_DRAM_WR_CLI2GRP_MAP0, 0x00000030, 0x55555565)
89};
90
91static const struct soc15_reg_golden golden_settings_athub_1_0_0[] =
92{
93 SOC15_REG_GOLDEN_VALUE(ATHUB, 0, mmRPB_ARB_CNTL, 0x0000ff00, 0x00000800),
94 SOC15_REG_GOLDEN_VALUE(ATHUB, 0, mmRPB_ARB_CNTL2, 0x00ff00ff, 0x00080008)
95};
96
97static const uint32_t ecc_umc_mcumc_ctrl_addrs[] = {
98 (0x000143c0 + 0x00000000),
99 (0x000143c0 + 0x00000800),
100 (0x000143c0 + 0x00001000),
101 (0x000143c0 + 0x00001800),
102 (0x000543c0 + 0x00000000),
103 (0x000543c0 + 0x00000800),
104 (0x000543c0 + 0x00001000),
105 (0x000543c0 + 0x00001800),
106 (0x000943c0 + 0x00000000),
107 (0x000943c0 + 0x00000800),
108 (0x000943c0 + 0x00001000),
109 (0x000943c0 + 0x00001800),
110 (0x000d43c0 + 0x00000000),
111 (0x000d43c0 + 0x00000800),
112 (0x000d43c0 + 0x00001000),
113 (0x000d43c0 + 0x00001800),
114 (0x001143c0 + 0x00000000),
115 (0x001143c0 + 0x00000800),
116 (0x001143c0 + 0x00001000),
117 (0x001143c0 + 0x00001800),
118 (0x001543c0 + 0x00000000),
119 (0x001543c0 + 0x00000800),
120 (0x001543c0 + 0x00001000),
121 (0x001543c0 + 0x00001800),
122 (0x001943c0 + 0x00000000),
123 (0x001943c0 + 0x00000800),
124 (0x001943c0 + 0x00001000),
125 (0x001943c0 + 0x00001800),
126 (0x001d43c0 + 0x00000000),
127 (0x001d43c0 + 0x00000800),
128 (0x001d43c0 + 0x00001000),
129 (0x001d43c0 + 0x00001800),
130};
131
132static const uint32_t ecc_umc_mcumc_ctrl_mask_addrs[] = {
133 (0x000143e0 + 0x00000000),
134 (0x000143e0 + 0x00000800),
135 (0x000143e0 + 0x00001000),
136 (0x000143e0 + 0x00001800),
137 (0x000543e0 + 0x00000000),
138 (0x000543e0 + 0x00000800),
139 (0x000543e0 + 0x00001000),
140 (0x000543e0 + 0x00001800),
141 (0x000943e0 + 0x00000000),
142 (0x000943e0 + 0x00000800),
143 (0x000943e0 + 0x00001000),
144 (0x000943e0 + 0x00001800),
145 (0x000d43e0 + 0x00000000),
146 (0x000d43e0 + 0x00000800),
147 (0x000d43e0 + 0x00001000),
148 (0x000d43e0 + 0x00001800),
149 (0x001143e0 + 0x00000000),
150 (0x001143e0 + 0x00000800),
151 (0x001143e0 + 0x00001000),
152 (0x001143e0 + 0x00001800),
153 (0x001543e0 + 0x00000000),
154 (0x001543e0 + 0x00000800),
155 (0x001543e0 + 0x00001000),
156 (0x001543e0 + 0x00001800),
157 (0x001943e0 + 0x00000000),
158 (0x001943e0 + 0x00000800),
159 (0x001943e0 + 0x00001000),
160 (0x001943e0 + 0x00001800),
161 (0x001d43e0 + 0x00000000),
162 (0x001d43e0 + 0x00000800),
163 (0x001d43e0 + 0x00001000),
164 (0x001d43e0 + 0x00001800),
165};
166
167static const uint32_t ecc_umc_mcumc_status_addrs[] = {
168 (0x000143c2 + 0x00000000),
169 (0x000143c2 + 0x00000800),
170 (0x000143c2 + 0x00001000),
171 (0x000143c2 + 0x00001800),
172 (0x000543c2 + 0x00000000),
173 (0x000543c2 + 0x00000800),
174 (0x000543c2 + 0x00001000),
175 (0x000543c2 + 0x00001800),
176 (0x000943c2 + 0x00000000),
177 (0x000943c2 + 0x00000800),
178 (0x000943c2 + 0x00001000),
179 (0x000943c2 + 0x00001800),
180 (0x000d43c2 + 0x00000000),
181 (0x000d43c2 + 0x00000800),
182 (0x000d43c2 + 0x00001000),
183 (0x000d43c2 + 0x00001800),
184 (0x001143c2 + 0x00000000),
185 (0x001143c2 + 0x00000800),
186 (0x001143c2 + 0x00001000),
187 (0x001143c2 + 0x00001800),
188 (0x001543c2 + 0x00000000),
189 (0x001543c2 + 0x00000800),
190 (0x001543c2 + 0x00001000),
191 (0x001543c2 + 0x00001800),
192 (0x001943c2 + 0x00000000),
193 (0x001943c2 + 0x00000800),
194 (0x001943c2 + 0x00001000),
195 (0x001943c2 + 0x00001800),
196 (0x001d43c2 + 0x00000000),
197 (0x001d43c2 + 0x00000800),
198 (0x001d43c2 + 0x00001000),
199 (0x001d43c2 + 0x00001800),
200};
201
202static int gmc_v9_0_ecc_interrupt_state(struct amdgpu_device *adev,
203 struct amdgpu_irq_src *src,
204 unsigned type,
205 enum amdgpu_interrupt_state state)
206{
207 u32 bits, i, tmp, reg;
208
209 /* Devices newer then VEGA10/12 shall have these programming
210 sequences performed by PSP BL */
211 if (adev->asic_type >= CHIP_VEGA20)
212 return 0;
213
214 bits = 0x7f;
215
216 switch (state) {
217 case AMDGPU_IRQ_STATE_DISABLE:
218 for (i = 0; i < ARRAY_SIZE(ecc_umc_mcumc_ctrl_addrs); i++) {
219 reg = ecc_umc_mcumc_ctrl_addrs[i];
220 tmp = RREG32(reg);
221 tmp &= ~bits;
222 WREG32(reg, tmp);
223 }
224 for (i = 0; i < ARRAY_SIZE(ecc_umc_mcumc_ctrl_mask_addrs); i++) {
225 reg = ecc_umc_mcumc_ctrl_mask_addrs[i];
226 tmp = RREG32(reg);
227 tmp &= ~bits;
228 WREG32(reg, tmp);
229 }
230 break;
231 case AMDGPU_IRQ_STATE_ENABLE:
232 for (i = 0; i < ARRAY_SIZE(ecc_umc_mcumc_ctrl_addrs); i++) {
233 reg = ecc_umc_mcumc_ctrl_addrs[i];
234 tmp = RREG32(reg);
235 tmp |= bits;
236 WREG32(reg, tmp);
237 }
238 for (i = 0; i < ARRAY_SIZE(ecc_umc_mcumc_ctrl_mask_addrs); i++) {
239 reg = ecc_umc_mcumc_ctrl_mask_addrs[i];
240 tmp = RREG32(reg);
241 tmp |= bits;
242 WREG32(reg, tmp);
243 }
244 break;
245 default:
246 break;
247 }
248
249 return 0;
250}
251
252static int gmc_v9_0_vm_fault_interrupt_state(struct amdgpu_device *adev,
253 struct amdgpu_irq_src *src,
254 unsigned type,
255 enum amdgpu_interrupt_state state)
256{
257 struct amdgpu_vmhub *hub;
258 u32 tmp, reg, bits, i, j;
259
260 bits = VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
261 VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
262 VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
263 VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
264 VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
265 VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
266 VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK;
267
268 switch (state) {
269 case AMDGPU_IRQ_STATE_DISABLE:
270 for (j = 0; j < adev->num_vmhubs; j++) {
271 hub = &adev->vmhub[j];
272 for (i = 0; i < 16; i++) {
273 reg = hub->vm_context0_cntl + i;
274 tmp = RREG32(reg);
275 tmp &= ~bits;
276 WREG32(reg, tmp);
277 }
278 }
279 break;
280 case AMDGPU_IRQ_STATE_ENABLE:
281 for (j = 0; j < adev->num_vmhubs; j++) {
282 hub = &adev->vmhub[j];
283 for (i = 0; i < 16; i++) {
284 reg = hub->vm_context0_cntl + i;
285 tmp = RREG32(reg);
286 tmp |= bits;
287 WREG32(reg, tmp);
288 }
289 }
290 default:
291 break;
292 }
293
294 return 0;
295}
296
297static int gmc_v9_0_process_interrupt(struct amdgpu_device *adev,
298 struct amdgpu_irq_src *source,
299 struct amdgpu_iv_entry *entry)
300{
301 struct amdgpu_vmhub *hub;
302 bool retry_fault = !!(entry->src_data[1] & 0x80);
303 uint32_t status = 0;
304 u64 addr;
305 char hub_name[10];
306
307 addr = (u64)entry->src_data[0] << 12;
308 addr |= ((u64)entry->src_data[1] & 0xf) << 44;
309
310 if (retry_fault && amdgpu_gmc_filter_faults(adev, addr, entry->pasid,
311 entry->timestamp))
312 return 1; /* This also prevents sending it to KFD */
313
314 if (entry->client_id == SOC15_IH_CLIENTID_VMC) {
315 snprintf(hub_name, sizeof(hub_name), "mmhub0");
316 hub = &adev->vmhub[AMDGPU_MMHUB_0];
317 } else if (entry->client_id == SOC15_IH_CLIENTID_VMC1) {
318 snprintf(hub_name, sizeof(hub_name), "mmhub1");
319 hub = &adev->vmhub[AMDGPU_MMHUB_1];
320 } else {
321 snprintf(hub_name, sizeof(hub_name), "gfxhub0");
322 hub = &adev->vmhub[AMDGPU_GFXHUB_0];
323 }
324
325 /* If it's the first fault for this address, process it normally */
326 if (retry_fault && !in_interrupt() &&
327 amdgpu_vm_handle_fault(adev, entry->pasid, addr))
328 return 1; /* This also prevents sending it to KFD */
329
330 if (!amdgpu_sriov_vf(adev)) {
331 /*
332 * Issue a dummy read to wait for the status register to
333 * be updated to avoid reading an incorrect value due to
334 * the new fast GRBM interface.
335 */
336 if (entry->vmid_src == AMDGPU_GFXHUB_0)
337 RREG32(hub->vm_l2_pro_fault_status);
338
339 status = RREG32(hub->vm_l2_pro_fault_status);
340 WREG32_P(hub->vm_l2_pro_fault_cntl, 1, ~1);
341 }
342
343 if (printk_ratelimit()) {
344 struct amdgpu_task_info task_info;
345
346 memset(&task_info, 0, sizeof(struct amdgpu_task_info));
347 amdgpu_vm_get_task_info(adev, entry->pasid, &task_info);
348
349 dev_err(adev->dev,
350 "[%s] %s page fault (src_id:%u ring:%u vmid:%u "
351 "pasid:%u, for process %s pid %d thread %s pid %d)\n",
352 hub_name, retry_fault ? "retry" : "no-retry",
353 entry->src_id, entry->ring_id, entry->vmid,
354 entry->pasid, task_info.process_name, task_info.tgid,
355 task_info.task_name, task_info.pid);
356 dev_err(adev->dev, " in page starting at address 0x%016llx from client %d\n",
357 addr, entry->client_id);
358 if (!amdgpu_sriov_vf(adev)) {
359 dev_err(adev->dev,
360 "VM_L2_PROTECTION_FAULT_STATUS:0x%08X\n",
361 status);
362 dev_err(adev->dev, "\t Faulty UTCL2 client ID: 0x%lx\n",
363 REG_GET_FIELD(status,
364 VM_L2_PROTECTION_FAULT_STATUS, CID));
365 dev_err(adev->dev, "\t MORE_FAULTS: 0x%lx\n",
366 REG_GET_FIELD(status,
367 VM_L2_PROTECTION_FAULT_STATUS, MORE_FAULTS));
368 dev_err(adev->dev, "\t WALKER_ERROR: 0x%lx\n",
369 REG_GET_FIELD(status,
370 VM_L2_PROTECTION_FAULT_STATUS, WALKER_ERROR));
371 dev_err(adev->dev, "\t PERMISSION_FAULTS: 0x%lx\n",
372 REG_GET_FIELD(status,
373 VM_L2_PROTECTION_FAULT_STATUS, PERMISSION_FAULTS));
374 dev_err(adev->dev, "\t MAPPING_ERROR: 0x%lx\n",
375 REG_GET_FIELD(status,
376 VM_L2_PROTECTION_FAULT_STATUS, MAPPING_ERROR));
377 dev_err(adev->dev, "\t RW: 0x%lx\n",
378 REG_GET_FIELD(status,
379 VM_L2_PROTECTION_FAULT_STATUS, RW));
380
381 }
382 }
383
384 return 0;
385}
386
387static const struct amdgpu_irq_src_funcs gmc_v9_0_irq_funcs = {
388 .set = gmc_v9_0_vm_fault_interrupt_state,
389 .process = gmc_v9_0_process_interrupt,
390};
391
392
393static const struct amdgpu_irq_src_funcs gmc_v9_0_ecc_funcs = {
394 .set = gmc_v9_0_ecc_interrupt_state,
395 .process = amdgpu_umc_process_ecc_irq,
396};
397
398static void gmc_v9_0_set_irq_funcs(struct amdgpu_device *adev)
399{
400 adev->gmc.vm_fault.num_types = 1;
401 adev->gmc.vm_fault.funcs = &gmc_v9_0_irq_funcs;
402
403 if (!amdgpu_sriov_vf(adev)) {
404 adev->gmc.ecc_irq.num_types = 1;
405 adev->gmc.ecc_irq.funcs = &gmc_v9_0_ecc_funcs;
406 }
407}
408
409static uint32_t gmc_v9_0_get_invalidate_req(unsigned int vmid,
410 uint32_t flush_type)
411{
412 u32 req = 0;
413
414 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ,
415 PER_VMID_INVALIDATE_REQ, 1 << vmid);
416 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, FLUSH_TYPE, flush_type);
417 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PTES, 1);
418 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE0, 1);
419 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE1, 1);
420 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE2, 1);
421 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L1_PTES, 1);
422 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ,
423 CLEAR_PROTECTION_FAULT_STATUS_ADDR, 0);
424
425 return req;
426}
427
428/**
429 * gmc_v9_0_use_invalidate_semaphore - judge whether to use semaphore
430 *
431 * @adev: amdgpu_device pointer
432 * @vmhub: vmhub type
433 *
434 */
435static bool gmc_v9_0_use_invalidate_semaphore(struct amdgpu_device *adev,
436 uint32_t vmhub)
437{
438 return ((vmhub == AMDGPU_MMHUB_0 ||
439 vmhub == AMDGPU_MMHUB_1) &&
440 (!amdgpu_sriov_vf(adev)) &&
441 (!(!(adev->apu_flags & AMD_APU_IS_RAVEN2) &&
442 (adev->apu_flags & AMD_APU_IS_PICASSO))));
443}
444
445static bool gmc_v9_0_get_atc_vmid_pasid_mapping_info(struct amdgpu_device *adev,
446 uint8_t vmid, uint16_t *p_pasid)
447{
448 uint32_t value;
449
450 value = RREG32(SOC15_REG_OFFSET(ATHUB, 0, mmATC_VMID0_PASID_MAPPING)
451 + vmid);
452 *p_pasid = value & ATC_VMID0_PASID_MAPPING__PASID_MASK;
453
454 return !!(value & ATC_VMID0_PASID_MAPPING__VALID_MASK);
455}
456
457/*
458 * GART
459 * VMID 0 is the physical GPU addresses as used by the kernel.
460 * VMIDs 1-15 are used for userspace clients and are handled
461 * by the amdgpu vm/hsa code.
462 */
463
464/**
465 * gmc_v9_0_flush_gpu_tlb - tlb flush with certain type
466 *
467 * @adev: amdgpu_device pointer
468 * @vmid: vm instance to flush
469 * @flush_type: the flush type
470 *
471 * Flush the TLB for the requested page table using certain type.
472 */
473static void gmc_v9_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid,
474 uint32_t vmhub, uint32_t flush_type)
475{
476 bool use_semaphore = gmc_v9_0_use_invalidate_semaphore(adev, vmhub);
477 const unsigned eng = 17;
478 u32 j, inv_req, inv_req2, tmp;
479 struct amdgpu_vmhub *hub;
480
481 BUG_ON(vmhub >= adev->num_vmhubs);
482
483 hub = &adev->vmhub[vmhub];
484 if (adev->gmc.xgmi.num_physical_nodes &&
485 adev->asic_type == CHIP_VEGA20) {
486 /* Vega20+XGMI caches PTEs in TC and TLB. Add a
487 * heavy-weight TLB flush (type 2), which flushes
488 * both. Due to a race condition with concurrent
489 * memory accesses using the same TLB cache line, we
490 * still need a second TLB flush after this.
491 */
492 inv_req = gmc_v9_0_get_invalidate_req(vmid, 2);
493 inv_req2 = gmc_v9_0_get_invalidate_req(vmid, flush_type);
494 } else {
495 inv_req = gmc_v9_0_get_invalidate_req(vmid, flush_type);
496 inv_req2 = 0;
497 }
498
499 /* This is necessary for a HW workaround under SRIOV as well
500 * as GFXOFF under bare metal
501 */
502 if (adev->gfx.kiq.ring.sched.ready &&
503 (amdgpu_sriov_runtime(adev) || !amdgpu_sriov_vf(adev)) &&
504 !adev->in_gpu_reset) {
505 uint32_t req = hub->vm_inv_eng0_req + hub->eng_distance * eng;
506 uint32_t ack = hub->vm_inv_eng0_ack + hub->eng_distance * eng;
507
508 amdgpu_virt_kiq_reg_write_reg_wait(adev, req, ack, inv_req,
509 1 << vmid);
510 return;
511 }
512
513 spin_lock(&adev->gmc.invalidate_lock);
514
515 /*
516 * It may lose gpuvm invalidate acknowldege state across power-gating
517 * off cycle, add semaphore acquire before invalidation and semaphore
518 * release after invalidation to avoid entering power gated state
519 * to WA the Issue
520 */
521
522 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */
523 if (use_semaphore) {
524 for (j = 0; j < adev->usec_timeout; j++) {
525 /* a read return value of 1 means semaphore acuqire */
526 tmp = RREG32_NO_KIQ(hub->vm_inv_eng0_sem +
527 hub->eng_distance * eng);
528 if (tmp & 0x1)
529 break;
530 udelay(1);
531 }
532
533 if (j >= adev->usec_timeout)
534 DRM_ERROR("Timeout waiting for sem acquire in VM flush!\n");
535 }
536
537 do {
538 WREG32_NO_KIQ(hub->vm_inv_eng0_req +
539 hub->eng_distance * eng, inv_req);
540
541 /*
542 * Issue a dummy read to wait for the ACK register to
543 * be cleared to avoid a false ACK due to the new fast
544 * GRBM interface.
545 */
546 if (vmhub == AMDGPU_GFXHUB_0)
547 RREG32_NO_KIQ(hub->vm_inv_eng0_req +
548 hub->eng_distance * eng);
549
550 for (j = 0; j < adev->usec_timeout; j++) {
551 tmp = RREG32_NO_KIQ(hub->vm_inv_eng0_ack +
552 hub->eng_distance * eng);
553 if (tmp & (1 << vmid))
554 break;
555 udelay(1);
556 }
557
558 inv_req = inv_req2;
559 inv_req2 = 0;
560 } while (inv_req);
561
562 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */
563 if (use_semaphore)
564 /*
565 * add semaphore release after invalidation,
566 * write with 0 means semaphore release
567 */
568 WREG32_NO_KIQ(hub->vm_inv_eng0_sem +
569 hub->eng_distance * eng, 0);
570
571 spin_unlock(&adev->gmc.invalidate_lock);
572
573 if (j < adev->usec_timeout)
574 return;
575
576 DRM_ERROR("Timeout waiting for VM flush ACK!\n");
577}
578
579/**
580 * gmc_v9_0_flush_gpu_tlb_pasid - tlb flush via pasid
581 *
582 * @adev: amdgpu_device pointer
583 * @pasid: pasid to be flush
584 *
585 * Flush the TLB for the requested pasid.
586 */
587static int gmc_v9_0_flush_gpu_tlb_pasid(struct amdgpu_device *adev,
588 uint16_t pasid, uint32_t flush_type,
589 bool all_hub)
590{
591 int vmid, i;
592 signed long r;
593 uint32_t seq;
594 uint16_t queried_pasid;
595 bool ret;
596 struct amdgpu_ring *ring = &adev->gfx.kiq.ring;
597 struct amdgpu_kiq *kiq = &adev->gfx.kiq;
598
599 if (adev->in_gpu_reset)
600 return -EIO;
601
602 if (ring->sched.ready) {
603 /* Vega20+XGMI caches PTEs in TC and TLB. Add a
604 * heavy-weight TLB flush (type 2), which flushes
605 * both. Due to a race condition with concurrent
606 * memory accesses using the same TLB cache line, we
607 * still need a second TLB flush after this.
608 */
609 bool vega20_xgmi_wa = (adev->gmc.xgmi.num_physical_nodes &&
610 adev->asic_type == CHIP_VEGA20);
611 /* 2 dwords flush + 8 dwords fence */
612 unsigned int ndw = kiq->pmf->invalidate_tlbs_size + 8;
613
614 if (vega20_xgmi_wa)
615 ndw += kiq->pmf->invalidate_tlbs_size;
616
617 spin_lock(&adev->gfx.kiq.ring_lock);
618 /* 2 dwords flush + 8 dwords fence */
619 amdgpu_ring_alloc(ring, ndw);
620 if (vega20_xgmi_wa)
621 kiq->pmf->kiq_invalidate_tlbs(ring,
622 pasid, 2, all_hub);
623 kiq->pmf->kiq_invalidate_tlbs(ring,
624 pasid, flush_type, all_hub);
625 r = amdgpu_fence_emit_polling(ring, &seq, MAX_KIQ_REG_WAIT);
626 if (r) {
627 amdgpu_ring_undo(ring);
628 spin_unlock(&adev->gfx.kiq.ring_lock);
629 return -ETIME;
630 }
631
632 amdgpu_ring_commit(ring);
633 spin_unlock(&adev->gfx.kiq.ring_lock);
634 r = amdgpu_fence_wait_polling(ring, seq, adev->usec_timeout);
635 if (r < 1) {
636 DRM_ERROR("wait for kiq fence error: %ld.\n", r);
637 return -ETIME;
638 }
639
640 return 0;
641 }
642
643 for (vmid = 1; vmid < 16; vmid++) {
644
645 ret = gmc_v9_0_get_atc_vmid_pasid_mapping_info(adev, vmid,
646 &queried_pasid);
647 if (ret && queried_pasid == pasid) {
648 if (all_hub) {
649 for (i = 0; i < adev->num_vmhubs; i++)
650 gmc_v9_0_flush_gpu_tlb(adev, vmid,
651 i, flush_type);
652 } else {
653 gmc_v9_0_flush_gpu_tlb(adev, vmid,
654 AMDGPU_GFXHUB_0, flush_type);
655 }
656 break;
657 }
658 }
659
660 return 0;
661
662}
663
664static uint64_t gmc_v9_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring,
665 unsigned vmid, uint64_t pd_addr)
666{
667 bool use_semaphore = gmc_v9_0_use_invalidate_semaphore(ring->adev, ring->funcs->vmhub);
668 struct amdgpu_device *adev = ring->adev;
669 struct amdgpu_vmhub *hub = &adev->vmhub[ring->funcs->vmhub];
670 uint32_t req = gmc_v9_0_get_invalidate_req(vmid, 0);
671 unsigned eng = ring->vm_inv_eng;
672
673 /*
674 * It may lose gpuvm invalidate acknowldege state across power-gating
675 * off cycle, add semaphore acquire before invalidation and semaphore
676 * release after invalidation to avoid entering power gated state
677 * to WA the Issue
678 */
679
680 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */
681 if (use_semaphore)
682 /* a read return value of 1 means semaphore acuqire */
683 amdgpu_ring_emit_reg_wait(ring,
684 hub->vm_inv_eng0_sem +
685 hub->eng_distance * eng, 0x1, 0x1);
686
687 amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_lo32 +
688 (hub->ctx_addr_distance * vmid),
689 lower_32_bits(pd_addr));
690
691 amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_hi32 +
692 (hub->ctx_addr_distance * vmid),
693 upper_32_bits(pd_addr));
694
695 amdgpu_ring_emit_reg_write_reg_wait(ring, hub->vm_inv_eng0_req +
696 hub->eng_distance * eng,
697 hub->vm_inv_eng0_ack +
698 hub->eng_distance * eng,
699 req, 1 << vmid);
700
701 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */
702 if (use_semaphore)
703 /*
704 * add semaphore release after invalidation,
705 * write with 0 means semaphore release
706 */
707 amdgpu_ring_emit_wreg(ring, hub->vm_inv_eng0_sem +
708 hub->eng_distance * eng, 0);
709
710 return pd_addr;
711}
712
713static void gmc_v9_0_emit_pasid_mapping(struct amdgpu_ring *ring, unsigned vmid,
714 unsigned pasid)
715{
716 struct amdgpu_device *adev = ring->adev;
717 uint32_t reg;
718
719 /* Do nothing because there's no lut register for mmhub1. */
720 if (ring->funcs->vmhub == AMDGPU_MMHUB_1)
721 return;
722
723 if (ring->funcs->vmhub == AMDGPU_GFXHUB_0)
724 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT) + vmid;
725 else
726 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT_MM) + vmid;
727
728 amdgpu_ring_emit_wreg(ring, reg, pasid);
729}
730
731/*
732 * PTE format on VEGA 10:
733 * 63:59 reserved
734 * 58:57 mtype
735 * 56 F
736 * 55 L
737 * 54 P
738 * 53 SW
739 * 52 T
740 * 50:48 reserved
741 * 47:12 4k physical page base address
742 * 11:7 fragment
743 * 6 write
744 * 5 read
745 * 4 exe
746 * 3 Z
747 * 2 snooped
748 * 1 system
749 * 0 valid
750 *
751 * PDE format on VEGA 10:
752 * 63:59 block fragment size
753 * 58:55 reserved
754 * 54 P
755 * 53:48 reserved
756 * 47:6 physical base address of PD or PTE
757 * 5:3 reserved
758 * 2 C
759 * 1 system
760 * 0 valid
761 */
762
763static uint64_t gmc_v9_0_map_mtype(struct amdgpu_device *adev, uint32_t flags)
764
765{
766 switch (flags) {
767 case AMDGPU_VM_MTYPE_DEFAULT:
768 return AMDGPU_PTE_MTYPE_VG10(MTYPE_NC);
769 case AMDGPU_VM_MTYPE_NC:
770 return AMDGPU_PTE_MTYPE_VG10(MTYPE_NC);
771 case AMDGPU_VM_MTYPE_WC:
772 return AMDGPU_PTE_MTYPE_VG10(MTYPE_WC);
773 case AMDGPU_VM_MTYPE_RW:
774 return AMDGPU_PTE_MTYPE_VG10(MTYPE_RW);
775 case AMDGPU_VM_MTYPE_CC:
776 return AMDGPU_PTE_MTYPE_VG10(MTYPE_CC);
777 case AMDGPU_VM_MTYPE_UC:
778 return AMDGPU_PTE_MTYPE_VG10(MTYPE_UC);
779 default:
780 return AMDGPU_PTE_MTYPE_VG10(MTYPE_NC);
781 }
782}
783
784static void gmc_v9_0_get_vm_pde(struct amdgpu_device *adev, int level,
785 uint64_t *addr, uint64_t *flags)
786{
787 if (!(*flags & AMDGPU_PDE_PTE) && !(*flags & AMDGPU_PTE_SYSTEM))
788 *addr = adev->vm_manager.vram_base_offset + *addr -
789 adev->gmc.vram_start;
790 BUG_ON(*addr & 0xFFFF00000000003FULL);
791
792 if (!adev->gmc.translate_further)
793 return;
794
795 if (level == AMDGPU_VM_PDB1) {
796 /* Set the block fragment size */
797 if (!(*flags & AMDGPU_PDE_PTE))
798 *flags |= AMDGPU_PDE_BFS(0x9);
799
800 } else if (level == AMDGPU_VM_PDB0) {
801 if (*flags & AMDGPU_PDE_PTE)
802 *flags &= ~AMDGPU_PDE_PTE;
803 else
804 *flags |= AMDGPU_PTE_TF;
805 }
806}
807
808static void gmc_v9_0_get_vm_pte(struct amdgpu_device *adev,
809 struct amdgpu_bo_va_mapping *mapping,
810 uint64_t *flags)
811{
812 *flags &= ~AMDGPU_PTE_EXECUTABLE;
813 *flags |= mapping->flags & AMDGPU_PTE_EXECUTABLE;
814
815 *flags &= ~AMDGPU_PTE_MTYPE_VG10_MASK;
816 *flags |= mapping->flags & AMDGPU_PTE_MTYPE_VG10_MASK;
817
818 if (mapping->flags & AMDGPU_PTE_PRT) {
819 *flags |= AMDGPU_PTE_PRT;
820 *flags &= ~AMDGPU_PTE_VALID;
821 }
822
823 if (adev->asic_type == CHIP_ARCTURUS &&
824 !(*flags & AMDGPU_PTE_SYSTEM) &&
825 mapping->bo_va->is_xgmi)
826 *flags |= AMDGPU_PTE_SNOOPED;
827}
828
829static const struct amdgpu_gmc_funcs gmc_v9_0_gmc_funcs = {
830 .flush_gpu_tlb = gmc_v9_0_flush_gpu_tlb,
831 .flush_gpu_tlb_pasid = gmc_v9_0_flush_gpu_tlb_pasid,
832 .emit_flush_gpu_tlb = gmc_v9_0_emit_flush_gpu_tlb,
833 .emit_pasid_mapping = gmc_v9_0_emit_pasid_mapping,
834 .map_mtype = gmc_v9_0_map_mtype,
835 .get_vm_pde = gmc_v9_0_get_vm_pde,
836 .get_vm_pte = gmc_v9_0_get_vm_pte
837};
838
839static void gmc_v9_0_set_gmc_funcs(struct amdgpu_device *adev)
840{
841 adev->gmc.gmc_funcs = &gmc_v9_0_gmc_funcs;
842}
843
844static void gmc_v9_0_set_umc_funcs(struct amdgpu_device *adev)
845{
846 switch (adev->asic_type) {
847 case CHIP_VEGA10:
848 adev->umc.funcs = &umc_v6_0_funcs;
849 break;
850 case CHIP_VEGA20:
851 adev->umc.max_ras_err_cnt_per_query = UMC_V6_1_TOTAL_CHANNEL_NUM;
852 adev->umc.channel_inst_num = UMC_V6_1_CHANNEL_INSTANCE_NUM;
853 adev->umc.umc_inst_num = UMC_V6_1_UMC_INSTANCE_NUM;
854 adev->umc.channel_offs = UMC_V6_1_PER_CHANNEL_OFFSET_VG20;
855 adev->umc.channel_idx_tbl = &umc_v6_1_channel_idx_tbl[0][0];
856 adev->umc.funcs = &umc_v6_1_funcs;
857 break;
858 case CHIP_ARCTURUS:
859 adev->umc.max_ras_err_cnt_per_query = UMC_V6_1_TOTAL_CHANNEL_NUM;
860 adev->umc.channel_inst_num = UMC_V6_1_CHANNEL_INSTANCE_NUM;
861 adev->umc.umc_inst_num = UMC_V6_1_UMC_INSTANCE_NUM;
862 adev->umc.channel_offs = UMC_V6_1_PER_CHANNEL_OFFSET_ARCT;
863 adev->umc.channel_idx_tbl = &umc_v6_1_channel_idx_tbl[0][0];
864 adev->umc.funcs = &umc_v6_1_funcs;
865 break;
866 default:
867 break;
868 }
869}
870
871static void gmc_v9_0_set_mmhub_funcs(struct amdgpu_device *adev)
872{
873 switch (adev->asic_type) {
874 case CHIP_VEGA20:
875 adev->mmhub.funcs = &mmhub_v1_0_funcs;
876 break;
877 case CHIP_ARCTURUS:
878 adev->mmhub.funcs = &mmhub_v9_4_funcs;
879 break;
880 default:
881 break;
882 }
883}
884
885static int gmc_v9_0_early_init(void *handle)
886{
887 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
888
889 gmc_v9_0_set_gmc_funcs(adev);
890 gmc_v9_0_set_irq_funcs(adev);
891 gmc_v9_0_set_umc_funcs(adev);
892 gmc_v9_0_set_mmhub_funcs(adev);
893
894 adev->gmc.shared_aperture_start = 0x2000000000000000ULL;
895 adev->gmc.shared_aperture_end =
896 adev->gmc.shared_aperture_start + (4ULL << 30) - 1;
897 adev->gmc.private_aperture_start = 0x1000000000000000ULL;
898 adev->gmc.private_aperture_end =
899 adev->gmc.private_aperture_start + (4ULL << 30) - 1;
900
901 return 0;
902}
903
904static bool gmc_v9_0_keep_stolen_memory(struct amdgpu_device *adev)
905{
906
907 /*
908 * TODO:
909 * Currently there is a bug where some memory client outside
910 * of the driver writes to first 8M of VRAM on S3 resume,
911 * this overrides GART which by default gets placed in first 8M and
912 * causes VM_FAULTS once GTT is accessed.
913 * Keep the stolen memory reservation until the while this is not solved.
914 * Also check code in gmc_v9_0_get_vbios_fb_size and gmc_v9_0_late_init
915 */
916 switch (adev->asic_type) {
917 case CHIP_VEGA10:
918 case CHIP_RAVEN:
919 case CHIP_ARCTURUS:
920 case CHIP_RENOIR:
921 return true;
922 case CHIP_VEGA12:
923 case CHIP_VEGA20:
924 default:
925 return false;
926 }
927}
928
929static int gmc_v9_0_late_init(void *handle)
930{
931 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
932 int r;
933
934 if (!gmc_v9_0_keep_stolen_memory(adev))
935 amdgpu_bo_late_init(adev);
936
937 r = amdgpu_gmc_allocate_vm_inv_eng(adev);
938 if (r)
939 return r;
940 /* Check if ecc is available */
941 if (!amdgpu_sriov_vf(adev) && (adev->asic_type == CHIP_VEGA10)) {
942 r = amdgpu_atomfirmware_mem_ecc_supported(adev);
943 if (!r) {
944 DRM_INFO("ECC is not present.\n");
945 if (adev->df.funcs->enable_ecc_force_par_wr_rmw)
946 adev->df.funcs->enable_ecc_force_par_wr_rmw(adev, false);
947 } else
948 DRM_INFO("ECC is active.\n");
949
950 r = amdgpu_atomfirmware_sram_ecc_supported(adev);
951 if (!r)
952 DRM_INFO("SRAM ECC is not present.\n");
953 else
954 DRM_INFO("SRAM ECC is active.\n");
955 }
956
957 if (adev->mmhub.funcs && adev->mmhub.funcs->reset_ras_error_count)
958 adev->mmhub.funcs->reset_ras_error_count(adev);
959
960 r = amdgpu_gmc_ras_late_init(adev);
961 if (r)
962 return r;
963
964 return amdgpu_irq_get(adev, &adev->gmc.vm_fault, 0);
965}
966
967static void gmc_v9_0_vram_gtt_location(struct amdgpu_device *adev,
968 struct amdgpu_gmc *mc)
969{
970 u64 base = 0;
971
972 if (adev->asic_type == CHIP_ARCTURUS)
973 base = mmhub_v9_4_get_fb_location(adev);
974 else if (!amdgpu_sriov_vf(adev))
975 base = mmhub_v1_0_get_fb_location(adev);
976
977 /* add the xgmi offset of the physical node */
978 base += adev->gmc.xgmi.physical_node_id * adev->gmc.xgmi.node_segment_size;
979 amdgpu_gmc_vram_location(adev, mc, base);
980 amdgpu_gmc_gart_location(adev, mc);
981 amdgpu_gmc_agp_location(adev, mc);
982 /* base offset of vram pages */
983 adev->vm_manager.vram_base_offset = gfxhub_v1_0_get_mc_fb_offset(adev);
984
985 /* XXX: add the xgmi offset of the physical node? */
986 adev->vm_manager.vram_base_offset +=
987 adev->gmc.xgmi.physical_node_id * adev->gmc.xgmi.node_segment_size;
988}
989
990/**
991 * gmc_v9_0_mc_init - initialize the memory controller driver params
992 *
993 * @adev: amdgpu_device pointer
994 *
995 * Look up the amount of vram, vram width, and decide how to place
996 * vram and gart within the GPU's physical address space.
997 * Returns 0 for success.
998 */
999static int gmc_v9_0_mc_init(struct amdgpu_device *adev)
1000{
1001 int r;
1002
1003 /* size in MB on si */
1004 adev->gmc.mc_vram_size =
1005 adev->nbio.funcs->get_memsize(adev) * 1024ULL * 1024ULL;
1006 adev->gmc.real_vram_size = adev->gmc.mc_vram_size;
1007
1008 if (!(adev->flags & AMD_IS_APU)) {
1009 r = amdgpu_device_resize_fb_bar(adev);
1010 if (r)
1011 return r;
1012 }
1013 adev->gmc.aper_base = pci_resource_start(adev->pdev, 0);
1014 adev->gmc.aper_size = pci_resource_len(adev->pdev, 0);
1015
1016#ifdef CONFIG_X86_64
1017 if (adev->flags & AMD_IS_APU) {
1018 adev->gmc.aper_base = gfxhub_v1_0_get_mc_fb_offset(adev);
1019 adev->gmc.aper_size = adev->gmc.real_vram_size;
1020 }
1021#endif
1022 /* In case the PCI BAR is larger than the actual amount of vram */
1023 adev->gmc.visible_vram_size = adev->gmc.aper_size;
1024 if (adev->gmc.visible_vram_size > adev->gmc.real_vram_size)
1025 adev->gmc.visible_vram_size = adev->gmc.real_vram_size;
1026
1027 /* set the gart size */
1028 if (amdgpu_gart_size == -1) {
1029 switch (adev->asic_type) {
1030 case CHIP_VEGA10: /* all engines support GPUVM */
1031 case CHIP_VEGA12: /* all engines support GPUVM */
1032 case CHIP_VEGA20:
1033 case CHIP_ARCTURUS:
1034 default:
1035 adev->gmc.gart_size = 512ULL << 20;
1036 break;
1037 case CHIP_RAVEN: /* DCE SG support */
1038 case CHIP_RENOIR:
1039 adev->gmc.gart_size = 1024ULL << 20;
1040 break;
1041 }
1042 } else {
1043 adev->gmc.gart_size = (u64)amdgpu_gart_size << 20;
1044 }
1045
1046 gmc_v9_0_vram_gtt_location(adev, &adev->gmc);
1047
1048 return 0;
1049}
1050
1051static int gmc_v9_0_gart_init(struct amdgpu_device *adev)
1052{
1053 int r;
1054
1055 if (adev->gart.bo) {
1056 WARN(1, "VEGA10 PCIE GART already initialized\n");
1057 return 0;
1058 }
1059 /* Initialize common gart structure */
1060 r = amdgpu_gart_init(adev);
1061 if (r)
1062 return r;
1063 adev->gart.table_size = adev->gart.num_gpu_pages * 8;
1064 adev->gart.gart_pte_flags = AMDGPU_PTE_MTYPE_VG10(MTYPE_UC) |
1065 AMDGPU_PTE_EXECUTABLE;
1066 return amdgpu_gart_table_vram_alloc(adev);
1067}
1068
1069static unsigned gmc_v9_0_get_vbios_fb_size(struct amdgpu_device *adev)
1070{
1071 u32 d1vga_control;
1072 unsigned size;
1073
1074 /*
1075 * TODO Remove once GART corruption is resolved
1076 * Check related code in gmc_v9_0_sw_fini
1077 * */
1078 if (gmc_v9_0_keep_stolen_memory(adev))
1079 return 9 * 1024 * 1024;
1080
1081 d1vga_control = RREG32_SOC15(DCE, 0, mmD1VGA_CONTROL);
1082 if (REG_GET_FIELD(d1vga_control, D1VGA_CONTROL, D1VGA_MODE_ENABLE)) {
1083 size = 9 * 1024 * 1024; /* reserve 8MB for vga emulator and 1 MB for FB */
1084 } else {
1085 u32 viewport;
1086
1087 switch (adev->asic_type) {
1088 case CHIP_RAVEN:
1089 case CHIP_RENOIR:
1090 viewport = RREG32_SOC15(DCE, 0, mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION);
1091 size = (REG_GET_FIELD(viewport,
1092 HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_HEIGHT) *
1093 REG_GET_FIELD(viewport,
1094 HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_WIDTH) *
1095 4);
1096 break;
1097 case CHIP_VEGA10:
1098 case CHIP_VEGA12:
1099 case CHIP_VEGA20:
1100 default:
1101 viewport = RREG32_SOC15(DCE, 0, mmSCL0_VIEWPORT_SIZE);
1102 size = (REG_GET_FIELD(viewport, SCL0_VIEWPORT_SIZE, VIEWPORT_HEIGHT) *
1103 REG_GET_FIELD(viewport, SCL0_VIEWPORT_SIZE, VIEWPORT_WIDTH) *
1104 4);
1105 break;
1106 }
1107 }
1108 /* return 0 if the pre-OS buffer uses up most of vram */
1109 if ((adev->gmc.real_vram_size - size) < (8 * 1024 * 1024))
1110 return 0;
1111
1112 return size;
1113}
1114
1115static int gmc_v9_0_sw_init(void *handle)
1116{
1117 int r, vram_width = 0, vram_type = 0, vram_vendor = 0;
1118 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1119
1120 gfxhub_v1_0_init(adev);
1121 if (adev->asic_type == CHIP_ARCTURUS)
1122 mmhub_v9_4_init(adev);
1123 else
1124 mmhub_v1_0_init(adev);
1125
1126 spin_lock_init(&adev->gmc.invalidate_lock);
1127
1128 r = amdgpu_atomfirmware_get_vram_info(adev,
1129 &vram_width, &vram_type, &vram_vendor);
1130 if (amdgpu_sriov_vf(adev))
1131 /* For Vega10 SR-IOV, vram_width can't be read from ATOM as RAVEN,
1132 * and DF related registers is not readable, seems hardcord is the
1133 * only way to set the correct vram_width
1134 */
1135 adev->gmc.vram_width = 2048;
1136 else if (amdgpu_emu_mode != 1)
1137 adev->gmc.vram_width = vram_width;
1138
1139 if (!adev->gmc.vram_width) {
1140 int chansize, numchan;
1141
1142 /* hbm memory channel size */
1143 if (adev->flags & AMD_IS_APU)
1144 chansize = 64;
1145 else
1146 chansize = 128;
1147
1148 numchan = adev->df.funcs->get_hbm_channel_number(adev);
1149 adev->gmc.vram_width = numchan * chansize;
1150 }
1151
1152 adev->gmc.vram_type = vram_type;
1153 adev->gmc.vram_vendor = vram_vendor;
1154 switch (adev->asic_type) {
1155 case CHIP_RAVEN:
1156 adev->num_vmhubs = 2;
1157
1158 if (adev->rev_id == 0x0 || adev->rev_id == 0x1) {
1159 amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48);
1160 } else {
1161 /* vm_size is 128TB + 512GB for legacy 3-level page support */
1162 amdgpu_vm_adjust_size(adev, 128 * 1024 + 512, 9, 2, 48);
1163 adev->gmc.translate_further =
1164 adev->vm_manager.num_level > 1;
1165 }
1166 break;
1167 case CHIP_VEGA10:
1168 case CHIP_VEGA12:
1169 case CHIP_VEGA20:
1170 case CHIP_RENOIR:
1171 adev->num_vmhubs = 2;
1172
1173
1174 /*
1175 * To fulfill 4-level page support,
1176 * vm size is 256TB (48bit), maximum size of Vega10,
1177 * block size 512 (9bit)
1178 */
1179 /* sriov restrict max_pfn below AMDGPU_GMC_HOLE */
1180 if (amdgpu_sriov_vf(adev))
1181 amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 47);
1182 else
1183 amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48);
1184 break;
1185 case CHIP_ARCTURUS:
1186 adev->num_vmhubs = 3;
1187
1188 /* Keep the vm size same with Vega20 */
1189 amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48);
1190 break;
1191 default:
1192 break;
1193 }
1194
1195 /* This interrupt is VMC page fault.*/
1196 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VMC, VMC_1_0__SRCID__VM_FAULT,
1197 &adev->gmc.vm_fault);
1198 if (r)
1199 return r;
1200
1201 if (adev->asic_type == CHIP_ARCTURUS) {
1202 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VMC1, VMC_1_0__SRCID__VM_FAULT,
1203 &adev->gmc.vm_fault);
1204 if (r)
1205 return r;
1206 }
1207
1208 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_UTCL2, UTCL2_1_0__SRCID__FAULT,
1209 &adev->gmc.vm_fault);
1210
1211 if (r)
1212 return r;
1213
1214 if (!amdgpu_sriov_vf(adev)) {
1215 /* interrupt sent to DF. */
1216 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DF, 0,
1217 &adev->gmc.ecc_irq);
1218 if (r)
1219 return r;
1220 }
1221
1222 /* Set the internal MC address mask
1223 * This is the max address of the GPU's
1224 * internal address space.
1225 */
1226 adev->gmc.mc_mask = 0xffffffffffffULL; /* 48 bit MC */
1227
1228 r = dma_set_mask_and_coherent(adev->dev, DMA_BIT_MASK(44));
1229 if (r) {
1230 printk(KERN_WARNING "amdgpu: No suitable DMA available.\n");
1231 return r;
1232 }
1233 adev->need_swiotlb = drm_need_swiotlb(44);
1234
1235 if (adev->gmc.xgmi.supported) {
1236 r = gfxhub_v1_1_get_xgmi_info(adev);
1237 if (r)
1238 return r;
1239 }
1240
1241 r = gmc_v9_0_mc_init(adev);
1242 if (r)
1243 return r;
1244
1245 adev->gmc.stolen_size = gmc_v9_0_get_vbios_fb_size(adev);
1246
1247 /* Memory manager */
1248 r = amdgpu_bo_init(adev);
1249 if (r)
1250 return r;
1251
1252 r = gmc_v9_0_gart_init(adev);
1253 if (r)
1254 return r;
1255
1256 /*
1257 * number of VMs
1258 * VMID 0 is reserved for System
1259 * amdgpu graphics/compute will use VMIDs 1..n-1
1260 * amdkfd will use VMIDs n..15
1261 *
1262 * The first KFD VMID is 8 for GPUs with graphics, 3 for
1263 * compute-only GPUs. On compute-only GPUs that leaves 2 VMIDs
1264 * for video processing.
1265 */
1266 adev->vm_manager.first_kfd_vmid =
1267 adev->asic_type == CHIP_ARCTURUS ? 3 : 8;
1268
1269 amdgpu_vm_manager_init(adev);
1270
1271 return 0;
1272}
1273
1274static int gmc_v9_0_sw_fini(void *handle)
1275{
1276 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1277 void *stolen_vga_buf;
1278
1279 amdgpu_gmc_ras_fini(adev);
1280 amdgpu_gem_force_release(adev);
1281 amdgpu_vm_manager_fini(adev);
1282
1283 if (gmc_v9_0_keep_stolen_memory(adev))
1284 amdgpu_bo_free_kernel(&adev->stolen_vga_memory, NULL, &stolen_vga_buf);
1285
1286 amdgpu_gart_table_vram_free(adev);
1287 amdgpu_bo_fini(adev);
1288 amdgpu_gart_fini(adev);
1289
1290 return 0;
1291}
1292
1293static void gmc_v9_0_init_golden_registers(struct amdgpu_device *adev)
1294{
1295
1296 switch (adev->asic_type) {
1297 case CHIP_VEGA10:
1298 if (amdgpu_sriov_vf(adev))
1299 break;
1300 fallthrough;
1301 case CHIP_VEGA20:
1302 soc15_program_register_sequence(adev,
1303 golden_settings_mmhub_1_0_0,
1304 ARRAY_SIZE(golden_settings_mmhub_1_0_0));
1305 soc15_program_register_sequence(adev,
1306 golden_settings_athub_1_0_0,
1307 ARRAY_SIZE(golden_settings_athub_1_0_0));
1308 break;
1309 case CHIP_VEGA12:
1310 break;
1311 case CHIP_RAVEN:
1312 /* TODO for renoir */
1313 soc15_program_register_sequence(adev,
1314 golden_settings_athub_1_0_0,
1315 ARRAY_SIZE(golden_settings_athub_1_0_0));
1316 break;
1317 default:
1318 break;
1319 }
1320}
1321
1322/**
1323 * gmc_v9_0_restore_registers - restores regs
1324 *
1325 * @adev: amdgpu_device pointer
1326 *
1327 * This restores register values, saved at suspend.
1328 */
1329static void gmc_v9_0_restore_registers(struct amdgpu_device *adev)
1330{
1331 if (adev->asic_type == CHIP_RAVEN)
1332 WREG32(mmDCHUBBUB_SDPIF_MMIO_CNTRL_0, adev->gmc.sdpif_register);
1333}
1334
1335/**
1336 * gmc_v9_0_gart_enable - gart enable
1337 *
1338 * @adev: amdgpu_device pointer
1339 */
1340static int gmc_v9_0_gart_enable(struct amdgpu_device *adev)
1341{
1342 int r;
1343
1344 if (adev->gart.bo == NULL) {
1345 dev_err(adev->dev, "No VRAM object for PCIE GART.\n");
1346 return -EINVAL;
1347 }
1348 r = amdgpu_gart_table_vram_pin(adev);
1349 if (r)
1350 return r;
1351
1352 r = gfxhub_v1_0_gart_enable(adev);
1353 if (r)
1354 return r;
1355
1356 if (adev->asic_type == CHIP_ARCTURUS)
1357 r = mmhub_v9_4_gart_enable(adev);
1358 else
1359 r = mmhub_v1_0_gart_enable(adev);
1360 if (r)
1361 return r;
1362
1363 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
1364 (unsigned)(adev->gmc.gart_size >> 20),
1365 (unsigned long long)amdgpu_bo_gpu_offset(adev->gart.bo));
1366 adev->gart.ready = true;
1367 return 0;
1368}
1369
1370static int gmc_v9_0_hw_init(void *handle)
1371{
1372 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1373 bool value;
1374 int r, i;
1375 u32 tmp;
1376
1377 /* The sequence of these two function calls matters.*/
1378 gmc_v9_0_init_golden_registers(adev);
1379
1380 if (adev->mode_info.num_crtc) {
1381 if (adev->asic_type != CHIP_ARCTURUS) {
1382 /* Lockout access through VGA aperture*/
1383 WREG32_FIELD15(DCE, 0, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1);
1384
1385 /* disable VGA render */
1386 WREG32_FIELD15(DCE, 0, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0);
1387 }
1388 }
1389
1390 amdgpu_device_program_register_sequence(adev,
1391 golden_settings_vega10_hdp,
1392 ARRAY_SIZE(golden_settings_vega10_hdp));
1393
1394 switch (adev->asic_type) {
1395 case CHIP_RAVEN:
1396 /* TODO for renoir */
1397 mmhub_v1_0_update_power_gating(adev, true);
1398 break;
1399 case CHIP_ARCTURUS:
1400 WREG32_FIELD15(HDP, 0, HDP_MMHUB_CNTL, HDP_MMHUB_GCC, 1);
1401 break;
1402 default:
1403 break;
1404 }
1405
1406 WREG32_FIELD15(HDP, 0, HDP_MISC_CNTL, FLUSH_INVALIDATE_CACHE, 1);
1407
1408 tmp = RREG32_SOC15(HDP, 0, mmHDP_HOST_PATH_CNTL);
1409 WREG32_SOC15(HDP, 0, mmHDP_HOST_PATH_CNTL, tmp);
1410
1411 WREG32_SOC15(HDP, 0, mmHDP_NONSURFACE_BASE, (adev->gmc.vram_start >> 8));
1412 WREG32_SOC15(HDP, 0, mmHDP_NONSURFACE_BASE_HI, (adev->gmc.vram_start >> 40));
1413
1414 /* After HDP is initialized, flush HDP.*/
1415 adev->nbio.funcs->hdp_flush(adev, NULL);
1416
1417 if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS)
1418 value = false;
1419 else
1420 value = true;
1421
1422 if (!amdgpu_sriov_vf(adev)) {
1423 gfxhub_v1_0_set_fault_enable_default(adev, value);
1424 if (adev->asic_type == CHIP_ARCTURUS)
1425 mmhub_v9_4_set_fault_enable_default(adev, value);
1426 else
1427 mmhub_v1_0_set_fault_enable_default(adev, value);
1428 }
1429 for (i = 0; i < adev->num_vmhubs; ++i)
1430 gmc_v9_0_flush_gpu_tlb(adev, 0, i, 0);
1431
1432 if (adev->umc.funcs && adev->umc.funcs->init_registers)
1433 adev->umc.funcs->init_registers(adev);
1434
1435 r = gmc_v9_0_gart_enable(adev);
1436
1437 return r;
1438}
1439
1440/**
1441 * gmc_v9_0_save_registers - saves regs
1442 *
1443 * @adev: amdgpu_device pointer
1444 *
1445 * This saves potential register values that should be
1446 * restored upon resume
1447 */
1448static void gmc_v9_0_save_registers(struct amdgpu_device *adev)
1449{
1450 if (adev->asic_type == CHIP_RAVEN)
1451 adev->gmc.sdpif_register = RREG32(mmDCHUBBUB_SDPIF_MMIO_CNTRL_0);
1452}
1453
1454/**
1455 * gmc_v9_0_gart_disable - gart disable
1456 *
1457 * @adev: amdgpu_device pointer
1458 *
1459 * This disables all VM page table.
1460 */
1461static void gmc_v9_0_gart_disable(struct amdgpu_device *adev)
1462{
1463 gfxhub_v1_0_gart_disable(adev);
1464 if (adev->asic_type == CHIP_ARCTURUS)
1465 mmhub_v9_4_gart_disable(adev);
1466 else
1467 mmhub_v1_0_gart_disable(adev);
1468 amdgpu_gart_table_vram_unpin(adev);
1469}
1470
1471static int gmc_v9_0_hw_fini(void *handle)
1472{
1473 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1474
1475 if (amdgpu_sriov_vf(adev)) {
1476 /* full access mode, so don't touch any GMC register */
1477 DRM_DEBUG("For SRIOV client, shouldn't do anything.\n");
1478 return 0;
1479 }
1480
1481 amdgpu_irq_put(adev, &adev->gmc.ecc_irq, 0);
1482 amdgpu_irq_put(adev, &adev->gmc.vm_fault, 0);
1483 gmc_v9_0_gart_disable(adev);
1484
1485 return 0;
1486}
1487
1488static int gmc_v9_0_suspend(void *handle)
1489{
1490 int r;
1491 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1492
1493 r = gmc_v9_0_hw_fini(adev);
1494 if (r)
1495 return r;
1496
1497 gmc_v9_0_save_registers(adev);
1498
1499 return 0;
1500}
1501
1502static int gmc_v9_0_resume(void *handle)
1503{
1504 int r;
1505 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1506
1507 gmc_v9_0_restore_registers(adev);
1508 r = gmc_v9_0_hw_init(adev);
1509 if (r)
1510 return r;
1511
1512 amdgpu_vmid_reset_all(adev);
1513
1514 return 0;
1515}
1516
1517static bool gmc_v9_0_is_idle(void *handle)
1518{
1519 /* MC is always ready in GMC v9.*/
1520 return true;
1521}
1522
1523static int gmc_v9_0_wait_for_idle(void *handle)
1524{
1525 /* There is no need to wait for MC idle in GMC v9.*/
1526 return 0;
1527}
1528
1529static int gmc_v9_0_soft_reset(void *handle)
1530{
1531 /* XXX for emulation.*/
1532 return 0;
1533}
1534
1535static int gmc_v9_0_set_clockgating_state(void *handle,
1536 enum amd_clockgating_state state)
1537{
1538 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1539
1540 if (adev->asic_type == CHIP_ARCTURUS)
1541 mmhub_v9_4_set_clockgating(adev, state);
1542 else
1543 mmhub_v1_0_set_clockgating(adev, state);
1544
1545 athub_v1_0_set_clockgating(adev, state);
1546
1547 return 0;
1548}
1549
1550static void gmc_v9_0_get_clockgating_state(void *handle, u32 *flags)
1551{
1552 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1553
1554 if (adev->asic_type == CHIP_ARCTURUS)
1555 mmhub_v9_4_get_clockgating(adev, flags);
1556 else
1557 mmhub_v1_0_get_clockgating(adev, flags);
1558
1559 athub_v1_0_get_clockgating(adev, flags);
1560}
1561
1562static int gmc_v9_0_set_powergating_state(void *handle,
1563 enum amd_powergating_state state)
1564{
1565 return 0;
1566}
1567
1568const struct amd_ip_funcs gmc_v9_0_ip_funcs = {
1569 .name = "gmc_v9_0",
1570 .early_init = gmc_v9_0_early_init,
1571 .late_init = gmc_v9_0_late_init,
1572 .sw_init = gmc_v9_0_sw_init,
1573 .sw_fini = gmc_v9_0_sw_fini,
1574 .hw_init = gmc_v9_0_hw_init,
1575 .hw_fini = gmc_v9_0_hw_fini,
1576 .suspend = gmc_v9_0_suspend,
1577 .resume = gmc_v9_0_resume,
1578 .is_idle = gmc_v9_0_is_idle,
1579 .wait_for_idle = gmc_v9_0_wait_for_idle,
1580 .soft_reset = gmc_v9_0_soft_reset,
1581 .set_clockgating_state = gmc_v9_0_set_clockgating_state,
1582 .set_powergating_state = gmc_v9_0_set_powergating_state,
1583 .get_clockgating_state = gmc_v9_0_get_clockgating_state,
1584};
1585
1586const struct amdgpu_ip_block_version gmc_v9_0_ip_block =
1587{
1588 .type = AMD_IP_BLOCK_TYPE_GMC,
1589 .major = 9,
1590 .minor = 0,
1591 .rev = 0,
1592 .funcs = &gmc_v9_0_ip_funcs,
1593};
1/*
2 * Copyright 2016 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24#include <linux/firmware.h>
25#include <linux/pci.h>
26
27#include <drm/drm_cache.h>
28
29#include "amdgpu.h"
30#include "gmc_v9_0.h"
31#include "amdgpu_atomfirmware.h"
32#include "amdgpu_gem.h"
33
34#include "gc/gc_9_0_sh_mask.h"
35#include "dce/dce_12_0_offset.h"
36#include "dce/dce_12_0_sh_mask.h"
37#include "vega10_enum.h"
38#include "mmhub/mmhub_1_0_offset.h"
39#include "athub/athub_1_0_sh_mask.h"
40#include "athub/athub_1_0_offset.h"
41#include "oss/osssys_4_0_offset.h"
42
43#include "soc15.h"
44#include "soc15d.h"
45#include "soc15_common.h"
46#include "umc/umc_6_0_sh_mask.h"
47
48#include "gfxhub_v1_0.h"
49#include "mmhub_v1_0.h"
50#include "athub_v1_0.h"
51#include "gfxhub_v1_1.h"
52#include "gfxhub_v1_2.h"
53#include "mmhub_v9_4.h"
54#include "mmhub_v1_7.h"
55#include "mmhub_v1_8.h"
56#include "umc_v6_1.h"
57#include "umc_v6_0.h"
58#include "umc_v6_7.h"
59#include "umc_v12_0.h"
60#include "hdp_v4_0.h"
61#include "mca_v3_0.h"
62
63#include "ivsrcid/vmc/irqsrcs_vmc_1_0.h"
64
65#include "amdgpu_ras.h"
66#include "amdgpu_xgmi.h"
67
68/* add these here since we already include dce12 headers and these are for DCN */
69#define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION 0x055d
70#define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX 2
71#define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH__SHIFT 0x0
72#define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT__SHIFT 0x10
73#define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH_MASK 0x00003FFFL
74#define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT_MASK 0x3FFF0000L
75#define mmDCHUBBUB_SDPIF_MMIO_CNTRL_0 0x049d
76#define mmDCHUBBUB_SDPIF_MMIO_CNTRL_0_BASE_IDX 2
77
78#define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_DCN2 0x05ea
79#define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_DCN2_BASE_IDX 2
80
81#define MAX_MEM_RANGES 8
82
83static const char * const gfxhub_client_ids[] = {
84 "CB",
85 "DB",
86 "IA",
87 "WD",
88 "CPF",
89 "CPC",
90 "CPG",
91 "RLC",
92 "TCP",
93 "SQC (inst)",
94 "SQC (data)",
95 "SQG",
96 "PA",
97};
98
99static const char *mmhub_client_ids_raven[][2] = {
100 [0][0] = "MP1",
101 [1][0] = "MP0",
102 [2][0] = "VCN",
103 [3][0] = "VCNU",
104 [4][0] = "HDP",
105 [5][0] = "DCE",
106 [13][0] = "UTCL2",
107 [19][0] = "TLS",
108 [26][0] = "OSS",
109 [27][0] = "SDMA0",
110 [0][1] = "MP1",
111 [1][1] = "MP0",
112 [2][1] = "VCN",
113 [3][1] = "VCNU",
114 [4][1] = "HDP",
115 [5][1] = "XDP",
116 [6][1] = "DBGU0",
117 [7][1] = "DCE",
118 [8][1] = "DCEDWB0",
119 [9][1] = "DCEDWB1",
120 [26][1] = "OSS",
121 [27][1] = "SDMA0",
122};
123
124static const char *mmhub_client_ids_renoir[][2] = {
125 [0][0] = "MP1",
126 [1][0] = "MP0",
127 [2][0] = "HDP",
128 [4][0] = "DCEDMC",
129 [5][0] = "DCEVGA",
130 [13][0] = "UTCL2",
131 [19][0] = "TLS",
132 [26][0] = "OSS",
133 [27][0] = "SDMA0",
134 [28][0] = "VCN",
135 [29][0] = "VCNU",
136 [30][0] = "JPEG",
137 [0][1] = "MP1",
138 [1][1] = "MP0",
139 [2][1] = "HDP",
140 [3][1] = "XDP",
141 [6][1] = "DBGU0",
142 [7][1] = "DCEDMC",
143 [8][1] = "DCEVGA",
144 [9][1] = "DCEDWB",
145 [26][1] = "OSS",
146 [27][1] = "SDMA0",
147 [28][1] = "VCN",
148 [29][1] = "VCNU",
149 [30][1] = "JPEG",
150};
151
152static const char *mmhub_client_ids_vega10[][2] = {
153 [0][0] = "MP0",
154 [1][0] = "UVD",
155 [2][0] = "UVDU",
156 [3][0] = "HDP",
157 [13][0] = "UTCL2",
158 [14][0] = "OSS",
159 [15][0] = "SDMA1",
160 [32+0][0] = "VCE0",
161 [32+1][0] = "VCE0U",
162 [32+2][0] = "XDMA",
163 [32+3][0] = "DCE",
164 [32+4][0] = "MP1",
165 [32+14][0] = "SDMA0",
166 [0][1] = "MP0",
167 [1][1] = "UVD",
168 [2][1] = "UVDU",
169 [3][1] = "DBGU0",
170 [4][1] = "HDP",
171 [5][1] = "XDP",
172 [14][1] = "OSS",
173 [15][1] = "SDMA0",
174 [32+0][1] = "VCE0",
175 [32+1][1] = "VCE0U",
176 [32+2][1] = "XDMA",
177 [32+3][1] = "DCE",
178 [32+4][1] = "DCEDWB",
179 [32+5][1] = "MP1",
180 [32+6][1] = "DBGU1",
181 [32+14][1] = "SDMA1",
182};
183
184static const char *mmhub_client_ids_vega12[][2] = {
185 [0][0] = "MP0",
186 [1][0] = "VCE0",
187 [2][0] = "VCE0U",
188 [3][0] = "HDP",
189 [13][0] = "UTCL2",
190 [14][0] = "OSS",
191 [15][0] = "SDMA1",
192 [32+0][0] = "DCE",
193 [32+1][0] = "XDMA",
194 [32+2][0] = "UVD",
195 [32+3][0] = "UVDU",
196 [32+4][0] = "MP1",
197 [32+15][0] = "SDMA0",
198 [0][1] = "MP0",
199 [1][1] = "VCE0",
200 [2][1] = "VCE0U",
201 [3][1] = "DBGU0",
202 [4][1] = "HDP",
203 [5][1] = "XDP",
204 [14][1] = "OSS",
205 [15][1] = "SDMA0",
206 [32+0][1] = "DCE",
207 [32+1][1] = "DCEDWB",
208 [32+2][1] = "XDMA",
209 [32+3][1] = "UVD",
210 [32+4][1] = "UVDU",
211 [32+5][1] = "MP1",
212 [32+6][1] = "DBGU1",
213 [32+15][1] = "SDMA1",
214};
215
216static const char *mmhub_client_ids_vega20[][2] = {
217 [0][0] = "XDMA",
218 [1][0] = "DCE",
219 [2][0] = "VCE0",
220 [3][0] = "VCE0U",
221 [4][0] = "UVD",
222 [5][0] = "UVD1U",
223 [13][0] = "OSS",
224 [14][0] = "HDP",
225 [15][0] = "SDMA0",
226 [32+0][0] = "UVD",
227 [32+1][0] = "UVDU",
228 [32+2][0] = "MP1",
229 [32+3][0] = "MP0",
230 [32+12][0] = "UTCL2",
231 [32+14][0] = "SDMA1",
232 [0][1] = "XDMA",
233 [1][1] = "DCE",
234 [2][1] = "DCEDWB",
235 [3][1] = "VCE0",
236 [4][1] = "VCE0U",
237 [5][1] = "UVD1",
238 [6][1] = "UVD1U",
239 [7][1] = "DBGU0",
240 [8][1] = "XDP",
241 [13][1] = "OSS",
242 [14][1] = "HDP",
243 [15][1] = "SDMA0",
244 [32+0][1] = "UVD",
245 [32+1][1] = "UVDU",
246 [32+2][1] = "DBGU1",
247 [32+3][1] = "MP1",
248 [32+4][1] = "MP0",
249 [32+14][1] = "SDMA1",
250};
251
252static const char *mmhub_client_ids_arcturus[][2] = {
253 [0][0] = "DBGU1",
254 [1][0] = "XDP",
255 [2][0] = "MP1",
256 [14][0] = "HDP",
257 [171][0] = "JPEG",
258 [172][0] = "VCN",
259 [173][0] = "VCNU",
260 [203][0] = "JPEG1",
261 [204][0] = "VCN1",
262 [205][0] = "VCN1U",
263 [256][0] = "SDMA0",
264 [257][0] = "SDMA1",
265 [258][0] = "SDMA2",
266 [259][0] = "SDMA3",
267 [260][0] = "SDMA4",
268 [261][0] = "SDMA5",
269 [262][0] = "SDMA6",
270 [263][0] = "SDMA7",
271 [384][0] = "OSS",
272 [0][1] = "DBGU1",
273 [1][1] = "XDP",
274 [2][1] = "MP1",
275 [14][1] = "HDP",
276 [171][1] = "JPEG",
277 [172][1] = "VCN",
278 [173][1] = "VCNU",
279 [203][1] = "JPEG1",
280 [204][1] = "VCN1",
281 [205][1] = "VCN1U",
282 [256][1] = "SDMA0",
283 [257][1] = "SDMA1",
284 [258][1] = "SDMA2",
285 [259][1] = "SDMA3",
286 [260][1] = "SDMA4",
287 [261][1] = "SDMA5",
288 [262][1] = "SDMA6",
289 [263][1] = "SDMA7",
290 [384][1] = "OSS",
291};
292
293static const char *mmhub_client_ids_aldebaran[][2] = {
294 [2][0] = "MP1",
295 [3][0] = "MP0",
296 [32+1][0] = "DBGU_IO0",
297 [32+2][0] = "DBGU_IO2",
298 [32+4][0] = "MPIO",
299 [96+11][0] = "JPEG0",
300 [96+12][0] = "VCN0",
301 [96+13][0] = "VCNU0",
302 [128+11][0] = "JPEG1",
303 [128+12][0] = "VCN1",
304 [128+13][0] = "VCNU1",
305 [160+1][0] = "XDP",
306 [160+14][0] = "HDP",
307 [256+0][0] = "SDMA0",
308 [256+1][0] = "SDMA1",
309 [256+2][0] = "SDMA2",
310 [256+3][0] = "SDMA3",
311 [256+4][0] = "SDMA4",
312 [384+0][0] = "OSS",
313 [2][1] = "MP1",
314 [3][1] = "MP0",
315 [32+1][1] = "DBGU_IO0",
316 [32+2][1] = "DBGU_IO2",
317 [32+4][1] = "MPIO",
318 [96+11][1] = "JPEG0",
319 [96+12][1] = "VCN0",
320 [96+13][1] = "VCNU0",
321 [128+11][1] = "JPEG1",
322 [128+12][1] = "VCN1",
323 [128+13][1] = "VCNU1",
324 [160+1][1] = "XDP",
325 [160+14][1] = "HDP",
326 [256+0][1] = "SDMA0",
327 [256+1][1] = "SDMA1",
328 [256+2][1] = "SDMA2",
329 [256+3][1] = "SDMA3",
330 [256+4][1] = "SDMA4",
331 [384+0][1] = "OSS",
332};
333
334static const struct soc15_reg_golden golden_settings_mmhub_1_0_0[] = {
335 SOC15_REG_GOLDEN_VALUE(MMHUB, 0, mmDAGB1_WRCLI2, 0x00000007, 0xfe5fe0fa),
336 SOC15_REG_GOLDEN_VALUE(MMHUB, 0, mmMMEA1_DRAM_WR_CLI2GRP_MAP0, 0x00000030, 0x55555565)
337};
338
339static const struct soc15_reg_golden golden_settings_athub_1_0_0[] = {
340 SOC15_REG_GOLDEN_VALUE(ATHUB, 0, mmRPB_ARB_CNTL, 0x0000ff00, 0x00000800),
341 SOC15_REG_GOLDEN_VALUE(ATHUB, 0, mmRPB_ARB_CNTL2, 0x00ff00ff, 0x00080008)
342};
343
344static const uint32_t ecc_umc_mcumc_ctrl_addrs[] = {
345 (0x000143c0 + 0x00000000),
346 (0x000143c0 + 0x00000800),
347 (0x000143c0 + 0x00001000),
348 (0x000143c0 + 0x00001800),
349 (0x000543c0 + 0x00000000),
350 (0x000543c0 + 0x00000800),
351 (0x000543c0 + 0x00001000),
352 (0x000543c0 + 0x00001800),
353 (0x000943c0 + 0x00000000),
354 (0x000943c0 + 0x00000800),
355 (0x000943c0 + 0x00001000),
356 (0x000943c0 + 0x00001800),
357 (0x000d43c0 + 0x00000000),
358 (0x000d43c0 + 0x00000800),
359 (0x000d43c0 + 0x00001000),
360 (0x000d43c0 + 0x00001800),
361 (0x001143c0 + 0x00000000),
362 (0x001143c0 + 0x00000800),
363 (0x001143c0 + 0x00001000),
364 (0x001143c0 + 0x00001800),
365 (0x001543c0 + 0x00000000),
366 (0x001543c0 + 0x00000800),
367 (0x001543c0 + 0x00001000),
368 (0x001543c0 + 0x00001800),
369 (0x001943c0 + 0x00000000),
370 (0x001943c0 + 0x00000800),
371 (0x001943c0 + 0x00001000),
372 (0x001943c0 + 0x00001800),
373 (0x001d43c0 + 0x00000000),
374 (0x001d43c0 + 0x00000800),
375 (0x001d43c0 + 0x00001000),
376 (0x001d43c0 + 0x00001800),
377};
378
379static const uint32_t ecc_umc_mcumc_ctrl_mask_addrs[] = {
380 (0x000143e0 + 0x00000000),
381 (0x000143e0 + 0x00000800),
382 (0x000143e0 + 0x00001000),
383 (0x000143e0 + 0x00001800),
384 (0x000543e0 + 0x00000000),
385 (0x000543e0 + 0x00000800),
386 (0x000543e0 + 0x00001000),
387 (0x000543e0 + 0x00001800),
388 (0x000943e0 + 0x00000000),
389 (0x000943e0 + 0x00000800),
390 (0x000943e0 + 0x00001000),
391 (0x000943e0 + 0x00001800),
392 (0x000d43e0 + 0x00000000),
393 (0x000d43e0 + 0x00000800),
394 (0x000d43e0 + 0x00001000),
395 (0x000d43e0 + 0x00001800),
396 (0x001143e0 + 0x00000000),
397 (0x001143e0 + 0x00000800),
398 (0x001143e0 + 0x00001000),
399 (0x001143e0 + 0x00001800),
400 (0x001543e0 + 0x00000000),
401 (0x001543e0 + 0x00000800),
402 (0x001543e0 + 0x00001000),
403 (0x001543e0 + 0x00001800),
404 (0x001943e0 + 0x00000000),
405 (0x001943e0 + 0x00000800),
406 (0x001943e0 + 0x00001000),
407 (0x001943e0 + 0x00001800),
408 (0x001d43e0 + 0x00000000),
409 (0x001d43e0 + 0x00000800),
410 (0x001d43e0 + 0x00001000),
411 (0x001d43e0 + 0x00001800),
412};
413
414static int gmc_v9_0_ecc_interrupt_state(struct amdgpu_device *adev,
415 struct amdgpu_irq_src *src,
416 unsigned int type,
417 enum amdgpu_interrupt_state state)
418{
419 u32 bits, i, tmp, reg;
420
421 /* Devices newer then VEGA10/12 shall have these programming
422 * sequences performed by PSP BL
423 */
424 if (adev->asic_type >= CHIP_VEGA20)
425 return 0;
426
427 bits = 0x7f;
428
429 switch (state) {
430 case AMDGPU_IRQ_STATE_DISABLE:
431 for (i = 0; i < ARRAY_SIZE(ecc_umc_mcumc_ctrl_addrs); i++) {
432 reg = ecc_umc_mcumc_ctrl_addrs[i];
433 tmp = RREG32(reg);
434 tmp &= ~bits;
435 WREG32(reg, tmp);
436 }
437 for (i = 0; i < ARRAY_SIZE(ecc_umc_mcumc_ctrl_mask_addrs); i++) {
438 reg = ecc_umc_mcumc_ctrl_mask_addrs[i];
439 tmp = RREG32(reg);
440 tmp &= ~bits;
441 WREG32(reg, tmp);
442 }
443 break;
444 case AMDGPU_IRQ_STATE_ENABLE:
445 for (i = 0; i < ARRAY_SIZE(ecc_umc_mcumc_ctrl_addrs); i++) {
446 reg = ecc_umc_mcumc_ctrl_addrs[i];
447 tmp = RREG32(reg);
448 tmp |= bits;
449 WREG32(reg, tmp);
450 }
451 for (i = 0; i < ARRAY_SIZE(ecc_umc_mcumc_ctrl_mask_addrs); i++) {
452 reg = ecc_umc_mcumc_ctrl_mask_addrs[i];
453 tmp = RREG32(reg);
454 tmp |= bits;
455 WREG32(reg, tmp);
456 }
457 break;
458 default:
459 break;
460 }
461
462 return 0;
463}
464
465static int gmc_v9_0_vm_fault_interrupt_state(struct amdgpu_device *adev,
466 struct amdgpu_irq_src *src,
467 unsigned int type,
468 enum amdgpu_interrupt_state state)
469{
470 struct amdgpu_vmhub *hub;
471 u32 tmp, reg, bits, i, j;
472
473 bits = VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
474 VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
475 VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
476 VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
477 VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
478 VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
479 VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK;
480
481 switch (state) {
482 case AMDGPU_IRQ_STATE_DISABLE:
483 for_each_set_bit(j, adev->vmhubs_mask, AMDGPU_MAX_VMHUBS) {
484 hub = &adev->vmhub[j];
485 for (i = 0; i < 16; i++) {
486 reg = hub->vm_context0_cntl + i;
487
488 /* This works because this interrupt is only
489 * enabled at init/resume and disabled in
490 * fini/suspend, so the overall state doesn't
491 * change over the course of suspend/resume.
492 */
493 if (adev->in_s0ix && (j == AMDGPU_GFXHUB(0)))
494 continue;
495
496 if (j >= AMDGPU_MMHUB0(0))
497 tmp = RREG32_SOC15_IP(MMHUB, reg);
498 else
499 tmp = RREG32_SOC15_IP(GC, reg);
500
501 tmp &= ~bits;
502
503 if (j >= AMDGPU_MMHUB0(0))
504 WREG32_SOC15_IP(MMHUB, reg, tmp);
505 else
506 WREG32_SOC15_IP(GC, reg, tmp);
507 }
508 }
509 break;
510 case AMDGPU_IRQ_STATE_ENABLE:
511 for_each_set_bit(j, adev->vmhubs_mask, AMDGPU_MAX_VMHUBS) {
512 hub = &adev->vmhub[j];
513 for (i = 0; i < 16; i++) {
514 reg = hub->vm_context0_cntl + i;
515
516 /* This works because this interrupt is only
517 * enabled at init/resume and disabled in
518 * fini/suspend, so the overall state doesn't
519 * change over the course of suspend/resume.
520 */
521 if (adev->in_s0ix && (j == AMDGPU_GFXHUB(0)))
522 continue;
523
524 if (j >= AMDGPU_MMHUB0(0))
525 tmp = RREG32_SOC15_IP(MMHUB, reg);
526 else
527 tmp = RREG32_SOC15_IP(GC, reg);
528
529 tmp |= bits;
530
531 if (j >= AMDGPU_MMHUB0(0))
532 WREG32_SOC15_IP(MMHUB, reg, tmp);
533 else
534 WREG32_SOC15_IP(GC, reg, tmp);
535 }
536 }
537 break;
538 default:
539 break;
540 }
541
542 return 0;
543}
544
545static int gmc_v9_0_process_interrupt(struct amdgpu_device *adev,
546 struct amdgpu_irq_src *source,
547 struct amdgpu_iv_entry *entry)
548{
549 bool retry_fault = !!(entry->src_data[1] & 0x80);
550 bool write_fault = !!(entry->src_data[1] & 0x20);
551 uint32_t status = 0, cid = 0, rw = 0;
552 struct amdgpu_task_info task_info;
553 struct amdgpu_vmhub *hub;
554 const char *mmhub_cid;
555 const char *hub_name;
556 unsigned int vmhub;
557 u64 addr;
558 uint32_t cam_index = 0;
559 int ret, xcc_id = 0;
560 uint32_t node_id;
561
562 node_id = entry->node_id;
563
564 addr = (u64)entry->src_data[0] << 12;
565 addr |= ((u64)entry->src_data[1] & 0xf) << 44;
566
567 if (entry->client_id == SOC15_IH_CLIENTID_VMC) {
568 hub_name = "mmhub0";
569 vmhub = AMDGPU_MMHUB0(node_id / 4);
570 } else if (entry->client_id == SOC15_IH_CLIENTID_VMC1) {
571 hub_name = "mmhub1";
572 vmhub = AMDGPU_MMHUB1(0);
573 } else {
574 hub_name = "gfxhub0";
575 if (adev->gfx.funcs->ih_node_to_logical_xcc) {
576 xcc_id = adev->gfx.funcs->ih_node_to_logical_xcc(adev,
577 node_id);
578 if (xcc_id < 0)
579 xcc_id = 0;
580 }
581 vmhub = xcc_id;
582 }
583 hub = &adev->vmhub[vmhub];
584
585 if (retry_fault) {
586 if (adev->irq.retry_cam_enabled) {
587 /* Delegate it to a different ring if the hardware hasn't
588 * already done it.
589 */
590 if (entry->ih == &adev->irq.ih) {
591 amdgpu_irq_delegate(adev, entry, 8);
592 return 1;
593 }
594
595 cam_index = entry->src_data[2] & 0x3ff;
596
597 ret = amdgpu_vm_handle_fault(adev, entry->pasid, entry->vmid, node_id,
598 addr, write_fault);
599 WDOORBELL32(adev->irq.retry_cam_doorbell_index, cam_index);
600 if (ret)
601 return 1;
602 } else {
603 /* Process it onyl if it's the first fault for this address */
604 if (entry->ih != &adev->irq.ih_soft &&
605 amdgpu_gmc_filter_faults(adev, entry->ih, addr, entry->pasid,
606 entry->timestamp))
607 return 1;
608
609 /* Delegate it to a different ring if the hardware hasn't
610 * already done it.
611 */
612 if (entry->ih == &adev->irq.ih) {
613 amdgpu_irq_delegate(adev, entry, 8);
614 return 1;
615 }
616
617 /* Try to handle the recoverable page faults by filling page
618 * tables
619 */
620 if (amdgpu_vm_handle_fault(adev, entry->pasid, entry->vmid, node_id,
621 addr, write_fault))
622 return 1;
623 }
624 }
625
626 if (!printk_ratelimit())
627 return 0;
628
629 memset(&task_info, 0, sizeof(struct amdgpu_task_info));
630 amdgpu_vm_get_task_info(adev, entry->pasid, &task_info);
631
632 dev_err(adev->dev,
633 "[%s] %s page fault (src_id:%u ring:%u vmid:%u pasid:%u, for process %s pid %d thread %s pid %d)\n",
634 hub_name, retry_fault ? "retry" : "no-retry",
635 entry->src_id, entry->ring_id, entry->vmid,
636 entry->pasid, task_info.process_name, task_info.tgid,
637 task_info.task_name, task_info.pid);
638 dev_err(adev->dev, " in page starting at address 0x%016llx from IH client 0x%x (%s)\n",
639 addr, entry->client_id,
640 soc15_ih_clientid_name[entry->client_id]);
641
642 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 3))
643 dev_err(adev->dev, " cookie node_id %d fault from die %s%d%s\n",
644 node_id, node_id % 4 == 3 ? "RSV" : "AID", node_id / 4,
645 node_id % 4 == 1 ? ".XCD0" : node_id % 4 == 2 ? ".XCD1" : "");
646
647 if (amdgpu_sriov_vf(adev))
648 return 0;
649
650 /*
651 * Issue a dummy read to wait for the status register to
652 * be updated to avoid reading an incorrect value due to
653 * the new fast GRBM interface.
654 */
655 if ((entry->vmid_src == AMDGPU_GFXHUB(0)) &&
656 (amdgpu_ip_version(adev, GC_HWIP, 0) < IP_VERSION(9, 4, 2)))
657 RREG32(hub->vm_l2_pro_fault_status);
658
659 status = RREG32(hub->vm_l2_pro_fault_status);
660 cid = REG_GET_FIELD(status, VM_L2_PROTECTION_FAULT_STATUS, CID);
661 rw = REG_GET_FIELD(status, VM_L2_PROTECTION_FAULT_STATUS, RW);
662 WREG32_P(hub->vm_l2_pro_fault_cntl, 1, ~1);
663
664 amdgpu_vm_update_fault_cache(adev, entry->pasid, addr, status, vmhub);
665
666 dev_err(adev->dev,
667 "VM_L2_PROTECTION_FAULT_STATUS:0x%08X\n",
668 status);
669 if (entry->vmid_src == AMDGPU_GFXHUB(0)) {
670 dev_err(adev->dev, "\t Faulty UTCL2 client ID: %s (0x%x)\n",
671 cid >= ARRAY_SIZE(gfxhub_client_ids) ? "unknown" :
672 gfxhub_client_ids[cid],
673 cid);
674 } else {
675 switch (amdgpu_ip_version(adev, MMHUB_HWIP, 0)) {
676 case IP_VERSION(9, 0, 0):
677 mmhub_cid = mmhub_client_ids_vega10[cid][rw];
678 break;
679 case IP_VERSION(9, 3, 0):
680 mmhub_cid = mmhub_client_ids_vega12[cid][rw];
681 break;
682 case IP_VERSION(9, 4, 0):
683 mmhub_cid = mmhub_client_ids_vega20[cid][rw];
684 break;
685 case IP_VERSION(9, 4, 1):
686 mmhub_cid = mmhub_client_ids_arcturus[cid][rw];
687 break;
688 case IP_VERSION(9, 1, 0):
689 case IP_VERSION(9, 2, 0):
690 mmhub_cid = mmhub_client_ids_raven[cid][rw];
691 break;
692 case IP_VERSION(1, 5, 0):
693 case IP_VERSION(2, 4, 0):
694 mmhub_cid = mmhub_client_ids_renoir[cid][rw];
695 break;
696 case IP_VERSION(1, 8, 0):
697 case IP_VERSION(9, 4, 2):
698 mmhub_cid = mmhub_client_ids_aldebaran[cid][rw];
699 break;
700 default:
701 mmhub_cid = NULL;
702 break;
703 }
704 dev_err(adev->dev, "\t Faulty UTCL2 client ID: %s (0x%x)\n",
705 mmhub_cid ? mmhub_cid : "unknown", cid);
706 }
707 dev_err(adev->dev, "\t MORE_FAULTS: 0x%lx\n",
708 REG_GET_FIELD(status,
709 VM_L2_PROTECTION_FAULT_STATUS, MORE_FAULTS));
710 dev_err(adev->dev, "\t WALKER_ERROR: 0x%lx\n",
711 REG_GET_FIELD(status,
712 VM_L2_PROTECTION_FAULT_STATUS, WALKER_ERROR));
713 dev_err(adev->dev, "\t PERMISSION_FAULTS: 0x%lx\n",
714 REG_GET_FIELD(status,
715 VM_L2_PROTECTION_FAULT_STATUS, PERMISSION_FAULTS));
716 dev_err(adev->dev, "\t MAPPING_ERROR: 0x%lx\n",
717 REG_GET_FIELD(status,
718 VM_L2_PROTECTION_FAULT_STATUS, MAPPING_ERROR));
719 dev_err(adev->dev, "\t RW: 0x%x\n", rw);
720 return 0;
721}
722
723static const struct amdgpu_irq_src_funcs gmc_v9_0_irq_funcs = {
724 .set = gmc_v9_0_vm_fault_interrupt_state,
725 .process = gmc_v9_0_process_interrupt,
726};
727
728
729static const struct amdgpu_irq_src_funcs gmc_v9_0_ecc_funcs = {
730 .set = gmc_v9_0_ecc_interrupt_state,
731 .process = amdgpu_umc_process_ecc_irq,
732};
733
734static void gmc_v9_0_set_irq_funcs(struct amdgpu_device *adev)
735{
736 adev->gmc.vm_fault.num_types = 1;
737 adev->gmc.vm_fault.funcs = &gmc_v9_0_irq_funcs;
738
739 if (!amdgpu_sriov_vf(adev) &&
740 !adev->gmc.xgmi.connected_to_cpu &&
741 !adev->gmc.is_app_apu) {
742 adev->gmc.ecc_irq.num_types = 1;
743 adev->gmc.ecc_irq.funcs = &gmc_v9_0_ecc_funcs;
744 }
745}
746
747static uint32_t gmc_v9_0_get_invalidate_req(unsigned int vmid,
748 uint32_t flush_type)
749{
750 u32 req = 0;
751
752 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ,
753 PER_VMID_INVALIDATE_REQ, 1 << vmid);
754 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, FLUSH_TYPE, flush_type);
755 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PTES, 1);
756 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE0, 1);
757 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE1, 1);
758 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE2, 1);
759 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L1_PTES, 1);
760 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ,
761 CLEAR_PROTECTION_FAULT_STATUS_ADDR, 0);
762
763 return req;
764}
765
766/**
767 * gmc_v9_0_use_invalidate_semaphore - judge whether to use semaphore
768 *
769 * @adev: amdgpu_device pointer
770 * @vmhub: vmhub type
771 *
772 */
773static bool gmc_v9_0_use_invalidate_semaphore(struct amdgpu_device *adev,
774 uint32_t vmhub)
775{
776 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 2) ||
777 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 3))
778 return false;
779
780 return ((vmhub == AMDGPU_MMHUB0(0) ||
781 vmhub == AMDGPU_MMHUB1(0)) &&
782 (!amdgpu_sriov_vf(adev)) &&
783 (!(!(adev->apu_flags & AMD_APU_IS_RAVEN2) &&
784 (adev->apu_flags & AMD_APU_IS_PICASSO))));
785}
786
787static bool gmc_v9_0_get_atc_vmid_pasid_mapping_info(struct amdgpu_device *adev,
788 uint8_t vmid, uint16_t *p_pasid)
789{
790 uint32_t value;
791
792 value = RREG32(SOC15_REG_OFFSET(ATHUB, 0, mmATC_VMID0_PASID_MAPPING)
793 + vmid);
794 *p_pasid = value & ATC_VMID0_PASID_MAPPING__PASID_MASK;
795
796 return !!(value & ATC_VMID0_PASID_MAPPING__VALID_MASK);
797}
798
799/*
800 * GART
801 * VMID 0 is the physical GPU addresses as used by the kernel.
802 * VMIDs 1-15 are used for userspace clients and are handled
803 * by the amdgpu vm/hsa code.
804 */
805
806/**
807 * gmc_v9_0_flush_gpu_tlb - tlb flush with certain type
808 *
809 * @adev: amdgpu_device pointer
810 * @vmid: vm instance to flush
811 * @vmhub: which hub to flush
812 * @flush_type: the flush type
813 *
814 * Flush the TLB for the requested page table using certain type.
815 */
816static void gmc_v9_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid,
817 uint32_t vmhub, uint32_t flush_type)
818{
819 bool use_semaphore = gmc_v9_0_use_invalidate_semaphore(adev, vmhub);
820 u32 j, inv_req, tmp, sem, req, ack, inst;
821 const unsigned int eng = 17;
822 struct amdgpu_vmhub *hub;
823
824 BUG_ON(vmhub >= AMDGPU_MAX_VMHUBS);
825
826 hub = &adev->vmhub[vmhub];
827 inv_req = gmc_v9_0_get_invalidate_req(vmid, flush_type);
828 sem = hub->vm_inv_eng0_sem + hub->eng_distance * eng;
829 req = hub->vm_inv_eng0_req + hub->eng_distance * eng;
830 ack = hub->vm_inv_eng0_ack + hub->eng_distance * eng;
831
832 /* This is necessary for a HW workaround under SRIOV as well
833 * as GFXOFF under bare metal
834 */
835 if (vmhub >= AMDGPU_MMHUB0(0))
836 inst = GET_INST(GC, 0);
837 else
838 inst = vmhub;
839 if (adev->gfx.kiq[inst].ring.sched.ready &&
840 (amdgpu_sriov_runtime(adev) || !amdgpu_sriov_vf(adev))) {
841 uint32_t req = hub->vm_inv_eng0_req + hub->eng_distance * eng;
842 uint32_t ack = hub->vm_inv_eng0_ack + hub->eng_distance * eng;
843
844 amdgpu_virt_kiq_reg_write_reg_wait(adev, req, ack, inv_req,
845 1 << vmid, inst);
846 return;
847 }
848
849 spin_lock(&adev->gmc.invalidate_lock);
850
851 /*
852 * It may lose gpuvm invalidate acknowldege state across power-gating
853 * off cycle, add semaphore acquire before invalidation and semaphore
854 * release after invalidation to avoid entering power gated state
855 * to WA the Issue
856 */
857
858 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */
859 if (use_semaphore) {
860 for (j = 0; j < adev->usec_timeout; j++) {
861 /* a read return value of 1 means semaphore acquire */
862 if (vmhub >= AMDGPU_MMHUB0(0))
863 tmp = RREG32_SOC15_IP_NO_KIQ(MMHUB, sem, inst);
864 else
865 tmp = RREG32_SOC15_IP_NO_KIQ(GC, sem, inst);
866 if (tmp & 0x1)
867 break;
868 udelay(1);
869 }
870
871 if (j >= adev->usec_timeout)
872 DRM_ERROR("Timeout waiting for sem acquire in VM flush!\n");
873 }
874
875 if (vmhub >= AMDGPU_MMHUB0(0))
876 WREG32_SOC15_IP_NO_KIQ(MMHUB, req, inv_req, inst);
877 else
878 WREG32_SOC15_IP_NO_KIQ(GC, req, inv_req, inst);
879
880 /*
881 * Issue a dummy read to wait for the ACK register to
882 * be cleared to avoid a false ACK due to the new fast
883 * GRBM interface.
884 */
885 if ((vmhub == AMDGPU_GFXHUB(0)) &&
886 (amdgpu_ip_version(adev, GC_HWIP, 0) < IP_VERSION(9, 4, 2)))
887 RREG32_NO_KIQ(req);
888
889 for (j = 0; j < adev->usec_timeout; j++) {
890 if (vmhub >= AMDGPU_MMHUB0(0))
891 tmp = RREG32_SOC15_IP_NO_KIQ(MMHUB, ack, inst);
892 else
893 tmp = RREG32_SOC15_IP_NO_KIQ(GC, ack, inst);
894 if (tmp & (1 << vmid))
895 break;
896 udelay(1);
897 }
898
899 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */
900 if (use_semaphore) {
901 /*
902 * add semaphore release after invalidation,
903 * write with 0 means semaphore release
904 */
905 if (vmhub >= AMDGPU_MMHUB0(0))
906 WREG32_SOC15_IP_NO_KIQ(MMHUB, sem, 0, inst);
907 else
908 WREG32_SOC15_IP_NO_KIQ(GC, sem, 0, inst);
909 }
910
911 spin_unlock(&adev->gmc.invalidate_lock);
912
913 if (j < adev->usec_timeout)
914 return;
915
916 DRM_ERROR("Timeout waiting for VM flush ACK!\n");
917}
918
919/**
920 * gmc_v9_0_flush_gpu_tlb_pasid - tlb flush via pasid
921 *
922 * @adev: amdgpu_device pointer
923 * @pasid: pasid to be flush
924 * @flush_type: the flush type
925 * @all_hub: flush all hubs
926 * @inst: is used to select which instance of KIQ to use for the invalidation
927 *
928 * Flush the TLB for the requested pasid.
929 */
930static void gmc_v9_0_flush_gpu_tlb_pasid(struct amdgpu_device *adev,
931 uint16_t pasid, uint32_t flush_type,
932 bool all_hub, uint32_t inst)
933{
934 uint16_t queried;
935 int i, vmid;
936
937 for (vmid = 1; vmid < 16; vmid++) {
938 bool valid;
939
940 valid = gmc_v9_0_get_atc_vmid_pasid_mapping_info(adev, vmid,
941 &queried);
942 if (!valid || queried != pasid)
943 continue;
944
945 if (all_hub) {
946 for_each_set_bit(i, adev->vmhubs_mask,
947 AMDGPU_MAX_VMHUBS)
948 gmc_v9_0_flush_gpu_tlb(adev, vmid, i,
949 flush_type);
950 } else {
951 gmc_v9_0_flush_gpu_tlb(adev, vmid,
952 AMDGPU_GFXHUB(0),
953 flush_type);
954 }
955 }
956}
957
958static uint64_t gmc_v9_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring,
959 unsigned int vmid, uint64_t pd_addr)
960{
961 bool use_semaphore = gmc_v9_0_use_invalidate_semaphore(ring->adev, ring->vm_hub);
962 struct amdgpu_device *adev = ring->adev;
963 struct amdgpu_vmhub *hub = &adev->vmhub[ring->vm_hub];
964 uint32_t req = gmc_v9_0_get_invalidate_req(vmid, 0);
965 unsigned int eng = ring->vm_inv_eng;
966
967 /*
968 * It may lose gpuvm invalidate acknowldege state across power-gating
969 * off cycle, add semaphore acquire before invalidation and semaphore
970 * release after invalidation to avoid entering power gated state
971 * to WA the Issue
972 */
973
974 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */
975 if (use_semaphore)
976 /* a read return value of 1 means semaphore acuqire */
977 amdgpu_ring_emit_reg_wait(ring,
978 hub->vm_inv_eng0_sem +
979 hub->eng_distance * eng, 0x1, 0x1);
980
981 amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_lo32 +
982 (hub->ctx_addr_distance * vmid),
983 lower_32_bits(pd_addr));
984
985 amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_hi32 +
986 (hub->ctx_addr_distance * vmid),
987 upper_32_bits(pd_addr));
988
989 amdgpu_ring_emit_reg_write_reg_wait(ring, hub->vm_inv_eng0_req +
990 hub->eng_distance * eng,
991 hub->vm_inv_eng0_ack +
992 hub->eng_distance * eng,
993 req, 1 << vmid);
994
995 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */
996 if (use_semaphore)
997 /*
998 * add semaphore release after invalidation,
999 * write with 0 means semaphore release
1000 */
1001 amdgpu_ring_emit_wreg(ring, hub->vm_inv_eng0_sem +
1002 hub->eng_distance * eng, 0);
1003
1004 return pd_addr;
1005}
1006
1007static void gmc_v9_0_emit_pasid_mapping(struct amdgpu_ring *ring, unsigned int vmid,
1008 unsigned int pasid)
1009{
1010 struct amdgpu_device *adev = ring->adev;
1011 uint32_t reg;
1012
1013 /* Do nothing because there's no lut register for mmhub1. */
1014 if (ring->vm_hub == AMDGPU_MMHUB1(0))
1015 return;
1016
1017 if (ring->vm_hub == AMDGPU_GFXHUB(0))
1018 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT) + vmid;
1019 else
1020 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT_MM) + vmid;
1021
1022 amdgpu_ring_emit_wreg(ring, reg, pasid);
1023}
1024
1025/*
1026 * PTE format on VEGA 10:
1027 * 63:59 reserved
1028 * 58:57 mtype
1029 * 56 F
1030 * 55 L
1031 * 54 P
1032 * 53 SW
1033 * 52 T
1034 * 50:48 reserved
1035 * 47:12 4k physical page base address
1036 * 11:7 fragment
1037 * 6 write
1038 * 5 read
1039 * 4 exe
1040 * 3 Z
1041 * 2 snooped
1042 * 1 system
1043 * 0 valid
1044 *
1045 * PDE format on VEGA 10:
1046 * 63:59 block fragment size
1047 * 58:55 reserved
1048 * 54 P
1049 * 53:48 reserved
1050 * 47:6 physical base address of PD or PTE
1051 * 5:3 reserved
1052 * 2 C
1053 * 1 system
1054 * 0 valid
1055 */
1056
1057static uint64_t gmc_v9_0_map_mtype(struct amdgpu_device *adev, uint32_t flags)
1058
1059{
1060 switch (flags) {
1061 case AMDGPU_VM_MTYPE_DEFAULT:
1062 return AMDGPU_PTE_MTYPE_VG10(MTYPE_NC);
1063 case AMDGPU_VM_MTYPE_NC:
1064 return AMDGPU_PTE_MTYPE_VG10(MTYPE_NC);
1065 case AMDGPU_VM_MTYPE_WC:
1066 return AMDGPU_PTE_MTYPE_VG10(MTYPE_WC);
1067 case AMDGPU_VM_MTYPE_RW:
1068 return AMDGPU_PTE_MTYPE_VG10(MTYPE_RW);
1069 case AMDGPU_VM_MTYPE_CC:
1070 return AMDGPU_PTE_MTYPE_VG10(MTYPE_CC);
1071 case AMDGPU_VM_MTYPE_UC:
1072 return AMDGPU_PTE_MTYPE_VG10(MTYPE_UC);
1073 default:
1074 return AMDGPU_PTE_MTYPE_VG10(MTYPE_NC);
1075 }
1076}
1077
1078static void gmc_v9_0_get_vm_pde(struct amdgpu_device *adev, int level,
1079 uint64_t *addr, uint64_t *flags)
1080{
1081 if (!(*flags & AMDGPU_PDE_PTE) && !(*flags & AMDGPU_PTE_SYSTEM))
1082 *addr = amdgpu_gmc_vram_mc2pa(adev, *addr);
1083 BUG_ON(*addr & 0xFFFF00000000003FULL);
1084
1085 if (!adev->gmc.translate_further)
1086 return;
1087
1088 if (level == AMDGPU_VM_PDB1) {
1089 /* Set the block fragment size */
1090 if (!(*flags & AMDGPU_PDE_PTE))
1091 *flags |= AMDGPU_PDE_BFS(0x9);
1092
1093 } else if (level == AMDGPU_VM_PDB0) {
1094 if (*flags & AMDGPU_PDE_PTE) {
1095 *flags &= ~AMDGPU_PDE_PTE;
1096 if (!(*flags & AMDGPU_PTE_VALID))
1097 *addr |= 1 << PAGE_SHIFT;
1098 } else {
1099 *flags |= AMDGPU_PTE_TF;
1100 }
1101 }
1102}
1103
1104static void gmc_v9_0_get_coherence_flags(struct amdgpu_device *adev,
1105 struct amdgpu_bo *bo,
1106 struct amdgpu_bo_va_mapping *mapping,
1107 uint64_t *flags)
1108{
1109 struct amdgpu_device *bo_adev = amdgpu_ttm_adev(bo->tbo.bdev);
1110 bool is_vram = bo->tbo.resource->mem_type == TTM_PL_VRAM;
1111 bool coherent = bo->flags & (AMDGPU_GEM_CREATE_COHERENT | AMDGPU_GEM_CREATE_EXT_COHERENT);
1112 bool ext_coherent = bo->flags & AMDGPU_GEM_CREATE_EXT_COHERENT;
1113 bool uncached = bo->flags & AMDGPU_GEM_CREATE_UNCACHED;
1114 struct amdgpu_vm *vm = mapping->bo_va->base.vm;
1115 unsigned int mtype_local, mtype;
1116 bool snoop = false;
1117 bool is_local;
1118
1119 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
1120 case IP_VERSION(9, 4, 1):
1121 case IP_VERSION(9, 4, 2):
1122 if (is_vram) {
1123 if (bo_adev == adev) {
1124 if (uncached)
1125 mtype = MTYPE_UC;
1126 else if (coherent)
1127 mtype = MTYPE_CC;
1128 else
1129 mtype = MTYPE_RW;
1130 /* FIXME: is this still needed? Or does
1131 * amdgpu_ttm_tt_pde_flags already handle this?
1132 */
1133 if ((amdgpu_ip_version(adev, GC_HWIP, 0) ==
1134 IP_VERSION(9, 4, 2) ||
1135 amdgpu_ip_version(adev, GC_HWIP, 0) ==
1136 IP_VERSION(9, 4, 3)) &&
1137 adev->gmc.xgmi.connected_to_cpu)
1138 snoop = true;
1139 } else {
1140 if (uncached || coherent)
1141 mtype = MTYPE_UC;
1142 else
1143 mtype = MTYPE_NC;
1144 if (mapping->bo_va->is_xgmi)
1145 snoop = true;
1146 }
1147 } else {
1148 if (uncached || coherent)
1149 mtype = MTYPE_UC;
1150 else
1151 mtype = MTYPE_NC;
1152 /* FIXME: is this still needed? Or does
1153 * amdgpu_ttm_tt_pde_flags already handle this?
1154 */
1155 snoop = true;
1156 }
1157 break;
1158 case IP_VERSION(9, 4, 3):
1159 /* Only local VRAM BOs or system memory on non-NUMA APUs
1160 * can be assumed to be local in their entirety. Choose
1161 * MTYPE_NC as safe fallback for all system memory BOs on
1162 * NUMA systems. Their MTYPE can be overridden per-page in
1163 * gmc_v9_0_override_vm_pte_flags.
1164 */
1165 mtype_local = MTYPE_RW;
1166 if (amdgpu_mtype_local == 1) {
1167 DRM_INFO_ONCE("Using MTYPE_NC for local memory\n");
1168 mtype_local = MTYPE_NC;
1169 } else if (amdgpu_mtype_local == 2) {
1170 DRM_INFO_ONCE("Using MTYPE_CC for local memory\n");
1171 mtype_local = MTYPE_CC;
1172 } else {
1173 DRM_INFO_ONCE("Using MTYPE_RW for local memory\n");
1174 }
1175 is_local = (!is_vram && (adev->flags & AMD_IS_APU) &&
1176 num_possible_nodes() <= 1) ||
1177 (is_vram && adev == bo_adev &&
1178 KFD_XCP_MEM_ID(adev, bo->xcp_id) == vm->mem_id);
1179 snoop = true;
1180 if (uncached) {
1181 mtype = MTYPE_UC;
1182 } else if (ext_coherent) {
1183 if (adev->rev_id)
1184 mtype = is_local ? MTYPE_CC : MTYPE_UC;
1185 else
1186 mtype = MTYPE_UC;
1187 } else if (adev->flags & AMD_IS_APU) {
1188 mtype = is_local ? mtype_local : MTYPE_NC;
1189 } else {
1190 /* dGPU */
1191 if (is_local)
1192 mtype = mtype_local;
1193 else if (is_vram)
1194 mtype = MTYPE_NC;
1195 else
1196 mtype = MTYPE_UC;
1197 }
1198
1199 break;
1200 default:
1201 if (uncached || coherent)
1202 mtype = MTYPE_UC;
1203 else
1204 mtype = MTYPE_NC;
1205
1206 /* FIXME: is this still needed? Or does
1207 * amdgpu_ttm_tt_pde_flags already handle this?
1208 */
1209 if (!is_vram)
1210 snoop = true;
1211 }
1212
1213 if (mtype != MTYPE_NC)
1214 *flags = (*flags & ~AMDGPU_PTE_MTYPE_VG10_MASK) |
1215 AMDGPU_PTE_MTYPE_VG10(mtype);
1216 *flags |= snoop ? AMDGPU_PTE_SNOOPED : 0;
1217}
1218
1219static void gmc_v9_0_get_vm_pte(struct amdgpu_device *adev,
1220 struct amdgpu_bo_va_mapping *mapping,
1221 uint64_t *flags)
1222{
1223 struct amdgpu_bo *bo = mapping->bo_va->base.bo;
1224
1225 *flags &= ~AMDGPU_PTE_EXECUTABLE;
1226 *flags |= mapping->flags & AMDGPU_PTE_EXECUTABLE;
1227
1228 *flags &= ~AMDGPU_PTE_MTYPE_VG10_MASK;
1229 *flags |= mapping->flags & AMDGPU_PTE_MTYPE_VG10_MASK;
1230
1231 if (mapping->flags & AMDGPU_PTE_PRT) {
1232 *flags |= AMDGPU_PTE_PRT;
1233 *flags &= ~AMDGPU_PTE_VALID;
1234 }
1235
1236 if (bo && bo->tbo.resource)
1237 gmc_v9_0_get_coherence_flags(adev, mapping->bo_va->base.bo,
1238 mapping, flags);
1239}
1240
1241static void gmc_v9_0_override_vm_pte_flags(struct amdgpu_device *adev,
1242 struct amdgpu_vm *vm,
1243 uint64_t addr, uint64_t *flags)
1244{
1245 int local_node, nid;
1246
1247 /* Only GFX 9.4.3 APUs associate GPUs with NUMA nodes. Local system
1248 * memory can use more efficient MTYPEs.
1249 */
1250 if (amdgpu_ip_version(adev, GC_HWIP, 0) != IP_VERSION(9, 4, 3))
1251 return;
1252
1253 /* Only direct-mapped memory allows us to determine the NUMA node from
1254 * the DMA address.
1255 */
1256 if (!adev->ram_is_direct_mapped) {
1257 dev_dbg_ratelimited(adev->dev, "RAM is not direct mapped\n");
1258 return;
1259 }
1260
1261 /* MTYPE_NC is the same default and can be overridden.
1262 * MTYPE_UC will be present if the memory is extended-coherent
1263 * and can also be overridden.
1264 */
1265 if ((*flags & AMDGPU_PTE_MTYPE_VG10_MASK) !=
1266 AMDGPU_PTE_MTYPE_VG10(MTYPE_NC) &&
1267 (*flags & AMDGPU_PTE_MTYPE_VG10_MASK) !=
1268 AMDGPU_PTE_MTYPE_VG10(MTYPE_UC)) {
1269 dev_dbg_ratelimited(adev->dev, "MTYPE is not NC or UC\n");
1270 return;
1271 }
1272
1273 /* FIXME: Only supported on native mode for now. For carve-out, the
1274 * NUMA affinity of the GPU/VM needs to come from the PCI info because
1275 * memory partitions are not associated with different NUMA nodes.
1276 */
1277 if (adev->gmc.is_app_apu && vm->mem_id >= 0) {
1278 local_node = adev->gmc.mem_partitions[vm->mem_id].numa.node;
1279 } else {
1280 dev_dbg_ratelimited(adev->dev, "Only native mode APU is supported.\n");
1281 return;
1282 }
1283
1284 /* Only handle real RAM. Mappings of PCIe resources don't have struct
1285 * page or NUMA nodes.
1286 */
1287 if (!page_is_ram(addr >> PAGE_SHIFT)) {
1288 dev_dbg_ratelimited(adev->dev, "Page is not RAM.\n");
1289 return;
1290 }
1291 nid = pfn_to_nid(addr >> PAGE_SHIFT);
1292 dev_dbg_ratelimited(adev->dev, "vm->mem_id=%d, local_node=%d, nid=%d\n",
1293 vm->mem_id, local_node, nid);
1294 if (nid == local_node) {
1295 uint64_t old_flags = *flags;
1296 if ((*flags & AMDGPU_PTE_MTYPE_VG10_MASK) ==
1297 AMDGPU_PTE_MTYPE_VG10(MTYPE_NC)) {
1298 unsigned int mtype_local = MTYPE_RW;
1299
1300 if (amdgpu_mtype_local == 1)
1301 mtype_local = MTYPE_NC;
1302 else if (amdgpu_mtype_local == 2)
1303 mtype_local = MTYPE_CC;
1304
1305 *flags = (*flags & ~AMDGPU_PTE_MTYPE_VG10_MASK) |
1306 AMDGPU_PTE_MTYPE_VG10(mtype_local);
1307 } else if (adev->rev_id) {
1308 /* MTYPE_UC case */
1309 *flags = (*flags & ~AMDGPU_PTE_MTYPE_VG10_MASK) |
1310 AMDGPU_PTE_MTYPE_VG10(MTYPE_CC);
1311 }
1312
1313 dev_dbg_ratelimited(adev->dev, "flags updated from %llx to %llx\n",
1314 old_flags, *flags);
1315 }
1316}
1317
1318static unsigned int gmc_v9_0_get_vbios_fb_size(struct amdgpu_device *adev)
1319{
1320 u32 d1vga_control = RREG32_SOC15(DCE, 0, mmD1VGA_CONTROL);
1321 unsigned int size;
1322
1323 /* TODO move to DC so GMC doesn't need to hard-code DCN registers */
1324
1325 if (REG_GET_FIELD(d1vga_control, D1VGA_CONTROL, D1VGA_MODE_ENABLE)) {
1326 size = AMDGPU_VBIOS_VGA_ALLOCATION;
1327 } else {
1328 u32 viewport;
1329
1330 switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) {
1331 case IP_VERSION(1, 0, 0):
1332 case IP_VERSION(1, 0, 1):
1333 viewport = RREG32_SOC15(DCE, 0, mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION);
1334 size = (REG_GET_FIELD(viewport,
1335 HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_HEIGHT) *
1336 REG_GET_FIELD(viewport,
1337 HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_WIDTH) *
1338 4);
1339 break;
1340 case IP_VERSION(2, 1, 0):
1341 viewport = RREG32_SOC15(DCE, 0, mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_DCN2);
1342 size = (REG_GET_FIELD(viewport,
1343 HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_HEIGHT) *
1344 REG_GET_FIELD(viewport,
1345 HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_WIDTH) *
1346 4);
1347 break;
1348 default:
1349 viewport = RREG32_SOC15(DCE, 0, mmSCL0_VIEWPORT_SIZE);
1350 size = (REG_GET_FIELD(viewport, SCL0_VIEWPORT_SIZE, VIEWPORT_HEIGHT) *
1351 REG_GET_FIELD(viewport, SCL0_VIEWPORT_SIZE, VIEWPORT_WIDTH) *
1352 4);
1353 break;
1354 }
1355 }
1356
1357 return size;
1358}
1359
1360static enum amdgpu_memory_partition
1361gmc_v9_0_get_memory_partition(struct amdgpu_device *adev, u32 *supp_modes)
1362{
1363 enum amdgpu_memory_partition mode = UNKNOWN_MEMORY_PARTITION_MODE;
1364
1365 if (adev->nbio.funcs->get_memory_partition_mode)
1366 mode = adev->nbio.funcs->get_memory_partition_mode(adev,
1367 supp_modes);
1368
1369 return mode;
1370}
1371
1372static enum amdgpu_memory_partition
1373gmc_v9_0_query_memory_partition(struct amdgpu_device *adev)
1374{
1375 if (amdgpu_sriov_vf(adev))
1376 return AMDGPU_NPS1_PARTITION_MODE;
1377
1378 return gmc_v9_0_get_memory_partition(adev, NULL);
1379}
1380
1381static const struct amdgpu_gmc_funcs gmc_v9_0_gmc_funcs = {
1382 .flush_gpu_tlb = gmc_v9_0_flush_gpu_tlb,
1383 .flush_gpu_tlb_pasid = gmc_v9_0_flush_gpu_tlb_pasid,
1384 .emit_flush_gpu_tlb = gmc_v9_0_emit_flush_gpu_tlb,
1385 .emit_pasid_mapping = gmc_v9_0_emit_pasid_mapping,
1386 .map_mtype = gmc_v9_0_map_mtype,
1387 .get_vm_pde = gmc_v9_0_get_vm_pde,
1388 .get_vm_pte = gmc_v9_0_get_vm_pte,
1389 .override_vm_pte_flags = gmc_v9_0_override_vm_pte_flags,
1390 .get_vbios_fb_size = gmc_v9_0_get_vbios_fb_size,
1391 .query_mem_partition_mode = &gmc_v9_0_query_memory_partition,
1392};
1393
1394static void gmc_v9_0_set_gmc_funcs(struct amdgpu_device *adev)
1395{
1396 adev->gmc.gmc_funcs = &gmc_v9_0_gmc_funcs;
1397}
1398
1399static void gmc_v9_0_set_umc_funcs(struct amdgpu_device *adev)
1400{
1401 switch (amdgpu_ip_version(adev, UMC_HWIP, 0)) {
1402 case IP_VERSION(6, 0, 0):
1403 adev->umc.funcs = &umc_v6_0_funcs;
1404 break;
1405 case IP_VERSION(6, 1, 1):
1406 adev->umc.max_ras_err_cnt_per_query = UMC_V6_1_TOTAL_CHANNEL_NUM;
1407 adev->umc.channel_inst_num = UMC_V6_1_CHANNEL_INSTANCE_NUM;
1408 adev->umc.umc_inst_num = UMC_V6_1_UMC_INSTANCE_NUM;
1409 adev->umc.channel_offs = UMC_V6_1_PER_CHANNEL_OFFSET_VG20;
1410 adev->umc.retire_unit = 1;
1411 adev->umc.channel_idx_tbl = &umc_v6_1_channel_idx_tbl[0][0];
1412 adev->umc.ras = &umc_v6_1_ras;
1413 break;
1414 case IP_VERSION(6, 1, 2):
1415 adev->umc.max_ras_err_cnt_per_query = UMC_V6_1_TOTAL_CHANNEL_NUM;
1416 adev->umc.channel_inst_num = UMC_V6_1_CHANNEL_INSTANCE_NUM;
1417 adev->umc.umc_inst_num = UMC_V6_1_UMC_INSTANCE_NUM;
1418 adev->umc.channel_offs = UMC_V6_1_PER_CHANNEL_OFFSET_ARCT;
1419 adev->umc.retire_unit = 1;
1420 adev->umc.channel_idx_tbl = &umc_v6_1_channel_idx_tbl[0][0];
1421 adev->umc.ras = &umc_v6_1_ras;
1422 break;
1423 case IP_VERSION(6, 7, 0):
1424 adev->umc.max_ras_err_cnt_per_query =
1425 UMC_V6_7_TOTAL_CHANNEL_NUM * UMC_V6_7_BAD_PAGE_NUM_PER_CHANNEL;
1426 adev->umc.channel_inst_num = UMC_V6_7_CHANNEL_INSTANCE_NUM;
1427 adev->umc.umc_inst_num = UMC_V6_7_UMC_INSTANCE_NUM;
1428 adev->umc.channel_offs = UMC_V6_7_PER_CHANNEL_OFFSET;
1429 adev->umc.retire_unit = (UMC_V6_7_NA_MAP_PA_NUM * 2);
1430 if (!adev->gmc.xgmi.connected_to_cpu)
1431 adev->umc.ras = &umc_v6_7_ras;
1432 if (1 & adev->smuio.funcs->get_die_id(adev))
1433 adev->umc.channel_idx_tbl = &umc_v6_7_channel_idx_tbl_first[0][0];
1434 else
1435 adev->umc.channel_idx_tbl = &umc_v6_7_channel_idx_tbl_second[0][0];
1436 break;
1437 case IP_VERSION(12, 0, 0):
1438 adev->umc.max_ras_err_cnt_per_query =
1439 UMC_V12_0_TOTAL_CHANNEL_NUM(adev) * UMC_V12_0_BAD_PAGE_NUM_PER_CHANNEL;
1440 adev->umc.channel_inst_num = UMC_V12_0_CHANNEL_INSTANCE_NUM;
1441 adev->umc.umc_inst_num = UMC_V12_0_UMC_INSTANCE_NUM;
1442 adev->umc.node_inst_num /= UMC_V12_0_UMC_INSTANCE_NUM;
1443 adev->umc.channel_offs = UMC_V12_0_PER_CHANNEL_OFFSET;
1444 adev->umc.active_mask = adev->aid_mask;
1445 adev->umc.retire_unit = UMC_V12_0_BAD_PAGE_NUM_PER_CHANNEL;
1446 adev->umc.channel_idx_tbl = &umc_v12_0_channel_idx_tbl[0][0][0];
1447 if (!adev->gmc.xgmi.connected_to_cpu && !adev->gmc.is_app_apu)
1448 adev->umc.ras = &umc_v12_0_ras;
1449 break;
1450 default:
1451 break;
1452 }
1453}
1454
1455static void gmc_v9_0_set_mmhub_funcs(struct amdgpu_device *adev)
1456{
1457 switch (amdgpu_ip_version(adev, MMHUB_HWIP, 0)) {
1458 case IP_VERSION(9, 4, 1):
1459 adev->mmhub.funcs = &mmhub_v9_4_funcs;
1460 break;
1461 case IP_VERSION(9, 4, 2):
1462 adev->mmhub.funcs = &mmhub_v1_7_funcs;
1463 break;
1464 case IP_VERSION(1, 8, 0):
1465 adev->mmhub.funcs = &mmhub_v1_8_funcs;
1466 break;
1467 default:
1468 adev->mmhub.funcs = &mmhub_v1_0_funcs;
1469 break;
1470 }
1471}
1472
1473static void gmc_v9_0_set_mmhub_ras_funcs(struct amdgpu_device *adev)
1474{
1475 switch (amdgpu_ip_version(adev, MMHUB_HWIP, 0)) {
1476 case IP_VERSION(9, 4, 0):
1477 adev->mmhub.ras = &mmhub_v1_0_ras;
1478 break;
1479 case IP_VERSION(9, 4, 1):
1480 adev->mmhub.ras = &mmhub_v9_4_ras;
1481 break;
1482 case IP_VERSION(9, 4, 2):
1483 adev->mmhub.ras = &mmhub_v1_7_ras;
1484 break;
1485 case IP_VERSION(1, 8, 0):
1486 adev->mmhub.ras = &mmhub_v1_8_ras;
1487 break;
1488 default:
1489 /* mmhub ras is not available */
1490 break;
1491 }
1492}
1493
1494static void gmc_v9_0_set_gfxhub_funcs(struct amdgpu_device *adev)
1495{
1496 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 3))
1497 adev->gfxhub.funcs = &gfxhub_v1_2_funcs;
1498 else
1499 adev->gfxhub.funcs = &gfxhub_v1_0_funcs;
1500}
1501
1502static void gmc_v9_0_set_hdp_ras_funcs(struct amdgpu_device *adev)
1503{
1504 adev->hdp.ras = &hdp_v4_0_ras;
1505}
1506
1507static void gmc_v9_0_set_mca_ras_funcs(struct amdgpu_device *adev)
1508{
1509 struct amdgpu_mca *mca = &adev->mca;
1510
1511 /* is UMC the right IP to check for MCA? Maybe DF? */
1512 switch (amdgpu_ip_version(adev, UMC_HWIP, 0)) {
1513 case IP_VERSION(6, 7, 0):
1514 if (!adev->gmc.xgmi.connected_to_cpu) {
1515 mca->mp0.ras = &mca_v3_0_mp0_ras;
1516 mca->mp1.ras = &mca_v3_0_mp1_ras;
1517 mca->mpio.ras = &mca_v3_0_mpio_ras;
1518 }
1519 break;
1520 default:
1521 break;
1522 }
1523}
1524
1525static void gmc_v9_0_set_xgmi_ras_funcs(struct amdgpu_device *adev)
1526{
1527 if (!adev->gmc.xgmi.connected_to_cpu)
1528 adev->gmc.xgmi.ras = &xgmi_ras;
1529}
1530
1531static int gmc_v9_0_early_init(void *handle)
1532{
1533 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1534
1535 /*
1536 * 9.4.0, 9.4.1 and 9.4.3 don't have XGMI defined
1537 * in their IP discovery tables
1538 */
1539 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 0) ||
1540 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 1) ||
1541 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 3))
1542 adev->gmc.xgmi.supported = true;
1543
1544 if (amdgpu_ip_version(adev, XGMI_HWIP, 0) == IP_VERSION(6, 1, 0)) {
1545 adev->gmc.xgmi.supported = true;
1546 adev->gmc.xgmi.connected_to_cpu =
1547 adev->smuio.funcs->is_host_gpu_xgmi_supported(adev);
1548 }
1549
1550 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 3)) {
1551 enum amdgpu_pkg_type pkg_type =
1552 adev->smuio.funcs->get_pkg_type(adev);
1553 /* On GFXIP 9.4.3. APU, there is no physical VRAM domain present
1554 * and the APU, can be in used two possible modes:
1555 * - carveout mode
1556 * - native APU mode
1557 * "is_app_apu" can be used to identify the APU in the native
1558 * mode.
1559 */
1560 adev->gmc.is_app_apu = (pkg_type == AMDGPU_PKG_TYPE_APU &&
1561 !pci_resource_len(adev->pdev, 0));
1562 }
1563
1564 gmc_v9_0_set_gmc_funcs(adev);
1565 gmc_v9_0_set_irq_funcs(adev);
1566 gmc_v9_0_set_umc_funcs(adev);
1567 gmc_v9_0_set_mmhub_funcs(adev);
1568 gmc_v9_0_set_mmhub_ras_funcs(adev);
1569 gmc_v9_0_set_gfxhub_funcs(adev);
1570 gmc_v9_0_set_hdp_ras_funcs(adev);
1571 gmc_v9_0_set_mca_ras_funcs(adev);
1572 gmc_v9_0_set_xgmi_ras_funcs(adev);
1573
1574 adev->gmc.shared_aperture_start = 0x2000000000000000ULL;
1575 adev->gmc.shared_aperture_end =
1576 adev->gmc.shared_aperture_start + (4ULL << 30) - 1;
1577 adev->gmc.private_aperture_start = 0x1000000000000000ULL;
1578 adev->gmc.private_aperture_end =
1579 adev->gmc.private_aperture_start + (4ULL << 30) - 1;
1580 adev->gmc.noretry_flags = AMDGPU_VM_NORETRY_FLAGS_TF;
1581
1582 return 0;
1583}
1584
1585static int gmc_v9_0_late_init(void *handle)
1586{
1587 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1588 int r;
1589
1590 r = amdgpu_gmc_allocate_vm_inv_eng(adev);
1591 if (r)
1592 return r;
1593
1594 /*
1595 * Workaround performance drop issue with VBIOS enables partial
1596 * writes, while disables HBM ECC for vega10.
1597 */
1598 if (!amdgpu_sriov_vf(adev) &&
1599 (amdgpu_ip_version(adev, UMC_HWIP, 0) == IP_VERSION(6, 0, 0))) {
1600 if (!(adev->ras_enabled & (1 << AMDGPU_RAS_BLOCK__UMC))) {
1601 if (adev->df.funcs &&
1602 adev->df.funcs->enable_ecc_force_par_wr_rmw)
1603 adev->df.funcs->enable_ecc_force_par_wr_rmw(adev, false);
1604 }
1605 }
1606
1607 if (!amdgpu_persistent_edc_harvesting_supported(adev)) {
1608 amdgpu_ras_reset_error_count(adev, AMDGPU_RAS_BLOCK__MMHUB);
1609 amdgpu_ras_reset_error_count(adev, AMDGPU_RAS_BLOCK__HDP);
1610 }
1611
1612 r = amdgpu_gmc_ras_late_init(adev);
1613 if (r)
1614 return r;
1615
1616 return amdgpu_irq_get(adev, &adev->gmc.vm_fault, 0);
1617}
1618
1619static void gmc_v9_0_vram_gtt_location(struct amdgpu_device *adev,
1620 struct amdgpu_gmc *mc)
1621{
1622 u64 base = adev->mmhub.funcs->get_fb_location(adev);
1623
1624 amdgpu_gmc_set_agp_default(adev, mc);
1625
1626 /* add the xgmi offset of the physical node */
1627 base += adev->gmc.xgmi.physical_node_id * adev->gmc.xgmi.node_segment_size;
1628 if (adev->gmc.xgmi.connected_to_cpu) {
1629 amdgpu_gmc_sysvm_location(adev, mc);
1630 } else {
1631 amdgpu_gmc_vram_location(adev, mc, base);
1632 amdgpu_gmc_gart_location(adev, mc, AMDGPU_GART_PLACEMENT_BEST_FIT);
1633 if (!amdgpu_sriov_vf(adev) && (amdgpu_agp == 1))
1634 amdgpu_gmc_agp_location(adev, mc);
1635 }
1636 /* base offset of vram pages */
1637 adev->vm_manager.vram_base_offset = adev->gfxhub.funcs->get_mc_fb_offset(adev);
1638
1639 /* XXX: add the xgmi offset of the physical node? */
1640 adev->vm_manager.vram_base_offset +=
1641 adev->gmc.xgmi.physical_node_id * adev->gmc.xgmi.node_segment_size;
1642}
1643
1644/**
1645 * gmc_v9_0_mc_init - initialize the memory controller driver params
1646 *
1647 * @adev: amdgpu_device pointer
1648 *
1649 * Look up the amount of vram, vram width, and decide how to place
1650 * vram and gart within the GPU's physical address space.
1651 * Returns 0 for success.
1652 */
1653static int gmc_v9_0_mc_init(struct amdgpu_device *adev)
1654{
1655 int r;
1656
1657 /* size in MB on si */
1658 if (!adev->gmc.is_app_apu) {
1659 adev->gmc.mc_vram_size =
1660 adev->nbio.funcs->get_memsize(adev) * 1024ULL * 1024ULL;
1661 } else {
1662 DRM_DEBUG("Set mc_vram_size = 0 for APP APU\n");
1663 adev->gmc.mc_vram_size = 0;
1664 }
1665 adev->gmc.real_vram_size = adev->gmc.mc_vram_size;
1666
1667 if (!(adev->flags & AMD_IS_APU) &&
1668 !adev->gmc.xgmi.connected_to_cpu) {
1669 r = amdgpu_device_resize_fb_bar(adev);
1670 if (r)
1671 return r;
1672 }
1673 adev->gmc.aper_base = pci_resource_start(adev->pdev, 0);
1674 adev->gmc.aper_size = pci_resource_len(adev->pdev, 0);
1675
1676#ifdef CONFIG_X86_64
1677 /*
1678 * AMD Accelerated Processing Platform (APP) supporting GPU-HOST xgmi
1679 * interface can use VRAM through here as it appears system reserved
1680 * memory in host address space.
1681 *
1682 * For APUs, VRAM is just the stolen system memory and can be accessed
1683 * directly.
1684 *
1685 * Otherwise, use the legacy Host Data Path (HDP) through PCIe BAR.
1686 */
1687
1688 /* check whether both host-gpu and gpu-gpu xgmi links exist */
1689 if ((!amdgpu_sriov_vf(adev) &&
1690 (adev->flags & AMD_IS_APU) && !amdgpu_passthrough(adev)) ||
1691 (adev->gmc.xgmi.supported &&
1692 adev->gmc.xgmi.connected_to_cpu)) {
1693 adev->gmc.aper_base =
1694 adev->gfxhub.funcs->get_mc_fb_offset(adev) +
1695 adev->gmc.xgmi.physical_node_id *
1696 adev->gmc.xgmi.node_segment_size;
1697 adev->gmc.aper_size = adev->gmc.real_vram_size;
1698 }
1699
1700#endif
1701 adev->gmc.visible_vram_size = adev->gmc.aper_size;
1702
1703 /* set the gart size */
1704 if (amdgpu_gart_size == -1) {
1705 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
1706 case IP_VERSION(9, 0, 1): /* all engines support GPUVM */
1707 case IP_VERSION(9, 2, 1): /* all engines support GPUVM */
1708 case IP_VERSION(9, 4, 0):
1709 case IP_VERSION(9, 4, 1):
1710 case IP_VERSION(9, 4, 2):
1711 case IP_VERSION(9, 4, 3):
1712 default:
1713 adev->gmc.gart_size = 512ULL << 20;
1714 break;
1715 case IP_VERSION(9, 1, 0): /* DCE SG support */
1716 case IP_VERSION(9, 2, 2): /* DCE SG support */
1717 case IP_VERSION(9, 3, 0):
1718 adev->gmc.gart_size = 1024ULL << 20;
1719 break;
1720 }
1721 } else {
1722 adev->gmc.gart_size = (u64)amdgpu_gart_size << 20;
1723 }
1724
1725 adev->gmc.gart_size += adev->pm.smu_prv_buffer_size;
1726
1727 gmc_v9_0_vram_gtt_location(adev, &adev->gmc);
1728
1729 return 0;
1730}
1731
1732static int gmc_v9_0_gart_init(struct amdgpu_device *adev)
1733{
1734 int r;
1735
1736 if (adev->gart.bo) {
1737 WARN(1, "VEGA10 PCIE GART already initialized\n");
1738 return 0;
1739 }
1740
1741 if (adev->gmc.xgmi.connected_to_cpu) {
1742 adev->gmc.vmid0_page_table_depth = 1;
1743 adev->gmc.vmid0_page_table_block_size = 12;
1744 } else {
1745 adev->gmc.vmid0_page_table_depth = 0;
1746 adev->gmc.vmid0_page_table_block_size = 0;
1747 }
1748
1749 /* Initialize common gart structure */
1750 r = amdgpu_gart_init(adev);
1751 if (r)
1752 return r;
1753 adev->gart.table_size = adev->gart.num_gpu_pages * 8;
1754 adev->gart.gart_pte_flags = AMDGPU_PTE_MTYPE_VG10(MTYPE_UC) |
1755 AMDGPU_PTE_EXECUTABLE;
1756
1757 if (!adev->gmc.real_vram_size) {
1758 dev_info(adev->dev, "Put GART in system memory for APU\n");
1759 r = amdgpu_gart_table_ram_alloc(adev);
1760 if (r)
1761 dev_err(adev->dev, "Failed to allocate GART in system memory\n");
1762 } else {
1763 r = amdgpu_gart_table_vram_alloc(adev);
1764 if (r)
1765 return r;
1766
1767 if (adev->gmc.xgmi.connected_to_cpu)
1768 r = amdgpu_gmc_pdb0_alloc(adev);
1769 }
1770
1771 return r;
1772}
1773
1774/**
1775 * gmc_v9_0_save_registers - saves regs
1776 *
1777 * @adev: amdgpu_device pointer
1778 *
1779 * This saves potential register values that should be
1780 * restored upon resume
1781 */
1782static void gmc_v9_0_save_registers(struct amdgpu_device *adev)
1783{
1784 if ((amdgpu_ip_version(adev, DCE_HWIP, 0) == IP_VERSION(1, 0, 0)) ||
1785 (amdgpu_ip_version(adev, DCE_HWIP, 0) == IP_VERSION(1, 0, 1)))
1786 adev->gmc.sdpif_register = RREG32_SOC15(DCE, 0, mmDCHUBBUB_SDPIF_MMIO_CNTRL_0);
1787}
1788
1789static bool gmc_v9_0_validate_partition_info(struct amdgpu_device *adev)
1790{
1791 enum amdgpu_memory_partition mode;
1792 u32 supp_modes;
1793 bool valid;
1794
1795 mode = gmc_v9_0_get_memory_partition(adev, &supp_modes);
1796
1797 /* Mode detected by hardware not present in supported modes */
1798 if ((mode != UNKNOWN_MEMORY_PARTITION_MODE) &&
1799 !(BIT(mode - 1) & supp_modes))
1800 return false;
1801
1802 switch (mode) {
1803 case UNKNOWN_MEMORY_PARTITION_MODE:
1804 case AMDGPU_NPS1_PARTITION_MODE:
1805 valid = (adev->gmc.num_mem_partitions == 1);
1806 break;
1807 case AMDGPU_NPS2_PARTITION_MODE:
1808 valid = (adev->gmc.num_mem_partitions == 2);
1809 break;
1810 case AMDGPU_NPS4_PARTITION_MODE:
1811 valid = (adev->gmc.num_mem_partitions == 3 ||
1812 adev->gmc.num_mem_partitions == 4);
1813 break;
1814 default:
1815 valid = false;
1816 }
1817
1818 return valid;
1819}
1820
1821static bool gmc_v9_0_is_node_present(int *node_ids, int num_ids, int nid)
1822{
1823 int i;
1824
1825 /* Check if node with id 'nid' is present in 'node_ids' array */
1826 for (i = 0; i < num_ids; ++i)
1827 if (node_ids[i] == nid)
1828 return true;
1829
1830 return false;
1831}
1832
1833static void
1834gmc_v9_0_init_acpi_mem_ranges(struct amdgpu_device *adev,
1835 struct amdgpu_mem_partition_info *mem_ranges)
1836{
1837 struct amdgpu_numa_info numa_info;
1838 int node_ids[MAX_MEM_RANGES];
1839 int num_ranges = 0, ret;
1840 int num_xcc, xcc_id;
1841 uint32_t xcc_mask;
1842
1843 num_xcc = NUM_XCC(adev->gfx.xcc_mask);
1844 xcc_mask = (1U << num_xcc) - 1;
1845
1846 for_each_inst(xcc_id, xcc_mask) {
1847 ret = amdgpu_acpi_get_mem_info(adev, xcc_id, &numa_info);
1848 if (ret)
1849 continue;
1850
1851 if (numa_info.nid == NUMA_NO_NODE) {
1852 mem_ranges[0].size = numa_info.size;
1853 mem_ranges[0].numa.node = numa_info.nid;
1854 num_ranges = 1;
1855 break;
1856 }
1857
1858 if (gmc_v9_0_is_node_present(node_ids, num_ranges,
1859 numa_info.nid))
1860 continue;
1861
1862 node_ids[num_ranges] = numa_info.nid;
1863 mem_ranges[num_ranges].numa.node = numa_info.nid;
1864 mem_ranges[num_ranges].size = numa_info.size;
1865 ++num_ranges;
1866 }
1867
1868 adev->gmc.num_mem_partitions = num_ranges;
1869}
1870
1871static void
1872gmc_v9_0_init_sw_mem_ranges(struct amdgpu_device *adev,
1873 struct amdgpu_mem_partition_info *mem_ranges)
1874{
1875 enum amdgpu_memory_partition mode;
1876 u32 start_addr = 0, size;
1877 int i;
1878
1879 mode = gmc_v9_0_query_memory_partition(adev);
1880
1881 switch (mode) {
1882 case UNKNOWN_MEMORY_PARTITION_MODE:
1883 case AMDGPU_NPS1_PARTITION_MODE:
1884 adev->gmc.num_mem_partitions = 1;
1885 break;
1886 case AMDGPU_NPS2_PARTITION_MODE:
1887 adev->gmc.num_mem_partitions = 2;
1888 break;
1889 case AMDGPU_NPS4_PARTITION_MODE:
1890 if (adev->flags & AMD_IS_APU)
1891 adev->gmc.num_mem_partitions = 3;
1892 else
1893 adev->gmc.num_mem_partitions = 4;
1894 break;
1895 default:
1896 adev->gmc.num_mem_partitions = 1;
1897 break;
1898 }
1899
1900 size = adev->gmc.real_vram_size >> AMDGPU_GPU_PAGE_SHIFT;
1901 size /= adev->gmc.num_mem_partitions;
1902
1903 for (i = 0; i < adev->gmc.num_mem_partitions; ++i) {
1904 mem_ranges[i].range.fpfn = start_addr;
1905 mem_ranges[i].size = ((u64)size << AMDGPU_GPU_PAGE_SHIFT);
1906 mem_ranges[i].range.lpfn = start_addr + size - 1;
1907 start_addr += size;
1908 }
1909
1910 /* Adjust the last one */
1911 mem_ranges[adev->gmc.num_mem_partitions - 1].range.lpfn =
1912 (adev->gmc.real_vram_size >> AMDGPU_GPU_PAGE_SHIFT) - 1;
1913 mem_ranges[adev->gmc.num_mem_partitions - 1].size =
1914 adev->gmc.real_vram_size -
1915 ((u64)mem_ranges[adev->gmc.num_mem_partitions - 1].range.fpfn
1916 << AMDGPU_GPU_PAGE_SHIFT);
1917}
1918
1919static int gmc_v9_0_init_mem_ranges(struct amdgpu_device *adev)
1920{
1921 bool valid;
1922
1923 adev->gmc.mem_partitions = kcalloc(MAX_MEM_RANGES,
1924 sizeof(struct amdgpu_mem_partition_info),
1925 GFP_KERNEL);
1926 if (!adev->gmc.mem_partitions)
1927 return -ENOMEM;
1928
1929 /* TODO : Get the range from PSP/Discovery for dGPU */
1930 if (adev->gmc.is_app_apu)
1931 gmc_v9_0_init_acpi_mem_ranges(adev, adev->gmc.mem_partitions);
1932 else
1933 gmc_v9_0_init_sw_mem_ranges(adev, adev->gmc.mem_partitions);
1934
1935 if (amdgpu_sriov_vf(adev))
1936 valid = true;
1937 else
1938 valid = gmc_v9_0_validate_partition_info(adev);
1939 if (!valid) {
1940 /* TODO: handle invalid case */
1941 dev_WARN(adev->dev,
1942 "Mem ranges not matching with hardware config");
1943 }
1944
1945 return 0;
1946}
1947
1948static void gmc_v9_4_3_init_vram_info(struct amdgpu_device *adev)
1949{
1950 adev->gmc.vram_type = AMDGPU_VRAM_TYPE_HBM;
1951 adev->gmc.vram_width = 128 * 64;
1952}
1953
1954static int gmc_v9_0_sw_init(void *handle)
1955{
1956 int r, vram_width = 0, vram_type = 0, vram_vendor = 0, dma_addr_bits;
1957 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1958 unsigned long inst_mask = adev->aid_mask;
1959
1960 adev->gfxhub.funcs->init(adev);
1961
1962 adev->mmhub.funcs->init(adev);
1963
1964 spin_lock_init(&adev->gmc.invalidate_lock);
1965
1966 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 3)) {
1967 gmc_v9_4_3_init_vram_info(adev);
1968 } else if (!adev->bios) {
1969 if (adev->flags & AMD_IS_APU) {
1970 adev->gmc.vram_type = AMDGPU_VRAM_TYPE_DDR4;
1971 adev->gmc.vram_width = 64 * 64;
1972 } else {
1973 adev->gmc.vram_type = AMDGPU_VRAM_TYPE_HBM;
1974 adev->gmc.vram_width = 128 * 64;
1975 }
1976 } else {
1977 r = amdgpu_atomfirmware_get_vram_info(adev,
1978 &vram_width, &vram_type, &vram_vendor);
1979 if (amdgpu_sriov_vf(adev))
1980 /* For Vega10 SR-IOV, vram_width can't be read from ATOM as RAVEN,
1981 * and DF related registers is not readable, seems hardcord is the
1982 * only way to set the correct vram_width
1983 */
1984 adev->gmc.vram_width = 2048;
1985 else if (amdgpu_emu_mode != 1)
1986 adev->gmc.vram_width = vram_width;
1987
1988 if (!adev->gmc.vram_width) {
1989 int chansize, numchan;
1990
1991 /* hbm memory channel size */
1992 if (adev->flags & AMD_IS_APU)
1993 chansize = 64;
1994 else
1995 chansize = 128;
1996 if (adev->df.funcs &&
1997 adev->df.funcs->get_hbm_channel_number) {
1998 numchan = adev->df.funcs->get_hbm_channel_number(adev);
1999 adev->gmc.vram_width = numchan * chansize;
2000 }
2001 }
2002
2003 adev->gmc.vram_type = vram_type;
2004 adev->gmc.vram_vendor = vram_vendor;
2005 }
2006 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
2007 case IP_VERSION(9, 1, 0):
2008 case IP_VERSION(9, 2, 2):
2009 set_bit(AMDGPU_GFXHUB(0), adev->vmhubs_mask);
2010 set_bit(AMDGPU_MMHUB0(0), adev->vmhubs_mask);
2011
2012 if (adev->rev_id == 0x0 || adev->rev_id == 0x1) {
2013 amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48);
2014 } else {
2015 /* vm_size is 128TB + 512GB for legacy 3-level page support */
2016 amdgpu_vm_adjust_size(adev, 128 * 1024 + 512, 9, 2, 48);
2017 adev->gmc.translate_further =
2018 adev->vm_manager.num_level > 1;
2019 }
2020 break;
2021 case IP_VERSION(9, 0, 1):
2022 case IP_VERSION(9, 2, 1):
2023 case IP_VERSION(9, 4, 0):
2024 case IP_VERSION(9, 3, 0):
2025 case IP_VERSION(9, 4, 2):
2026 set_bit(AMDGPU_GFXHUB(0), adev->vmhubs_mask);
2027 set_bit(AMDGPU_MMHUB0(0), adev->vmhubs_mask);
2028
2029 /*
2030 * To fulfill 4-level page support,
2031 * vm size is 256TB (48bit), maximum size of Vega10,
2032 * block size 512 (9bit)
2033 */
2034
2035 amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48);
2036 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 2))
2037 adev->gmc.translate_further = adev->vm_manager.num_level > 1;
2038 break;
2039 case IP_VERSION(9, 4, 1):
2040 set_bit(AMDGPU_GFXHUB(0), adev->vmhubs_mask);
2041 set_bit(AMDGPU_MMHUB0(0), adev->vmhubs_mask);
2042 set_bit(AMDGPU_MMHUB1(0), adev->vmhubs_mask);
2043
2044 /* Keep the vm size same with Vega20 */
2045 amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48);
2046 adev->gmc.translate_further = adev->vm_manager.num_level > 1;
2047 break;
2048 case IP_VERSION(9, 4, 3):
2049 bitmap_set(adev->vmhubs_mask, AMDGPU_GFXHUB(0),
2050 NUM_XCC(adev->gfx.xcc_mask));
2051
2052 inst_mask <<= AMDGPU_MMHUB0(0);
2053 bitmap_or(adev->vmhubs_mask, adev->vmhubs_mask, &inst_mask, 32);
2054
2055 amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48);
2056 adev->gmc.translate_further = adev->vm_manager.num_level > 1;
2057 break;
2058 default:
2059 break;
2060 }
2061
2062 /* This interrupt is VMC page fault.*/
2063 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VMC, VMC_1_0__SRCID__VM_FAULT,
2064 &adev->gmc.vm_fault);
2065 if (r)
2066 return r;
2067
2068 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 1)) {
2069 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VMC1, VMC_1_0__SRCID__VM_FAULT,
2070 &adev->gmc.vm_fault);
2071 if (r)
2072 return r;
2073 }
2074
2075 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_UTCL2, UTCL2_1_0__SRCID__FAULT,
2076 &adev->gmc.vm_fault);
2077
2078 if (r)
2079 return r;
2080
2081 if (!amdgpu_sriov_vf(adev) &&
2082 !adev->gmc.xgmi.connected_to_cpu &&
2083 !adev->gmc.is_app_apu) {
2084 /* interrupt sent to DF. */
2085 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DF, 0,
2086 &adev->gmc.ecc_irq);
2087 if (r)
2088 return r;
2089 }
2090
2091 /* Set the internal MC address mask
2092 * This is the max address of the GPU's
2093 * internal address space.
2094 */
2095 adev->gmc.mc_mask = 0xffffffffffffULL; /* 48 bit MC */
2096
2097 dma_addr_bits = amdgpu_ip_version(adev, GC_HWIP, 0) >=
2098 IP_VERSION(9, 4, 2) ?
2099 48 :
2100 44;
2101 r = dma_set_mask_and_coherent(adev->dev, DMA_BIT_MASK(dma_addr_bits));
2102 if (r) {
2103 dev_warn(adev->dev, "amdgpu: No suitable DMA available.\n");
2104 return r;
2105 }
2106 adev->need_swiotlb = drm_need_swiotlb(dma_addr_bits);
2107
2108 r = gmc_v9_0_mc_init(adev);
2109 if (r)
2110 return r;
2111
2112 amdgpu_gmc_get_vbios_allocations(adev);
2113
2114 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 3)) {
2115 r = gmc_v9_0_init_mem_ranges(adev);
2116 if (r)
2117 return r;
2118 }
2119
2120 /* Memory manager */
2121 r = amdgpu_bo_init(adev);
2122 if (r)
2123 return r;
2124
2125 r = gmc_v9_0_gart_init(adev);
2126 if (r)
2127 return r;
2128
2129 /*
2130 * number of VMs
2131 * VMID 0 is reserved for System
2132 * amdgpu graphics/compute will use VMIDs 1..n-1
2133 * amdkfd will use VMIDs n..15
2134 *
2135 * The first KFD VMID is 8 for GPUs with graphics, 3 for
2136 * compute-only GPUs. On compute-only GPUs that leaves 2 VMIDs
2137 * for video processing.
2138 */
2139 adev->vm_manager.first_kfd_vmid =
2140 (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 1) ||
2141 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 2) ||
2142 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 3)) ?
2143 3 :
2144 8;
2145
2146 amdgpu_vm_manager_init(adev);
2147
2148 gmc_v9_0_save_registers(adev);
2149
2150 r = amdgpu_gmc_ras_sw_init(adev);
2151 if (r)
2152 return r;
2153
2154 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 3))
2155 amdgpu_gmc_sysfs_init(adev);
2156
2157 return 0;
2158}
2159
2160static int gmc_v9_0_sw_fini(void *handle)
2161{
2162 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2163
2164 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 3))
2165 amdgpu_gmc_sysfs_fini(adev);
2166
2167 amdgpu_gmc_ras_fini(adev);
2168 amdgpu_gem_force_release(adev);
2169 amdgpu_vm_manager_fini(adev);
2170 if (!adev->gmc.real_vram_size) {
2171 dev_info(adev->dev, "Put GART in system memory for APU free\n");
2172 amdgpu_gart_table_ram_free(adev);
2173 } else {
2174 amdgpu_gart_table_vram_free(adev);
2175 }
2176 amdgpu_bo_free_kernel(&adev->gmc.pdb0_bo, NULL, &adev->gmc.ptr_pdb0);
2177 amdgpu_bo_fini(adev);
2178
2179 adev->gmc.num_mem_partitions = 0;
2180 kfree(adev->gmc.mem_partitions);
2181
2182 return 0;
2183}
2184
2185static void gmc_v9_0_init_golden_registers(struct amdgpu_device *adev)
2186{
2187 switch (amdgpu_ip_version(adev, MMHUB_HWIP, 0)) {
2188 case IP_VERSION(9, 0, 0):
2189 if (amdgpu_sriov_vf(adev))
2190 break;
2191 fallthrough;
2192 case IP_VERSION(9, 4, 0):
2193 soc15_program_register_sequence(adev,
2194 golden_settings_mmhub_1_0_0,
2195 ARRAY_SIZE(golden_settings_mmhub_1_0_0));
2196 soc15_program_register_sequence(adev,
2197 golden_settings_athub_1_0_0,
2198 ARRAY_SIZE(golden_settings_athub_1_0_0));
2199 break;
2200 case IP_VERSION(9, 1, 0):
2201 case IP_VERSION(9, 2, 0):
2202 /* TODO for renoir */
2203 soc15_program_register_sequence(adev,
2204 golden_settings_athub_1_0_0,
2205 ARRAY_SIZE(golden_settings_athub_1_0_0));
2206 break;
2207 default:
2208 break;
2209 }
2210}
2211
2212/**
2213 * gmc_v9_0_restore_registers - restores regs
2214 *
2215 * @adev: amdgpu_device pointer
2216 *
2217 * This restores register values, saved at suspend.
2218 */
2219void gmc_v9_0_restore_registers(struct amdgpu_device *adev)
2220{
2221 if ((amdgpu_ip_version(adev, DCE_HWIP, 0) == IP_VERSION(1, 0, 0)) ||
2222 (amdgpu_ip_version(adev, DCE_HWIP, 0) == IP_VERSION(1, 0, 1))) {
2223 WREG32_SOC15(DCE, 0, mmDCHUBBUB_SDPIF_MMIO_CNTRL_0, adev->gmc.sdpif_register);
2224 WARN_ON(adev->gmc.sdpif_register !=
2225 RREG32_SOC15(DCE, 0, mmDCHUBBUB_SDPIF_MMIO_CNTRL_0));
2226 }
2227}
2228
2229/**
2230 * gmc_v9_0_gart_enable - gart enable
2231 *
2232 * @adev: amdgpu_device pointer
2233 */
2234static int gmc_v9_0_gart_enable(struct amdgpu_device *adev)
2235{
2236 int r;
2237
2238 if (adev->gmc.xgmi.connected_to_cpu)
2239 amdgpu_gmc_init_pdb0(adev);
2240
2241 if (adev->gart.bo == NULL) {
2242 dev_err(adev->dev, "No VRAM object for PCIE GART.\n");
2243 return -EINVAL;
2244 }
2245
2246 amdgpu_gtt_mgr_recover(&adev->mman.gtt_mgr);
2247
2248 if (!adev->in_s0ix) {
2249 r = adev->gfxhub.funcs->gart_enable(adev);
2250 if (r)
2251 return r;
2252 }
2253
2254 r = adev->mmhub.funcs->gart_enable(adev);
2255 if (r)
2256 return r;
2257
2258 DRM_INFO("PCIE GART of %uM enabled.\n",
2259 (unsigned int)(adev->gmc.gart_size >> 20));
2260 if (adev->gmc.pdb0_bo)
2261 DRM_INFO("PDB0 located at 0x%016llX\n",
2262 (unsigned long long)amdgpu_bo_gpu_offset(adev->gmc.pdb0_bo));
2263 DRM_INFO("PTB located at 0x%016llX\n",
2264 (unsigned long long)amdgpu_bo_gpu_offset(adev->gart.bo));
2265
2266 return 0;
2267}
2268
2269static int gmc_v9_0_hw_init(void *handle)
2270{
2271 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2272 bool value;
2273 int i, r;
2274
2275 adev->gmc.flush_pasid_uses_kiq = true;
2276
2277 /* Vega20+XGMI caches PTEs in TC and TLB. Add a heavy-weight TLB flush
2278 * (type 2), which flushes both. Due to a race condition with
2279 * concurrent memory accesses using the same TLB cache line, we still
2280 * need a second TLB flush after this.
2281 */
2282 adev->gmc.flush_tlb_needs_extra_type_2 =
2283 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 0) &&
2284 adev->gmc.xgmi.num_physical_nodes;
2285 /*
2286 * TODO: This workaround is badly documented and had a buggy
2287 * implementation. We should probably verify what we do here.
2288 */
2289 adev->gmc.flush_tlb_needs_extra_type_0 =
2290 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 3) &&
2291 adev->rev_id == 0;
2292
2293 /* The sequence of these two function calls matters.*/
2294 gmc_v9_0_init_golden_registers(adev);
2295
2296 if (adev->mode_info.num_crtc) {
2297 /* Lockout access through VGA aperture*/
2298 WREG32_FIELD15(DCE, 0, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1);
2299 /* disable VGA render */
2300 WREG32_FIELD15(DCE, 0, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0);
2301 }
2302
2303 if (adev->mmhub.funcs->update_power_gating)
2304 adev->mmhub.funcs->update_power_gating(adev, true);
2305
2306 adev->hdp.funcs->init_registers(adev);
2307
2308 /* After HDP is initialized, flush HDP.*/
2309 adev->hdp.funcs->flush_hdp(adev, NULL);
2310
2311 if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS)
2312 value = false;
2313 else
2314 value = true;
2315
2316 if (!amdgpu_sriov_vf(adev)) {
2317 if (!adev->in_s0ix)
2318 adev->gfxhub.funcs->set_fault_enable_default(adev, value);
2319 adev->mmhub.funcs->set_fault_enable_default(adev, value);
2320 }
2321 for_each_set_bit(i, adev->vmhubs_mask, AMDGPU_MAX_VMHUBS) {
2322 if (adev->in_s0ix && (i == AMDGPU_GFXHUB(0)))
2323 continue;
2324 gmc_v9_0_flush_gpu_tlb(adev, 0, i, 0);
2325 }
2326
2327 if (adev->umc.funcs && adev->umc.funcs->init_registers)
2328 adev->umc.funcs->init_registers(adev);
2329
2330 r = gmc_v9_0_gart_enable(adev);
2331 if (r)
2332 return r;
2333
2334 if (amdgpu_emu_mode == 1)
2335 return amdgpu_gmc_vram_checking(adev);
2336
2337 return 0;
2338}
2339
2340/**
2341 * gmc_v9_0_gart_disable - gart disable
2342 *
2343 * @adev: amdgpu_device pointer
2344 *
2345 * This disables all VM page table.
2346 */
2347static void gmc_v9_0_gart_disable(struct amdgpu_device *adev)
2348{
2349 if (!adev->in_s0ix)
2350 adev->gfxhub.funcs->gart_disable(adev);
2351 adev->mmhub.funcs->gart_disable(adev);
2352}
2353
2354static int gmc_v9_0_hw_fini(void *handle)
2355{
2356 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2357
2358 gmc_v9_0_gart_disable(adev);
2359
2360 if (amdgpu_sriov_vf(adev)) {
2361 /* full access mode, so don't touch any GMC register */
2362 DRM_DEBUG("For SRIOV client, shouldn't do anything.\n");
2363 return 0;
2364 }
2365
2366 /*
2367 * Pair the operations did in gmc_v9_0_hw_init and thus maintain
2368 * a correct cached state for GMC. Otherwise, the "gate" again
2369 * operation on S3 resuming will fail due to wrong cached state.
2370 */
2371 if (adev->mmhub.funcs->update_power_gating)
2372 adev->mmhub.funcs->update_power_gating(adev, false);
2373
2374 amdgpu_irq_put(adev, &adev->gmc.vm_fault, 0);
2375
2376 if (adev->gmc.ecc_irq.funcs &&
2377 amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__UMC))
2378 amdgpu_irq_put(adev, &adev->gmc.ecc_irq, 0);
2379
2380 return 0;
2381}
2382
2383static int gmc_v9_0_suspend(void *handle)
2384{
2385 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2386
2387 return gmc_v9_0_hw_fini(adev);
2388}
2389
2390static int gmc_v9_0_resume(void *handle)
2391{
2392 int r;
2393 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2394
2395 r = gmc_v9_0_hw_init(adev);
2396 if (r)
2397 return r;
2398
2399 amdgpu_vmid_reset_all(adev);
2400
2401 return 0;
2402}
2403
2404static bool gmc_v9_0_is_idle(void *handle)
2405{
2406 /* MC is always ready in GMC v9.*/
2407 return true;
2408}
2409
2410static int gmc_v9_0_wait_for_idle(void *handle)
2411{
2412 /* There is no need to wait for MC idle in GMC v9.*/
2413 return 0;
2414}
2415
2416static int gmc_v9_0_soft_reset(void *handle)
2417{
2418 /* XXX for emulation.*/
2419 return 0;
2420}
2421
2422static int gmc_v9_0_set_clockgating_state(void *handle,
2423 enum amd_clockgating_state state)
2424{
2425 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2426
2427 adev->mmhub.funcs->set_clockgating(adev, state);
2428
2429 athub_v1_0_set_clockgating(adev, state);
2430
2431 return 0;
2432}
2433
2434static void gmc_v9_0_get_clockgating_state(void *handle, u64 *flags)
2435{
2436 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2437
2438 adev->mmhub.funcs->get_clockgating(adev, flags);
2439
2440 athub_v1_0_get_clockgating(adev, flags);
2441}
2442
2443static int gmc_v9_0_set_powergating_state(void *handle,
2444 enum amd_powergating_state state)
2445{
2446 return 0;
2447}
2448
2449const struct amd_ip_funcs gmc_v9_0_ip_funcs = {
2450 .name = "gmc_v9_0",
2451 .early_init = gmc_v9_0_early_init,
2452 .late_init = gmc_v9_0_late_init,
2453 .sw_init = gmc_v9_0_sw_init,
2454 .sw_fini = gmc_v9_0_sw_fini,
2455 .hw_init = gmc_v9_0_hw_init,
2456 .hw_fini = gmc_v9_0_hw_fini,
2457 .suspend = gmc_v9_0_suspend,
2458 .resume = gmc_v9_0_resume,
2459 .is_idle = gmc_v9_0_is_idle,
2460 .wait_for_idle = gmc_v9_0_wait_for_idle,
2461 .soft_reset = gmc_v9_0_soft_reset,
2462 .set_clockgating_state = gmc_v9_0_set_clockgating_state,
2463 .set_powergating_state = gmc_v9_0_set_powergating_state,
2464 .get_clockgating_state = gmc_v9_0_get_clockgating_state,
2465};
2466
2467const struct amdgpu_ip_block_version gmc_v9_0_ip_block = {
2468 .type = AMD_IP_BLOCK_TYPE_GMC,
2469 .major = 9,
2470 .minor = 0,
2471 .rev = 0,
2472 .funcs = &gmc_v9_0_ip_funcs,
2473};