1/*
   2 * Copyright 2016 Advanced Micro Devices, Inc.
   3 *
   4 * Permission is hereby granted, free of charge, to any person obtaining a
   5 * copy of this software and associated documentation files (the "Software"),
   6 * to deal in the Software without restriction, including without limitation
   7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8 * and/or sell copies of the Software, and to permit persons to whom the
   9 * Software is furnished to do so, subject to the following conditions:
  10 *
  11 * The above copyright notice and this permission notice shall be included in
  12 * all copies or substantial portions of the Software.
  13 *
  14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20 * OTHER DEALINGS IN THE SOFTWARE.
  21 *
  22 */
  23
  24#include <linux/firmware.h>
  25#include <linux/pci.h>
  26
  27#include <drm/drm_cache.h>
  28
  29#include "amdgpu.h"
  30#include "gmc_v9_0.h"
  31#include "amdgpu_atomfirmware.h"
  32#include "amdgpu_gem.h"
  33
  34#include "hdp/hdp_4_0_offset.h"
  35#include "hdp/hdp_4_0_sh_mask.h"
  36#include "gc/gc_9_0_sh_mask.h"
  37#include "dce/dce_12_0_offset.h"
  38#include "dce/dce_12_0_sh_mask.h"
  39#include "vega10_enum.h"
  40#include "mmhub/mmhub_1_0_offset.h"
  41#include "athub/athub_1_0_sh_mask.h"
  42#include "athub/athub_1_0_offset.h"
  43#include "oss/osssys_4_0_offset.h"
  44
  45#include "soc15.h"
  46#include "soc15d.h"
  47#include "soc15_common.h"
  48#include "umc/umc_6_0_sh_mask.h"
  49
  50#include "gfxhub_v1_0.h"
  51#include "mmhub_v1_0.h"
  52#include "athub_v1_0.h"
  53#include "gfxhub_v1_1.h"
  54#include "mmhub_v9_4.h"
 
  55#include "umc_v6_1.h"
  56#include "umc_v6_0.h"
 
  57
  58#include "ivsrcid/vmc/irqsrcs_vmc_1_0.h"
  59
  60#include "amdgpu_ras.h"
  61#include "amdgpu_xgmi.h"
  62
  63/* add these here since we already include dce12 headers and these are for DCN */
  64#define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION                                                          0x055d
  65#define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX                                                 2
  66#define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH__SHIFT                                        0x0
  67#define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT__SHIFT                                       0x10
  68#define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH_MASK                                          0x00003FFFL
  69#define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT_MASK                                         0x3FFF0000L
 
 
  70
  71static const u32 golden_settings_vega10_hdp[] =
  72{
  73	0xf64, 0x0fffffff, 0x00000000,
  74	0xf65, 0x0fffffff, 0x00000000,
  75	0xf66, 0x0fffffff, 0x00000000,
  76	0xf67, 0x0fffffff, 0x00000000,
  77	0xf68, 0x0fffffff, 0x00000000,
  78	0xf6a, 0x0fffffff, 0x00000000,
  79	0xf6b, 0x0fffffff, 0x00000000,
  80	0xf6c, 0x0fffffff, 0x00000000,
  81	0xf6d, 0x0fffffff, 0x00000000,
  82	0xf6e, 0x0fffffff, 0x00000000,
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
  83};
  84
  85static const struct soc15_reg_golden golden_settings_mmhub_1_0_0[] =
  86{
  87	SOC15_REG_GOLDEN_VALUE(MMHUB, 0, mmDAGB1_WRCLI2, 0x00000007, 0xfe5fe0fa),
  88	SOC15_REG_GOLDEN_VALUE(MMHUB, 0, mmMMEA1_DRAM_WR_CLI2GRP_MAP0, 0x00000030, 0x55555565)
  89};
  90
  91static const struct soc15_reg_golden golden_settings_athub_1_0_0[] =
  92{
  93	SOC15_REG_GOLDEN_VALUE(ATHUB, 0, mmRPB_ARB_CNTL, 0x0000ff00, 0x00000800),
  94	SOC15_REG_GOLDEN_VALUE(ATHUB, 0, mmRPB_ARB_CNTL2, 0x00ff00ff, 0x00080008)
  95};
  96
  97static const uint32_t ecc_umc_mcumc_ctrl_addrs[] = {
  98	(0x000143c0 + 0x00000000),
  99	(0x000143c0 + 0x00000800),
 100	(0x000143c0 + 0x00001000),
 101	(0x000143c0 + 0x00001800),
 102	(0x000543c0 + 0x00000000),
 103	(0x000543c0 + 0x00000800),
 104	(0x000543c0 + 0x00001000),
 105	(0x000543c0 + 0x00001800),
 106	(0x000943c0 + 0x00000000),
 107	(0x000943c0 + 0x00000800),
 108	(0x000943c0 + 0x00001000),
 109	(0x000943c0 + 0x00001800),
 110	(0x000d43c0 + 0x00000000),
 111	(0x000d43c0 + 0x00000800),
 112	(0x000d43c0 + 0x00001000),
 113	(0x000d43c0 + 0x00001800),
 114	(0x001143c0 + 0x00000000),
 115	(0x001143c0 + 0x00000800),
 116	(0x001143c0 + 0x00001000),
 117	(0x001143c0 + 0x00001800),
 118	(0x001543c0 + 0x00000000),
 119	(0x001543c0 + 0x00000800),
 120	(0x001543c0 + 0x00001000),
 121	(0x001543c0 + 0x00001800),
 122	(0x001943c0 + 0x00000000),
 123	(0x001943c0 + 0x00000800),
 124	(0x001943c0 + 0x00001000),
 125	(0x001943c0 + 0x00001800),
 126	(0x001d43c0 + 0x00000000),
 127	(0x001d43c0 + 0x00000800),
 128	(0x001d43c0 + 0x00001000),
 129	(0x001d43c0 + 0x00001800),
 130};
 131
 132static const uint32_t ecc_umc_mcumc_ctrl_mask_addrs[] = {
 133	(0x000143e0 + 0x00000000),
 134	(0x000143e0 + 0x00000800),
 135	(0x000143e0 + 0x00001000),
 136	(0x000143e0 + 0x00001800),
 137	(0x000543e0 + 0x00000000),
 138	(0x000543e0 + 0x00000800),
 139	(0x000543e0 + 0x00001000),
 140	(0x000543e0 + 0x00001800),
 141	(0x000943e0 + 0x00000000),
 142	(0x000943e0 + 0x00000800),
 143	(0x000943e0 + 0x00001000),
 144	(0x000943e0 + 0x00001800),
 145	(0x000d43e0 + 0x00000000),
 146	(0x000d43e0 + 0x00000800),
 147	(0x000d43e0 + 0x00001000),
 148	(0x000d43e0 + 0x00001800),
 149	(0x001143e0 + 0x00000000),
 150	(0x001143e0 + 0x00000800),
 151	(0x001143e0 + 0x00001000),
 152	(0x001143e0 + 0x00001800),
 153	(0x001543e0 + 0x00000000),
 154	(0x001543e0 + 0x00000800),
 155	(0x001543e0 + 0x00001000),
 156	(0x001543e0 + 0x00001800),
 157	(0x001943e0 + 0x00000000),
 158	(0x001943e0 + 0x00000800),
 159	(0x001943e0 + 0x00001000),
 160	(0x001943e0 + 0x00001800),
 161	(0x001d43e0 + 0x00000000),
 162	(0x001d43e0 + 0x00000800),
 163	(0x001d43e0 + 0x00001000),
 164	(0x001d43e0 + 0x00001800),
 165};
 166
 167static const uint32_t ecc_umc_mcumc_status_addrs[] = {
 168	(0x000143c2 + 0x00000000),
 169	(0x000143c2 + 0x00000800),
 170	(0x000143c2 + 0x00001000),
 171	(0x000143c2 + 0x00001800),
 172	(0x000543c2 + 0x00000000),
 173	(0x000543c2 + 0x00000800),
 174	(0x000543c2 + 0x00001000),
 175	(0x000543c2 + 0x00001800),
 176	(0x000943c2 + 0x00000000),
 177	(0x000943c2 + 0x00000800),
 178	(0x000943c2 + 0x00001000),
 179	(0x000943c2 + 0x00001800),
 180	(0x000d43c2 + 0x00000000),
 181	(0x000d43c2 + 0x00000800),
 182	(0x000d43c2 + 0x00001000),
 183	(0x000d43c2 + 0x00001800),
 184	(0x001143c2 + 0x00000000),
 185	(0x001143c2 + 0x00000800),
 186	(0x001143c2 + 0x00001000),
 187	(0x001143c2 + 0x00001800),
 188	(0x001543c2 + 0x00000000),
 189	(0x001543c2 + 0x00000800),
 190	(0x001543c2 + 0x00001000),
 191	(0x001543c2 + 0x00001800),
 192	(0x001943c2 + 0x00000000),
 193	(0x001943c2 + 0x00000800),
 194	(0x001943c2 + 0x00001000),
 195	(0x001943c2 + 0x00001800),
 196	(0x001d43c2 + 0x00000000),
 197	(0x001d43c2 + 0x00000800),
 198	(0x001d43c2 + 0x00001000),
 199	(0x001d43c2 + 0x00001800),
 200};
 201
 202static int gmc_v9_0_ecc_interrupt_state(struct amdgpu_device *adev,
 203		struct amdgpu_irq_src *src,
 204		unsigned type,
 205		enum amdgpu_interrupt_state state)
 206{
 207	u32 bits, i, tmp, reg;
 208
 209	/* Devices newer then VEGA10/12 shall have these programming
 210	     sequences performed by PSP BL */
 211	if (adev->asic_type >= CHIP_VEGA20)
 212		return 0;
 213
 214	bits = 0x7f;
 215
 216	switch (state) {
 217	case AMDGPU_IRQ_STATE_DISABLE:
 218		for (i = 0; i < ARRAY_SIZE(ecc_umc_mcumc_ctrl_addrs); i++) {
 219			reg = ecc_umc_mcumc_ctrl_addrs[i];
 220			tmp = RREG32(reg);
 221			tmp &= ~bits;
 222			WREG32(reg, tmp);
 223		}
 224		for (i = 0; i < ARRAY_SIZE(ecc_umc_mcumc_ctrl_mask_addrs); i++) {
 225			reg = ecc_umc_mcumc_ctrl_mask_addrs[i];
 226			tmp = RREG32(reg);
 227			tmp &= ~bits;
 228			WREG32(reg, tmp);
 229		}
 230		break;
 231	case AMDGPU_IRQ_STATE_ENABLE:
 232		for (i = 0; i < ARRAY_SIZE(ecc_umc_mcumc_ctrl_addrs); i++) {
 233			reg = ecc_umc_mcumc_ctrl_addrs[i];
 234			tmp = RREG32(reg);
 235			tmp |= bits;
 236			WREG32(reg, tmp);
 237		}
 238		for (i = 0; i < ARRAY_SIZE(ecc_umc_mcumc_ctrl_mask_addrs); i++) {
 239			reg = ecc_umc_mcumc_ctrl_mask_addrs[i];
 240			tmp = RREG32(reg);
 241			tmp |= bits;
 242			WREG32(reg, tmp);
 243		}
 244		break;
 245	default:
 246		break;
 247	}
 248
 249	return 0;
 250}
 251
 252static int gmc_v9_0_vm_fault_interrupt_state(struct amdgpu_device *adev,
 253					struct amdgpu_irq_src *src,
 254					unsigned type,
 255					enum amdgpu_interrupt_state state)
 256{
 257	struct amdgpu_vmhub *hub;
 258	u32 tmp, reg, bits, i, j;
 259
 260	bits = VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
 261		VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
 262		VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
 263		VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
 264		VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
 265		VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
 266		VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK;
 267
 268	switch (state) {
 269	case AMDGPU_IRQ_STATE_DISABLE:
 270		for (j = 0; j < adev->num_vmhubs; j++) {
 271			hub = &adev->vmhub[j];
 272			for (i = 0; i < 16; i++) {
 273				reg = hub->vm_context0_cntl + i;
 274				tmp = RREG32(reg);
 275				tmp &= ~bits;
 276				WREG32(reg, tmp);
 277			}
 278		}
 279		break;
 280	case AMDGPU_IRQ_STATE_ENABLE:
 281		for (j = 0; j < adev->num_vmhubs; j++) {
 282			hub = &adev->vmhub[j];
 283			for (i = 0; i < 16; i++) {
 284				reg = hub->vm_context0_cntl + i;
 285				tmp = RREG32(reg);
 286				tmp |= bits;
 287				WREG32(reg, tmp);
 288			}
 289		}
 
 290	default:
 291		break;
 292	}
 293
 294	return 0;
 295}
 296
 297static int gmc_v9_0_process_interrupt(struct amdgpu_device *adev,
 298				struct amdgpu_irq_src *source,
 299				struct amdgpu_iv_entry *entry)
 300{
 301	struct amdgpu_vmhub *hub;
 302	bool retry_fault = !!(entry->src_data[1] & 0x80);
 303	uint32_t status = 0;
 
 
 
 
 304	u64 addr;
 305	char hub_name[10];
 306
 307	addr = (u64)entry->src_data[0] << 12;
 308	addr |= ((u64)entry->src_data[1] & 0xf) << 44;
 309
 310	if (retry_fault && amdgpu_gmc_filter_faults(adev, addr, entry->pasid,
 311						    entry->timestamp))
 312		return 1; /* This also prevents sending it to KFD */
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 313
 314	if (entry->client_id == SOC15_IH_CLIENTID_VMC) {
 315		snprintf(hub_name, sizeof(hub_name), "mmhub0");
 316		hub = &adev->vmhub[AMDGPU_MMHUB_0];
 317	} else if (entry->client_id == SOC15_IH_CLIENTID_VMC1) {
 318		snprintf(hub_name, sizeof(hub_name), "mmhub1");
 319		hub = &adev->vmhub[AMDGPU_MMHUB_1];
 320	} else {
 321		snprintf(hub_name, sizeof(hub_name), "gfxhub0");
 322		hub = &adev->vmhub[AMDGPU_GFXHUB_0];
 323	}
 324
 325	/* If it's the first fault for this address, process it normally */
 326	if (retry_fault && !in_interrupt() &&
 327	    amdgpu_vm_handle_fault(adev, entry->pasid, addr))
 328		return 1; /* This also prevents sending it to KFD */
 329
 330	if (!amdgpu_sriov_vf(adev)) {
 331		/*
 332		 * Issue a dummy read to wait for the status register to
 333		 * be updated to avoid reading an incorrect value due to
 334		 * the new fast GRBM interface.
 335		 */
 336		if (entry->vmid_src == AMDGPU_GFXHUB_0)
 337			RREG32(hub->vm_l2_pro_fault_status);
 
 
 338
 339		status = RREG32(hub->vm_l2_pro_fault_status);
 340		WREG32_P(hub->vm_l2_pro_fault_cntl, 1, ~1);
 341	}
 342
 343	if (printk_ratelimit()) {
 344		struct amdgpu_task_info task_info;
 345
 346		memset(&task_info, 0, sizeof(struct amdgpu_task_info));
 347		amdgpu_vm_get_task_info(adev, entry->pasid, &task_info);
 348
 349		dev_err(adev->dev,
 350			"[%s] %s page fault (src_id:%u ring:%u vmid:%u "
 351			"pasid:%u, for process %s pid %d thread %s pid %d)\n",
 352			hub_name, retry_fault ? "retry" : "no-retry",
 353			entry->src_id, entry->ring_id, entry->vmid,
 354			entry->pasid, task_info.process_name, task_info.tgid,
 355			task_info.task_name, task_info.pid);
 356		dev_err(adev->dev, "  in page starting at address 0x%016llx from client %d\n",
 357			addr, entry->client_id);
 358		if (!amdgpu_sriov_vf(adev)) {
 359			dev_err(adev->dev,
 360				"VM_L2_PROTECTION_FAULT_STATUS:0x%08X\n",
 361				status);
 362			dev_err(adev->dev, "\t Faulty UTCL2 client ID: 0x%lx\n",
 363				REG_GET_FIELD(status,
 364				VM_L2_PROTECTION_FAULT_STATUS, CID));
 365			dev_err(adev->dev, "\t MORE_FAULTS: 0x%lx\n",
 366				REG_GET_FIELD(status,
 367				VM_L2_PROTECTION_FAULT_STATUS, MORE_FAULTS));
 368			dev_err(adev->dev, "\t WALKER_ERROR: 0x%lx\n",
 369				REG_GET_FIELD(status,
 370				VM_L2_PROTECTION_FAULT_STATUS, WALKER_ERROR));
 371			dev_err(adev->dev, "\t PERMISSION_FAULTS: 0x%lx\n",
 372				REG_GET_FIELD(status,
 373				VM_L2_PROTECTION_FAULT_STATUS, PERMISSION_FAULTS));
 374			dev_err(adev->dev, "\t MAPPING_ERROR: 0x%lx\n",
 375				REG_GET_FIELD(status,
 376				VM_L2_PROTECTION_FAULT_STATUS, MAPPING_ERROR));
 377			dev_err(adev->dev, "\t RW: 0x%lx\n",
 378				REG_GET_FIELD(status,
 379				VM_L2_PROTECTION_FAULT_STATUS, RW));
 380
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 381		}
 
 
 382	}
 383
 
 
 
 
 
 
 
 
 
 
 
 
 384	return 0;
 385}
 386
 387static const struct amdgpu_irq_src_funcs gmc_v9_0_irq_funcs = {
 388	.set = gmc_v9_0_vm_fault_interrupt_state,
 389	.process = gmc_v9_0_process_interrupt,
 390};
 391
 392
 393static const struct amdgpu_irq_src_funcs gmc_v9_0_ecc_funcs = {
 394	.set = gmc_v9_0_ecc_interrupt_state,
 395	.process = amdgpu_umc_process_ecc_irq,
 396};
 397
 398static void gmc_v9_0_set_irq_funcs(struct amdgpu_device *adev)
 399{
 400	adev->gmc.vm_fault.num_types = 1;
 401	adev->gmc.vm_fault.funcs = &gmc_v9_0_irq_funcs;
 402
 403	if (!amdgpu_sriov_vf(adev)) {
 
 404		adev->gmc.ecc_irq.num_types = 1;
 405		adev->gmc.ecc_irq.funcs = &gmc_v9_0_ecc_funcs;
 406	}
 407}
 408
 409static uint32_t gmc_v9_0_get_invalidate_req(unsigned int vmid,
 410					uint32_t flush_type)
 411{
 412	u32 req = 0;
 413
 414	req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ,
 415			    PER_VMID_INVALIDATE_REQ, 1 << vmid);
 416	req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, FLUSH_TYPE, flush_type);
 417	req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PTES, 1);
 418	req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE0, 1);
 419	req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE1, 1);
 420	req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE2, 1);
 421	req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L1_PTES, 1);
 422	req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ,
 423			    CLEAR_PROTECTION_FAULT_STATUS_ADDR,	0);
 424
 425	return req;
 426}
 427
 428/**
 429 * gmc_v9_0_use_invalidate_semaphore - judge whether to use semaphore
 430 *
 431 * @adev: amdgpu_device pointer
 432 * @vmhub: vmhub type
 433 *
 434 */
 435static bool gmc_v9_0_use_invalidate_semaphore(struct amdgpu_device *adev,
 436				       uint32_t vmhub)
 437{
 
 
 
 438	return ((vmhub == AMDGPU_MMHUB_0 ||
 439		 vmhub == AMDGPU_MMHUB_1) &&
 440		(!amdgpu_sriov_vf(adev)) &&
 441		(!(!(adev->apu_flags & AMD_APU_IS_RAVEN2) &&
 442		   (adev->apu_flags & AMD_APU_IS_PICASSO))));
 443}
 444
 445static bool gmc_v9_0_get_atc_vmid_pasid_mapping_info(struct amdgpu_device *adev,
 446					uint8_t vmid, uint16_t *p_pasid)
 447{
 448	uint32_t value;
 449
 450	value = RREG32(SOC15_REG_OFFSET(ATHUB, 0, mmATC_VMID0_PASID_MAPPING)
 451		     + vmid);
 452	*p_pasid = value & ATC_VMID0_PASID_MAPPING__PASID_MASK;
 453
 454	return !!(value & ATC_VMID0_PASID_MAPPING__VALID_MASK);
 455}
 456
 457/*
 458 * GART
 459 * VMID 0 is the physical GPU addresses as used by the kernel.
 460 * VMIDs 1-15 are used for userspace clients and are handled
 461 * by the amdgpu vm/hsa code.
 462 */
 463
 464/**
 465 * gmc_v9_0_flush_gpu_tlb - tlb flush with certain type
 466 *
 467 * @adev: amdgpu_device pointer
 468 * @vmid: vm instance to flush
 
 469 * @flush_type: the flush type
 470 *
 471 * Flush the TLB for the requested page table using certain type.
 472 */
 473static void gmc_v9_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid,
 474					uint32_t vmhub, uint32_t flush_type)
 475{
 476	bool use_semaphore = gmc_v9_0_use_invalidate_semaphore(adev, vmhub);
 477	const unsigned eng = 17;
 478	u32 j, inv_req, inv_req2, tmp;
 479	struct amdgpu_vmhub *hub;
 480
 481	BUG_ON(vmhub >= adev->num_vmhubs);
 482
 483	hub = &adev->vmhub[vmhub];
 484	if (adev->gmc.xgmi.num_physical_nodes &&
 485	    adev->asic_type == CHIP_VEGA20) {
 486		/* Vega20+XGMI caches PTEs in TC and TLB. Add a
 487		 * heavy-weight TLB flush (type 2), which flushes
 488		 * both. Due to a race condition with concurrent
 489		 * memory accesses using the same TLB cache line, we
 490		 * still need a second TLB flush after this.
 491		 */
 492		inv_req = gmc_v9_0_get_invalidate_req(vmid, 2);
 493		inv_req2 = gmc_v9_0_get_invalidate_req(vmid, flush_type);
 494	} else {
 495		inv_req = gmc_v9_0_get_invalidate_req(vmid, flush_type);
 496		inv_req2 = 0;
 497	}
 498
 499	/* This is necessary for a HW workaround under SRIOV as well
 500	 * as GFXOFF under bare metal
 501	 */
 502	if (adev->gfx.kiq.ring.sched.ready &&
 503			(amdgpu_sriov_runtime(adev) || !amdgpu_sriov_vf(adev)) &&
 504			!adev->in_gpu_reset) {
 505		uint32_t req = hub->vm_inv_eng0_req + hub->eng_distance * eng;
 506		uint32_t ack = hub->vm_inv_eng0_ack + hub->eng_distance * eng;
 507
 508		amdgpu_virt_kiq_reg_write_reg_wait(adev, req, ack, inv_req,
 509						   1 << vmid);
 
 510		return;
 511	}
 512
 513	spin_lock(&adev->gmc.invalidate_lock);
 514
 515	/*
 516	 * It may lose gpuvm invalidate acknowldege state across power-gating
 517	 * off cycle, add semaphore acquire before invalidation and semaphore
 518	 * release after invalidation to avoid entering power gated state
 519	 * to WA the Issue
 520	 */
 521
 522	/* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */
 523	if (use_semaphore) {
 524		for (j = 0; j < adev->usec_timeout; j++) {
 525			/* a read return value of 1 means semaphore acuqire */
 526			tmp = RREG32_NO_KIQ(hub->vm_inv_eng0_sem +
 527					    hub->eng_distance * eng);
 528			if (tmp & 0x1)
 529				break;
 530			udelay(1);
 531		}
 532
 533		if (j >= adev->usec_timeout)
 534			DRM_ERROR("Timeout waiting for sem acquire in VM flush!\n");
 535	}
 536
 537	do {
 538		WREG32_NO_KIQ(hub->vm_inv_eng0_req +
 539			      hub->eng_distance * eng, inv_req);
 540
 541		/*
 542		 * Issue a dummy read to wait for the ACK register to
 543		 * be cleared to avoid a false ACK due to the new fast
 544		 * GRBM interface.
 545		 */
 546		if (vmhub == AMDGPU_GFXHUB_0)
 
 547			RREG32_NO_KIQ(hub->vm_inv_eng0_req +
 548				      hub->eng_distance * eng);
 549
 550		for (j = 0; j < adev->usec_timeout; j++) {
 551			tmp = RREG32_NO_KIQ(hub->vm_inv_eng0_ack +
 552					    hub->eng_distance * eng);
 553			if (tmp & (1 << vmid))
 554				break;
 555			udelay(1);
 556		}
 557
 558		inv_req = inv_req2;
 559		inv_req2 = 0;
 560	} while (inv_req);
 561
 562	/* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */
 563	if (use_semaphore)
 564		/*
 565		 * add semaphore release after invalidation,
 566		 * write with 0 means semaphore release
 567		 */
 568		WREG32_NO_KIQ(hub->vm_inv_eng0_sem +
 569			      hub->eng_distance * eng, 0);
 570
 571	spin_unlock(&adev->gmc.invalidate_lock);
 572
 573	if (j < adev->usec_timeout)
 574		return;
 575
 576	DRM_ERROR("Timeout waiting for VM flush ACK!\n");
 577}
 578
 579/**
 580 * gmc_v9_0_flush_gpu_tlb_pasid - tlb flush via pasid
 581 *
 582 * @adev: amdgpu_device pointer
 583 * @pasid: pasid to be flush
 
 
 584 *
 585 * Flush the TLB for the requested pasid.
 586 */
 587static int gmc_v9_0_flush_gpu_tlb_pasid(struct amdgpu_device *adev,
 588					uint16_t pasid, uint32_t flush_type,
 589					bool all_hub)
 590{
 591	int vmid, i;
 592	signed long r;
 593	uint32_t seq;
 594	uint16_t queried_pasid;
 595	bool ret;
 596	struct amdgpu_ring *ring = &adev->gfx.kiq.ring;
 597	struct amdgpu_kiq *kiq = &adev->gfx.kiq;
 598
 599	if (adev->in_gpu_reset)
 600		return -EIO;
 601
 602	if (ring->sched.ready) {
 603		/* Vega20+XGMI caches PTEs in TC and TLB. Add a
 604		 * heavy-weight TLB flush (type 2), which flushes
 605		 * both. Due to a race condition with concurrent
 606		 * memory accesses using the same TLB cache line, we
 607		 * still need a second TLB flush after this.
 608		 */
 609		bool vega20_xgmi_wa = (adev->gmc.xgmi.num_physical_nodes &&
 610				       adev->asic_type == CHIP_VEGA20);
 611		/* 2 dwords flush + 8 dwords fence */
 612		unsigned int ndw = kiq->pmf->invalidate_tlbs_size + 8;
 613
 614		if (vega20_xgmi_wa)
 615			ndw += kiq->pmf->invalidate_tlbs_size;
 616
 617		spin_lock(&adev->gfx.kiq.ring_lock);
 618		/* 2 dwords flush + 8 dwords fence */
 619		amdgpu_ring_alloc(ring, ndw);
 620		if (vega20_xgmi_wa)
 621			kiq->pmf->kiq_invalidate_tlbs(ring,
 622						      pasid, 2, all_hub);
 623		kiq->pmf->kiq_invalidate_tlbs(ring,
 624					pasid, flush_type, all_hub);
 625		r = amdgpu_fence_emit_polling(ring, &seq, MAX_KIQ_REG_WAIT);
 626		if (r) {
 627			amdgpu_ring_undo(ring);
 628			spin_unlock(&adev->gfx.kiq.ring_lock);
 
 629			return -ETIME;
 630		}
 631
 632		amdgpu_ring_commit(ring);
 633		spin_unlock(&adev->gfx.kiq.ring_lock);
 634		r = amdgpu_fence_wait_polling(ring, seq, adev->usec_timeout);
 635		if (r < 1) {
 636			DRM_ERROR("wait for kiq fence error: %ld.\n", r);
 
 637			return -ETIME;
 638		}
 639
 640		return 0;
 641	}
 642
 643	for (vmid = 1; vmid < 16; vmid++) {
 644
 645		ret = gmc_v9_0_get_atc_vmid_pasid_mapping_info(adev, vmid,
 646				&queried_pasid);
 647		if (ret && queried_pasid == pasid) {
 648			if (all_hub) {
 649				for (i = 0; i < adev->num_vmhubs; i++)
 650					gmc_v9_0_flush_gpu_tlb(adev, vmid,
 651							i, flush_type);
 652			} else {
 653				gmc_v9_0_flush_gpu_tlb(adev, vmid,
 654						AMDGPU_GFXHUB_0, flush_type);
 655			}
 656			break;
 657		}
 658	}
 659
 660	return 0;
 661
 662}
 663
 664static uint64_t gmc_v9_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring,
 665					    unsigned vmid, uint64_t pd_addr)
 666{
 667	bool use_semaphore = gmc_v9_0_use_invalidate_semaphore(ring->adev, ring->funcs->vmhub);
 668	struct amdgpu_device *adev = ring->adev;
 669	struct amdgpu_vmhub *hub = &adev->vmhub[ring->funcs->vmhub];
 670	uint32_t req = gmc_v9_0_get_invalidate_req(vmid, 0);
 671	unsigned eng = ring->vm_inv_eng;
 672
 673	/*
 674	 * It may lose gpuvm invalidate acknowldege state across power-gating
 675	 * off cycle, add semaphore acquire before invalidation and semaphore
 676	 * release after invalidation to avoid entering power gated state
 677	 * to WA the Issue
 678	 */
 679
 680	/* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */
 681	if (use_semaphore)
 682		/* a read return value of 1 means semaphore acuqire */
 683		amdgpu_ring_emit_reg_wait(ring,
 684					  hub->vm_inv_eng0_sem +
 685					  hub->eng_distance * eng, 0x1, 0x1);
 686
 687	amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_lo32 +
 688			      (hub->ctx_addr_distance * vmid),
 689			      lower_32_bits(pd_addr));
 690
 691	amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_hi32 +
 692			      (hub->ctx_addr_distance * vmid),
 693			      upper_32_bits(pd_addr));
 694
 695	amdgpu_ring_emit_reg_write_reg_wait(ring, hub->vm_inv_eng0_req +
 696					    hub->eng_distance * eng,
 697					    hub->vm_inv_eng0_ack +
 698					    hub->eng_distance * eng,
 699					    req, 1 << vmid);
 700
 701	/* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */
 702	if (use_semaphore)
 703		/*
 704		 * add semaphore release after invalidation,
 705		 * write with 0 means semaphore release
 706		 */
 707		amdgpu_ring_emit_wreg(ring, hub->vm_inv_eng0_sem +
 708				      hub->eng_distance * eng, 0);
 709
 710	return pd_addr;
 711}
 712
 713static void gmc_v9_0_emit_pasid_mapping(struct amdgpu_ring *ring, unsigned vmid,
 714					unsigned pasid)
 715{
 716	struct amdgpu_device *adev = ring->adev;
 717	uint32_t reg;
 718
 719	/* Do nothing because there's no lut register for mmhub1. */
 720	if (ring->funcs->vmhub == AMDGPU_MMHUB_1)
 721		return;
 722
 723	if (ring->funcs->vmhub == AMDGPU_GFXHUB_0)
 724		reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT) + vmid;
 725	else
 726		reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT_MM) + vmid;
 727
 728	amdgpu_ring_emit_wreg(ring, reg, pasid);
 729}
 730
 731/*
 732 * PTE format on VEGA 10:
 733 * 63:59 reserved
 734 * 58:57 mtype
 735 * 56 F
 736 * 55 L
 737 * 54 P
 738 * 53 SW
 739 * 52 T
 740 * 50:48 reserved
 741 * 47:12 4k physical page base address
 742 * 11:7 fragment
 743 * 6 write
 744 * 5 read
 745 * 4 exe
 746 * 3 Z
 747 * 2 snooped
 748 * 1 system
 749 * 0 valid
 750 *
 751 * PDE format on VEGA 10:
 752 * 63:59 block fragment size
 753 * 58:55 reserved
 754 * 54 P
 755 * 53:48 reserved
 756 * 47:6 physical base address of PD or PTE
 757 * 5:3 reserved
 758 * 2 C
 759 * 1 system
 760 * 0 valid
 761 */
 762
 763static uint64_t gmc_v9_0_map_mtype(struct amdgpu_device *adev, uint32_t flags)
 764
 765{
 766	switch (flags) {
 767	case AMDGPU_VM_MTYPE_DEFAULT:
 768		return AMDGPU_PTE_MTYPE_VG10(MTYPE_NC);
 769	case AMDGPU_VM_MTYPE_NC:
 770		return AMDGPU_PTE_MTYPE_VG10(MTYPE_NC);
 771	case AMDGPU_VM_MTYPE_WC:
 772		return AMDGPU_PTE_MTYPE_VG10(MTYPE_WC);
 773	case AMDGPU_VM_MTYPE_RW:
 774		return AMDGPU_PTE_MTYPE_VG10(MTYPE_RW);
 775	case AMDGPU_VM_MTYPE_CC:
 776		return AMDGPU_PTE_MTYPE_VG10(MTYPE_CC);
 777	case AMDGPU_VM_MTYPE_UC:
 778		return AMDGPU_PTE_MTYPE_VG10(MTYPE_UC);
 779	default:
 780		return AMDGPU_PTE_MTYPE_VG10(MTYPE_NC);
 781	}
 782}
 783
 784static void gmc_v9_0_get_vm_pde(struct amdgpu_device *adev, int level,
 785				uint64_t *addr, uint64_t *flags)
 786{
 787	if (!(*flags & AMDGPU_PDE_PTE) && !(*flags & AMDGPU_PTE_SYSTEM))
 788		*addr = adev->vm_manager.vram_base_offset + *addr -
 789			adev->gmc.vram_start;
 790	BUG_ON(*addr & 0xFFFF00000000003FULL);
 791
 792	if (!adev->gmc.translate_further)
 793		return;
 794
 795	if (level == AMDGPU_VM_PDB1) {
 796		/* Set the block fragment size */
 797		if (!(*flags & AMDGPU_PDE_PTE))
 798			*flags |= AMDGPU_PDE_BFS(0x9);
 799
 800	} else if (level == AMDGPU_VM_PDB0) {
 801		if (*flags & AMDGPU_PDE_PTE)
 802			*flags &= ~AMDGPU_PDE_PTE;
 803		else
 804			*flags |= AMDGPU_PTE_TF;
 805	}
 806}
 807
 808static void gmc_v9_0_get_vm_pte(struct amdgpu_device *adev,
 809				struct amdgpu_bo_va_mapping *mapping,
 810				uint64_t *flags)
 811{
 812	*flags &= ~AMDGPU_PTE_EXECUTABLE;
 813	*flags |= mapping->flags & AMDGPU_PTE_EXECUTABLE;
 814
 815	*flags &= ~AMDGPU_PTE_MTYPE_VG10_MASK;
 816	*flags |= mapping->flags & AMDGPU_PTE_MTYPE_VG10_MASK;
 817
 818	if (mapping->flags & AMDGPU_PTE_PRT) {
 819		*flags |= AMDGPU_PTE_PRT;
 820		*flags &= ~AMDGPU_PTE_VALID;
 821	}
 822
 823	if (adev->asic_type == CHIP_ARCTURUS &&
 
 824	    !(*flags & AMDGPU_PTE_SYSTEM) &&
 825	    mapping->bo_va->is_xgmi)
 826		*flags |= AMDGPU_PTE_SNOOPED;
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 827}
 828
 829static const struct amdgpu_gmc_funcs gmc_v9_0_gmc_funcs = {
 830	.flush_gpu_tlb = gmc_v9_0_flush_gpu_tlb,
 831	.flush_gpu_tlb_pasid = gmc_v9_0_flush_gpu_tlb_pasid,
 832	.emit_flush_gpu_tlb = gmc_v9_0_emit_flush_gpu_tlb,
 833	.emit_pasid_mapping = gmc_v9_0_emit_pasid_mapping,
 834	.map_mtype = gmc_v9_0_map_mtype,
 835	.get_vm_pde = gmc_v9_0_get_vm_pde,
 836	.get_vm_pte = gmc_v9_0_get_vm_pte
 
 837};
 838
 839static void gmc_v9_0_set_gmc_funcs(struct amdgpu_device *adev)
 840{
 841	adev->gmc.gmc_funcs = &gmc_v9_0_gmc_funcs;
 842}
 843
 844static void gmc_v9_0_set_umc_funcs(struct amdgpu_device *adev)
 845{
 846	switch (adev->asic_type) {
 847	case CHIP_VEGA10:
 848		adev->umc.funcs = &umc_v6_0_funcs;
 849		break;
 850	case CHIP_VEGA20:
 851		adev->umc.max_ras_err_cnt_per_query = UMC_V6_1_TOTAL_CHANNEL_NUM;
 852		adev->umc.channel_inst_num = UMC_V6_1_CHANNEL_INSTANCE_NUM;
 853		adev->umc.umc_inst_num = UMC_V6_1_UMC_INSTANCE_NUM;
 854		adev->umc.channel_offs = UMC_V6_1_PER_CHANNEL_OFFSET_VG20;
 855		adev->umc.channel_idx_tbl = &umc_v6_1_channel_idx_tbl[0][0];
 856		adev->umc.funcs = &umc_v6_1_funcs;
 857		break;
 858	case CHIP_ARCTURUS:
 859		adev->umc.max_ras_err_cnt_per_query = UMC_V6_1_TOTAL_CHANNEL_NUM;
 860		adev->umc.channel_inst_num = UMC_V6_1_CHANNEL_INSTANCE_NUM;
 861		adev->umc.umc_inst_num = UMC_V6_1_UMC_INSTANCE_NUM;
 862		adev->umc.channel_offs = UMC_V6_1_PER_CHANNEL_OFFSET_ARCT;
 863		adev->umc.channel_idx_tbl = &umc_v6_1_channel_idx_tbl[0][0];
 864		adev->umc.funcs = &umc_v6_1_funcs;
 865		break;
 866	default:
 867		break;
 868	}
 869}
 870
 871static void gmc_v9_0_set_mmhub_funcs(struct amdgpu_device *adev)
 872{
 873	switch (adev->asic_type) {
 874	case CHIP_VEGA20:
 
 
 
 
 
 
 875		adev->mmhub.funcs = &mmhub_v1_0_funcs;
 876		break;
 
 
 
 
 
 
 
 
 
 877	case CHIP_ARCTURUS:
 878		adev->mmhub.funcs = &mmhub_v9_4_funcs;
 
 
 
 879		break;
 880	default:
 
 881		break;
 882	}
 883}
 884
 
 
 
 
 
 
 
 
 
 
 885static int gmc_v9_0_early_init(void *handle)
 886{
 887	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 888
 
 
 
 
 
 
 
 
 
 
 889	gmc_v9_0_set_gmc_funcs(adev);
 890	gmc_v9_0_set_irq_funcs(adev);
 891	gmc_v9_0_set_umc_funcs(adev);
 892	gmc_v9_0_set_mmhub_funcs(adev);
 
 
 
 893
 894	adev->gmc.shared_aperture_start = 0x2000000000000000ULL;
 895	adev->gmc.shared_aperture_end =
 896		adev->gmc.shared_aperture_start + (4ULL << 30) - 1;
 897	adev->gmc.private_aperture_start = 0x1000000000000000ULL;
 898	adev->gmc.private_aperture_end =
 899		adev->gmc.private_aperture_start + (4ULL << 30) - 1;
 900
 901	return 0;
 902}
 903
 904static bool gmc_v9_0_keep_stolen_memory(struct amdgpu_device *adev)
 905{
 906
 907	/*
 908	 * TODO:
 909	 * Currently there is a bug where some memory client outside
 910	 * of the driver writes to first 8M of VRAM on S3 resume,
 911	 * this overrides GART which by default gets placed in first 8M and
 912	 * causes VM_FAULTS once GTT is accessed.
 913	 * Keep the stolen memory reservation until the while this is not solved.
 914	 * Also check code in gmc_v9_0_get_vbios_fb_size and gmc_v9_0_late_init
 915	 */
 916	switch (adev->asic_type) {
 917	case CHIP_VEGA10:
 918	case CHIP_RAVEN:
 919	case CHIP_ARCTURUS:
 920	case CHIP_RENOIR:
 921		return true;
 922	case CHIP_VEGA12:
 923	case CHIP_VEGA20:
 924	default:
 925		return false;
 926	}
 927}
 928
 929static int gmc_v9_0_late_init(void *handle)
 930{
 931	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 932	int r;
 933
 934	if (!gmc_v9_0_keep_stolen_memory(adev))
 935		amdgpu_bo_late_init(adev);
 936
 937	r = amdgpu_gmc_allocate_vm_inv_eng(adev);
 938	if (r)
 939		return r;
 940	/* Check if ecc is available */
 
 
 
 
 941	if (!amdgpu_sriov_vf(adev) && (adev->asic_type == CHIP_VEGA10)) {
 942		r = amdgpu_atomfirmware_mem_ecc_supported(adev);
 943		if (!r) {
 944			DRM_INFO("ECC is not present.\n");
 945			if (adev->df.funcs->enable_ecc_force_par_wr_rmw)
 946				adev->df.funcs->enable_ecc_force_par_wr_rmw(adev, false);
 947		} else
 948			DRM_INFO("ECC is active.\n");
 949
 950		r = amdgpu_atomfirmware_sram_ecc_supported(adev);
 951		if (!r)
 952			DRM_INFO("SRAM ECC is not present.\n");
 953		else
 954			DRM_INFO("SRAM ECC is active.\n");
 955	}
 956
 957	if (adev->mmhub.funcs && adev->mmhub.funcs->reset_ras_error_count)
 958		adev->mmhub.funcs->reset_ras_error_count(adev);
 
 
 
 
 
 
 
 959
 960	r = amdgpu_gmc_ras_late_init(adev);
 961	if (r)
 962		return r;
 963
 964	return amdgpu_irq_get(adev, &adev->gmc.vm_fault, 0);
 965}
 966
 967static void gmc_v9_0_vram_gtt_location(struct amdgpu_device *adev,
 968					struct amdgpu_gmc *mc)
 969{
 970	u64 base = 0;
 971
 972	if (adev->asic_type == CHIP_ARCTURUS)
 973		base = mmhub_v9_4_get_fb_location(adev);
 974	else if (!amdgpu_sriov_vf(adev))
 975		base = mmhub_v1_0_get_fb_location(adev);
 976
 977	/* add the xgmi offset of the physical node */
 978	base += adev->gmc.xgmi.physical_node_id * adev->gmc.xgmi.node_segment_size;
 979	amdgpu_gmc_vram_location(adev, mc, base);
 980	amdgpu_gmc_gart_location(adev, mc);
 981	amdgpu_gmc_agp_location(adev, mc);
 
 
 
 
 982	/* base offset of vram pages */
 983	adev->vm_manager.vram_base_offset = gfxhub_v1_0_get_mc_fb_offset(adev);
 984
 985	/* XXX: add the xgmi offset of the physical node? */
 986	adev->vm_manager.vram_base_offset +=
 987		adev->gmc.xgmi.physical_node_id * adev->gmc.xgmi.node_segment_size;
 988}
 989
 990/**
 991 * gmc_v9_0_mc_init - initialize the memory controller driver params
 992 *
 993 * @adev: amdgpu_device pointer
 994 *
 995 * Look up the amount of vram, vram width, and decide how to place
 996 * vram and gart within the GPU's physical address space.
 997 * Returns 0 for success.
 998 */
 999static int gmc_v9_0_mc_init(struct amdgpu_device *adev)
1000{
1001	int r;
1002
1003	/* size in MB on si */
1004	adev->gmc.mc_vram_size =
1005		adev->nbio.funcs->get_memsize(adev) * 1024ULL * 1024ULL;
1006	adev->gmc.real_vram_size = adev->gmc.mc_vram_size;
1007
1008	if (!(adev->flags & AMD_IS_APU)) {
 
1009		r = amdgpu_device_resize_fb_bar(adev);
1010		if (r)
1011			return r;
1012	}
1013	adev->gmc.aper_base = pci_resource_start(adev->pdev, 0);
1014	adev->gmc.aper_size = pci_resource_len(adev->pdev, 0);
1015
1016#ifdef CONFIG_X86_64
1017	if (adev->flags & AMD_IS_APU) {
1018		adev->gmc.aper_base = gfxhub_v1_0_get_mc_fb_offset(adev);
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1019		adev->gmc.aper_size = adev->gmc.real_vram_size;
1020	}
 
1021#endif
1022	/* In case the PCI BAR is larger than the actual amount of vram */
1023	adev->gmc.visible_vram_size = adev->gmc.aper_size;
1024	if (adev->gmc.visible_vram_size > adev->gmc.real_vram_size)
1025		adev->gmc.visible_vram_size = adev->gmc.real_vram_size;
1026
1027	/* set the gart size */
1028	if (amdgpu_gart_size == -1) {
1029		switch (adev->asic_type) {
1030		case CHIP_VEGA10:  /* all engines support GPUVM */
1031		case CHIP_VEGA12:  /* all engines support GPUVM */
1032		case CHIP_VEGA20:
1033		case CHIP_ARCTURUS:
 
1034		default:
1035			adev->gmc.gart_size = 512ULL << 20;
1036			break;
1037		case CHIP_RAVEN:   /* DCE SG support */
1038		case CHIP_RENOIR:
1039			adev->gmc.gart_size = 1024ULL << 20;
1040			break;
1041		}
1042	} else {
1043		adev->gmc.gart_size = (u64)amdgpu_gart_size << 20;
1044	}
1045
 
 
1046	gmc_v9_0_vram_gtt_location(adev, &adev->gmc);
1047
1048	return 0;
1049}
1050
1051static int gmc_v9_0_gart_init(struct amdgpu_device *adev)
1052{
1053	int r;
1054
1055	if (adev->gart.bo) {
1056		WARN(1, "VEGA10 PCIE GART already initialized\n");
1057		return 0;
1058	}
 
 
 
 
 
 
 
 
 
1059	/* Initialize common gart structure */
1060	r = amdgpu_gart_init(adev);
1061	if (r)
1062		return r;
1063	adev->gart.table_size = adev->gart.num_gpu_pages * 8;
1064	adev->gart.gart_pte_flags = AMDGPU_PTE_MTYPE_VG10(MTYPE_UC) |
1065				 AMDGPU_PTE_EXECUTABLE;
1066	return amdgpu_gart_table_vram_alloc(adev);
1067}
1068
1069static unsigned gmc_v9_0_get_vbios_fb_size(struct amdgpu_device *adev)
1070{
1071	u32 d1vga_control;
1072	unsigned size;
1073
1074	/*
1075	 * TODO Remove once GART corruption is resolved
1076	 * Check related code in gmc_v9_0_sw_fini
1077	 * */
1078	if (gmc_v9_0_keep_stolen_memory(adev))
1079		return 9 * 1024 * 1024;
1080
1081	d1vga_control = RREG32_SOC15(DCE, 0, mmD1VGA_CONTROL);
1082	if (REG_GET_FIELD(d1vga_control, D1VGA_CONTROL, D1VGA_MODE_ENABLE)) {
1083		size = 9 * 1024 * 1024; /* reserve 8MB for vga emulator and 1 MB for FB */
1084	} else {
1085		u32 viewport;
1086
1087		switch (adev->asic_type) {
1088		case CHIP_RAVEN:
1089		case CHIP_RENOIR:
1090			viewport = RREG32_SOC15(DCE, 0, mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION);
1091			size = (REG_GET_FIELD(viewport,
1092					      HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_HEIGHT) *
1093				REG_GET_FIELD(viewport,
1094					      HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_WIDTH) *
1095				4);
1096			break;
1097		case CHIP_VEGA10:
1098		case CHIP_VEGA12:
1099		case CHIP_VEGA20:
1100		default:
1101			viewport = RREG32_SOC15(DCE, 0, mmSCL0_VIEWPORT_SIZE);
1102			size = (REG_GET_FIELD(viewport, SCL0_VIEWPORT_SIZE, VIEWPORT_HEIGHT) *
1103				REG_GET_FIELD(viewport, SCL0_VIEWPORT_SIZE, VIEWPORT_WIDTH) *
1104				4);
1105			break;
1106		}
1107	}
1108	/* return 0 if the pre-OS buffer uses up most of vram */
1109	if ((adev->gmc.real_vram_size - size) < (8 * 1024 * 1024))
1110		return 0;
1111
1112	return size;
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1113}
1114
1115static int gmc_v9_0_sw_init(void *handle)
1116{
1117	int r, vram_width = 0, vram_type = 0, vram_vendor = 0;
1118	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1119
1120	gfxhub_v1_0_init(adev);
1121	if (adev->asic_type == CHIP_ARCTURUS)
1122		mmhub_v9_4_init(adev);
1123	else
1124		mmhub_v1_0_init(adev);
1125
1126	spin_lock_init(&adev->gmc.invalidate_lock);
1127
1128	r = amdgpu_atomfirmware_get_vram_info(adev,
1129		&vram_width, &vram_type, &vram_vendor);
1130	if (amdgpu_sriov_vf(adev))
1131		/* For Vega10 SR-IOV, vram_width can't be read from ATOM as RAVEN,
1132		 * and DF related registers is not readable, seems hardcord is the
1133		 * only way to set the correct vram_width
1134		 */
1135		adev->gmc.vram_width = 2048;
1136	else if (amdgpu_emu_mode != 1)
1137		adev->gmc.vram_width = vram_width;
1138
1139	if (!adev->gmc.vram_width) {
1140		int chansize, numchan;
1141
1142		/* hbm memory channel size */
1143		if (adev->flags & AMD_IS_APU)
1144			chansize = 64;
1145		else
1146			chansize = 128;
1147
1148		numchan = adev->df.funcs->get_hbm_channel_number(adev);
1149		adev->gmc.vram_width = numchan * chansize;
1150	}
1151
1152	adev->gmc.vram_type = vram_type;
1153	adev->gmc.vram_vendor = vram_vendor;
1154	switch (adev->asic_type) {
1155	case CHIP_RAVEN:
1156		adev->num_vmhubs = 2;
1157
1158		if (adev->rev_id == 0x0 || adev->rev_id == 0x1) {
1159			amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48);
1160		} else {
1161			/* vm_size is 128TB + 512GB for legacy 3-level page support */
1162			amdgpu_vm_adjust_size(adev, 128 * 1024 + 512, 9, 2, 48);
1163			adev->gmc.translate_further =
1164				adev->vm_manager.num_level > 1;
1165		}
1166		break;
1167	case CHIP_VEGA10:
1168	case CHIP_VEGA12:
1169	case CHIP_VEGA20:
1170	case CHIP_RENOIR:
 
1171		adev->num_vmhubs = 2;
1172
1173
1174		/*
1175		 * To fulfill 4-level page support,
1176		 * vm size is 256TB (48bit), maximum size of Vega10,
1177		 * block size 512 (9bit)
1178		 */
1179		/* sriov restrict max_pfn below AMDGPU_GMC_HOLE */
1180		if (amdgpu_sriov_vf(adev))
1181			amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 47);
1182		else
1183			amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48);
1184		break;
1185	case CHIP_ARCTURUS:
1186		adev->num_vmhubs = 3;
1187
1188		/* Keep the vm size same with Vega20 */
1189		amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48);
1190		break;
1191	default:
1192		break;
1193	}
1194
1195	/* This interrupt is VMC page fault.*/
1196	r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VMC, VMC_1_0__SRCID__VM_FAULT,
1197				&adev->gmc.vm_fault);
1198	if (r)
1199		return r;
1200
1201	if (adev->asic_type == CHIP_ARCTURUS) {
1202		r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VMC1, VMC_1_0__SRCID__VM_FAULT,
1203					&adev->gmc.vm_fault);
1204		if (r)
1205			return r;
1206	}
1207
1208	r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_UTCL2, UTCL2_1_0__SRCID__FAULT,
1209				&adev->gmc.vm_fault);
1210
1211	if (r)
1212		return r;
1213
1214	if (!amdgpu_sriov_vf(adev)) {
 
1215		/* interrupt sent to DF. */
1216		r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DF, 0,
1217				      &adev->gmc.ecc_irq);
1218		if (r)
1219			return r;
1220	}
1221
1222	/* Set the internal MC address mask
1223	 * This is the max address of the GPU's
1224	 * internal address space.
1225	 */
1226	adev->gmc.mc_mask = 0xffffffffffffULL; /* 48 bit MC */
1227
1228	r = dma_set_mask_and_coherent(adev->dev, DMA_BIT_MASK(44));
1229	if (r) {
1230		printk(KERN_WARNING "amdgpu: No suitable DMA available.\n");
1231		return r;
1232	}
1233	adev->need_swiotlb = drm_need_swiotlb(44);
1234
1235	if (adev->gmc.xgmi.supported) {
1236		r = gfxhub_v1_1_get_xgmi_info(adev);
1237		if (r)
1238			return r;
1239	}
1240
1241	r = gmc_v9_0_mc_init(adev);
1242	if (r)
1243		return r;
1244
1245	adev->gmc.stolen_size = gmc_v9_0_get_vbios_fb_size(adev);
1246
1247	/* Memory manager */
1248	r = amdgpu_bo_init(adev);
1249	if (r)
1250		return r;
1251
1252	r = gmc_v9_0_gart_init(adev);
1253	if (r)
1254		return r;
1255
1256	/*
1257	 * number of VMs
1258	 * VMID 0 is reserved for System
1259	 * amdgpu graphics/compute will use VMIDs 1..n-1
1260	 * amdkfd will use VMIDs n..15
1261	 *
1262	 * The first KFD VMID is 8 for GPUs with graphics, 3 for
1263	 * compute-only GPUs. On compute-only GPUs that leaves 2 VMIDs
1264	 * for video processing.
1265	 */
1266	adev->vm_manager.first_kfd_vmid =
1267		adev->asic_type == CHIP_ARCTURUS ? 3 : 8;
 
1268
1269	amdgpu_vm_manager_init(adev);
1270
 
 
1271	return 0;
1272}
1273
1274static int gmc_v9_0_sw_fini(void *handle)
1275{
1276	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1277	void *stolen_vga_buf;
1278
1279	amdgpu_gmc_ras_fini(adev);
1280	amdgpu_gem_force_release(adev);
1281	amdgpu_vm_manager_fini(adev);
1282
1283	if (gmc_v9_0_keep_stolen_memory(adev))
1284		amdgpu_bo_free_kernel(&adev->stolen_vga_memory, NULL, &stolen_vga_buf);
1285
1286	amdgpu_gart_table_vram_free(adev);
 
1287	amdgpu_bo_fini(adev);
1288	amdgpu_gart_fini(adev);
1289
1290	return 0;
1291}
1292
1293static void gmc_v9_0_init_golden_registers(struct amdgpu_device *adev)
1294{
1295
1296	switch (adev->asic_type) {
1297	case CHIP_VEGA10:
1298		if (amdgpu_sriov_vf(adev))
1299			break;
1300		fallthrough;
1301	case CHIP_VEGA20:
1302		soc15_program_register_sequence(adev,
1303						golden_settings_mmhub_1_0_0,
1304						ARRAY_SIZE(golden_settings_mmhub_1_0_0));
1305		soc15_program_register_sequence(adev,
1306						golden_settings_athub_1_0_0,
1307						ARRAY_SIZE(golden_settings_athub_1_0_0));
1308		break;
1309	case CHIP_VEGA12:
1310		break;
1311	case CHIP_RAVEN:
1312		/* TODO for renoir */
1313		soc15_program_register_sequence(adev,
1314						golden_settings_athub_1_0_0,
1315						ARRAY_SIZE(golden_settings_athub_1_0_0));
1316		break;
1317	default:
1318		break;
1319	}
1320}
1321
1322/**
1323 * gmc_v9_0_restore_registers - restores regs
1324 *
1325 * @adev: amdgpu_device pointer
1326 *
1327 * This restores register values, saved at suspend.
1328 */
1329static void gmc_v9_0_restore_registers(struct amdgpu_device *adev)
1330{
1331	if (adev->asic_type == CHIP_RAVEN)
1332		WREG32(mmDCHUBBUB_SDPIF_MMIO_CNTRL_0, adev->gmc.sdpif_register);
 
 
 
1333}
1334
1335/**
1336 * gmc_v9_0_gart_enable - gart enable
1337 *
1338 * @adev: amdgpu_device pointer
1339 */
1340static int gmc_v9_0_gart_enable(struct amdgpu_device *adev)
1341{
1342	int r;
1343
 
 
 
1344	if (adev->gart.bo == NULL) {
1345		dev_err(adev->dev, "No VRAM object for PCIE GART.\n");
1346		return -EINVAL;
1347	}
 
1348	r = amdgpu_gart_table_vram_pin(adev);
1349	if (r)
1350		return r;
1351
1352	r = gfxhub_v1_0_gart_enable(adev);
1353	if (r)
1354		return r;
1355
1356	if (adev->asic_type == CHIP_ARCTURUS)
1357		r = mmhub_v9_4_gart_enable(adev);
1358	else
1359		r = mmhub_v1_0_gart_enable(adev);
1360	if (r)
1361		return r;
1362
1363	DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
1364		 (unsigned)(adev->gmc.gart_size >> 20),
1365		 (unsigned long long)amdgpu_bo_gpu_offset(adev->gart.bo));
 
 
 
 
 
1366	adev->gart.ready = true;
1367	return 0;
1368}
1369
1370static int gmc_v9_0_hw_init(void *handle)
1371{
1372	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1373	bool value;
1374	int r, i;
1375	u32 tmp;
1376
1377	/* The sequence of these two function calls matters.*/
1378	gmc_v9_0_init_golden_registers(adev);
1379
1380	if (adev->mode_info.num_crtc) {
1381		if (adev->asic_type != CHIP_ARCTURUS) {
1382			/* Lockout access through VGA aperture*/
1383			WREG32_FIELD15(DCE, 0, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1);
1384
1385			/* disable VGA render */
1386			WREG32_FIELD15(DCE, 0, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0);
1387		}
1388	}
1389
1390	amdgpu_device_program_register_sequence(adev,
1391						golden_settings_vega10_hdp,
1392						ARRAY_SIZE(golden_settings_vega10_hdp));
1393
1394	switch (adev->asic_type) {
1395	case CHIP_RAVEN:
1396		/* TODO for renoir */
1397		mmhub_v1_0_update_power_gating(adev, true);
1398		break;
1399	case CHIP_ARCTURUS:
1400		WREG32_FIELD15(HDP, 0, HDP_MMHUB_CNTL, HDP_MMHUB_GCC, 1);
1401		break;
1402	default:
1403		break;
1404	}
1405
1406	WREG32_FIELD15(HDP, 0, HDP_MISC_CNTL, FLUSH_INVALIDATE_CACHE, 1);
 
1407
1408	tmp = RREG32_SOC15(HDP, 0, mmHDP_HOST_PATH_CNTL);
1409	WREG32_SOC15(HDP, 0, mmHDP_HOST_PATH_CNTL, tmp);
1410
1411	WREG32_SOC15(HDP, 0, mmHDP_NONSURFACE_BASE, (adev->gmc.vram_start >> 8));
1412	WREG32_SOC15(HDP, 0, mmHDP_NONSURFACE_BASE_HI, (adev->gmc.vram_start >> 40));
1413
1414	/* After HDP is initialized, flush HDP.*/
1415	adev->nbio.funcs->hdp_flush(adev, NULL);
1416
1417	if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS)
1418		value = false;
1419	else
1420		value = true;
1421
1422	if (!amdgpu_sriov_vf(adev)) {
1423		gfxhub_v1_0_set_fault_enable_default(adev, value);
1424		if (adev->asic_type == CHIP_ARCTURUS)
1425			mmhub_v9_4_set_fault_enable_default(adev, value);
1426		else
1427			mmhub_v1_0_set_fault_enable_default(adev, value);
1428	}
1429	for (i = 0; i < adev->num_vmhubs; ++i)
1430		gmc_v9_0_flush_gpu_tlb(adev, 0, i, 0);
1431
1432	if (adev->umc.funcs && adev->umc.funcs->init_registers)
1433		adev->umc.funcs->init_registers(adev);
1434
1435	r = gmc_v9_0_gart_enable(adev);
1436
1437	return r;
1438}
1439
1440/**
1441 * gmc_v9_0_save_registers - saves regs
1442 *
1443 * @adev: amdgpu_device pointer
1444 *
1445 * This saves potential register values that should be
1446 * restored upon resume
1447 */
1448static void gmc_v9_0_save_registers(struct amdgpu_device *adev)
1449{
1450	if (adev->asic_type == CHIP_RAVEN)
1451		adev->gmc.sdpif_register = RREG32(mmDCHUBBUB_SDPIF_MMIO_CNTRL_0);
1452}
1453
1454/**
1455 * gmc_v9_0_gart_disable - gart disable
1456 *
1457 * @adev: amdgpu_device pointer
1458 *
1459 * This disables all VM page table.
1460 */
1461static void gmc_v9_0_gart_disable(struct amdgpu_device *adev)
1462{
1463	gfxhub_v1_0_gart_disable(adev);
1464	if (adev->asic_type == CHIP_ARCTURUS)
1465		mmhub_v9_4_gart_disable(adev);
1466	else
1467		mmhub_v1_0_gart_disable(adev);
1468	amdgpu_gart_table_vram_unpin(adev);
1469}
1470
1471static int gmc_v9_0_hw_fini(void *handle)
1472{
1473	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1474
 
 
1475	if (amdgpu_sriov_vf(adev)) {
1476		/* full access mode, so don't touch any GMC register */
1477		DRM_DEBUG("For SRIOV client, shouldn't do anything.\n");
1478		return 0;
1479	}
1480
1481	amdgpu_irq_put(adev, &adev->gmc.ecc_irq, 0);
1482	amdgpu_irq_put(adev, &adev->gmc.vm_fault, 0);
1483	gmc_v9_0_gart_disable(adev);
1484
1485	return 0;
1486}
1487
1488static int gmc_v9_0_suspend(void *handle)
1489{
1490	int r;
1491	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1492
1493	r = gmc_v9_0_hw_fini(adev);
1494	if (r)
1495		return r;
1496
1497	gmc_v9_0_save_registers(adev);
1498
1499	return 0;
1500}
1501
1502static int gmc_v9_0_resume(void *handle)
1503{
1504	int r;
1505	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1506
1507	gmc_v9_0_restore_registers(adev);
1508	r = gmc_v9_0_hw_init(adev);
1509	if (r)
1510		return r;
1511
1512	amdgpu_vmid_reset_all(adev);
1513
1514	return 0;
1515}
1516
1517static bool gmc_v9_0_is_idle(void *handle)
1518{
1519	/* MC is always ready in GMC v9.*/
1520	return true;
1521}
1522
1523static int gmc_v9_0_wait_for_idle(void *handle)
1524{
1525	/* There is no need to wait for MC idle in GMC v9.*/
1526	return 0;
1527}
1528
1529static int gmc_v9_0_soft_reset(void *handle)
1530{
1531	/* XXX for emulation.*/
1532	return 0;
1533}
1534
1535static int gmc_v9_0_set_clockgating_state(void *handle,
1536					enum amd_clockgating_state state)
1537{
1538	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1539
1540	if (adev->asic_type == CHIP_ARCTURUS)
1541		mmhub_v9_4_set_clockgating(adev, state);
1542	else
1543		mmhub_v1_0_set_clockgating(adev, state);
1544
1545	athub_v1_0_set_clockgating(adev, state);
1546
1547	return 0;
1548}
1549
1550static void gmc_v9_0_get_clockgating_state(void *handle, u32 *flags)
1551{
1552	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1553
1554	if (adev->asic_type == CHIP_ARCTURUS)
1555		mmhub_v9_4_get_clockgating(adev, flags);
1556	else
1557		mmhub_v1_0_get_clockgating(adev, flags);
1558
1559	athub_v1_0_get_clockgating(adev, flags);
1560}
1561
1562static int gmc_v9_0_set_powergating_state(void *handle,
1563					enum amd_powergating_state state)
1564{
1565	return 0;
1566}
1567
1568const struct amd_ip_funcs gmc_v9_0_ip_funcs = {
1569	.name = "gmc_v9_0",
1570	.early_init = gmc_v9_0_early_init,
1571	.late_init = gmc_v9_0_late_init,
1572	.sw_init = gmc_v9_0_sw_init,
1573	.sw_fini = gmc_v9_0_sw_fini,
1574	.hw_init = gmc_v9_0_hw_init,
1575	.hw_fini = gmc_v9_0_hw_fini,
1576	.suspend = gmc_v9_0_suspend,
1577	.resume = gmc_v9_0_resume,
1578	.is_idle = gmc_v9_0_is_idle,
1579	.wait_for_idle = gmc_v9_0_wait_for_idle,
1580	.soft_reset = gmc_v9_0_soft_reset,
1581	.set_clockgating_state = gmc_v9_0_set_clockgating_state,
1582	.set_powergating_state = gmc_v9_0_set_powergating_state,
1583	.get_clockgating_state = gmc_v9_0_get_clockgating_state,
1584};
1585
1586const struct amdgpu_ip_block_version gmc_v9_0_ip_block =
1587{
1588	.type = AMD_IP_BLOCK_TYPE_GMC,
1589	.major = 9,
1590	.minor = 0,
1591	.rev = 0,
1592	.funcs = &gmc_v9_0_ip_funcs,
1593};