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1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Root interrupt controller for the BCM2836 (Raspberry Pi 2).
4 *
5 * Copyright 2015 Broadcom
6 */
7
8#include <linux/cpu.h>
9#include <linux/of_address.h>
10#include <linux/of_irq.h>
11#include <linux/irqchip.h>
12#include <linux/irqdomain.h>
13#include <linux/irqchip/irq-bcm2836.h>
14
15#include <asm/exception.h>
16
17struct bcm2836_arm_irqchip_intc {
18 struct irq_domain *domain;
19 void __iomem *base;
20};
21
22static struct bcm2836_arm_irqchip_intc intc __read_mostly;
23
24static void bcm2836_arm_irqchip_mask_per_cpu_irq(unsigned int reg_offset,
25 unsigned int bit,
26 int cpu)
27{
28 void __iomem *reg = intc.base + reg_offset + 4 * cpu;
29
30 writel(readl(reg) & ~BIT(bit), reg);
31}
32
33static void bcm2836_arm_irqchip_unmask_per_cpu_irq(unsigned int reg_offset,
34 unsigned int bit,
35 int cpu)
36{
37 void __iomem *reg = intc.base + reg_offset + 4 * cpu;
38
39 writel(readl(reg) | BIT(bit), reg);
40}
41
42static void bcm2836_arm_irqchip_mask_timer_irq(struct irq_data *d)
43{
44 bcm2836_arm_irqchip_mask_per_cpu_irq(LOCAL_TIMER_INT_CONTROL0,
45 d->hwirq - LOCAL_IRQ_CNTPSIRQ,
46 smp_processor_id());
47}
48
49static void bcm2836_arm_irqchip_unmask_timer_irq(struct irq_data *d)
50{
51 bcm2836_arm_irqchip_unmask_per_cpu_irq(LOCAL_TIMER_INT_CONTROL0,
52 d->hwirq - LOCAL_IRQ_CNTPSIRQ,
53 smp_processor_id());
54}
55
56static struct irq_chip bcm2836_arm_irqchip_timer = {
57 .name = "bcm2836-timer",
58 .irq_mask = bcm2836_arm_irqchip_mask_timer_irq,
59 .irq_unmask = bcm2836_arm_irqchip_unmask_timer_irq,
60};
61
62static void bcm2836_arm_irqchip_mask_pmu_irq(struct irq_data *d)
63{
64 writel(1 << smp_processor_id(), intc.base + LOCAL_PM_ROUTING_CLR);
65}
66
67static void bcm2836_arm_irqchip_unmask_pmu_irq(struct irq_data *d)
68{
69 writel(1 << smp_processor_id(), intc.base + LOCAL_PM_ROUTING_SET);
70}
71
72static struct irq_chip bcm2836_arm_irqchip_pmu = {
73 .name = "bcm2836-pmu",
74 .irq_mask = bcm2836_arm_irqchip_mask_pmu_irq,
75 .irq_unmask = bcm2836_arm_irqchip_unmask_pmu_irq,
76};
77
78static void bcm2836_arm_irqchip_mask_gpu_irq(struct irq_data *d)
79{
80}
81
82static void bcm2836_arm_irqchip_unmask_gpu_irq(struct irq_data *d)
83{
84}
85
86static struct irq_chip bcm2836_arm_irqchip_gpu = {
87 .name = "bcm2836-gpu",
88 .irq_mask = bcm2836_arm_irqchip_mask_gpu_irq,
89 .irq_unmask = bcm2836_arm_irqchip_unmask_gpu_irq,
90};
91
92static int bcm2836_map(struct irq_domain *d, unsigned int irq,
93 irq_hw_number_t hw)
94{
95 struct irq_chip *chip;
96
97 switch (hw) {
98 case LOCAL_IRQ_CNTPSIRQ:
99 case LOCAL_IRQ_CNTPNSIRQ:
100 case LOCAL_IRQ_CNTHPIRQ:
101 case LOCAL_IRQ_CNTVIRQ:
102 chip = &bcm2836_arm_irqchip_timer;
103 break;
104 case LOCAL_IRQ_GPU_FAST:
105 chip = &bcm2836_arm_irqchip_gpu;
106 break;
107 case LOCAL_IRQ_PMU_FAST:
108 chip = &bcm2836_arm_irqchip_pmu;
109 break;
110 default:
111 pr_warn_once("Unexpected hw irq: %lu\n", hw);
112 return -EINVAL;
113 }
114
115 irq_set_percpu_devid(irq);
116 irq_domain_set_info(d, irq, hw, chip, d->host_data,
117 handle_percpu_devid_irq, NULL, NULL);
118 irq_set_status_flags(irq, IRQ_NOAUTOEN);
119
120 return 0;
121}
122
123static void
124__exception_irq_entry bcm2836_arm_irqchip_handle_irq(struct pt_regs *regs)
125{
126 int cpu = smp_processor_id();
127 u32 stat;
128
129 stat = readl_relaxed(intc.base + LOCAL_IRQ_PENDING0 + 4 * cpu);
130 if (stat & BIT(LOCAL_IRQ_MAILBOX0)) {
131#ifdef CONFIG_SMP
132 void __iomem *mailbox0 = (intc.base +
133 LOCAL_MAILBOX0_CLR0 + 16 * cpu);
134 u32 mbox_val = readl(mailbox0);
135 u32 ipi = ffs(mbox_val) - 1;
136
137 writel(1 << ipi, mailbox0);
138 handle_IPI(ipi, regs);
139#endif
140 } else if (stat) {
141 u32 hwirq = ffs(stat) - 1;
142
143 handle_domain_irq(intc.domain, hwirq, regs);
144 }
145}
146
147#ifdef CONFIG_SMP
148static void bcm2836_arm_irqchip_send_ipi(const struct cpumask *mask,
149 unsigned int ipi)
150{
151 int cpu;
152 void __iomem *mailbox0_base = intc.base + LOCAL_MAILBOX0_SET0;
153
154 /*
155 * Ensure that stores to normal memory are visible to the
156 * other CPUs before issuing the IPI.
157 */
158 smp_wmb();
159
160 for_each_cpu(cpu, mask) {
161 writel(1 << ipi, mailbox0_base + 16 * cpu);
162 }
163}
164
165static int bcm2836_cpu_starting(unsigned int cpu)
166{
167 bcm2836_arm_irqchip_unmask_per_cpu_irq(LOCAL_MAILBOX_INT_CONTROL0, 0,
168 cpu);
169 return 0;
170}
171
172static int bcm2836_cpu_dying(unsigned int cpu)
173{
174 bcm2836_arm_irqchip_mask_per_cpu_irq(LOCAL_MAILBOX_INT_CONTROL0, 0,
175 cpu);
176 return 0;
177}
178#endif
179
180static const struct irq_domain_ops bcm2836_arm_irqchip_intc_ops = {
181 .xlate = irq_domain_xlate_onetwocell,
182 .map = bcm2836_map,
183};
184
185static void
186bcm2836_arm_irqchip_smp_init(void)
187{
188#ifdef CONFIG_SMP
189 /* Unmask IPIs to the boot CPU. */
190 cpuhp_setup_state(CPUHP_AP_IRQ_BCM2836_STARTING,
191 "irqchip/bcm2836:starting", bcm2836_cpu_starting,
192 bcm2836_cpu_dying);
193
194 set_smp_cross_call(bcm2836_arm_irqchip_send_ipi);
195#endif
196}
197
198/*
199 * The LOCAL_IRQ_CNT* timer firings are based off of the external
200 * oscillator with some scaling. The firmware sets up CNTFRQ to
201 * report 19.2Mhz, but doesn't set up the scaling registers.
202 */
203static void bcm2835_init_local_timer_frequency(void)
204{
205 /*
206 * Set the timer to source from the 19.2Mhz crystal clock (bit
207 * 8 unset), and only increment by 1 instead of 2 (bit 9
208 * unset).
209 */
210 writel(0, intc.base + LOCAL_CONTROL);
211
212 /*
213 * Set the timer prescaler to 1:1 (timer freq = input freq *
214 * 2**31 / prescaler)
215 */
216 writel(0x80000000, intc.base + LOCAL_PRESCALER);
217}
218
219static int __init bcm2836_arm_irqchip_l1_intc_of_init(struct device_node *node,
220 struct device_node *parent)
221{
222 intc.base = of_iomap(node, 0);
223 if (!intc.base) {
224 panic("%pOF: unable to map local interrupt registers\n", node);
225 }
226
227 bcm2835_init_local_timer_frequency();
228
229 intc.domain = irq_domain_add_linear(node, LAST_IRQ + 1,
230 &bcm2836_arm_irqchip_intc_ops,
231 NULL);
232 if (!intc.domain)
233 panic("%pOF: unable to create IRQ domain\n", node);
234
235 bcm2836_arm_irqchip_smp_init();
236
237 set_handle_irq(bcm2836_arm_irqchip_handle_irq);
238 return 0;
239}
240
241IRQCHIP_DECLARE(bcm2836_arm_irqchip_l1_intc, "brcm,bcm2836-l1-intc",
242 bcm2836_arm_irqchip_l1_intc_of_init);
1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Root interrupt controller for the BCM2836 (Raspberry Pi 2).
4 *
5 * Copyright 2015 Broadcom
6 */
7
8#include <linux/cpu.h>
9#include <linux/of_address.h>
10#include <linux/of_irq.h>
11#include <linux/irqchip.h>
12#include <linux/irqdomain.h>
13#include <linux/irqchip/chained_irq.h>
14#include <linux/irqchip/irq-bcm2836.h>
15
16#include <asm/exception.h>
17
18struct bcm2836_arm_irqchip_intc {
19 struct irq_domain *domain;
20 void __iomem *base;
21};
22
23static struct bcm2836_arm_irqchip_intc intc __read_mostly;
24
25static void bcm2836_arm_irqchip_mask_per_cpu_irq(unsigned int reg_offset,
26 unsigned int bit,
27 int cpu)
28{
29 void __iomem *reg = intc.base + reg_offset + 4 * cpu;
30
31 writel(readl(reg) & ~BIT(bit), reg);
32}
33
34static void bcm2836_arm_irqchip_unmask_per_cpu_irq(unsigned int reg_offset,
35 unsigned int bit,
36 int cpu)
37{
38 void __iomem *reg = intc.base + reg_offset + 4 * cpu;
39
40 writel(readl(reg) | BIT(bit), reg);
41}
42
43static void bcm2836_arm_irqchip_mask_timer_irq(struct irq_data *d)
44{
45 bcm2836_arm_irqchip_mask_per_cpu_irq(LOCAL_TIMER_INT_CONTROL0,
46 d->hwirq - LOCAL_IRQ_CNTPSIRQ,
47 smp_processor_id());
48}
49
50static void bcm2836_arm_irqchip_unmask_timer_irq(struct irq_data *d)
51{
52 bcm2836_arm_irqchip_unmask_per_cpu_irq(LOCAL_TIMER_INT_CONTROL0,
53 d->hwirq - LOCAL_IRQ_CNTPSIRQ,
54 smp_processor_id());
55}
56
57static struct irq_chip bcm2836_arm_irqchip_timer = {
58 .name = "bcm2836-timer",
59 .irq_mask = bcm2836_arm_irqchip_mask_timer_irq,
60 .irq_unmask = bcm2836_arm_irqchip_unmask_timer_irq,
61};
62
63static void bcm2836_arm_irqchip_mask_pmu_irq(struct irq_data *d)
64{
65 writel(1 << smp_processor_id(), intc.base + LOCAL_PM_ROUTING_CLR);
66}
67
68static void bcm2836_arm_irqchip_unmask_pmu_irq(struct irq_data *d)
69{
70 writel(1 << smp_processor_id(), intc.base + LOCAL_PM_ROUTING_SET);
71}
72
73static struct irq_chip bcm2836_arm_irqchip_pmu = {
74 .name = "bcm2836-pmu",
75 .irq_mask = bcm2836_arm_irqchip_mask_pmu_irq,
76 .irq_unmask = bcm2836_arm_irqchip_unmask_pmu_irq,
77};
78
79static void bcm2836_arm_irqchip_mask_gpu_irq(struct irq_data *d)
80{
81}
82
83static void bcm2836_arm_irqchip_unmask_gpu_irq(struct irq_data *d)
84{
85}
86
87static struct irq_chip bcm2836_arm_irqchip_gpu = {
88 .name = "bcm2836-gpu",
89 .irq_mask = bcm2836_arm_irqchip_mask_gpu_irq,
90 .irq_unmask = bcm2836_arm_irqchip_unmask_gpu_irq,
91};
92
93static void bcm2836_arm_irqchip_dummy_op(struct irq_data *d)
94{
95}
96
97static struct irq_chip bcm2836_arm_irqchip_dummy = {
98 .name = "bcm2836-dummy",
99 .irq_eoi = bcm2836_arm_irqchip_dummy_op,
100};
101
102static int bcm2836_map(struct irq_domain *d, unsigned int irq,
103 irq_hw_number_t hw)
104{
105 struct irq_chip *chip;
106
107 switch (hw) {
108 case LOCAL_IRQ_MAILBOX0:
109 chip = &bcm2836_arm_irqchip_dummy;
110 break;
111 case LOCAL_IRQ_CNTPSIRQ:
112 case LOCAL_IRQ_CNTPNSIRQ:
113 case LOCAL_IRQ_CNTHPIRQ:
114 case LOCAL_IRQ_CNTVIRQ:
115 chip = &bcm2836_arm_irqchip_timer;
116 break;
117 case LOCAL_IRQ_GPU_FAST:
118 chip = &bcm2836_arm_irqchip_gpu;
119 break;
120 case LOCAL_IRQ_PMU_FAST:
121 chip = &bcm2836_arm_irqchip_pmu;
122 break;
123 default:
124 pr_warn_once("Unexpected hw irq: %lu\n", hw);
125 return -EINVAL;
126 }
127
128 irq_set_percpu_devid(irq);
129 irq_domain_set_info(d, irq, hw, chip, d->host_data,
130 handle_percpu_devid_irq, NULL, NULL);
131 irq_set_status_flags(irq, IRQ_NOAUTOEN);
132
133 return 0;
134}
135
136static void
137__exception_irq_entry bcm2836_arm_irqchip_handle_irq(struct pt_regs *regs)
138{
139 int cpu = smp_processor_id();
140 u32 stat;
141
142 stat = readl_relaxed(intc.base + LOCAL_IRQ_PENDING0 + 4 * cpu);
143 if (stat) {
144 u32 hwirq = ffs(stat) - 1;
145
146 generic_handle_domain_irq(intc.domain, hwirq);
147 }
148}
149
150#ifdef CONFIG_SMP
151static struct irq_domain *ipi_domain;
152
153static void bcm2836_arm_irqchip_handle_ipi(struct irq_desc *desc)
154{
155 struct irq_chip *chip = irq_desc_get_chip(desc);
156 int cpu = smp_processor_id();
157 u32 mbox_val;
158
159 chained_irq_enter(chip, desc);
160
161 mbox_val = readl_relaxed(intc.base + LOCAL_MAILBOX0_CLR0 + 16 * cpu);
162 if (mbox_val) {
163 int hwirq = ffs(mbox_val) - 1;
164 generic_handle_domain_irq(ipi_domain, hwirq);
165 }
166
167 chained_irq_exit(chip, desc);
168}
169
170static void bcm2836_arm_irqchip_ipi_ack(struct irq_data *d)
171{
172 int cpu = smp_processor_id();
173
174 writel_relaxed(BIT(d->hwirq),
175 intc.base + LOCAL_MAILBOX0_CLR0 + 16 * cpu);
176}
177
178static void bcm2836_arm_irqchip_ipi_send_mask(struct irq_data *d,
179 const struct cpumask *mask)
180{
181 int cpu;
182 void __iomem *mailbox0_base = intc.base + LOCAL_MAILBOX0_SET0;
183
184 /*
185 * Ensure that stores to normal memory are visible to the
186 * other CPUs before issuing the IPI.
187 */
188 smp_wmb();
189
190 for_each_cpu(cpu, mask)
191 writel_relaxed(BIT(d->hwirq), mailbox0_base + 16 * cpu);
192}
193
194static struct irq_chip bcm2836_arm_irqchip_ipi = {
195 .name = "IPI",
196 .irq_mask = bcm2836_arm_irqchip_dummy_op,
197 .irq_unmask = bcm2836_arm_irqchip_dummy_op,
198 .irq_ack = bcm2836_arm_irqchip_ipi_ack,
199 .ipi_send_mask = bcm2836_arm_irqchip_ipi_send_mask,
200};
201
202static int bcm2836_arm_irqchip_ipi_alloc(struct irq_domain *d,
203 unsigned int virq,
204 unsigned int nr_irqs, void *args)
205{
206 int i;
207
208 for (i = 0; i < nr_irqs; i++) {
209 irq_set_percpu_devid(virq + i);
210 irq_domain_set_info(d, virq + i, i, &bcm2836_arm_irqchip_ipi,
211 d->host_data,
212 handle_percpu_devid_irq,
213 NULL, NULL);
214 }
215
216 return 0;
217}
218
219static void bcm2836_arm_irqchip_ipi_free(struct irq_domain *d,
220 unsigned int virq,
221 unsigned int nr_irqs)
222{
223 /* Not freeing IPIs */
224}
225
226static const struct irq_domain_ops ipi_domain_ops = {
227 .alloc = bcm2836_arm_irqchip_ipi_alloc,
228 .free = bcm2836_arm_irqchip_ipi_free,
229};
230
231static int bcm2836_cpu_starting(unsigned int cpu)
232{
233 bcm2836_arm_irqchip_unmask_per_cpu_irq(LOCAL_MAILBOX_INT_CONTROL0, 0,
234 cpu);
235 return 0;
236}
237
238static int bcm2836_cpu_dying(unsigned int cpu)
239{
240 bcm2836_arm_irqchip_mask_per_cpu_irq(LOCAL_MAILBOX_INT_CONTROL0, 0,
241 cpu);
242 return 0;
243}
244
245#define BITS_PER_MBOX 32
246
247static void __init bcm2836_arm_irqchip_smp_init(void)
248{
249 struct irq_fwspec ipi_fwspec = {
250 .fwnode = intc.domain->fwnode,
251 .param_count = 1,
252 .param = {
253 [0] = LOCAL_IRQ_MAILBOX0,
254 },
255 };
256 int base_ipi, mux_irq;
257
258 mux_irq = irq_create_fwspec_mapping(&ipi_fwspec);
259 if (WARN_ON(mux_irq <= 0))
260 return;
261
262 ipi_domain = irq_domain_create_linear(intc.domain->fwnode,
263 BITS_PER_MBOX, &ipi_domain_ops,
264 NULL);
265 if (WARN_ON(!ipi_domain))
266 return;
267
268 ipi_domain->flags |= IRQ_DOMAIN_FLAG_IPI_SINGLE;
269 irq_domain_update_bus_token(ipi_domain, DOMAIN_BUS_IPI);
270
271 base_ipi = __irq_domain_alloc_irqs(ipi_domain, -1, BITS_PER_MBOX,
272 NUMA_NO_NODE, NULL,
273 false, NULL);
274
275 if (WARN_ON(!base_ipi))
276 return;
277
278 set_smp_ipi_range(base_ipi, BITS_PER_MBOX);
279
280 irq_set_chained_handler_and_data(mux_irq,
281 bcm2836_arm_irqchip_handle_ipi, NULL);
282
283 /* Unmask IPIs to the boot CPU. */
284 cpuhp_setup_state(CPUHP_AP_IRQ_BCM2836_STARTING,
285 "irqchip/bcm2836:starting", bcm2836_cpu_starting,
286 bcm2836_cpu_dying);
287}
288#else
289#define bcm2836_arm_irqchip_smp_init() do { } while(0)
290#endif
291
292static const struct irq_domain_ops bcm2836_arm_irqchip_intc_ops = {
293 .xlate = irq_domain_xlate_onetwocell,
294 .map = bcm2836_map,
295};
296
297/*
298 * The LOCAL_IRQ_CNT* timer firings are based off of the external
299 * oscillator with some scaling. The firmware sets up CNTFRQ to
300 * report 19.2Mhz, but doesn't set up the scaling registers.
301 */
302static void bcm2835_init_local_timer_frequency(void)
303{
304 /*
305 * Set the timer to source from the 19.2Mhz crystal clock (bit
306 * 8 unset), and only increment by 1 instead of 2 (bit 9
307 * unset).
308 */
309 writel(0, intc.base + LOCAL_CONTROL);
310
311 /*
312 * Set the timer prescaler to 1:1 (timer freq = input freq *
313 * 2**31 / prescaler)
314 */
315 writel(0x80000000, intc.base + LOCAL_PRESCALER);
316}
317
318static int __init bcm2836_arm_irqchip_l1_intc_of_init(struct device_node *node,
319 struct device_node *parent)
320{
321 intc.base = of_iomap(node, 0);
322 if (!intc.base) {
323 panic("%pOF: unable to map local interrupt registers\n", node);
324 }
325
326 bcm2835_init_local_timer_frequency();
327
328 intc.domain = irq_domain_add_linear(node, LAST_IRQ + 1,
329 &bcm2836_arm_irqchip_intc_ops,
330 NULL);
331 if (!intc.domain)
332 panic("%pOF: unable to create IRQ domain\n", node);
333
334 irq_domain_update_bus_token(intc.domain, DOMAIN_BUS_WIRED);
335
336 bcm2836_arm_irqchip_smp_init();
337
338 set_handle_irq(bcm2836_arm_irqchip_handle_irq);
339 return 0;
340}
341
342IRQCHIP_DECLARE(bcm2836_arm_irqchip_l1_intc, "brcm,bcm2836-l1-intc",
343 bcm2836_arm_irqchip_l1_intc_of_init);