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1/*
2 * Copyright 2019 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24#include <linux/delay.h>
25#include <linux/firmware.h>
26#include <linux/module.h>
27#include <linux/pci.h>
28
29#include "amdgpu.h"
30#include "amdgpu_ucode.h"
31#include "amdgpu_trace.h"
32
33#include "gc/gc_10_3_0_offset.h"
34#include "gc/gc_10_3_0_sh_mask.h"
35#include "ivsrcid/sdma0/irqsrcs_sdma0_5_0.h"
36#include "ivsrcid/sdma1/irqsrcs_sdma1_5_0.h"
37#include "ivsrcid/sdma2/irqsrcs_sdma2_5_0.h"
38#include "ivsrcid/sdma3/irqsrcs_sdma3_5_0.h"
39
40#include "soc15_common.h"
41#include "soc15.h"
42#include "navi10_sdma_pkt_open.h"
43#include "nbio_v2_3.h"
44#include "sdma_common.h"
45#include "sdma_v5_2.h"
46
47MODULE_FIRMWARE("amdgpu/sienna_cichlid_sdma.bin");
48MODULE_FIRMWARE("amdgpu/navy_flounder_sdma.bin");
49
50#define SDMA1_REG_OFFSET 0x600
51#define SDMA3_REG_OFFSET 0x400
52#define SDMA0_HYP_DEC_REG_START 0x5880
53#define SDMA0_HYP_DEC_REG_END 0x5893
54#define SDMA1_HYP_DEC_REG_OFFSET 0x20
55
56static void sdma_v5_2_set_ring_funcs(struct amdgpu_device *adev);
57static void sdma_v5_2_set_buffer_funcs(struct amdgpu_device *adev);
58static void sdma_v5_2_set_vm_pte_funcs(struct amdgpu_device *adev);
59static void sdma_v5_2_set_irq_funcs(struct amdgpu_device *adev);
60
61static u32 sdma_v5_2_get_reg_offset(struct amdgpu_device *adev, u32 instance, u32 internal_offset)
62{
63 u32 base;
64
65 if (internal_offset >= SDMA0_HYP_DEC_REG_START &&
66 internal_offset <= SDMA0_HYP_DEC_REG_END) {
67 base = adev->reg_offset[GC_HWIP][0][1];
68 if (instance != 0)
69 internal_offset += SDMA1_HYP_DEC_REG_OFFSET * instance;
70 } else {
71 if (instance < 2) {
72 base = adev->reg_offset[GC_HWIP][0][0];
73 if (instance == 1)
74 internal_offset += SDMA1_REG_OFFSET;
75 } else {
76 base = adev->reg_offset[GC_HWIP][0][2];
77 if (instance == 3)
78 internal_offset += SDMA3_REG_OFFSET;
79 }
80 }
81
82 return base + internal_offset;
83}
84
85static void sdma_v5_2_init_golden_registers(struct amdgpu_device *adev)
86{
87 switch (adev->asic_type) {
88 case CHIP_SIENNA_CICHLID:
89 case CHIP_NAVY_FLOUNDER:
90 break;
91 default:
92 break;
93 }
94}
95
96static int sdma_v5_2_init_inst_ctx(struct amdgpu_sdma_instance *sdma_inst)
97{
98 int err = 0;
99 const struct sdma_firmware_header_v1_0 *hdr;
100
101 err = amdgpu_ucode_validate(sdma_inst->fw);
102 if (err)
103 return err;
104
105 hdr = (const struct sdma_firmware_header_v1_0 *)sdma_inst->fw->data;
106 sdma_inst->fw_version = le32_to_cpu(hdr->header.ucode_version);
107 sdma_inst->feature_version = le32_to_cpu(hdr->ucode_feature_version);
108
109 if (sdma_inst->feature_version >= 20)
110 sdma_inst->burst_nop = true;
111
112 return 0;
113}
114
115static void sdma_v5_2_destroy_inst_ctx(struct amdgpu_device *adev)
116{
117 int i;
118
119 for (i = 0; i < adev->sdma.num_instances; i++) {
120 release_firmware(adev->sdma.instance[i].fw);
121 adev->sdma.instance[i].fw = NULL;
122
123 if (adev->asic_type == CHIP_SIENNA_CICHLID)
124 break;
125 }
126
127 memset((void*)adev->sdma.instance, 0,
128 sizeof(struct amdgpu_sdma_instance) * AMDGPU_MAX_SDMA_INSTANCES);
129}
130
131/**
132 * sdma_v5_2_init_microcode - load ucode images from disk
133 *
134 * @adev: amdgpu_device pointer
135 *
136 * Use the firmware interface to load the ucode images into
137 * the driver (not loaded into hw).
138 * Returns 0 on success, error on failure.
139 */
140
141// emulation only, won't work on real chip
142// navi10 real chip need to use PSP to load firmware
143static int sdma_v5_2_init_microcode(struct amdgpu_device *adev)
144{
145 const char *chip_name;
146 char fw_name[40];
147 int err = 0, i;
148 struct amdgpu_firmware_info *info = NULL;
149 const struct common_firmware_header *header = NULL;
150
151 DRM_DEBUG("\n");
152
153 switch (adev->asic_type) {
154 case CHIP_SIENNA_CICHLID:
155 chip_name = "sienna_cichlid";
156 break;
157 case CHIP_NAVY_FLOUNDER:
158 chip_name = "navy_flounder";
159 break;
160 default:
161 BUG();
162 }
163
164 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma.bin", chip_name);
165
166 err = request_firmware(&adev->sdma.instance[0].fw, fw_name, adev->dev);
167 if (err)
168 goto out;
169
170 err = sdma_v5_2_init_inst_ctx(&adev->sdma.instance[0]);
171 if (err)
172 goto out;
173
174 for (i = 1; i < adev->sdma.num_instances; i++) {
175 if (adev->asic_type == CHIP_SIENNA_CICHLID ||
176 adev->asic_type == CHIP_NAVY_FLOUNDER) {
177 memcpy((void*)&adev->sdma.instance[i],
178 (void*)&adev->sdma.instance[0],
179 sizeof(struct amdgpu_sdma_instance));
180 } else {
181 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma%d.bin", chip_name, i);
182 err = request_firmware(&adev->sdma.instance[i].fw, fw_name, adev->dev);
183 if (err)
184 goto out;
185
186 err = sdma_v5_2_init_inst_ctx(&adev->sdma.instance[0]);
187 if (err)
188 goto out;
189 }
190 }
191
192 DRM_DEBUG("psp_load == '%s'\n",
193 adev->firmware.load_type == AMDGPU_FW_LOAD_PSP ? "true" : "false");
194
195 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
196 for (i = 0; i < adev->sdma.num_instances; i++) {
197 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SDMA0 + i];
198 info->ucode_id = AMDGPU_UCODE_ID_SDMA0 + i;
199 info->fw = adev->sdma.instance[i].fw;
200 header = (const struct common_firmware_header *)info->fw->data;
201 adev->firmware.fw_size +=
202 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
203 }
204 }
205
206out:
207 if (err) {
208 DRM_ERROR("sdma_v5_2: Failed to load firmware \"%s\"\n", fw_name);
209 sdma_v5_2_destroy_inst_ctx(adev);
210 }
211 return err;
212}
213
214static unsigned sdma_v5_2_ring_init_cond_exec(struct amdgpu_ring *ring)
215{
216 unsigned ret;
217
218 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_COND_EXE));
219 amdgpu_ring_write(ring, lower_32_bits(ring->cond_exe_gpu_addr));
220 amdgpu_ring_write(ring, upper_32_bits(ring->cond_exe_gpu_addr));
221 amdgpu_ring_write(ring, 1);
222 ret = ring->wptr & ring->buf_mask;/* this is the offset we need patch later */
223 amdgpu_ring_write(ring, 0x55aa55aa);/* insert dummy here and patch it later */
224
225 return ret;
226}
227
228static void sdma_v5_2_ring_patch_cond_exec(struct amdgpu_ring *ring,
229 unsigned offset)
230{
231 unsigned cur;
232
233 BUG_ON(offset > ring->buf_mask);
234 BUG_ON(ring->ring[offset] != 0x55aa55aa);
235
236 cur = (ring->wptr - 1) & ring->buf_mask;
237 if (cur > offset)
238 ring->ring[offset] = cur - offset;
239 else
240 ring->ring[offset] = (ring->buf_mask + 1) - offset + cur;
241}
242
243/**
244 * sdma_v5_2_ring_get_rptr - get the current read pointer
245 *
246 * @ring: amdgpu ring pointer
247 *
248 * Get the current rptr from the hardware (NAVI10+).
249 */
250static uint64_t sdma_v5_2_ring_get_rptr(struct amdgpu_ring *ring)
251{
252 u64 *rptr;
253
254 /* XXX check if swapping is necessary on BE */
255 rptr = ((u64 *)&ring->adev->wb.wb[ring->rptr_offs]);
256
257 DRM_DEBUG("rptr before shift == 0x%016llx\n", *rptr);
258 return ((*rptr) >> 2);
259}
260
261/**
262 * sdma_v5_2_ring_get_wptr - get the current write pointer
263 *
264 * @ring: amdgpu ring pointer
265 *
266 * Get the current wptr from the hardware (NAVI10+).
267 */
268static uint64_t sdma_v5_2_ring_get_wptr(struct amdgpu_ring *ring)
269{
270 struct amdgpu_device *adev = ring->adev;
271 u64 wptr;
272
273 if (ring->use_doorbell) {
274 /* XXX check if swapping is necessary on BE */
275 wptr = READ_ONCE(*((u64 *)&adev->wb.wb[ring->wptr_offs]));
276 DRM_DEBUG("wptr/doorbell before shift == 0x%016llx\n", wptr);
277 } else {
278 wptr = RREG32(sdma_v5_2_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR_HI));
279 wptr = wptr << 32;
280 wptr |= RREG32(sdma_v5_2_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR));
281 DRM_DEBUG("wptr before shift [%i] wptr == 0x%016llx\n", ring->me, wptr);
282 }
283
284 return wptr >> 2;
285}
286
287/**
288 * sdma_v5_2_ring_set_wptr - commit the write pointer
289 *
290 * @ring: amdgpu ring pointer
291 *
292 * Write the wptr back to the hardware (NAVI10+).
293 */
294static void sdma_v5_2_ring_set_wptr(struct amdgpu_ring *ring)
295{
296 struct amdgpu_device *adev = ring->adev;
297
298 DRM_DEBUG("Setting write pointer\n");
299 if (ring->use_doorbell) {
300 DRM_DEBUG("Using doorbell -- "
301 "wptr_offs == 0x%08x "
302 "lower_32_bits(ring->wptr) << 2 == 0x%08x "
303 "upper_32_bits(ring->wptr) << 2 == 0x%08x\n",
304 ring->wptr_offs,
305 lower_32_bits(ring->wptr << 2),
306 upper_32_bits(ring->wptr << 2));
307 /* XXX check if swapping is necessary on BE */
308 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr << 2);
309 adev->wb.wb[ring->wptr_offs + 1] = upper_32_bits(ring->wptr << 2);
310 DRM_DEBUG("calling WDOORBELL64(0x%08x, 0x%016llx)\n",
311 ring->doorbell_index, ring->wptr << 2);
312 WDOORBELL64(ring->doorbell_index, ring->wptr << 2);
313 } else {
314 DRM_DEBUG("Not using doorbell -- "
315 "mmSDMA%i_GFX_RB_WPTR == 0x%08x "
316 "mmSDMA%i_GFX_RB_WPTR_HI == 0x%08x\n",
317 ring->me,
318 lower_32_bits(ring->wptr << 2),
319 ring->me,
320 upper_32_bits(ring->wptr << 2));
321 WREG32(sdma_v5_2_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR),
322 lower_32_bits(ring->wptr << 2));
323 WREG32(sdma_v5_2_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR_HI),
324 upper_32_bits(ring->wptr << 2));
325 }
326}
327
328static void sdma_v5_2_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
329{
330 struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring);
331 int i;
332
333 for (i = 0; i < count; i++)
334 if (sdma && sdma->burst_nop && (i == 0))
335 amdgpu_ring_write(ring, ring->funcs->nop |
336 SDMA_PKT_NOP_HEADER_COUNT(count - 1));
337 else
338 amdgpu_ring_write(ring, ring->funcs->nop);
339}
340
341/**
342 * sdma_v5_2_ring_emit_ib - Schedule an IB on the DMA engine
343 *
344 * @ring: amdgpu ring pointer
345 * @ib: IB object to schedule
346 *
347 * Schedule an IB in the DMA ring.
348 */
349static void sdma_v5_2_ring_emit_ib(struct amdgpu_ring *ring,
350 struct amdgpu_job *job,
351 struct amdgpu_ib *ib,
352 uint32_t flags)
353{
354 unsigned vmid = AMDGPU_JOB_GET_VMID(job);
355 uint64_t csa_mc_addr = amdgpu_sdma_get_csa_mc_addr(ring, vmid);
356
357 /* An IB packet must end on a 8 DW boundary--the next dword
358 * must be on a 8-dword boundary. Our IB packet below is 6
359 * dwords long, thus add x number of NOPs, such that, in
360 * modular arithmetic,
361 * wptr + 6 + x = 8k, k >= 0, which in C is,
362 * (wptr + 6 + x) % 8 = 0.
363 * The expression below, is a solution of x.
364 */
365 sdma_v5_2_ring_insert_nop(ring, (2 - lower_32_bits(ring->wptr)) & 7);
366
367 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) |
368 SDMA_PKT_INDIRECT_HEADER_VMID(vmid & 0xf));
369 /* base must be 32 byte aligned */
370 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0);
371 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
372 amdgpu_ring_write(ring, ib->length_dw);
373 amdgpu_ring_write(ring, lower_32_bits(csa_mc_addr));
374 amdgpu_ring_write(ring, upper_32_bits(csa_mc_addr));
375}
376
377/**
378 * sdma_v5_2_ring_emit_hdp_flush - emit an hdp flush on the DMA ring
379 *
380 * @ring: amdgpu ring pointer
381 *
382 * Emit an hdp flush packet on the requested DMA ring.
383 */
384static void sdma_v5_2_ring_emit_hdp_flush(struct amdgpu_ring *ring)
385{
386 struct amdgpu_device *adev = ring->adev;
387 u32 ref_and_mask = 0;
388 const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg;
389
390 ref_and_mask = nbio_hf_reg->ref_and_mask_sdma0 << ring->me;
391
392 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
393 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(1) |
394 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* == */
395 amdgpu_ring_write(ring, (adev->nbio.funcs->get_hdp_flush_done_offset(adev)) << 2);
396 amdgpu_ring_write(ring, (adev->nbio.funcs->get_hdp_flush_req_offset(adev)) << 2);
397 amdgpu_ring_write(ring, ref_and_mask); /* reference */
398 amdgpu_ring_write(ring, ref_and_mask); /* mask */
399 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
400 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */
401}
402
403/**
404 * sdma_v5_2_ring_emit_fence - emit a fence on the DMA ring
405 *
406 * @ring: amdgpu ring pointer
407 * @fence: amdgpu fence object
408 *
409 * Add a DMA fence packet to the ring to write
410 * the fence seq number and DMA trap packet to generate
411 * an interrupt if needed.
412 */
413static void sdma_v5_2_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
414 unsigned flags)
415{
416 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
417 /* write the fence */
418 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE) |
419 SDMA_PKT_FENCE_HEADER_MTYPE(0x3)); /* Ucached(UC) */
420 /* zero in first two bits */
421 BUG_ON(addr & 0x3);
422 amdgpu_ring_write(ring, lower_32_bits(addr));
423 amdgpu_ring_write(ring, upper_32_bits(addr));
424 amdgpu_ring_write(ring, lower_32_bits(seq));
425
426 /* optionally write high bits as well */
427 if (write64bit) {
428 addr += 4;
429 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE) |
430 SDMA_PKT_FENCE_HEADER_MTYPE(0x3));
431 /* zero in first two bits */
432 BUG_ON(addr & 0x3);
433 amdgpu_ring_write(ring, lower_32_bits(addr));
434 amdgpu_ring_write(ring, upper_32_bits(addr));
435 amdgpu_ring_write(ring, upper_32_bits(seq));
436 }
437
438 if (flags & AMDGPU_FENCE_FLAG_INT) {
439 /* generate an interrupt */
440 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_TRAP));
441 amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(0));
442 }
443}
444
445
446/**
447 * sdma_v5_2_gfx_stop - stop the gfx async dma engines
448 *
449 * @adev: amdgpu_device pointer
450 *
451 * Stop the gfx async dma ring buffers.
452 */
453static void sdma_v5_2_gfx_stop(struct amdgpu_device *adev)
454{
455 struct amdgpu_ring *sdma0 = &adev->sdma.instance[0].ring;
456 struct amdgpu_ring *sdma1 = &adev->sdma.instance[1].ring;
457 struct amdgpu_ring *sdma2 = &adev->sdma.instance[2].ring;
458 struct amdgpu_ring *sdma3 = &adev->sdma.instance[3].ring;
459 u32 rb_cntl, ib_cntl;
460 int i;
461
462 if ((adev->mman.buffer_funcs_ring == sdma0) ||
463 (adev->mman.buffer_funcs_ring == sdma1) ||
464 (adev->mman.buffer_funcs_ring == sdma2) ||
465 (adev->mman.buffer_funcs_ring == sdma3))
466 amdgpu_ttm_set_buffer_funcs_status(adev, false);
467
468 for (i = 0; i < adev->sdma.num_instances; i++) {
469 rb_cntl = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL));
470 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0);
471 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl);
472 ib_cntl = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL));
473 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 0);
474 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL), ib_cntl);
475 }
476
477 sdma0->sched.ready = false;
478 sdma1->sched.ready = false;
479 sdma2->sched.ready = false;
480 sdma3->sched.ready = false;
481}
482
483/**
484 * sdma_v5_2_rlc_stop - stop the compute async dma engines
485 *
486 * @adev: amdgpu_device pointer
487 *
488 * Stop the compute async dma queues.
489 */
490static void sdma_v5_2_rlc_stop(struct amdgpu_device *adev)
491{
492 /* XXX todo */
493}
494
495/**
496 * sdma_v_0_ctx_switch_enable - stop the async dma engines context switch
497 *
498 * @adev: amdgpu_device pointer
499 * @enable: enable/disable the DMA MEs context switch.
500 *
501 * Halt or unhalt the async dma engines context switch.
502 */
503static void sdma_v5_2_ctx_switch_enable(struct amdgpu_device *adev, bool enable)
504{
505 u32 f32_cntl, phase_quantum = 0;
506 int i;
507
508 if (amdgpu_sdma_phase_quantum) {
509 unsigned value = amdgpu_sdma_phase_quantum;
510 unsigned unit = 0;
511
512 while (value > (SDMA0_PHASE0_QUANTUM__VALUE_MASK >>
513 SDMA0_PHASE0_QUANTUM__VALUE__SHIFT)) {
514 value = (value + 1) >> 1;
515 unit++;
516 }
517 if (unit > (SDMA0_PHASE0_QUANTUM__UNIT_MASK >>
518 SDMA0_PHASE0_QUANTUM__UNIT__SHIFT)) {
519 value = (SDMA0_PHASE0_QUANTUM__VALUE_MASK >>
520 SDMA0_PHASE0_QUANTUM__VALUE__SHIFT);
521 unit = (SDMA0_PHASE0_QUANTUM__UNIT_MASK >>
522 SDMA0_PHASE0_QUANTUM__UNIT__SHIFT);
523 WARN_ONCE(1,
524 "clamping sdma_phase_quantum to %uK clock cycles\n",
525 value << unit);
526 }
527 phase_quantum =
528 value << SDMA0_PHASE0_QUANTUM__VALUE__SHIFT |
529 unit << SDMA0_PHASE0_QUANTUM__UNIT__SHIFT;
530 }
531
532 for (i = 0; i < adev->sdma.num_instances; i++) {
533 f32_cntl = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CNTL));
534 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,
535 AUTO_CTXSW_ENABLE, enable ? 1 : 0);
536 if (enable && amdgpu_sdma_phase_quantum) {
537 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_PHASE0_QUANTUM),
538 phase_quantum);
539 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_PHASE1_QUANTUM),
540 phase_quantum);
541 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_PHASE2_QUANTUM),
542 phase_quantum);
543 }
544 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CNTL), f32_cntl);
545 }
546
547}
548
549/**
550 * sdma_v5_2_enable - stop the async dma engines
551 *
552 * @adev: amdgpu_device pointer
553 * @enable: enable/disable the DMA MEs.
554 *
555 * Halt or unhalt the async dma engines.
556 */
557static void sdma_v5_2_enable(struct amdgpu_device *adev, bool enable)
558{
559 u32 f32_cntl;
560 int i;
561
562 if (enable == false) {
563 sdma_v5_2_gfx_stop(adev);
564 sdma_v5_2_rlc_stop(adev);
565 }
566
567 for (i = 0; i < adev->sdma.num_instances; i++) {
568 f32_cntl = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_F32_CNTL));
569 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, enable ? 0 : 1);
570 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_F32_CNTL), f32_cntl);
571 }
572}
573
574/**
575 * sdma_v5_2_gfx_resume - setup and start the async dma engines
576 *
577 * @adev: amdgpu_device pointer
578 *
579 * Set up the gfx DMA ring buffers and enable them.
580 * Returns 0 for success, error for failure.
581 */
582static int sdma_v5_2_gfx_resume(struct amdgpu_device *adev)
583{
584 struct amdgpu_ring *ring;
585 u32 rb_cntl, ib_cntl;
586 u32 rb_bufsz;
587 u32 wb_offset;
588 u32 doorbell;
589 u32 doorbell_offset;
590 u32 temp;
591 u32 wptr_poll_cntl;
592 u64 wptr_gpu_addr;
593 int i, r;
594
595 for (i = 0; i < adev->sdma.num_instances; i++) {
596 ring = &adev->sdma.instance[i].ring;
597 wb_offset = (ring->rptr_offs * 4);
598
599 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL), 0);
600
601 /* Set ring buffer size in dwords */
602 rb_bufsz = order_base_2(ring->ring_size / 4);
603 rb_cntl = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL));
604 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz);
605#ifdef __BIG_ENDIAN
606 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1);
607 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL,
608 RPTR_WRITEBACK_SWAP_ENABLE, 1);
609#endif
610 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl);
611
612 /* Initialize the ring buffer's read and write pointers */
613 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR), 0);
614 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_HI), 0);
615 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), 0);
616 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI), 0);
617
618 /* setup the wptr shadow polling */
619 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
620 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO),
621 lower_32_bits(wptr_gpu_addr));
622 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI),
623 upper_32_bits(wptr_gpu_addr));
624 wptr_poll_cntl = RREG32(sdma_v5_2_get_reg_offset(adev, i,
625 mmSDMA0_GFX_RB_WPTR_POLL_CNTL));
626 wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl,
627 SDMA0_GFX_RB_WPTR_POLL_CNTL,
628 F32_POLL_ENABLE, 1);
629 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_CNTL),
630 wptr_poll_cntl);
631
632 /* set the wb address whether it's enabled or not */
633 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_ADDR_HI),
634 upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF);
635 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_ADDR_LO),
636 lower_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC);
637
638 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1);
639
640 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_BASE), ring->gpu_addr >> 8);
641 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_BASE_HI), ring->gpu_addr >> 40);
642
643 ring->wptr = 0;
644
645 /* before programing wptr to a less value, need set minor_ptr_update first */
646 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_MINOR_PTR_UPDATE), 1);
647
648 if (!amdgpu_sriov_vf(adev)) { /* only bare-metal use register write for wptr */
649 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), lower_32_bits(ring->wptr) << 2);
650 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI), upper_32_bits(ring->wptr) << 2);
651 }
652
653 doorbell = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL));
654 doorbell_offset = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL_OFFSET));
655
656 if (ring->use_doorbell) {
657 doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 1);
658 doorbell_offset = REG_SET_FIELD(doorbell_offset, SDMA0_GFX_DOORBELL_OFFSET,
659 OFFSET, ring->doorbell_index);
660 } else {
661 doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 0);
662 }
663 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL), doorbell);
664 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL_OFFSET), doorbell_offset);
665
666 adev->nbio.funcs->sdma_doorbell_range(adev, i, ring->use_doorbell,
667 ring->doorbell_index,
668 adev->doorbell_index.sdma_doorbell_range);
669
670 if (amdgpu_sriov_vf(adev))
671 sdma_v5_2_ring_set_wptr(ring);
672
673 /* set minor_ptr_update to 0 after wptr programed */
674 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_MINOR_PTR_UPDATE), 0);
675
676 /* set utc l1 enable flag always to 1 */
677 temp = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CNTL));
678 temp = REG_SET_FIELD(temp, SDMA0_CNTL, UTC_L1_ENABLE, 1);
679
680 /* enable MCBP */
681 temp = REG_SET_FIELD(temp, SDMA0_CNTL, MIDCMD_PREEMPT_ENABLE, 1);
682 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CNTL), temp);
683
684 /* Set up RESP_MODE to non-copy addresses */
685 temp = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UTCL1_CNTL));
686 temp = REG_SET_FIELD(temp, SDMA0_UTCL1_CNTL, RESP_MODE, 3);
687 temp = REG_SET_FIELD(temp, SDMA0_UTCL1_CNTL, REDO_DELAY, 9);
688 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UTCL1_CNTL), temp);
689
690 /* program default cache read and write policy */
691 temp = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UTCL1_PAGE));
692 /* clean read policy and write policy bits */
693 temp &= 0xFF0FFF;
694 temp |= ((CACHE_READ_POLICY_L2__DEFAULT << 12) |
695 (CACHE_WRITE_POLICY_L2__DEFAULT << 14) |
696 0x01000000);
697 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UTCL1_PAGE), temp);
698
699 if (!amdgpu_sriov_vf(adev)) {
700 /* unhalt engine */
701 temp = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_F32_CNTL));
702 temp = REG_SET_FIELD(temp, SDMA0_F32_CNTL, HALT, 0);
703 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_F32_CNTL), temp);
704 }
705
706 /* enable DMA RB */
707 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1);
708 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl);
709
710 ib_cntl = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL));
711 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 1);
712#ifdef __BIG_ENDIAN
713 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_SWAP_ENABLE, 1);
714#endif
715 /* enable DMA IBs */
716 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL), ib_cntl);
717
718 ring->sched.ready = true;
719
720 if (amdgpu_sriov_vf(adev)) { /* bare-metal sequence doesn't need below to lines */
721 sdma_v5_2_ctx_switch_enable(adev, true);
722 sdma_v5_2_enable(adev, true);
723 }
724
725 r = amdgpu_ring_test_ring(ring);
726 if (r) {
727 ring->sched.ready = false;
728 return r;
729 }
730
731 if (adev->mman.buffer_funcs_ring == ring)
732 amdgpu_ttm_set_buffer_funcs_status(adev, true);
733 }
734
735 return 0;
736}
737
738/**
739 * sdma_v5_2_rlc_resume - setup and start the async dma engines
740 *
741 * @adev: amdgpu_device pointer
742 *
743 * Set up the compute DMA queues and enable them.
744 * Returns 0 for success, error for failure.
745 */
746static int sdma_v5_2_rlc_resume(struct amdgpu_device *adev)
747{
748 return 0;
749}
750
751/**
752 * sdma_v5_2_load_microcode - load the sDMA ME ucode
753 *
754 * @adev: amdgpu_device pointer
755 *
756 * Loads the sDMA0/1/2/3 ucode.
757 * Returns 0 for success, -EINVAL if the ucode is not available.
758 */
759static int sdma_v5_2_load_microcode(struct amdgpu_device *adev)
760{
761 const struct sdma_firmware_header_v1_0 *hdr;
762 const __le32 *fw_data;
763 u32 fw_size;
764 int i, j;
765
766 /* halt the MEs */
767 sdma_v5_2_enable(adev, false);
768
769 for (i = 0; i < adev->sdma.num_instances; i++) {
770 if (!adev->sdma.instance[i].fw)
771 return -EINVAL;
772
773 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data;
774 amdgpu_ucode_print_sdma_hdr(&hdr->header);
775 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
776
777 fw_data = (const __le32 *)
778 (adev->sdma.instance[i].fw->data +
779 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
780
781 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UCODE_ADDR), 0);
782
783 for (j = 0; j < fw_size; j++) {
784 if (amdgpu_emu_mode == 1 && j % 500 == 0)
785 msleep(1);
786 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UCODE_DATA), le32_to_cpup(fw_data++));
787 }
788
789 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UCODE_ADDR), adev->sdma.instance[i].fw_version);
790 }
791
792 return 0;
793}
794
795/**
796 * sdma_v5_2_start - setup and start the async dma engines
797 *
798 * @adev: amdgpu_device pointer
799 *
800 * Set up the DMA engines and enable them.
801 * Returns 0 for success, error for failure.
802 */
803static int sdma_v5_2_start(struct amdgpu_device *adev)
804{
805 int r = 0;
806
807 if (amdgpu_sriov_vf(adev)) {
808 sdma_v5_2_ctx_switch_enable(adev, false);
809 sdma_v5_2_enable(adev, false);
810
811 /* set RB registers */
812 r = sdma_v5_2_gfx_resume(adev);
813 return r;
814 }
815
816 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
817 r = sdma_v5_2_load_microcode(adev);
818 if (r)
819 return r;
820
821 /* The value of mmSDMA_F32_CNTL is invalid the moment after loading fw */
822 if (amdgpu_emu_mode == 1)
823 msleep(1000);
824 }
825
826 /* unhalt the MEs */
827 sdma_v5_2_enable(adev, true);
828 /* enable sdma ring preemption */
829 sdma_v5_2_ctx_switch_enable(adev, true);
830
831 /* start the gfx rings and rlc compute queues */
832 r = sdma_v5_2_gfx_resume(adev);
833 if (r)
834 return r;
835 r = sdma_v5_2_rlc_resume(adev);
836
837 return r;
838}
839
840/**
841 * sdma_v5_2_ring_test_ring - simple async dma engine test
842 *
843 * @ring: amdgpu_ring structure holding ring information
844 *
845 * Test the DMA engine by writing using it to write an
846 * value to memory.
847 * Returns 0 for success, error for failure.
848 */
849static int sdma_v5_2_ring_test_ring(struct amdgpu_ring *ring)
850{
851 struct amdgpu_device *adev = ring->adev;
852 unsigned i;
853 unsigned index;
854 int r;
855 u32 tmp;
856 u64 gpu_addr;
857
858 r = amdgpu_device_wb_get(adev, &index);
859 if (r) {
860 dev_err(adev->dev, "(%d) failed to allocate wb slot\n", r);
861 return r;
862 }
863
864 gpu_addr = adev->wb.gpu_addr + (index * 4);
865 tmp = 0xCAFEDEAD;
866 adev->wb.wb[index] = cpu_to_le32(tmp);
867
868 r = amdgpu_ring_alloc(ring, 5);
869 if (r) {
870 DRM_ERROR("amdgpu: dma failed to lock ring %d (%d).\n", ring->idx, r);
871 amdgpu_device_wb_free(adev, index);
872 return r;
873 }
874
875 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
876 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR));
877 amdgpu_ring_write(ring, lower_32_bits(gpu_addr));
878 amdgpu_ring_write(ring, upper_32_bits(gpu_addr));
879 amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0));
880 amdgpu_ring_write(ring, 0xDEADBEEF);
881 amdgpu_ring_commit(ring);
882
883 for (i = 0; i < adev->usec_timeout; i++) {
884 tmp = le32_to_cpu(adev->wb.wb[index]);
885 if (tmp == 0xDEADBEEF)
886 break;
887 if (amdgpu_emu_mode == 1)
888 msleep(1);
889 else
890 udelay(1);
891 }
892
893 if (i >= adev->usec_timeout)
894 r = -ETIMEDOUT;
895
896 amdgpu_device_wb_free(adev, index);
897
898 return r;
899}
900
901/**
902 * sdma_v5_2_ring_test_ib - test an IB on the DMA engine
903 *
904 * @ring: amdgpu_ring structure holding ring information
905 *
906 * Test a simple IB in the DMA ring.
907 * Returns 0 on success, error on failure.
908 */
909static int sdma_v5_2_ring_test_ib(struct amdgpu_ring *ring, long timeout)
910{
911 struct amdgpu_device *adev = ring->adev;
912 struct amdgpu_ib ib;
913 struct dma_fence *f = NULL;
914 unsigned index;
915 long r;
916 u32 tmp = 0;
917 u64 gpu_addr;
918
919 r = amdgpu_device_wb_get(adev, &index);
920 if (r) {
921 dev_err(adev->dev, "(%ld) failed to allocate wb slot\n", r);
922 return r;
923 }
924
925 gpu_addr = adev->wb.gpu_addr + (index * 4);
926 tmp = 0xCAFEDEAD;
927 adev->wb.wb[index] = cpu_to_le32(tmp);
928 memset(&ib, 0, sizeof(ib));
929 r = amdgpu_ib_get(adev, NULL, 256, AMDGPU_IB_POOL_DIRECT, &ib);
930 if (r) {
931 DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r);
932 goto err0;
933 }
934
935 ib.ptr[0] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
936 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR);
937 ib.ptr[1] = lower_32_bits(gpu_addr);
938 ib.ptr[2] = upper_32_bits(gpu_addr);
939 ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0);
940 ib.ptr[4] = 0xDEADBEEF;
941 ib.ptr[5] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
942 ib.ptr[6] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
943 ib.ptr[7] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
944 ib.length_dw = 8;
945
946 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
947 if (r)
948 goto err1;
949
950 r = dma_fence_wait_timeout(f, false, timeout);
951 if (r == 0) {
952 DRM_ERROR("amdgpu: IB test timed out\n");
953 r = -ETIMEDOUT;
954 goto err1;
955 } else if (r < 0) {
956 DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r);
957 goto err1;
958 }
959 tmp = le32_to_cpu(adev->wb.wb[index]);
960 if (tmp == 0xDEADBEEF)
961 r = 0;
962 else
963 r = -EINVAL;
964
965err1:
966 amdgpu_ib_free(adev, &ib, NULL);
967 dma_fence_put(f);
968err0:
969 amdgpu_device_wb_free(adev, index);
970 return r;
971}
972
973
974/**
975 * sdma_v5_2_vm_copy_pte - update PTEs by copying them from the GART
976 *
977 * @ib: indirect buffer to fill with commands
978 * @pe: addr of the page entry
979 * @src: src addr to copy from
980 * @count: number of page entries to update
981 *
982 * Update PTEs by copying them from the GART using sDMA.
983 */
984static void sdma_v5_2_vm_copy_pte(struct amdgpu_ib *ib,
985 uint64_t pe, uint64_t src,
986 unsigned count)
987{
988 unsigned bytes = count * 8;
989
990 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
991 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR);
992 ib->ptr[ib->length_dw++] = bytes - 1;
993 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
994 ib->ptr[ib->length_dw++] = lower_32_bits(src);
995 ib->ptr[ib->length_dw++] = upper_32_bits(src);
996 ib->ptr[ib->length_dw++] = lower_32_bits(pe);
997 ib->ptr[ib->length_dw++] = upper_32_bits(pe);
998
999}
1000
1001/**
1002 * sdma_v5_2_vm_write_pte - update PTEs by writing them manually
1003 *
1004 * @ib: indirect buffer to fill with commands
1005 * @pe: addr of the page entry
1006 * @addr: dst addr to write into pe
1007 * @count: number of page entries to update
1008 * @incr: increase next addr by incr bytes
1009 * @flags: access flags
1010 *
1011 * Update PTEs by writing them manually using sDMA.
1012 */
1013static void sdma_v5_2_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe,
1014 uint64_t value, unsigned count,
1015 uint32_t incr)
1016{
1017 unsigned ndw = count * 2;
1018
1019 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
1020 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR);
1021 ib->ptr[ib->length_dw++] = lower_32_bits(pe);
1022 ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1023 ib->ptr[ib->length_dw++] = ndw - 1;
1024 for (; ndw > 0; ndw -= 2) {
1025 ib->ptr[ib->length_dw++] = lower_32_bits(value);
1026 ib->ptr[ib->length_dw++] = upper_32_bits(value);
1027 value += incr;
1028 }
1029}
1030
1031/**
1032 * sdma_v5_2_vm_set_pte_pde - update the page tables using sDMA
1033 *
1034 * @ib: indirect buffer to fill with commands
1035 * @pe: addr of the page entry
1036 * @addr: dst addr to write into pe
1037 * @count: number of page entries to update
1038 * @incr: increase next addr by incr bytes
1039 * @flags: access flags
1040 *
1041 * Update the page tables using sDMA.
1042 */
1043static void sdma_v5_2_vm_set_pte_pde(struct amdgpu_ib *ib,
1044 uint64_t pe,
1045 uint64_t addr, unsigned count,
1046 uint32_t incr, uint64_t flags)
1047{
1048 /* for physically contiguous pages (vram) */
1049 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_PTEPDE);
1050 ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */
1051 ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1052 ib->ptr[ib->length_dw++] = lower_32_bits(flags); /* mask */
1053 ib->ptr[ib->length_dw++] = upper_32_bits(flags);
1054 ib->ptr[ib->length_dw++] = lower_32_bits(addr); /* value */
1055 ib->ptr[ib->length_dw++] = upper_32_bits(addr);
1056 ib->ptr[ib->length_dw++] = incr; /* increment size */
1057 ib->ptr[ib->length_dw++] = 0;
1058 ib->ptr[ib->length_dw++] = count - 1; /* number of entries */
1059}
1060
1061/**
1062 * sdma_v5_2_ring_pad_ib - pad the IB
1063 *
1064 * @ib: indirect buffer to fill with padding
1065 *
1066 * Pad the IB with NOPs to a boundary multiple of 8.
1067 */
1068static void sdma_v5_2_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib)
1069{
1070 struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring);
1071 u32 pad_count;
1072 int i;
1073
1074 pad_count = (-ib->length_dw) & 0x7;
1075 for (i = 0; i < pad_count; i++)
1076 if (sdma && sdma->burst_nop && (i == 0))
1077 ib->ptr[ib->length_dw++] =
1078 SDMA_PKT_HEADER_OP(SDMA_OP_NOP) |
1079 SDMA_PKT_NOP_HEADER_COUNT(pad_count - 1);
1080 else
1081 ib->ptr[ib->length_dw++] =
1082 SDMA_PKT_HEADER_OP(SDMA_OP_NOP);
1083}
1084
1085
1086/**
1087 * sdma_v5_2_ring_emit_pipeline_sync - sync the pipeline
1088 *
1089 * @ring: amdgpu_ring pointer
1090 *
1091 * Make sure all previous operations are completed (CIK).
1092 */
1093static void sdma_v5_2_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
1094{
1095 uint32_t seq = ring->fence_drv.sync_seq;
1096 uint64_t addr = ring->fence_drv.gpu_addr;
1097
1098 /* wait for idle */
1099 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
1100 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) |
1101 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3) | /* equal */
1102 SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL(1));
1103 amdgpu_ring_write(ring, addr & 0xfffffffc);
1104 amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff);
1105 amdgpu_ring_write(ring, seq); /* reference */
1106 amdgpu_ring_write(ring, 0xffffffff); /* mask */
1107 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
1108 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(4)); /* retry count, poll interval */
1109}
1110
1111
1112/**
1113 * sdma_v5_2_ring_emit_vm_flush - vm flush using sDMA
1114 *
1115 * @ring: amdgpu_ring pointer
1116 * @vm: amdgpu_vm pointer
1117 *
1118 * Update the page table base and flush the VM TLB
1119 * using sDMA.
1120 */
1121static void sdma_v5_2_ring_emit_vm_flush(struct amdgpu_ring *ring,
1122 unsigned vmid, uint64_t pd_addr)
1123{
1124 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
1125}
1126
1127static void sdma_v5_2_ring_emit_wreg(struct amdgpu_ring *ring,
1128 uint32_t reg, uint32_t val)
1129{
1130 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
1131 SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
1132 amdgpu_ring_write(ring, reg);
1133 amdgpu_ring_write(ring, val);
1134}
1135
1136static void sdma_v5_2_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
1137 uint32_t val, uint32_t mask)
1138{
1139 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
1140 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) |
1141 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* equal */
1142 amdgpu_ring_write(ring, reg << 2);
1143 amdgpu_ring_write(ring, 0);
1144 amdgpu_ring_write(ring, val); /* reference */
1145 amdgpu_ring_write(ring, mask); /* mask */
1146 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
1147 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10));
1148}
1149
1150static void sdma_v5_2_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring,
1151 uint32_t reg0, uint32_t reg1,
1152 uint32_t ref, uint32_t mask)
1153{
1154 amdgpu_ring_emit_wreg(ring, reg0, ref);
1155 /* wait for a cycle to reset vm_inv_eng*_ack */
1156 amdgpu_ring_emit_reg_wait(ring, reg0, 0, 0);
1157 amdgpu_ring_emit_reg_wait(ring, reg1, mask, mask);
1158}
1159
1160static int sdma_v5_2_early_init(void *handle)
1161{
1162 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1163
1164 switch (adev->asic_type) {
1165 case CHIP_SIENNA_CICHLID:
1166 adev->sdma.num_instances = 4;
1167 break;
1168 case CHIP_NAVY_FLOUNDER:
1169 adev->sdma.num_instances = 2;
1170 break;
1171 default:
1172 break;
1173 }
1174
1175 sdma_v5_2_set_ring_funcs(adev);
1176 sdma_v5_2_set_buffer_funcs(adev);
1177 sdma_v5_2_set_vm_pte_funcs(adev);
1178 sdma_v5_2_set_irq_funcs(adev);
1179
1180 return 0;
1181}
1182
1183static unsigned sdma_v5_2_seq_to_irq_id(int seq_num)
1184{
1185 switch (seq_num) {
1186 case 0:
1187 return SOC15_IH_CLIENTID_SDMA0;
1188 case 1:
1189 return SOC15_IH_CLIENTID_SDMA1;
1190 case 2:
1191 return SOC15_IH_CLIENTID_SDMA2;
1192 case 3:
1193 return SOC15_IH_CLIENTID_SDMA3_Sienna_Cichlid;
1194 default:
1195 break;
1196 }
1197 return -EINVAL;
1198}
1199
1200static unsigned sdma_v5_2_seq_to_trap_id(int seq_num)
1201{
1202 switch (seq_num) {
1203 case 0:
1204 return SDMA0_5_0__SRCID__SDMA_TRAP;
1205 case 1:
1206 return SDMA1_5_0__SRCID__SDMA_TRAP;
1207 case 2:
1208 return SDMA2_5_0__SRCID__SDMA_TRAP;
1209 case 3:
1210 return SDMA3_5_0__SRCID__SDMA_TRAP;
1211 default:
1212 break;
1213 }
1214 return -EINVAL;
1215}
1216
1217static int sdma_v5_2_sw_init(void *handle)
1218{
1219 struct amdgpu_ring *ring;
1220 int r, i;
1221 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1222
1223 /* SDMA trap event */
1224 for (i = 0; i < adev->sdma.num_instances; i++) {
1225 r = amdgpu_irq_add_id(adev, sdma_v5_2_seq_to_irq_id(i),
1226 sdma_v5_2_seq_to_trap_id(i),
1227 &adev->sdma.trap_irq);
1228 if (r)
1229 return r;
1230 }
1231
1232 r = sdma_v5_2_init_microcode(adev);
1233 if (r) {
1234 DRM_ERROR("Failed to load sdma firmware!\n");
1235 return r;
1236 }
1237
1238 for (i = 0; i < adev->sdma.num_instances; i++) {
1239 ring = &adev->sdma.instance[i].ring;
1240 ring->ring_obj = NULL;
1241 ring->use_doorbell = true;
1242 ring->me = i;
1243
1244 DRM_INFO("use_doorbell being set to: [%s]\n",
1245 ring->use_doorbell?"true":"false");
1246
1247 ring->doorbell_index =
1248 (adev->doorbell_index.sdma_engine[i] << 1); //get DWORD offset
1249
1250 sprintf(ring->name, "sdma%d", i);
1251 r = amdgpu_ring_init(adev, ring, 1024,
1252 &adev->sdma.trap_irq,
1253 AMDGPU_SDMA_IRQ_INSTANCE0 + i,
1254 AMDGPU_RING_PRIO_DEFAULT);
1255 if (r)
1256 return r;
1257 }
1258
1259 return r;
1260}
1261
1262static int sdma_v5_2_sw_fini(void *handle)
1263{
1264 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1265 int i;
1266
1267 for (i = 0; i < adev->sdma.num_instances; i++)
1268 amdgpu_ring_fini(&adev->sdma.instance[i].ring);
1269
1270 sdma_v5_2_destroy_inst_ctx(adev);
1271
1272 return 0;
1273}
1274
1275static int sdma_v5_2_hw_init(void *handle)
1276{
1277 int r;
1278 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1279
1280 sdma_v5_2_init_golden_registers(adev);
1281
1282 r = sdma_v5_2_start(adev);
1283
1284 return r;
1285}
1286
1287static int sdma_v5_2_hw_fini(void *handle)
1288{
1289 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1290
1291 if (amdgpu_sriov_vf(adev))
1292 return 0;
1293
1294 sdma_v5_2_ctx_switch_enable(adev, false);
1295 sdma_v5_2_enable(adev, false);
1296
1297 return 0;
1298}
1299
1300static int sdma_v5_2_suspend(void *handle)
1301{
1302 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1303
1304 return sdma_v5_2_hw_fini(adev);
1305}
1306
1307static int sdma_v5_2_resume(void *handle)
1308{
1309 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1310
1311 return sdma_v5_2_hw_init(adev);
1312}
1313
1314static bool sdma_v5_2_is_idle(void *handle)
1315{
1316 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1317 u32 i;
1318
1319 for (i = 0; i < adev->sdma.num_instances; i++) {
1320 u32 tmp = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_STATUS_REG));
1321
1322 if (!(tmp & SDMA0_STATUS_REG__IDLE_MASK))
1323 return false;
1324 }
1325
1326 return true;
1327}
1328
1329static int sdma_v5_2_wait_for_idle(void *handle)
1330{
1331 unsigned i;
1332 u32 sdma0, sdma1, sdma2, sdma3;
1333 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1334
1335 for (i = 0; i < adev->usec_timeout; i++) {
1336 sdma0 = RREG32(sdma_v5_2_get_reg_offset(adev, 0, mmSDMA0_STATUS_REG));
1337 sdma1 = RREG32(sdma_v5_2_get_reg_offset(adev, 1, mmSDMA0_STATUS_REG));
1338 sdma2 = RREG32(sdma_v5_2_get_reg_offset(adev, 2, mmSDMA0_STATUS_REG));
1339 sdma3 = RREG32(sdma_v5_2_get_reg_offset(adev, 3, mmSDMA0_STATUS_REG));
1340
1341 if (sdma0 & sdma1 & sdma2 & sdma3 & SDMA0_STATUS_REG__IDLE_MASK)
1342 return 0;
1343 udelay(1);
1344 }
1345 return -ETIMEDOUT;
1346}
1347
1348static int sdma_v5_2_soft_reset(void *handle)
1349{
1350 /* todo */
1351
1352 return 0;
1353}
1354
1355static int sdma_v5_2_ring_preempt_ib(struct amdgpu_ring *ring)
1356{
1357 int i, r = 0;
1358 struct amdgpu_device *adev = ring->adev;
1359 u32 index = 0;
1360 u64 sdma_gfx_preempt;
1361
1362 amdgpu_sdma_get_index_from_ring(ring, &index);
1363 sdma_gfx_preempt =
1364 sdma_v5_2_get_reg_offset(adev, index, mmSDMA0_GFX_PREEMPT);
1365
1366 /* assert preemption condition */
1367 amdgpu_ring_set_preempt_cond_exec(ring, false);
1368
1369 /* emit the trailing fence */
1370 ring->trail_seq += 1;
1371 amdgpu_ring_alloc(ring, 10);
1372 sdma_v5_2_ring_emit_fence(ring, ring->trail_fence_gpu_addr,
1373 ring->trail_seq, 0);
1374 amdgpu_ring_commit(ring);
1375
1376 /* assert IB preemption */
1377 WREG32(sdma_gfx_preempt, 1);
1378
1379 /* poll the trailing fence */
1380 for (i = 0; i < adev->usec_timeout; i++) {
1381 if (ring->trail_seq ==
1382 le32_to_cpu(*(ring->trail_fence_cpu_addr)))
1383 break;
1384 udelay(1);
1385 }
1386
1387 if (i >= adev->usec_timeout) {
1388 r = -EINVAL;
1389 DRM_ERROR("ring %d failed to be preempted\n", ring->idx);
1390 }
1391
1392 /* deassert IB preemption */
1393 WREG32(sdma_gfx_preempt, 0);
1394
1395 /* deassert the preemption condition */
1396 amdgpu_ring_set_preempt_cond_exec(ring, true);
1397 return r;
1398}
1399
1400static int sdma_v5_2_set_trap_irq_state(struct amdgpu_device *adev,
1401 struct amdgpu_irq_src *source,
1402 unsigned type,
1403 enum amdgpu_interrupt_state state)
1404{
1405 u32 sdma_cntl;
1406
1407 u32 reg_offset = sdma_v5_2_get_reg_offset(adev, type, mmSDMA0_CNTL);
1408
1409 sdma_cntl = RREG32(reg_offset);
1410 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE,
1411 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
1412 WREG32(reg_offset, sdma_cntl);
1413
1414 return 0;
1415}
1416
1417static int sdma_v5_2_process_trap_irq(struct amdgpu_device *adev,
1418 struct amdgpu_irq_src *source,
1419 struct amdgpu_iv_entry *entry)
1420{
1421 DRM_DEBUG("IH: SDMA trap\n");
1422 switch (entry->client_id) {
1423 case SOC15_IH_CLIENTID_SDMA0:
1424 switch (entry->ring_id) {
1425 case 0:
1426 amdgpu_fence_process(&adev->sdma.instance[0].ring);
1427 break;
1428 case 1:
1429 /* XXX compute */
1430 break;
1431 case 2:
1432 /* XXX compute */
1433 break;
1434 case 3:
1435 /* XXX page queue*/
1436 break;
1437 }
1438 break;
1439 case SOC15_IH_CLIENTID_SDMA1:
1440 switch (entry->ring_id) {
1441 case 0:
1442 amdgpu_fence_process(&adev->sdma.instance[1].ring);
1443 break;
1444 case 1:
1445 /* XXX compute */
1446 break;
1447 case 2:
1448 /* XXX compute */
1449 break;
1450 case 3:
1451 /* XXX page queue*/
1452 break;
1453 }
1454 break;
1455 case SOC15_IH_CLIENTID_SDMA2:
1456 switch (entry->ring_id) {
1457 case 0:
1458 amdgpu_fence_process(&adev->sdma.instance[2].ring);
1459 break;
1460 case 1:
1461 /* XXX compute */
1462 break;
1463 case 2:
1464 /* XXX compute */
1465 break;
1466 case 3:
1467 /* XXX page queue*/
1468 break;
1469 }
1470 break;
1471 case SOC15_IH_CLIENTID_SDMA3_Sienna_Cichlid:
1472 switch (entry->ring_id) {
1473 case 0:
1474 amdgpu_fence_process(&adev->sdma.instance[3].ring);
1475 break;
1476 case 1:
1477 /* XXX compute */
1478 break;
1479 case 2:
1480 /* XXX compute */
1481 break;
1482 case 3:
1483 /* XXX page queue*/
1484 break;
1485 }
1486 break;
1487 }
1488 return 0;
1489}
1490
1491static int sdma_v5_2_process_illegal_inst_irq(struct amdgpu_device *adev,
1492 struct amdgpu_irq_src *source,
1493 struct amdgpu_iv_entry *entry)
1494{
1495 return 0;
1496}
1497
1498static void sdma_v5_2_update_medium_grain_clock_gating(struct amdgpu_device *adev,
1499 bool enable)
1500{
1501 uint32_t data, def;
1502 int i;
1503
1504 for (i = 0; i < adev->sdma.num_instances; i++) {
1505 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG)) {
1506 /* Enable sdma clock gating */
1507 def = data = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL));
1508 data &= ~(SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK |
1509 SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK |
1510 SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK |
1511 SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK |
1512 SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK |
1513 SDMA0_CLK_CTRL__SOFT_OVERRIDER_REG_MASK);
1514 if (def != data)
1515 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL), data);
1516 } else {
1517 /* Disable sdma clock gating */
1518 def = data = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL));
1519 data |= (SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK |
1520 SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK |
1521 SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK |
1522 SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK |
1523 SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK |
1524 SDMA0_CLK_CTRL__SOFT_OVERRIDER_REG_MASK);
1525 if (def != data)
1526 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL), data);
1527 }
1528 }
1529}
1530
1531static void sdma_v5_2_update_medium_grain_light_sleep(struct amdgpu_device *adev,
1532 bool enable)
1533{
1534 uint32_t data, def;
1535 int i;
1536
1537 for (i = 0; i < adev->sdma.num_instances; i++) {
1538 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_LS)) {
1539 /* Enable sdma mem light sleep */
1540 def = data = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL));
1541 data |= SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK;
1542 if (def != data)
1543 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL), data);
1544
1545 } else {
1546 /* Disable sdma mem light sleep */
1547 def = data = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL));
1548 data &= ~SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK;
1549 if (def != data)
1550 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL), data);
1551
1552 }
1553 }
1554}
1555
1556static int sdma_v5_2_set_clockgating_state(void *handle,
1557 enum amd_clockgating_state state)
1558{
1559 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1560
1561 if (amdgpu_sriov_vf(adev))
1562 return 0;
1563
1564 switch (adev->asic_type) {
1565 case CHIP_SIENNA_CICHLID:
1566 case CHIP_NAVY_FLOUNDER:
1567 sdma_v5_2_update_medium_grain_clock_gating(adev,
1568 state == AMD_CG_STATE_GATE ? true : false);
1569 sdma_v5_2_update_medium_grain_light_sleep(adev,
1570 state == AMD_CG_STATE_GATE ? true : false);
1571 break;
1572 default:
1573 break;
1574 }
1575
1576 return 0;
1577}
1578
1579static int sdma_v5_2_set_powergating_state(void *handle,
1580 enum amd_powergating_state state)
1581{
1582 return 0;
1583}
1584
1585static void sdma_v5_2_get_clockgating_state(void *handle, u32 *flags)
1586{
1587 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1588 int data;
1589
1590 if (amdgpu_sriov_vf(adev))
1591 *flags = 0;
1592
1593 /* AMD_CG_SUPPORT_SDMA_LS */
1594 data = RREG32_KIQ(sdma_v5_2_get_reg_offset(adev, 0, mmSDMA0_POWER_CNTL));
1595 if (data & SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK)
1596 *flags |= AMD_CG_SUPPORT_SDMA_LS;
1597}
1598
1599const struct amd_ip_funcs sdma_v5_2_ip_funcs = {
1600 .name = "sdma_v5_2",
1601 .early_init = sdma_v5_2_early_init,
1602 .late_init = NULL,
1603 .sw_init = sdma_v5_2_sw_init,
1604 .sw_fini = sdma_v5_2_sw_fini,
1605 .hw_init = sdma_v5_2_hw_init,
1606 .hw_fini = sdma_v5_2_hw_fini,
1607 .suspend = sdma_v5_2_suspend,
1608 .resume = sdma_v5_2_resume,
1609 .is_idle = sdma_v5_2_is_idle,
1610 .wait_for_idle = sdma_v5_2_wait_for_idle,
1611 .soft_reset = sdma_v5_2_soft_reset,
1612 .set_clockgating_state = sdma_v5_2_set_clockgating_state,
1613 .set_powergating_state = sdma_v5_2_set_powergating_state,
1614 .get_clockgating_state = sdma_v5_2_get_clockgating_state,
1615};
1616
1617static const struct amdgpu_ring_funcs sdma_v5_2_ring_funcs = {
1618 .type = AMDGPU_RING_TYPE_SDMA,
1619 .align_mask = 0xf,
1620 .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP),
1621 .support_64bit_ptrs = true,
1622 .vmhub = AMDGPU_GFXHUB_0,
1623 .get_rptr = sdma_v5_2_ring_get_rptr,
1624 .get_wptr = sdma_v5_2_ring_get_wptr,
1625 .set_wptr = sdma_v5_2_ring_set_wptr,
1626 .emit_frame_size =
1627 5 + /* sdma_v5_2_ring_init_cond_exec */
1628 6 + /* sdma_v5_2_ring_emit_hdp_flush */
1629 3 + /* hdp_invalidate */
1630 6 + /* sdma_v5_2_ring_emit_pipeline_sync */
1631 /* sdma_v5_2_ring_emit_vm_flush */
1632 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 +
1633 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6 +
1634 10 + 10 + 10, /* sdma_v5_2_ring_emit_fence x3 for user fence, vm fence */
1635 .emit_ib_size = 7 + 6, /* sdma_v5_2_ring_emit_ib */
1636 .emit_ib = sdma_v5_2_ring_emit_ib,
1637 .emit_fence = sdma_v5_2_ring_emit_fence,
1638 .emit_pipeline_sync = sdma_v5_2_ring_emit_pipeline_sync,
1639 .emit_vm_flush = sdma_v5_2_ring_emit_vm_flush,
1640 .emit_hdp_flush = sdma_v5_2_ring_emit_hdp_flush,
1641 .test_ring = sdma_v5_2_ring_test_ring,
1642 .test_ib = sdma_v5_2_ring_test_ib,
1643 .insert_nop = sdma_v5_2_ring_insert_nop,
1644 .pad_ib = sdma_v5_2_ring_pad_ib,
1645 .emit_wreg = sdma_v5_2_ring_emit_wreg,
1646 .emit_reg_wait = sdma_v5_2_ring_emit_reg_wait,
1647 .emit_reg_write_reg_wait = sdma_v5_2_ring_emit_reg_write_reg_wait,
1648 .init_cond_exec = sdma_v5_2_ring_init_cond_exec,
1649 .patch_cond_exec = sdma_v5_2_ring_patch_cond_exec,
1650 .preempt_ib = sdma_v5_2_ring_preempt_ib,
1651};
1652
1653static void sdma_v5_2_set_ring_funcs(struct amdgpu_device *adev)
1654{
1655 int i;
1656
1657 for (i = 0; i < adev->sdma.num_instances; i++) {
1658 adev->sdma.instance[i].ring.funcs = &sdma_v5_2_ring_funcs;
1659 adev->sdma.instance[i].ring.me = i;
1660 }
1661}
1662
1663static const struct amdgpu_irq_src_funcs sdma_v5_2_trap_irq_funcs = {
1664 .set = sdma_v5_2_set_trap_irq_state,
1665 .process = sdma_v5_2_process_trap_irq,
1666};
1667
1668static const struct amdgpu_irq_src_funcs sdma_v5_2_illegal_inst_irq_funcs = {
1669 .process = sdma_v5_2_process_illegal_inst_irq,
1670};
1671
1672static void sdma_v5_2_set_irq_funcs(struct amdgpu_device *adev)
1673{
1674 adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_INSTANCE0 +
1675 adev->sdma.num_instances;
1676 adev->sdma.trap_irq.funcs = &sdma_v5_2_trap_irq_funcs;
1677 adev->sdma.illegal_inst_irq.funcs = &sdma_v5_2_illegal_inst_irq_funcs;
1678}
1679
1680/**
1681 * sdma_v5_2_emit_copy_buffer - copy buffer using the sDMA engine
1682 *
1683 * @ring: amdgpu_ring structure holding ring information
1684 * @src_offset: src GPU address
1685 * @dst_offset: dst GPU address
1686 * @byte_count: number of bytes to xfer
1687 *
1688 * Copy GPU buffers using the DMA engine.
1689 * Used by the amdgpu ttm implementation to move pages if
1690 * registered as the asic copy callback.
1691 */
1692static void sdma_v5_2_emit_copy_buffer(struct amdgpu_ib *ib,
1693 uint64_t src_offset,
1694 uint64_t dst_offset,
1695 uint32_t byte_count,
1696 bool tmz)
1697{
1698 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
1699 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR) |
1700 SDMA_PKT_COPY_LINEAR_HEADER_TMZ(tmz ? 1 : 0);
1701 ib->ptr[ib->length_dw++] = byte_count - 1;
1702 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
1703 ib->ptr[ib->length_dw++] = lower_32_bits(src_offset);
1704 ib->ptr[ib->length_dw++] = upper_32_bits(src_offset);
1705 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1706 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
1707}
1708
1709/**
1710 * sdma_v5_2_emit_fill_buffer - fill buffer using the sDMA engine
1711 *
1712 * @ring: amdgpu_ring structure holding ring information
1713 * @src_data: value to write to buffer
1714 * @dst_offset: dst GPU address
1715 * @byte_count: number of bytes to xfer
1716 *
1717 * Fill GPU buffers using the DMA engine.
1718 */
1719static void sdma_v5_2_emit_fill_buffer(struct amdgpu_ib *ib,
1720 uint32_t src_data,
1721 uint64_t dst_offset,
1722 uint32_t byte_count)
1723{
1724 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_CONST_FILL);
1725 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1726 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
1727 ib->ptr[ib->length_dw++] = src_data;
1728 ib->ptr[ib->length_dw++] = byte_count - 1;
1729}
1730
1731static const struct amdgpu_buffer_funcs sdma_v5_2_buffer_funcs = {
1732 .copy_max_bytes = 0x400000,
1733 .copy_num_dw = 7,
1734 .emit_copy_buffer = sdma_v5_2_emit_copy_buffer,
1735
1736 .fill_max_bytes = 0x400000,
1737 .fill_num_dw = 5,
1738 .emit_fill_buffer = sdma_v5_2_emit_fill_buffer,
1739};
1740
1741static void sdma_v5_2_set_buffer_funcs(struct amdgpu_device *adev)
1742{
1743 if (adev->mman.buffer_funcs == NULL) {
1744 adev->mman.buffer_funcs = &sdma_v5_2_buffer_funcs;
1745 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring;
1746 }
1747}
1748
1749static const struct amdgpu_vm_pte_funcs sdma_v5_2_vm_pte_funcs = {
1750 .copy_pte_num_dw = 7,
1751 .copy_pte = sdma_v5_2_vm_copy_pte,
1752 .write_pte = sdma_v5_2_vm_write_pte,
1753 .set_pte_pde = sdma_v5_2_vm_set_pte_pde,
1754};
1755
1756static void sdma_v5_2_set_vm_pte_funcs(struct amdgpu_device *adev)
1757{
1758 unsigned i;
1759
1760 if (adev->vm_manager.vm_pte_funcs == NULL) {
1761 adev->vm_manager.vm_pte_funcs = &sdma_v5_2_vm_pte_funcs;
1762 for (i = 0; i < adev->sdma.num_instances; i++) {
1763 adev->vm_manager.vm_pte_scheds[i] =
1764 &adev->sdma.instance[i].ring.sched;
1765 }
1766 adev->vm_manager.vm_pte_num_scheds = adev->sdma.num_instances;
1767 }
1768}
1769
1770const struct amdgpu_ip_block_version sdma_v5_2_ip_block = {
1771 .type = AMD_IP_BLOCK_TYPE_SDMA,
1772 .major = 5,
1773 .minor = 2,
1774 .rev = 0,
1775 .funcs = &sdma_v5_2_ip_funcs,
1776};
1/*
2 * Copyright 2019 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24#include <linux/delay.h>
25#include <linux/firmware.h>
26#include <linux/module.h>
27#include <linux/pci.h>
28
29#include "amdgpu.h"
30#include "amdgpu_ucode.h"
31#include "amdgpu_trace.h"
32
33#include "gc/gc_10_3_0_offset.h"
34#include "gc/gc_10_3_0_sh_mask.h"
35#include "ivsrcid/sdma0/irqsrcs_sdma0_5_0.h"
36#include "ivsrcid/sdma1/irqsrcs_sdma1_5_0.h"
37#include "ivsrcid/sdma2/irqsrcs_sdma2_5_0.h"
38#include "ivsrcid/sdma3/irqsrcs_sdma3_5_0.h"
39
40#include "soc15_common.h"
41#include "soc15.h"
42#include "navi10_sdma_pkt_open.h"
43#include "nbio_v2_3.h"
44#include "sdma_common.h"
45#include "sdma_v5_2.h"
46
47MODULE_FIRMWARE("amdgpu/sienna_cichlid_sdma.bin");
48MODULE_FIRMWARE("amdgpu/navy_flounder_sdma.bin");
49MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_sdma.bin");
50MODULE_FIRMWARE("amdgpu/beige_goby_sdma.bin");
51
52MODULE_FIRMWARE("amdgpu/vangogh_sdma.bin");
53MODULE_FIRMWARE("amdgpu/yellow_carp_sdma.bin");
54MODULE_FIRMWARE("amdgpu/sdma_5_2_6.bin");
55MODULE_FIRMWARE("amdgpu/sdma_5_2_7.bin");
56
57#define SDMA1_REG_OFFSET 0x600
58#define SDMA3_REG_OFFSET 0x400
59#define SDMA0_HYP_DEC_REG_START 0x5880
60#define SDMA0_HYP_DEC_REG_END 0x5893
61#define SDMA1_HYP_DEC_REG_OFFSET 0x20
62
63static void sdma_v5_2_set_ring_funcs(struct amdgpu_device *adev);
64static void sdma_v5_2_set_buffer_funcs(struct amdgpu_device *adev);
65static void sdma_v5_2_set_vm_pte_funcs(struct amdgpu_device *adev);
66static void sdma_v5_2_set_irq_funcs(struct amdgpu_device *adev);
67
68static u32 sdma_v5_2_get_reg_offset(struct amdgpu_device *adev, u32 instance, u32 internal_offset)
69{
70 u32 base;
71
72 if (internal_offset >= SDMA0_HYP_DEC_REG_START &&
73 internal_offset <= SDMA0_HYP_DEC_REG_END) {
74 base = adev->reg_offset[GC_HWIP][0][1];
75 if (instance != 0)
76 internal_offset += SDMA1_HYP_DEC_REG_OFFSET * instance;
77 } else {
78 if (instance < 2) {
79 base = adev->reg_offset[GC_HWIP][0][0];
80 if (instance == 1)
81 internal_offset += SDMA1_REG_OFFSET;
82 } else {
83 base = adev->reg_offset[GC_HWIP][0][2];
84 if (instance == 3)
85 internal_offset += SDMA3_REG_OFFSET;
86 }
87 }
88
89 return base + internal_offset;
90}
91
92/**
93 * sdma_v5_2_init_microcode - load ucode images from disk
94 *
95 * @adev: amdgpu_device pointer
96 *
97 * Use the firmware interface to load the ucode images into
98 * the driver (not loaded into hw).
99 * Returns 0 on success, error on failure.
100 */
101
102// emulation only, won't work on real chip
103// navi10 real chip need to use PSP to load firmware
104static int sdma_v5_2_init_microcode(struct amdgpu_device *adev)
105{
106 const char *chip_name;
107 char fw_name[40];
108
109 DRM_DEBUG("\n");
110
111 switch (adev->ip_versions[SDMA0_HWIP][0]) {
112 case IP_VERSION(5, 2, 0):
113 chip_name = "sienna_cichlid_sdma";
114 break;
115 case IP_VERSION(5, 2, 2):
116 chip_name = "navy_flounder_sdma";
117 break;
118 case IP_VERSION(5, 2, 1):
119 chip_name = "vangogh_sdma";
120 break;
121 case IP_VERSION(5, 2, 4):
122 chip_name = "dimgrey_cavefish_sdma";
123 break;
124 case IP_VERSION(5, 2, 5):
125 chip_name = "beige_goby_sdma";
126 break;
127 case IP_VERSION(5, 2, 3):
128 chip_name = "yellow_carp_sdma";
129 break;
130 case IP_VERSION(5, 2, 6):
131 chip_name = "sdma_5_2_6";
132 break;
133 case IP_VERSION(5, 2, 7):
134 chip_name = "sdma_5_2_7";
135 break;
136 default:
137 BUG();
138 }
139
140 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s.bin", chip_name);
141
142 return amdgpu_sdma_init_microcode(adev, fw_name, 0, true);
143}
144
145static unsigned sdma_v5_2_ring_init_cond_exec(struct amdgpu_ring *ring)
146{
147 unsigned ret;
148
149 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_COND_EXE));
150 amdgpu_ring_write(ring, lower_32_bits(ring->cond_exe_gpu_addr));
151 amdgpu_ring_write(ring, upper_32_bits(ring->cond_exe_gpu_addr));
152 amdgpu_ring_write(ring, 1);
153 ret = ring->wptr & ring->buf_mask;/* this is the offset we need patch later */
154 amdgpu_ring_write(ring, 0x55aa55aa);/* insert dummy here and patch it later */
155
156 return ret;
157}
158
159static void sdma_v5_2_ring_patch_cond_exec(struct amdgpu_ring *ring,
160 unsigned offset)
161{
162 unsigned cur;
163
164 BUG_ON(offset > ring->buf_mask);
165 BUG_ON(ring->ring[offset] != 0x55aa55aa);
166
167 cur = (ring->wptr - 1) & ring->buf_mask;
168 if (cur > offset)
169 ring->ring[offset] = cur - offset;
170 else
171 ring->ring[offset] = (ring->buf_mask + 1) - offset + cur;
172}
173
174/**
175 * sdma_v5_2_ring_get_rptr - get the current read pointer
176 *
177 * @ring: amdgpu ring pointer
178 *
179 * Get the current rptr from the hardware (NAVI10+).
180 */
181static uint64_t sdma_v5_2_ring_get_rptr(struct amdgpu_ring *ring)
182{
183 u64 *rptr;
184
185 /* XXX check if swapping is necessary on BE */
186 rptr = (u64 *)ring->rptr_cpu_addr;
187
188 DRM_DEBUG("rptr before shift == 0x%016llx\n", *rptr);
189 return ((*rptr) >> 2);
190}
191
192/**
193 * sdma_v5_2_ring_get_wptr - get the current write pointer
194 *
195 * @ring: amdgpu ring pointer
196 *
197 * Get the current wptr from the hardware (NAVI10+).
198 */
199static uint64_t sdma_v5_2_ring_get_wptr(struct amdgpu_ring *ring)
200{
201 struct amdgpu_device *adev = ring->adev;
202 u64 wptr;
203
204 if (ring->use_doorbell) {
205 /* XXX check if swapping is necessary on BE */
206 wptr = READ_ONCE(*((u64 *)ring->wptr_cpu_addr));
207 DRM_DEBUG("wptr/doorbell before shift == 0x%016llx\n", wptr);
208 } else {
209 wptr = RREG32(sdma_v5_2_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR_HI));
210 wptr = wptr << 32;
211 wptr |= RREG32(sdma_v5_2_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR));
212 DRM_DEBUG("wptr before shift [%i] wptr == 0x%016llx\n", ring->me, wptr);
213 }
214
215 return wptr >> 2;
216}
217
218/**
219 * sdma_v5_2_ring_set_wptr - commit the write pointer
220 *
221 * @ring: amdgpu ring pointer
222 *
223 * Write the wptr back to the hardware (NAVI10+).
224 */
225static void sdma_v5_2_ring_set_wptr(struct amdgpu_ring *ring)
226{
227 struct amdgpu_device *adev = ring->adev;
228
229 DRM_DEBUG("Setting write pointer\n");
230 if (ring->use_doorbell) {
231 DRM_DEBUG("Using doorbell -- "
232 "wptr_offs == 0x%08x "
233 "lower_32_bits(ring->wptr << 2) == 0x%08x "
234 "upper_32_bits(ring->wptr << 2) == 0x%08x\n",
235 ring->wptr_offs,
236 lower_32_bits(ring->wptr << 2),
237 upper_32_bits(ring->wptr << 2));
238 /* XXX check if swapping is necessary on BE */
239 atomic64_set((atomic64_t *)ring->wptr_cpu_addr,
240 ring->wptr << 2);
241 DRM_DEBUG("calling WDOORBELL64(0x%08x, 0x%016llx)\n",
242 ring->doorbell_index, ring->wptr << 2);
243 WDOORBELL64(ring->doorbell_index, ring->wptr << 2);
244 } else {
245 DRM_DEBUG("Not using doorbell -- "
246 "mmSDMA%i_GFX_RB_WPTR == 0x%08x "
247 "mmSDMA%i_GFX_RB_WPTR_HI == 0x%08x\n",
248 ring->me,
249 lower_32_bits(ring->wptr << 2),
250 ring->me,
251 upper_32_bits(ring->wptr << 2));
252 WREG32(sdma_v5_2_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR),
253 lower_32_bits(ring->wptr << 2));
254 WREG32(sdma_v5_2_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR_HI),
255 upper_32_bits(ring->wptr << 2));
256 }
257}
258
259static void sdma_v5_2_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
260{
261 struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring);
262 int i;
263
264 for (i = 0; i < count; i++)
265 if (sdma && sdma->burst_nop && (i == 0))
266 amdgpu_ring_write(ring, ring->funcs->nop |
267 SDMA_PKT_NOP_HEADER_COUNT(count - 1));
268 else
269 amdgpu_ring_write(ring, ring->funcs->nop);
270}
271
272/**
273 * sdma_v5_2_ring_emit_ib - Schedule an IB on the DMA engine
274 *
275 * @ring: amdgpu ring pointer
276 * @job: job to retrieve vmid from
277 * @ib: IB object to schedule
278 * @flags: unused
279 *
280 * Schedule an IB in the DMA ring.
281 */
282static void sdma_v5_2_ring_emit_ib(struct amdgpu_ring *ring,
283 struct amdgpu_job *job,
284 struct amdgpu_ib *ib,
285 uint32_t flags)
286{
287 unsigned vmid = AMDGPU_JOB_GET_VMID(job);
288 uint64_t csa_mc_addr = amdgpu_sdma_get_csa_mc_addr(ring, vmid);
289
290 /* An IB packet must end on a 8 DW boundary--the next dword
291 * must be on a 8-dword boundary. Our IB packet below is 6
292 * dwords long, thus add x number of NOPs, such that, in
293 * modular arithmetic,
294 * wptr + 6 + x = 8k, k >= 0, which in C is,
295 * (wptr + 6 + x) % 8 = 0.
296 * The expression below, is a solution of x.
297 */
298 sdma_v5_2_ring_insert_nop(ring, (2 - lower_32_bits(ring->wptr)) & 7);
299
300 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) |
301 SDMA_PKT_INDIRECT_HEADER_VMID(vmid & 0xf));
302 /* base must be 32 byte aligned */
303 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0);
304 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
305 amdgpu_ring_write(ring, ib->length_dw);
306 amdgpu_ring_write(ring, lower_32_bits(csa_mc_addr));
307 amdgpu_ring_write(ring, upper_32_bits(csa_mc_addr));
308}
309
310/**
311 * sdma_v5_2_ring_emit_mem_sync - flush the IB by graphics cache rinse
312 *
313 * @ring: amdgpu ring pointer
314 *
315 * flush the IB by graphics cache rinse.
316 */
317static void sdma_v5_2_ring_emit_mem_sync(struct amdgpu_ring *ring)
318{
319 uint32_t gcr_cntl = SDMA_GCR_GL2_INV | SDMA_GCR_GL2_WB |
320 SDMA_GCR_GLM_INV | SDMA_GCR_GL1_INV |
321 SDMA_GCR_GLV_INV | SDMA_GCR_GLK_INV |
322 SDMA_GCR_GLI_INV(1);
323
324 /* flush entire cache L0/L1/L2, this can be optimized by performance requirement */
325 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_GCR_REQ));
326 amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD1_BASE_VA_31_7(0));
327 amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD2_GCR_CONTROL_15_0(gcr_cntl) |
328 SDMA_PKT_GCR_REQ_PAYLOAD2_BASE_VA_47_32(0));
329 amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD3_LIMIT_VA_31_7(0) |
330 SDMA_PKT_GCR_REQ_PAYLOAD3_GCR_CONTROL_18_16(gcr_cntl >> 16));
331 amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD4_LIMIT_VA_47_32(0) |
332 SDMA_PKT_GCR_REQ_PAYLOAD4_VMID(0));
333}
334
335/**
336 * sdma_v5_2_ring_emit_hdp_flush - emit an hdp flush on the DMA ring
337 *
338 * @ring: amdgpu ring pointer
339 *
340 * Emit an hdp flush packet on the requested DMA ring.
341 */
342static void sdma_v5_2_ring_emit_hdp_flush(struct amdgpu_ring *ring)
343{
344 struct amdgpu_device *adev = ring->adev;
345 u32 ref_and_mask = 0;
346 const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg;
347
348 ref_and_mask = nbio_hf_reg->ref_and_mask_sdma0 << ring->me;
349
350 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
351 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(1) |
352 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* == */
353 amdgpu_ring_write(ring, (adev->nbio.funcs->get_hdp_flush_done_offset(adev)) << 2);
354 amdgpu_ring_write(ring, (adev->nbio.funcs->get_hdp_flush_req_offset(adev)) << 2);
355 amdgpu_ring_write(ring, ref_and_mask); /* reference */
356 amdgpu_ring_write(ring, ref_and_mask); /* mask */
357 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
358 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */
359}
360
361/**
362 * sdma_v5_2_ring_emit_fence - emit a fence on the DMA ring
363 *
364 * @ring: amdgpu ring pointer
365 * @addr: address
366 * @seq: sequence number
367 * @flags: fence related flags
368 *
369 * Add a DMA fence packet to the ring to write
370 * the fence seq number and DMA trap packet to generate
371 * an interrupt if needed.
372 */
373static void sdma_v5_2_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
374 unsigned flags)
375{
376 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
377 /* write the fence */
378 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE) |
379 SDMA_PKT_FENCE_HEADER_MTYPE(0x3)); /* Ucached(UC) */
380 /* zero in first two bits */
381 BUG_ON(addr & 0x3);
382 amdgpu_ring_write(ring, lower_32_bits(addr));
383 amdgpu_ring_write(ring, upper_32_bits(addr));
384 amdgpu_ring_write(ring, lower_32_bits(seq));
385
386 /* optionally write high bits as well */
387 if (write64bit) {
388 addr += 4;
389 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE) |
390 SDMA_PKT_FENCE_HEADER_MTYPE(0x3));
391 /* zero in first two bits */
392 BUG_ON(addr & 0x3);
393 amdgpu_ring_write(ring, lower_32_bits(addr));
394 amdgpu_ring_write(ring, upper_32_bits(addr));
395 amdgpu_ring_write(ring, upper_32_bits(seq));
396 }
397
398 if ((flags & AMDGPU_FENCE_FLAG_INT)) {
399 uint32_t ctx = ring->is_mes_queue ?
400 (ring->hw_queue_id | AMDGPU_FENCE_MES_QUEUE_FLAG) : 0;
401 /* generate an interrupt */
402 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_TRAP));
403 amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(ctx));
404 }
405}
406
407
408/**
409 * sdma_v5_2_gfx_stop - stop the gfx async dma engines
410 *
411 * @adev: amdgpu_device pointer
412 *
413 * Stop the gfx async dma ring buffers.
414 */
415static void sdma_v5_2_gfx_stop(struct amdgpu_device *adev)
416{
417 u32 rb_cntl, ib_cntl;
418 int i;
419
420 amdgpu_sdma_unset_buffer_funcs_helper(adev);
421
422 for (i = 0; i < adev->sdma.num_instances; i++) {
423 rb_cntl = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL));
424 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0);
425 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl);
426 ib_cntl = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL));
427 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 0);
428 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL), ib_cntl);
429 }
430}
431
432/**
433 * sdma_v5_2_rlc_stop - stop the compute async dma engines
434 *
435 * @adev: amdgpu_device pointer
436 *
437 * Stop the compute async dma queues.
438 */
439static void sdma_v5_2_rlc_stop(struct amdgpu_device *adev)
440{
441 /* XXX todo */
442}
443
444/**
445 * sdma_v5_2_ctx_switch_enable - stop the async dma engines context switch
446 *
447 * @adev: amdgpu_device pointer
448 * @enable: enable/disable the DMA MEs context switch.
449 *
450 * Halt or unhalt the async dma engines context switch.
451 */
452static void sdma_v5_2_ctx_switch_enable(struct amdgpu_device *adev, bool enable)
453{
454 u32 f32_cntl, phase_quantum = 0;
455 int i;
456
457 if (amdgpu_sdma_phase_quantum) {
458 unsigned value = amdgpu_sdma_phase_quantum;
459 unsigned unit = 0;
460
461 while (value > (SDMA0_PHASE0_QUANTUM__VALUE_MASK >>
462 SDMA0_PHASE0_QUANTUM__VALUE__SHIFT)) {
463 value = (value + 1) >> 1;
464 unit++;
465 }
466 if (unit > (SDMA0_PHASE0_QUANTUM__UNIT_MASK >>
467 SDMA0_PHASE0_QUANTUM__UNIT__SHIFT)) {
468 value = (SDMA0_PHASE0_QUANTUM__VALUE_MASK >>
469 SDMA0_PHASE0_QUANTUM__VALUE__SHIFT);
470 unit = (SDMA0_PHASE0_QUANTUM__UNIT_MASK >>
471 SDMA0_PHASE0_QUANTUM__UNIT__SHIFT);
472 WARN_ONCE(1,
473 "clamping sdma_phase_quantum to %uK clock cycles\n",
474 value << unit);
475 }
476 phase_quantum =
477 value << SDMA0_PHASE0_QUANTUM__VALUE__SHIFT |
478 unit << SDMA0_PHASE0_QUANTUM__UNIT__SHIFT;
479 }
480
481 for (i = 0; i < adev->sdma.num_instances; i++) {
482 if (enable && amdgpu_sdma_phase_quantum) {
483 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_PHASE0_QUANTUM),
484 phase_quantum);
485 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_PHASE1_QUANTUM),
486 phase_quantum);
487 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_PHASE2_QUANTUM),
488 phase_quantum);
489 }
490
491 if (!amdgpu_sriov_vf(adev)) {
492 f32_cntl = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CNTL));
493 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,
494 AUTO_CTXSW_ENABLE, enable ? 1 : 0);
495 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CNTL), f32_cntl);
496 }
497 }
498
499}
500
501/**
502 * sdma_v5_2_enable - stop the async dma engines
503 *
504 * @adev: amdgpu_device pointer
505 * @enable: enable/disable the DMA MEs.
506 *
507 * Halt or unhalt the async dma engines.
508 */
509static void sdma_v5_2_enable(struct amdgpu_device *adev, bool enable)
510{
511 u32 f32_cntl;
512 int i;
513
514 if (!enable) {
515 sdma_v5_2_gfx_stop(adev);
516 sdma_v5_2_rlc_stop(adev);
517 }
518
519 if (!amdgpu_sriov_vf(adev)) {
520 for (i = 0; i < adev->sdma.num_instances; i++) {
521 f32_cntl = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_F32_CNTL));
522 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, enable ? 0 : 1);
523 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_F32_CNTL), f32_cntl);
524 }
525 }
526}
527
528/**
529 * sdma_v5_2_gfx_resume - setup and start the async dma engines
530 *
531 * @adev: amdgpu_device pointer
532 *
533 * Set up the gfx DMA ring buffers and enable them.
534 * Returns 0 for success, error for failure.
535 */
536static int sdma_v5_2_gfx_resume(struct amdgpu_device *adev)
537{
538 struct amdgpu_ring *ring;
539 u32 rb_cntl, ib_cntl;
540 u32 rb_bufsz;
541 u32 doorbell;
542 u32 doorbell_offset;
543 u32 temp;
544 u32 wptr_poll_cntl;
545 u64 wptr_gpu_addr;
546 int i, r;
547
548 for (i = 0; i < adev->sdma.num_instances; i++) {
549 ring = &adev->sdma.instance[i].ring;
550
551 if (!amdgpu_sriov_vf(adev))
552 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL), 0);
553
554 /* Set ring buffer size in dwords */
555 rb_bufsz = order_base_2(ring->ring_size / 4);
556 rb_cntl = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL));
557 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz);
558#ifdef __BIG_ENDIAN
559 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1);
560 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL,
561 RPTR_WRITEBACK_SWAP_ENABLE, 1);
562#endif
563 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl);
564
565 /* Initialize the ring buffer's read and write pointers */
566 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR), 0);
567 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_HI), 0);
568 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), 0);
569 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI), 0);
570
571 /* setup the wptr shadow polling */
572 wptr_gpu_addr = ring->wptr_gpu_addr;
573 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO),
574 lower_32_bits(wptr_gpu_addr));
575 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI),
576 upper_32_bits(wptr_gpu_addr));
577 wptr_poll_cntl = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i,
578 mmSDMA0_GFX_RB_WPTR_POLL_CNTL));
579 wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl,
580 SDMA0_GFX_RB_WPTR_POLL_CNTL,
581 F32_POLL_ENABLE, 1);
582 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_CNTL),
583 wptr_poll_cntl);
584
585 /* set the wb address whether it's enabled or not */
586 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_ADDR_HI),
587 upper_32_bits(ring->rptr_gpu_addr) & 0xFFFFFFFF);
588 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_ADDR_LO),
589 lower_32_bits(ring->rptr_gpu_addr) & 0xFFFFFFFC);
590
591 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1);
592
593 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_BASE), ring->gpu_addr >> 8);
594 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_BASE_HI), ring->gpu_addr >> 40);
595
596 ring->wptr = 0;
597
598 /* before programing wptr to a less value, need set minor_ptr_update first */
599 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_MINOR_PTR_UPDATE), 1);
600
601 if (!amdgpu_sriov_vf(adev)) { /* only bare-metal use register write for wptr */
602 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), lower_32_bits(ring->wptr << 2));
603 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI), upper_32_bits(ring->wptr << 2));
604 }
605
606 doorbell = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL));
607 doorbell_offset = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL_OFFSET));
608
609 if (ring->use_doorbell) {
610 doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 1);
611 doorbell_offset = REG_SET_FIELD(doorbell_offset, SDMA0_GFX_DOORBELL_OFFSET,
612 OFFSET, ring->doorbell_index);
613 } else {
614 doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 0);
615 }
616 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL), doorbell);
617 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL_OFFSET), doorbell_offset);
618
619 adev->nbio.funcs->sdma_doorbell_range(adev, i, ring->use_doorbell,
620 ring->doorbell_index,
621 adev->doorbell_index.sdma_doorbell_range);
622
623 if (amdgpu_sriov_vf(adev))
624 sdma_v5_2_ring_set_wptr(ring);
625
626 /* set minor_ptr_update to 0 after wptr programed */
627
628 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_MINOR_PTR_UPDATE), 0);
629
630 /* SRIOV VF has no control of any of registers below */
631 if (!amdgpu_sriov_vf(adev)) {
632 /* set utc l1 enable flag always to 1 */
633 temp = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CNTL));
634 temp = REG_SET_FIELD(temp, SDMA0_CNTL, UTC_L1_ENABLE, 1);
635
636 /* enable MCBP */
637 temp = REG_SET_FIELD(temp, SDMA0_CNTL, MIDCMD_PREEMPT_ENABLE, 1);
638 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CNTL), temp);
639
640 /* Set up RESP_MODE to non-copy addresses */
641 temp = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UTCL1_CNTL));
642 temp = REG_SET_FIELD(temp, SDMA0_UTCL1_CNTL, RESP_MODE, 3);
643 temp = REG_SET_FIELD(temp, SDMA0_UTCL1_CNTL, REDO_DELAY, 9);
644 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UTCL1_CNTL), temp);
645
646 /* program default cache read and write policy */
647 temp = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UTCL1_PAGE));
648 /* clean read policy and write policy bits */
649 temp &= 0xFF0FFF;
650 temp |= ((CACHE_READ_POLICY_L2__DEFAULT << 12) |
651 (CACHE_WRITE_POLICY_L2__DEFAULT << 14) |
652 SDMA0_UTCL1_PAGE__LLC_NOALLOC_MASK);
653 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UTCL1_PAGE), temp);
654
655 /* unhalt engine */
656 temp = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_F32_CNTL));
657 temp = REG_SET_FIELD(temp, SDMA0_F32_CNTL, HALT, 0);
658 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_F32_CNTL), temp);
659 }
660
661 /* enable DMA RB */
662 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1);
663 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl);
664
665 ib_cntl = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL));
666 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 1);
667#ifdef __BIG_ENDIAN
668 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_SWAP_ENABLE, 1);
669#endif
670 /* enable DMA IBs */
671 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL), ib_cntl);
672
673 ring->sched.ready = true;
674
675 if (amdgpu_sriov_vf(adev)) { /* bare-metal sequence doesn't need below to lines */
676 sdma_v5_2_ctx_switch_enable(adev, true);
677 sdma_v5_2_enable(adev, true);
678 }
679
680 r = amdgpu_ring_test_ring(ring);
681 if (r) {
682 ring->sched.ready = false;
683 return r;
684 }
685
686 if (adev->mman.buffer_funcs_ring == ring)
687 amdgpu_ttm_set_buffer_funcs_status(adev, true);
688 }
689
690 return 0;
691}
692
693/**
694 * sdma_v5_2_rlc_resume - setup and start the async dma engines
695 *
696 * @adev: amdgpu_device pointer
697 *
698 * Set up the compute DMA queues and enable them.
699 * Returns 0 for success, error for failure.
700 */
701static int sdma_v5_2_rlc_resume(struct amdgpu_device *adev)
702{
703 return 0;
704}
705
706/**
707 * sdma_v5_2_load_microcode - load the sDMA ME ucode
708 *
709 * @adev: amdgpu_device pointer
710 *
711 * Loads the sDMA0/1/2/3 ucode.
712 * Returns 0 for success, -EINVAL if the ucode is not available.
713 */
714static int sdma_v5_2_load_microcode(struct amdgpu_device *adev)
715{
716 const struct sdma_firmware_header_v1_0 *hdr;
717 const __le32 *fw_data;
718 u32 fw_size;
719 int i, j;
720
721 /* halt the MEs */
722 sdma_v5_2_enable(adev, false);
723
724 for (i = 0; i < adev->sdma.num_instances; i++) {
725 if (!adev->sdma.instance[i].fw)
726 return -EINVAL;
727
728 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data;
729 amdgpu_ucode_print_sdma_hdr(&hdr->header);
730 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
731
732 fw_data = (const __le32 *)
733 (adev->sdma.instance[i].fw->data +
734 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
735
736 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UCODE_ADDR), 0);
737
738 for (j = 0; j < fw_size; j++) {
739 if (amdgpu_emu_mode == 1 && j % 500 == 0)
740 msleep(1);
741 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UCODE_DATA), le32_to_cpup(fw_data++));
742 }
743
744 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UCODE_ADDR), adev->sdma.instance[i].fw_version);
745 }
746
747 return 0;
748}
749
750static int sdma_v5_2_soft_reset(void *handle)
751{
752 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
753 u32 grbm_soft_reset;
754 u32 tmp;
755 int i;
756
757 for (i = 0; i < adev->sdma.num_instances; i++) {
758 grbm_soft_reset = REG_SET_FIELD(0,
759 GRBM_SOFT_RESET, SOFT_RESET_SDMA0,
760 1);
761 grbm_soft_reset <<= i;
762
763 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
764 tmp |= grbm_soft_reset;
765 DRM_DEBUG("GRBM_SOFT_RESET=0x%08X\n", tmp);
766 WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp);
767 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
768
769 udelay(50);
770
771 tmp &= ~grbm_soft_reset;
772 WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp);
773 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
774
775 udelay(50);
776 }
777
778 return 0;
779}
780
781/**
782 * sdma_v5_2_start - setup and start the async dma engines
783 *
784 * @adev: amdgpu_device pointer
785 *
786 * Set up the DMA engines and enable them.
787 * Returns 0 for success, error for failure.
788 */
789static int sdma_v5_2_start(struct amdgpu_device *adev)
790{
791 int r = 0;
792
793 if (amdgpu_sriov_vf(adev)) {
794 sdma_v5_2_ctx_switch_enable(adev, false);
795 sdma_v5_2_enable(adev, false);
796
797 /* set RB registers */
798 r = sdma_v5_2_gfx_resume(adev);
799 return r;
800 }
801
802 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
803 r = sdma_v5_2_load_microcode(adev);
804 if (r)
805 return r;
806
807 /* The value of mmSDMA_F32_CNTL is invalid the moment after loading fw */
808 if (amdgpu_emu_mode == 1)
809 msleep(1000);
810 }
811
812 /* TODO: check whether can submit a doorbell request to raise
813 * a doorbell fence to exit gfxoff.
814 */
815 if (adev->in_s0ix)
816 amdgpu_gfx_off_ctrl(adev, false);
817
818 sdma_v5_2_soft_reset(adev);
819 /* unhalt the MEs */
820 sdma_v5_2_enable(adev, true);
821 /* enable sdma ring preemption */
822 sdma_v5_2_ctx_switch_enable(adev, true);
823
824 /* start the gfx rings and rlc compute queues */
825 r = sdma_v5_2_gfx_resume(adev);
826 if (adev->in_s0ix)
827 amdgpu_gfx_off_ctrl(adev, true);
828 if (r)
829 return r;
830 r = sdma_v5_2_rlc_resume(adev);
831
832 return r;
833}
834
835static int sdma_v5_2_mqd_init(struct amdgpu_device *adev, void *mqd,
836 struct amdgpu_mqd_prop *prop)
837{
838 struct v10_sdma_mqd *m = mqd;
839 uint64_t wb_gpu_addr;
840
841 m->sdmax_rlcx_rb_cntl =
842 order_base_2(prop->queue_size / 4) << SDMA0_RLC0_RB_CNTL__RB_SIZE__SHIFT |
843 1 << SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT |
844 6 << SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT |
845 1 << SDMA0_RLC0_RB_CNTL__RB_PRIV__SHIFT;
846
847 m->sdmax_rlcx_rb_base = lower_32_bits(prop->hqd_base_gpu_addr >> 8);
848 m->sdmax_rlcx_rb_base_hi = upper_32_bits(prop->hqd_base_gpu_addr >> 8);
849
850 m->sdmax_rlcx_rb_wptr_poll_cntl = RREG32(sdma_v5_2_get_reg_offset(adev, 0,
851 mmSDMA0_GFX_RB_WPTR_POLL_CNTL));
852
853 wb_gpu_addr = prop->wptr_gpu_addr;
854 m->sdmax_rlcx_rb_wptr_poll_addr_lo = lower_32_bits(wb_gpu_addr);
855 m->sdmax_rlcx_rb_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr);
856
857 wb_gpu_addr = prop->rptr_gpu_addr;
858 m->sdmax_rlcx_rb_rptr_addr_lo = lower_32_bits(wb_gpu_addr);
859 m->sdmax_rlcx_rb_rptr_addr_hi = upper_32_bits(wb_gpu_addr);
860
861 m->sdmax_rlcx_ib_cntl = RREG32(sdma_v5_2_get_reg_offset(adev, 0,
862 mmSDMA0_GFX_IB_CNTL));
863
864 m->sdmax_rlcx_doorbell_offset =
865 prop->doorbell_index << SDMA0_RLC0_DOORBELL_OFFSET__OFFSET__SHIFT;
866
867 m->sdmax_rlcx_doorbell = REG_SET_FIELD(0, SDMA0_RLC0_DOORBELL, ENABLE, 1);
868
869 return 0;
870}
871
872static void sdma_v5_2_set_mqd_funcs(struct amdgpu_device *adev)
873{
874 adev->mqds[AMDGPU_HW_IP_DMA].mqd_size = sizeof(struct v10_sdma_mqd);
875 adev->mqds[AMDGPU_HW_IP_DMA].init_mqd = sdma_v5_2_mqd_init;
876}
877
878/**
879 * sdma_v5_2_ring_test_ring - simple async dma engine test
880 *
881 * @ring: amdgpu_ring structure holding ring information
882 *
883 * Test the DMA engine by writing using it to write an
884 * value to memory.
885 * Returns 0 for success, error for failure.
886 */
887static int sdma_v5_2_ring_test_ring(struct amdgpu_ring *ring)
888{
889 struct amdgpu_device *adev = ring->adev;
890 unsigned i;
891 unsigned index;
892 int r;
893 u32 tmp;
894 u64 gpu_addr;
895 volatile uint32_t *cpu_ptr = NULL;
896
897 tmp = 0xCAFEDEAD;
898
899 if (ring->is_mes_queue) {
900 uint32_t offset = 0;
901 offset = amdgpu_mes_ctx_get_offs(ring,
902 AMDGPU_MES_CTX_PADDING_OFFS);
903 gpu_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset);
904 cpu_ptr = amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset);
905 *cpu_ptr = tmp;
906 } else {
907 r = amdgpu_device_wb_get(adev, &index);
908 if (r) {
909 dev_err(adev->dev, "(%d) failed to allocate wb slot\n", r);
910 return r;
911 }
912
913 gpu_addr = adev->wb.gpu_addr + (index * 4);
914 adev->wb.wb[index] = cpu_to_le32(tmp);
915 }
916
917 r = amdgpu_ring_alloc(ring, 20);
918 if (r) {
919 DRM_ERROR("amdgpu: dma failed to lock ring %d (%d).\n", ring->idx, r);
920 amdgpu_device_wb_free(adev, index);
921 return r;
922 }
923
924 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
925 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR));
926 amdgpu_ring_write(ring, lower_32_bits(gpu_addr));
927 amdgpu_ring_write(ring, upper_32_bits(gpu_addr));
928 amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0));
929 amdgpu_ring_write(ring, 0xDEADBEEF);
930 amdgpu_ring_commit(ring);
931
932 for (i = 0; i < adev->usec_timeout; i++) {
933 if (ring->is_mes_queue)
934 tmp = le32_to_cpu(*cpu_ptr);
935 else
936 tmp = le32_to_cpu(adev->wb.wb[index]);
937 if (tmp == 0xDEADBEEF)
938 break;
939 if (amdgpu_emu_mode == 1)
940 msleep(1);
941 else
942 udelay(1);
943 }
944
945 if (i >= adev->usec_timeout)
946 r = -ETIMEDOUT;
947
948 if (!ring->is_mes_queue)
949 amdgpu_device_wb_free(adev, index);
950
951 return r;
952}
953
954/**
955 * sdma_v5_2_ring_test_ib - test an IB on the DMA engine
956 *
957 * @ring: amdgpu_ring structure holding ring information
958 * @timeout: timeout value in jiffies, or MAX_SCHEDULE_TIMEOUT
959 *
960 * Test a simple IB in the DMA ring.
961 * Returns 0 on success, error on failure.
962 */
963static int sdma_v5_2_ring_test_ib(struct amdgpu_ring *ring, long timeout)
964{
965 struct amdgpu_device *adev = ring->adev;
966 struct amdgpu_ib ib;
967 struct dma_fence *f = NULL;
968 unsigned index;
969 long r;
970 u32 tmp = 0;
971 u64 gpu_addr;
972 volatile uint32_t *cpu_ptr = NULL;
973
974 tmp = 0xCAFEDEAD;
975 memset(&ib, 0, sizeof(ib));
976
977 if (ring->is_mes_queue) {
978 uint32_t offset = 0;
979 offset = amdgpu_mes_ctx_get_offs(ring, AMDGPU_MES_CTX_IB_OFFS);
980 ib.gpu_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset);
981 ib.ptr = (void *)amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset);
982
983 offset = amdgpu_mes_ctx_get_offs(ring,
984 AMDGPU_MES_CTX_PADDING_OFFS);
985 gpu_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset);
986 cpu_ptr = amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset);
987 *cpu_ptr = tmp;
988 } else {
989 r = amdgpu_device_wb_get(adev, &index);
990 if (r) {
991 dev_err(adev->dev, "(%ld) failed to allocate wb slot\n", r);
992 return r;
993 }
994
995 gpu_addr = adev->wb.gpu_addr + (index * 4);
996 adev->wb.wb[index] = cpu_to_le32(tmp);
997
998 r = amdgpu_ib_get(adev, NULL, 256, AMDGPU_IB_POOL_DIRECT, &ib);
999 if (r) {
1000 DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r);
1001 goto err0;
1002 }
1003 }
1004
1005 ib.ptr[0] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
1006 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR);
1007 ib.ptr[1] = lower_32_bits(gpu_addr);
1008 ib.ptr[2] = upper_32_bits(gpu_addr);
1009 ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0);
1010 ib.ptr[4] = 0xDEADBEEF;
1011 ib.ptr[5] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
1012 ib.ptr[6] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
1013 ib.ptr[7] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
1014 ib.length_dw = 8;
1015
1016 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
1017 if (r)
1018 goto err1;
1019
1020 r = dma_fence_wait_timeout(f, false, timeout);
1021 if (r == 0) {
1022 DRM_ERROR("amdgpu: IB test timed out\n");
1023 r = -ETIMEDOUT;
1024 goto err1;
1025 } else if (r < 0) {
1026 DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r);
1027 goto err1;
1028 }
1029
1030 if (ring->is_mes_queue)
1031 tmp = le32_to_cpu(*cpu_ptr);
1032 else
1033 tmp = le32_to_cpu(adev->wb.wb[index]);
1034
1035 if (tmp == 0xDEADBEEF)
1036 r = 0;
1037 else
1038 r = -EINVAL;
1039
1040err1:
1041 amdgpu_ib_free(adev, &ib, NULL);
1042 dma_fence_put(f);
1043err0:
1044 if (!ring->is_mes_queue)
1045 amdgpu_device_wb_free(adev, index);
1046 return r;
1047}
1048
1049
1050/**
1051 * sdma_v5_2_vm_copy_pte - update PTEs by copying them from the GART
1052 *
1053 * @ib: indirect buffer to fill with commands
1054 * @pe: addr of the page entry
1055 * @src: src addr to copy from
1056 * @count: number of page entries to update
1057 *
1058 * Update PTEs by copying them from the GART using sDMA.
1059 */
1060static void sdma_v5_2_vm_copy_pte(struct amdgpu_ib *ib,
1061 uint64_t pe, uint64_t src,
1062 unsigned count)
1063{
1064 unsigned bytes = count * 8;
1065
1066 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
1067 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR);
1068 ib->ptr[ib->length_dw++] = bytes - 1;
1069 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
1070 ib->ptr[ib->length_dw++] = lower_32_bits(src);
1071 ib->ptr[ib->length_dw++] = upper_32_bits(src);
1072 ib->ptr[ib->length_dw++] = lower_32_bits(pe);
1073 ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1074
1075}
1076
1077/**
1078 * sdma_v5_2_vm_write_pte - update PTEs by writing them manually
1079 *
1080 * @ib: indirect buffer to fill with commands
1081 * @pe: addr of the page entry
1082 * @value: dst addr to write into pe
1083 * @count: number of page entries to update
1084 * @incr: increase next addr by incr bytes
1085 *
1086 * Update PTEs by writing them manually using sDMA.
1087 */
1088static void sdma_v5_2_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe,
1089 uint64_t value, unsigned count,
1090 uint32_t incr)
1091{
1092 unsigned ndw = count * 2;
1093
1094 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
1095 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR);
1096 ib->ptr[ib->length_dw++] = lower_32_bits(pe);
1097 ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1098 ib->ptr[ib->length_dw++] = ndw - 1;
1099 for (; ndw > 0; ndw -= 2) {
1100 ib->ptr[ib->length_dw++] = lower_32_bits(value);
1101 ib->ptr[ib->length_dw++] = upper_32_bits(value);
1102 value += incr;
1103 }
1104}
1105
1106/**
1107 * sdma_v5_2_vm_set_pte_pde - update the page tables using sDMA
1108 *
1109 * @ib: indirect buffer to fill with commands
1110 * @pe: addr of the page entry
1111 * @addr: dst addr to write into pe
1112 * @count: number of page entries to update
1113 * @incr: increase next addr by incr bytes
1114 * @flags: access flags
1115 *
1116 * Update the page tables using sDMA.
1117 */
1118static void sdma_v5_2_vm_set_pte_pde(struct amdgpu_ib *ib,
1119 uint64_t pe,
1120 uint64_t addr, unsigned count,
1121 uint32_t incr, uint64_t flags)
1122{
1123 /* for physically contiguous pages (vram) */
1124 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_PTEPDE);
1125 ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */
1126 ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1127 ib->ptr[ib->length_dw++] = lower_32_bits(flags); /* mask */
1128 ib->ptr[ib->length_dw++] = upper_32_bits(flags);
1129 ib->ptr[ib->length_dw++] = lower_32_bits(addr); /* value */
1130 ib->ptr[ib->length_dw++] = upper_32_bits(addr);
1131 ib->ptr[ib->length_dw++] = incr; /* increment size */
1132 ib->ptr[ib->length_dw++] = 0;
1133 ib->ptr[ib->length_dw++] = count - 1; /* number of entries */
1134}
1135
1136/**
1137 * sdma_v5_2_ring_pad_ib - pad the IB
1138 *
1139 * @ib: indirect buffer to fill with padding
1140 * @ring: amdgpu_ring structure holding ring information
1141 *
1142 * Pad the IB with NOPs to a boundary multiple of 8.
1143 */
1144static void sdma_v5_2_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib)
1145{
1146 struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring);
1147 u32 pad_count;
1148 int i;
1149
1150 pad_count = (-ib->length_dw) & 0x7;
1151 for (i = 0; i < pad_count; i++)
1152 if (sdma && sdma->burst_nop && (i == 0))
1153 ib->ptr[ib->length_dw++] =
1154 SDMA_PKT_HEADER_OP(SDMA_OP_NOP) |
1155 SDMA_PKT_NOP_HEADER_COUNT(pad_count - 1);
1156 else
1157 ib->ptr[ib->length_dw++] =
1158 SDMA_PKT_HEADER_OP(SDMA_OP_NOP);
1159}
1160
1161
1162/**
1163 * sdma_v5_2_ring_emit_pipeline_sync - sync the pipeline
1164 *
1165 * @ring: amdgpu_ring pointer
1166 *
1167 * Make sure all previous operations are completed (CIK).
1168 */
1169static void sdma_v5_2_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
1170{
1171 uint32_t seq = ring->fence_drv.sync_seq;
1172 uint64_t addr = ring->fence_drv.gpu_addr;
1173
1174 /* wait for idle */
1175 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
1176 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) |
1177 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3) | /* equal */
1178 SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL(1));
1179 amdgpu_ring_write(ring, addr & 0xfffffffc);
1180 amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff);
1181 amdgpu_ring_write(ring, seq); /* reference */
1182 amdgpu_ring_write(ring, 0xffffffff); /* mask */
1183 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
1184 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(4)); /* retry count, poll interval */
1185}
1186
1187
1188/**
1189 * sdma_v5_2_ring_emit_vm_flush - vm flush using sDMA
1190 *
1191 * @ring: amdgpu_ring pointer
1192 * @vmid: vmid number to use
1193 * @pd_addr: address
1194 *
1195 * Update the page table base and flush the VM TLB
1196 * using sDMA.
1197 */
1198static void sdma_v5_2_ring_emit_vm_flush(struct amdgpu_ring *ring,
1199 unsigned vmid, uint64_t pd_addr)
1200{
1201 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
1202}
1203
1204static void sdma_v5_2_ring_emit_wreg(struct amdgpu_ring *ring,
1205 uint32_t reg, uint32_t val)
1206{
1207 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
1208 SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
1209 amdgpu_ring_write(ring, reg);
1210 amdgpu_ring_write(ring, val);
1211}
1212
1213static void sdma_v5_2_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
1214 uint32_t val, uint32_t mask)
1215{
1216 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
1217 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) |
1218 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* equal */
1219 amdgpu_ring_write(ring, reg << 2);
1220 amdgpu_ring_write(ring, 0);
1221 amdgpu_ring_write(ring, val); /* reference */
1222 amdgpu_ring_write(ring, mask); /* mask */
1223 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
1224 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10));
1225}
1226
1227static void sdma_v5_2_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring,
1228 uint32_t reg0, uint32_t reg1,
1229 uint32_t ref, uint32_t mask)
1230{
1231 amdgpu_ring_emit_wreg(ring, reg0, ref);
1232 /* wait for a cycle to reset vm_inv_eng*_ack */
1233 amdgpu_ring_emit_reg_wait(ring, reg0, 0, 0);
1234 amdgpu_ring_emit_reg_wait(ring, reg1, mask, mask);
1235}
1236
1237static int sdma_v5_2_early_init(void *handle)
1238{
1239 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1240
1241 sdma_v5_2_set_ring_funcs(adev);
1242 sdma_v5_2_set_buffer_funcs(adev);
1243 sdma_v5_2_set_vm_pte_funcs(adev);
1244 sdma_v5_2_set_irq_funcs(adev);
1245 sdma_v5_2_set_mqd_funcs(adev);
1246
1247 return 0;
1248}
1249
1250static unsigned sdma_v5_2_seq_to_irq_id(int seq_num)
1251{
1252 switch (seq_num) {
1253 case 0:
1254 return SOC15_IH_CLIENTID_SDMA0;
1255 case 1:
1256 return SOC15_IH_CLIENTID_SDMA1;
1257 case 2:
1258 return SOC15_IH_CLIENTID_SDMA2;
1259 case 3:
1260 return SOC15_IH_CLIENTID_SDMA3_Sienna_Cichlid;
1261 default:
1262 break;
1263 }
1264 return -EINVAL;
1265}
1266
1267static unsigned sdma_v5_2_seq_to_trap_id(int seq_num)
1268{
1269 switch (seq_num) {
1270 case 0:
1271 return SDMA0_5_0__SRCID__SDMA_TRAP;
1272 case 1:
1273 return SDMA1_5_0__SRCID__SDMA_TRAP;
1274 case 2:
1275 return SDMA2_5_0__SRCID__SDMA_TRAP;
1276 case 3:
1277 return SDMA3_5_0__SRCID__SDMA_TRAP;
1278 default:
1279 break;
1280 }
1281 return -EINVAL;
1282}
1283
1284static int sdma_v5_2_sw_init(void *handle)
1285{
1286 struct amdgpu_ring *ring;
1287 int r, i;
1288 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1289
1290 /* SDMA trap event */
1291 for (i = 0; i < adev->sdma.num_instances; i++) {
1292 r = amdgpu_irq_add_id(adev, sdma_v5_2_seq_to_irq_id(i),
1293 sdma_v5_2_seq_to_trap_id(i),
1294 &adev->sdma.trap_irq);
1295 if (r)
1296 return r;
1297 }
1298
1299 r = sdma_v5_2_init_microcode(adev);
1300 if (r) {
1301 DRM_ERROR("Failed to load sdma firmware!\n");
1302 return r;
1303 }
1304
1305 for (i = 0; i < adev->sdma.num_instances; i++) {
1306 ring = &adev->sdma.instance[i].ring;
1307 ring->ring_obj = NULL;
1308 ring->use_doorbell = true;
1309 ring->me = i;
1310
1311 DRM_INFO("use_doorbell being set to: [%s]\n",
1312 ring->use_doorbell?"true":"false");
1313
1314 ring->doorbell_index =
1315 (adev->doorbell_index.sdma_engine[i] << 1); //get DWORD offset
1316
1317 sprintf(ring->name, "sdma%d", i);
1318 r = amdgpu_ring_init(adev, ring, 1024, &adev->sdma.trap_irq,
1319 AMDGPU_SDMA_IRQ_INSTANCE0 + i,
1320 AMDGPU_RING_PRIO_DEFAULT, NULL);
1321 if (r)
1322 return r;
1323 }
1324
1325 return r;
1326}
1327
1328static int sdma_v5_2_sw_fini(void *handle)
1329{
1330 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1331 int i;
1332
1333 for (i = 0; i < adev->sdma.num_instances; i++)
1334 amdgpu_ring_fini(&adev->sdma.instance[i].ring);
1335
1336 amdgpu_sdma_destroy_inst_ctx(adev, true);
1337
1338 return 0;
1339}
1340
1341static int sdma_v5_2_hw_init(void *handle)
1342{
1343 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1344
1345 return sdma_v5_2_start(adev);
1346}
1347
1348static int sdma_v5_2_hw_fini(void *handle)
1349{
1350 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1351
1352 if (amdgpu_sriov_vf(adev)) {
1353 /* disable the scheduler for SDMA */
1354 amdgpu_sdma_unset_buffer_funcs_helper(adev);
1355 return 0;
1356 }
1357
1358 sdma_v5_2_ctx_switch_enable(adev, false);
1359 sdma_v5_2_enable(adev, false);
1360
1361 return 0;
1362}
1363
1364static int sdma_v5_2_suspend(void *handle)
1365{
1366 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1367
1368 return sdma_v5_2_hw_fini(adev);
1369}
1370
1371static int sdma_v5_2_resume(void *handle)
1372{
1373 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1374
1375 return sdma_v5_2_hw_init(adev);
1376}
1377
1378static bool sdma_v5_2_is_idle(void *handle)
1379{
1380 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1381 u32 i;
1382
1383 for (i = 0; i < adev->sdma.num_instances; i++) {
1384 u32 tmp = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_STATUS_REG));
1385
1386 if (!(tmp & SDMA0_STATUS_REG__IDLE_MASK))
1387 return false;
1388 }
1389
1390 return true;
1391}
1392
1393static int sdma_v5_2_wait_for_idle(void *handle)
1394{
1395 unsigned i;
1396 u32 sdma0, sdma1, sdma2, sdma3;
1397 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1398
1399 for (i = 0; i < adev->usec_timeout; i++) {
1400 sdma0 = RREG32(sdma_v5_2_get_reg_offset(adev, 0, mmSDMA0_STATUS_REG));
1401 sdma1 = RREG32(sdma_v5_2_get_reg_offset(adev, 1, mmSDMA0_STATUS_REG));
1402 sdma2 = RREG32(sdma_v5_2_get_reg_offset(adev, 2, mmSDMA0_STATUS_REG));
1403 sdma3 = RREG32(sdma_v5_2_get_reg_offset(adev, 3, mmSDMA0_STATUS_REG));
1404
1405 if (sdma0 & sdma1 & sdma2 & sdma3 & SDMA0_STATUS_REG__IDLE_MASK)
1406 return 0;
1407 udelay(1);
1408 }
1409 return -ETIMEDOUT;
1410}
1411
1412static int sdma_v5_2_ring_preempt_ib(struct amdgpu_ring *ring)
1413{
1414 int i, r = 0;
1415 struct amdgpu_device *adev = ring->adev;
1416 u32 index = 0;
1417 u64 sdma_gfx_preempt;
1418
1419 amdgpu_sdma_get_index_from_ring(ring, &index);
1420 sdma_gfx_preempt =
1421 sdma_v5_2_get_reg_offset(adev, index, mmSDMA0_GFX_PREEMPT);
1422
1423 /* assert preemption condition */
1424 amdgpu_ring_set_preempt_cond_exec(ring, false);
1425
1426 /* emit the trailing fence */
1427 ring->trail_seq += 1;
1428 amdgpu_ring_alloc(ring, 10);
1429 sdma_v5_2_ring_emit_fence(ring, ring->trail_fence_gpu_addr,
1430 ring->trail_seq, 0);
1431 amdgpu_ring_commit(ring);
1432
1433 /* assert IB preemption */
1434 WREG32(sdma_gfx_preempt, 1);
1435
1436 /* poll the trailing fence */
1437 for (i = 0; i < adev->usec_timeout; i++) {
1438 if (ring->trail_seq ==
1439 le32_to_cpu(*(ring->trail_fence_cpu_addr)))
1440 break;
1441 udelay(1);
1442 }
1443
1444 if (i >= adev->usec_timeout) {
1445 r = -EINVAL;
1446 DRM_ERROR("ring %d failed to be preempted\n", ring->idx);
1447 }
1448
1449 /* deassert IB preemption */
1450 WREG32(sdma_gfx_preempt, 0);
1451
1452 /* deassert the preemption condition */
1453 amdgpu_ring_set_preempt_cond_exec(ring, true);
1454 return r;
1455}
1456
1457static int sdma_v5_2_set_trap_irq_state(struct amdgpu_device *adev,
1458 struct amdgpu_irq_src *source,
1459 unsigned type,
1460 enum amdgpu_interrupt_state state)
1461{
1462 u32 sdma_cntl;
1463 u32 reg_offset = sdma_v5_2_get_reg_offset(adev, type, mmSDMA0_CNTL);
1464
1465 if (!amdgpu_sriov_vf(adev)) {
1466 sdma_cntl = RREG32(reg_offset);
1467 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE,
1468 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
1469 WREG32(reg_offset, sdma_cntl);
1470 }
1471
1472 return 0;
1473}
1474
1475static int sdma_v5_2_process_trap_irq(struct amdgpu_device *adev,
1476 struct amdgpu_irq_src *source,
1477 struct amdgpu_iv_entry *entry)
1478{
1479 uint32_t mes_queue_id = entry->src_data[0];
1480
1481 DRM_DEBUG("IH: SDMA trap\n");
1482
1483 if (adev->enable_mes && (mes_queue_id & AMDGPU_FENCE_MES_QUEUE_FLAG)) {
1484 struct amdgpu_mes_queue *queue;
1485
1486 mes_queue_id &= AMDGPU_FENCE_MES_QUEUE_ID_MASK;
1487
1488 spin_lock(&adev->mes.queue_id_lock);
1489 queue = idr_find(&adev->mes.queue_id_idr, mes_queue_id);
1490 if (queue) {
1491 DRM_DEBUG("process smda queue id = %d\n", mes_queue_id);
1492 amdgpu_fence_process(queue->ring);
1493 }
1494 spin_unlock(&adev->mes.queue_id_lock);
1495 return 0;
1496 }
1497
1498 switch (entry->client_id) {
1499 case SOC15_IH_CLIENTID_SDMA0:
1500 switch (entry->ring_id) {
1501 case 0:
1502 amdgpu_fence_process(&adev->sdma.instance[0].ring);
1503 break;
1504 case 1:
1505 /* XXX compute */
1506 break;
1507 case 2:
1508 /* XXX compute */
1509 break;
1510 case 3:
1511 /* XXX page queue*/
1512 break;
1513 }
1514 break;
1515 case SOC15_IH_CLIENTID_SDMA1:
1516 switch (entry->ring_id) {
1517 case 0:
1518 amdgpu_fence_process(&adev->sdma.instance[1].ring);
1519 break;
1520 case 1:
1521 /* XXX compute */
1522 break;
1523 case 2:
1524 /* XXX compute */
1525 break;
1526 case 3:
1527 /* XXX page queue*/
1528 break;
1529 }
1530 break;
1531 case SOC15_IH_CLIENTID_SDMA2:
1532 switch (entry->ring_id) {
1533 case 0:
1534 amdgpu_fence_process(&adev->sdma.instance[2].ring);
1535 break;
1536 case 1:
1537 /* XXX compute */
1538 break;
1539 case 2:
1540 /* XXX compute */
1541 break;
1542 case 3:
1543 /* XXX page queue*/
1544 break;
1545 }
1546 break;
1547 case SOC15_IH_CLIENTID_SDMA3_Sienna_Cichlid:
1548 switch (entry->ring_id) {
1549 case 0:
1550 amdgpu_fence_process(&adev->sdma.instance[3].ring);
1551 break;
1552 case 1:
1553 /* XXX compute */
1554 break;
1555 case 2:
1556 /* XXX compute */
1557 break;
1558 case 3:
1559 /* XXX page queue*/
1560 break;
1561 }
1562 break;
1563 }
1564 return 0;
1565}
1566
1567static int sdma_v5_2_process_illegal_inst_irq(struct amdgpu_device *adev,
1568 struct amdgpu_irq_src *source,
1569 struct amdgpu_iv_entry *entry)
1570{
1571 return 0;
1572}
1573
1574static void sdma_v5_2_update_medium_grain_clock_gating(struct amdgpu_device *adev,
1575 bool enable)
1576{
1577 uint32_t data, def;
1578 int i;
1579
1580 for (i = 0; i < adev->sdma.num_instances; i++) {
1581
1582 if (adev->sdma.instance[i].fw_version < 70 && adev->ip_versions[SDMA0_HWIP][0] == IP_VERSION(5, 2, 1))
1583 adev->cg_flags &= ~AMD_CG_SUPPORT_SDMA_MGCG;
1584
1585 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG)) {
1586 /* Enable sdma clock gating */
1587 def = data = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL));
1588 data &= ~(SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK |
1589 SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK |
1590 SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK |
1591 SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK |
1592 SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK |
1593 SDMA0_CLK_CTRL__SOFT_OVERRIDER_REG_MASK);
1594 if (def != data)
1595 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL), data);
1596 } else {
1597 /* Disable sdma clock gating */
1598 def = data = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL));
1599 data |= (SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK |
1600 SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK |
1601 SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK |
1602 SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK |
1603 SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK |
1604 SDMA0_CLK_CTRL__SOFT_OVERRIDER_REG_MASK);
1605 if (def != data)
1606 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL), data);
1607 }
1608 }
1609}
1610
1611static void sdma_v5_2_update_medium_grain_light_sleep(struct amdgpu_device *adev,
1612 bool enable)
1613{
1614 uint32_t data, def;
1615 int i;
1616
1617 for (i = 0; i < adev->sdma.num_instances; i++) {
1618
1619 if (adev->sdma.instance[i].fw_version < 70 && adev->ip_versions[SDMA0_HWIP][0] == IP_VERSION(5, 2, 1))
1620 adev->cg_flags &= ~AMD_CG_SUPPORT_SDMA_LS;
1621
1622 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_LS)) {
1623 /* Enable sdma mem light sleep */
1624 def = data = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL));
1625 data |= SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK;
1626 if (def != data)
1627 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL), data);
1628
1629 } else {
1630 /* Disable sdma mem light sleep */
1631 def = data = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL));
1632 data &= ~SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK;
1633 if (def != data)
1634 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL), data);
1635
1636 }
1637 }
1638}
1639
1640static int sdma_v5_2_set_clockgating_state(void *handle,
1641 enum amd_clockgating_state state)
1642{
1643 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1644
1645 if (amdgpu_sriov_vf(adev))
1646 return 0;
1647
1648 switch (adev->ip_versions[SDMA0_HWIP][0]) {
1649 case IP_VERSION(5, 2, 0):
1650 case IP_VERSION(5, 2, 2):
1651 case IP_VERSION(5, 2, 1):
1652 case IP_VERSION(5, 2, 4):
1653 case IP_VERSION(5, 2, 5):
1654 case IP_VERSION(5, 2, 6):
1655 case IP_VERSION(5, 2, 3):
1656 sdma_v5_2_update_medium_grain_clock_gating(adev,
1657 state == AMD_CG_STATE_GATE);
1658 sdma_v5_2_update_medium_grain_light_sleep(adev,
1659 state == AMD_CG_STATE_GATE);
1660 break;
1661 default:
1662 break;
1663 }
1664
1665 return 0;
1666}
1667
1668static int sdma_v5_2_set_powergating_state(void *handle,
1669 enum amd_powergating_state state)
1670{
1671 return 0;
1672}
1673
1674static void sdma_v5_2_get_clockgating_state(void *handle, u64 *flags)
1675{
1676 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1677 int data;
1678
1679 if (amdgpu_sriov_vf(adev))
1680 *flags = 0;
1681
1682 /* AMD_CG_SUPPORT_SDMA_MGCG */
1683 data = RREG32(sdma_v5_2_get_reg_offset(adev, 0, mmSDMA0_CLK_CTRL));
1684 if (!(data & SDMA0_CLK_CTRL__CGCG_EN_OVERRIDE_MASK))
1685 *flags |= AMD_CG_SUPPORT_SDMA_MGCG;
1686
1687 /* AMD_CG_SUPPORT_SDMA_LS */
1688 data = RREG32_KIQ(sdma_v5_2_get_reg_offset(adev, 0, mmSDMA0_POWER_CNTL));
1689 if (data & SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK)
1690 *flags |= AMD_CG_SUPPORT_SDMA_LS;
1691}
1692
1693const struct amd_ip_funcs sdma_v5_2_ip_funcs = {
1694 .name = "sdma_v5_2",
1695 .early_init = sdma_v5_2_early_init,
1696 .late_init = NULL,
1697 .sw_init = sdma_v5_2_sw_init,
1698 .sw_fini = sdma_v5_2_sw_fini,
1699 .hw_init = sdma_v5_2_hw_init,
1700 .hw_fini = sdma_v5_2_hw_fini,
1701 .suspend = sdma_v5_2_suspend,
1702 .resume = sdma_v5_2_resume,
1703 .is_idle = sdma_v5_2_is_idle,
1704 .wait_for_idle = sdma_v5_2_wait_for_idle,
1705 .soft_reset = sdma_v5_2_soft_reset,
1706 .set_clockgating_state = sdma_v5_2_set_clockgating_state,
1707 .set_powergating_state = sdma_v5_2_set_powergating_state,
1708 .get_clockgating_state = sdma_v5_2_get_clockgating_state,
1709};
1710
1711static const struct amdgpu_ring_funcs sdma_v5_2_ring_funcs = {
1712 .type = AMDGPU_RING_TYPE_SDMA,
1713 .align_mask = 0xf,
1714 .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP),
1715 .support_64bit_ptrs = true,
1716 .secure_submission_supported = true,
1717 .vmhub = AMDGPU_GFXHUB_0,
1718 .get_rptr = sdma_v5_2_ring_get_rptr,
1719 .get_wptr = sdma_v5_2_ring_get_wptr,
1720 .set_wptr = sdma_v5_2_ring_set_wptr,
1721 .emit_frame_size =
1722 5 + /* sdma_v5_2_ring_init_cond_exec */
1723 6 + /* sdma_v5_2_ring_emit_hdp_flush */
1724 3 + /* hdp_invalidate */
1725 6 + /* sdma_v5_2_ring_emit_pipeline_sync */
1726 /* sdma_v5_2_ring_emit_vm_flush */
1727 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 +
1728 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6 +
1729 10 + 10 + 10, /* sdma_v5_2_ring_emit_fence x3 for user fence, vm fence */
1730 .emit_ib_size = 7 + 6, /* sdma_v5_2_ring_emit_ib */
1731 .emit_ib = sdma_v5_2_ring_emit_ib,
1732 .emit_mem_sync = sdma_v5_2_ring_emit_mem_sync,
1733 .emit_fence = sdma_v5_2_ring_emit_fence,
1734 .emit_pipeline_sync = sdma_v5_2_ring_emit_pipeline_sync,
1735 .emit_vm_flush = sdma_v5_2_ring_emit_vm_flush,
1736 .emit_hdp_flush = sdma_v5_2_ring_emit_hdp_flush,
1737 .test_ring = sdma_v5_2_ring_test_ring,
1738 .test_ib = sdma_v5_2_ring_test_ib,
1739 .insert_nop = sdma_v5_2_ring_insert_nop,
1740 .pad_ib = sdma_v5_2_ring_pad_ib,
1741 .emit_wreg = sdma_v5_2_ring_emit_wreg,
1742 .emit_reg_wait = sdma_v5_2_ring_emit_reg_wait,
1743 .emit_reg_write_reg_wait = sdma_v5_2_ring_emit_reg_write_reg_wait,
1744 .init_cond_exec = sdma_v5_2_ring_init_cond_exec,
1745 .patch_cond_exec = sdma_v5_2_ring_patch_cond_exec,
1746 .preempt_ib = sdma_v5_2_ring_preempt_ib,
1747};
1748
1749static void sdma_v5_2_set_ring_funcs(struct amdgpu_device *adev)
1750{
1751 int i;
1752
1753 for (i = 0; i < adev->sdma.num_instances; i++) {
1754 adev->sdma.instance[i].ring.funcs = &sdma_v5_2_ring_funcs;
1755 adev->sdma.instance[i].ring.me = i;
1756 }
1757}
1758
1759static const struct amdgpu_irq_src_funcs sdma_v5_2_trap_irq_funcs = {
1760 .set = sdma_v5_2_set_trap_irq_state,
1761 .process = sdma_v5_2_process_trap_irq,
1762};
1763
1764static const struct amdgpu_irq_src_funcs sdma_v5_2_illegal_inst_irq_funcs = {
1765 .process = sdma_v5_2_process_illegal_inst_irq,
1766};
1767
1768static void sdma_v5_2_set_irq_funcs(struct amdgpu_device *adev)
1769{
1770 adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_INSTANCE0 +
1771 adev->sdma.num_instances;
1772 adev->sdma.trap_irq.funcs = &sdma_v5_2_trap_irq_funcs;
1773 adev->sdma.illegal_inst_irq.funcs = &sdma_v5_2_illegal_inst_irq_funcs;
1774}
1775
1776/**
1777 * sdma_v5_2_emit_copy_buffer - copy buffer using the sDMA engine
1778 *
1779 * @ib: indirect buffer to copy to
1780 * @src_offset: src GPU address
1781 * @dst_offset: dst GPU address
1782 * @byte_count: number of bytes to xfer
1783 * @tmz: if a secure copy should be used
1784 *
1785 * Copy GPU buffers using the DMA engine.
1786 * Used by the amdgpu ttm implementation to move pages if
1787 * registered as the asic copy callback.
1788 */
1789static void sdma_v5_2_emit_copy_buffer(struct amdgpu_ib *ib,
1790 uint64_t src_offset,
1791 uint64_t dst_offset,
1792 uint32_t byte_count,
1793 bool tmz)
1794{
1795 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
1796 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR) |
1797 SDMA_PKT_COPY_LINEAR_HEADER_TMZ(tmz ? 1 : 0);
1798 ib->ptr[ib->length_dw++] = byte_count - 1;
1799 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
1800 ib->ptr[ib->length_dw++] = lower_32_bits(src_offset);
1801 ib->ptr[ib->length_dw++] = upper_32_bits(src_offset);
1802 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1803 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
1804}
1805
1806/**
1807 * sdma_v5_2_emit_fill_buffer - fill buffer using the sDMA engine
1808 *
1809 * @ib: indirect buffer to fill
1810 * @src_data: value to write to buffer
1811 * @dst_offset: dst GPU address
1812 * @byte_count: number of bytes to xfer
1813 *
1814 * Fill GPU buffers using the DMA engine.
1815 */
1816static void sdma_v5_2_emit_fill_buffer(struct amdgpu_ib *ib,
1817 uint32_t src_data,
1818 uint64_t dst_offset,
1819 uint32_t byte_count)
1820{
1821 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_CONST_FILL);
1822 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1823 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
1824 ib->ptr[ib->length_dw++] = src_data;
1825 ib->ptr[ib->length_dw++] = byte_count - 1;
1826}
1827
1828static const struct amdgpu_buffer_funcs sdma_v5_2_buffer_funcs = {
1829 .copy_max_bytes = 0x400000,
1830 .copy_num_dw = 7,
1831 .emit_copy_buffer = sdma_v5_2_emit_copy_buffer,
1832
1833 .fill_max_bytes = 0x400000,
1834 .fill_num_dw = 5,
1835 .emit_fill_buffer = sdma_v5_2_emit_fill_buffer,
1836};
1837
1838static void sdma_v5_2_set_buffer_funcs(struct amdgpu_device *adev)
1839{
1840 if (adev->mman.buffer_funcs == NULL) {
1841 adev->mman.buffer_funcs = &sdma_v5_2_buffer_funcs;
1842 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring;
1843 }
1844}
1845
1846static const struct amdgpu_vm_pte_funcs sdma_v5_2_vm_pte_funcs = {
1847 .copy_pte_num_dw = 7,
1848 .copy_pte = sdma_v5_2_vm_copy_pte,
1849 .write_pte = sdma_v5_2_vm_write_pte,
1850 .set_pte_pde = sdma_v5_2_vm_set_pte_pde,
1851};
1852
1853static void sdma_v5_2_set_vm_pte_funcs(struct amdgpu_device *adev)
1854{
1855 unsigned i;
1856
1857 if (adev->vm_manager.vm_pte_funcs == NULL) {
1858 adev->vm_manager.vm_pte_funcs = &sdma_v5_2_vm_pte_funcs;
1859 for (i = 0; i < adev->sdma.num_instances; i++) {
1860 adev->vm_manager.vm_pte_scheds[i] =
1861 &adev->sdma.instance[i].ring.sched;
1862 }
1863 adev->vm_manager.vm_pte_num_scheds = adev->sdma.num_instances;
1864 }
1865}
1866
1867const struct amdgpu_ip_block_version sdma_v5_2_ip_block = {
1868 .type = AMD_IP_BLOCK_TYPE_SDMA,
1869 .major = 5,
1870 .minor = 2,
1871 .rev = 0,
1872 .funcs = &sdma_v5_2_ip_funcs,
1873};