1/*
   2 * Copyright 2019 Advanced Micro Devices, Inc.
   3 *
   4 * Permission is hereby granted, free of charge, to any person obtaining a
   5 * copy of this software and associated documentation files (the "Software"),
   6 * to deal in the Software without restriction, including without limitation
   7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8 * and/or sell copies of the Software, and to permit persons to whom the
   9 * Software is furnished to do so, subject to the following conditions:
  10 *
  11 * The above copyright notice and this permission notice shall be included in
  12 * all copies or substantial portions of the Software.
  13 *
  14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20 * OTHER DEALINGS IN THE SOFTWARE.
  21 *
  22 */
  23
  24#include <linux/delay.h>
  25#include <linux/firmware.h>
  26#include <linux/module.h>
  27#include <linux/pci.h>
  28
  29#include "amdgpu.h"
  30#include "amdgpu_ucode.h"
  31#include "amdgpu_trace.h"
  32
  33#include "gc/gc_10_3_0_offset.h"
  34#include "gc/gc_10_3_0_sh_mask.h"
  35#include "ivsrcid/sdma0/irqsrcs_sdma0_5_0.h"
  36#include "ivsrcid/sdma1/irqsrcs_sdma1_5_0.h"
  37#include "ivsrcid/sdma2/irqsrcs_sdma2_5_0.h"
  38#include "ivsrcid/sdma3/irqsrcs_sdma3_5_0.h"
  39
  40#include "soc15_common.h"
  41#include "soc15.h"
  42#include "navi10_sdma_pkt_open.h"
  43#include "nbio_v2_3.h"
  44#include "sdma_common.h"
  45#include "sdma_v5_2.h"
  46
  47MODULE_FIRMWARE("amdgpu/sienna_cichlid_sdma.bin");
  48MODULE_FIRMWARE("amdgpu/navy_flounder_sdma.bin");
 
 
 
 
 
 
 
  49
  50#define SDMA1_REG_OFFSET 0x600
  51#define SDMA3_REG_OFFSET 0x400
  52#define SDMA0_HYP_DEC_REG_START 0x5880
  53#define SDMA0_HYP_DEC_REG_END 0x5893
  54#define SDMA1_HYP_DEC_REG_OFFSET 0x20
  55
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
  56static void sdma_v5_2_set_ring_funcs(struct amdgpu_device *adev);
  57static void sdma_v5_2_set_buffer_funcs(struct amdgpu_device *adev);
  58static void sdma_v5_2_set_vm_pte_funcs(struct amdgpu_device *adev);
  59static void sdma_v5_2_set_irq_funcs(struct amdgpu_device *adev);
  60
  61static u32 sdma_v5_2_get_reg_offset(struct amdgpu_device *adev, u32 instance, u32 internal_offset)
  62{
  63	u32 base;
  64
  65	if (internal_offset >= SDMA0_HYP_DEC_REG_START &&
  66	    internal_offset <= SDMA0_HYP_DEC_REG_END) {
  67		base = adev->reg_offset[GC_HWIP][0][1];
  68		if (instance != 0)
  69			internal_offset += SDMA1_HYP_DEC_REG_OFFSET * instance;
  70	} else {
  71		if (instance < 2) {
  72			base = adev->reg_offset[GC_HWIP][0][0];
  73			if (instance == 1)
  74				internal_offset += SDMA1_REG_OFFSET;
  75		} else {
  76			base = adev->reg_offset[GC_HWIP][0][2];
  77			if (instance == 3)
  78				internal_offset += SDMA3_REG_OFFSET;
  79		}
  80	}
  81
  82	return base + internal_offset;
  83}
  84
  85static void sdma_v5_2_init_golden_registers(struct amdgpu_device *adev)
  86{
  87	switch (adev->asic_type) {
  88	case CHIP_SIENNA_CICHLID:
  89	case CHIP_NAVY_FLOUNDER:
  90		break;
  91	default:
  92		break;
  93	}
  94}
  95
  96static int sdma_v5_2_init_inst_ctx(struct amdgpu_sdma_instance *sdma_inst)
  97{
  98	int err = 0;
  99	const struct sdma_firmware_header_v1_0 *hdr;
 100
 101	err = amdgpu_ucode_validate(sdma_inst->fw);
 102	if (err)
 103		return err;
 104
 105	hdr = (const struct sdma_firmware_header_v1_0 *)sdma_inst->fw->data;
 106	sdma_inst->fw_version = le32_to_cpu(hdr->header.ucode_version);
 107	sdma_inst->feature_version = le32_to_cpu(hdr->ucode_feature_version);
 108
 109	if (sdma_inst->feature_version >= 20)
 110		sdma_inst->burst_nop = true;
 111
 112	return 0;
 113}
 114
 115static void sdma_v5_2_destroy_inst_ctx(struct amdgpu_device *adev)
 116{
 117	int i;
 118
 119	for (i = 0; i < adev->sdma.num_instances; i++) {
 120		release_firmware(adev->sdma.instance[i].fw);
 121		adev->sdma.instance[i].fw = NULL;
 122
 123		if (adev->asic_type == CHIP_SIENNA_CICHLID)
 124			break;
 125	}
 126
 127	memset((void*)adev->sdma.instance, 0,
 128	       sizeof(struct amdgpu_sdma_instance) * AMDGPU_MAX_SDMA_INSTANCES);
 129}
 130
 131/**
 132 * sdma_v5_2_init_microcode - load ucode images from disk
 133 *
 134 * @adev: amdgpu_device pointer
 135 *
 136 * Use the firmware interface to load the ucode images into
 137 * the driver (not loaded into hw).
 138 * Returns 0 on success, error on failure.
 139 */
 140
 141// emulation only, won't work on real chip
 142// navi10 real chip need to use PSP to load firmware
 143static int sdma_v5_2_init_microcode(struct amdgpu_device *adev)
 144{
 145	const char *chip_name;
 146	char fw_name[40];
 147	int err = 0, i;
 148	struct amdgpu_firmware_info *info = NULL;
 149	const struct common_firmware_header *header = NULL;
 150
 151	DRM_DEBUG("\n");
 152
 153	switch (adev->asic_type) {
 154	case CHIP_SIENNA_CICHLID:
 155		chip_name = "sienna_cichlid";
 156		break;
 157	case CHIP_NAVY_FLOUNDER:
 158		chip_name = "navy_flounder";
 159		break;
 160	default:
 161		BUG();
 162	}
 163
 164	snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma.bin", chip_name);
 165
 166	err = request_firmware(&adev->sdma.instance[0].fw, fw_name, adev->dev);
 167	if (err)
 168		goto out;
 169
 170	err = sdma_v5_2_init_inst_ctx(&adev->sdma.instance[0]);
 171	if (err)
 172		goto out;
 173
 174	for (i = 1; i < adev->sdma.num_instances; i++) {
 175		if (adev->asic_type == CHIP_SIENNA_CICHLID ||
 176		    adev->asic_type == CHIP_NAVY_FLOUNDER) {
 177			memcpy((void*)&adev->sdma.instance[i],
 178			       (void*)&adev->sdma.instance[0],
 179			       sizeof(struct amdgpu_sdma_instance));
 180		} else {
 181			snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma%d.bin", chip_name, i);
 182			err = request_firmware(&adev->sdma.instance[i].fw, fw_name, adev->dev);
 183			if (err)
 184				goto out;
 185
 186			err = sdma_v5_2_init_inst_ctx(&adev->sdma.instance[0]);
 187			if (err)
 188				goto out;
 189		}
 190	}
 191
 192	DRM_DEBUG("psp_load == '%s'\n",
 193		  adev->firmware.load_type == AMDGPU_FW_LOAD_PSP ? "true" : "false");
 194
 195	if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
 196		for (i = 0; i < adev->sdma.num_instances; i++) {
 197			info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SDMA0 + i];
 198			info->ucode_id = AMDGPU_UCODE_ID_SDMA0 + i;
 199			info->fw = adev->sdma.instance[i].fw;
 200			header = (const struct common_firmware_header *)info->fw->data;
 201			adev->firmware.fw_size +=
 202				ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
 203		}
 204	}
 205
 206out:
 207	if (err) {
 208		DRM_ERROR("sdma_v5_2: Failed to load firmware \"%s\"\n", fw_name);
 209		sdma_v5_2_destroy_inst_ctx(adev);
 210	}
 211	return err;
 212}
 213
 214static unsigned sdma_v5_2_ring_init_cond_exec(struct amdgpu_ring *ring)
 215{
 216	unsigned ret;
 217
 218	amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_COND_EXE));
 219	amdgpu_ring_write(ring, lower_32_bits(ring->cond_exe_gpu_addr));
 220	amdgpu_ring_write(ring, upper_32_bits(ring->cond_exe_gpu_addr));
 221	amdgpu_ring_write(ring, 1);
 222	ret = ring->wptr & ring->buf_mask;/* this is the offset we need patch later */
 223	amdgpu_ring_write(ring, 0x55aa55aa);/* insert dummy here and patch it later */
 
 
 224
 225	return ret;
 226}
 227
 228static void sdma_v5_2_ring_patch_cond_exec(struct amdgpu_ring *ring,
 229					   unsigned offset)
 230{
 231	unsigned cur;
 232
 233	BUG_ON(offset > ring->buf_mask);
 234	BUG_ON(ring->ring[offset] != 0x55aa55aa);
 235
 236	cur = (ring->wptr - 1) & ring->buf_mask;
 237	if (cur > offset)
 238		ring->ring[offset] = cur - offset;
 239	else
 240		ring->ring[offset] = (ring->buf_mask + 1) - offset + cur;
 241}
 242
 243/**
 244 * sdma_v5_2_ring_get_rptr - get the current read pointer
 245 *
 246 * @ring: amdgpu ring pointer
 247 *
 248 * Get the current rptr from the hardware (NAVI10+).
 249 */
 250static uint64_t sdma_v5_2_ring_get_rptr(struct amdgpu_ring *ring)
 251{
 252	u64 *rptr;
 253
 254	/* XXX check if swapping is necessary on BE */
 255	rptr = ((u64 *)&ring->adev->wb.wb[ring->rptr_offs]);
 256
 257	DRM_DEBUG("rptr before shift == 0x%016llx\n", *rptr);
 258	return ((*rptr) >> 2);
 259}
 260
 261/**
 262 * sdma_v5_2_ring_get_wptr - get the current write pointer
 263 *
 264 * @ring: amdgpu ring pointer
 265 *
 266 * Get the current wptr from the hardware (NAVI10+).
 267 */
 268static uint64_t sdma_v5_2_ring_get_wptr(struct amdgpu_ring *ring)
 269{
 270	struct amdgpu_device *adev = ring->adev;
 271	u64 wptr;
 272
 273	if (ring->use_doorbell) {
 274		/* XXX check if swapping is necessary on BE */
 275		wptr = READ_ONCE(*((u64 *)&adev->wb.wb[ring->wptr_offs]));
 276		DRM_DEBUG("wptr/doorbell before shift == 0x%016llx\n", wptr);
 277	} else {
 278		wptr = RREG32(sdma_v5_2_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR_HI));
 279		wptr = wptr << 32;
 280		wptr |= RREG32(sdma_v5_2_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR));
 281		DRM_DEBUG("wptr before shift [%i] wptr == 0x%016llx\n", ring->me, wptr);
 282	}
 283
 284	return wptr >> 2;
 285}
 286
 287/**
 288 * sdma_v5_2_ring_set_wptr - commit the write pointer
 289 *
 290 * @ring: amdgpu ring pointer
 291 *
 292 * Write the wptr back to the hardware (NAVI10+).
 293 */
 294static void sdma_v5_2_ring_set_wptr(struct amdgpu_ring *ring)
 295{
 296	struct amdgpu_device *adev = ring->adev;
 297
 298	DRM_DEBUG("Setting write pointer\n");
 299	if (ring->use_doorbell) {
 300		DRM_DEBUG("Using doorbell -- "
 301				"wptr_offs == 0x%08x "
 302				"lower_32_bits(ring->wptr) << 2 == 0x%08x "
 303				"upper_32_bits(ring->wptr) << 2 == 0x%08x\n",
 304				ring->wptr_offs,
 305				lower_32_bits(ring->wptr << 2),
 306				upper_32_bits(ring->wptr << 2));
 307		/* XXX check if swapping is necessary on BE */
 308		adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr << 2);
 309		adev->wb.wb[ring->wptr_offs + 1] = upper_32_bits(ring->wptr << 2);
 310		DRM_DEBUG("calling WDOORBELL64(0x%08x, 0x%016llx)\n",
 311				ring->doorbell_index, ring->wptr << 2);
 312		WDOORBELL64(ring->doorbell_index, ring->wptr << 2);
 
 
 
 
 
 
 
 
 
 
 313	} else {
 314		DRM_DEBUG("Not using doorbell -- "
 315				"mmSDMA%i_GFX_RB_WPTR == 0x%08x "
 316				"mmSDMA%i_GFX_RB_WPTR_HI == 0x%08x\n",
 317				ring->me,
 318				lower_32_bits(ring->wptr << 2),
 319				ring->me,
 320				upper_32_bits(ring->wptr << 2));
 321		WREG32(sdma_v5_2_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR),
 322			lower_32_bits(ring->wptr << 2));
 323		WREG32(sdma_v5_2_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR_HI),
 324			upper_32_bits(ring->wptr << 2));
 325	}
 326}
 327
 328static void sdma_v5_2_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
 329{
 330	struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring);
 331	int i;
 332
 333	for (i = 0; i < count; i++)
 334		if (sdma && sdma->burst_nop && (i == 0))
 335			amdgpu_ring_write(ring, ring->funcs->nop |
 336				SDMA_PKT_NOP_HEADER_COUNT(count - 1));
 337		else
 338			amdgpu_ring_write(ring, ring->funcs->nop);
 339}
 340
 341/**
 342 * sdma_v5_2_ring_emit_ib - Schedule an IB on the DMA engine
 343 *
 344 * @ring: amdgpu ring pointer
 
 345 * @ib: IB object to schedule
 
 346 *
 347 * Schedule an IB in the DMA ring.
 348 */
 349static void sdma_v5_2_ring_emit_ib(struct amdgpu_ring *ring,
 350				   struct amdgpu_job *job,
 351				   struct amdgpu_ib *ib,
 352				   uint32_t flags)
 353{
 354	unsigned vmid = AMDGPU_JOB_GET_VMID(job);
 355	uint64_t csa_mc_addr = amdgpu_sdma_get_csa_mc_addr(ring, vmid);
 356
 357	/* An IB packet must end on a 8 DW boundary--the next dword
 358	 * must be on a 8-dword boundary. Our IB packet below is 6
 359	 * dwords long, thus add x number of NOPs, such that, in
 360	 * modular arithmetic,
 361	 * wptr + 6 + x = 8k, k >= 0, which in C is,
 362	 * (wptr + 6 + x) % 8 = 0.
 363	 * The expression below, is a solution of x.
 364	 */
 365	sdma_v5_2_ring_insert_nop(ring, (2 - lower_32_bits(ring->wptr)) & 7);
 366
 367	amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) |
 368			  SDMA_PKT_INDIRECT_HEADER_VMID(vmid & 0xf));
 369	/* base must be 32 byte aligned */
 370	amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0);
 371	amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
 372	amdgpu_ring_write(ring, ib->length_dw);
 373	amdgpu_ring_write(ring, lower_32_bits(csa_mc_addr));
 374	amdgpu_ring_write(ring, upper_32_bits(csa_mc_addr));
 375}
 376
 377/**
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 378 * sdma_v5_2_ring_emit_hdp_flush - emit an hdp flush on the DMA ring
 379 *
 380 * @ring: amdgpu ring pointer
 381 *
 382 * Emit an hdp flush packet on the requested DMA ring.
 383 */
 384static void sdma_v5_2_ring_emit_hdp_flush(struct amdgpu_ring *ring)
 385{
 386	struct amdgpu_device *adev = ring->adev;
 387	u32 ref_and_mask = 0;
 388	const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg;
 389
 390	ref_and_mask = nbio_hf_reg->ref_and_mask_sdma0 << ring->me;
 
 
 
 391
 392	amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
 393			  SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(1) |
 394			  SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* == */
 395	amdgpu_ring_write(ring, (adev->nbio.funcs->get_hdp_flush_done_offset(adev)) << 2);
 396	amdgpu_ring_write(ring, (adev->nbio.funcs->get_hdp_flush_req_offset(adev)) << 2);
 397	amdgpu_ring_write(ring, ref_and_mask); /* reference */
 398	amdgpu_ring_write(ring, ref_and_mask); /* mask */
 399	amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
 400			  SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */
 
 401}
 402
 403/**
 404 * sdma_v5_2_ring_emit_fence - emit a fence on the DMA ring
 405 *
 406 * @ring: amdgpu ring pointer
 407 * @fence: amdgpu fence object
 
 
 408 *
 409 * Add a DMA fence packet to the ring to write
 410 * the fence seq number and DMA trap packet to generate
 411 * an interrupt if needed.
 412 */
 413static void sdma_v5_2_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
 414				      unsigned flags)
 415{
 416	bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
 417	/* write the fence */
 418	amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE) |
 419			  SDMA_PKT_FENCE_HEADER_MTYPE(0x3)); /* Ucached(UC) */
 420	/* zero in first two bits */
 421	BUG_ON(addr & 0x3);
 422	amdgpu_ring_write(ring, lower_32_bits(addr));
 423	amdgpu_ring_write(ring, upper_32_bits(addr));
 424	amdgpu_ring_write(ring, lower_32_bits(seq));
 425
 426	/* optionally write high bits as well */
 427	if (write64bit) {
 428		addr += 4;
 429		amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE) |
 430				  SDMA_PKT_FENCE_HEADER_MTYPE(0x3));
 431		/* zero in first two bits */
 432		BUG_ON(addr & 0x3);
 433		amdgpu_ring_write(ring, lower_32_bits(addr));
 434		amdgpu_ring_write(ring, upper_32_bits(addr));
 435		amdgpu_ring_write(ring, upper_32_bits(seq));
 436	}
 437
 438	if (flags & AMDGPU_FENCE_FLAG_INT) {
 
 
 439		/* generate an interrupt */
 440		amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_TRAP));
 441		amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(0));
 442	}
 443}
 444
 445
 446/**
 447 * sdma_v5_2_gfx_stop - stop the gfx async dma engines
 448 *
 449 * @adev: amdgpu_device pointer
 450 *
 451 * Stop the gfx async dma ring buffers.
 452 */
 453static void sdma_v5_2_gfx_stop(struct amdgpu_device *adev)
 454{
 455	struct amdgpu_ring *sdma0 = &adev->sdma.instance[0].ring;
 456	struct amdgpu_ring *sdma1 = &adev->sdma.instance[1].ring;
 457	struct amdgpu_ring *sdma2 = &adev->sdma.instance[2].ring;
 458	struct amdgpu_ring *sdma3 = &adev->sdma.instance[3].ring;
 459	u32 rb_cntl, ib_cntl;
 460	int i;
 461
 462	if ((adev->mman.buffer_funcs_ring == sdma0) ||
 463	    (adev->mman.buffer_funcs_ring == sdma1) ||
 464	    (adev->mman.buffer_funcs_ring == sdma2) ||
 465	    (adev->mman.buffer_funcs_ring == sdma3))
 466		amdgpu_ttm_set_buffer_funcs_status(adev, false);
 467
 468	for (i = 0; i < adev->sdma.num_instances; i++) {
 469		rb_cntl = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL));
 470		rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0);
 471		WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl);
 472		ib_cntl = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL));
 473		ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 0);
 474		WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL), ib_cntl);
 475	}
 476
 477	sdma0->sched.ready = false;
 478	sdma1->sched.ready = false;
 479	sdma2->sched.ready = false;
 480	sdma3->sched.ready = false;
 481}
 482
 483/**
 484 * sdma_v5_2_rlc_stop - stop the compute async dma engines
 485 *
 486 * @adev: amdgpu_device pointer
 487 *
 488 * Stop the compute async dma queues.
 489 */
 490static void sdma_v5_2_rlc_stop(struct amdgpu_device *adev)
 491{
 492	/* XXX todo */
 493}
 494
 495/**
 496 * sdma_v_0_ctx_switch_enable - stop the async dma engines context switch
 497 *
 498 * @adev: amdgpu_device pointer
 499 * @enable: enable/disable the DMA MEs context switch.
 500 *
 501 * Halt or unhalt the async dma engines context switch.
 502 */
 503static void sdma_v5_2_ctx_switch_enable(struct amdgpu_device *adev, bool enable)
 504{
 505	u32 f32_cntl, phase_quantum = 0;
 506	int i;
 507
 508	if (amdgpu_sdma_phase_quantum) {
 509		unsigned value = amdgpu_sdma_phase_quantum;
 510		unsigned unit = 0;
 511
 512		while (value > (SDMA0_PHASE0_QUANTUM__VALUE_MASK >>
 513				SDMA0_PHASE0_QUANTUM__VALUE__SHIFT)) {
 514			value = (value + 1) >> 1;
 515			unit++;
 516		}
 517		if (unit > (SDMA0_PHASE0_QUANTUM__UNIT_MASK >>
 518			    SDMA0_PHASE0_QUANTUM__UNIT__SHIFT)) {
 519			value = (SDMA0_PHASE0_QUANTUM__VALUE_MASK >>
 520				 SDMA0_PHASE0_QUANTUM__VALUE__SHIFT);
 521			unit = (SDMA0_PHASE0_QUANTUM__UNIT_MASK >>
 522				SDMA0_PHASE0_QUANTUM__UNIT__SHIFT);
 523			WARN_ONCE(1,
 524			"clamping sdma_phase_quantum to %uK clock cycles\n",
 525				  value << unit);
 526		}
 527		phase_quantum =
 528			value << SDMA0_PHASE0_QUANTUM__VALUE__SHIFT |
 529			unit  << SDMA0_PHASE0_QUANTUM__UNIT__SHIFT;
 530	}
 531
 532	for (i = 0; i < adev->sdma.num_instances; i++) {
 533		f32_cntl = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CNTL));
 534		f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,
 535				AUTO_CTXSW_ENABLE, enable ? 1 : 0);
 536		if (enable && amdgpu_sdma_phase_quantum) {
 537			WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_PHASE0_QUANTUM),
 538			       phase_quantum);
 539			WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_PHASE1_QUANTUM),
 540			       phase_quantum);
 541			WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_PHASE2_QUANTUM),
 542			       phase_quantum);
 543		}
 544		WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CNTL), f32_cntl);
 
 
 
 
 
 
 545	}
 546
 547}
 548
 549/**
 550 * sdma_v5_2_enable - stop the async dma engines
 551 *
 552 * @adev: amdgpu_device pointer
 553 * @enable: enable/disable the DMA MEs.
 554 *
 555 * Halt or unhalt the async dma engines.
 556 */
 557static void sdma_v5_2_enable(struct amdgpu_device *adev, bool enable)
 558{
 559	u32 f32_cntl;
 560	int i;
 561
 562	if (enable == false) {
 563		sdma_v5_2_gfx_stop(adev);
 564		sdma_v5_2_rlc_stop(adev);
 565	}
 566
 567	for (i = 0; i < adev->sdma.num_instances; i++) {
 568		f32_cntl = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_F32_CNTL));
 569		f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, enable ? 0 : 1);
 570		WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_F32_CNTL), f32_cntl);
 
 
 571	}
 572}
 573
 574/**
 575 * sdma_v5_2_gfx_resume - setup and start the async dma engines
 576 *
 577 * @adev: amdgpu_device pointer
 
 
 578 *
 579 * Set up the gfx DMA ring buffers and enable them.
 580 * Returns 0 for success, error for failure.
 581 */
 582static int sdma_v5_2_gfx_resume(struct amdgpu_device *adev)
 
 583{
 584	struct amdgpu_ring *ring;
 585	u32 rb_cntl, ib_cntl;
 586	u32 rb_bufsz;
 587	u32 wb_offset;
 588	u32 doorbell;
 589	u32 doorbell_offset;
 590	u32 temp;
 591	u32 wptr_poll_cntl;
 592	u64 wptr_gpu_addr;
 593	int i, r;
 594
 595	for (i = 0; i < adev->sdma.num_instances; i++) {
 596		ring = &adev->sdma.instance[i].ring;
 597		wb_offset = (ring->rptr_offs * 4);
 598
 599		WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL), 0);
 
 600
 601		/* Set ring buffer size in dwords */
 602		rb_bufsz = order_base_2(ring->ring_size / 4);
 603		rb_cntl = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL));
 604		rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz);
 605#ifdef __BIG_ENDIAN
 606		rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1);
 607		rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL,
 608					RPTR_WRITEBACK_SWAP_ENABLE, 1);
 609#endif
 610		WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl);
 611
 612		/* Initialize the ring buffer's read and write pointers */
 613		WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR), 0);
 614		WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_HI), 0);
 615		WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), 0);
 616		WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI), 0);
 617
 618		/* setup the wptr shadow polling */
 619		wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
 620		WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO),
 621		       lower_32_bits(wptr_gpu_addr));
 622		WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI),
 623		       upper_32_bits(wptr_gpu_addr));
 624		wptr_poll_cntl = RREG32(sdma_v5_2_get_reg_offset(adev, i,
 625							 mmSDMA0_GFX_RB_WPTR_POLL_CNTL));
 626		wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl,
 627					       SDMA0_GFX_RB_WPTR_POLL_CNTL,
 628					       F32_POLL_ENABLE, 1);
 629		WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_CNTL),
 630		       wptr_poll_cntl);
 631
 632		/* set the wb address whether it's enabled or not */
 633		WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_ADDR_HI),
 634		       upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF);
 635		WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_ADDR_LO),
 636		       lower_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC);
 
 
 
 
 
 
 
 637
 638		rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1);
 639
 640		WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_BASE), ring->gpu_addr >> 8);
 641		WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_BASE_HI), ring->gpu_addr >> 40);
 642
 
 643		ring->wptr = 0;
 644
 645		/* before programing wptr to a less value, need set minor_ptr_update first */
 646		WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_MINOR_PTR_UPDATE), 1);
 647
 648		if (!amdgpu_sriov_vf(adev)) { /* only bare-metal use register write for wptr */
 649			WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), lower_32_bits(ring->wptr) << 2);
 650			WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI), upper_32_bits(ring->wptr) << 2);
 651		}
 652
 653		doorbell = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL));
 654		doorbell_offset = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL_OFFSET));
 655
 656		if (ring->use_doorbell) {
 657			doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 1);
 658			doorbell_offset = REG_SET_FIELD(doorbell_offset, SDMA0_GFX_DOORBELL_OFFSET,
 659					OFFSET, ring->doorbell_index);
 660		} else {
 661			doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 0);
 662		}
 663		WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL), doorbell);
 664		WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL_OFFSET), doorbell_offset);
 665
 666		adev->nbio.funcs->sdma_doorbell_range(adev, i, ring->use_doorbell,
 667						      ring->doorbell_index,
 668						      adev->doorbell_index.sdma_doorbell_range);
 
 
 
 669
 670		if (amdgpu_sriov_vf(adev))
 671			sdma_v5_2_ring_set_wptr(ring);
 672
 673		/* set minor_ptr_update to 0 after wptr programed */
 674		WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_MINOR_PTR_UPDATE), 0);
 675
 
 
 676		/* set utc l1 enable flag always to 1 */
 677		temp = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CNTL));
 678		temp = REG_SET_FIELD(temp, SDMA0_CNTL, UTC_L1_ENABLE, 1);
 679
 680		/* enable MCBP */
 681		temp = REG_SET_FIELD(temp, SDMA0_CNTL, MIDCMD_PREEMPT_ENABLE, 1);
 682		WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CNTL), temp);
 683
 684		/* Set up RESP_MODE to non-copy addresses */
 685		temp = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UTCL1_CNTL));
 686		temp = REG_SET_FIELD(temp, SDMA0_UTCL1_CNTL, RESP_MODE, 3);
 687		temp = REG_SET_FIELD(temp, SDMA0_UTCL1_CNTL, REDO_DELAY, 9);
 688		WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UTCL1_CNTL), temp);
 689
 690		/* program default cache read and write policy */
 691		temp = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UTCL1_PAGE));
 692		/* clean read policy and write policy bits */
 693		temp &= 0xFF0FFF;
 694		temp |= ((CACHE_READ_POLICY_L2__DEFAULT << 12) |
 695			 (CACHE_WRITE_POLICY_L2__DEFAULT << 14) |
 696			 0x01000000);
 697		WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UTCL1_PAGE), temp);
 698
 699		if (!amdgpu_sriov_vf(adev)) {
 700			/* unhalt engine */
 701			temp = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_F32_CNTL));
 702			temp = REG_SET_FIELD(temp, SDMA0_F32_CNTL, HALT, 0);
 703			WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_F32_CNTL), temp);
 704		}
 705
 706		/* enable DMA RB */
 707		rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1);
 708		WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl);
 709
 710		ib_cntl = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL));
 711		ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 1);
 712#ifdef __BIG_ENDIAN
 713		ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_SWAP_ENABLE, 1);
 714#endif
 715		/* enable DMA IBs */
 716		WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL), ib_cntl);
 717
 718		ring->sched.ready = true;
 
 
 
 719
 720		if (amdgpu_sriov_vf(adev)) { /* bare-metal sequence doesn't need below to lines */
 721			sdma_v5_2_ctx_switch_enable(adev, true);
 722			sdma_v5_2_enable(adev, true);
 723		}
 724
 725		r = amdgpu_ring_test_ring(ring);
 726		if (r) {
 727			ring->sched.ready = false;
 728			return r;
 729		}
 
 
 
 
 
 
 730
 731		if (adev->mman.buffer_funcs_ring == ring)
 732			amdgpu_ttm_set_buffer_funcs_status(adev, true);
 
 
 733	}
 734
 735	return 0;
 736}
 737
 738/**
 739 * sdma_v5_2_rlc_resume - setup and start the async dma engines
 740 *
 741 * @adev: amdgpu_device pointer
 742 *
 743 * Set up the compute DMA queues and enable them.
 744 * Returns 0 for success, error for failure.
 745 */
 746static int sdma_v5_2_rlc_resume(struct amdgpu_device *adev)
 747{
 748	return 0;
 749}
 750
 751/**
 752 * sdma_v5_2_load_microcode - load the sDMA ME ucode
 753 *
 754 * @adev: amdgpu_device pointer
 755 *
 756 * Loads the sDMA0/1/2/3 ucode.
 757 * Returns 0 for success, -EINVAL if the ucode is not available.
 758 */
 759static int sdma_v5_2_load_microcode(struct amdgpu_device *adev)
 760{
 761	const struct sdma_firmware_header_v1_0 *hdr;
 762	const __le32 *fw_data;
 763	u32 fw_size;
 764	int i, j;
 765
 766	/* halt the MEs */
 767	sdma_v5_2_enable(adev, false);
 768
 769	for (i = 0; i < adev->sdma.num_instances; i++) {
 770		if (!adev->sdma.instance[i].fw)
 771			return -EINVAL;
 772
 773		hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data;
 774		amdgpu_ucode_print_sdma_hdr(&hdr->header);
 775		fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
 776
 777		fw_data = (const __le32 *)
 778			(adev->sdma.instance[i].fw->data +
 779				le32_to_cpu(hdr->header.ucode_array_offset_bytes));
 780
 781		WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UCODE_ADDR), 0);
 782
 783		for (j = 0; j < fw_size; j++) {
 784			if (amdgpu_emu_mode == 1 && j % 500 == 0)
 785				msleep(1);
 786			WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UCODE_DATA), le32_to_cpup(fw_data++));
 787		}
 788
 789		WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UCODE_ADDR), adev->sdma.instance[i].fw_version);
 790	}
 791
 792	return 0;
 793}
 794
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 795/**
 796 * sdma_v5_2_start - setup and start the async dma engines
 797 *
 798 * @adev: amdgpu_device pointer
 799 *
 800 * Set up the DMA engines and enable them.
 801 * Returns 0 for success, error for failure.
 802 */
 803static int sdma_v5_2_start(struct amdgpu_device *adev)
 804{
 805	int r = 0;
 
 806
 807	if (amdgpu_sriov_vf(adev)) {
 808		sdma_v5_2_ctx_switch_enable(adev, false);
 809		sdma_v5_2_enable(adev, false);
 810
 811		/* set RB registers */
 812		r = sdma_v5_2_gfx_resume(adev);
 813		return r;
 814	}
 815
 816	if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
 817		r = sdma_v5_2_load_microcode(adev);
 818		if (r)
 819			return r;
 820
 821		/* The value of mmSDMA_F32_CNTL is invalid the moment after loading fw */
 822		if (amdgpu_emu_mode == 1)
 823			msleep(1000);
 824	}
 825
 
 
 
 
 
 826	/* unhalt the MEs */
 827	sdma_v5_2_enable(adev, true);
 828	/* enable sdma ring preemption */
 829	sdma_v5_2_ctx_switch_enable(adev, true);
 830
 831	/* start the gfx rings and rlc compute queues */
 832	r = sdma_v5_2_gfx_resume(adev);
 833	if (r)
 834		return r;
 835	r = sdma_v5_2_rlc_resume(adev);
 836
 837	return r;
 838}
 839
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 840/**
 841 * sdma_v5_2_ring_test_ring - simple async dma engine test
 842 *
 843 * @ring: amdgpu_ring structure holding ring information
 844 *
 845 * Test the DMA engine by writing using it to write an
 846 * value to memory.
 847 * Returns 0 for success, error for failure.
 848 */
 849static int sdma_v5_2_ring_test_ring(struct amdgpu_ring *ring)
 850{
 851	struct amdgpu_device *adev = ring->adev;
 852	unsigned i;
 853	unsigned index;
 854	int r;
 855	u32 tmp;
 856	u64 gpu_addr;
 
 857
 858	r = amdgpu_device_wb_get(adev, &index);
 859	if (r) {
 860		dev_err(adev->dev, "(%d) failed to allocate wb slot\n", r);
 861		return r;
 862	}
 863
 864	gpu_addr = adev->wb.gpu_addr + (index * 4);
 865	tmp = 0xCAFEDEAD;
 866	adev->wb.wb[index] = cpu_to_le32(tmp);
 867
 868	r = amdgpu_ring_alloc(ring, 5);
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 869	if (r) {
 870		DRM_ERROR("amdgpu: dma failed to lock ring %d (%d).\n", ring->idx, r);
 871		amdgpu_device_wb_free(adev, index);
 
 872		return r;
 873	}
 874
 875	amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
 876			  SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR));
 877	amdgpu_ring_write(ring, lower_32_bits(gpu_addr));
 878	amdgpu_ring_write(ring, upper_32_bits(gpu_addr));
 879	amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0));
 880	amdgpu_ring_write(ring, 0xDEADBEEF);
 881	amdgpu_ring_commit(ring);
 882
 883	for (i = 0; i < adev->usec_timeout; i++) {
 884		tmp = le32_to_cpu(adev->wb.wb[index]);
 
 
 
 885		if (tmp == 0xDEADBEEF)
 886			break;
 887		if (amdgpu_emu_mode == 1)
 888			msleep(1);
 889		else
 890			udelay(1);
 891	}
 892
 893	if (i >= adev->usec_timeout)
 894		r = -ETIMEDOUT;
 895
 896	amdgpu_device_wb_free(adev, index);
 
 897
 898	return r;
 899}
 900
 901/**
 902 * sdma_v5_2_ring_test_ib - test an IB on the DMA engine
 903 *
 904 * @ring: amdgpu_ring structure holding ring information
 
 905 *
 906 * Test a simple IB in the DMA ring.
 907 * Returns 0 on success, error on failure.
 908 */
 909static int sdma_v5_2_ring_test_ib(struct amdgpu_ring *ring, long timeout)
 910{
 911	struct amdgpu_device *adev = ring->adev;
 912	struct amdgpu_ib ib;
 913	struct dma_fence *f = NULL;
 914	unsigned index;
 915	long r;
 916	u32 tmp = 0;
 917	u64 gpu_addr;
 
 918
 919	r = amdgpu_device_wb_get(adev, &index);
 920	if (r) {
 921		dev_err(adev->dev, "(%ld) failed to allocate wb slot\n", r);
 922		return r;
 923	}
 924
 925	gpu_addr = adev->wb.gpu_addr + (index * 4);
 926	tmp = 0xCAFEDEAD;
 927	adev->wb.wb[index] = cpu_to_le32(tmp);
 928	memset(&ib, 0, sizeof(ib));
 929	r = amdgpu_ib_get(adev, NULL, 256, AMDGPU_IB_POOL_DIRECT, &ib);
 930	if (r) {
 931		DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r);
 932		goto err0;
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 933	}
 934
 935	ib.ptr[0] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
 936		SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR);
 937	ib.ptr[1] = lower_32_bits(gpu_addr);
 938	ib.ptr[2] = upper_32_bits(gpu_addr);
 939	ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0);
 940	ib.ptr[4] = 0xDEADBEEF;
 941	ib.ptr[5] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
 942	ib.ptr[6] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
 943	ib.ptr[7] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
 944	ib.length_dw = 8;
 945
 946	r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
 947	if (r)
 948		goto err1;
 949
 950	r = dma_fence_wait_timeout(f, false, timeout);
 951	if (r == 0) {
 952		DRM_ERROR("amdgpu: IB test timed out\n");
 953		r = -ETIMEDOUT;
 954		goto err1;
 955	} else if (r < 0) {
 956		DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r);
 957		goto err1;
 958	}
 959	tmp = le32_to_cpu(adev->wb.wb[index]);
 
 
 
 
 
 960	if (tmp == 0xDEADBEEF)
 961		r = 0;
 962	else
 963		r = -EINVAL;
 964
 965err1:
 966	amdgpu_ib_free(adev, &ib, NULL);
 967	dma_fence_put(f);
 968err0:
 969	amdgpu_device_wb_free(adev, index);
 
 970	return r;
 971}
 972
 973
 974/**
 975 * sdma_v5_2_vm_copy_pte - update PTEs by copying them from the GART
 976 *
 977 * @ib: indirect buffer to fill with commands
 978 * @pe: addr of the page entry
 979 * @src: src addr to copy from
 980 * @count: number of page entries to update
 981 *
 982 * Update PTEs by copying them from the GART using sDMA.
 983 */
 984static void sdma_v5_2_vm_copy_pte(struct amdgpu_ib *ib,
 985				  uint64_t pe, uint64_t src,
 986				  unsigned count)
 987{
 988	unsigned bytes = count * 8;
 989
 990	ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
 991		SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR);
 992	ib->ptr[ib->length_dw++] = bytes - 1;
 993	ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
 994	ib->ptr[ib->length_dw++] = lower_32_bits(src);
 995	ib->ptr[ib->length_dw++] = upper_32_bits(src);
 996	ib->ptr[ib->length_dw++] = lower_32_bits(pe);
 997	ib->ptr[ib->length_dw++] = upper_32_bits(pe);
 998
 999}
1000
1001/**
1002 * sdma_v5_2_vm_write_pte - update PTEs by writing them manually
1003 *
1004 * @ib: indirect buffer to fill with commands
1005 * @pe: addr of the page entry
1006 * @addr: dst addr to write into pe
1007 * @count: number of page entries to update
1008 * @incr: increase next addr by incr bytes
1009 * @flags: access flags
1010 *
1011 * Update PTEs by writing them manually using sDMA.
1012 */
1013static void sdma_v5_2_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe,
1014				   uint64_t value, unsigned count,
1015				   uint32_t incr)
1016{
1017	unsigned ndw = count * 2;
1018
1019	ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
1020		SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR);
1021	ib->ptr[ib->length_dw++] = lower_32_bits(pe);
1022	ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1023	ib->ptr[ib->length_dw++] = ndw - 1;
1024	for (; ndw > 0; ndw -= 2) {
1025		ib->ptr[ib->length_dw++] = lower_32_bits(value);
1026		ib->ptr[ib->length_dw++] = upper_32_bits(value);
1027		value += incr;
1028	}
1029}
1030
1031/**
1032 * sdma_v5_2_vm_set_pte_pde - update the page tables using sDMA
1033 *
1034 * @ib: indirect buffer to fill with commands
1035 * @pe: addr of the page entry
1036 * @addr: dst addr to write into pe
1037 * @count: number of page entries to update
1038 * @incr: increase next addr by incr bytes
1039 * @flags: access flags
1040 *
1041 * Update the page tables using sDMA.
1042 */
1043static void sdma_v5_2_vm_set_pte_pde(struct amdgpu_ib *ib,
1044				     uint64_t pe,
1045				     uint64_t addr, unsigned count,
1046				     uint32_t incr, uint64_t flags)
1047{
1048	/* for physically contiguous pages (vram) */
1049	ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_PTEPDE);
1050	ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */
1051	ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1052	ib->ptr[ib->length_dw++] = lower_32_bits(flags); /* mask */
1053	ib->ptr[ib->length_dw++] = upper_32_bits(flags);
1054	ib->ptr[ib->length_dw++] = lower_32_bits(addr); /* value */
1055	ib->ptr[ib->length_dw++] = upper_32_bits(addr);
1056	ib->ptr[ib->length_dw++] = incr; /* increment size */
1057	ib->ptr[ib->length_dw++] = 0;
1058	ib->ptr[ib->length_dw++] = count - 1; /* number of entries */
1059}
1060
1061/**
1062 * sdma_v5_2_ring_pad_ib - pad the IB
1063 *
1064 * @ib: indirect buffer to fill with padding
 
1065 *
1066 * Pad the IB with NOPs to a boundary multiple of 8.
1067 */
1068static void sdma_v5_2_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib)
1069{
1070	struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring);
1071	u32 pad_count;
1072	int i;
1073
1074	pad_count = (-ib->length_dw) & 0x7;
1075	for (i = 0; i < pad_count; i++)
1076		if (sdma && sdma->burst_nop && (i == 0))
1077			ib->ptr[ib->length_dw++] =
1078				SDMA_PKT_HEADER_OP(SDMA_OP_NOP) |
1079				SDMA_PKT_NOP_HEADER_COUNT(pad_count - 1);
1080		else
1081			ib->ptr[ib->length_dw++] =
1082				SDMA_PKT_HEADER_OP(SDMA_OP_NOP);
1083}
1084
1085
1086/**
1087 * sdma_v5_2_ring_emit_pipeline_sync - sync the pipeline
1088 *
1089 * @ring: amdgpu_ring pointer
1090 *
1091 * Make sure all previous operations are completed (CIK).
1092 */
1093static void sdma_v5_2_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
1094{
1095	uint32_t seq = ring->fence_drv.sync_seq;
1096	uint64_t addr = ring->fence_drv.gpu_addr;
1097
1098	/* wait for idle */
1099	amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
1100			  SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) |
1101			  SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3) | /* equal */
1102			  SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL(1));
1103	amdgpu_ring_write(ring, addr & 0xfffffffc);
1104	amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff);
1105	amdgpu_ring_write(ring, seq); /* reference */
1106	amdgpu_ring_write(ring, 0xffffffff); /* mask */
1107	amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
1108			  SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(4)); /* retry count, poll interval */
1109}
1110
1111
1112/**
1113 * sdma_v5_2_ring_emit_vm_flush - vm flush using sDMA
1114 *
1115 * @ring: amdgpu_ring pointer
1116 * @vm: amdgpu_vm pointer
 
1117 *
1118 * Update the page table base and flush the VM TLB
1119 * using sDMA.
1120 */
1121static void sdma_v5_2_ring_emit_vm_flush(struct amdgpu_ring *ring,
1122					 unsigned vmid, uint64_t pd_addr)
1123{
1124	amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1125}
1126
1127static void sdma_v5_2_ring_emit_wreg(struct amdgpu_ring *ring,
1128				     uint32_t reg, uint32_t val)
1129{
1130	amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
1131			  SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
1132	amdgpu_ring_write(ring, reg);
1133	amdgpu_ring_write(ring, val);
1134}
1135
1136static void sdma_v5_2_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
1137					 uint32_t val, uint32_t mask)
1138{
1139	amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
1140			  SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) |
1141			  SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* equal */
1142	amdgpu_ring_write(ring, reg << 2);
1143	amdgpu_ring_write(ring, 0);
1144	amdgpu_ring_write(ring, val); /* reference */
1145	amdgpu_ring_write(ring, mask); /* mask */
1146	amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
1147			  SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10));
1148}
1149
1150static void sdma_v5_2_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring,
1151						   uint32_t reg0, uint32_t reg1,
1152						   uint32_t ref, uint32_t mask)
1153{
1154	amdgpu_ring_emit_wreg(ring, reg0, ref);
1155	/* wait for a cycle to reset vm_inv_eng*_ack */
1156	amdgpu_ring_emit_reg_wait(ring, reg0, 0, 0);
1157	amdgpu_ring_emit_reg_wait(ring, reg1, mask, mask);
1158}
1159
1160static int sdma_v5_2_early_init(void *handle)
1161{
1162	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 
1163
1164	switch (adev->asic_type) {
1165	case CHIP_SIENNA_CICHLID:
1166		adev->sdma.num_instances = 4;
1167		break;
1168	case CHIP_NAVY_FLOUNDER:
1169		adev->sdma.num_instances = 2;
1170		break;
1171	default:
1172		break;
1173	}
1174
1175	sdma_v5_2_set_ring_funcs(adev);
1176	sdma_v5_2_set_buffer_funcs(adev);
1177	sdma_v5_2_set_vm_pte_funcs(adev);
1178	sdma_v5_2_set_irq_funcs(adev);
 
1179
1180	return 0;
1181}
1182
1183static unsigned sdma_v5_2_seq_to_irq_id(int seq_num)
1184{
1185	switch (seq_num) {
1186	case 0:
1187		return SOC15_IH_CLIENTID_SDMA0;
1188	case 1:
1189		return SOC15_IH_CLIENTID_SDMA1;
1190	case 2:
1191		return SOC15_IH_CLIENTID_SDMA2;
1192	case 3:
1193		return SOC15_IH_CLIENTID_SDMA3_Sienna_Cichlid;
1194	default:
1195		break;
1196	}
1197	return -EINVAL;
1198}
1199
1200static unsigned sdma_v5_2_seq_to_trap_id(int seq_num)
1201{
1202	switch (seq_num) {
1203	case 0:
1204		return SDMA0_5_0__SRCID__SDMA_TRAP;
1205	case 1:
1206		return SDMA1_5_0__SRCID__SDMA_TRAP;
1207	case 2:
1208		return SDMA2_5_0__SRCID__SDMA_TRAP;
1209	case 3:
1210		return SDMA3_5_0__SRCID__SDMA_TRAP;
1211	default:
1212		break;
1213	}
1214	return -EINVAL;
1215}
1216
1217static int sdma_v5_2_sw_init(void *handle)
1218{
1219	struct amdgpu_ring *ring;
1220	int r, i;
1221	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 
 
1222
1223	/* SDMA trap event */
1224	for (i = 0; i < adev->sdma.num_instances; i++) {
1225		r = amdgpu_irq_add_id(adev, sdma_v5_2_seq_to_irq_id(i),
1226				      sdma_v5_2_seq_to_trap_id(i),
1227				      &adev->sdma.trap_irq);
1228		if (r)
1229			return r;
1230	}
1231
1232	r = sdma_v5_2_init_microcode(adev);
1233	if (r) {
1234		DRM_ERROR("Failed to load sdma firmware!\n");
1235		return r;
1236	}
1237
1238	for (i = 0; i < adev->sdma.num_instances; i++) {
1239		ring = &adev->sdma.instance[i].ring;
1240		ring->ring_obj = NULL;
1241		ring->use_doorbell = true;
1242		ring->me = i;
1243
1244		DRM_INFO("use_doorbell being set to: [%s]\n",
1245				ring->use_doorbell?"true":"false");
1246
1247		ring->doorbell_index =
1248			(adev->doorbell_index.sdma_engine[i] << 1); //get DWORD offset
1249
 
1250		sprintf(ring->name, "sdma%d", i);
1251		r = amdgpu_ring_init(adev, ring, 1024,
1252				     &adev->sdma.trap_irq,
1253				     AMDGPU_SDMA_IRQ_INSTANCE0 + i,
1254				     AMDGPU_RING_PRIO_DEFAULT);
1255		if (r)
1256			return r;
1257	}
1258
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1259	return r;
1260}
1261
1262static int sdma_v5_2_sw_fini(void *handle)
1263{
1264	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1265	int i;
1266
1267	for (i = 0; i < adev->sdma.num_instances; i++)
1268		amdgpu_ring_fini(&adev->sdma.instance[i].ring);
1269
1270	sdma_v5_2_destroy_inst_ctx(adev);
 
 
 
1271
1272	return 0;
1273}
1274
1275static int sdma_v5_2_hw_init(void *handle)
1276{
1277	int r;
1278	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1279
1280	sdma_v5_2_init_golden_registers(adev);
1281
1282	r = sdma_v5_2_start(adev);
1283
1284	return r;
1285}
1286
1287static int sdma_v5_2_hw_fini(void *handle)
1288{
1289	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1290
1291	if (amdgpu_sriov_vf(adev))
1292		return 0;
1293
1294	sdma_v5_2_ctx_switch_enable(adev, false);
1295	sdma_v5_2_enable(adev, false);
1296
1297	return 0;
1298}
1299
1300static int sdma_v5_2_suspend(void *handle)
1301{
1302	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1303
1304	return sdma_v5_2_hw_fini(adev);
1305}
1306
1307static int sdma_v5_2_resume(void *handle)
1308{
1309	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1310
1311	return sdma_v5_2_hw_init(adev);
1312}
1313
1314static bool sdma_v5_2_is_idle(void *handle)
1315{
1316	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1317	u32 i;
1318
1319	for (i = 0; i < adev->sdma.num_instances; i++) {
1320		u32 tmp = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_STATUS_REG));
1321
1322		if (!(tmp & SDMA0_STATUS_REG__IDLE_MASK))
1323			return false;
1324	}
1325
1326	return true;
1327}
1328
1329static int sdma_v5_2_wait_for_idle(void *handle)
1330{
1331	unsigned i;
1332	u32 sdma0, sdma1, sdma2, sdma3;
1333	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1334
1335	for (i = 0; i < adev->usec_timeout; i++) {
1336		sdma0 = RREG32(sdma_v5_2_get_reg_offset(adev, 0, mmSDMA0_STATUS_REG));
1337		sdma1 = RREG32(sdma_v5_2_get_reg_offset(adev, 1, mmSDMA0_STATUS_REG));
1338		sdma2 = RREG32(sdma_v5_2_get_reg_offset(adev, 2, mmSDMA0_STATUS_REG));
1339		sdma3 = RREG32(sdma_v5_2_get_reg_offset(adev, 3, mmSDMA0_STATUS_REG));
1340
1341		if (sdma0 & sdma1 & sdma2 & sdma3 & SDMA0_STATUS_REG__IDLE_MASK)
1342			return 0;
1343		udelay(1);
1344	}
1345	return -ETIMEDOUT;
1346}
1347
1348static int sdma_v5_2_soft_reset(void *handle)
1349{
1350	/* todo */
 
 
1351
1352	return 0;
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1353}
1354
1355static int sdma_v5_2_ring_preempt_ib(struct amdgpu_ring *ring)
1356{
1357	int i, r = 0;
1358	struct amdgpu_device *adev = ring->adev;
1359	u32 index = 0;
1360	u64 sdma_gfx_preempt;
1361
1362	amdgpu_sdma_get_index_from_ring(ring, &index);
1363	sdma_gfx_preempt =
1364		sdma_v5_2_get_reg_offset(adev, index, mmSDMA0_GFX_PREEMPT);
1365
1366	/* assert preemption condition */
1367	amdgpu_ring_set_preempt_cond_exec(ring, false);
1368
1369	/* emit the trailing fence */
1370	ring->trail_seq += 1;
1371	amdgpu_ring_alloc(ring, 10);
1372	sdma_v5_2_ring_emit_fence(ring, ring->trail_fence_gpu_addr,
1373				  ring->trail_seq, 0);
1374	amdgpu_ring_commit(ring);
1375
1376	/* assert IB preemption */
1377	WREG32(sdma_gfx_preempt, 1);
1378
1379	/* poll the trailing fence */
1380	for (i = 0; i < adev->usec_timeout; i++) {
1381		if (ring->trail_seq ==
1382		    le32_to_cpu(*(ring->trail_fence_cpu_addr)))
1383			break;
1384		udelay(1);
1385	}
1386
1387	if (i >= adev->usec_timeout) {
1388		r = -EINVAL;
1389		DRM_ERROR("ring %d failed to be preempted\n", ring->idx);
1390	}
1391
1392	/* deassert IB preemption */
1393	WREG32(sdma_gfx_preempt, 0);
1394
1395	/* deassert the preemption condition */
1396	amdgpu_ring_set_preempt_cond_exec(ring, true);
1397	return r;
1398}
1399
1400static int sdma_v5_2_set_trap_irq_state(struct amdgpu_device *adev,
1401					struct amdgpu_irq_src *source,
1402					unsigned type,
1403					enum amdgpu_interrupt_state state)
1404{
1405	u32 sdma_cntl;
1406
1407	u32 reg_offset = sdma_v5_2_get_reg_offset(adev, type, mmSDMA0_CNTL);
1408
1409	sdma_cntl = RREG32(reg_offset);
1410	sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE,
1411		       state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
1412	WREG32(reg_offset, sdma_cntl);
 
 
1413
1414	return 0;
1415}
1416
1417static int sdma_v5_2_process_trap_irq(struct amdgpu_device *adev,
1418				      struct amdgpu_irq_src *source,
1419				      struct amdgpu_iv_entry *entry)
1420{
 
 
1421	DRM_DEBUG("IH: SDMA trap\n");
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1422	switch (entry->client_id) {
1423	case SOC15_IH_CLIENTID_SDMA0:
1424		switch (entry->ring_id) {
1425		case 0:
1426			amdgpu_fence_process(&adev->sdma.instance[0].ring);
1427			break;
1428		case 1:
1429			/* XXX compute */
1430			break;
1431		case 2:
1432			/* XXX compute */
1433			break;
1434		case 3:
1435			/* XXX page queue*/
1436			break;
1437		}
1438		break;
1439	case SOC15_IH_CLIENTID_SDMA1:
1440		switch (entry->ring_id) {
1441		case 0:
1442			amdgpu_fence_process(&adev->sdma.instance[1].ring);
1443			break;
1444		case 1:
1445			/* XXX compute */
1446			break;
1447		case 2:
1448			/* XXX compute */
1449			break;
1450		case 3:
1451			/* XXX page queue*/
1452			break;
1453		}
1454		break;
1455	case SOC15_IH_CLIENTID_SDMA2:
1456		switch (entry->ring_id) {
1457		case 0:
1458			amdgpu_fence_process(&adev->sdma.instance[2].ring);
1459			break;
1460		case 1:
1461			/* XXX compute */
1462			break;
1463		case 2:
1464			/* XXX compute */
1465			break;
1466		case 3:
1467			/* XXX page queue*/
1468			break;
1469		}
1470		break;
1471	case SOC15_IH_CLIENTID_SDMA3_Sienna_Cichlid:
1472		switch (entry->ring_id) {
1473		case 0:
1474			amdgpu_fence_process(&adev->sdma.instance[3].ring);
1475			break;
1476		case 1:
1477			/* XXX compute */
1478			break;
1479		case 2:
1480			/* XXX compute */
1481			break;
1482		case 3:
1483			/* XXX page queue*/
1484			break;
1485		}
1486		break;
1487	}
1488	return 0;
1489}
1490
1491static int sdma_v5_2_process_illegal_inst_irq(struct amdgpu_device *adev,
1492					      struct amdgpu_irq_src *source,
1493					      struct amdgpu_iv_entry *entry)
1494{
1495	return 0;
1496}
1497
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1498static void sdma_v5_2_update_medium_grain_clock_gating(struct amdgpu_device *adev,
1499						       bool enable)
1500{
1501	uint32_t data, def;
1502	int i;
1503
1504	for (i = 0; i < adev->sdma.num_instances; i++) {
 
 
 
 
1505		if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG)) {
1506			/* Enable sdma clock gating */
1507			def = data = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL));
1508			data &= ~(SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK |
1509				  SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK |
1510				  SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK |
1511				  SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK |
1512				  SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK |
1513				  SDMA0_CLK_CTRL__SOFT_OVERRIDER_REG_MASK);
1514			if (def != data)
1515				WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL), data);
1516		} else {
1517			/* Disable sdma clock gating */
1518			def = data = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL));
1519			data |= (SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK |
1520				 SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK |
1521				 SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK |
1522				 SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK |
1523				 SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK |
1524				 SDMA0_CLK_CTRL__SOFT_OVERRIDER_REG_MASK);
1525			if (def != data)
1526				WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL), data);
1527		}
1528	}
1529}
1530
1531static void sdma_v5_2_update_medium_grain_light_sleep(struct amdgpu_device *adev,
1532						      bool enable)
1533{
1534	uint32_t data, def;
1535	int i;
1536
1537	for (i = 0; i < adev->sdma.num_instances; i++) {
 
 
 
 
 
1538		if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_LS)) {
1539			/* Enable sdma mem light sleep */
1540			def = data = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL));
1541			data |= SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK;
1542			if (def != data)
1543				WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL), data);
1544
1545		} else {
1546			/* Disable sdma mem light sleep */
1547			def = data = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL));
1548			data &= ~SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK;
1549			if (def != data)
1550				WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL), data);
1551
1552		}
1553	}
1554}
1555
1556static int sdma_v5_2_set_clockgating_state(void *handle,
1557					   enum amd_clockgating_state state)
1558{
1559	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1560
1561	if (amdgpu_sriov_vf(adev))
1562		return 0;
1563
1564	switch (adev->asic_type) {
1565	case CHIP_SIENNA_CICHLID:
1566	case CHIP_NAVY_FLOUNDER:
 
 
 
 
 
 
1567		sdma_v5_2_update_medium_grain_clock_gating(adev,
1568				state == AMD_CG_STATE_GATE ? true : false);
1569		sdma_v5_2_update_medium_grain_light_sleep(adev,
1570				state == AMD_CG_STATE_GATE ? true : false);
1571		break;
1572	default:
1573		break;
1574	}
1575
1576	return 0;
1577}
1578
1579static int sdma_v5_2_set_powergating_state(void *handle,
1580					  enum amd_powergating_state state)
1581{
1582	return 0;
1583}
1584
1585static void sdma_v5_2_get_clockgating_state(void *handle, u32 *flags)
1586{
1587	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1588	int data;
1589
1590	if (amdgpu_sriov_vf(adev))
1591		*flags = 0;
1592
 
 
 
 
 
1593	/* AMD_CG_SUPPORT_SDMA_LS */
1594	data = RREG32_KIQ(sdma_v5_2_get_reg_offset(adev, 0, mmSDMA0_POWER_CNTL));
1595	if (data & SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK)
1596		*flags |= AMD_CG_SUPPORT_SDMA_LS;
1597}
1598
1599const struct amd_ip_funcs sdma_v5_2_ip_funcs = {
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1600	.name = "sdma_v5_2",
1601	.early_init = sdma_v5_2_early_init,
1602	.late_init = NULL,
1603	.sw_init = sdma_v5_2_sw_init,
1604	.sw_fini = sdma_v5_2_sw_fini,
1605	.hw_init = sdma_v5_2_hw_init,
1606	.hw_fini = sdma_v5_2_hw_fini,
1607	.suspend = sdma_v5_2_suspend,
1608	.resume = sdma_v5_2_resume,
1609	.is_idle = sdma_v5_2_is_idle,
1610	.wait_for_idle = sdma_v5_2_wait_for_idle,
1611	.soft_reset = sdma_v5_2_soft_reset,
1612	.set_clockgating_state = sdma_v5_2_set_clockgating_state,
1613	.set_powergating_state = sdma_v5_2_set_powergating_state,
1614	.get_clockgating_state = sdma_v5_2_get_clockgating_state,
 
 
1615};
1616
1617static const struct amdgpu_ring_funcs sdma_v5_2_ring_funcs = {
1618	.type = AMDGPU_RING_TYPE_SDMA,
1619	.align_mask = 0xf,
1620	.nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP),
1621	.support_64bit_ptrs = true,
1622	.vmhub = AMDGPU_GFXHUB_0,
1623	.get_rptr = sdma_v5_2_ring_get_rptr,
1624	.get_wptr = sdma_v5_2_ring_get_wptr,
1625	.set_wptr = sdma_v5_2_ring_set_wptr,
1626	.emit_frame_size =
1627		5 + /* sdma_v5_2_ring_init_cond_exec */
1628		6 + /* sdma_v5_2_ring_emit_hdp_flush */
1629		3 + /* hdp_invalidate */
1630		6 + /* sdma_v5_2_ring_emit_pipeline_sync */
1631		/* sdma_v5_2_ring_emit_vm_flush */
1632		SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 +
1633		SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6 +
1634		10 + 10 + 10, /* sdma_v5_2_ring_emit_fence x3 for user fence, vm fence */
1635	.emit_ib_size = 7 + 6, /* sdma_v5_2_ring_emit_ib */
1636	.emit_ib = sdma_v5_2_ring_emit_ib,
 
1637	.emit_fence = sdma_v5_2_ring_emit_fence,
1638	.emit_pipeline_sync = sdma_v5_2_ring_emit_pipeline_sync,
1639	.emit_vm_flush = sdma_v5_2_ring_emit_vm_flush,
1640	.emit_hdp_flush = sdma_v5_2_ring_emit_hdp_flush,
1641	.test_ring = sdma_v5_2_ring_test_ring,
1642	.test_ib = sdma_v5_2_ring_test_ib,
1643	.insert_nop = sdma_v5_2_ring_insert_nop,
1644	.pad_ib = sdma_v5_2_ring_pad_ib,
 
 
1645	.emit_wreg = sdma_v5_2_ring_emit_wreg,
1646	.emit_reg_wait = sdma_v5_2_ring_emit_reg_wait,
1647	.emit_reg_write_reg_wait = sdma_v5_2_ring_emit_reg_write_reg_wait,
1648	.init_cond_exec = sdma_v5_2_ring_init_cond_exec,
1649	.patch_cond_exec = sdma_v5_2_ring_patch_cond_exec,
1650	.preempt_ib = sdma_v5_2_ring_preempt_ib,
 
1651};
1652
1653static void sdma_v5_2_set_ring_funcs(struct amdgpu_device *adev)
1654{
1655	int i;
1656
1657	for (i = 0; i < adev->sdma.num_instances; i++) {
1658		adev->sdma.instance[i].ring.funcs = &sdma_v5_2_ring_funcs;
1659		adev->sdma.instance[i].ring.me = i;
1660	}
1661}
1662
1663static const struct amdgpu_irq_src_funcs sdma_v5_2_trap_irq_funcs = {
1664	.set = sdma_v5_2_set_trap_irq_state,
1665	.process = sdma_v5_2_process_trap_irq,
1666};
1667
1668static const struct amdgpu_irq_src_funcs sdma_v5_2_illegal_inst_irq_funcs = {
1669	.process = sdma_v5_2_process_illegal_inst_irq,
1670};
1671
1672static void sdma_v5_2_set_irq_funcs(struct amdgpu_device *adev)
1673{
1674	adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_INSTANCE0 +
1675					adev->sdma.num_instances;
1676	adev->sdma.trap_irq.funcs = &sdma_v5_2_trap_irq_funcs;
1677	adev->sdma.illegal_inst_irq.funcs = &sdma_v5_2_illegal_inst_irq_funcs;
1678}
1679
1680/**
1681 * sdma_v5_2_emit_copy_buffer - copy buffer using the sDMA engine
1682 *
1683 * @ring: amdgpu_ring structure holding ring information
1684 * @src_offset: src GPU address
1685 * @dst_offset: dst GPU address
1686 * @byte_count: number of bytes to xfer
 
1687 *
1688 * Copy GPU buffers using the DMA engine.
1689 * Used by the amdgpu ttm implementation to move pages if
1690 * registered as the asic copy callback.
1691 */
1692static void sdma_v5_2_emit_copy_buffer(struct amdgpu_ib *ib,
1693				       uint64_t src_offset,
1694				       uint64_t dst_offset,
1695				       uint32_t byte_count,
1696				       bool tmz)
1697{
1698	ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
1699		SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR) |
1700		SDMA_PKT_COPY_LINEAR_HEADER_TMZ(tmz ? 1 : 0);
1701	ib->ptr[ib->length_dw++] = byte_count - 1;
1702	ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
1703	ib->ptr[ib->length_dw++] = lower_32_bits(src_offset);
1704	ib->ptr[ib->length_dw++] = upper_32_bits(src_offset);
1705	ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1706	ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
1707}
1708
1709/**
1710 * sdma_v5_2_emit_fill_buffer - fill buffer using the sDMA engine
1711 *
1712 * @ring: amdgpu_ring structure holding ring information
1713 * @src_data: value to write to buffer
1714 * @dst_offset: dst GPU address
1715 * @byte_count: number of bytes to xfer
1716 *
1717 * Fill GPU buffers using the DMA engine.
1718 */
1719static void sdma_v5_2_emit_fill_buffer(struct amdgpu_ib *ib,
1720				       uint32_t src_data,
1721				       uint64_t dst_offset,
1722				       uint32_t byte_count)
1723{
1724	ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_CONST_FILL);
1725	ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1726	ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
1727	ib->ptr[ib->length_dw++] = src_data;
1728	ib->ptr[ib->length_dw++] = byte_count - 1;
1729}
1730
1731static const struct amdgpu_buffer_funcs sdma_v5_2_buffer_funcs = {
1732	.copy_max_bytes = 0x400000,
1733	.copy_num_dw = 7,
1734	.emit_copy_buffer = sdma_v5_2_emit_copy_buffer,
1735
1736	.fill_max_bytes = 0x400000,
1737	.fill_num_dw = 5,
1738	.emit_fill_buffer = sdma_v5_2_emit_fill_buffer,
1739};
1740
1741static void sdma_v5_2_set_buffer_funcs(struct amdgpu_device *adev)
1742{
1743	if (adev->mman.buffer_funcs == NULL) {
1744		adev->mman.buffer_funcs = &sdma_v5_2_buffer_funcs;
1745		adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring;
1746	}
1747}
1748
1749static const struct amdgpu_vm_pte_funcs sdma_v5_2_vm_pte_funcs = {
1750	.copy_pte_num_dw = 7,
1751	.copy_pte = sdma_v5_2_vm_copy_pte,
1752	.write_pte = sdma_v5_2_vm_write_pte,
1753	.set_pte_pde = sdma_v5_2_vm_set_pte_pde,
1754};
1755
1756static void sdma_v5_2_set_vm_pte_funcs(struct amdgpu_device *adev)
1757{
1758	unsigned i;
1759
1760	if (adev->vm_manager.vm_pte_funcs == NULL) {
1761		adev->vm_manager.vm_pte_funcs = &sdma_v5_2_vm_pte_funcs;
1762		for (i = 0; i < adev->sdma.num_instances; i++) {
1763			adev->vm_manager.vm_pte_scheds[i] =
1764				&adev->sdma.instance[i].ring.sched;
1765		}
1766		adev->vm_manager.vm_pte_num_scheds = adev->sdma.num_instances;
1767	}
1768}
1769
1770const struct amdgpu_ip_block_version sdma_v5_2_ip_block = {
1771	.type = AMD_IP_BLOCK_TYPE_SDMA,
1772	.major = 5,
1773	.minor = 2,
1774	.rev = 0,
1775	.funcs = &sdma_v5_2_ip_funcs,
1776};