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1/*
2 * Copyright 2019 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24#ifndef _AMDGPU_RAS_EEPROM_H
25#define _AMDGPU_RAS_EEPROM_H
26
27#include <linux/i2c.h>
28
29struct amdgpu_device;
30
31enum amdgpu_ras_eeprom_err_type{
32 AMDGPU_RAS_EEPROM_ERR_PLACE_HOLDER,
33 AMDGPU_RAS_EEPROM_ERR_RECOVERABLE,
34 AMDGPU_RAS_EEPROM_ERR_NON_RECOVERABLE
35};
36
37struct amdgpu_ras_eeprom_table_header {
38 uint32_t header;
39 uint32_t version;
40 uint32_t first_rec_offset;
41 uint32_t tbl_size;
42 uint32_t checksum;
43}__attribute__((__packed__));
44
45struct amdgpu_ras_eeprom_control {
46 struct amdgpu_ras_eeprom_table_header tbl_hdr;
47 uint32_t next_addr;
48 unsigned int num_recs;
49 struct mutex tbl_mutex;
50 uint32_t tbl_byte_sum;
51 uint16_t i2c_address; // 8-bit represented address
52};
53
54/*
55 * Represents single table record. Packed to be easily serialized into byte
56 * stream.
57 */
58struct eeprom_table_record {
59
60 union {
61 uint64_t address;
62 uint64_t offset;
63 };
64
65 uint64_t retired_page;
66 uint64_t ts;
67
68 enum amdgpu_ras_eeprom_err_type err_type;
69
70 union {
71 unsigned char bank;
72 unsigned char cu;
73 };
74
75 unsigned char mem_channel;
76 unsigned char mcumc_id;
77}__attribute__((__packed__));
78
79int amdgpu_ras_eeprom_init(struct amdgpu_ras_eeprom_control *control);
80int amdgpu_ras_eeprom_reset_table(struct amdgpu_ras_eeprom_control *control);
81
82int amdgpu_ras_eeprom_process_recods(struct amdgpu_ras_eeprom_control *control,
83 struct eeprom_table_record *records,
84 bool write,
85 int num);
86
87void amdgpu_ras_eeprom_test(struct amdgpu_ras_eeprom_control *control);
88
89#endif // _AMDGPU_RAS_EEPROM_H
1/*
2 * Copyright 2019 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24#ifndef _AMDGPU_RAS_EEPROM_H
25#define _AMDGPU_RAS_EEPROM_H
26
27#include <linux/i2c.h>
28
29struct amdgpu_device;
30
31enum amdgpu_ras_eeprom_err_type {
32 AMDGPU_RAS_EEPROM_ERR_NA,
33 AMDGPU_RAS_EEPROM_ERR_RECOVERABLE,
34 AMDGPU_RAS_EEPROM_ERR_NON_RECOVERABLE,
35 AMDGPU_RAS_EEPROM_ERR_COUNT,
36};
37
38struct amdgpu_ras_eeprom_table_header {
39 uint32_t header;
40 uint32_t version;
41 uint32_t first_rec_offset;
42 uint32_t tbl_size;
43 uint32_t checksum;
44} __packed;
45
46struct amdgpu_ras_eeprom_control {
47 struct amdgpu_ras_eeprom_table_header tbl_hdr;
48
49 /* Base I2C EEPPROM 19-bit memory address,
50 * where the table is located. For more information,
51 * see top of amdgpu_eeprom.c.
52 */
53 u32 i2c_address;
54
55 /* The byte offset off of @i2c_address
56 * where the table header is found,
57 * and where the records start--always
58 * right after the header.
59 */
60 u32 ras_header_offset;
61 u32 ras_record_offset;
62
63 /* Number of records in the table.
64 */
65 u32 ras_num_recs;
66
67 /* First record index to read, 0-based.
68 * Range is [0, num_recs-1]. This is
69 * an absolute index, starting right after
70 * the table header.
71 */
72 u32 ras_fri;
73
74 /* Maximum possible number of records
75 * we could store, i.e. the maximum capacity
76 * of the table.
77 */
78 u32 ras_max_record_count;
79
80 /* Protect table access via this mutex.
81 */
82 struct mutex ras_tbl_mutex;
83
84 /* Record channel info which occurred bad pages
85 */
86 u32 bad_channel_bitmap;
87};
88
89/*
90 * Represents single table record. Packed to be easily serialized into byte
91 * stream.
92 */
93struct eeprom_table_record {
94
95 union {
96 uint64_t address;
97 uint64_t offset;
98 };
99
100 uint64_t retired_page;
101 uint64_t ts;
102
103 enum amdgpu_ras_eeprom_err_type err_type;
104
105 union {
106 unsigned char bank;
107 unsigned char cu;
108 };
109
110 unsigned char mem_channel;
111 unsigned char mcumc_id;
112} __packed;
113
114int amdgpu_ras_eeprom_init(struct amdgpu_ras_eeprom_control *control,
115 bool *exceed_err_limit);
116
117int amdgpu_ras_eeprom_reset_table(struct amdgpu_ras_eeprom_control *control);
118
119bool amdgpu_ras_eeprom_check_err_threshold(struct amdgpu_device *adev);
120
121int amdgpu_ras_eeprom_read(struct amdgpu_ras_eeprom_control *control,
122 struct eeprom_table_record *records, const u32 num);
123
124int amdgpu_ras_eeprom_append(struct amdgpu_ras_eeprom_control *control,
125 struct eeprom_table_record *records, const u32 num);
126
127uint32_t amdgpu_ras_eeprom_max_record_count(void);
128
129void amdgpu_ras_debugfs_set_ret_size(struct amdgpu_ras_eeprom_control *control);
130
131extern const struct file_operations amdgpu_ras_debugfs_eeprom_size_ops;
132extern const struct file_operations amdgpu_ras_debugfs_eeprom_table_ops;
133
134#endif // _AMDGPU_RAS_EEPROM_H