1/*
 2 * Copyright 2019 Advanced Micro Devices, Inc.
 3 *
 4 * Permission is hereby granted, free of charge, to any person obtaining a
 5 * copy of this software and associated documentation files (the "Software"),
 6 * to deal in the Software without restriction, including without limitation
 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 8 * and/or sell copies of the Software, and to permit persons to whom the
 9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24#ifndef _AMDGPU_RAS_EEPROM_H
25#define _AMDGPU_RAS_EEPROM_H
26
27#include <linux/i2c.h>
28
29struct amdgpu_device;
30
31enum amdgpu_ras_eeprom_err_type{
32	AMDGPU_RAS_EEPROM_ERR_PLACE_HOLDER,
33	AMDGPU_RAS_EEPROM_ERR_RECOVERABLE,
34	AMDGPU_RAS_EEPROM_ERR_NON_RECOVERABLE
35};
36
37struct amdgpu_ras_eeprom_table_header {
38	uint32_t header;
39	uint32_t version;
40	uint32_t first_rec_offset;
41	uint32_t tbl_size;
42	uint32_t checksum;
43}__attribute__((__packed__));
44
45struct amdgpu_ras_eeprom_control {
46	struct amdgpu_ras_eeprom_table_header tbl_hdr;
47	uint32_t next_addr;
48	unsigned int num_recs;
49	struct mutex tbl_mutex;
50	uint32_t tbl_byte_sum;
51	uint16_t i2c_address; // 8-bit represented address
52};
53
54/*
55 * Represents single table record. Packed to be easily serialized into byte
56 * stream.
57 */
58struct eeprom_table_record {
59
60	union {
61		uint64_t address;
62		uint64_t offset;
63	};
64
65	uint64_t retired_page;
66	uint64_t ts;
67
68	enum amdgpu_ras_eeprom_err_type err_type;
69
70	union {
71		unsigned char bank;
72		unsigned char cu;
73	};
74
75	unsigned char mem_channel;
76	unsigned char mcumc_id;
77}__attribute__((__packed__));
78
79int amdgpu_ras_eeprom_init(struct amdgpu_ras_eeprom_control *control);
80int amdgpu_ras_eeprom_reset_table(struct amdgpu_ras_eeprom_control *control);
81
82int amdgpu_ras_eeprom_process_recods(struct amdgpu_ras_eeprom_control *control,
83					    struct eeprom_table_record *records,
84					    bool write,
85					    int num);
86
87void amdgpu_ras_eeprom_test(struct amdgpu_ras_eeprom_control *control);
88
89#endif // _AMDGPU_RAS_EEPROM_H