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1/* SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) */
2/* Copyright(c) 2015-17 Intel Corporation. */
3
4#ifndef __SDW_INTEL_LOCAL_H
5#define __SDW_INTEL_LOCAL_H
6
7/**
8 * struct sdw_intel_link_res - Soundwire Intel link resource structure,
9 * typically populated by the controller driver.
10 * @pdev: platform_device
11 * @mmio_base: mmio base of SoundWire registers
12 * @registers: Link IO registers base
13 * @shim: Audio shim pointer
14 * @alh: ALH (Audio Link Hub) pointer
15 * @irq: Interrupt line
16 * @ops: Shim callback ops
17 * @dev: device implementing hw_params and free callbacks
18 * @shim_lock: mutex to handle access to shared SHIM registers
19 * @shim_mask: global pointer to check SHIM register initialization
20 * @cdns: Cadence master descriptor
21 * @list: used to walk-through all masters exposed by the same controller
22 */
23struct sdw_intel_link_res {
24 struct platform_device *pdev;
25 void __iomem *mmio_base; /* not strictly needed, useful for debug */
26 void __iomem *registers;
27 void __iomem *shim;
28 void __iomem *alh;
29 int irq;
30 const struct sdw_intel_ops *ops;
31 struct device *dev;
32 struct mutex *shim_lock; /* protect shared registers */
33 u32 *shim_mask;
34 struct sdw_cdns *cdns;
35 struct list_head list;
36};
37
38struct sdw_intel {
39 struct sdw_cdns cdns;
40 int instance;
41 struct sdw_intel_link_res *link_res;
42#ifdef CONFIG_DEBUG_FS
43 struct dentry *debugfs;
44#endif
45};
46
47#define SDW_INTEL_QUIRK_MASK_BUS_DISABLE BIT(1)
48
49int intel_master_startup(struct platform_device *pdev);
50int intel_master_process_wakeen_event(struct platform_device *pdev);
51
52#endif /* __SDW_INTEL_LOCAL_H */
1/* SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) */
2/* Copyright(c) 2015-17 Intel Corporation. */
3
4#ifndef __SDW_INTEL_LOCAL_H
5#define __SDW_INTEL_LOCAL_H
6
7/**
8 * struct sdw_intel_link_res - Soundwire Intel link resource structure,
9 * typically populated by the controller driver.
10 * @hw_ops: platform-specific ops
11 * @mmio_base: mmio base of SoundWire registers
12 * @registers: Link IO registers base
13 * @shim: Audio shim pointer
14 * @alh: ALH (Audio Link Hub) pointer
15 * @irq: Interrupt line
16 * @ops: Shim callback ops
17 * @dev: device implementing hw_params and free callbacks
18 * @shim_lock: mutex to handle access to shared SHIM registers
19 * @shim_mask: global pointer to check SHIM register initialization
20 * @clock_stop_quirks: mask defining requested behavior on pm_suspend
21 * @link_mask: global mask needed for power-up/down sequences
22 * @cdns: Cadence master descriptor
23 * @list: used to walk-through all masters exposed by the same controller
24 */
25struct sdw_intel_link_res {
26 const struct sdw_intel_hw_ops *hw_ops;
27
28 void __iomem *mmio_base; /* not strictly needed, useful for debug */
29 void __iomem *registers;
30 void __iomem *shim;
31 void __iomem *alh;
32 int irq;
33 const struct sdw_intel_ops *ops;
34 struct device *dev;
35 struct mutex *shim_lock; /* protect shared registers */
36 u32 *shim_mask;
37 u32 clock_stop_quirks;
38 u32 link_mask;
39 struct sdw_cdns *cdns;
40 struct list_head list;
41};
42
43struct sdw_intel {
44 struct sdw_cdns cdns;
45 int instance;
46 struct sdw_intel_link_res *link_res;
47 bool startup_done;
48#ifdef CONFIG_DEBUG_FS
49 struct dentry *debugfs;
50#endif
51};
52
53#define cdns_to_intel(_cdns) container_of(_cdns, struct sdw_intel, cdns)
54
55#define INTEL_MASTER_RESET_ITERATIONS 10
56
57#define SDW_INTEL_CHECK_OPS(sdw, cb) ((sdw) && (sdw)->link_res && (sdw)->link_res->hw_ops && \
58 (sdw)->link_res->hw_ops->cb)
59#define SDW_INTEL_OPS(sdw, cb) ((sdw)->link_res->hw_ops->cb)
60
61static inline void sdw_intel_debugfs_init(struct sdw_intel *sdw)
62{
63 if (SDW_INTEL_CHECK_OPS(sdw, debugfs_init))
64 SDW_INTEL_OPS(sdw, debugfs_init)(sdw);
65}
66
67static inline void sdw_intel_debugfs_exit(struct sdw_intel *sdw)
68{
69 if (SDW_INTEL_CHECK_OPS(sdw, debugfs_exit))
70 SDW_INTEL_OPS(sdw, debugfs_exit)(sdw);
71}
72
73static inline int sdw_intel_register_dai(struct sdw_intel *sdw)
74{
75 if (SDW_INTEL_CHECK_OPS(sdw, register_dai))
76 return SDW_INTEL_OPS(sdw, register_dai)(sdw);
77 return -ENOTSUPP;
78}
79
80static inline void sdw_intel_check_clock_stop(struct sdw_intel *sdw)
81{
82 if (SDW_INTEL_CHECK_OPS(sdw, check_clock_stop))
83 SDW_INTEL_OPS(sdw, check_clock_stop)(sdw);
84}
85
86static inline int sdw_intel_start_bus(struct sdw_intel *sdw)
87{
88 if (SDW_INTEL_CHECK_OPS(sdw, start_bus))
89 return SDW_INTEL_OPS(sdw, start_bus)(sdw);
90 return -ENOTSUPP;
91}
92
93static inline int sdw_intel_start_bus_after_reset(struct sdw_intel *sdw)
94{
95 if (SDW_INTEL_CHECK_OPS(sdw, start_bus_after_reset))
96 return SDW_INTEL_OPS(sdw, start_bus_after_reset)(sdw);
97 return -ENOTSUPP;
98}
99
100static inline int sdw_intel_start_bus_after_clock_stop(struct sdw_intel *sdw)
101{
102 if (SDW_INTEL_CHECK_OPS(sdw, start_bus_after_clock_stop))
103 return SDW_INTEL_OPS(sdw, start_bus_after_clock_stop)(sdw);
104 return -ENOTSUPP;
105}
106
107static inline int sdw_intel_stop_bus(struct sdw_intel *sdw, bool clock_stop)
108{
109 if (SDW_INTEL_CHECK_OPS(sdw, stop_bus))
110 return SDW_INTEL_OPS(sdw, stop_bus)(sdw, clock_stop);
111 return -ENOTSUPP;
112}
113
114static inline int sdw_intel_link_power_up(struct sdw_intel *sdw)
115{
116 if (SDW_INTEL_CHECK_OPS(sdw, link_power_up))
117 return SDW_INTEL_OPS(sdw, link_power_up)(sdw);
118 return -ENOTSUPP;
119}
120
121static inline int sdw_intel_link_power_down(struct sdw_intel *sdw)
122{
123 if (SDW_INTEL_CHECK_OPS(sdw, link_power_down))
124 return SDW_INTEL_OPS(sdw, link_power_down)(sdw);
125 return -ENOTSUPP;
126}
127
128static inline int sdw_intel_shim_check_wake(struct sdw_intel *sdw)
129{
130 if (SDW_INTEL_CHECK_OPS(sdw, shim_check_wake))
131 return SDW_INTEL_OPS(sdw, shim_check_wake)(sdw);
132 return -ENOTSUPP;
133}
134
135static inline void sdw_intel_shim_wake(struct sdw_intel *sdw, bool wake_enable)
136{
137 if (SDW_INTEL_CHECK_OPS(sdw, shim_wake))
138 SDW_INTEL_OPS(sdw, shim_wake)(sdw, wake_enable);
139}
140
141#endif /* __SDW_INTEL_LOCAL_H */