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  1// SPDX-License-Identifier: GPL-2.0
  2/*
  3 * Texas Instruments TSC2046 SPI ADC driver
  4 *
  5 * Copyright (c) 2021 Oleksij Rempel <kernel@pengutronix.de>, Pengutronix
  6 */
  7
  8#include <linux/bitfield.h>
  9#include <linux/cleanup.h>
 10#include <linux/delay.h>
 11#include <linux/module.h>
 12#include <linux/regulator/consumer.h>
 13#include <linux/spi/spi.h>
 14#include <linux/units.h>
 15
 16#include <linux/unaligned.h>
 17
 18#include <linux/iio/buffer.h>
 19#include <linux/iio/trigger_consumer.h>
 20#include <linux/iio/triggered_buffer.h>
 21#include <linux/iio/trigger.h>
 22
 23/*
 24 * The PENIRQ of TSC2046 controller is implemented as level shifter attached to
 25 * the X+ line. If voltage of the X+ line reaches a specific level the IRQ will
 26 * be activated or deactivated.
 27 * To make this kind of IRQ reusable as trigger following additions were
 28 * implemented:
 29 * - rate limiting:
 30 *   For typical touchscreen use case, we need to trigger about each 10ms.
 31 * - hrtimer:
 32 *   Continue triggering at least once after the IRQ was deactivated. Then
 33 *   deactivate this trigger to stop sampling in order to reduce power
 34 *   consumption.
 35 */
 36
 37#define TI_TSC2046_NAME				"tsc2046"
 38
 39/* This driver doesn't aim at the peak continuous sample rate */
 40#define	TI_TSC2046_MAX_SAMPLE_RATE		125000
 41#define	TI_TSC2046_SAMPLE_BITS \
 42	BITS_PER_TYPE(struct tsc2046_adc_atom)
 43#define	TI_TSC2046_MAX_CLK_FREQ \
 44	(TI_TSC2046_MAX_SAMPLE_RATE * TI_TSC2046_SAMPLE_BITS)
 45
 46#define TI_TSC2046_SAMPLE_INTERVAL_US		10000
 47
 48#define TI_TSC2046_START			BIT(7)
 49#define TI_TSC2046_ADDR				GENMASK(6, 4)
 50#define TI_TSC2046_ADDR_TEMP1			7
 51#define TI_TSC2046_ADDR_AUX			6
 52#define TI_TSC2046_ADDR_X			5
 53#define TI_TSC2046_ADDR_Z2			4
 54#define TI_TSC2046_ADDR_Z1			3
 55#define TI_TSC2046_ADDR_VBAT			2
 56#define TI_TSC2046_ADDR_Y			1
 57#define TI_TSC2046_ADDR_TEMP0			0
 58
 59/*
 60 * The mode bit sets the resolution of the ADC. With this bit low, the next
 61 * conversion has 12-bit resolution, whereas with this bit high, the next
 62 * conversion has 8-bit resolution. This driver is optimized for 12-bit mode.
 63 * So, for this driver, this bit should stay zero.
 64 */
 65#define TI_TSC2046_8BIT_MODE			BIT(3)
 66
 67/*
 68 * SER/DFR - The SER/DFR bit controls the reference mode, either single-ended
 69 * (high) or differential (low).
 70 */
 71#define TI_TSC2046_SER				BIT(2)
 72
 73/*
 74 * If VREF_ON and ADC_ON are both zero, then the chip operates in
 75 * auto-wake/suspend mode. In most case this bits should stay zero.
 76 */
 77#define TI_TSC2046_PD1_VREF_ON			BIT(1)
 78#define TI_TSC2046_PD0_ADC_ON			BIT(0)
 79
 80/*
 81 * All supported devices can do 8 or 12bit resolution. This driver
 82 * supports only 12bit mode, here we have a 16bit data transfer, where
 83 * the MSB and the 3 LSB are 0.
 84 */
 85#define TI_TSC2046_DATA_12BIT			GENMASK(14, 3)
 86
 87#define TI_TSC2046_MAX_CHAN			8
 88#define TI_TSC2046_MIN_POLL_CNT			3
 89#define TI_TSC2046_EXT_POLL_CNT			3
 90#define TI_TSC2046_POLL_CNT \
 91	(TI_TSC2046_MIN_POLL_CNT + TI_TSC2046_EXT_POLL_CNT)
 92#define TI_TSC2046_INT_VREF			2500
 93
 94/* Represents a HW sample */
 95struct tsc2046_adc_atom {
 96	/*
 97	 * Command transmitted to the controller. This field is empty on the RX
 98	 * buffer.
 99	 */
100	u8 cmd;
101	/*
102	 * Data received from the controller. This field is empty for the TX
103	 * buffer
104	 */
105	__be16 data;
106} __packed;
107
108/* Layout of atomic buffers within big buffer */
109struct tsc2046_adc_group_layout {
110	/* Group offset within the SPI RX buffer */
111	unsigned int offset;
112	/*
113	 * Amount of tsc2046_adc_atom structs within the same command gathered
114	 * within same group.
115	 */
116	unsigned int count;
117	/*
118	 * Settling samples (tsc2046_adc_atom structs) which should be skipped
119	 * before good samples will start.
120	 */
121	unsigned int skip;
122};
123
124struct tsc2046_adc_dcfg {
125	const struct iio_chan_spec *channels;
126	unsigned int num_channels;
127};
128
129struct tsc2046_adc_ch_cfg {
130	unsigned int settling_time_us;
131	unsigned int oversampling_ratio;
132};
133
134enum tsc2046_state {
135	TSC2046_STATE_SHUTDOWN,
136	TSC2046_STATE_STANDBY,
137	TSC2046_STATE_POLL,
138	TSC2046_STATE_POLL_IRQ_DISABLE,
139	TSC2046_STATE_ENABLE_IRQ,
140};
141
142struct tsc2046_adc_priv {
143	struct spi_device *spi;
144	const struct tsc2046_adc_dcfg *dcfg;
145	bool internal_vref;
146
147	struct iio_trigger *trig;
148	struct hrtimer trig_timer;
149	enum tsc2046_state state;
150	int poll_cnt;
151	spinlock_t state_lock;
152
153	struct spi_transfer xfer;
154	struct spi_message msg;
155
156	struct {
157		/* Scan data for each channel */
158		u16 data[TI_TSC2046_MAX_CHAN];
159		/* Timestamp */
160		s64 ts __aligned(8);
161	} scan_buf;
162
163	/*
164	 * Lock to protect the layout and the SPI transfer buffer.
165	 * tsc2046_adc_group_layout can be changed within update_scan_mode(),
166	 * in this case the l[] and tx/rx buffer will be out of sync to each
167	 * other.
168	 */
169	struct mutex slock;
170	struct tsc2046_adc_group_layout l[TI_TSC2046_MAX_CHAN];
171	struct tsc2046_adc_atom *rx;
172	struct tsc2046_adc_atom *tx;
173
174	unsigned int count;
175	unsigned int groups;
176	u32 effective_speed_hz;
177	u32 scan_interval_us;
178	u32 time_per_scan_us;
179	u32 time_per_bit_ns;
180	unsigned int vref_mv;
181
182	struct tsc2046_adc_ch_cfg ch_cfg[TI_TSC2046_MAX_CHAN];
183};
184
185#define TI_TSC2046_V_CHAN(index, bits, name)			\
186{								\
187	.type = IIO_VOLTAGE,					\
188	.indexed = 1,						\
189	.channel = index,					\
190	.info_mask_separate = BIT(IIO_CHAN_INFO_RAW),		\
191	.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE),	\
192	.datasheet_name = "#name",				\
193	.scan_index = index,					\
194	.scan_type = {						\
195		.sign = 'u',					\
196		.realbits = bits,				\
197		.storagebits = 16,				\
198		.endianness = IIO_CPU,				\
199	},							\
200}
201
202#define DECLARE_TI_TSC2046_8_CHANNELS(name, bits) \
203const struct iio_chan_spec name ## _channels[] = { \
204	TI_TSC2046_V_CHAN(0, bits, TEMP0), \
205	TI_TSC2046_V_CHAN(1, bits, Y), \
206	TI_TSC2046_V_CHAN(2, bits, VBAT), \
207	TI_TSC2046_V_CHAN(3, bits, Z1), \
208	TI_TSC2046_V_CHAN(4, bits, Z2), \
209	TI_TSC2046_V_CHAN(5, bits, X), \
210	TI_TSC2046_V_CHAN(6, bits, AUX), \
211	TI_TSC2046_V_CHAN(7, bits, TEMP1), \
212	IIO_CHAN_SOFT_TIMESTAMP(8), \
213}
214
215static DECLARE_TI_TSC2046_8_CHANNELS(tsc2046_adc, 12);
216
217static const struct tsc2046_adc_dcfg tsc2046_adc_dcfg_tsc2046e = {
218	.channels = tsc2046_adc_channels,
219	.num_channels = ARRAY_SIZE(tsc2046_adc_channels),
220};
221
222/*
223 * Convert time to a number of samples which can be transferred within this
224 * time.
225 */
226static unsigned int tsc2046_adc_time_to_count(struct tsc2046_adc_priv *priv,
227					      unsigned long time)
228{
229	unsigned int bit_count, sample_count;
230
231	bit_count = DIV_ROUND_UP(time * NSEC_PER_USEC, priv->time_per_bit_ns);
232	sample_count = DIV_ROUND_UP(bit_count, TI_TSC2046_SAMPLE_BITS);
233
234	dev_dbg(&priv->spi->dev, "Effective speed %u, time per bit: %u, count bits: %u, count samples: %u\n",
235		priv->effective_speed_hz, priv->time_per_bit_ns,
236		bit_count, sample_count);
237
238	return sample_count;
239}
240
241static u8 tsc2046_adc_get_cmd(struct tsc2046_adc_priv *priv, int ch_idx,
242			      bool keep_power)
243{
244	u32 pd;
245
246	/*
247	 * if PD bits are 0, controller will automatically disable ADC, VREF and
248	 * enable IRQ.
249	 */
250	if (keep_power)
251		pd = TI_TSC2046_PD0_ADC_ON;
252	else
253		pd = 0;
254
255	switch (ch_idx) {
256	case TI_TSC2046_ADDR_TEMP1:
257	case TI_TSC2046_ADDR_AUX:
258	case TI_TSC2046_ADDR_VBAT:
259	case TI_TSC2046_ADDR_TEMP0:
260		pd |= TI_TSC2046_SER;
261		if (priv->internal_vref)
262			pd |= TI_TSC2046_PD1_VREF_ON;
263	}
264
265	return TI_TSC2046_START | FIELD_PREP(TI_TSC2046_ADDR, ch_idx) | pd;
266}
267
268static u16 tsc2046_adc_get_value(struct tsc2046_adc_atom *buf)
269{
270	return FIELD_GET(TI_TSC2046_DATA_12BIT, get_unaligned_be16(&buf->data));
271}
272
273static int tsc2046_adc_read_one(struct tsc2046_adc_priv *priv, int ch_idx,
274				u32 *effective_speed_hz)
275{
276	struct tsc2046_adc_ch_cfg *ch = &priv->ch_cfg[ch_idx];
277	unsigned int val, val_normalized = 0;
278	int ret, i, count_skip = 0, max_count;
279	struct spi_transfer xfer;
280	struct spi_message msg;
281	u8 cmd;
282
283	if (!effective_speed_hz) {
284		count_skip = tsc2046_adc_time_to_count(priv, ch->settling_time_us);
285		max_count = count_skip + ch->oversampling_ratio;
286	} else {
287		max_count = 1;
288	}
289
290	if (sizeof(struct tsc2046_adc_atom) * max_count > PAGE_SIZE)
291		return -ENOSPC;
292
293	struct tsc2046_adc_atom *tx_buf __free(kfree) = kcalloc(max_count,
294								sizeof(*tx_buf),
295								GFP_KERNEL);
296	if (!tx_buf)
297		return -ENOMEM;
298
299	struct tsc2046_adc_atom *rx_buf __free(kfree) = kcalloc(max_count,
300								sizeof(*rx_buf),
301								GFP_KERNEL);
302	if (!rx_buf)
303		return -ENOMEM;
304
305	/*
306	 * Do not enable automatic power down on working samples. Otherwise the
307	 * plates will never be completely charged.
308	 */
309	cmd = tsc2046_adc_get_cmd(priv, ch_idx, true);
310
311	for (i = 0; i < max_count - 1; i++)
312		tx_buf[i].cmd = cmd;
313
314	/* automatically power down on last sample */
315	tx_buf[i].cmd = tsc2046_adc_get_cmd(priv, ch_idx, false);
316
317	memset(&xfer, 0, sizeof(xfer));
318	xfer.tx_buf = tx_buf;
319	xfer.rx_buf = rx_buf;
320	xfer.len = sizeof(*tx_buf) * max_count;
321	spi_message_init_with_transfers(&msg, &xfer, 1);
322
323	/*
324	 * We aren't using spi_write_then_read() because we need to be able
325	 * to get hold of the effective_speed_hz from the xfer
326	 */
327	ret = spi_sync(priv->spi, &msg);
328	if (ret) {
329		dev_err_ratelimited(&priv->spi->dev, "SPI transfer failed %pe\n",
330				    ERR_PTR(ret));
331		return ret;
332	}
333
334	if (effective_speed_hz)
335		*effective_speed_hz = xfer.effective_speed_hz;
336
337	for (i = 0; i < max_count - count_skip; i++) {
338		val = tsc2046_adc_get_value(&rx_buf[count_skip + i]);
339		val_normalized += val;
340	}
341
342	return DIV_ROUND_UP(val_normalized, max_count - count_skip);
343}
344
345static size_t tsc2046_adc_group_set_layout(struct tsc2046_adc_priv *priv,
346					   unsigned int group,
347					   unsigned int ch_idx)
348{
349	struct tsc2046_adc_ch_cfg *ch = &priv->ch_cfg[ch_idx];
350	struct tsc2046_adc_group_layout *cur;
351	unsigned int max_count, count_skip;
352	unsigned int offset = 0;
353
354	if (group)
355		offset = priv->l[group - 1].offset + priv->l[group - 1].count;
356
357	count_skip = tsc2046_adc_time_to_count(priv, ch->settling_time_us);
358	max_count = count_skip + ch->oversampling_ratio;
359
360	cur = &priv->l[group];
361	cur->offset = offset;
362	cur->count = max_count;
363	cur->skip = count_skip;
364
365	return sizeof(*priv->tx) * max_count;
366}
367
368static void tsc2046_adc_group_set_cmd(struct tsc2046_adc_priv *priv,
369				      unsigned int group, int ch_idx)
370{
371	struct tsc2046_adc_group_layout *l = &priv->l[group];
372	unsigned int i;
373	u8 cmd;
374
375	/*
376	 * Do not enable automatic power down on working samples. Otherwise the
377	 * plates will never be completely charged.
378	 */
379	cmd = tsc2046_adc_get_cmd(priv, ch_idx, true);
380
381	for (i = 0; i < l->count - 1; i++)
382		priv->tx[l->offset + i].cmd = cmd;
383
384	/* automatically power down on last sample */
385	priv->tx[l->offset + i].cmd = tsc2046_adc_get_cmd(priv, ch_idx, false);
386}
387
388static u16 tsc2046_adc_get_val(struct tsc2046_adc_priv *priv, int group)
389{
390	struct tsc2046_adc_group_layout *l;
391	unsigned int val, val_normalized = 0;
392	int valid_count, i;
393
394	l = &priv->l[group];
395	valid_count = l->count - l->skip;
396
397	for (i = 0; i < valid_count; i++) {
398		val = tsc2046_adc_get_value(&priv->rx[l->offset + l->skip + i]);
399		val_normalized += val;
400	}
401
402	return DIV_ROUND_UP(val_normalized, valid_count);
403}
404
405static int tsc2046_adc_scan(struct iio_dev *indio_dev)
406{
407	struct tsc2046_adc_priv *priv = iio_priv(indio_dev);
408	struct device *dev = &priv->spi->dev;
409	int group;
410	int ret;
411
412	ret = spi_sync(priv->spi, &priv->msg);
413	if (ret < 0) {
414		dev_err_ratelimited(dev, "SPI transfer failed: %pe\n", ERR_PTR(ret));
415		return ret;
416	}
417
418	for (group = 0; group < priv->groups; group++)
419		priv->scan_buf.data[group] = tsc2046_adc_get_val(priv, group);
420
421	ret = iio_push_to_buffers_with_timestamp(indio_dev, &priv->scan_buf,
422						 iio_get_time_ns(indio_dev));
423	/* If the consumer is kfifo, we may get a EBUSY here - ignore it. */
424	if (ret < 0 && ret != -EBUSY) {
425		dev_err_ratelimited(dev, "Failed to push scan buffer %pe\n",
426				    ERR_PTR(ret));
427
428		return ret;
429	}
430
431	return 0;
432}
433
434static irqreturn_t tsc2046_adc_trigger_handler(int irq, void *p)
435{
436	struct iio_poll_func *pf = p;
437	struct iio_dev *indio_dev = pf->indio_dev;
438	struct tsc2046_adc_priv *priv = iio_priv(indio_dev);
439
440	mutex_lock(&priv->slock);
441	tsc2046_adc_scan(indio_dev);
442	mutex_unlock(&priv->slock);
443
444	iio_trigger_notify_done(indio_dev->trig);
445
446	return IRQ_HANDLED;
447}
448
449static int tsc2046_adc_read_raw(struct iio_dev *indio_dev,
450				struct iio_chan_spec const *chan,
451				int *val, int *val2, long m)
452{
453	struct tsc2046_adc_priv *priv = iio_priv(indio_dev);
454	int ret;
455
456	switch (m) {
457	case IIO_CHAN_INFO_RAW:
458		ret = tsc2046_adc_read_one(priv, chan->channel, NULL);
459		if (ret < 0)
460			return ret;
461
462		*val = ret;
463
464		return IIO_VAL_INT;
465	case IIO_CHAN_INFO_SCALE:
466		/*
467		 * Note: the TSC2046 has internal voltage divider on the VBAT
468		 * line. This divider can be influenced by external divider.
469		 * So, it is better to use external voltage-divider driver
470		 * instead, which is calculating complete chain.
471		 */
472		*val = priv->vref_mv;
473		*val2 = chan->scan_type.realbits;
474		return IIO_VAL_FRACTIONAL_LOG2;
475	}
476
477	return -EINVAL;
478}
479
480static int tsc2046_adc_update_scan_mode(struct iio_dev *indio_dev,
481					const unsigned long *active_scan_mask)
482{
483	struct tsc2046_adc_priv *priv = iio_priv(indio_dev);
484	unsigned int ch_idx, group = 0;
485	size_t size;
486
487	mutex_lock(&priv->slock);
488
489	size = 0;
490	for_each_set_bit(ch_idx, active_scan_mask, ARRAY_SIZE(priv->l)) {
491		size += tsc2046_adc_group_set_layout(priv, group, ch_idx);
492		tsc2046_adc_group_set_cmd(priv, group, ch_idx);
493		group++;
494	}
495
496	priv->groups = group;
497	priv->xfer.len = size;
498	priv->time_per_scan_us = size * 8 * priv->time_per_bit_ns / NSEC_PER_USEC;
499
500	if (priv->scan_interval_us < priv->time_per_scan_us)
501		dev_warn(&priv->spi->dev, "The scan interval (%d) is less then calculated scan time (%d)\n",
502			 priv->scan_interval_us, priv->time_per_scan_us);
503
504	mutex_unlock(&priv->slock);
505
506	return 0;
507}
508
509static const struct iio_info tsc2046_adc_info = {
510	.read_raw	  = tsc2046_adc_read_raw,
511	.update_scan_mode = tsc2046_adc_update_scan_mode,
512};
513
514static enum hrtimer_restart tsc2046_adc_timer(struct hrtimer *hrtimer)
515{
516	struct tsc2046_adc_priv *priv = container_of(hrtimer,
517						     struct tsc2046_adc_priv,
518						     trig_timer);
519	unsigned long flags;
520
521	/*
522	 * This state machine should address following challenges :
523	 * - the interrupt source is based on level shifter attached to the X
524	 *   channel of ADC. It will change the state every time we switch
525	 *   between channels. So, we need to disable IRQ if we do
526	 *   iio_trigger_poll().
527	 * - we should do iio_trigger_poll() at some reduced sample rate
528	 * - we should still trigger for some amount of time after last
529	 *   interrupt with enabled IRQ was processed.
530	 */
531
532	spin_lock_irqsave(&priv->state_lock, flags);
533	switch (priv->state) {
534	case TSC2046_STATE_ENABLE_IRQ:
535		if (priv->poll_cnt < TI_TSC2046_POLL_CNT) {
536			priv->poll_cnt++;
537			hrtimer_start(&priv->trig_timer,
538				      ns_to_ktime(priv->scan_interval_us *
539						  NSEC_PER_USEC),
540				      HRTIMER_MODE_REL_SOFT);
541
542			if (priv->poll_cnt >= TI_TSC2046_MIN_POLL_CNT) {
543				priv->state = TSC2046_STATE_POLL_IRQ_DISABLE;
544				enable_irq(priv->spi->irq);
545			} else {
546				priv->state = TSC2046_STATE_POLL;
547			}
548		} else {
549			priv->state = TSC2046_STATE_STANDBY;
550			enable_irq(priv->spi->irq);
551		}
552		break;
553	case TSC2046_STATE_POLL_IRQ_DISABLE:
554		disable_irq_nosync(priv->spi->irq);
555		fallthrough;
556	case TSC2046_STATE_POLL:
557		priv->state = TSC2046_STATE_ENABLE_IRQ;
558		/* iio_trigger_poll() starts hrtimer */
559		iio_trigger_poll(priv->trig);
560		break;
561	case TSC2046_STATE_SHUTDOWN:
562		break;
563	case TSC2046_STATE_STANDBY:
564		fallthrough;
565	default:
566		dev_warn(&priv->spi->dev, "Got unexpected state: %i\n",
567			 priv->state);
568		break;
569	}
570	spin_unlock_irqrestore(&priv->state_lock, flags);
571
572	return HRTIMER_NORESTART;
573}
574
575static irqreturn_t tsc2046_adc_irq(int irq, void *dev_id)
576{
577	struct iio_dev *indio_dev = dev_id;
578	struct tsc2046_adc_priv *priv = iio_priv(indio_dev);
579	unsigned long flags;
580
581	hrtimer_try_to_cancel(&priv->trig_timer);
582
583	spin_lock_irqsave(&priv->state_lock, flags);
584	if (priv->state != TSC2046_STATE_SHUTDOWN) {
585		priv->state = TSC2046_STATE_ENABLE_IRQ;
586		priv->poll_cnt = 0;
587
588		/* iio_trigger_poll() starts hrtimer */
589		disable_irq_nosync(priv->spi->irq);
590		iio_trigger_poll(priv->trig);
591	}
592	spin_unlock_irqrestore(&priv->state_lock, flags);
593
594	return IRQ_HANDLED;
595}
596
597static void tsc2046_adc_reenable_trigger(struct iio_trigger *trig)
598{
599	struct iio_dev *indio_dev = iio_trigger_get_drvdata(trig);
600	struct tsc2046_adc_priv *priv = iio_priv(indio_dev);
601	ktime_t tim;
602
603	/*
604	 * We can sample it as fast as we can, but usually we do not need so
605	 * many samples. Reduce the sample rate for default (touchscreen) use
606	 * case.
607	 */
608	tim = ns_to_ktime((priv->scan_interval_us - priv->time_per_scan_us) *
609			  NSEC_PER_USEC);
610	hrtimer_start(&priv->trig_timer, tim, HRTIMER_MODE_REL_SOFT);
611}
612
613static int tsc2046_adc_set_trigger_state(struct iio_trigger *trig, bool enable)
614{
615	struct iio_dev *indio_dev = iio_trigger_get_drvdata(trig);
616	struct tsc2046_adc_priv *priv = iio_priv(indio_dev);
617	unsigned long flags;
618
619	if (enable) {
620		spin_lock_irqsave(&priv->state_lock, flags);
621		if (priv->state == TSC2046_STATE_SHUTDOWN) {
622			priv->state = TSC2046_STATE_STANDBY;
623			enable_irq(priv->spi->irq);
624		}
625		spin_unlock_irqrestore(&priv->state_lock, flags);
626	} else {
627		spin_lock_irqsave(&priv->state_lock, flags);
628
629		if (priv->state == TSC2046_STATE_STANDBY ||
630		    priv->state == TSC2046_STATE_POLL_IRQ_DISABLE)
631			disable_irq_nosync(priv->spi->irq);
632
633		priv->state = TSC2046_STATE_SHUTDOWN;
634		spin_unlock_irqrestore(&priv->state_lock, flags);
635
636		hrtimer_cancel(&priv->trig_timer);
637	}
638
639	return 0;
640}
641
642static const struct iio_trigger_ops tsc2046_adc_trigger_ops = {
643	.set_trigger_state = tsc2046_adc_set_trigger_state,
644	.reenable = tsc2046_adc_reenable_trigger,
645};
646
647static int tsc2046_adc_setup_spi_msg(struct tsc2046_adc_priv *priv)
648{
649	unsigned int ch_idx;
650	size_t size;
651	int ret;
652
653	/*
654	 * Make dummy read to set initial power state and get real SPI clock
655	 * freq. It seems to be not important which channel is used for this
656	 * case.
657	 */
658	ret = tsc2046_adc_read_one(priv, TI_TSC2046_ADDR_TEMP0,
659				   &priv->effective_speed_hz);
660	if (ret < 0)
661		return ret;
662
663	/*
664	 * In case SPI controller do not report effective_speed_hz, use
665	 * configure value and hope it will match.
666	 */
667	if (!priv->effective_speed_hz)
668		priv->effective_speed_hz = priv->spi->max_speed_hz;
669
670
671	priv->scan_interval_us = TI_TSC2046_SAMPLE_INTERVAL_US;
672	priv->time_per_bit_ns = DIV_ROUND_UP(NSEC_PER_SEC,
673					     priv->effective_speed_hz);
674
675	/*
676	 * Calculate and allocate maximal size buffer if all channels are
677	 * enabled.
678	 */
679	size = 0;
680	for (ch_idx = 0; ch_idx < ARRAY_SIZE(priv->l); ch_idx++)
681		size += tsc2046_adc_group_set_layout(priv, ch_idx, ch_idx);
682
683	if (size > PAGE_SIZE) {
684		dev_err(&priv->spi->dev,
685			"Calculated scan buffer is too big. Try to reduce spi-max-frequency, settling-time-us or oversampling-ratio\n");
686		return -ENOSPC;
687	}
688
689	priv->tx = devm_kzalloc(&priv->spi->dev, size, GFP_KERNEL);
690	if (!priv->tx)
691		return -ENOMEM;
692
693	priv->rx = devm_kzalloc(&priv->spi->dev, size, GFP_KERNEL);
694	if (!priv->rx)
695		return -ENOMEM;
696
697	priv->xfer.tx_buf = priv->tx;
698	priv->xfer.rx_buf = priv->rx;
699	priv->xfer.len = size;
700	spi_message_init_with_transfers(&priv->msg, &priv->xfer, 1);
701
702	return 0;
703}
704
705static void tsc2046_adc_parse_fwnode(struct tsc2046_adc_priv *priv)
706{
707	struct fwnode_handle *child;
708	struct device *dev = &priv->spi->dev;
709	unsigned int i;
710
711	for (i = 0; i < ARRAY_SIZE(priv->ch_cfg); i++) {
712		priv->ch_cfg[i].settling_time_us = 1;
713		priv->ch_cfg[i].oversampling_ratio = 1;
714	}
715
716	device_for_each_child_node(dev, child) {
717		u32 stl, overs, reg;
718		int ret;
719
720		ret = fwnode_property_read_u32(child, "reg", &reg);
721		if (ret) {
722			dev_err(dev, "invalid reg on %pfw, err: %pe\n", child,
723				ERR_PTR(ret));
724			continue;
725		}
726
727		if (reg >= ARRAY_SIZE(priv->ch_cfg)) {
728			dev_err(dev, "%pfw: Unsupported reg value: %i, max supported is: %zu.\n",
729				child, reg, ARRAY_SIZE(priv->ch_cfg));
730			continue;
731		}
732
733		ret = fwnode_property_read_u32(child, "settling-time-us", &stl);
734		if (!ret)
735			priv->ch_cfg[reg].settling_time_us = stl;
736
737		ret = fwnode_property_read_u32(child, "oversampling-ratio",
738					       &overs);
739		if (!ret)
740			priv->ch_cfg[reg].oversampling_ratio = overs;
741	}
742}
743
744static int tsc2046_adc_probe(struct spi_device *spi)
745{
746	const struct tsc2046_adc_dcfg *dcfg;
747	struct device *dev = &spi->dev;
748	struct tsc2046_adc_priv *priv;
749	struct iio_dev *indio_dev;
750	struct iio_trigger *trig;
751	int ret;
752
753	if (spi->max_speed_hz > TI_TSC2046_MAX_CLK_FREQ) {
754		dev_err(dev, "SPI max_speed_hz is too high: %d Hz. Max supported freq is %zu Hz\n",
755			spi->max_speed_hz, TI_TSC2046_MAX_CLK_FREQ);
756		return -EINVAL;
757	}
758
759	dcfg = spi_get_device_match_data(spi);
760	if (!dcfg)
761		return -EINVAL;
762
763	spi->bits_per_word = 8;
764	spi->mode &= ~SPI_MODE_X_MASK;
765	spi->mode |= SPI_MODE_0;
766	ret = spi_setup(spi);
767	if (ret < 0)
768		return dev_err_probe(dev, ret, "Error in SPI setup\n");
769
770	indio_dev = devm_iio_device_alloc(dev, sizeof(*priv));
771	if (!indio_dev)
772		return -ENOMEM;
773
774	priv = iio_priv(indio_dev);
775	priv->dcfg = dcfg;
776
777	priv->spi = spi;
778
779	indio_dev->name = TI_TSC2046_NAME;
780	indio_dev->modes = INDIO_DIRECT_MODE;
781	indio_dev->channels = dcfg->channels;
782	indio_dev->num_channels = dcfg->num_channels;
783	indio_dev->info = &tsc2046_adc_info;
784
785	ret = devm_regulator_get_enable_read_voltage(dev, "vref");
786	if (ret < 0 && ret != -ENODEV)
787		return ret;
788
789	priv->internal_vref = ret == -ENODEV;
790	priv->vref_mv = priv->internal_vref ? TI_TSC2046_INT_VREF : ret / MILLI;
791
792	tsc2046_adc_parse_fwnode(priv);
793
794	ret = tsc2046_adc_setup_spi_msg(priv);
795	if (ret)
796		return ret;
797
798	mutex_init(&priv->slock);
799
800	ret = devm_request_irq(dev, spi->irq, &tsc2046_adc_irq,
801			       IRQF_NO_AUTOEN, indio_dev->name, indio_dev);
802	if (ret)
803		return ret;
804
805	trig = devm_iio_trigger_alloc(dev, "touchscreen-%s", indio_dev->name);
806	if (!trig)
807		return -ENOMEM;
808
809	priv->trig = trig;
810	iio_trigger_set_drvdata(trig, indio_dev);
811	trig->ops = &tsc2046_adc_trigger_ops;
812
813	spin_lock_init(&priv->state_lock);
814	priv->state = TSC2046_STATE_SHUTDOWN;
815	hrtimer_init(&priv->trig_timer, CLOCK_MONOTONIC,
816		     HRTIMER_MODE_REL_SOFT);
817	priv->trig_timer.function = tsc2046_adc_timer;
818
819	ret = devm_iio_trigger_register(dev, trig);
820	if (ret) {
821		dev_err(dev, "failed to register trigger\n");
822		return ret;
823	}
824
825	ret = devm_iio_triggered_buffer_setup(dev, indio_dev, NULL,
826					      &tsc2046_adc_trigger_handler, NULL);
827	if (ret) {
828		dev_err(dev, "Failed to setup triggered buffer\n");
829		return ret;
830	}
831
832	/* set default trigger */
833	indio_dev->trig = iio_trigger_get(priv->trig);
834
835	return devm_iio_device_register(dev, indio_dev);
836}
837
838static const struct of_device_id ads7950_of_table[] = {
839	{ .compatible = "ti,tsc2046e-adc", .data = &tsc2046_adc_dcfg_tsc2046e },
840	{ }
841};
842MODULE_DEVICE_TABLE(of, ads7950_of_table);
843
844static const struct spi_device_id tsc2046_adc_spi_ids[] = {
845	{ "tsc2046e-adc", (unsigned long)&tsc2046_adc_dcfg_tsc2046e },
846	{ }
847};
848MODULE_DEVICE_TABLE(spi, tsc2046_adc_spi_ids);
849
850static struct spi_driver tsc2046_adc_driver = {
851	.driver = {
852		.name = "tsc2046",
853		.of_match_table = ads7950_of_table,
854	},
855	.id_table = tsc2046_adc_spi_ids,
856	.probe = tsc2046_adc_probe,
857};
858module_spi_driver(tsc2046_adc_driver);
859
860MODULE_AUTHOR("Oleksij Rempel <kernel@pengutronix.de>");
861MODULE_DESCRIPTION("TI TSC2046 ADC");
862MODULE_LICENSE("GPL v2");