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1/*
2 * Copyright 2015 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22
23#ifndef __AMD_SHARED_H__
24#define __AMD_SHARED_H__
25
26#include <drm/amd_asic_type.h>
27
28
29#define AMD_MAX_USEC_TIMEOUT 1000000 /* 1000 ms */
30
31/*
32 * Chip flags
33 */
34enum amd_chip_flags {
35 AMD_ASIC_MASK = 0x0000ffffUL,
36 AMD_FLAGS_MASK = 0xffff0000UL,
37 AMD_IS_MOBILITY = 0x00010000UL,
38 AMD_IS_APU = 0x00020000UL,
39 AMD_IS_PX = 0x00040000UL,
40 AMD_EXP_HW_SUPPORT = 0x00080000UL,
41};
42
43enum amd_apu_flags {
44 AMD_APU_IS_RAVEN = 0x00000001UL,
45 AMD_APU_IS_RAVEN2 = 0x00000002UL,
46 AMD_APU_IS_PICASSO = 0x00000004UL,
47 AMD_APU_IS_RENOIR = 0x00000008UL,
48};
49
50enum amd_ip_block_type {
51 AMD_IP_BLOCK_TYPE_COMMON,
52 AMD_IP_BLOCK_TYPE_GMC,
53 AMD_IP_BLOCK_TYPE_IH,
54 AMD_IP_BLOCK_TYPE_SMC,
55 AMD_IP_BLOCK_TYPE_PSP,
56 AMD_IP_BLOCK_TYPE_DCE,
57 AMD_IP_BLOCK_TYPE_GFX,
58 AMD_IP_BLOCK_TYPE_SDMA,
59 AMD_IP_BLOCK_TYPE_UVD,
60 AMD_IP_BLOCK_TYPE_VCE,
61 AMD_IP_BLOCK_TYPE_ACP,
62 AMD_IP_BLOCK_TYPE_VCN,
63 AMD_IP_BLOCK_TYPE_MES,
64 AMD_IP_BLOCK_TYPE_JPEG
65};
66
67enum amd_clockgating_state {
68 AMD_CG_STATE_GATE = 0,
69 AMD_CG_STATE_UNGATE,
70};
71
72
73enum amd_powergating_state {
74 AMD_PG_STATE_GATE = 0,
75 AMD_PG_STATE_UNGATE,
76};
77
78
79/* CG flags */
80#define AMD_CG_SUPPORT_GFX_MGCG (1 << 0)
81#define AMD_CG_SUPPORT_GFX_MGLS (1 << 1)
82#define AMD_CG_SUPPORT_GFX_CGCG (1 << 2)
83#define AMD_CG_SUPPORT_GFX_CGLS (1 << 3)
84#define AMD_CG_SUPPORT_GFX_CGTS (1 << 4)
85#define AMD_CG_SUPPORT_GFX_CGTS_LS (1 << 5)
86#define AMD_CG_SUPPORT_GFX_CP_LS (1 << 6)
87#define AMD_CG_SUPPORT_GFX_RLC_LS (1 << 7)
88#define AMD_CG_SUPPORT_MC_LS (1 << 8)
89#define AMD_CG_SUPPORT_MC_MGCG (1 << 9)
90#define AMD_CG_SUPPORT_SDMA_LS (1 << 10)
91#define AMD_CG_SUPPORT_SDMA_MGCG (1 << 11)
92#define AMD_CG_SUPPORT_BIF_LS (1 << 12)
93#define AMD_CG_SUPPORT_UVD_MGCG (1 << 13)
94#define AMD_CG_SUPPORT_VCE_MGCG (1 << 14)
95#define AMD_CG_SUPPORT_HDP_LS (1 << 15)
96#define AMD_CG_SUPPORT_HDP_MGCG (1 << 16)
97#define AMD_CG_SUPPORT_ROM_MGCG (1 << 17)
98#define AMD_CG_SUPPORT_DRM_LS (1 << 18)
99#define AMD_CG_SUPPORT_BIF_MGCG (1 << 19)
100#define AMD_CG_SUPPORT_GFX_3D_CGCG (1 << 20)
101#define AMD_CG_SUPPORT_GFX_3D_CGLS (1 << 21)
102#define AMD_CG_SUPPORT_DRM_MGCG (1 << 22)
103#define AMD_CG_SUPPORT_DF_MGCG (1 << 23)
104#define AMD_CG_SUPPORT_VCN_MGCG (1 << 24)
105#define AMD_CG_SUPPORT_HDP_DS (1 << 25)
106#define AMD_CG_SUPPORT_HDP_SD (1 << 26)
107#define AMD_CG_SUPPORT_IH_CG (1 << 27)
108#define AMD_CG_SUPPORT_ATHUB_LS (1 << 28)
109#define AMD_CG_SUPPORT_ATHUB_MGCG (1 << 29)
110#define AMD_CG_SUPPORT_JPEG_MGCG (1 << 30)
111/* PG flags */
112#define AMD_PG_SUPPORT_GFX_PG (1 << 0)
113#define AMD_PG_SUPPORT_GFX_SMG (1 << 1)
114#define AMD_PG_SUPPORT_GFX_DMG (1 << 2)
115#define AMD_PG_SUPPORT_UVD (1 << 3)
116#define AMD_PG_SUPPORT_VCE (1 << 4)
117#define AMD_PG_SUPPORT_CP (1 << 5)
118#define AMD_PG_SUPPORT_GDS (1 << 6)
119#define AMD_PG_SUPPORT_RLC_SMU_HS (1 << 7)
120#define AMD_PG_SUPPORT_SDMA (1 << 8)
121#define AMD_PG_SUPPORT_ACP (1 << 9)
122#define AMD_PG_SUPPORT_SAMU (1 << 10)
123#define AMD_PG_SUPPORT_GFX_QUICK_MG (1 << 11)
124#define AMD_PG_SUPPORT_GFX_PIPELINE (1 << 12)
125#define AMD_PG_SUPPORT_MMHUB (1 << 13)
126#define AMD_PG_SUPPORT_VCN (1 << 14)
127#define AMD_PG_SUPPORT_VCN_DPG (1 << 15)
128#define AMD_PG_SUPPORT_ATHUB (1 << 16)
129#define AMD_PG_SUPPORT_JPEG (1 << 17)
130
131enum PP_FEATURE_MASK {
132 PP_SCLK_DPM_MASK = 0x1,
133 PP_MCLK_DPM_MASK = 0x2,
134 PP_PCIE_DPM_MASK = 0x4,
135 PP_SCLK_DEEP_SLEEP_MASK = 0x8,
136 PP_POWER_CONTAINMENT_MASK = 0x10,
137 PP_UVD_HANDSHAKE_MASK = 0x20,
138 PP_SMC_VOLTAGE_CONTROL_MASK = 0x40,
139 PP_VBI_TIME_SUPPORT_MASK = 0x80,
140 PP_ULV_MASK = 0x100,
141 PP_ENABLE_GFX_CG_THRU_SMU = 0x200,
142 PP_CLOCK_STRETCH_MASK = 0x400,
143 PP_OD_FUZZY_FAN_CONTROL_MASK = 0x800,
144 PP_SOCCLK_DPM_MASK = 0x1000,
145 PP_DCEFCLK_DPM_MASK = 0x2000,
146 PP_OVERDRIVE_MASK = 0x4000,
147 PP_GFXOFF_MASK = 0x8000,
148 PP_ACG_MASK = 0x10000,
149 PP_STUTTER_MODE = 0x20000,
150 PP_AVFS_MASK = 0x40000,
151};
152
153enum DC_FEATURE_MASK {
154 DC_FBC_MASK = 0x1,
155 DC_MULTI_MON_PP_MCLK_SWITCH_MASK = 0x2,
156 DC_DISABLE_FRACTIONAL_PWM_MASK = 0x4,
157 DC_PSR_MASK = 0x8,
158};
159
160enum DC_DEBUG_MASK {
161 DC_DISABLE_PIPE_SPLIT = 0x1,
162 DC_DISABLE_STUTTER = 0x2,
163 DC_DISABLE_DSC = 0x4,
164 DC_DISABLE_CLOCK_GATING = 0x8
165};
166
167enum amd_dpm_forced_level;
168/**
169 * struct amd_ip_funcs - general hooks for managing amdgpu IP Blocks
170 */
171struct amd_ip_funcs {
172 /** @name: Name of IP block */
173 char *name;
174 /**
175 * @early_init:
176 *
177 * sets up early driver state (pre sw_init),
178 * does not configure hw - Optional
179 */
180 int (*early_init)(void *handle);
181 /** @late_init: sets up late driver/hw state (post hw_init) - Optional */
182 int (*late_init)(void *handle);
183 /** @sw_init: sets up driver state, does not configure hw */
184 int (*sw_init)(void *handle);
185 /** @sw_fini: tears down driver state, does not configure hw */
186 int (*sw_fini)(void *handle);
187 /** @hw_init: sets up the hw state */
188 int (*hw_init)(void *handle);
189 /** @hw_fini: tears down the hw state */
190 int (*hw_fini)(void *handle);
191 /** @late_fini: final cleanup */
192 void (*late_fini)(void *handle);
193 /** @suspend: handles IP specific hw/sw changes for suspend */
194 int (*suspend)(void *handle);
195 /** @resume: handles IP specific hw/sw changes for resume */
196 int (*resume)(void *handle);
197 /** @is_idle: returns current IP block idle status */
198 bool (*is_idle)(void *handle);
199 /** @wait_for_idle: poll for idle */
200 int (*wait_for_idle)(void *handle);
201 /** @check_soft_reset: check soft reset the IP block */
202 bool (*check_soft_reset)(void *handle);
203 /** @pre_soft_reset: pre soft reset the IP block */
204 int (*pre_soft_reset)(void *handle);
205 /** @soft_reset: soft reset the IP block */
206 int (*soft_reset)(void *handle);
207 /** @post_soft_reset: post soft reset the IP block */
208 int (*post_soft_reset)(void *handle);
209 /** @set_clockgating_state: enable/disable cg for the IP block */
210 int (*set_clockgating_state)(void *handle,
211 enum amd_clockgating_state state);
212 /** @set_powergating_state: enable/disable pg for the IP block */
213 int (*set_powergating_state)(void *handle,
214 enum amd_powergating_state state);
215 /** @get_clockgating_state: get current clockgating status */
216 void (*get_clockgating_state)(void *handle, u32 *flags);
217 /** @enable_umd_pstate: enable UMD powerstate */
218 int (*enable_umd_pstate)(void *handle, enum amd_dpm_forced_level *level);
219};
220
221
222#endif /* __AMD_SHARED_H__ */
1/*
2 * Copyright 2015 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22
23#ifndef __AMD_SHARED_H__
24#define __AMD_SHARED_H__
25
26#include <drm/amd_asic_type.h>
27#include <drm/drm_print.h>
28
29
30#define AMD_MAX_USEC_TIMEOUT 1000000 /* 1000 ms */
31struct amdgpu_ip_block;
32
33
34/*
35 * Chip flags
36 */
37enum amd_chip_flags {
38 AMD_ASIC_MASK = 0x0000ffffUL,
39 AMD_FLAGS_MASK = 0xffff0000UL,
40 AMD_IS_MOBILITY = 0x00010000UL,
41 AMD_IS_APU = 0x00020000UL,
42 AMD_IS_PX = 0x00040000UL,
43 AMD_EXP_HW_SUPPORT = 0x00080000UL,
44};
45
46enum amd_apu_flags {
47 AMD_APU_IS_RAVEN = 0x00000001UL,
48 AMD_APU_IS_RAVEN2 = 0x00000002UL,
49 AMD_APU_IS_PICASSO = 0x00000004UL,
50 AMD_APU_IS_RENOIR = 0x00000008UL,
51 AMD_APU_IS_GREEN_SARDINE = 0x00000010UL,
52 AMD_APU_IS_VANGOGH = 0x00000020UL,
53 AMD_APU_IS_CYAN_SKILLFISH2 = 0x00000040UL,
54};
55
56/**
57* DOC: IP Blocks
58*
59* GPUs are composed of IP (intellectual property) blocks. These
60* IP blocks provide various functionalities: display, graphics,
61* video decode, etc. The IP blocks that comprise a particular GPU
62* are listed in the GPU's respective SoC file. amdgpu_device.c
63* acquires the list of IP blocks for the GPU in use on initialization.
64* It can then operate on this list to perform standard driver operations
65* such as: init, fini, suspend, resume, etc.
66*
67*
68* IP block implementations are named using the following convention:
69* <functionality>_v<version> (E.g.: gfx_v6_0).
70*/
71
72/**
73* enum amd_ip_block_type - Used to classify IP blocks by functionality.
74*
75* @AMD_IP_BLOCK_TYPE_COMMON: GPU Family
76* @AMD_IP_BLOCK_TYPE_GMC: Graphics Memory Controller
77* @AMD_IP_BLOCK_TYPE_IH: Interrupt Handler
78* @AMD_IP_BLOCK_TYPE_SMC: System Management Controller
79* @AMD_IP_BLOCK_TYPE_PSP: Platform Security Processor
80* @AMD_IP_BLOCK_TYPE_DCE: Display and Compositing Engine
81* @AMD_IP_BLOCK_TYPE_GFX: Graphics and Compute Engine
82* @AMD_IP_BLOCK_TYPE_SDMA: System DMA Engine
83* @AMD_IP_BLOCK_TYPE_UVD: Unified Video Decoder
84* @AMD_IP_BLOCK_TYPE_VCE: Video Compression Engine
85* @AMD_IP_BLOCK_TYPE_ACP: Audio Co-Processor
86* @AMD_IP_BLOCK_TYPE_VCN: Video Core/Codec Next
87* @AMD_IP_BLOCK_TYPE_MES: Micro-Engine Scheduler
88* @AMD_IP_BLOCK_TYPE_JPEG: JPEG Engine
89* @AMD_IP_BLOCK_TYPE_VPE: Video Processing Engine
90* @AMD_IP_BLOCK_TYPE_UMSCH_MM: User Mode Scheduler for Multimedia
91* @AMD_IP_BLOCK_TYPE_ISP: Image Signal Processor
92* @AMD_IP_BLOCK_TYPE_NUM: Total number of IP block types
93*/
94enum amd_ip_block_type {
95 AMD_IP_BLOCK_TYPE_COMMON,
96 AMD_IP_BLOCK_TYPE_GMC,
97 AMD_IP_BLOCK_TYPE_IH,
98 AMD_IP_BLOCK_TYPE_SMC,
99 AMD_IP_BLOCK_TYPE_PSP,
100 AMD_IP_BLOCK_TYPE_DCE,
101 AMD_IP_BLOCK_TYPE_GFX,
102 AMD_IP_BLOCK_TYPE_SDMA,
103 AMD_IP_BLOCK_TYPE_UVD,
104 AMD_IP_BLOCK_TYPE_VCE,
105 AMD_IP_BLOCK_TYPE_ACP,
106 AMD_IP_BLOCK_TYPE_VCN,
107 AMD_IP_BLOCK_TYPE_MES,
108 AMD_IP_BLOCK_TYPE_JPEG,
109 AMD_IP_BLOCK_TYPE_VPE,
110 AMD_IP_BLOCK_TYPE_UMSCH_MM,
111 AMD_IP_BLOCK_TYPE_ISP,
112 AMD_IP_BLOCK_TYPE_NUM,
113};
114
115enum amd_clockgating_state {
116 AMD_CG_STATE_GATE = 0,
117 AMD_CG_STATE_UNGATE,
118};
119
120
121enum amd_powergating_state {
122 AMD_PG_STATE_GATE = 0,
123 AMD_PG_STATE_UNGATE,
124};
125
126
127/* CG flags */
128#define AMD_CG_SUPPORT_GFX_MGCG (1ULL << 0)
129#define AMD_CG_SUPPORT_GFX_MGLS (1ULL << 1)
130#define AMD_CG_SUPPORT_GFX_CGCG (1ULL << 2)
131#define AMD_CG_SUPPORT_GFX_CGLS (1ULL << 3)
132#define AMD_CG_SUPPORT_GFX_CGTS (1ULL << 4)
133#define AMD_CG_SUPPORT_GFX_CGTS_LS (1ULL << 5)
134#define AMD_CG_SUPPORT_GFX_CP_LS (1ULL << 6)
135#define AMD_CG_SUPPORT_GFX_RLC_LS (1ULL << 7)
136#define AMD_CG_SUPPORT_MC_LS (1ULL << 8)
137#define AMD_CG_SUPPORT_MC_MGCG (1ULL << 9)
138#define AMD_CG_SUPPORT_SDMA_LS (1ULL << 10)
139#define AMD_CG_SUPPORT_SDMA_MGCG (1ULL << 11)
140#define AMD_CG_SUPPORT_BIF_LS (1ULL << 12)
141#define AMD_CG_SUPPORT_UVD_MGCG (1ULL << 13)
142#define AMD_CG_SUPPORT_VCE_MGCG (1ULL << 14)
143#define AMD_CG_SUPPORT_HDP_LS (1ULL << 15)
144#define AMD_CG_SUPPORT_HDP_MGCG (1ULL << 16)
145#define AMD_CG_SUPPORT_ROM_MGCG (1ULL << 17)
146#define AMD_CG_SUPPORT_DRM_LS (1ULL << 18)
147#define AMD_CG_SUPPORT_BIF_MGCG (1ULL << 19)
148#define AMD_CG_SUPPORT_GFX_3D_CGCG (1ULL << 20)
149#define AMD_CG_SUPPORT_GFX_3D_CGLS (1ULL << 21)
150#define AMD_CG_SUPPORT_DRM_MGCG (1ULL << 22)
151#define AMD_CG_SUPPORT_DF_MGCG (1ULL << 23)
152#define AMD_CG_SUPPORT_VCN_MGCG (1ULL << 24)
153#define AMD_CG_SUPPORT_HDP_DS (1ULL << 25)
154#define AMD_CG_SUPPORT_HDP_SD (1ULL << 26)
155#define AMD_CG_SUPPORT_IH_CG (1ULL << 27)
156#define AMD_CG_SUPPORT_ATHUB_LS (1ULL << 28)
157#define AMD_CG_SUPPORT_ATHUB_MGCG (1ULL << 29)
158#define AMD_CG_SUPPORT_JPEG_MGCG (1ULL << 30)
159#define AMD_CG_SUPPORT_GFX_FGCG (1ULL << 31)
160#define AMD_CG_SUPPORT_REPEATER_FGCG (1ULL << 32)
161#define AMD_CG_SUPPORT_GFX_PERF_CLK (1ULL << 33)
162/* PG flags */
163#define AMD_PG_SUPPORT_GFX_PG (1 << 0)
164#define AMD_PG_SUPPORT_GFX_SMG (1 << 1)
165#define AMD_PG_SUPPORT_GFX_DMG (1 << 2)
166#define AMD_PG_SUPPORT_UVD (1 << 3)
167#define AMD_PG_SUPPORT_VCE (1 << 4)
168#define AMD_PG_SUPPORT_CP (1 << 5)
169#define AMD_PG_SUPPORT_GDS (1 << 6)
170#define AMD_PG_SUPPORT_RLC_SMU_HS (1 << 7)
171#define AMD_PG_SUPPORT_SDMA (1 << 8)
172#define AMD_PG_SUPPORT_ACP (1 << 9)
173#define AMD_PG_SUPPORT_SAMU (1 << 10)
174#define AMD_PG_SUPPORT_GFX_QUICK_MG (1 << 11)
175#define AMD_PG_SUPPORT_GFX_PIPELINE (1 << 12)
176#define AMD_PG_SUPPORT_MMHUB (1 << 13)
177#define AMD_PG_SUPPORT_VCN (1 << 14)
178#define AMD_PG_SUPPORT_VCN_DPG (1 << 15)
179#define AMD_PG_SUPPORT_ATHUB (1 << 16)
180#define AMD_PG_SUPPORT_JPEG (1 << 17)
181#define AMD_PG_SUPPORT_IH_SRAM_PG (1 << 18)
182#define AMD_PG_SUPPORT_JPEG_DPG (1 << 19)
183
184/**
185 * enum PP_FEATURE_MASK - Used to mask power play features.
186 *
187 * @PP_SCLK_DPM_MASK: Dynamic adjustment of the system (graphics) clock.
188 * @PP_MCLK_DPM_MASK: Dynamic adjustment of the memory clock.
189 * @PP_PCIE_DPM_MASK: Dynamic adjustment of PCIE clocks and lanes.
190 * @PP_SCLK_DEEP_SLEEP_MASK: System (graphics) clock deep sleep.
191 * @PP_POWER_CONTAINMENT_MASK: Power containment.
192 * @PP_UVD_HANDSHAKE_MASK: Unified video decoder handshake.
193 * @PP_SMC_VOLTAGE_CONTROL_MASK: Dynamic voltage control.
194 * @PP_VBI_TIME_SUPPORT_MASK: Vertical blank interval support.
195 * @PP_ULV_MASK: Ultra low voltage.
196 * @PP_ENABLE_GFX_CG_THRU_SMU: SMU control of GFX engine clockgating.
197 * @PP_CLOCK_STRETCH_MASK: Clock stretching.
198 * @PP_OD_FUZZY_FAN_CONTROL_MASK: Overdrive fuzzy fan control.
199 * @PP_SOCCLK_DPM_MASK: Dynamic adjustment of the SoC clock.
200 * @PP_DCEFCLK_DPM_MASK: Dynamic adjustment of the Display Controller Engine Fabric clock.
201 * @PP_OVERDRIVE_MASK: Over- and under-clocking support.
202 * @PP_GFXOFF_MASK: Dynamic graphics engine power control.
203 * @PP_ACG_MASK: Adaptive clock generator.
204 * @PP_STUTTER_MODE: Stutter mode.
205 * @PP_AVFS_MASK: Adaptive voltage and frequency scaling.
206 * @PP_GFX_DCS_MASK: GFX Async DCS.
207 *
208 * To override these settings on boot, append amdgpu.ppfeaturemask=<mask> to
209 * the kernel's command line parameters. This is usually done through a system's
210 * boot loader (E.g. GRUB). If manually loading the driver, pass
211 * ppfeaturemask=<mask> as a modprobe parameter.
212 */
213enum PP_FEATURE_MASK {
214 PP_SCLK_DPM_MASK = 0x1,
215 PP_MCLK_DPM_MASK = 0x2,
216 PP_PCIE_DPM_MASK = 0x4,
217 PP_SCLK_DEEP_SLEEP_MASK = 0x8,
218 PP_POWER_CONTAINMENT_MASK = 0x10,
219 PP_UVD_HANDSHAKE_MASK = 0x20,
220 PP_SMC_VOLTAGE_CONTROL_MASK = 0x40,
221 PP_VBI_TIME_SUPPORT_MASK = 0x80,
222 PP_ULV_MASK = 0x100,
223 PP_ENABLE_GFX_CG_THRU_SMU = 0x200,
224 PP_CLOCK_STRETCH_MASK = 0x400,
225 PP_OD_FUZZY_FAN_CONTROL_MASK = 0x800,
226 PP_SOCCLK_DPM_MASK = 0x1000,
227 PP_DCEFCLK_DPM_MASK = 0x2000,
228 PP_OVERDRIVE_MASK = 0x4000,
229 PP_GFXOFF_MASK = 0x8000,
230 PP_ACG_MASK = 0x10000,
231 PP_STUTTER_MODE = 0x20000,
232 PP_AVFS_MASK = 0x40000,
233 PP_GFX_DCS_MASK = 0x80000,
234};
235
236enum amd_harvest_ip_mask {
237 AMD_HARVEST_IP_VCN_MASK = 0x1,
238 AMD_HARVEST_IP_JPEG_MASK = 0x2,
239 AMD_HARVEST_IP_DMU_MASK = 0x4,
240};
241
242enum DC_FEATURE_MASK {
243 //Default value can be found at "uint amdgpu_dc_feature_mask"
244 DC_FBC_MASK = (1 << 0), //0x1, disabled by default
245 DC_MULTI_MON_PP_MCLK_SWITCH_MASK = (1 << 1), //0x2, enabled by default
246 DC_DISABLE_FRACTIONAL_PWM_MASK = (1 << 2), //0x4, disabled by default
247 DC_PSR_MASK = (1 << 3), //0x8, disabled by default for dcn < 3.1
248 DC_EDP_NO_POWER_SEQUENCING = (1 << 4), //0x10, disabled by default
249 DC_DISABLE_LTTPR_DP1_4A = (1 << 5), //0x20, disabled by default
250 DC_DISABLE_LTTPR_DP2_0 = (1 << 6), //0x40, disabled by default
251 DC_PSR_ALLOW_SMU_OPT = (1 << 7), //0x80, disabled by default
252 DC_PSR_ALLOW_MULTI_DISP_OPT = (1 << 8), //0x100, disabled by default
253 DC_REPLAY_MASK = (1 << 9), //0x200, disabled by default for dcn < 3.1.4
254};
255
256/**
257 * enum DC_DEBUG_MASK - Bits that are useful for debugging the Display Core IP
258 */
259enum DC_DEBUG_MASK {
260 /**
261 * @DC_DISABLE_PIPE_SPLIT: If set, disable pipe-splitting
262 */
263 DC_DISABLE_PIPE_SPLIT = 0x1,
264
265 /**
266 * @DC_DISABLE_STUTTER: If set, disable memory stutter mode
267 */
268 DC_DISABLE_STUTTER = 0x2,
269
270 /**
271 * @DC_DISABLE_DSC: If set, disable display stream compression
272 */
273 DC_DISABLE_DSC = 0x4,
274
275 /**
276 * @DC_DISABLE_CLOCK_GATING: If set, disable clock gating optimizations
277 */
278 DC_DISABLE_CLOCK_GATING = 0x8,
279
280 /**
281 * @DC_DISABLE_PSR: If set, disable Panel self refresh v1 and PSR-SU
282 */
283 DC_DISABLE_PSR = 0x10,
284
285 /**
286 * @DC_FORCE_SUBVP_MCLK_SWITCH: If set, force mclk switch in subvp, even
287 * if mclk switch in vblank is possible
288 */
289 DC_FORCE_SUBVP_MCLK_SWITCH = 0x20,
290
291 /**
292 * @DC_DISABLE_MPO: If set, disable multi-plane offloading
293 */
294 DC_DISABLE_MPO = 0x40,
295
296 /**
297 * @DC_ENABLE_DPIA_TRACE: If set, enable trace logging for DPIA
298 */
299 DC_ENABLE_DPIA_TRACE = 0x80,
300
301 /**
302 * @DC_ENABLE_DML2: If set, force usage of DML2, even if the DCN version
303 * does not default to it.
304 */
305 DC_ENABLE_DML2 = 0x100,
306
307 /**
308 * @DC_DISABLE_PSR_SU: If set, disable PSR SU
309 */
310 DC_DISABLE_PSR_SU = 0x200,
311
312 /**
313 * @DC_DISABLE_REPLAY: If set, disable Panel Replay
314 */
315 DC_DISABLE_REPLAY = 0x400,
316
317 /**
318 * @DC_DISABLE_IPS: If set, disable all Idle Power States, all the time.
319 * If more than one IPS debug bit is set, the lowest bit takes
320 * precedence. For example, if DC_FORCE_IPS_ENABLE and
321 * DC_DISABLE_IPS_DYNAMIC are set, then DC_DISABLE_IPS_DYNAMIC takes
322 * precedence.
323 */
324 DC_DISABLE_IPS = 0x800,
325
326 /**
327 * @DC_DISABLE_IPS_DYNAMIC: If set, disable all IPS, all the time,
328 * *except* when driver goes into suspend.
329 */
330 DC_DISABLE_IPS_DYNAMIC = 0x1000,
331
332 /**
333 * @DC_DISABLE_IPS2_DYNAMIC: If set, disable IPS2 (IPS1 allowed) if
334 * there is an enabled display. Otherwise, enable all IPS.
335 */
336 DC_DISABLE_IPS2_DYNAMIC = 0x2000,
337
338 /**
339 * @DC_FORCE_IPS_ENABLE: If set, force enable all IPS, all the time.
340 */
341 DC_FORCE_IPS_ENABLE = 0x4000,
342 /**
343 * @DC_DISABLE_ACPI_EDID: If set, don't attempt to fetch EDID for
344 * eDP display from ACPI _DDC method.
345 */
346 DC_DISABLE_ACPI_EDID = 0x8000,
347};
348
349enum amd_dpm_forced_level;
350
351/**
352 * struct amd_ip_funcs - general hooks for managing amdgpu IP Blocks
353 * @name: Name of IP block
354 * @early_init: sets up early driver state (pre sw_init),
355 * does not configure hw - Optional
356 * @late_init: sets up late driver/hw state (post hw_init) - Optional
357 * @sw_init: sets up driver state, does not configure hw
358 * @sw_fini: tears down driver state, does not configure hw
359 * @early_fini: tears down stuff before dev detached from driver
360 * @hw_init: sets up the hw state
361 * @hw_fini: tears down the hw state
362 * @late_fini: final cleanup
363 * @prepare_suspend: handle IP specific changes to prepare for suspend
364 * (such as allocating any required memory)
365 * @suspend: handles IP specific hw/sw changes for suspend
366 * @resume: handles IP specific hw/sw changes for resume
367 * @is_idle: returns current IP block idle status
368 * @wait_for_idle: poll for idle
369 * @check_soft_reset: check soft reset the IP block
370 * @pre_soft_reset: pre soft reset the IP block
371 * @soft_reset: soft reset the IP block
372 * @post_soft_reset: post soft reset the IP block
373 * @set_clockgating_state: enable/disable cg for the IP block
374 * @set_powergating_state: enable/disable pg for the IP block
375 * @get_clockgating_state: get current clockgating status
376 * @dump_ip_state: dump the IP state of the ASIC during a gpu hang
377 * @print_ip_state: print the IP state in devcoredump for each IP of the ASIC
378 *
379 * These hooks provide an interface for controlling the operational state
380 * of IP blocks. After acquiring a list of IP blocks for the GPU in use,
381 * the driver can make chip-wide state changes by walking this list and
382 * making calls to hooks from each IP block. This list is ordered to ensure
383 * that the driver initializes the IP blocks in a safe sequence.
384 */
385struct amd_ip_funcs {
386 char *name;
387 int (*early_init)(struct amdgpu_ip_block *ip_block);
388 int (*late_init)(struct amdgpu_ip_block *ip_block);
389 int (*sw_init)(struct amdgpu_ip_block *ip_block);
390 int (*sw_fini)(struct amdgpu_ip_block *ip_block);
391 int (*early_fini)(struct amdgpu_ip_block *ip_block);
392 int (*hw_init)(struct amdgpu_ip_block *ip_block);
393 int (*hw_fini)(struct amdgpu_ip_block *ip_block);
394 void (*late_fini)(struct amdgpu_ip_block *ip_block);
395 int (*prepare_suspend)(struct amdgpu_ip_block *ip_block);
396 int (*suspend)(struct amdgpu_ip_block *ip_block);
397 int (*resume)(struct amdgpu_ip_block *ip_block);
398 bool (*is_idle)(void *handle);
399 int (*wait_for_idle)(struct amdgpu_ip_block *ip_block);
400 bool (*check_soft_reset)(struct amdgpu_ip_block *ip_block);
401 int (*pre_soft_reset)(struct amdgpu_ip_block *ip_block);
402 int (*soft_reset)(struct amdgpu_ip_block *ip_block);
403 int (*post_soft_reset)(struct amdgpu_ip_block *ip_block);
404 int (*set_clockgating_state)(void *handle,
405 enum amd_clockgating_state state);
406 int (*set_powergating_state)(void *handle,
407 enum amd_powergating_state state);
408 void (*get_clockgating_state)(void *handle, u64 *flags);
409 void (*dump_ip_state)(struct amdgpu_ip_block *ip_block);
410 void (*print_ip_state)(struct amdgpu_ip_block *ip_block, struct drm_printer *p);
411};
412
413
414#endif /* __AMD_SHARED_H__ */