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1/*
2 * Copyright 2015 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22
23#ifndef __AMD_SHARED_H__
24#define __AMD_SHARED_H__
25
26#include <drm/amd_asic_type.h>
27
28
29#define AMD_MAX_USEC_TIMEOUT 1000000 /* 1000 ms */
30
31/*
32 * Chip flags
33 */
34enum amd_chip_flags {
35 AMD_ASIC_MASK = 0x0000ffffUL,
36 AMD_FLAGS_MASK = 0xffff0000UL,
37 AMD_IS_MOBILITY = 0x00010000UL,
38 AMD_IS_APU = 0x00020000UL,
39 AMD_IS_PX = 0x00040000UL,
40 AMD_EXP_HW_SUPPORT = 0x00080000UL,
41};
42
43enum amd_apu_flags {
44 AMD_APU_IS_RAVEN = 0x00000001UL,
45 AMD_APU_IS_RAVEN2 = 0x00000002UL,
46 AMD_APU_IS_PICASSO = 0x00000004UL,
47 AMD_APU_IS_RENOIR = 0x00000008UL,
48 AMD_APU_IS_GREEN_SARDINE = 0x00000010UL,
49 AMD_APU_IS_VANGOGH = 0x00000020UL,
50 AMD_APU_IS_CYAN_SKILLFISH2 = 0x00000040UL,
51};
52
53/**
54* DOC: IP Blocks
55*
56* GPUs are composed of IP (intellectual property) blocks. These
57* IP blocks provide various functionalities: display, graphics,
58* video decode, etc. The IP blocks that comprise a particular GPU
59* are listed in the GPU's respective SoC file. amdgpu_device.c
60* acquires the list of IP blocks for the GPU in use on initialization.
61* It can then operate on this list to perform standard driver operations
62* such as: init, fini, suspend, resume, etc.
63*
64*
65* IP block implementations are named using the following convention:
66* <functionality>_v<version> (E.g.: gfx_v6_0).
67*/
68
69/**
70* enum amd_ip_block_type - Used to classify IP blocks by functionality.
71*
72* @AMD_IP_BLOCK_TYPE_COMMON: GPU Family
73* @AMD_IP_BLOCK_TYPE_GMC: Graphics Memory Controller
74* @AMD_IP_BLOCK_TYPE_IH: Interrupt Handler
75* @AMD_IP_BLOCK_TYPE_SMC: System Management Controller
76* @AMD_IP_BLOCK_TYPE_PSP: Platform Security Processor
77* @AMD_IP_BLOCK_TYPE_DCE: Display and Compositing Engine
78* @AMD_IP_BLOCK_TYPE_GFX: Graphics and Compute Engine
79* @AMD_IP_BLOCK_TYPE_SDMA: System DMA Engine
80* @AMD_IP_BLOCK_TYPE_UVD: Unified Video Decoder
81* @AMD_IP_BLOCK_TYPE_VCE: Video Compression Engine
82* @AMD_IP_BLOCK_TYPE_ACP: Audio Co-Processor
83* @AMD_IP_BLOCK_TYPE_VCN: Video Core/Codec Next
84* @AMD_IP_BLOCK_TYPE_MES: Micro-Engine Scheduler
85* @AMD_IP_BLOCK_TYPE_JPEG: JPEG Engine
86* @AMD_IP_BLOCK_TYPE_VPE: Video Processing Engine
87* @AMD_IP_BLOCK_TYPE_UMSCH_MM: User Mode Schduler for Multimedia
88* @AMD_IP_BLOCK_TYPE_NUM: Total number of IP block types
89*/
90enum amd_ip_block_type {
91 AMD_IP_BLOCK_TYPE_COMMON,
92 AMD_IP_BLOCK_TYPE_GMC,
93 AMD_IP_BLOCK_TYPE_IH,
94 AMD_IP_BLOCK_TYPE_SMC,
95 AMD_IP_BLOCK_TYPE_PSP,
96 AMD_IP_BLOCK_TYPE_DCE,
97 AMD_IP_BLOCK_TYPE_GFX,
98 AMD_IP_BLOCK_TYPE_SDMA,
99 AMD_IP_BLOCK_TYPE_UVD,
100 AMD_IP_BLOCK_TYPE_VCE,
101 AMD_IP_BLOCK_TYPE_ACP,
102 AMD_IP_BLOCK_TYPE_VCN,
103 AMD_IP_BLOCK_TYPE_MES,
104 AMD_IP_BLOCK_TYPE_JPEG,
105 AMD_IP_BLOCK_TYPE_VPE,
106 AMD_IP_BLOCK_TYPE_UMSCH_MM,
107 AMD_IP_BLOCK_TYPE_NUM,
108};
109
110enum amd_clockgating_state {
111 AMD_CG_STATE_GATE = 0,
112 AMD_CG_STATE_UNGATE,
113};
114
115
116enum amd_powergating_state {
117 AMD_PG_STATE_GATE = 0,
118 AMD_PG_STATE_UNGATE,
119};
120
121
122/* CG flags */
123#define AMD_CG_SUPPORT_GFX_MGCG (1ULL << 0)
124#define AMD_CG_SUPPORT_GFX_MGLS (1ULL << 1)
125#define AMD_CG_SUPPORT_GFX_CGCG (1ULL << 2)
126#define AMD_CG_SUPPORT_GFX_CGLS (1ULL << 3)
127#define AMD_CG_SUPPORT_GFX_CGTS (1ULL << 4)
128#define AMD_CG_SUPPORT_GFX_CGTS_LS (1ULL << 5)
129#define AMD_CG_SUPPORT_GFX_CP_LS (1ULL << 6)
130#define AMD_CG_SUPPORT_GFX_RLC_LS (1ULL << 7)
131#define AMD_CG_SUPPORT_MC_LS (1ULL << 8)
132#define AMD_CG_SUPPORT_MC_MGCG (1ULL << 9)
133#define AMD_CG_SUPPORT_SDMA_LS (1ULL << 10)
134#define AMD_CG_SUPPORT_SDMA_MGCG (1ULL << 11)
135#define AMD_CG_SUPPORT_BIF_LS (1ULL << 12)
136#define AMD_CG_SUPPORT_UVD_MGCG (1ULL << 13)
137#define AMD_CG_SUPPORT_VCE_MGCG (1ULL << 14)
138#define AMD_CG_SUPPORT_HDP_LS (1ULL << 15)
139#define AMD_CG_SUPPORT_HDP_MGCG (1ULL << 16)
140#define AMD_CG_SUPPORT_ROM_MGCG (1ULL << 17)
141#define AMD_CG_SUPPORT_DRM_LS (1ULL << 18)
142#define AMD_CG_SUPPORT_BIF_MGCG (1ULL << 19)
143#define AMD_CG_SUPPORT_GFX_3D_CGCG (1ULL << 20)
144#define AMD_CG_SUPPORT_GFX_3D_CGLS (1ULL << 21)
145#define AMD_CG_SUPPORT_DRM_MGCG (1ULL << 22)
146#define AMD_CG_SUPPORT_DF_MGCG (1ULL << 23)
147#define AMD_CG_SUPPORT_VCN_MGCG (1ULL << 24)
148#define AMD_CG_SUPPORT_HDP_DS (1ULL << 25)
149#define AMD_CG_SUPPORT_HDP_SD (1ULL << 26)
150#define AMD_CG_SUPPORT_IH_CG (1ULL << 27)
151#define AMD_CG_SUPPORT_ATHUB_LS (1ULL << 28)
152#define AMD_CG_SUPPORT_ATHUB_MGCG (1ULL << 29)
153#define AMD_CG_SUPPORT_JPEG_MGCG (1ULL << 30)
154#define AMD_CG_SUPPORT_GFX_FGCG (1ULL << 31)
155#define AMD_CG_SUPPORT_REPEATER_FGCG (1ULL << 32)
156#define AMD_CG_SUPPORT_GFX_PERF_CLK (1ULL << 33)
157/* PG flags */
158#define AMD_PG_SUPPORT_GFX_PG (1 << 0)
159#define AMD_PG_SUPPORT_GFX_SMG (1 << 1)
160#define AMD_PG_SUPPORT_GFX_DMG (1 << 2)
161#define AMD_PG_SUPPORT_UVD (1 << 3)
162#define AMD_PG_SUPPORT_VCE (1 << 4)
163#define AMD_PG_SUPPORT_CP (1 << 5)
164#define AMD_PG_SUPPORT_GDS (1 << 6)
165#define AMD_PG_SUPPORT_RLC_SMU_HS (1 << 7)
166#define AMD_PG_SUPPORT_SDMA (1 << 8)
167#define AMD_PG_SUPPORT_ACP (1 << 9)
168#define AMD_PG_SUPPORT_SAMU (1 << 10)
169#define AMD_PG_SUPPORT_GFX_QUICK_MG (1 << 11)
170#define AMD_PG_SUPPORT_GFX_PIPELINE (1 << 12)
171#define AMD_PG_SUPPORT_MMHUB (1 << 13)
172#define AMD_PG_SUPPORT_VCN (1 << 14)
173#define AMD_PG_SUPPORT_VCN_DPG (1 << 15)
174#define AMD_PG_SUPPORT_ATHUB (1 << 16)
175#define AMD_PG_SUPPORT_JPEG (1 << 17)
176#define AMD_PG_SUPPORT_IH_SRAM_PG (1 << 18)
177#define AMD_PG_SUPPORT_JPEG_DPG (1 << 19)
178
179/**
180 * enum PP_FEATURE_MASK - Used to mask power play features.
181 *
182 * @PP_SCLK_DPM_MASK: Dynamic adjustment of the system (graphics) clock.
183 * @PP_MCLK_DPM_MASK: Dynamic adjustment of the memory clock.
184 * @PP_PCIE_DPM_MASK: Dynamic adjustment of PCIE clocks and lanes.
185 * @PP_SCLK_DEEP_SLEEP_MASK: System (graphics) clock deep sleep.
186 * @PP_POWER_CONTAINMENT_MASK: Power containment.
187 * @PP_UVD_HANDSHAKE_MASK: Unified video decoder handshake.
188 * @PP_SMC_VOLTAGE_CONTROL_MASK: Dynamic voltage control.
189 * @PP_VBI_TIME_SUPPORT_MASK: Vertical blank interval support.
190 * @PP_ULV_MASK: Ultra low voltage.
191 * @PP_ENABLE_GFX_CG_THRU_SMU: SMU control of GFX engine clockgating.
192 * @PP_CLOCK_STRETCH_MASK: Clock stretching.
193 * @PP_OD_FUZZY_FAN_CONTROL_MASK: Overdrive fuzzy fan control.
194 * @PP_SOCCLK_DPM_MASK: Dynamic adjustment of the SoC clock.
195 * @PP_DCEFCLK_DPM_MASK: Dynamic adjustment of the Display Controller Engine Fabric clock.
196 * @PP_OVERDRIVE_MASK: Over- and under-clocking support.
197 * @PP_GFXOFF_MASK: Dynamic graphics engine power control.
198 * @PP_ACG_MASK: Adaptive clock generator.
199 * @PP_STUTTER_MODE: Stutter mode.
200 * @PP_AVFS_MASK: Adaptive voltage and frequency scaling.
201 * @PP_GFX_DCS_MASK: GFX Async DCS.
202 *
203 * To override these settings on boot, append amdgpu.ppfeaturemask=<mask> to
204 * the kernel's command line parameters. This is usually done through a system's
205 * boot loader (E.g. GRUB). If manually loading the driver, pass
206 * ppfeaturemask=<mask> as a modprobe parameter.
207 */
208enum PP_FEATURE_MASK {
209 PP_SCLK_DPM_MASK = 0x1,
210 PP_MCLK_DPM_MASK = 0x2,
211 PP_PCIE_DPM_MASK = 0x4,
212 PP_SCLK_DEEP_SLEEP_MASK = 0x8,
213 PP_POWER_CONTAINMENT_MASK = 0x10,
214 PP_UVD_HANDSHAKE_MASK = 0x20,
215 PP_SMC_VOLTAGE_CONTROL_MASK = 0x40,
216 PP_VBI_TIME_SUPPORT_MASK = 0x80,
217 PP_ULV_MASK = 0x100,
218 PP_ENABLE_GFX_CG_THRU_SMU = 0x200,
219 PP_CLOCK_STRETCH_MASK = 0x400,
220 PP_OD_FUZZY_FAN_CONTROL_MASK = 0x800,
221 PP_SOCCLK_DPM_MASK = 0x1000,
222 PP_DCEFCLK_DPM_MASK = 0x2000,
223 PP_OVERDRIVE_MASK = 0x4000,
224 PP_GFXOFF_MASK = 0x8000,
225 PP_ACG_MASK = 0x10000,
226 PP_STUTTER_MODE = 0x20000,
227 PP_AVFS_MASK = 0x40000,
228 PP_GFX_DCS_MASK = 0x80000,
229};
230
231enum amd_harvest_ip_mask {
232 AMD_HARVEST_IP_VCN_MASK = 0x1,
233 AMD_HARVEST_IP_JPEG_MASK = 0x2,
234 AMD_HARVEST_IP_DMU_MASK = 0x4,
235};
236
237enum DC_FEATURE_MASK {
238 //Default value can be found at "uint amdgpu_dc_feature_mask"
239 DC_FBC_MASK = (1 << 0), //0x1, disabled by default
240 DC_MULTI_MON_PP_MCLK_SWITCH_MASK = (1 << 1), //0x2, enabled by default
241 DC_DISABLE_FRACTIONAL_PWM_MASK = (1 << 2), //0x4, disabled by default
242 DC_PSR_MASK = (1 << 3), //0x8, disabled by default for dcn < 3.1
243 DC_EDP_NO_POWER_SEQUENCING = (1 << 4), //0x10, disabled by default
244 DC_DISABLE_LTTPR_DP1_4A = (1 << 5), //0x20, disabled by default
245 DC_DISABLE_LTTPR_DP2_0 = (1 << 6), //0x40, disabled by default
246 DC_PSR_ALLOW_SMU_OPT = (1 << 7), //0x80, disabled by default
247 DC_PSR_ALLOW_MULTI_DISP_OPT = (1 << 8), //0x100, disabled by default
248 DC_REPLAY_MASK = (1 << 9), //0x200, disabled by default for dcn < 3.1.4
249};
250
251enum DC_DEBUG_MASK {
252 DC_DISABLE_PIPE_SPLIT = 0x1,
253 DC_DISABLE_STUTTER = 0x2,
254 DC_DISABLE_DSC = 0x4,
255 DC_DISABLE_CLOCK_GATING = 0x8,
256 DC_DISABLE_PSR = 0x10,
257 DC_FORCE_SUBVP_MCLK_SWITCH = 0x20,
258 DC_DISABLE_MPO = 0x40,
259 DC_ENABLE_DPIA_TRACE = 0x80,
260 DC_ENABLE_DML2 = 0x100,
261 DC_DISABLE_PSR_SU = 0x200,
262 DC_DISABLE_REPLAY = 0x400,
263 DC_DISABLE_IPS = 0x800,
264};
265
266enum amd_dpm_forced_level;
267
268/**
269 * struct amd_ip_funcs - general hooks for managing amdgpu IP Blocks
270 * @name: Name of IP block
271 * @early_init: sets up early driver state (pre sw_init),
272 * does not configure hw - Optional
273 * @late_init: sets up late driver/hw state (post hw_init) - Optional
274 * @sw_init: sets up driver state, does not configure hw
275 * @sw_fini: tears down driver state, does not configure hw
276 * @early_fini: tears down stuff before dev detached from driver
277 * @hw_init: sets up the hw state
278 * @hw_fini: tears down the hw state
279 * @late_fini: final cleanup
280 * @prepare_suspend: handle IP specific changes to prepare for suspend
281 * (such as allocating any required memory)
282 * @suspend: handles IP specific hw/sw changes for suspend
283 * @resume: handles IP specific hw/sw changes for resume
284 * @is_idle: returns current IP block idle status
285 * @wait_for_idle: poll for idle
286 * @check_soft_reset: check soft reset the IP block
287 * @pre_soft_reset: pre soft reset the IP block
288 * @soft_reset: soft reset the IP block
289 * @post_soft_reset: post soft reset the IP block
290 * @set_clockgating_state: enable/disable cg for the IP block
291 * @set_powergating_state: enable/disable pg for the IP block
292 * @get_clockgating_state: get current clockgating status
293 *
294 * These hooks provide an interface for controlling the operational state
295 * of IP blocks. After acquiring a list of IP blocks for the GPU in use,
296 * the driver can make chip-wide state changes by walking this list and
297 * making calls to hooks from each IP block. This list is ordered to ensure
298 * that the driver initializes the IP blocks in a safe sequence.
299 */
300struct amd_ip_funcs {
301 char *name;
302 int (*early_init)(void *handle);
303 int (*late_init)(void *handle);
304 int (*sw_init)(void *handle);
305 int (*sw_fini)(void *handle);
306 int (*early_fini)(void *handle);
307 int (*hw_init)(void *handle);
308 int (*hw_fini)(void *handle);
309 void (*late_fini)(void *handle);
310 int (*prepare_suspend)(void *handle);
311 int (*suspend)(void *handle);
312 int (*resume)(void *handle);
313 bool (*is_idle)(void *handle);
314 int (*wait_for_idle)(void *handle);
315 bool (*check_soft_reset)(void *handle);
316 int (*pre_soft_reset)(void *handle);
317 int (*soft_reset)(void *handle);
318 int (*post_soft_reset)(void *handle);
319 int (*set_clockgating_state)(void *handle,
320 enum amd_clockgating_state state);
321 int (*set_powergating_state)(void *handle,
322 enum amd_powergating_state state);
323 void (*get_clockgating_state)(void *handle, u64 *flags);
324};
325
326
327#endif /* __AMD_SHARED_H__ */