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1/*
2 * Copyright 2012-14 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26#ifndef DC_INTERFACE_H_
27#define DC_INTERFACE_H_
28
29#include "dc_types.h"
30#include "grph_object_defs.h"
31#include "logger_types.h"
32#if defined(CONFIG_DRM_AMD_DC_HDCP)
33#include "hdcp_types.h"
34#endif
35#include "gpio_types.h"
36#include "link_service_types.h"
37#include "grph_object_ctrl_defs.h"
38#include <inc/hw/opp.h>
39
40#include "inc/hw_sequencer.h"
41#include "inc/compressor.h"
42#include "inc/hw/dmcu.h"
43#include "dml/display_mode_lib.h"
44
45#define DC_VER "3.2.95"
46
47#define MAX_SURFACES 3
48#define MAX_PLANES 6
49#define MAX_STREAMS 6
50#define MAX_SINKS_PER_LINK 4
51
52/*******************************************************************************
53 * Display Core Interfaces
54 ******************************************************************************/
55struct dc_versions {
56 const char *dc_ver;
57 struct dmcu_version dmcu_version;
58};
59
60enum dp_protocol_version {
61 DP_VERSION_1_4,
62};
63
64enum dc_plane_type {
65 DC_PLANE_TYPE_INVALID,
66 DC_PLANE_TYPE_DCE_RGB,
67 DC_PLANE_TYPE_DCE_UNDERLAY,
68 DC_PLANE_TYPE_DCN_UNIVERSAL,
69};
70
71struct dc_plane_cap {
72 enum dc_plane_type type;
73 uint32_t blends_with_above : 1;
74 uint32_t blends_with_below : 1;
75 uint32_t per_pixel_alpha : 1;
76 struct {
77 uint32_t argb8888 : 1;
78 uint32_t nv12 : 1;
79 uint32_t fp16 : 1;
80 uint32_t p010 : 1;
81 uint32_t ayuv : 1;
82 } pixel_format_support;
83 // max upscaling factor x1000
84 // upscaling factors are always >= 1
85 // for example, 1080p -> 8K is 4.0, or 4000 raw value
86 struct {
87 uint32_t argb8888;
88 uint32_t nv12;
89 uint32_t fp16;
90 } max_upscale_factor;
91 // max downscale factor x1000
92 // downscale factors are always <= 1
93 // for example, 8K -> 1080p is 0.25, or 250 raw value
94 struct {
95 uint32_t argb8888;
96 uint32_t nv12;
97 uint32_t fp16;
98 } max_downscale_factor;
99 // minimal width/height
100 uint32_t min_width;
101 uint32_t min_height;
102};
103
104// Color management caps (DPP and MPC)
105struct rom_curve_caps {
106 uint16_t srgb : 1;
107 uint16_t bt2020 : 1;
108 uint16_t gamma2_2 : 1;
109 uint16_t pq : 1;
110 uint16_t hlg : 1;
111};
112
113struct dpp_color_caps {
114 uint16_t dcn_arch : 1; // all DCE generations treated the same
115 // input lut is different than most LUTs, just plain 256-entry lookup
116 uint16_t input_lut_shared : 1; // shared with DGAM
117 uint16_t icsc : 1;
118 uint16_t dgam_ram : 1;
119 uint16_t post_csc : 1; // before gamut remap
120 uint16_t gamma_corr : 1;
121
122 // hdr_mult and gamut remap always available in DPP (in that order)
123 // 3d lut implies shaper LUT,
124 // it may be shared with MPC - check MPC:shared_3d_lut flag
125 uint16_t hw_3d_lut : 1;
126 uint16_t ogam_ram : 1; // blnd gam
127 uint16_t ocsc : 1;
128 struct rom_curve_caps dgam_rom_caps;
129 struct rom_curve_caps ogam_rom_caps;
130};
131
132struct mpc_color_caps {
133 uint16_t gamut_remap : 1;
134 uint16_t ogam_ram : 1;
135 uint16_t ocsc : 1;
136 uint16_t num_3dluts : 3; //3d lut always assumes a preceding shaper LUT
137 uint16_t shared_3d_lut:1; //can be in either DPP or MPC, but single instance
138
139 struct rom_curve_caps ogam_rom_caps;
140};
141
142struct dc_color_caps {
143 struct dpp_color_caps dpp;
144 struct mpc_color_caps mpc;
145};
146
147struct dc_caps {
148 uint32_t max_streams;
149 uint32_t max_links;
150 uint32_t max_audios;
151 uint32_t max_slave_planes;
152 uint32_t max_planes;
153 uint32_t max_downscale_ratio;
154 uint32_t i2c_speed_in_khz;
155 uint32_t dmdata_alloc_size;
156 unsigned int max_cursor_size;
157 unsigned int max_video_width;
158 int linear_pitch_alignment;
159 bool dcc_const_color;
160 bool dynamic_audio;
161 bool is_apu;
162 bool dual_link_dvi;
163 bool post_blend_color_processing;
164 bool force_dp_tps4_for_cp2520;
165 bool disable_dp_clk_share;
166 bool psp_setup_panel_mode;
167 bool extended_aux_timeout_support;
168 bool dmcub_support;
169 enum dp_protocol_version max_dp_protocol_version;
170 struct dc_plane_cap planes[MAX_PLANES];
171 struct dc_color_caps color;
172};
173
174struct dc_bug_wa {
175 bool no_connect_phy_config;
176 bool dedcn20_305_wa;
177 bool skip_clock_update;
178 bool lt_early_cr_pattern;
179};
180
181struct dc_dcc_surface_param {
182 struct dc_size surface_size;
183 enum surface_pixel_format format;
184 enum swizzle_mode_values swizzle_mode;
185 enum dc_scan_direction scan;
186};
187
188struct dc_dcc_setting {
189 unsigned int max_compressed_blk_size;
190 unsigned int max_uncompressed_blk_size;
191 bool independent_64b_blks;
192#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
193 //These bitfields to be used starting with DCN 3.0
194 struct {
195 uint32_t dcc_256_64_64 : 1;//available in ASICs before DCN 3.0 (the worst compression case)
196 uint32_t dcc_128_128_uncontrained : 1; //available in ASICs before DCN 3.0
197 uint32_t dcc_256_128_128 : 1; //available starting with DCN 3.0
198 uint32_t dcc_256_256_unconstrained : 1; //available in ASICs before DCN 3.0 (the best compression case)
199 } dcc_controls;
200#endif
201};
202
203struct dc_surface_dcc_cap {
204 union {
205 struct {
206 struct dc_dcc_setting rgb;
207 } grph;
208
209 struct {
210 struct dc_dcc_setting luma;
211 struct dc_dcc_setting chroma;
212 } video;
213 };
214
215 bool capable;
216 bool const_color_support;
217};
218
219struct dc_static_screen_params {
220 struct {
221 bool force_trigger;
222 bool cursor_update;
223 bool surface_update;
224 bool overlay_update;
225 } triggers;
226 unsigned int num_frames;
227};
228
229
230/* Surface update type is used by dc_update_surfaces_and_stream
231 * The update type is determined at the very beginning of the function based
232 * on parameters passed in and decides how much programming (or updating) is
233 * going to be done during the call.
234 *
235 * UPDATE_TYPE_FAST is used for really fast updates that do not require much
236 * logical calculations or hardware register programming. This update MUST be
237 * ISR safe on windows. Currently fast update will only be used to flip surface
238 * address.
239 *
240 * UPDATE_TYPE_MED is used for slower updates which require significant hw
241 * re-programming however do not affect bandwidth consumption or clock
242 * requirements. At present, this is the level at which front end updates
243 * that do not require us to run bw_calcs happen. These are in/out transfer func
244 * updates, viewport offset changes, recout size changes and pixel depth changes.
245 * This update can be done at ISR, but we want to minimize how often this happens.
246 *
247 * UPDATE_TYPE_FULL is slow. Really slow. This requires us to recalculate our
248 * bandwidth and clocks, possibly rearrange some pipes and reprogram anything front
249 * end related. Any time viewport dimensions, recout dimensions, scaling ratios or
250 * gamma need to be adjusted or pipe needs to be turned on (or disconnected) we do
251 * a full update. This cannot be done at ISR level and should be a rare event.
252 * Unless someone is stress testing mpo enter/exit, playing with colour or adjusting
253 * underscan we don't expect to see this call at all.
254 */
255
256enum surface_update_type {
257 UPDATE_TYPE_FAST, /* super fast, safe to execute in isr */
258 UPDATE_TYPE_MED, /* ISR safe, most of programming needed, no bw/clk change*/
259 UPDATE_TYPE_FULL, /* may need to shuffle resources */
260};
261
262/* Forward declaration*/
263struct dc;
264struct dc_plane_state;
265struct dc_state;
266
267
268struct dc_cap_funcs {
269 bool (*get_dcc_compression_cap)(const struct dc *dc,
270 const struct dc_dcc_surface_param *input,
271 struct dc_surface_dcc_cap *output);
272};
273
274struct link_training_settings;
275
276
277/* Structure to hold configuration flags set by dm at dc creation. */
278struct dc_config {
279 bool gpu_vm_support;
280 bool disable_disp_pll_sharing;
281 bool fbc_support;
282 bool optimize_edp_link_rate;
283 bool disable_fractional_pwm;
284 bool allow_seamless_boot_optimization;
285 bool power_down_display_on_boot;
286 bool edp_not_connected;
287 bool force_enum_edp;
288 bool forced_clocks;
289 bool allow_lttpr_non_transparent_mode;
290 bool multi_mon_pp_mclk_switch;
291 bool disable_dmcu;
292 bool enable_4to1MPC;
293#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
294 bool clamp_min_dcfclk;
295#endif
296};
297
298enum visual_confirm {
299 VISUAL_CONFIRM_DISABLE = 0,
300 VISUAL_CONFIRM_SURFACE = 1,
301 VISUAL_CONFIRM_HDR = 2,
302 VISUAL_CONFIRM_MPCTREE = 4,
303 VISUAL_CONFIRM_PSR = 5,
304};
305
306enum dcc_option {
307 DCC_ENABLE = 0,
308 DCC_DISABLE = 1,
309 DCC_HALF_REQ_DISALBE = 2,
310};
311
312enum pipe_split_policy {
313 MPC_SPLIT_DYNAMIC = 0,
314 MPC_SPLIT_AVOID = 1,
315 MPC_SPLIT_AVOID_MULT_DISP = 2,
316};
317
318enum wm_report_mode {
319 WM_REPORT_DEFAULT = 0,
320 WM_REPORT_OVERRIDE = 1,
321};
322enum dtm_pstate{
323 dtm_level_p0 = 0,/*highest voltage*/
324 dtm_level_p1,
325 dtm_level_p2,
326 dtm_level_p3,
327 dtm_level_p4,/*when active_display_count = 0*/
328};
329
330enum dcn_pwr_state {
331 DCN_PWR_STATE_UNKNOWN = -1,
332 DCN_PWR_STATE_MISSION_MODE = 0,
333 DCN_PWR_STATE_LOW_POWER = 3,
334};
335
336/*
337 * For any clocks that may differ per pipe
338 * only the max is stored in this structure
339 */
340struct dc_clocks {
341 int dispclk_khz;
342 int dppclk_khz;
343 int disp_dpp_voltage_level_khz;
344 int dcfclk_khz;
345 int socclk_khz;
346 int dcfclk_deep_sleep_khz;
347 int fclk_khz;
348 int phyclk_khz;
349 int dramclk_khz;
350 bool p_state_change_support;
351 enum dcn_pwr_state pwr_state;
352 /*
353 * Elements below are not compared for the purposes of
354 * optimization required
355 */
356 bool prev_p_state_change_support;
357 enum dtm_pstate dtm_level;
358 int max_supported_dppclk_khz;
359 int max_supported_dispclk_khz;
360 int bw_dppclk_khz; /*a copy of dppclk_khz*/
361 int bw_dispclk_khz;
362};
363
364struct dc_bw_validation_profile {
365 bool enable;
366
367 unsigned long long total_ticks;
368 unsigned long long voltage_level_ticks;
369 unsigned long long watermark_ticks;
370 unsigned long long rq_dlg_ticks;
371
372 unsigned long long total_count;
373 unsigned long long skip_fast_count;
374 unsigned long long skip_pass_count;
375 unsigned long long skip_fail_count;
376};
377
378#define BW_VAL_TRACE_SETUP() \
379 unsigned long long end_tick = 0; \
380 unsigned long long voltage_level_tick = 0; \
381 unsigned long long watermark_tick = 0; \
382 unsigned long long start_tick = dc->debug.bw_val_profile.enable ? \
383 dm_get_timestamp(dc->ctx) : 0
384
385#define BW_VAL_TRACE_COUNT() \
386 if (dc->debug.bw_val_profile.enable) \
387 dc->debug.bw_val_profile.total_count++
388
389#define BW_VAL_TRACE_SKIP(status) \
390 if (dc->debug.bw_val_profile.enable) { \
391 if (!voltage_level_tick) \
392 voltage_level_tick = dm_get_timestamp(dc->ctx); \
393 dc->debug.bw_val_profile.skip_ ## status ## _count++; \
394 }
395
396#define BW_VAL_TRACE_END_VOLTAGE_LEVEL() \
397 if (dc->debug.bw_val_profile.enable) \
398 voltage_level_tick = dm_get_timestamp(dc->ctx)
399
400#define BW_VAL_TRACE_END_WATERMARKS() \
401 if (dc->debug.bw_val_profile.enable) \
402 watermark_tick = dm_get_timestamp(dc->ctx)
403
404#define BW_VAL_TRACE_FINISH() \
405 if (dc->debug.bw_val_profile.enable) { \
406 end_tick = dm_get_timestamp(dc->ctx); \
407 dc->debug.bw_val_profile.total_ticks += end_tick - start_tick; \
408 dc->debug.bw_val_profile.voltage_level_ticks += voltage_level_tick - start_tick; \
409 if (watermark_tick) { \
410 dc->debug.bw_val_profile.watermark_ticks += watermark_tick - voltage_level_tick; \
411 dc->debug.bw_val_profile.rq_dlg_ticks += end_tick - watermark_tick; \
412 } \
413 }
414
415struct dc_debug_options {
416 enum visual_confirm visual_confirm;
417 bool sanity_checks;
418 bool max_disp_clk;
419 bool surface_trace;
420 bool timing_trace;
421 bool clock_trace;
422 bool validation_trace;
423 bool bandwidth_calcs_trace;
424 int max_downscale_src_width;
425
426 /* stutter efficiency related */
427 bool disable_stutter;
428 bool use_max_lb;
429 enum dcc_option disable_dcc;
430 enum pipe_split_policy pipe_split_policy;
431 bool force_single_disp_pipe_split;
432 bool voltage_align_fclk;
433
434 bool disable_dfs_bypass;
435 bool disable_dpp_power_gate;
436 bool disable_hubp_power_gate;
437 bool disable_dsc_power_gate;
438 int dsc_min_slice_height_override;
439 int dsc_bpp_increment_div;
440 bool native422_support;
441 bool disable_pplib_wm_range;
442 enum wm_report_mode pplib_wm_report_mode;
443 unsigned int min_disp_clk_khz;
444 unsigned int min_dpp_clk_khz;
445 int sr_exit_time_dpm0_ns;
446 int sr_enter_plus_exit_time_dpm0_ns;
447 int sr_exit_time_ns;
448 int sr_enter_plus_exit_time_ns;
449 int urgent_latency_ns;
450 uint32_t underflow_assert_delay_us;
451 int percent_of_ideal_drambw;
452 int dram_clock_change_latency_ns;
453 bool optimized_watermark;
454 int always_scale;
455 bool disable_pplib_clock_request;
456 bool disable_clock_gate;
457 bool disable_mem_low_power;
458 bool disable_dmcu;
459 bool disable_psr;
460 bool force_abm_enable;
461 bool disable_stereo_support;
462 bool vsr_support;
463 bool performance_trace;
464 bool az_endpoint_mute_only;
465 bool always_use_regamma;
466 bool p010_mpo_support;
467 bool recovery_enabled;
468 bool avoid_vbios_exec_table;
469 bool scl_reset_length10;
470 bool hdmi20_disable;
471 bool skip_detection_link_training;
472 bool edid_read_retry_times;
473 bool remove_disconnect_edp;
474 unsigned int force_odm_combine; //bit vector based on otg inst
475#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
476 unsigned int force_odm_combine_4to1; //bit vector based on otg inst
477#endif
478 unsigned int force_fclk_khz;
479 bool disable_tri_buf;
480 bool dmub_offload_enabled;
481 bool dmcub_emulation;
482#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
483 bool disable_idle_power_optimizations;
484#endif
485 bool dmub_command_table; /* for testing only */
486 struct dc_bw_validation_profile bw_val_profile;
487 bool disable_fec;
488 bool disable_48mhz_pwrdwn;
489 /* This forces a hard min on the DCFCLK requested to SMU/PP
490 * watermarks are not affected.
491 */
492 unsigned int force_min_dcfclk_mhz;
493#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
494 int dwb_fi_phase;
495#endif
496 bool disable_timing_sync;
497 bool cm_in_bypass;
498 int force_clock_mode;/*every mode change.*/
499
500 bool disable_dram_clock_change_vactive_support;
501 bool validate_dml_output;
502 bool enable_dmcub_surface_flip;
503 bool usbc_combo_phy_reset_wa;
504 bool disable_dsc;
505 bool enable_dram_clock_change_one_display_vactive;
506};
507
508struct dc_debug_data {
509 uint32_t ltFailCount;
510 uint32_t i2cErrorCount;
511 uint32_t auxErrorCount;
512};
513
514struct dc_phy_addr_space_config {
515 struct {
516 uint64_t start_addr;
517 uint64_t end_addr;
518 uint64_t fb_top;
519 uint64_t fb_offset;
520 uint64_t fb_base;
521 uint64_t agp_top;
522 uint64_t agp_bot;
523 uint64_t agp_base;
524 } system_aperture;
525
526 struct {
527 uint64_t page_table_start_addr;
528 uint64_t page_table_end_addr;
529 uint64_t page_table_base_addr;
530 } gart_config;
531
532 bool valid;
533 bool is_hvm_enabled;
534 uint64_t page_table_default_page_addr;
535};
536
537struct dc_virtual_addr_space_config {
538 uint64_t page_table_base_addr;
539 uint64_t page_table_start_addr;
540 uint64_t page_table_end_addr;
541 uint32_t page_table_block_size_in_bytes;
542 uint8_t page_table_depth; // 1 = 1 level, 2 = 2 level, etc. 0 = invalid
543};
544
545struct dc_bounding_box_overrides {
546 int sr_exit_time_ns;
547 int sr_enter_plus_exit_time_ns;
548 int urgent_latency_ns;
549 int percent_of_ideal_drambw;
550 int dram_clock_change_latency_ns;
551 int dummy_clock_change_latency_ns;
552 /* This forces a hard min on the DCFCLK we use
553 * for DML. Unlike the debug option for forcing
554 * DCFCLK, this override affects watermark calculations
555 */
556 int min_dcfclk_mhz;
557};
558
559struct dc_state;
560struct resource_pool;
561struct dce_hwseq;
562struct gpu_info_soc_bounding_box_v1_0;
563struct dc {
564 struct dc_versions versions;
565 struct dc_caps caps;
566 struct dc_cap_funcs cap_funcs;
567 struct dc_config config;
568 struct dc_debug_options debug;
569 struct dc_bounding_box_overrides bb_overrides;
570 struct dc_bug_wa work_arounds;
571 struct dc_context *ctx;
572 struct dc_phy_addr_space_config vm_pa_config;
573
574 uint8_t link_count;
575 struct dc_link *links[MAX_PIPES * 2];
576
577 struct dc_state *current_state;
578 struct resource_pool *res_pool;
579
580 struct clk_mgr *clk_mgr;
581
582 /* Display Engine Clock levels */
583 struct dm_pp_clock_levels sclk_lvls;
584
585 /* Inputs into BW and WM calculations. */
586 struct bw_calcs_dceip *bw_dceip;
587 struct bw_calcs_vbios *bw_vbios;
588#ifdef CONFIG_DRM_AMD_DC_DCN
589 struct dcn_soc_bounding_box *dcn_soc;
590 struct dcn_ip_params *dcn_ip;
591 struct display_mode_lib dml;
592#endif
593
594 /* HW functions */
595 struct hw_sequencer_funcs hwss;
596 struct dce_hwseq *hwseq;
597
598 /* Require to optimize clocks and bandwidth for added/removed planes */
599 bool optimized_required;
600 bool wm_optimized_required;
601#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
602 bool idle_optimizations_allowed;
603#endif
604
605 /* Require to maintain clocks and bandwidth for UEFI enabled HW */
606 int optimize_seamless_boot_streams;
607
608 /* FBC compressor */
609 struct compressor *fbc_compressor;
610
611 struct dc_debug_data debug_data;
612 struct dpcd_vendor_signature vendor_signature;
613
614 const char *build_id;
615 struct vm_helper *vm_helper;
616 const struct gpu_info_soc_bounding_box_v1_0 *soc_bounding_box;
617};
618
619enum frame_buffer_mode {
620 FRAME_BUFFER_MODE_LOCAL_ONLY = 0,
621 FRAME_BUFFER_MODE_ZFB_ONLY,
622 FRAME_BUFFER_MODE_MIXED_ZFB_AND_LOCAL,
623} ;
624
625struct dchub_init_data {
626 int64_t zfb_phys_addr_base;
627 int64_t zfb_mc_base_addr;
628 uint64_t zfb_size_in_byte;
629 enum frame_buffer_mode fb_mode;
630 bool dchub_initialzied;
631 bool dchub_info_valid;
632};
633
634struct dc_init_data {
635 struct hw_asic_id asic_id;
636 void *driver; /* ctx */
637 struct cgs_device *cgs_device;
638 struct dc_bounding_box_overrides bb_overrides;
639
640 int num_virtual_links;
641 /*
642 * If 'vbios_override' not NULL, it will be called instead
643 * of the real VBIOS. Intended use is Diagnostics on FPGA.
644 */
645 struct dc_bios *vbios_override;
646 enum dce_environment dce_environment;
647
648 struct dmub_offload_funcs *dmub_if;
649 struct dc_reg_helper_state *dmub_offload;
650
651 struct dc_config flags;
652 uint64_t log_mask;
653
654 /**
655 * gpu_info FW provided soc bounding box struct or 0 if not
656 * available in FW
657 */
658 const struct gpu_info_soc_bounding_box_v1_0 *soc_bounding_box;
659 struct dpcd_vendor_signature vendor_signature;
660#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
661 bool force_smu_not_present;
662#endif
663};
664
665struct dc_callback_init {
666#ifdef CONFIG_DRM_AMD_DC_HDCP
667 struct cp_psp cp_psp;
668#else
669 uint8_t reserved;
670#endif
671};
672
673struct dc *dc_create(const struct dc_init_data *init_params);
674void dc_hardware_init(struct dc *dc);
675
676int dc_get_vmid_use_vector(struct dc *dc);
677void dc_setup_vm_context(struct dc *dc, struct dc_virtual_addr_space_config *va_config, int vmid);
678/* Returns the number of vmids supported */
679int dc_setup_system_context(struct dc *dc, struct dc_phy_addr_space_config *pa_config);
680void dc_init_callbacks(struct dc *dc,
681 const struct dc_callback_init *init_params);
682void dc_deinit_callbacks(struct dc *dc);
683void dc_destroy(struct dc **dc);
684
685/*******************************************************************************
686 * Surface Interfaces
687 ******************************************************************************/
688
689enum {
690 TRANSFER_FUNC_POINTS = 1025
691};
692
693struct dc_hdr_static_metadata {
694 /* display chromaticities and white point in units of 0.00001 */
695 unsigned int chromaticity_green_x;
696 unsigned int chromaticity_green_y;
697 unsigned int chromaticity_blue_x;
698 unsigned int chromaticity_blue_y;
699 unsigned int chromaticity_red_x;
700 unsigned int chromaticity_red_y;
701 unsigned int chromaticity_white_point_x;
702 unsigned int chromaticity_white_point_y;
703
704 uint32_t min_luminance;
705 uint32_t max_luminance;
706 uint32_t maximum_content_light_level;
707 uint32_t maximum_frame_average_light_level;
708};
709
710enum dc_transfer_func_type {
711 TF_TYPE_PREDEFINED,
712 TF_TYPE_DISTRIBUTED_POINTS,
713 TF_TYPE_BYPASS,
714 TF_TYPE_HWPWL
715};
716
717struct dc_transfer_func_distributed_points {
718 struct fixed31_32 red[TRANSFER_FUNC_POINTS];
719 struct fixed31_32 green[TRANSFER_FUNC_POINTS];
720 struct fixed31_32 blue[TRANSFER_FUNC_POINTS];
721
722 uint16_t end_exponent;
723 uint16_t x_point_at_y1_red;
724 uint16_t x_point_at_y1_green;
725 uint16_t x_point_at_y1_blue;
726};
727
728enum dc_transfer_func_predefined {
729 TRANSFER_FUNCTION_SRGB,
730 TRANSFER_FUNCTION_BT709,
731 TRANSFER_FUNCTION_PQ,
732 TRANSFER_FUNCTION_LINEAR,
733 TRANSFER_FUNCTION_UNITY,
734 TRANSFER_FUNCTION_HLG,
735 TRANSFER_FUNCTION_HLG12,
736 TRANSFER_FUNCTION_GAMMA22,
737 TRANSFER_FUNCTION_GAMMA24,
738 TRANSFER_FUNCTION_GAMMA26
739};
740
741
742struct dc_transfer_func {
743 struct kref refcount;
744 enum dc_transfer_func_type type;
745 enum dc_transfer_func_predefined tf;
746 /* FP16 1.0 reference level in nits, default is 80 nits, only for PQ*/
747 uint32_t sdr_ref_white_level;
748 struct dc_context *ctx;
749 union {
750 struct pwl_params pwl;
751 struct dc_transfer_func_distributed_points tf_pts;
752 };
753};
754
755
756union dc_3dlut_state {
757 struct {
758 uint32_t initialized:1; /*if 3dlut is went through color module for initialization */
759 uint32_t rmu_idx_valid:1; /*if mux settings are valid*/
760 uint32_t rmu_mux_num:3; /*index of mux to use*/
761 uint32_t mpc_rmu0_mux:4; /*select mpcc on mux, one of the following : mpcc0, mpcc1, mpcc2, mpcc3*/
762 uint32_t mpc_rmu1_mux:4;
763 uint32_t mpc_rmu2_mux:4;
764 uint32_t reserved:15;
765 } bits;
766 uint32_t raw;
767};
768
769
770struct dc_3dlut {
771 struct kref refcount;
772 struct tetrahedral_params lut_3d;
773 struct fixed31_32 hdr_multiplier;
774 union dc_3dlut_state state;
775 struct dc_context *ctx;
776};
777/*
778 * This structure is filled in by dc_surface_get_status and contains
779 * the last requested address and the currently active address so the called
780 * can determine if there are any outstanding flips
781 */
782struct dc_plane_status {
783 struct dc_plane_address requested_address;
784 struct dc_plane_address current_address;
785 bool is_flip_pending;
786 bool is_right_eye;
787};
788
789union surface_update_flags {
790
791 struct {
792 uint32_t addr_update:1;
793 /* Medium updates */
794 uint32_t dcc_change:1;
795 uint32_t color_space_change:1;
796 uint32_t horizontal_mirror_change:1;
797 uint32_t per_pixel_alpha_change:1;
798 uint32_t global_alpha_change:1;
799 uint32_t hdr_mult:1;
800 uint32_t rotation_change:1;
801 uint32_t swizzle_change:1;
802 uint32_t scaling_change:1;
803 uint32_t position_change:1;
804 uint32_t in_transfer_func_change:1;
805 uint32_t input_csc_change:1;
806 uint32_t coeff_reduction_change:1;
807 uint32_t output_tf_change:1;
808 uint32_t pixel_format_change:1;
809 uint32_t plane_size_change:1;
810 uint32_t gamut_remap_change:1;
811
812 /* Full updates */
813 uint32_t new_plane:1;
814 uint32_t bpp_change:1;
815 uint32_t gamma_change:1;
816 uint32_t bandwidth_change:1;
817 uint32_t clock_change:1;
818 uint32_t stereo_format_change:1;
819 uint32_t full_update:1;
820 } bits;
821
822 uint32_t raw;
823};
824
825struct dc_plane_state {
826 struct dc_plane_address address;
827 struct dc_plane_flip_time time;
828 bool triplebuffer_flips;
829 struct scaling_taps scaling_quality;
830 struct rect src_rect;
831 struct rect dst_rect;
832 struct rect clip_rect;
833
834 struct plane_size plane_size;
835 union dc_tiling_info tiling_info;
836
837 struct dc_plane_dcc_param dcc;
838
839 struct dc_gamma *gamma_correction;
840 struct dc_transfer_func *in_transfer_func;
841 struct dc_bias_and_scale *bias_and_scale;
842 struct dc_csc_transform input_csc_color_matrix;
843 struct fixed31_32 coeff_reduction_factor;
844 struct fixed31_32 hdr_mult;
845 struct colorspace_transform gamut_remap_matrix;
846
847 // TODO: No longer used, remove
848 struct dc_hdr_static_metadata hdr_static_ctx;
849
850 enum dc_color_space color_space;
851
852 struct dc_3dlut *lut3d_func;
853 struct dc_transfer_func *in_shaper_func;
854 struct dc_transfer_func *blend_tf;
855
856#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
857 struct dc_transfer_func *gamcor_tf;
858#endif
859 enum surface_pixel_format format;
860 enum dc_rotation_angle rotation;
861 enum plane_stereo_format stereo_format;
862
863 bool is_tiling_rotated;
864 bool per_pixel_alpha;
865 bool global_alpha;
866 int global_alpha_value;
867 bool visible;
868 bool flip_immediate;
869 bool horizontal_mirror;
870 int layer_index;
871
872 union surface_update_flags update_flags;
873 /* private to DC core */
874 struct dc_plane_status status;
875 struct dc_context *ctx;
876
877 /* HACK: Workaround for forcing full reprogramming under some conditions */
878 bool force_full_update;
879
880 /* private to dc_surface.c */
881 enum dc_irq_source irq_source;
882 struct kref refcount;
883};
884
885struct dc_plane_info {
886 struct plane_size plane_size;
887 union dc_tiling_info tiling_info;
888 struct dc_plane_dcc_param dcc;
889 enum surface_pixel_format format;
890 enum dc_rotation_angle rotation;
891 enum plane_stereo_format stereo_format;
892 enum dc_color_space color_space;
893 bool horizontal_mirror;
894 bool visible;
895 bool per_pixel_alpha;
896 bool global_alpha;
897 int global_alpha_value;
898 bool input_csc_enabled;
899 int layer_index;
900};
901
902struct dc_scaling_info {
903 struct rect src_rect;
904 struct rect dst_rect;
905 struct rect clip_rect;
906 struct scaling_taps scaling_quality;
907};
908
909struct dc_surface_update {
910 struct dc_plane_state *surface;
911
912 /* isr safe update parameters. null means no updates */
913 const struct dc_flip_addrs *flip_addr;
914 const struct dc_plane_info *plane_info;
915 const struct dc_scaling_info *scaling_info;
916 struct fixed31_32 hdr_mult;
917 /* following updates require alloc/sleep/spin that is not isr safe,
918 * null means no updates
919 */
920 const struct dc_gamma *gamma;
921 const struct dc_transfer_func *in_transfer_func;
922
923 const struct dc_csc_transform *input_csc_color_matrix;
924 const struct fixed31_32 *coeff_reduction_factor;
925 const struct dc_transfer_func *func_shaper;
926 const struct dc_3dlut *lut3d_func;
927 const struct dc_transfer_func *blend_tf;
928 const struct colorspace_transform *gamut_remap_matrix;
929};
930
931/*
932 * Create a new surface with default parameters;
933 */
934struct dc_plane_state *dc_create_plane_state(struct dc *dc);
935const struct dc_plane_status *dc_plane_get_status(
936 const struct dc_plane_state *plane_state);
937
938void dc_plane_state_retain(struct dc_plane_state *plane_state);
939void dc_plane_state_release(struct dc_plane_state *plane_state);
940
941void dc_gamma_retain(struct dc_gamma *dc_gamma);
942void dc_gamma_release(struct dc_gamma **dc_gamma);
943struct dc_gamma *dc_create_gamma(void);
944
945void dc_transfer_func_retain(struct dc_transfer_func *dc_tf);
946void dc_transfer_func_release(struct dc_transfer_func *dc_tf);
947struct dc_transfer_func *dc_create_transfer_func(void);
948
949struct dc_3dlut *dc_create_3dlut_func(void);
950void dc_3dlut_func_release(struct dc_3dlut *lut);
951void dc_3dlut_func_retain(struct dc_3dlut *lut);
952/*
953 * This structure holds a surface address. There could be multiple addresses
954 * in cases such as Stereo 3D, Planar YUV, etc. Other per-flip attributes such
955 * as frame durations and DCC format can also be set.
956 */
957struct dc_flip_addrs {
958 struct dc_plane_address address;
959 unsigned int flip_timestamp_in_us;
960 bool flip_immediate;
961 /* TODO: add flip duration for FreeSync */
962 bool triplebuffer_flips;
963};
964
965bool dc_post_update_surfaces_to_stream(
966 struct dc *dc);
967
968#include "dc_stream.h"
969
970/*
971 * Structure to store surface/stream associations for validation
972 */
973struct dc_validation_set {
974 struct dc_stream_state *stream;
975 struct dc_plane_state *plane_states[MAX_SURFACES];
976 uint8_t plane_count;
977};
978
979bool dc_validate_seamless_boot_timing(const struct dc *dc,
980 const struct dc_sink *sink,
981 struct dc_crtc_timing *crtc_timing);
982
983enum dc_status dc_validate_plane(struct dc *dc, const struct dc_plane_state *plane_state);
984
985void get_clock_requirements_for_state(struct dc_state *state, struct AsicStateEx *info);
986
987bool dc_set_generic_gpio_for_stereo(bool enable,
988 struct gpio_service *gpio_service);
989
990/*
991 * fast_validate: we return after determining if we can support the new state,
992 * but before we populate the programming info
993 */
994enum dc_status dc_validate_global_state(
995 struct dc *dc,
996 struct dc_state *new_ctx,
997 bool fast_validate);
998
999
1000void dc_resource_state_construct(
1001 const struct dc *dc,
1002 struct dc_state *dst_ctx);
1003
1004#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
1005bool dc_acquire_release_mpc_3dlut(
1006 struct dc *dc, bool acquire,
1007 struct dc_stream_state *stream,
1008 struct dc_3dlut **lut,
1009 struct dc_transfer_func **shaper);
1010#endif
1011
1012void dc_resource_state_copy_construct(
1013 const struct dc_state *src_ctx,
1014 struct dc_state *dst_ctx);
1015
1016void dc_resource_state_copy_construct_current(
1017 const struct dc *dc,
1018 struct dc_state *dst_ctx);
1019
1020void dc_resource_state_destruct(struct dc_state *context);
1021
1022bool dc_resource_is_dsc_encoding_supported(const struct dc *dc);
1023
1024/*
1025 * TODO update to make it about validation sets
1026 * Set up streams and links associated to drive sinks
1027 * The streams parameter is an absolute set of all active streams.
1028 *
1029 * After this call:
1030 * Phy, Encoder, Timing Generator are programmed and enabled.
1031 * New streams are enabled with blank stream; no memory read.
1032 */
1033bool dc_commit_state(struct dc *dc, struct dc_state *context);
1034
1035void dc_power_down_on_boot(struct dc *dc);
1036
1037struct dc_state *dc_create_state(struct dc *dc);
1038struct dc_state *dc_copy_state(struct dc_state *src_ctx);
1039void dc_retain_state(struct dc_state *context);
1040void dc_release_state(struct dc_state *context);
1041
1042/*******************************************************************************
1043 * Link Interfaces
1044 ******************************************************************************/
1045
1046struct dpcd_caps {
1047 union dpcd_rev dpcd_rev;
1048 union max_lane_count max_ln_count;
1049 union max_down_spread max_down_spread;
1050 union dprx_feature dprx_feature;
1051
1052 /* valid only for eDP v1.4 or higher*/
1053 uint8_t edp_supported_link_rates_count;
1054 enum dc_link_rate edp_supported_link_rates[8];
1055
1056 /* dongle type (DP converter, CV smart dongle) */
1057 enum display_dongle_type dongle_type;
1058 /* branch device or sink device */
1059 bool is_branch_dev;
1060 /* Dongle's downstream count. */
1061 union sink_count sink_count;
1062 /* If dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER,
1063 indicates 'Frame Sequential-to-lllFrame Pack' conversion capability.*/
1064 struct dc_dongle_caps dongle_caps;
1065
1066 uint32_t sink_dev_id;
1067 int8_t sink_dev_id_str[6];
1068 int8_t sink_hw_revision;
1069 int8_t sink_fw_revision[2];
1070
1071 uint32_t branch_dev_id;
1072 int8_t branch_dev_name[6];
1073 int8_t branch_hw_revision;
1074 int8_t branch_fw_revision[2];
1075
1076 bool allow_invalid_MSA_timing_param;
1077 bool panel_mode_edp;
1078 bool dpcd_display_control_capable;
1079 bool ext_receiver_cap_field_present;
1080 union dpcd_fec_capability fec_cap;
1081 struct dpcd_dsc_capabilities dsc_caps;
1082 struct dc_lttpr_caps lttpr_caps;
1083 struct psr_caps psr_caps;
1084
1085};
1086
1087union dpcd_sink_ext_caps {
1088 struct {
1089 /* 0 - Sink supports backlight adjust via PWM during SDR/HDR mode
1090 * 1 - Sink supports backlight adjust via AUX during SDR/HDR mode.
1091 */
1092 uint8_t sdr_aux_backlight_control : 1;
1093 uint8_t hdr_aux_backlight_control : 1;
1094 uint8_t reserved_1 : 2;
1095 uint8_t oled : 1;
1096 uint8_t reserved : 3;
1097 } bits;
1098 uint8_t raw;
1099};
1100
1101#if defined(CONFIG_DRM_AMD_DC_HDCP)
1102union hdcp_rx_caps {
1103 struct {
1104 uint8_t version;
1105 uint8_t reserved;
1106 struct {
1107 uint8_t repeater : 1;
1108 uint8_t hdcp_capable : 1;
1109 uint8_t reserved : 6;
1110 } byte0;
1111 } fields;
1112 uint8_t raw[3];
1113};
1114
1115union hdcp_bcaps {
1116 struct {
1117 uint8_t HDCP_CAPABLE:1;
1118 uint8_t REPEATER:1;
1119 uint8_t RESERVED:6;
1120 } bits;
1121 uint8_t raw;
1122};
1123
1124struct hdcp_caps {
1125 union hdcp_rx_caps rx_caps;
1126 union hdcp_bcaps bcaps;
1127};
1128#endif
1129
1130#include "dc_link.h"
1131
1132#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
1133uint32_t dc_get_opp_for_plane(struct dc *dc, struct dc_plane_state *plane);
1134
1135#endif
1136/*******************************************************************************
1137 * Sink Interfaces - A sink corresponds to a display output device
1138 ******************************************************************************/
1139
1140struct dc_container_id {
1141 // 128bit GUID in binary form
1142 unsigned char guid[16];
1143 // 8 byte port ID -> ELD.PortID
1144 unsigned int portId[2];
1145 // 128bit GUID in binary formufacturer name -> ELD.ManufacturerName
1146 unsigned short manufacturerName;
1147 // 2 byte product code -> ELD.ProductCode
1148 unsigned short productCode;
1149};
1150
1151
1152struct dc_sink_dsc_caps {
1153 // 'true' if these are virtual DPCD's DSC caps (immediately upstream of sink in MST topology),
1154 // 'false' if they are sink's DSC caps
1155 bool is_virtual_dpcd_dsc;
1156 struct dsc_dec_dpcd_caps dsc_dec_caps;
1157};
1158
1159struct dc_sink_fec_caps {
1160 bool is_rx_fec_supported;
1161 bool is_topology_fec_supported;
1162};
1163
1164/*
1165 * The sink structure contains EDID and other display device properties
1166 */
1167struct dc_sink {
1168 enum signal_type sink_signal;
1169 struct dc_edid dc_edid; /* raw edid */
1170 struct dc_edid_caps edid_caps; /* parse display caps */
1171 struct dc_container_id *dc_container_id;
1172 uint32_t dongle_max_pix_clk;
1173 void *priv;
1174 struct stereo_3d_features features_3d[TIMING_3D_FORMAT_MAX];
1175 bool converter_disable_audio;
1176 bool is_mst_legacy;
1177 struct dc_sink_dsc_caps dsc_caps;
1178 struct dc_sink_fec_caps fec_caps;
1179
1180 bool is_vsc_sdp_colorimetry_supported;
1181
1182 /* private to DC core */
1183 struct dc_link *link;
1184 struct dc_context *ctx;
1185
1186 uint32_t sink_id;
1187
1188 /* private to dc_sink.c */
1189 // refcount must be the last member in dc_sink, since we want the
1190 // sink structure to be logically cloneable up to (but not including)
1191 // refcount
1192 struct kref refcount;
1193};
1194
1195void dc_sink_retain(struct dc_sink *sink);
1196void dc_sink_release(struct dc_sink *sink);
1197
1198struct dc_sink_init_data {
1199 enum signal_type sink_signal;
1200 struct dc_link *link;
1201 uint32_t dongle_max_pix_clk;
1202 bool converter_disable_audio;
1203 bool sink_is_legacy;
1204};
1205
1206struct dc_sink *dc_sink_create(const struct dc_sink_init_data *init_params);
1207
1208/* Newer interfaces */
1209struct dc_cursor {
1210 struct dc_plane_address address;
1211 struct dc_cursor_attributes attributes;
1212};
1213
1214
1215/*******************************************************************************
1216 * Interrupt interfaces
1217 ******************************************************************************/
1218enum dc_irq_source dc_interrupt_to_irq_source(
1219 struct dc *dc,
1220 uint32_t src_id,
1221 uint32_t ext_id);
1222bool dc_interrupt_set(struct dc *dc, enum dc_irq_source src, bool enable);
1223void dc_interrupt_ack(struct dc *dc, enum dc_irq_source src);
1224enum dc_irq_source dc_get_hpd_irq_source_at_index(
1225 struct dc *dc, uint32_t link_index);
1226
1227/*******************************************************************************
1228 * Power Interfaces
1229 ******************************************************************************/
1230
1231void dc_set_power_state(
1232 struct dc *dc,
1233 enum dc_acpi_cm_power_state power_state);
1234void dc_resume(struct dc *dc);
1235
1236void dc_power_down_on_boot(struct dc *dc);
1237
1238#if defined(CONFIG_DRM_AMD_DC_HDCP)
1239/*
1240 * HDCP Interfaces
1241 */
1242enum hdcp_message_status dc_process_hdcp_msg(
1243 enum signal_type signal,
1244 struct dc_link *link,
1245 struct hdcp_protection_message *message_info);
1246#endif
1247bool dc_is_dmcu_initialized(struct dc *dc);
1248
1249enum dc_status dc_set_clock(struct dc *dc, enum dc_clock_type clock_type, uint32_t clk_khz, uint32_t stepping);
1250void dc_get_clock(struct dc *dc, enum dc_clock_type clock_type, struct dc_clock_config *clock_cfg);
1251#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
1252
1253void dc_allow_idle_optimizations(struct dc *dc, bool allow);
1254
1255/*
1256 * blank all streams, and set min and max memory clock to
1257 * lowest and highest DPM level, respectively
1258 */
1259void dc_unlock_memory_clock_frequency(struct dc *dc);
1260
1261/*
1262 * set min memory clock to the min required for current mode,
1263 * max to maxDPM, and unblank streams
1264 */
1265void dc_lock_memory_clock_frequency(struct dc *dc);
1266
1267#endif
1268/*******************************************************************************
1269 * DSC Interfaces
1270 ******************************************************************************/
1271#include "dc_dsc.h"
1272#endif /* DC_INTERFACE_H_ */
1/*
2 * Copyright 2012-2023 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26#ifndef DC_INTERFACE_H_
27#define DC_INTERFACE_H_
28
29#include "dc_types.h"
30#include "dc_state.h"
31#include "dc_plane.h"
32#include "grph_object_defs.h"
33#include "logger_types.h"
34#include "hdcp_msg_types.h"
35#include "gpio_types.h"
36#include "link_service_types.h"
37#include "grph_object_ctrl_defs.h"
38#include <inc/hw/opp.h>
39
40#include "hwss/hw_sequencer.h"
41#include "inc/compressor.h"
42#include "inc/hw/dmcu.h"
43#include "dml/display_mode_lib.h"
44
45#include "dml2/dml2_wrapper.h"
46
47#include "dmub/inc/dmub_cmd.h"
48
49#include "spl/dc_spl_types.h"
50
51struct abm_save_restore;
52
53/* forward declaration */
54struct aux_payload;
55struct set_config_cmd_payload;
56struct dmub_notification;
57
58#define DC_VER "3.2.310"
59
60#define MAX_SURFACES 4
61#define MAX_PLANES 6
62#define MAX_STREAMS 6
63#define MIN_VIEWPORT_SIZE 12
64#define MAX_NUM_EDP 2
65#define MAX_HOST_ROUTERS_NUM 2
66
67/* Display Core Interfaces */
68struct dc_versions {
69 const char *dc_ver;
70 struct dmcu_version dmcu_version;
71};
72
73enum dp_protocol_version {
74 DP_VERSION_1_4 = 0,
75 DP_VERSION_2_1,
76 DP_VERSION_UNKNOWN,
77};
78
79enum dc_plane_type {
80 DC_PLANE_TYPE_INVALID,
81 DC_PLANE_TYPE_DCE_RGB,
82 DC_PLANE_TYPE_DCE_UNDERLAY,
83 DC_PLANE_TYPE_DCN_UNIVERSAL,
84};
85
86// Sizes defined as multiples of 64KB
87enum det_size {
88 DET_SIZE_DEFAULT = 0,
89 DET_SIZE_192KB = 3,
90 DET_SIZE_256KB = 4,
91 DET_SIZE_320KB = 5,
92 DET_SIZE_384KB = 6
93};
94
95
96struct dc_plane_cap {
97 enum dc_plane_type type;
98 uint32_t per_pixel_alpha : 1;
99 struct {
100 uint32_t argb8888 : 1;
101 uint32_t nv12 : 1;
102 uint32_t fp16 : 1;
103 uint32_t p010 : 1;
104 uint32_t ayuv : 1;
105 } pixel_format_support;
106 // max upscaling factor x1000
107 // upscaling factors are always >= 1
108 // for example, 1080p -> 8K is 4.0, or 4000 raw value
109 struct {
110 uint32_t argb8888;
111 uint32_t nv12;
112 uint32_t fp16;
113 } max_upscale_factor;
114 // max downscale factor x1000
115 // downscale factors are always <= 1
116 // for example, 8K -> 1080p is 0.25, or 250 raw value
117 struct {
118 uint32_t argb8888;
119 uint32_t nv12;
120 uint32_t fp16;
121 } max_downscale_factor;
122 // minimal width/height
123 uint32_t min_width;
124 uint32_t min_height;
125};
126
127/**
128 * DOC: color-management-caps
129 *
130 * **Color management caps (DPP and MPC)**
131 *
132 * Modules/color calculates various color operations which are translated to
133 * abstracted HW. DCE 5-12 had almost no important changes, but starting with
134 * DCN1, every new generation comes with fairly major differences in color
135 * pipeline. Therefore, we abstract color pipe capabilities so modules/DM can
136 * decide mapping to HW block based on logical capabilities.
137 */
138
139/**
140 * struct rom_curve_caps - predefined transfer function caps for degamma and regamma
141 * @srgb: RGB color space transfer func
142 * @bt2020: BT.2020 transfer func
143 * @gamma2_2: standard gamma
144 * @pq: perceptual quantizer transfer function
145 * @hlg: hybrid log–gamma transfer function
146 */
147struct rom_curve_caps {
148 uint16_t srgb : 1;
149 uint16_t bt2020 : 1;
150 uint16_t gamma2_2 : 1;
151 uint16_t pq : 1;
152 uint16_t hlg : 1;
153};
154
155/**
156 * struct dpp_color_caps - color pipeline capabilities for display pipe and
157 * plane blocks
158 *
159 * @dcn_arch: all DCE generations treated the same
160 * @input_lut_shared: shared with DGAM. Input LUT is different than most LUTs,
161 * just plain 256-entry lookup
162 * @icsc: input color space conversion
163 * @dgam_ram: programmable degamma LUT
164 * @post_csc: post color space conversion, before gamut remap
165 * @gamma_corr: degamma correction
166 * @hw_3d_lut: 3D LUT support. It implies a shaper LUT before. It may be shared
167 * with MPC by setting mpc:shared_3d_lut flag
168 * @ogam_ram: programmable out/blend gamma LUT
169 * @ocsc: output color space conversion
170 * @dgam_rom_for_yuv: pre-defined degamma LUT for YUV planes
171 * @dgam_rom_caps: pre-definied curve caps for degamma 1D LUT
172 * @ogam_rom_caps: pre-definied curve caps for regamma 1D LUT
173 *
174 * Note: hdr_mult and gamut remap (CTM) are always available in DPP (in that order)
175 */
176struct dpp_color_caps {
177 uint16_t dcn_arch : 1;
178 uint16_t input_lut_shared : 1;
179 uint16_t icsc : 1;
180 uint16_t dgam_ram : 1;
181 uint16_t post_csc : 1;
182 uint16_t gamma_corr : 1;
183 uint16_t hw_3d_lut : 1;
184 uint16_t ogam_ram : 1;
185 uint16_t ocsc : 1;
186 uint16_t dgam_rom_for_yuv : 1;
187 struct rom_curve_caps dgam_rom_caps;
188 struct rom_curve_caps ogam_rom_caps;
189};
190
191/**
192 * struct mpc_color_caps - color pipeline capabilities for multiple pipe and
193 * plane combined blocks
194 *
195 * @gamut_remap: color transformation matrix
196 * @ogam_ram: programmable out gamma LUT
197 * @ocsc: output color space conversion matrix
198 * @num_3dluts: MPC 3D LUT; always assumes a preceding shaper LUT
199 * @shared_3d_lut: shared 3D LUT flag. Can be either DPP or MPC, but single
200 * instance
201 * @ogam_rom_caps: pre-definied curve caps for regamma 1D LUT
202 */
203struct mpc_color_caps {
204 uint16_t gamut_remap : 1;
205 uint16_t ogam_ram : 1;
206 uint16_t ocsc : 1;
207 uint16_t num_3dluts : 3;
208 uint16_t shared_3d_lut:1;
209 struct rom_curve_caps ogam_rom_caps;
210};
211
212/**
213 * struct dc_color_caps - color pipes capabilities for DPP and MPC hw blocks
214 * @dpp: color pipes caps for DPP
215 * @mpc: color pipes caps for MPC
216 */
217struct dc_color_caps {
218 struct dpp_color_caps dpp;
219 struct mpc_color_caps mpc;
220};
221
222struct dc_dmub_caps {
223 bool psr;
224 bool mclk_sw;
225 bool subvp_psr;
226 bool gecc_enable;
227 uint8_t fams_ver;
228 bool aux_backlight_support;
229};
230
231struct dc_scl_caps {
232 bool sharpener_support;
233};
234
235struct dc_caps {
236 uint32_t max_streams;
237 uint32_t max_links;
238 uint32_t max_audios;
239 uint32_t max_slave_planes;
240 uint32_t max_slave_yuv_planes;
241 uint32_t max_slave_rgb_planes;
242 uint32_t max_planes;
243 uint32_t max_downscale_ratio;
244 uint32_t i2c_speed_in_khz;
245 uint32_t i2c_speed_in_khz_hdcp;
246 uint32_t dmdata_alloc_size;
247 unsigned int max_cursor_size;
248 unsigned int max_video_width;
249 /*
250 * max video plane width that can be safely assumed to be always
251 * supported by single DPP pipe.
252 */
253 unsigned int max_optimizable_video_width;
254 unsigned int min_horizontal_blanking_period;
255 int linear_pitch_alignment;
256 bool dcc_const_color;
257 bool dynamic_audio;
258 bool is_apu;
259 bool dual_link_dvi;
260 bool post_blend_color_processing;
261 bool force_dp_tps4_for_cp2520;
262 bool disable_dp_clk_share;
263 bool psp_setup_panel_mode;
264 bool extended_aux_timeout_support;
265 bool dmcub_support;
266 bool zstate_support;
267 bool ips_support;
268 uint32_t num_of_internal_disp;
269 enum dp_protocol_version max_dp_protocol_version;
270 unsigned int mall_size_per_mem_channel;
271 unsigned int mall_size_total;
272 unsigned int cursor_cache_size;
273 struct dc_plane_cap planes[MAX_PLANES];
274 struct dc_color_caps color;
275 struct dc_dmub_caps dmub_caps;
276 bool dp_hpo;
277 bool dp_hdmi21_pcon_support;
278 bool edp_dsc_support;
279 bool vbios_lttpr_aware;
280 bool vbios_lttpr_enable;
281 uint32_t max_otg_num;
282 uint32_t max_cab_allocation_bytes;
283 uint32_t cache_line_size;
284 uint32_t cache_num_ways;
285 uint16_t subvp_fw_processing_delay_us;
286 uint8_t subvp_drr_max_vblank_margin_us;
287 uint16_t subvp_prefetch_end_to_mall_start_us;
288 uint8_t subvp_swath_height_margin_lines; // subvp start line must be aligned to 2 x swath height
289 uint16_t subvp_pstate_allow_width_us;
290 uint16_t subvp_vertical_int_margin_us;
291 bool seamless_odm;
292 uint32_t max_v_total;
293 bool vtotal_limited_by_fp2;
294 uint32_t max_disp_clock_khz_at_vmin;
295 uint8_t subvp_drr_vblank_start_margin_us;
296 bool cursor_not_scaled;
297 bool dcmode_power_limits_present;
298 bool sequential_ono;
299 /* Conservative limit for DCC cases which require ODM4:1 to support*/
300 uint32_t dcc_plane_width_limit;
301 struct dc_scl_caps scl_caps;
302};
303
304struct dc_bug_wa {
305 bool no_connect_phy_config;
306 bool dedcn20_305_wa;
307 bool skip_clock_update;
308 bool lt_early_cr_pattern;
309 struct {
310 uint8_t uclk : 1;
311 uint8_t fclk : 1;
312 uint8_t dcfclk : 1;
313 uint8_t dcfclk_ds: 1;
314 } clock_update_disable_mask;
315 bool skip_psr_ips_crtc_disable;
316};
317struct dc_dcc_surface_param {
318 struct dc_size surface_size;
319 enum surface_pixel_format format;
320 unsigned int plane0_pitch;
321 struct dc_size plane1_size;
322 unsigned int plane1_pitch;
323 union {
324 enum swizzle_mode_values swizzle_mode;
325 enum swizzle_mode_addr3_values swizzle_mode_addr3;
326 };
327 enum dc_scan_direction scan;
328};
329
330struct dc_dcc_setting {
331 unsigned int max_compressed_blk_size;
332 unsigned int max_uncompressed_blk_size;
333 bool independent_64b_blks;
334 //These bitfields to be used starting with DCN 3.0
335 struct {
336 uint32_t dcc_256_64_64 : 1;//available in ASICs before DCN 3.0 (the worst compression case)
337 uint32_t dcc_128_128_uncontrained : 1; //available in ASICs before DCN 3.0
338 uint32_t dcc_256_128_128 : 1; //available starting with DCN 3.0
339 uint32_t dcc_256_256_unconstrained : 1; //available in ASICs before DCN 3.0 (the best compression case)
340 uint32_t dcc_256_256 : 1; //available in ASICs starting with DCN 4.0x (the best compression case)
341 uint32_t dcc_256_128 : 1; //available in ASICs starting with DCN 4.0x
342 uint32_t dcc_256_64 : 1; //available in ASICs starting with DCN 4.0x (the worst compression case)
343 } dcc_controls;
344};
345
346struct dc_surface_dcc_cap {
347 union {
348 struct {
349 struct dc_dcc_setting rgb;
350 } grph;
351
352 struct {
353 struct dc_dcc_setting luma;
354 struct dc_dcc_setting chroma;
355 } video;
356 };
357
358 bool capable;
359 bool const_color_support;
360};
361
362struct dc_static_screen_params {
363 struct {
364 bool force_trigger;
365 bool cursor_update;
366 bool surface_update;
367 bool overlay_update;
368 } triggers;
369 unsigned int num_frames;
370};
371
372
373/* Surface update type is used by dc_update_surfaces_and_stream
374 * The update type is determined at the very beginning of the function based
375 * on parameters passed in and decides how much programming (or updating) is
376 * going to be done during the call.
377 *
378 * UPDATE_TYPE_FAST is used for really fast updates that do not require much
379 * logical calculations or hardware register programming. This update MUST be
380 * ISR safe on windows. Currently fast update will only be used to flip surface
381 * address.
382 *
383 * UPDATE_TYPE_MED is used for slower updates which require significant hw
384 * re-programming however do not affect bandwidth consumption or clock
385 * requirements. At present, this is the level at which front end updates
386 * that do not require us to run bw_calcs happen. These are in/out transfer func
387 * updates, viewport offset changes, recout size changes and pixel depth changes.
388 * This update can be done at ISR, but we want to minimize how often this happens.
389 *
390 * UPDATE_TYPE_FULL is slow. Really slow. This requires us to recalculate our
391 * bandwidth and clocks, possibly rearrange some pipes and reprogram anything front
392 * end related. Any time viewport dimensions, recout dimensions, scaling ratios or
393 * gamma need to be adjusted or pipe needs to be turned on (or disconnected) we do
394 * a full update. This cannot be done at ISR level and should be a rare event.
395 * Unless someone is stress testing mpo enter/exit, playing with colour or adjusting
396 * underscan we don't expect to see this call at all.
397 */
398
399enum surface_update_type {
400 UPDATE_TYPE_FAST, /* super fast, safe to execute in isr */
401 UPDATE_TYPE_MED, /* ISR safe, most of programming needed, no bw/clk change*/
402 UPDATE_TYPE_FULL, /* may need to shuffle resources */
403};
404
405/* Forward declaration*/
406struct dc;
407struct dc_plane_state;
408struct dc_state;
409
410struct dc_cap_funcs {
411 bool (*get_dcc_compression_cap)(const struct dc *dc,
412 const struct dc_dcc_surface_param *input,
413 struct dc_surface_dcc_cap *output);
414 bool (*get_subvp_en)(struct dc *dc, struct dc_state *context);
415};
416
417struct link_training_settings;
418
419union allow_lttpr_non_transparent_mode {
420 struct {
421 bool DP1_4A : 1;
422 bool DP2_0 : 1;
423 } bits;
424 unsigned char raw;
425};
426
427/* Structure to hold configuration flags set by dm at dc creation. */
428struct dc_config {
429 bool gpu_vm_support;
430 bool disable_disp_pll_sharing;
431 bool fbc_support;
432 bool disable_fractional_pwm;
433 bool allow_seamless_boot_optimization;
434 bool seamless_boot_edp_requested;
435 bool edp_not_connected;
436 bool edp_no_power_sequencing;
437 bool force_enum_edp;
438 bool forced_clocks;
439 union allow_lttpr_non_transparent_mode allow_lttpr_non_transparent_mode;
440 bool multi_mon_pp_mclk_switch;
441 bool disable_dmcu;
442 bool enable_4to1MPC;
443 bool enable_windowed_mpo_odm;
444 bool forceHBR2CP2520; // Used for switching between test patterns TPS4 and CP2520
445 uint32_t allow_edp_hotplug_detection;
446 bool clamp_min_dcfclk;
447 uint64_t vblank_alignment_dto_params;
448 uint8_t vblank_alignment_max_frame_time_diff;
449 bool is_asymmetric_memory;
450 bool is_single_rank_dimm;
451 bool is_vmin_only_asic;
452 bool use_spl;
453 bool prefer_easf;
454 bool use_pipe_ctx_sync_logic;
455 bool ignore_dpref_ss;
456 bool enable_mipi_converter_optimization;
457 bool use_default_clock_table;
458 bool force_bios_enable_lttpr;
459 uint8_t force_bios_fixed_vs;
460 int sdpif_request_limit_words_per_umc;
461 bool dc_mode_clk_limit_support;
462 bool EnableMinDispClkODM;
463 bool enable_auto_dpm_test_logs;
464 unsigned int disable_ips;
465 unsigned int disable_ips_in_vpb;
466 bool usb4_bw_alloc_support;
467 bool allow_0_dtb_clk;
468 bool use_assr_psp_message;
469 bool support_edp0_on_dp1;
470 unsigned int enable_fpo_flicker_detection;
471 bool disable_hbr_audio_dp2;
472 bool consolidated_dpia_dp_lt;
473 bool set_pipe_unlock_order;
474};
475
476enum visual_confirm {
477 VISUAL_CONFIRM_DISABLE = 0,
478 VISUAL_CONFIRM_SURFACE = 1,
479 VISUAL_CONFIRM_HDR = 2,
480 VISUAL_CONFIRM_MPCTREE = 4,
481 VISUAL_CONFIRM_PSR = 5,
482 VISUAL_CONFIRM_SWAPCHAIN = 6,
483 VISUAL_CONFIRM_FAMS = 7,
484 VISUAL_CONFIRM_SWIZZLE = 9,
485 VISUAL_CONFIRM_REPLAY = 12,
486 VISUAL_CONFIRM_SUBVP = 14,
487 VISUAL_CONFIRM_MCLK_SWITCH = 16,
488 VISUAL_CONFIRM_FAMS2 = 19,
489 VISUAL_CONFIRM_HW_CURSOR = 20,
490};
491
492enum dc_psr_power_opts {
493 psr_power_opt_invalid = 0x0,
494 psr_power_opt_smu_opt_static_screen = 0x1,
495 psr_power_opt_z10_static_screen = 0x10,
496 psr_power_opt_ds_disable_allow = 0x100,
497};
498
499enum dml_hostvm_override_opts {
500 DML_HOSTVM_NO_OVERRIDE = 0x0,
501 DML_HOSTVM_OVERRIDE_FALSE = 0x1,
502 DML_HOSTVM_OVERRIDE_TRUE = 0x2,
503};
504
505enum dc_replay_power_opts {
506 replay_power_opt_invalid = 0x0,
507 replay_power_opt_smu_opt_static_screen = 0x1,
508 replay_power_opt_z10_static_screen = 0x10,
509};
510
511enum dcc_option {
512 DCC_ENABLE = 0,
513 DCC_DISABLE = 1,
514 DCC_HALF_REQ_DISALBE = 2,
515};
516
517enum in_game_fams_config {
518 INGAME_FAMS_SINGLE_DISP_ENABLE, // enable in-game fams
519 INGAME_FAMS_DISABLE, // disable in-game fams
520 INGAME_FAMS_MULTI_DISP_ENABLE, //enable in-game fams for multi-display
521 INGAME_FAMS_MULTI_DISP_CLAMPED_ONLY, //enable in-game fams for multi-display only for clamped RR strategies
522};
523
524/**
525 * enum pipe_split_policy - Pipe split strategy supported by DCN
526 *
527 * This enum is used to define the pipe split policy supported by DCN. By
528 * default, DC favors MPC_SPLIT_DYNAMIC.
529 */
530enum pipe_split_policy {
531 /**
532 * @MPC_SPLIT_DYNAMIC: DC will automatically decide how to split the
533 * pipe in order to bring the best trade-off between performance and
534 * power consumption. This is the recommended option.
535 */
536 MPC_SPLIT_DYNAMIC = 0,
537
538 /**
539 * @MPC_SPLIT_AVOID: Avoid pipe split, which means that DC will not
540 * try any sort of split optimization.
541 */
542 MPC_SPLIT_AVOID = 1,
543
544 /**
545 * @MPC_SPLIT_AVOID_MULT_DISP: With this option, DC will only try to
546 * optimize the pipe utilization when using a single display; if the
547 * user connects to a second display, DC will avoid pipe split.
548 */
549 MPC_SPLIT_AVOID_MULT_DISP = 2,
550};
551
552enum wm_report_mode {
553 WM_REPORT_DEFAULT = 0,
554 WM_REPORT_OVERRIDE = 1,
555};
556enum dtm_pstate{
557 dtm_level_p0 = 0,/*highest voltage*/
558 dtm_level_p1,
559 dtm_level_p2,
560 dtm_level_p3,
561 dtm_level_p4,/*when active_display_count = 0*/
562};
563
564enum dcn_pwr_state {
565 DCN_PWR_STATE_UNKNOWN = -1,
566 DCN_PWR_STATE_MISSION_MODE = 0,
567 DCN_PWR_STATE_LOW_POWER = 3,
568};
569
570enum dcn_zstate_support_state {
571 DCN_ZSTATE_SUPPORT_UNKNOWN,
572 DCN_ZSTATE_SUPPORT_ALLOW,
573 DCN_ZSTATE_SUPPORT_ALLOW_Z8_ONLY,
574 DCN_ZSTATE_SUPPORT_ALLOW_Z8_Z10_ONLY,
575 DCN_ZSTATE_SUPPORT_ALLOW_Z10_ONLY,
576 DCN_ZSTATE_SUPPORT_DISALLOW,
577};
578
579/*
580 * struct dc_clocks - DC pipe clocks
581 *
582 * For any clocks that may differ per pipe only the max is stored in this
583 * structure
584 */
585struct dc_clocks {
586 int dispclk_khz;
587 int actual_dispclk_khz;
588 int dppclk_khz;
589 int actual_dppclk_khz;
590 int disp_dpp_voltage_level_khz;
591 int dcfclk_khz;
592 int socclk_khz;
593 int dcfclk_deep_sleep_khz;
594 int fclk_khz;
595 int phyclk_khz;
596 int dramclk_khz;
597 bool p_state_change_support;
598 enum dcn_zstate_support_state zstate_support;
599 bool dtbclk_en;
600 int ref_dtbclk_khz;
601 bool fclk_p_state_change_support;
602 enum dcn_pwr_state pwr_state;
603 /*
604 * Elements below are not compared for the purposes of
605 * optimization required
606 */
607 bool prev_p_state_change_support;
608 bool fclk_prev_p_state_change_support;
609 int num_ways;
610 int host_router_bw_kbps[MAX_HOST_ROUTERS_NUM];
611
612 /*
613 * @fw_based_mclk_switching
614 *
615 * DC has a mechanism that leverage the variable refresh rate to switch
616 * memory clock in cases that we have a large latency to achieve the
617 * memory clock change and a short vblank window. DC has some
618 * requirements to enable this feature, and this field describes if the
619 * system support or not such a feature.
620 */
621 bool fw_based_mclk_switching;
622 bool fw_based_mclk_switching_shut_down;
623 int prev_num_ways;
624 enum dtm_pstate dtm_level;
625 int max_supported_dppclk_khz;
626 int max_supported_dispclk_khz;
627 int bw_dppclk_khz; /*a copy of dppclk_khz*/
628 int bw_dispclk_khz;
629 int idle_dramclk_khz;
630 int idle_fclk_khz;
631};
632
633struct dc_bw_validation_profile {
634 bool enable;
635
636 unsigned long long total_ticks;
637 unsigned long long voltage_level_ticks;
638 unsigned long long watermark_ticks;
639 unsigned long long rq_dlg_ticks;
640
641 unsigned long long total_count;
642 unsigned long long skip_fast_count;
643 unsigned long long skip_pass_count;
644 unsigned long long skip_fail_count;
645};
646
647#define BW_VAL_TRACE_SETUP() \
648 unsigned long long end_tick = 0; \
649 unsigned long long voltage_level_tick = 0; \
650 unsigned long long watermark_tick = 0; \
651 unsigned long long start_tick = dc->debug.bw_val_profile.enable ? \
652 dm_get_timestamp(dc->ctx) : 0
653
654#define BW_VAL_TRACE_COUNT() \
655 if (dc->debug.bw_val_profile.enable) \
656 dc->debug.bw_val_profile.total_count++
657
658#define BW_VAL_TRACE_SKIP(status) \
659 if (dc->debug.bw_val_profile.enable) { \
660 if (!voltage_level_tick) \
661 voltage_level_tick = dm_get_timestamp(dc->ctx); \
662 dc->debug.bw_val_profile.skip_ ## status ## _count++; \
663 }
664
665#define BW_VAL_TRACE_END_VOLTAGE_LEVEL() \
666 if (dc->debug.bw_val_profile.enable) \
667 voltage_level_tick = dm_get_timestamp(dc->ctx)
668
669#define BW_VAL_TRACE_END_WATERMARKS() \
670 if (dc->debug.bw_val_profile.enable) \
671 watermark_tick = dm_get_timestamp(dc->ctx)
672
673#define BW_VAL_TRACE_FINISH() \
674 if (dc->debug.bw_val_profile.enable) { \
675 end_tick = dm_get_timestamp(dc->ctx); \
676 dc->debug.bw_val_profile.total_ticks += end_tick - start_tick; \
677 dc->debug.bw_val_profile.voltage_level_ticks += voltage_level_tick - start_tick; \
678 if (watermark_tick) { \
679 dc->debug.bw_val_profile.watermark_ticks += watermark_tick - voltage_level_tick; \
680 dc->debug.bw_val_profile.rq_dlg_ticks += end_tick - watermark_tick; \
681 } \
682 }
683
684union mem_low_power_enable_options {
685 struct {
686 bool vga: 1;
687 bool i2c: 1;
688 bool dmcu: 1;
689 bool dscl: 1;
690 bool cm: 1;
691 bool mpc: 1;
692 bool optc: 1;
693 bool vpg: 1;
694 bool afmt: 1;
695 } bits;
696 uint32_t u32All;
697};
698
699union root_clock_optimization_options {
700 struct {
701 bool dpp: 1;
702 bool dsc: 1;
703 bool hdmistream: 1;
704 bool hdmichar: 1;
705 bool dpstream: 1;
706 bool symclk32_se: 1;
707 bool symclk32_le: 1;
708 bool symclk_fe: 1;
709 bool physymclk: 1;
710 bool dpiasymclk: 1;
711 uint32_t reserved: 22;
712 } bits;
713 uint32_t u32All;
714};
715
716union fine_grain_clock_gating_enable_options {
717 struct {
718 bool dccg_global_fgcg_rep : 1; /* Global fine grain clock gating of repeaters */
719 bool dchub : 1; /* Display controller hub */
720 bool dchubbub : 1;
721 bool dpp : 1; /* Display pipes and planes */
722 bool opp : 1; /* Output pixel processing */
723 bool optc : 1; /* Output pipe timing combiner */
724 bool dio : 1; /* Display output */
725 bool dwb : 1; /* Display writeback */
726 bool mmhubbub : 1; /* Multimedia hub */
727 bool dmu : 1; /* Display core management unit */
728 bool az : 1; /* Azalia */
729 bool dchvm : 1;
730 bool dsc : 1; /* Display stream compression */
731
732 uint32_t reserved : 19;
733 } bits;
734 uint32_t u32All;
735};
736
737enum pg_hw_pipe_resources {
738 PG_HUBP = 0,
739 PG_DPP,
740 PG_DSC,
741 PG_MPCC,
742 PG_OPP,
743 PG_OPTC,
744 PG_DPSTREAM,
745 PG_HDMISTREAM,
746 PG_PHYSYMCLK,
747 PG_HW_PIPE_RESOURCES_NUM_ELEMENT
748};
749
750enum pg_hw_resources {
751 PG_DCCG = 0,
752 PG_DCIO,
753 PG_DIO,
754 PG_DCHUBBUB,
755 PG_DCHVM,
756 PG_DWB,
757 PG_HPO,
758 PG_HW_RESOURCES_NUM_ELEMENT
759};
760
761struct pg_block_update {
762 bool pg_pipe_res_update[PG_HW_PIPE_RESOURCES_NUM_ELEMENT][MAX_PIPES];
763 bool pg_res_update[PG_HW_RESOURCES_NUM_ELEMENT];
764};
765
766union dpia_debug_options {
767 struct {
768 uint32_t disable_dpia:1; /* bit 0 */
769 uint32_t force_non_lttpr:1; /* bit 1 */
770 uint32_t extend_aux_rd_interval:1; /* bit 2 */
771 uint32_t disable_mst_dsc_work_around:1; /* bit 3 */
772 uint32_t enable_force_tbt3_work_around:1; /* bit 4 */
773 uint32_t disable_usb4_pm_support:1; /* bit 5 */
774 uint32_t enable_consolidated_dpia_dp_lt:1; /* bit 6 */
775 uint32_t reserved:25;
776 } bits;
777 uint32_t raw;
778};
779
780/* AUX wake work around options
781 * 0: enable/disable work around
782 * 1: use default timeout LINK_AUX_WAKE_TIMEOUT_MS
783 * 15-2: reserved
784 * 31-16: timeout in ms
785 */
786union aux_wake_wa_options {
787 struct {
788 uint32_t enable_wa : 1;
789 uint32_t use_default_timeout : 1;
790 uint32_t rsvd: 14;
791 uint32_t timeout_ms : 16;
792 } bits;
793 uint32_t raw;
794};
795
796struct dc_debug_data {
797 uint32_t ltFailCount;
798 uint32_t i2cErrorCount;
799 uint32_t auxErrorCount;
800};
801
802struct dc_phy_addr_space_config {
803 struct {
804 uint64_t start_addr;
805 uint64_t end_addr;
806 uint64_t fb_top;
807 uint64_t fb_offset;
808 uint64_t fb_base;
809 uint64_t agp_top;
810 uint64_t agp_bot;
811 uint64_t agp_base;
812 } system_aperture;
813
814 struct {
815 uint64_t page_table_start_addr;
816 uint64_t page_table_end_addr;
817 uint64_t page_table_base_addr;
818 bool base_addr_is_mc_addr;
819 } gart_config;
820
821 bool valid;
822 bool is_hvm_enabled;
823 uint64_t page_table_default_page_addr;
824};
825
826struct dc_virtual_addr_space_config {
827 uint64_t page_table_base_addr;
828 uint64_t page_table_start_addr;
829 uint64_t page_table_end_addr;
830 uint32_t page_table_block_size_in_bytes;
831 uint8_t page_table_depth; // 1 = 1 level, 2 = 2 level, etc. 0 = invalid
832};
833
834struct dc_bounding_box_overrides {
835 int sr_exit_time_ns;
836 int sr_enter_plus_exit_time_ns;
837 int sr_exit_z8_time_ns;
838 int sr_enter_plus_exit_z8_time_ns;
839 int urgent_latency_ns;
840 int percent_of_ideal_drambw;
841 int dram_clock_change_latency_ns;
842 int dummy_clock_change_latency_ns;
843 int fclk_clock_change_latency_ns;
844 /* This forces a hard min on the DCFCLK we use
845 * for DML. Unlike the debug option for forcing
846 * DCFCLK, this override affects watermark calculations
847 */
848 int min_dcfclk_mhz;
849};
850
851struct dc_state;
852struct resource_pool;
853struct dce_hwseq;
854struct link_service;
855
856/*
857 * struct dc_debug_options - DC debug struct
858 *
859 * This struct provides a simple mechanism for developers to change some
860 * configurations, enable/disable features, and activate extra debug options.
861 * This can be very handy to narrow down whether some specific feature is
862 * causing an issue or not.
863 */
864struct dc_debug_options {
865 bool native422_support;
866 bool disable_dsc;
867 enum visual_confirm visual_confirm;
868 int visual_confirm_rect_height;
869
870 bool sanity_checks;
871 bool max_disp_clk;
872 bool surface_trace;
873 bool clock_trace;
874 bool validation_trace;
875 bool bandwidth_calcs_trace;
876 int max_downscale_src_width;
877
878 /* stutter efficiency related */
879 bool disable_stutter;
880 bool use_max_lb;
881 enum dcc_option disable_dcc;
882
883 /*
884 * @pipe_split_policy: Define which pipe split policy is used by the
885 * display core.
886 */
887 enum pipe_split_policy pipe_split_policy;
888 bool force_single_disp_pipe_split;
889 bool voltage_align_fclk;
890 bool disable_min_fclk;
891
892 bool disable_dfs_bypass;
893 bool disable_dpp_power_gate;
894 bool disable_hubp_power_gate;
895 bool disable_dsc_power_gate;
896 bool disable_optc_power_gate;
897 bool disable_hpo_power_gate;
898 int dsc_min_slice_height_override;
899 int dsc_bpp_increment_div;
900 bool disable_pplib_wm_range;
901 enum wm_report_mode pplib_wm_report_mode;
902 unsigned int min_disp_clk_khz;
903 unsigned int min_dpp_clk_khz;
904 unsigned int min_dram_clk_khz;
905 int sr_exit_time_dpm0_ns;
906 int sr_enter_plus_exit_time_dpm0_ns;
907 int sr_exit_time_ns;
908 int sr_enter_plus_exit_time_ns;
909 int sr_exit_z8_time_ns;
910 int sr_enter_plus_exit_z8_time_ns;
911 int urgent_latency_ns;
912 uint32_t underflow_assert_delay_us;
913 int percent_of_ideal_drambw;
914 int dram_clock_change_latency_ns;
915 bool optimized_watermark;
916 int always_scale;
917 bool disable_pplib_clock_request;
918 bool disable_clock_gate;
919 bool disable_mem_low_power;
920 bool pstate_enabled;
921 bool disable_dmcu;
922 bool force_abm_enable;
923 bool disable_stereo_support;
924 bool vsr_support;
925 bool performance_trace;
926 bool az_endpoint_mute_only;
927 bool always_use_regamma;
928 bool recovery_enabled;
929 bool avoid_vbios_exec_table;
930 bool scl_reset_length10;
931 bool hdmi20_disable;
932 bool skip_detection_link_training;
933 uint32_t edid_read_retry_times;
934 unsigned int force_odm_combine; //bit vector based on otg inst
935 unsigned int seamless_boot_odm_combine;
936 unsigned int force_odm_combine_4to1; //bit vector based on otg inst
937 int minimum_z8_residency_time;
938 int minimum_z10_residency_time;
939 bool disable_z9_mpc;
940 unsigned int force_fclk_khz;
941 bool enable_tri_buf;
942 bool ips_disallow_entry;
943 bool dmub_offload_enabled;
944 bool dmcub_emulation;
945 bool disable_idle_power_optimizations;
946 unsigned int mall_size_override;
947 unsigned int mall_additional_timer_percent;
948 bool mall_error_as_fatal;
949 bool dmub_command_table; /* for testing only */
950 struct dc_bw_validation_profile bw_val_profile;
951 bool disable_fec;
952 bool disable_48mhz_pwrdwn;
953 /* This forces a hard min on the DCFCLK requested to SMU/PP
954 * watermarks are not affected.
955 */
956 unsigned int force_min_dcfclk_mhz;
957 int dwb_fi_phase;
958 bool disable_timing_sync;
959 bool cm_in_bypass;
960 int force_clock_mode;/*every mode change.*/
961
962 bool disable_dram_clock_change_vactive_support;
963 bool validate_dml_output;
964 bool enable_dmcub_surface_flip;
965 bool usbc_combo_phy_reset_wa;
966 bool enable_dram_clock_change_one_display_vactive;
967 /* TODO - remove once tested */
968 bool legacy_dp2_lt;
969 bool set_mst_en_for_sst;
970 bool disable_uhbr;
971 bool force_dp2_lt_fallback_method;
972 bool ignore_cable_id;
973 union mem_low_power_enable_options enable_mem_low_power;
974 union root_clock_optimization_options root_clock_optimization;
975 union fine_grain_clock_gating_enable_options enable_fine_grain_clock_gating;
976 bool hpo_optimization;
977 bool force_vblank_alignment;
978
979 /* Enable dmub aux for legacy ddc */
980 bool enable_dmub_aux_for_legacy_ddc;
981 bool disable_fams;
982 enum in_game_fams_config disable_fams_gaming;
983 /* FEC/PSR1 sequence enable delay in 100us */
984 uint8_t fec_enable_delay_in100us;
985 bool enable_driver_sequence_debug;
986 enum det_size crb_alloc_policy;
987 int crb_alloc_policy_min_disp_count;
988 bool disable_z10;
989 bool enable_z9_disable_interface;
990 bool psr_skip_crtc_disable;
991 uint32_t ips_skip_crtc_disable_mask;
992 union dpia_debug_options dpia_debug;
993 bool disable_fixed_vs_aux_timeout_wa;
994 uint32_t fixed_vs_aux_delay_config_wa;
995 bool force_disable_subvp;
996 bool force_subvp_mclk_switch;
997 bool allow_sw_cursor_fallback;
998 unsigned int force_subvp_num_ways;
999 unsigned int force_mall_ss_num_ways;
1000 bool alloc_extra_way_for_cursor;
1001 uint32_t subvp_extra_lines;
1002 bool force_usr_allow;
1003 /* uses value at boot and disables switch */
1004 bool disable_dtb_ref_clk_switch;
1005 bool extended_blank_optimization;
1006 union aux_wake_wa_options aux_wake_wa;
1007 uint32_t mst_start_top_delay;
1008 uint8_t psr_power_use_phy_fsm;
1009 enum dml_hostvm_override_opts dml_hostvm_override;
1010 bool dml_disallow_alternate_prefetch_modes;
1011 bool use_legacy_soc_bb_mechanism;
1012 bool exit_idle_opt_for_cursor_updates;
1013 bool using_dml2;
1014 bool enable_single_display_2to1_odm_policy;
1015 bool enable_double_buffered_dsc_pg_support;
1016 bool enable_dp_dig_pixel_rate_div_policy;
1017 bool using_dml21;
1018 enum lttpr_mode lttpr_mode_override;
1019 unsigned int dsc_delay_factor_wa_x1000;
1020 unsigned int min_prefetch_in_strobe_ns;
1021 bool disable_unbounded_requesting;
1022 bool dig_fifo_off_in_blank;
1023 bool override_dispclk_programming;
1024 bool otg_crc_db;
1025 bool disallow_dispclk_dppclk_ds;
1026 bool disable_fpo_optimizations;
1027 bool support_eDP1_5;
1028 uint32_t fpo_vactive_margin_us;
1029 bool disable_fpo_vactive;
1030 bool disable_boot_optimizations;
1031 bool override_odm_optimization;
1032 bool minimize_dispclk_using_odm;
1033 bool disable_subvp_high_refresh;
1034 bool disable_dp_plus_plus_wa;
1035 uint32_t fpo_vactive_min_active_margin_us;
1036 uint32_t fpo_vactive_max_blank_us;
1037 bool enable_hpo_pg_support;
1038 bool enable_legacy_fast_update;
1039 bool disable_dc_mode_overwrite;
1040 bool replay_skip_crtc_disabled;
1041 bool ignore_pg;/*do nothing, let pmfw control it*/
1042 bool psp_disabled_wa;
1043 unsigned int ips2_eval_delay_us;
1044 unsigned int ips2_entry_delay_us;
1045 bool optimize_ips_handshake;
1046 bool disable_dmub_reallow_idle;
1047 bool disable_timeout;
1048 bool disable_extblankadj;
1049 bool enable_idle_reg_checks;
1050 unsigned int static_screen_wait_frames;
1051 uint32_t pwm_freq;
1052 bool force_chroma_subsampling_1tap;
1053 unsigned int dcc_meta_propagation_delay_us;
1054 bool disable_422_left_edge_pixel;
1055 bool dml21_force_pstate_method;
1056 uint32_t dml21_force_pstate_method_values[MAX_PIPES];
1057 uint32_t dml21_disable_pstate_method_mask;
1058 union dmub_fams2_global_feature_config fams2_config;
1059 bool enable_legacy_clock_update;
1060 unsigned int force_cositing;
1061 unsigned int disable_spl;
1062 unsigned int force_easf;
1063 unsigned int force_sharpness;
1064 unsigned int force_sharpness_level;
1065 unsigned int force_lls;
1066 bool notify_dpia_hr_bw;
1067 bool enable_ips_visual_confirm;
1068 unsigned int sharpen_policy;
1069 unsigned int scale_to_sharpness_policy;
1070 bool skip_full_updated_if_possible;
1071 unsigned int enable_oled_edp_power_up_opt;
1072 bool enable_hblank_borrow;
1073};
1074
1075
1076/* Generic structure that can be used to query properties of DC. More fields
1077 * can be added as required.
1078 */
1079struct dc_current_properties {
1080 unsigned int cursor_size_limit;
1081};
1082
1083enum frame_buffer_mode {
1084 FRAME_BUFFER_MODE_LOCAL_ONLY = 0,
1085 FRAME_BUFFER_MODE_ZFB_ONLY,
1086 FRAME_BUFFER_MODE_MIXED_ZFB_AND_LOCAL,
1087} ;
1088
1089struct dchub_init_data {
1090 int64_t zfb_phys_addr_base;
1091 int64_t zfb_mc_base_addr;
1092 uint64_t zfb_size_in_byte;
1093 enum frame_buffer_mode fb_mode;
1094 bool dchub_initialzied;
1095 bool dchub_info_valid;
1096};
1097
1098struct dml2_soc_bb;
1099
1100struct dc_init_data {
1101 struct hw_asic_id asic_id;
1102 void *driver; /* ctx */
1103 struct cgs_device *cgs_device;
1104 struct dc_bounding_box_overrides bb_overrides;
1105
1106 int num_virtual_links;
1107 /*
1108 * If 'vbios_override' not NULL, it will be called instead
1109 * of the real VBIOS. Intended use is Diagnostics on FPGA.
1110 */
1111 struct dc_bios *vbios_override;
1112 enum dce_environment dce_environment;
1113
1114 struct dmub_offload_funcs *dmub_if;
1115 struct dc_reg_helper_state *dmub_offload;
1116
1117 struct dc_config flags;
1118 uint64_t log_mask;
1119
1120 struct dpcd_vendor_signature vendor_signature;
1121 bool force_smu_not_present;
1122 /*
1123 * IP offset for run time initializaion of register addresses
1124 *
1125 * DCN3.5+ will fail dc_create() if these fields are null for them. They are
1126 * applicable starting with DCN32/321 and are not used for ASICs upstreamed
1127 * before them.
1128 */
1129 uint32_t *dcn_reg_offsets;
1130 uint32_t *nbio_reg_offsets;
1131 uint32_t *clk_reg_offsets;
1132 struct dml2_soc_bb *bb_from_dmub;
1133};
1134
1135struct dc_callback_init {
1136 struct cp_psp cp_psp;
1137};
1138
1139struct dc *dc_create(const struct dc_init_data *init_params);
1140void dc_hardware_init(struct dc *dc);
1141
1142int dc_get_vmid_use_vector(struct dc *dc);
1143void dc_setup_vm_context(struct dc *dc, struct dc_virtual_addr_space_config *va_config, int vmid);
1144/* Returns the number of vmids supported */
1145int dc_setup_system_context(struct dc *dc, struct dc_phy_addr_space_config *pa_config);
1146void dc_init_callbacks(struct dc *dc,
1147 const struct dc_callback_init *init_params);
1148void dc_deinit_callbacks(struct dc *dc);
1149void dc_destroy(struct dc **dc);
1150
1151/* Surface Interfaces */
1152
1153enum {
1154 TRANSFER_FUNC_POINTS = 1025
1155};
1156
1157struct dc_hdr_static_metadata {
1158 /* display chromaticities and white point in units of 0.00001 */
1159 unsigned int chromaticity_green_x;
1160 unsigned int chromaticity_green_y;
1161 unsigned int chromaticity_blue_x;
1162 unsigned int chromaticity_blue_y;
1163 unsigned int chromaticity_red_x;
1164 unsigned int chromaticity_red_y;
1165 unsigned int chromaticity_white_point_x;
1166 unsigned int chromaticity_white_point_y;
1167
1168 uint32_t min_luminance;
1169 uint32_t max_luminance;
1170 uint32_t maximum_content_light_level;
1171 uint32_t maximum_frame_average_light_level;
1172};
1173
1174enum dc_transfer_func_type {
1175 TF_TYPE_PREDEFINED,
1176 TF_TYPE_DISTRIBUTED_POINTS,
1177 TF_TYPE_BYPASS,
1178 TF_TYPE_HWPWL
1179};
1180
1181struct dc_transfer_func_distributed_points {
1182 struct fixed31_32 red[TRANSFER_FUNC_POINTS];
1183 struct fixed31_32 green[TRANSFER_FUNC_POINTS];
1184 struct fixed31_32 blue[TRANSFER_FUNC_POINTS];
1185
1186 uint16_t end_exponent;
1187 uint16_t x_point_at_y1_red;
1188 uint16_t x_point_at_y1_green;
1189 uint16_t x_point_at_y1_blue;
1190};
1191
1192enum dc_transfer_func_predefined {
1193 TRANSFER_FUNCTION_SRGB,
1194 TRANSFER_FUNCTION_BT709,
1195 TRANSFER_FUNCTION_PQ,
1196 TRANSFER_FUNCTION_LINEAR,
1197 TRANSFER_FUNCTION_UNITY,
1198 TRANSFER_FUNCTION_HLG,
1199 TRANSFER_FUNCTION_HLG12,
1200 TRANSFER_FUNCTION_GAMMA22,
1201 TRANSFER_FUNCTION_GAMMA24,
1202 TRANSFER_FUNCTION_GAMMA26
1203};
1204
1205
1206struct dc_transfer_func {
1207 struct kref refcount;
1208 enum dc_transfer_func_type type;
1209 enum dc_transfer_func_predefined tf;
1210 /* FP16 1.0 reference level in nits, default is 80 nits, only for PQ*/
1211 uint32_t sdr_ref_white_level;
1212 union {
1213 struct pwl_params pwl;
1214 struct dc_transfer_func_distributed_points tf_pts;
1215 };
1216};
1217
1218
1219union dc_3dlut_state {
1220 struct {
1221 uint32_t initialized:1; /*if 3dlut is went through color module for initialization */
1222 uint32_t rmu_idx_valid:1; /*if mux settings are valid*/
1223 uint32_t rmu_mux_num:3; /*index of mux to use*/
1224 uint32_t mpc_rmu0_mux:4; /*select mpcc on mux, one of the following : mpcc0, mpcc1, mpcc2, mpcc3*/
1225 uint32_t mpc_rmu1_mux:4;
1226 uint32_t mpc_rmu2_mux:4;
1227 uint32_t reserved:15;
1228 } bits;
1229 uint32_t raw;
1230};
1231
1232
1233struct dc_3dlut {
1234 struct kref refcount;
1235 struct tetrahedral_params lut_3d;
1236 struct fixed31_32 hdr_multiplier;
1237 union dc_3dlut_state state;
1238};
1239/*
1240 * This structure is filled in by dc_surface_get_status and contains
1241 * the last requested address and the currently active address so the called
1242 * can determine if there are any outstanding flips
1243 */
1244struct dc_plane_status {
1245 struct dc_plane_address requested_address;
1246 struct dc_plane_address current_address;
1247 bool is_flip_pending;
1248 bool is_right_eye;
1249};
1250
1251union surface_update_flags {
1252
1253 struct {
1254 uint32_t addr_update:1;
1255 /* Medium updates */
1256 uint32_t dcc_change:1;
1257 uint32_t color_space_change:1;
1258 uint32_t horizontal_mirror_change:1;
1259 uint32_t per_pixel_alpha_change:1;
1260 uint32_t global_alpha_change:1;
1261 uint32_t hdr_mult:1;
1262 uint32_t rotation_change:1;
1263 uint32_t swizzle_change:1;
1264 uint32_t scaling_change:1;
1265 uint32_t position_change:1;
1266 uint32_t in_transfer_func_change:1;
1267 uint32_t input_csc_change:1;
1268 uint32_t coeff_reduction_change:1;
1269 uint32_t output_tf_change:1;
1270 uint32_t pixel_format_change:1;
1271 uint32_t plane_size_change:1;
1272 uint32_t gamut_remap_change:1;
1273
1274 /* Full updates */
1275 uint32_t new_plane:1;
1276 uint32_t bpp_change:1;
1277 uint32_t gamma_change:1;
1278 uint32_t bandwidth_change:1;
1279 uint32_t clock_change:1;
1280 uint32_t stereo_format_change:1;
1281 uint32_t lut_3d:1;
1282 uint32_t tmz_changed:1;
1283 uint32_t mcm_transfer_function_enable_change:1; /* disable or enable MCM transfer func */
1284 uint32_t full_update:1;
1285 uint32_t sdr_white_level_nits:1;
1286 } bits;
1287
1288 uint32_t raw;
1289};
1290
1291#define DC_REMOVE_PLANE_POINTERS 1
1292
1293struct dc_plane_state {
1294 struct dc_plane_address address;
1295 struct dc_plane_flip_time time;
1296 bool triplebuffer_flips;
1297 struct scaling_taps scaling_quality;
1298 struct rect src_rect;
1299 struct rect dst_rect;
1300 struct rect clip_rect;
1301
1302 struct plane_size plane_size;
1303 union dc_tiling_info tiling_info;
1304
1305 struct dc_plane_dcc_param dcc;
1306
1307 struct dc_gamma gamma_correction;
1308 struct dc_transfer_func in_transfer_func;
1309 struct dc_bias_and_scale bias_and_scale;
1310 struct dc_csc_transform input_csc_color_matrix;
1311 struct fixed31_32 coeff_reduction_factor;
1312 struct fixed31_32 hdr_mult;
1313 struct colorspace_transform gamut_remap_matrix;
1314
1315 // TODO: No longer used, remove
1316 struct dc_hdr_static_metadata hdr_static_ctx;
1317
1318 enum dc_color_space color_space;
1319
1320 struct dc_3dlut lut3d_func;
1321 struct dc_transfer_func in_shaper_func;
1322 struct dc_transfer_func blend_tf;
1323
1324 struct dc_transfer_func *gamcor_tf;
1325 enum surface_pixel_format format;
1326 enum dc_rotation_angle rotation;
1327 enum plane_stereo_format stereo_format;
1328
1329 bool is_tiling_rotated;
1330 bool per_pixel_alpha;
1331 bool pre_multiplied_alpha;
1332 bool global_alpha;
1333 int global_alpha_value;
1334 bool visible;
1335 bool flip_immediate;
1336 bool horizontal_mirror;
1337 int layer_index;
1338
1339 union surface_update_flags update_flags;
1340 bool flip_int_enabled;
1341 bool skip_manual_trigger;
1342
1343 /* private to DC core */
1344 struct dc_plane_status status;
1345 struct dc_context *ctx;
1346
1347 /* HACK: Workaround for forcing full reprogramming under some conditions */
1348 bool force_full_update;
1349
1350 bool is_phantom; // TODO: Change mall_stream_config into mall_plane_config instead
1351
1352 /* private to dc_surface.c */
1353 enum dc_irq_source irq_source;
1354 struct kref refcount;
1355 struct tg_color visual_confirm_color;
1356
1357 bool is_statically_allocated;
1358 enum chroma_cositing cositing;
1359 enum dc_cm2_shaper_3dlut_setting mcm_shaper_3dlut_setting;
1360 bool mcm_lut1d_enable;
1361 struct dc_cm2_func_luts mcm_luts;
1362 bool lut_bank_a;
1363 enum mpcc_movable_cm_location mcm_location;
1364 struct dc_csc_transform cursor_csc_color_matrix;
1365 bool adaptive_sharpness_en;
1366 int adaptive_sharpness_policy;
1367 int sharpness_level;
1368 enum linear_light_scaling linear_light_scaling;
1369 unsigned int sdr_white_level_nits;
1370};
1371
1372struct dc_plane_info {
1373 struct plane_size plane_size;
1374 union dc_tiling_info tiling_info;
1375 struct dc_plane_dcc_param dcc;
1376 enum surface_pixel_format format;
1377 enum dc_rotation_angle rotation;
1378 enum plane_stereo_format stereo_format;
1379 enum dc_color_space color_space;
1380 bool horizontal_mirror;
1381 bool visible;
1382 bool per_pixel_alpha;
1383 bool pre_multiplied_alpha;
1384 bool global_alpha;
1385 int global_alpha_value;
1386 bool input_csc_enabled;
1387 int layer_index;
1388 enum chroma_cositing cositing;
1389};
1390
1391#include "dc_stream.h"
1392
1393struct dc_scratch_space {
1394 /* used to temporarily backup plane states of a stream during
1395 * dc update. The reason is that plane states are overwritten
1396 * with surface updates in dc update. Once they are overwritten
1397 * current state is no longer valid. We want to temporarily
1398 * store current value in plane states so we can still recover
1399 * a valid current state during dc update.
1400 */
1401 struct dc_plane_state plane_states[MAX_SURFACES];
1402
1403 struct dc_stream_state stream_state;
1404};
1405
1406struct dc {
1407 struct dc_debug_options debug;
1408 struct dc_versions versions;
1409 struct dc_caps caps;
1410 struct dc_cap_funcs cap_funcs;
1411 struct dc_config config;
1412 struct dc_bounding_box_overrides bb_overrides;
1413 struct dc_bug_wa work_arounds;
1414 struct dc_context *ctx;
1415 struct dc_phy_addr_space_config vm_pa_config;
1416
1417 uint8_t link_count;
1418 struct dc_link *links[MAX_LINKS];
1419 struct link_service *link_srv;
1420
1421 struct dc_state *current_state;
1422 struct resource_pool *res_pool;
1423
1424 struct clk_mgr *clk_mgr;
1425
1426 /* Display Engine Clock levels */
1427 struct dm_pp_clock_levels sclk_lvls;
1428
1429 /* Inputs into BW and WM calculations. */
1430 struct bw_calcs_dceip *bw_dceip;
1431 struct bw_calcs_vbios *bw_vbios;
1432 struct dcn_soc_bounding_box *dcn_soc;
1433 struct dcn_ip_params *dcn_ip;
1434 struct display_mode_lib dml;
1435
1436 /* HW functions */
1437 struct hw_sequencer_funcs hwss;
1438 struct dce_hwseq *hwseq;
1439
1440 /* Require to optimize clocks and bandwidth for added/removed planes */
1441 bool optimized_required;
1442 bool wm_optimized_required;
1443 bool idle_optimizations_allowed;
1444 bool enable_c20_dtm_b0;
1445
1446 /* Require to maintain clocks and bandwidth for UEFI enabled HW */
1447
1448 /* FBC compressor */
1449 struct compressor *fbc_compressor;
1450
1451 struct dc_debug_data debug_data;
1452 struct dpcd_vendor_signature vendor_signature;
1453
1454 const char *build_id;
1455 struct vm_helper *vm_helper;
1456
1457 uint32_t *dcn_reg_offsets;
1458 uint32_t *nbio_reg_offsets;
1459 uint32_t *clk_reg_offsets;
1460
1461 /* Scratch memory */
1462 struct {
1463 struct {
1464 /*
1465 * For matching clock_limits table in driver with table
1466 * from PMFW.
1467 */
1468 struct _vcs_dpi_voltage_scaling_st clock_limits[DC__VOLTAGE_STATES];
1469 } update_bw_bounding_box;
1470 struct dc_scratch_space current_state;
1471 struct dc_scratch_space new_state;
1472 struct dc_stream_state temp_stream; // Used so we don't need to allocate stream on the stack
1473 bool pipes_to_unlock_first[MAX_PIPES]; /* Any of the pipes indicated here should be unlocked first */
1474 } scratch;
1475
1476 struct dml2_configuration_options dml2_options;
1477 struct dml2_configuration_options dml2_tmp;
1478 enum dc_acpi_cm_power_state power_state;
1479
1480};
1481
1482struct dc_scaling_info {
1483 struct rect src_rect;
1484 struct rect dst_rect;
1485 struct rect clip_rect;
1486 struct scaling_taps scaling_quality;
1487};
1488
1489struct dc_fast_update {
1490 const struct dc_flip_addrs *flip_addr;
1491 const struct dc_gamma *gamma;
1492 const struct colorspace_transform *gamut_remap_matrix;
1493 const struct dc_csc_transform *input_csc_color_matrix;
1494 const struct fixed31_32 *coeff_reduction_factor;
1495 struct dc_transfer_func *out_transfer_func;
1496 struct dc_csc_transform *output_csc_transform;
1497 const struct dc_csc_transform *cursor_csc_color_matrix;
1498};
1499
1500struct dc_surface_update {
1501 struct dc_plane_state *surface;
1502
1503 /* isr safe update parameters. null means no updates */
1504 const struct dc_flip_addrs *flip_addr;
1505 const struct dc_plane_info *plane_info;
1506 const struct dc_scaling_info *scaling_info;
1507 struct fixed31_32 hdr_mult;
1508 /* following updates require alloc/sleep/spin that is not isr safe,
1509 * null means no updates
1510 */
1511 const struct dc_gamma *gamma;
1512 const struct dc_transfer_func *in_transfer_func;
1513
1514 const struct dc_csc_transform *input_csc_color_matrix;
1515 const struct fixed31_32 *coeff_reduction_factor;
1516 const struct dc_transfer_func *func_shaper;
1517 const struct dc_3dlut *lut3d_func;
1518 const struct dc_transfer_func *blend_tf;
1519 const struct colorspace_transform *gamut_remap_matrix;
1520 /*
1521 * Color Transformations for pre-blend MCM (Shaper, 3DLUT, 1DLUT)
1522 *
1523 * change cm2_params.component_settings: Full update
1524 * change cm2_params.cm2_luts: Fast update
1525 */
1526 const struct dc_cm2_parameters *cm2_params;
1527 const struct dc_csc_transform *cursor_csc_color_matrix;
1528 unsigned int sdr_white_level_nits;
1529};
1530
1531/*
1532 * Create a new surface with default parameters;
1533 */
1534void dc_gamma_retain(struct dc_gamma *dc_gamma);
1535void dc_gamma_release(struct dc_gamma **dc_gamma);
1536struct dc_gamma *dc_create_gamma(void);
1537
1538void dc_transfer_func_retain(struct dc_transfer_func *dc_tf);
1539void dc_transfer_func_release(struct dc_transfer_func *dc_tf);
1540struct dc_transfer_func *dc_create_transfer_func(void);
1541
1542struct dc_3dlut *dc_create_3dlut_func(void);
1543void dc_3dlut_func_release(struct dc_3dlut *lut);
1544void dc_3dlut_func_retain(struct dc_3dlut *lut);
1545
1546void dc_post_update_surfaces_to_stream(
1547 struct dc *dc);
1548
1549#include "dc_stream.h"
1550
1551/**
1552 * struct dc_validation_set - Struct to store surface/stream associations for validation
1553 */
1554struct dc_validation_set {
1555 /**
1556 * @stream: Stream state properties
1557 */
1558 struct dc_stream_state *stream;
1559
1560 /**
1561 * @plane_states: Surface state
1562 */
1563 struct dc_plane_state *plane_states[MAX_SURFACES];
1564
1565 /**
1566 * @plane_count: Total of active planes
1567 */
1568 uint8_t plane_count;
1569};
1570
1571bool dc_validate_boot_timing(const struct dc *dc,
1572 const struct dc_sink *sink,
1573 struct dc_crtc_timing *crtc_timing);
1574
1575enum dc_status dc_validate_plane(struct dc *dc, const struct dc_plane_state *plane_state);
1576
1577void get_clock_requirements_for_state(struct dc_state *state, struct AsicStateEx *info);
1578
1579enum dc_status dc_validate_with_context(struct dc *dc,
1580 const struct dc_validation_set set[],
1581 int set_count,
1582 struct dc_state *context,
1583 bool fast_validate);
1584
1585bool dc_set_generic_gpio_for_stereo(bool enable,
1586 struct gpio_service *gpio_service);
1587
1588/*
1589 * fast_validate: we return after determining if we can support the new state,
1590 * but before we populate the programming info
1591 */
1592enum dc_status dc_validate_global_state(
1593 struct dc *dc,
1594 struct dc_state *new_ctx,
1595 bool fast_validate);
1596
1597bool dc_acquire_release_mpc_3dlut(
1598 struct dc *dc, bool acquire,
1599 struct dc_stream_state *stream,
1600 struct dc_3dlut **lut,
1601 struct dc_transfer_func **shaper);
1602
1603bool dc_resource_is_dsc_encoding_supported(const struct dc *dc);
1604void get_audio_check(struct audio_info *aud_modes,
1605 struct audio_check *aud_chk);
1606
1607bool fast_nonaddr_updates_exist(struct dc_fast_update *fast_update, int surface_count);
1608void populate_fast_updates(struct dc_fast_update *fast_update,
1609 struct dc_surface_update *srf_updates,
1610 int surface_count,
1611 struct dc_stream_update *stream_update);
1612/*
1613 * Set up streams and links associated to drive sinks
1614 * The streams parameter is an absolute set of all active streams.
1615 *
1616 * After this call:
1617 * Phy, Encoder, Timing Generator are programmed and enabled.
1618 * New streams are enabled with blank stream; no memory read.
1619 */
1620enum dc_status dc_commit_streams(struct dc *dc, struct dc_commit_streams_params *params);
1621
1622
1623struct dc_plane_state *dc_get_surface_for_mpcc(struct dc *dc,
1624 struct dc_stream_state *stream,
1625 int mpcc_inst);
1626
1627
1628uint32_t dc_get_opp_for_plane(struct dc *dc, struct dc_plane_state *plane);
1629
1630void dc_set_disable_128b_132b_stream_overhead(bool disable);
1631
1632/* The function returns minimum bandwidth required to drive a given timing
1633 * return - minimum required timing bandwidth in kbps.
1634 */
1635uint32_t dc_bandwidth_in_kbps_from_timing(
1636 const struct dc_crtc_timing *timing,
1637 const enum dc_link_encoding_format link_encoding);
1638
1639/* Link Interfaces */
1640/*
1641 * A link contains one or more sinks and their connected status.
1642 * The currently active signal type (HDMI, DP-SST, DP-MST) is also reported.
1643 */
1644struct dc_link {
1645 struct dc_sink *remote_sinks[MAX_SINKS_PER_LINK];
1646 unsigned int sink_count;
1647 struct dc_sink *local_sink;
1648 unsigned int link_index;
1649 enum dc_connection_type type;
1650 enum signal_type connector_signal;
1651 enum dc_irq_source irq_source_hpd;
1652 enum dc_irq_source irq_source_hpd_rx;/* aka DP Short Pulse */
1653
1654 bool is_hpd_filter_disabled;
1655 bool dp_ss_off;
1656
1657 /**
1658 * @link_state_valid:
1659 *
1660 * If there is no link and local sink, this variable should be set to
1661 * false. Otherwise, it should be set to true; usually, the function
1662 * core_link_enable_stream sets this field to true.
1663 */
1664 bool link_state_valid;
1665 bool aux_access_disabled;
1666 bool sync_lt_in_progress;
1667 bool skip_stream_reenable;
1668 bool is_internal_display;
1669 /** @todo Rename. Flag an endpoint as having a programmable mapping to a DIG encoder. */
1670 bool is_dig_mapping_flexible;
1671 bool hpd_status; /* HPD status of link without physical HPD pin. */
1672 bool is_hpd_pending; /* Indicates a new received hpd */
1673
1674 /* USB4 DPIA links skip verifying link cap, instead performing the fallback method
1675 * for every link training. This is incompatible with DP LL compliance automation,
1676 * which expects the same link settings to be used every retry on a link loss.
1677 * This flag is used to skip the fallback when link loss occurs during automation.
1678 */
1679 bool skip_fallback_on_link_loss;
1680
1681 bool edp_sink_present;
1682
1683 struct dp_trace dp_trace;
1684
1685 /* caps is the same as reported_link_cap. link_traing use
1686 * reported_link_cap. Will clean up. TODO
1687 */
1688 struct dc_link_settings reported_link_cap;
1689 struct dc_link_settings verified_link_cap;
1690 struct dc_link_settings cur_link_settings;
1691 struct dc_lane_settings cur_lane_setting[LANE_COUNT_DP_MAX];
1692 struct dc_link_settings preferred_link_setting;
1693 /* preferred_training_settings are override values that
1694 * come from DM. DM is responsible for the memory
1695 * management of the override pointers.
1696 */
1697 struct dc_link_training_overrides preferred_training_settings;
1698 struct dp_audio_test_data audio_test_data;
1699
1700 uint8_t ddc_hw_inst;
1701
1702 uint8_t hpd_src;
1703
1704 uint8_t link_enc_hw_inst;
1705 /* DIG link encoder ID. Used as index in link encoder resource pool.
1706 * For links with fixed mapping to DIG, this is not changed after dc_link
1707 * object creation.
1708 */
1709 enum engine_id eng_id;
1710 enum engine_id dpia_preferred_eng_id;
1711
1712 bool test_pattern_enabled;
1713 /* Pending/Current test pattern are only used to perform and track
1714 * FIXED_VS retimer test pattern/lane adjustment override state.
1715 * Pending allows link HWSS to differentiate PHY vs non-PHY pattern,
1716 * to perform specific lane adjust overrides before setting certain
1717 * PHY test patterns. In cases when lane adjust and set test pattern
1718 * calls are not performed atomically (i.e. performing link training),
1719 * pending_test_pattern will be invalid or contain a non-PHY test pattern
1720 * and current_test_pattern will contain required context for any future
1721 * set pattern/set lane adjust to transition between override state(s).
1722 * */
1723 enum dp_test_pattern current_test_pattern;
1724 enum dp_test_pattern pending_test_pattern;
1725
1726 union compliance_test_state compliance_test_state;
1727
1728 void *priv;
1729
1730 struct ddc_service *ddc;
1731
1732 enum dp_panel_mode panel_mode;
1733 bool aux_mode;
1734
1735 /* Private to DC core */
1736
1737 const struct dc *dc;
1738
1739 struct dc_context *ctx;
1740
1741 struct panel_cntl *panel_cntl;
1742 struct link_encoder *link_enc;
1743 struct graphics_object_id link_id;
1744 /* Endpoint type distinguishes display endpoints which do not have entries
1745 * in the BIOS connector table from those that do. Helps when tracking link
1746 * encoder to display endpoint assignments.
1747 */
1748 enum display_endpoint_type ep_type;
1749 union ddi_channel_mapping ddi_channel_mapping;
1750 struct connector_device_tag_info device_tag;
1751 struct dpcd_caps dpcd_caps;
1752 uint32_t dongle_max_pix_clk;
1753 unsigned short chip_caps;
1754 unsigned int dpcd_sink_count;
1755 struct hdcp_caps hdcp_caps;
1756 enum edp_revision edp_revision;
1757 union dpcd_sink_ext_caps dpcd_sink_ext_caps;
1758
1759 struct psr_settings psr_settings;
1760 struct replay_settings replay_settings;
1761
1762 /* Drive settings read from integrated info table */
1763 struct dc_lane_settings bios_forced_drive_settings;
1764
1765 /* Vendor specific LTTPR workaround variables */
1766 uint8_t vendor_specific_lttpr_link_rate_wa;
1767 bool apply_vendor_specific_lttpr_link_rate_wa;
1768
1769 /* MST record stream using this link */
1770 struct link_flags {
1771 bool dp_keep_receiver_powered;
1772 bool dp_skip_DID2;
1773 bool dp_skip_reset_segment;
1774 bool dp_skip_fs_144hz;
1775 bool dp_mot_reset_segment;
1776 /* Some USB4 docks do not handle turning off MST DSC once it has been enabled. */
1777 bool dpia_mst_dsc_always_on;
1778 /* Forced DPIA into TBT3 compatibility mode. */
1779 bool dpia_forced_tbt3_mode;
1780 bool dongle_mode_timing_override;
1781 bool blank_stream_on_ocs_change;
1782 bool read_dpcd204h_on_irq_hpd;
1783 } wa_flags;
1784 struct link_mst_stream_allocation_table mst_stream_alloc_table;
1785
1786 struct dc_link_status link_status;
1787 struct dprx_states dprx_states;
1788
1789 struct gpio *hpd_gpio;
1790 enum dc_link_fec_state fec_state;
1791 bool link_powered_externally; // Used to bypass hardware sequencing delays when panel is powered down forcibly
1792
1793 struct dc_panel_config panel_config;
1794 struct phy_state phy_state;
1795 // BW ALLOCATON USB4 ONLY
1796 struct dc_dpia_bw_alloc dpia_bw_alloc_config;
1797 bool skip_implict_edp_power_control;
1798 enum backlight_control_type backlight_control_type;
1799};
1800
1801/* Return an enumerated dc_link.
1802 * dc_link order is constant and determined at
1803 * boot time. They cannot be created or destroyed.
1804 * Use dc_get_caps() to get number of links.
1805 */
1806struct dc_link *dc_get_link_at_index(struct dc *dc, uint32_t link_index);
1807
1808/* Return instance id of the edp link. Inst 0 is primary edp link. */
1809bool dc_get_edp_link_panel_inst(const struct dc *dc,
1810 const struct dc_link *link,
1811 unsigned int *inst_out);
1812
1813/* Return an array of link pointers to edp links. */
1814void dc_get_edp_links(const struct dc *dc,
1815 struct dc_link **edp_links,
1816 int *edp_num);
1817
1818void dc_set_edp_power(const struct dc *dc, struct dc_link *edp_link,
1819 bool powerOn);
1820
1821/* The function initiates detection handshake over the given link. It first
1822 * determines if there are display connections over the link. If so it initiates
1823 * detection protocols supported by the connected receiver device. The function
1824 * contains protocol specific handshake sequences which are sometimes mandatory
1825 * to establish a proper connection between TX and RX. So it is always
1826 * recommended to call this function as the first link operation upon HPD event
1827 * or power up event. Upon completion, the function will update link structure
1828 * in place based on latest RX capabilities. The function may also cause dpms
1829 * to be reset to off for all currently enabled streams to the link. It is DM's
1830 * responsibility to serialize detection and DPMS updates.
1831 *
1832 * @reason - Indicate which event triggers this detection. dc may customize
1833 * detection flow depending on the triggering events.
1834 * return false - if detection is not fully completed. This could happen when
1835 * there is an unrecoverable error during detection or detection is partially
1836 * completed (detection has been delegated to dm mst manager ie.
1837 * link->connection_type == dc_connection_mst_branch when returning false).
1838 * return true - detection is completed, link has been fully updated with latest
1839 * detection result.
1840 */
1841bool dc_link_detect(struct dc_link *link, enum dc_detect_reason reason);
1842
1843struct dc_sink_init_data;
1844
1845/* When link connection type is dc_connection_mst_branch, remote sink can be
1846 * added to the link. The interface creates a remote sink and associates it with
1847 * current link. The sink will be retained by link until remove remote sink is
1848 * called.
1849 *
1850 * @dc_link - link the remote sink will be added to.
1851 * @edid - byte array of EDID raw data.
1852 * @len - size of the edid in byte
1853 * @init_data -
1854 */
1855struct dc_sink *dc_link_add_remote_sink(
1856 struct dc_link *dc_link,
1857 const uint8_t *edid,
1858 int len,
1859 struct dc_sink_init_data *init_data);
1860
1861/* Remove remote sink from a link with dc_connection_mst_branch connection type.
1862 * @link - link the sink should be removed from
1863 * @sink - sink to be removed.
1864 */
1865void dc_link_remove_remote_sink(
1866 struct dc_link *link,
1867 struct dc_sink *sink);
1868
1869/* Enable HPD interrupt handler for a given link */
1870void dc_link_enable_hpd(const struct dc_link *link);
1871
1872/* Disable HPD interrupt handler for a given link */
1873void dc_link_disable_hpd(const struct dc_link *link);
1874
1875/* determine if there is a sink connected to the link
1876 *
1877 * @type - dc_connection_single if connected, dc_connection_none otherwise.
1878 * return - false if an unexpected error occurs, true otherwise.
1879 *
1880 * NOTE: This function doesn't detect downstream sink connections i.e
1881 * dc_connection_mst_branch, dc_connection_sst_branch. In this case, it will
1882 * return dc_connection_single if the branch device is connected despite of
1883 * downstream sink's connection status.
1884 */
1885bool dc_link_detect_connection_type(struct dc_link *link,
1886 enum dc_connection_type *type);
1887
1888/* query current hpd pin value
1889 * return - true HPD is asserted (HPD high), false otherwise (HPD low)
1890 *
1891 */
1892bool dc_link_get_hpd_state(struct dc_link *link);
1893
1894/* Getter for cached link status from given link */
1895const struct dc_link_status *dc_link_get_status(const struct dc_link *link);
1896
1897/* enable/disable hardware HPD filter.
1898 *
1899 * @link - The link the HPD pin is associated with.
1900 * @enable = true - enable hardware HPD filter. HPD event will only queued to irq
1901 * handler once after no HPD change has been detected within dc default HPD
1902 * filtering interval since last HPD event. i.e if display keeps toggling hpd
1903 * pulses within default HPD interval, no HPD event will be received until HPD
1904 * toggles have stopped. Then HPD event will be queued to irq handler once after
1905 * dc default HPD filtering interval since last HPD event.
1906 *
1907 * @enable = false - disable hardware HPD filter. HPD event will be queued
1908 * immediately to irq handler after no HPD change has been detected within
1909 * IRQ_HPD (aka HPD short pulse) interval (i.e 2ms).
1910 */
1911void dc_link_enable_hpd_filter(struct dc_link *link, bool enable);
1912
1913/* submit i2c read/write payloads through ddc channel
1914 * @link_index - index to a link with ddc in i2c mode
1915 * @cmd - i2c command structure
1916 * return - true if success, false otherwise.
1917 */
1918bool dc_submit_i2c(
1919 struct dc *dc,
1920 uint32_t link_index,
1921 struct i2c_command *cmd);
1922
1923/* submit i2c read/write payloads through oem channel
1924 * @link_index - index to a link with ddc in i2c mode
1925 * @cmd - i2c command structure
1926 * return - true if success, false otherwise.
1927 */
1928bool dc_submit_i2c_oem(
1929 struct dc *dc,
1930 struct i2c_command *cmd);
1931
1932enum aux_return_code_type;
1933/* Attempt to transfer the given aux payload. This function does not perform
1934 * retries or handle error states. The reply is returned in the payload->reply
1935 * and the result through operation_result. Returns the number of bytes
1936 * transferred,or -1 on a failure.
1937 */
1938int dc_link_aux_transfer_raw(struct ddc_service *ddc,
1939 struct aux_payload *payload,
1940 enum aux_return_code_type *operation_result);
1941
1942bool dc_is_oem_i2c_device_present(
1943 struct dc *dc,
1944 size_t slave_address
1945);
1946
1947/* return true if the connected receiver supports the hdcp version */
1948bool dc_link_is_hdcp14(struct dc_link *link, enum signal_type signal);
1949bool dc_link_is_hdcp22(struct dc_link *link, enum signal_type signal);
1950
1951/* Notify DC about DP RX Interrupt (aka DP IRQ_HPD).
1952 *
1953 * TODO - When defer_handling is true the function will have a different purpose.
1954 * It no longer does complete hpd rx irq handling. We should create a separate
1955 * interface specifically for this case.
1956 *
1957 * Return:
1958 * true - Downstream port status changed. DM should call DC to do the
1959 * detection.
1960 * false - no change in Downstream port status. No further action required
1961 * from DM.
1962 */
1963bool dc_link_handle_hpd_rx_irq(struct dc_link *dc_link,
1964 union hpd_irq_data *hpd_irq_dpcd_data, bool *out_link_loss,
1965 bool defer_handling, bool *has_left_work);
1966/* handle DP specs define test automation sequence*/
1967void dc_link_dp_handle_automated_test(struct dc_link *link);
1968
1969/* handle DP Link loss sequence and try to recover RX link loss with best
1970 * effort
1971 */
1972void dc_link_dp_handle_link_loss(struct dc_link *link);
1973
1974/* Determine if hpd rx irq should be handled or ignored
1975 * return true - hpd rx irq should be handled.
1976 * return false - it is safe to ignore hpd rx irq event
1977 */
1978bool dc_link_dp_allow_hpd_rx_irq(const struct dc_link *link);
1979
1980/* Determine if link loss is indicated with a given hpd_irq_dpcd_data.
1981 * @link - link the hpd irq data associated with
1982 * @hpd_irq_dpcd_data - input hpd irq data
1983 * return - true if hpd irq data indicates a link lost
1984 */
1985bool dc_link_check_link_loss_status(struct dc_link *link,
1986 union hpd_irq_data *hpd_irq_dpcd_data);
1987
1988/* Read hpd rx irq data from a given link
1989 * @link - link where the hpd irq data should be read from
1990 * @irq_data - output hpd irq data
1991 * return - DC_OK if hpd irq data is read successfully, otherwise hpd irq data
1992 * read has failed.
1993 */
1994enum dc_status dc_link_dp_read_hpd_rx_irq_data(
1995 struct dc_link *link,
1996 union hpd_irq_data *irq_data);
1997
1998/* The function clears recorded DP RX states in the link. DM should call this
1999 * function when it is resuming from S3 power state to previously connected links.
2000 *
2001 * TODO - in the future we should consider to expand link resume interface to
2002 * support clearing previous rx states. So we don't have to rely on dm to call
2003 * this interface explicitly.
2004 */
2005void dc_link_clear_dprx_states(struct dc_link *link);
2006
2007/* Destruct the mst topology of the link and reset the allocated payload table
2008 *
2009 * NOTE: this should only be called if DM chooses not to call dc_link_detect but
2010 * still wants to reset MST topology on an unplug event */
2011bool dc_link_reset_cur_dp_mst_topology(struct dc_link *link);
2012
2013/* The function calculates effective DP link bandwidth when a given link is
2014 * using the given link settings.
2015 *
2016 * return - total effective link bandwidth in kbps.
2017 */
2018uint32_t dc_link_bandwidth_kbps(
2019 const struct dc_link *link,
2020 const struct dc_link_settings *link_setting);
2021
2022/* The function takes a snapshot of current link resource allocation state
2023 * @dc: pointer to dc of the dm calling this
2024 * @map: a dc link resource snapshot defined internally to dc.
2025 *
2026 * DM needs to capture a snapshot of current link resource allocation mapping
2027 * and store it in its persistent storage.
2028 *
2029 * Some of the link resource is using first come first serve policy.
2030 * The allocation mapping depends on original hotplug order. This information
2031 * is lost after driver is loaded next time. The snapshot is used in order to
2032 * restore link resource to its previous state so user will get consistent
2033 * link capability allocation across reboot.
2034 *
2035 */
2036void dc_get_cur_link_res_map(const struct dc *dc, uint32_t *map);
2037
2038/* This function restores link resource allocation state from a snapshot
2039 * @dc: pointer to dc of the dm calling this
2040 * @map: a dc link resource snapshot defined internally to dc.
2041 *
2042 * DM needs to call this function after initial link detection on boot and
2043 * before first commit streams to restore link resource allocation state
2044 * from previous boot session.
2045 *
2046 * Some of the link resource is using first come first serve policy.
2047 * The allocation mapping depends on original hotplug order. This information
2048 * is lost after driver is loaded next time. The snapshot is used in order to
2049 * restore link resource to its previous state so user will get consistent
2050 * link capability allocation across reboot.
2051 *
2052 */
2053void dc_restore_link_res_map(const struct dc *dc, uint32_t *map);
2054
2055/* TODO: this is not meant to be exposed to DM. Should switch to stream update
2056 * interface i.e stream_update->dsc_config
2057 */
2058bool dc_link_update_dsc_config(struct pipe_ctx *pipe_ctx);
2059
2060/* translate a raw link rate data to bandwidth in kbps */
2061uint32_t dc_link_bw_kbps_from_raw_frl_link_rate_data(const struct dc *dc, uint8_t bw);
2062
2063/* determine the optimal bandwidth given link and required bw.
2064 * @link - current detected link
2065 * @req_bw - requested bandwidth in kbps
2066 * @link_settings - returned most optimal link settings that can fit the
2067 * requested bandwidth
2068 * return - false if link can't support requested bandwidth, true if link
2069 * settings is found.
2070 */
2071bool dc_link_decide_edp_link_settings(struct dc_link *link,
2072 struct dc_link_settings *link_settings,
2073 uint32_t req_bw);
2074
2075/* return the max dp link settings can be driven by the link without considering
2076 * connected RX device and its capability
2077 */
2078bool dc_link_dp_get_max_link_enc_cap(const struct dc_link *link,
2079 struct dc_link_settings *max_link_enc_cap);
2080
2081/* determine when the link is driving MST mode, what DP link channel coding
2082 * format will be used. The decision will remain unchanged until next HPD event.
2083 *
2084 * @link - a link with DP RX connection
2085 * return - if stream is committed to this link with MST signal type, type of
2086 * channel coding format dc will choose.
2087 */
2088enum dp_link_encoding dc_link_dp_mst_decide_link_encoding_format(
2089 const struct dc_link *link);
2090
2091/* get max dp link settings the link can enable with all things considered. (i.e
2092 * TX/RX/Cable capabilities and dp override policies.
2093 *
2094 * @link - a link with DP RX connection
2095 * return - max dp link settings the link can enable.
2096 *
2097 */
2098const struct dc_link_settings *dc_link_get_link_cap(const struct dc_link *link);
2099
2100/* Get the highest encoding format that the link supports; highest meaning the
2101 * encoding format which supports the maximum bandwidth.
2102 *
2103 * @link - a link with DP RX connection
2104 * return - highest encoding format link supports.
2105 */
2106enum dc_link_encoding_format dc_link_get_highest_encoding_format(const struct dc_link *link);
2107
2108/* Check if a RX (ex. DP sink, MST hub, passive or active dongle) is connected
2109 * to a link with dp connector signal type.
2110 * @link - a link with dp connector signal type
2111 * return - true if connected, false otherwise
2112 */
2113bool dc_link_is_dp_sink_present(struct dc_link *link);
2114
2115/* Force DP lane settings update to main-link video signal and notify the change
2116 * to DP RX via DPCD. This is a debug interface used for video signal integrity
2117 * tuning purpose. The interface assumes link has already been enabled with DP
2118 * signal.
2119 *
2120 * @lt_settings - a container structure with desired hw_lane_settings
2121 */
2122void dc_link_set_drive_settings(struct dc *dc,
2123 struct link_training_settings *lt_settings,
2124 struct dc_link *link);
2125
2126/* Enable a test pattern in Link or PHY layer in an active link for compliance
2127 * test or debugging purpose. The test pattern will remain until next un-plug.
2128 *
2129 * @link - active link with DP signal output enabled.
2130 * @test_pattern - desired test pattern to output.
2131 * NOTE: set to DP_TEST_PATTERN_VIDEO_MODE to disable previous test pattern.
2132 * @test_pattern_color_space - for video test pattern choose a desired color
2133 * space.
2134 * @p_link_settings - For PHY pattern choose a desired link settings
2135 * @p_custom_pattern - some test pattern will require a custom input to
2136 * customize some pattern details. Otherwise keep it to NULL.
2137 * @cust_pattern_size - size of the custom pattern input.
2138 *
2139 */
2140bool dc_link_dp_set_test_pattern(
2141 struct dc_link *link,
2142 enum dp_test_pattern test_pattern,
2143 enum dp_test_pattern_color_space test_pattern_color_space,
2144 const struct link_training_settings *p_link_settings,
2145 const unsigned char *p_custom_pattern,
2146 unsigned int cust_pattern_size);
2147
2148/* Force DP link settings to always use a specific value until reboot to a
2149 * specific link. If link has already been enabled, the interface will also
2150 * switch to desired link settings immediately. This is a debug interface to
2151 * generic dp issue trouble shooting.
2152 */
2153void dc_link_set_preferred_link_settings(struct dc *dc,
2154 struct dc_link_settings *link_setting,
2155 struct dc_link *link);
2156
2157/* Force DP link to customize a specific link training behavior by overriding to
2158 * standard DP specs defined protocol. This is a debug interface to trouble shoot
2159 * display specific link training issues or apply some display specific
2160 * workaround in link training.
2161 *
2162 * @link_settings - if not NULL, force preferred link settings to the link.
2163 * @lt_override - a set of override pointers. If any pointer is none NULL, dc
2164 * will apply this particular override in future link training. If NULL is
2165 * passed in, dc resets previous overrides.
2166 * NOTE: DM must keep the memory from override pointers until DM resets preferred
2167 * training settings.
2168 */
2169void dc_link_set_preferred_training_settings(struct dc *dc,
2170 struct dc_link_settings *link_setting,
2171 struct dc_link_training_overrides *lt_overrides,
2172 struct dc_link *link,
2173 bool skip_immediate_retrain);
2174
2175/* return - true if FEC is supported with connected DP RX, false otherwise */
2176bool dc_link_is_fec_supported(const struct dc_link *link);
2177
2178/* query FEC enablement policy to determine if FEC will be enabled by dc during
2179 * link enablement.
2180 * return - true if FEC should be enabled, false otherwise.
2181 */
2182bool dc_link_should_enable_fec(const struct dc_link *link);
2183
2184/* determine lttpr mode the current link should be enabled with a specific link
2185 * settings.
2186 */
2187enum lttpr_mode dc_link_decide_lttpr_mode(struct dc_link *link,
2188 struct dc_link_settings *link_setting);
2189
2190/* Force DP RX to update its power state.
2191 * NOTE: this interface doesn't update dp main-link. Calling this function will
2192 * cause DP TX main-link and DP RX power states out of sync. DM has to restore
2193 * RX power state back upon finish DM specific execution requiring DP RX in a
2194 * specific power state.
2195 * @on - true to set DP RX in D0 power state, false to set DP RX in D3 power
2196 * state.
2197 */
2198void dc_link_dp_receiver_power_ctrl(struct dc_link *link, bool on);
2199
2200/* Force link to read base dp receiver caps from dpcd 000h - 00Fh and overwrite
2201 * current value read from extended receiver cap from 02200h - 0220Fh.
2202 * Some DP RX has problems of providing accurate DP receiver caps from extended
2203 * field, this interface is a workaround to revert link back to use base caps.
2204 */
2205void dc_link_overwrite_extended_receiver_cap(
2206 struct dc_link *link);
2207
2208void dc_link_edp_panel_backlight_power_on(struct dc_link *link,
2209 bool wait_for_hpd);
2210
2211/* Set backlight level of an embedded panel (eDP, LVDS).
2212 * backlight_pwm_u16_16 is unsigned 32 bit with 16 bit integer
2213 * and 16 bit fractional, where 1.0 is max backlight value.
2214 */
2215bool dc_link_set_backlight_level(const struct dc_link *dc_link,
2216 struct set_backlight_level_params *backlight_level_params);
2217
2218/* Set/get nits-based backlight level of an embedded panel (eDP, LVDS). */
2219bool dc_link_set_backlight_level_nits(struct dc_link *link,
2220 bool isHDR,
2221 uint32_t backlight_millinits,
2222 uint32_t transition_time_in_ms);
2223
2224bool dc_link_get_backlight_level_nits(struct dc_link *link,
2225 uint32_t *backlight_millinits,
2226 uint32_t *backlight_millinits_peak);
2227
2228int dc_link_get_backlight_level(const struct dc_link *dc_link);
2229
2230int dc_link_get_target_backlight_pwm(const struct dc_link *link);
2231
2232bool dc_link_set_psr_allow_active(struct dc_link *dc_link, const bool *enable,
2233 bool wait, bool force_static, const unsigned int *power_opts);
2234
2235bool dc_link_get_psr_state(const struct dc_link *dc_link, enum dc_psr_state *state);
2236
2237bool dc_link_setup_psr(struct dc_link *dc_link,
2238 const struct dc_stream_state *stream, struct psr_config *psr_config,
2239 struct psr_context *psr_context);
2240
2241/*
2242 * Communicate with DMUB to allow or disallow Panel Replay on the specified link:
2243 *
2244 * @link: pointer to the dc_link struct instance
2245 * @enable: enable(active) or disable(inactive) replay
2246 * @wait: state transition need to wait the active set completed.
2247 * @force_static: force disable(inactive) the replay
2248 * @power_opts: set power optimazation parameters to DMUB.
2249 *
2250 * return: allow Replay active will return true, else will return false.
2251 */
2252bool dc_link_set_replay_allow_active(struct dc_link *dc_link, const bool *enable,
2253 bool wait, bool force_static, const unsigned int *power_opts);
2254
2255bool dc_link_get_replay_state(const struct dc_link *dc_link, uint64_t *state);
2256
2257/* On eDP links this function call will stall until T12 has elapsed.
2258 * If the panel is not in power off state, this function will return
2259 * immediately.
2260 */
2261bool dc_link_wait_for_t12(struct dc_link *link);
2262
2263/* Determine if dp trace has been initialized to reflect upto date result *
2264 * return - true if trace is initialized and has valid data. False dp trace
2265 * doesn't have valid result.
2266 */
2267bool dc_dp_trace_is_initialized(struct dc_link *link);
2268
2269/* Query a dp trace flag to indicate if the current dp trace data has been
2270 * logged before
2271 */
2272bool dc_dp_trace_is_logged(struct dc_link *link,
2273 bool in_detection);
2274
2275/* Set dp trace flag to indicate whether DM has already logged the current dp
2276 * trace data. DM can set is_logged to true upon logging and check
2277 * dc_dp_trace_is_logged before logging to avoid logging the same result twice.
2278 */
2279void dc_dp_trace_set_is_logged_flag(struct dc_link *link,
2280 bool in_detection,
2281 bool is_logged);
2282
2283/* Obtain driver time stamp for last dp link training end. The time stamp is
2284 * formatted based on dm_get_timestamp DM function.
2285 * @in_detection - true to get link training end time stamp of last link
2286 * training in detection sequence. false to get link training end time stamp
2287 * of last link training in commit (dpms) sequence
2288 */
2289unsigned long long dc_dp_trace_get_lt_end_timestamp(struct dc_link *link,
2290 bool in_detection);
2291
2292/* Get how many link training attempts dc has done with latest sequence.
2293 * @in_detection - true to get link training count of last link
2294 * training in detection sequence. false to get link training count of last link
2295 * training in commit (dpms) sequence
2296 */
2297const struct dp_trace_lt_counts *dc_dp_trace_get_lt_counts(struct dc_link *link,
2298 bool in_detection);
2299
2300/* Get how many link loss has happened since last link training attempts */
2301unsigned int dc_dp_trace_get_link_loss_count(struct dc_link *link);
2302
2303/*
2304 * USB4 DPIA BW ALLOCATION PUBLIC FUNCTIONS
2305 */
2306/*
2307 * Send a request from DP-Tx requesting to allocate BW remotely after
2308 * allocating it locally. This will get processed by CM and a CB function
2309 * will be called.
2310 *
2311 * @link: pointer to the dc_link struct instance
2312 * @req_bw: The requested bw in Kbyte to allocated
2313 *
2314 * return: none
2315 */
2316void dc_link_set_usb4_req_bw_req(struct dc_link *link, int req_bw);
2317
2318/*
2319 * Handle function for when the status of the Request above is complete.
2320 * We will find out the result of allocating on CM and update structs.
2321 *
2322 * @link: pointer to the dc_link struct instance
2323 * @bw: Allocated or Estimated BW depending on the result
2324 * @result: Response type
2325 *
2326 * return: none
2327 */
2328void dc_link_handle_usb4_bw_alloc_response(struct dc_link *link,
2329 uint8_t bw, uint8_t result);
2330
2331/*
2332 * Handle the USB4 BW Allocation related functionality here:
2333 * Plug => Try to allocate max bw from timing parameters supported by the sink
2334 * Unplug => de-allocate bw
2335 *
2336 * @link: pointer to the dc_link struct instance
2337 * @peak_bw: Peak bw used by the link/sink
2338 *
2339 * return: allocated bw else return 0
2340 */
2341int dc_link_dp_dpia_handle_usb4_bandwidth_allocation_for_link(
2342 struct dc_link *link, int peak_bw);
2343
2344/*
2345 * Validate the BW of all the valid DPIA links to make sure it doesn't exceed
2346 * available BW for each host router
2347 *
2348 * @dc: pointer to dc struct
2349 * @stream: pointer to all possible streams
2350 * @count: number of valid DPIA streams
2351 *
2352 * return: TRUE if bw used by DPIAs doesn't exceed available BW else return FALSE
2353 */
2354bool dc_link_dp_dpia_validate(struct dc *dc, const struct dc_stream_state *streams,
2355 const unsigned int count);
2356
2357/* Sink Interfaces - A sink corresponds to a display output device */
2358
2359struct dc_container_id {
2360 // 128bit GUID in binary form
2361 unsigned char guid[16];
2362 // 8 byte port ID -> ELD.PortID
2363 unsigned int portId[2];
2364 // 128bit GUID in binary formufacturer name -> ELD.ManufacturerName
2365 unsigned short manufacturerName;
2366 // 2 byte product code -> ELD.ProductCode
2367 unsigned short productCode;
2368};
2369
2370
2371struct dc_sink_dsc_caps {
2372 // 'true' if these are virtual DPCD's DSC caps (immediately upstream of sink in MST topology),
2373 // 'false' if they are sink's DSC caps
2374 bool is_virtual_dpcd_dsc;
2375 // 'true' if MST topology supports DSC passthrough for sink
2376 // 'false' if MST topology does not support DSC passthrough
2377 bool is_dsc_passthrough_supported;
2378 struct dsc_dec_dpcd_caps dsc_dec_caps;
2379};
2380
2381struct dc_sink_fec_caps {
2382 bool is_rx_fec_supported;
2383 bool is_topology_fec_supported;
2384};
2385
2386struct scdc_caps {
2387 union hdmi_scdc_manufacturer_OUI_data manufacturer_OUI;
2388 union hdmi_scdc_device_id_data device_id;
2389};
2390
2391/*
2392 * The sink structure contains EDID and other display device properties
2393 */
2394struct dc_sink {
2395 enum signal_type sink_signal;
2396 struct dc_edid dc_edid; /* raw edid */
2397 struct dc_edid_caps edid_caps; /* parse display caps */
2398 struct dc_container_id *dc_container_id;
2399 uint32_t dongle_max_pix_clk;
2400 void *priv;
2401 struct stereo_3d_features features_3d[TIMING_3D_FORMAT_MAX];
2402 bool converter_disable_audio;
2403
2404 struct scdc_caps scdc_caps;
2405 struct dc_sink_dsc_caps dsc_caps;
2406 struct dc_sink_fec_caps fec_caps;
2407
2408 bool is_vsc_sdp_colorimetry_supported;
2409
2410 /* private to DC core */
2411 struct dc_link *link;
2412 struct dc_context *ctx;
2413
2414 uint32_t sink_id;
2415
2416 /* private to dc_sink.c */
2417 // refcount must be the last member in dc_sink, since we want the
2418 // sink structure to be logically cloneable up to (but not including)
2419 // refcount
2420 struct kref refcount;
2421};
2422
2423void dc_sink_retain(struct dc_sink *sink);
2424void dc_sink_release(struct dc_sink *sink);
2425
2426struct dc_sink_init_data {
2427 enum signal_type sink_signal;
2428 struct dc_link *link;
2429 uint32_t dongle_max_pix_clk;
2430 bool converter_disable_audio;
2431};
2432
2433struct dc_sink *dc_sink_create(const struct dc_sink_init_data *init_params);
2434
2435/* Newer interfaces */
2436struct dc_cursor {
2437 struct dc_plane_address address;
2438 struct dc_cursor_attributes attributes;
2439};
2440
2441
2442/* Interrupt interfaces */
2443enum dc_irq_source dc_interrupt_to_irq_source(
2444 struct dc *dc,
2445 uint32_t src_id,
2446 uint32_t ext_id);
2447bool dc_interrupt_set(struct dc *dc, enum dc_irq_source src, bool enable);
2448void dc_interrupt_ack(struct dc *dc, enum dc_irq_source src);
2449enum dc_irq_source dc_get_hpd_irq_source_at_index(
2450 struct dc *dc, uint32_t link_index);
2451
2452void dc_notify_vsync_int_state(struct dc *dc, struct dc_stream_state *stream, bool enable);
2453
2454/* Power Interfaces */
2455
2456void dc_set_power_state(
2457 struct dc *dc,
2458 enum dc_acpi_cm_power_state power_state);
2459void dc_resume(struct dc *dc);
2460
2461void dc_power_down_on_boot(struct dc *dc);
2462
2463/*
2464 * HDCP Interfaces
2465 */
2466enum hdcp_message_status dc_process_hdcp_msg(
2467 enum signal_type signal,
2468 struct dc_link *link,
2469 struct hdcp_protection_message *message_info);
2470bool dc_is_dmcu_initialized(struct dc *dc);
2471
2472enum dc_status dc_set_clock(struct dc *dc, enum dc_clock_type clock_type, uint32_t clk_khz, uint32_t stepping);
2473void dc_get_clock(struct dc *dc, enum dc_clock_type clock_type, struct dc_clock_config *clock_cfg);
2474
2475bool dc_is_plane_eligible_for_idle_optimizations(struct dc *dc,
2476 unsigned int pitch,
2477 unsigned int height,
2478 enum surface_pixel_format format,
2479 struct dc_cursor_attributes *cursor_attr);
2480
2481#define dc_allow_idle_optimizations(dc, allow) dc_allow_idle_optimizations_internal(dc, allow, __func__)
2482#define dc_exit_ips_for_hw_access(dc) dc_exit_ips_for_hw_access_internal(dc, __func__)
2483
2484void dc_allow_idle_optimizations_internal(struct dc *dc, bool allow, const char *caller_name);
2485void dc_exit_ips_for_hw_access_internal(struct dc *dc, const char *caller_name);
2486bool dc_dmub_is_ips_idle_state(struct dc *dc);
2487
2488/* set min and max memory clock to lowest and highest DPM level, respectively */
2489void dc_unlock_memory_clock_frequency(struct dc *dc);
2490
2491/* set min memory clock to the min required for current mode, max to maxDPM */
2492void dc_lock_memory_clock_frequency(struct dc *dc);
2493
2494/* set soft max for memclk, to be used for AC/DC switching clock limitations */
2495void dc_enable_dcmode_clk_limit(struct dc *dc, bool enable);
2496
2497/* cleanup on driver unload */
2498void dc_hardware_release(struct dc *dc);
2499
2500/* disables fw based mclk switch */
2501void dc_mclk_switch_using_fw_based_vblank_stretch_shut_down(struct dc *dc);
2502
2503bool dc_set_psr_allow_active(struct dc *dc, bool enable);
2504
2505bool dc_set_replay_allow_active(struct dc *dc, bool active);
2506
2507bool dc_set_ips_disable(struct dc *dc, unsigned int disable_ips);
2508
2509void dc_z10_restore(const struct dc *dc);
2510void dc_z10_save_init(struct dc *dc);
2511
2512bool dc_is_dmub_outbox_supported(struct dc *dc);
2513bool dc_enable_dmub_notifications(struct dc *dc);
2514
2515bool dc_abm_save_restore(
2516 struct dc *dc,
2517 struct dc_stream_state *stream,
2518 struct abm_save_restore *pData);
2519
2520void dc_enable_dmub_outbox(struct dc *dc);
2521
2522bool dc_process_dmub_aux_transfer_async(struct dc *dc,
2523 uint32_t link_index,
2524 struct aux_payload *payload);
2525
2526/* Get dc link index from dpia port index */
2527uint8_t get_link_index_from_dpia_port_index(const struct dc *dc,
2528 uint8_t dpia_port_index);
2529
2530bool dc_process_dmub_set_config_async(struct dc *dc,
2531 uint32_t link_index,
2532 struct set_config_cmd_payload *payload,
2533 struct dmub_notification *notify);
2534
2535enum dc_status dc_process_dmub_set_mst_slots(const struct dc *dc,
2536 uint32_t link_index,
2537 uint8_t mst_alloc_slots,
2538 uint8_t *mst_slots_in_use);
2539
2540void dc_process_dmub_dpia_set_tps_notification(const struct dc *dc, uint32_t link_index, uint8_t tps);
2541
2542void dc_process_dmub_dpia_hpd_int_enable(const struct dc *dc,
2543 uint32_t hpd_int_enable);
2544
2545void dc_print_dmub_diagnostic_data(const struct dc *dc);
2546
2547void dc_query_current_properties(struct dc *dc, struct dc_current_properties *properties);
2548
2549struct dc_power_profile {
2550 int power_level; /* Lower is better */
2551};
2552
2553struct dc_power_profile dc_get_power_profile_for_dc_state(const struct dc_state *context);
2554
2555unsigned int dc_get_det_buffer_size_from_state(const struct dc_state *context);
2556
2557/* DSC Interfaces */
2558#include "dc_dsc.h"
2559
2560/* Disable acc mode Interfaces */
2561void dc_disable_accelerated_mode(struct dc *dc);
2562
2563bool dc_is_timing_changed(struct dc_stream_state *cur_stream,
2564 struct dc_stream_state *new_stream);
2565
2566#endif /* DC_INTERFACE_H_ */