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1/*
2 * Copyright (c) 2018-2021 Advanced Micro Devices, Inc. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a copy
5 * of this software and associated documentation files (the "Software"), to deal
6 * in the Software without restriction, including without limitation the rights
7 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
8 * copies of the Software, and to permit persons to whom the Software is
9 * furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
17 * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
19 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
20 * THE SOFTWARE.
21 */
22
23#ifndef AMDGV_SRIOV_MSG__H_
24#define AMDGV_SRIOV_MSG__H_
25
26/* unit in kilobytes */
27#define AMD_SRIOV_MSG_VBIOS_OFFSET 0
28#define AMD_SRIOV_MSG_VBIOS_SIZE_KB 64
29#define AMD_SRIOV_MSG_DATAEXCHANGE_OFFSET_KB AMD_SRIOV_MSG_VBIOS_SIZE_KB
30#define AMD_SRIOV_MSG_DATAEXCHANGE_SIZE_KB 4
31#define AMD_SRIOV_MSG_TMR_OFFSET_KB 2048
32#define AMD_SRIOV_MSG_BAD_PAGE_SIZE_KB 2
33#define AMD_SRIOV_RAS_TELEMETRY_SIZE_KB 64
34/*
35 * layout
36 * 0 64KB 65KB 66KB 68KB 132KB
37 * | VBIOS | PF2VF | VF2PF | Bad Page | RAS Telemetry Region | ...
38 * | 64KB | 1KB | 1KB | 2KB | 64KB | ...
39 */
40
41#define AMD_SRIOV_MSG_SIZE_KB 1
42#define AMD_SRIOV_MSG_PF2VF_OFFSET_KB AMD_SRIOV_MSG_DATAEXCHANGE_OFFSET_KB
43#define AMD_SRIOV_MSG_VF2PF_OFFSET_KB (AMD_SRIOV_MSG_PF2VF_OFFSET_KB + AMD_SRIOV_MSG_SIZE_KB)
44#define AMD_SRIOV_MSG_BAD_PAGE_OFFSET_KB (AMD_SRIOV_MSG_VF2PF_OFFSET_KB + AMD_SRIOV_MSG_SIZE_KB)
45#define AMD_SRIOV_MSG_RAS_TELEMETRY_OFFSET_KB (AMD_SRIOV_MSG_BAD_PAGE_OFFSET_KB + AMD_SRIOV_MSG_BAD_PAGE_SIZE_KB)
46
47/*
48 * PF2VF history log:
49 * v1 defined in amdgim
50 * v2 current
51 *
52 * VF2PF history log:
53 * v1 defined in amdgim
54 * v2 defined in amdgim
55 * v3 current
56 */
57#define AMD_SRIOV_MSG_FW_VRAM_PF2VF_VER 2
58#define AMD_SRIOV_MSG_FW_VRAM_VF2PF_VER 3
59
60#define AMD_SRIOV_MSG_RESERVE_UCODE 24
61
62#define AMD_SRIOV_MSG_RESERVE_VCN_INST 4
63
64enum amd_sriov_ucode_engine_id {
65 AMD_SRIOV_UCODE_ID_VCE = 0,
66 AMD_SRIOV_UCODE_ID_UVD,
67 AMD_SRIOV_UCODE_ID_MC,
68 AMD_SRIOV_UCODE_ID_ME,
69 AMD_SRIOV_UCODE_ID_PFP,
70 AMD_SRIOV_UCODE_ID_CE,
71 AMD_SRIOV_UCODE_ID_RLC,
72 AMD_SRIOV_UCODE_ID_RLC_SRLC,
73 AMD_SRIOV_UCODE_ID_RLC_SRLG,
74 AMD_SRIOV_UCODE_ID_RLC_SRLS,
75 AMD_SRIOV_UCODE_ID_MEC,
76 AMD_SRIOV_UCODE_ID_MEC2,
77 AMD_SRIOV_UCODE_ID_SOS,
78 AMD_SRIOV_UCODE_ID_ASD,
79 AMD_SRIOV_UCODE_ID_TA_RAS,
80 AMD_SRIOV_UCODE_ID_TA_XGMI,
81 AMD_SRIOV_UCODE_ID_SMC,
82 AMD_SRIOV_UCODE_ID_SDMA,
83 AMD_SRIOV_UCODE_ID_SDMA2,
84 AMD_SRIOV_UCODE_ID_VCN,
85 AMD_SRIOV_UCODE_ID_DMCU,
86 AMD_SRIOV_UCODE_ID__MAX
87};
88
89#pragma pack(push, 1) // PF2VF / VF2PF data areas are byte packed
90
91union amd_sriov_msg_feature_flags {
92 struct {
93 uint32_t error_log_collect : 1;
94 uint32_t host_load_ucodes : 1;
95 uint32_t host_flr_vramlost : 1;
96 uint32_t mm_bw_management : 1;
97 uint32_t pp_one_vf_mode : 1;
98 uint32_t reg_indirect_acc : 1;
99 uint32_t av1_support : 1;
100 uint32_t vcn_rb_decouple : 1;
101 uint32_t mes_info_dump_enable : 1;
102 uint32_t ras_caps : 1;
103 uint32_t ras_telemetry : 1;
104 uint32_t reserved : 21;
105 } flags;
106 uint32_t all;
107};
108
109union amd_sriov_reg_access_flags {
110 struct {
111 uint32_t vf_reg_access_ih : 1;
112 uint32_t vf_reg_access_mmhub : 1;
113 uint32_t vf_reg_access_gc : 1;
114 uint32_t reserved : 29;
115 } flags;
116 uint32_t all;
117};
118
119union amd_sriov_ras_caps {
120 struct {
121 uint64_t block_umc : 1;
122 uint64_t block_sdma : 1;
123 uint64_t block_gfx : 1;
124 uint64_t block_mmhub : 1;
125 uint64_t block_athub : 1;
126 uint64_t block_pcie_bif : 1;
127 uint64_t block_hdp : 1;
128 uint64_t block_xgmi_wafl : 1;
129 uint64_t block_df : 1;
130 uint64_t block_smn : 1;
131 uint64_t block_sem : 1;
132 uint64_t block_mp0 : 1;
133 uint64_t block_mp1 : 1;
134 uint64_t block_fuse : 1;
135 uint64_t block_mca : 1;
136 uint64_t block_vcn : 1;
137 uint64_t block_jpeg : 1;
138 uint64_t block_ih : 1;
139 uint64_t block_mpio : 1;
140 uint64_t poison_propogation_mode : 1;
141 uint64_t reserved : 44;
142 } bits;
143 uint64_t all;
144};
145
146union amd_sriov_msg_os_info {
147 struct {
148 uint32_t windows : 1;
149 uint32_t reserved : 31;
150 } info;
151 uint32_t all;
152};
153
154struct amd_sriov_msg_uuid_info {
155 union {
156 struct {
157 uint32_t did : 16;
158 uint32_t fcn : 8;
159 uint32_t asic_7 : 8;
160 };
161 uint32_t time_low;
162 };
163
164 struct {
165 uint32_t time_mid : 16;
166 uint32_t time_high : 12;
167 uint32_t version : 4;
168 };
169
170 struct {
171 struct {
172 uint8_t clk_seq_hi : 6;
173 uint8_t variant : 2;
174 };
175 union {
176 uint8_t clk_seq_low;
177 uint8_t asic_6;
178 };
179 uint16_t asic_4;
180 };
181
182 uint32_t asic_0;
183};
184
185struct amd_sriov_msg_pf2vf_info_header {
186 /* the total structure size in byte */
187 uint32_t size;
188 /* version of this structure, written by the HOST */
189 uint32_t version;
190 /* reserved */
191 uint32_t reserved[2];
192};
193
194#define AMD_SRIOV_MSG_PF2VF_INFO_FILLED_SIZE (55)
195struct amd_sriov_msg_pf2vf_info {
196 /* header contains size and version */
197 struct amd_sriov_msg_pf2vf_info_header header;
198 /* use private key from mailbox 2 to create checksum */
199 uint32_t checksum;
200 /* The features flags of the HOST driver supports */
201 union amd_sriov_msg_feature_flags feature_flags;
202 /* (max_width * max_height * fps) / (16 * 16) */
203 uint32_t hevc_enc_max_mb_per_second;
204 /* (max_width * max_height) / (16 * 16) */
205 uint32_t hevc_enc_max_mb_per_frame;
206 /* (max_width * max_height * fps) / (16 * 16) */
207 uint32_t avc_enc_max_mb_per_second;
208 /* (max_width * max_height) / (16 * 16) */
209 uint32_t avc_enc_max_mb_per_frame;
210 /* MEC FW position in BYTE from the start of VF visible frame buffer */
211 uint64_t mecfw_offset;
212 /* MEC FW size in BYTE */
213 uint32_t mecfw_size;
214 /* UVD FW position in BYTE from the start of VF visible frame buffer */
215 uint64_t uvdfw_offset;
216 /* UVD FW size in BYTE */
217 uint32_t uvdfw_size;
218 /* VCE FW position in BYTE from the start of VF visible frame buffer */
219 uint64_t vcefw_offset;
220 /* VCE FW size in BYTE */
221 uint32_t vcefw_size;
222 /* Bad pages block position in BYTE */
223 uint32_t bp_block_offset_low;
224 uint32_t bp_block_offset_high;
225 /* Bad pages block size in BYTE */
226 uint32_t bp_block_size;
227 /* frequency for VF to update the VF2PF area in msec, 0 = manual */
228 uint32_t vf2pf_update_interval_ms;
229 /* identification in ROCm SMI */
230 uint64_t uuid;
231 uint32_t fcn_idx;
232 /* flags to indicate which register access method VF should use */
233 union amd_sriov_reg_access_flags reg_access_flags;
234 /* MM BW management */
235 struct {
236 uint32_t decode_max_dimension_pixels;
237 uint32_t decode_max_frame_pixels;
238 uint32_t encode_max_dimension_pixels;
239 uint32_t encode_max_frame_pixels;
240 } mm_bw_management[AMD_SRIOV_MSG_RESERVE_VCN_INST];
241 /* UUID info */
242 struct amd_sriov_msg_uuid_info uuid_info;
243 /* PCIE atomic ops support flag */
244 uint32_t pcie_atomic_ops_support_flags;
245 /* Portion of GPU memory occupied by VF. MAX value is 65535, but set to uint32_t to maintain alignment with reserved size */
246 uint32_t gpu_capacity;
247 /* vf bdf on host pci tree for debug only */
248 uint32_t bdf_on_host;
249 uint32_t more_bp; //Reserved for future use.
250 union amd_sriov_ras_caps ras_en_caps;
251 union amd_sriov_ras_caps ras_telemetry_en_caps;
252
253 /* reserved */
254 uint32_t reserved[256 - AMD_SRIOV_MSG_PF2VF_INFO_FILLED_SIZE];
255} __packed;
256
257struct amd_sriov_msg_vf2pf_info_header {
258 /* the total structure size in byte */
259 uint32_t size;
260 /* version of this structure, written by the guest */
261 uint32_t version;
262 /* reserved */
263 uint32_t reserved[2];
264};
265
266#define AMD_SRIOV_MSG_VF2PF_INFO_FILLED_SIZE (73)
267struct amd_sriov_msg_vf2pf_info {
268 /* header contains size and version */
269 struct amd_sriov_msg_vf2pf_info_header header;
270 uint32_t checksum;
271 /* driver version */
272 uint8_t driver_version[64];
273 /* driver certification, 1=WHQL, 0=None */
274 uint32_t driver_cert;
275 /* guest OS type and version */
276 union amd_sriov_msg_os_info os_info;
277 /* guest fb information in the unit of MB */
278 uint32_t fb_usage;
279 /* guest gfx engine usage percentage */
280 uint32_t gfx_usage;
281 /* guest gfx engine health percentage */
282 uint32_t gfx_health;
283 /* guest compute engine usage percentage */
284 uint32_t compute_usage;
285 /* guest compute engine health percentage */
286 uint32_t compute_health;
287 /* guest avc engine usage percentage. 0xffff means N/A */
288 uint32_t avc_enc_usage;
289 /* guest avc engine health percentage. 0xffff means N/A */
290 uint32_t avc_enc_health;
291 /* guest hevc engine usage percentage. 0xffff means N/A */
292 uint32_t hevc_enc_usage;
293 /* guest hevc engine usage percentage. 0xffff means N/A */
294 uint32_t hevc_enc_health;
295 /* combined encode/decode usage */
296 uint32_t encode_usage;
297 uint32_t decode_usage;
298 /* Version of PF2VF that VF understands */
299 uint32_t pf2vf_version_required;
300 /* additional FB usage */
301 uint32_t fb_vis_usage;
302 uint32_t fb_vis_size;
303 uint32_t fb_size;
304 /* guest ucode data, each one is 1.25 Dword */
305 struct {
306 uint8_t id;
307 uint32_t version;
308 } ucode_info[AMD_SRIOV_MSG_RESERVE_UCODE];
309 uint64_t dummy_page_addr;
310 /* FB allocated for guest MES to record UQ info */
311 uint64_t mes_info_addr;
312 uint32_t mes_info_size;
313 /* reserved */
314 uint32_t reserved[256 - AMD_SRIOV_MSG_VF2PF_INFO_FILLED_SIZE];
315} __packed;
316
317/* mailbox message send from guest to host */
318enum amd_sriov_mailbox_request_message {
319 MB_REQ_MSG_REQ_GPU_INIT_ACCESS = 1,
320 MB_REQ_MSG_REL_GPU_INIT_ACCESS,
321 MB_REQ_MSG_REQ_GPU_FINI_ACCESS,
322 MB_REQ_MSG_REL_GPU_FINI_ACCESS,
323 MB_REQ_MSG_REQ_GPU_RESET_ACCESS,
324 MB_REQ_MSG_REQ_GPU_INIT_DATA,
325 MB_REQ_MSG_PSP_VF_CMD_RELAY,
326
327 MB_REQ_MSG_LOG_VF_ERROR = 200,
328 MB_REQ_MSG_READY_TO_RESET = 201,
329 MB_REQ_MSG_RAS_POISON = 202,
330 MB_REQ_RAS_ERROR_COUNT = 203,
331};
332
333/* mailbox message send from host to guest */
334enum amd_sriov_mailbox_response_message {
335 MB_RES_MSG_CLR_MSG_BUF = 0,
336 MB_RES_MSG_READY_TO_ACCESS_GPU = 1,
337 MB_RES_MSG_FLR_NOTIFICATION,
338 MB_RES_MSG_FLR_NOTIFICATION_COMPLETION,
339 MB_RES_MSG_SUCCESS,
340 MB_RES_MSG_FAIL,
341 MB_RES_MSG_QUERY_ALIVE,
342 MB_RES_MSG_GPU_INIT_DATA_READY,
343 MB_RES_MSG_RAS_ERROR_COUNT_READY = 11,
344
345 MB_RES_MSG_TEXT_MESSAGE = 255
346};
347
348enum amd_sriov_ras_telemetry_gpu_block {
349 RAS_TELEMETRY_GPU_BLOCK_UMC = 0,
350 RAS_TELEMETRY_GPU_BLOCK_SDMA = 1,
351 RAS_TELEMETRY_GPU_BLOCK_GFX = 2,
352 RAS_TELEMETRY_GPU_BLOCK_MMHUB = 3,
353 RAS_TELEMETRY_GPU_BLOCK_ATHUB = 4,
354 RAS_TELEMETRY_GPU_BLOCK_PCIE_BIF = 5,
355 RAS_TELEMETRY_GPU_BLOCK_HDP = 6,
356 RAS_TELEMETRY_GPU_BLOCK_XGMI_WAFL = 7,
357 RAS_TELEMETRY_GPU_BLOCK_DF = 8,
358 RAS_TELEMETRY_GPU_BLOCK_SMN = 9,
359 RAS_TELEMETRY_GPU_BLOCK_SEM = 10,
360 RAS_TELEMETRY_GPU_BLOCK_MP0 = 11,
361 RAS_TELEMETRY_GPU_BLOCK_MP1 = 12,
362 RAS_TELEMETRY_GPU_BLOCK_FUSE = 13,
363 RAS_TELEMETRY_GPU_BLOCK_MCA = 14,
364 RAS_TELEMETRY_GPU_BLOCK_VCN = 15,
365 RAS_TELEMETRY_GPU_BLOCK_JPEG = 16,
366 RAS_TELEMETRY_GPU_BLOCK_IH = 17,
367 RAS_TELEMETRY_GPU_BLOCK_MPIO = 18,
368 RAS_TELEMETRY_GPU_BLOCK_COUNT = 19,
369};
370
371struct amd_sriov_ras_telemetry_header {
372 uint32_t checksum;
373 uint32_t used_size;
374 uint32_t reserved[2];
375};
376
377struct amd_sriov_ras_telemetry_error_count {
378 struct {
379 uint32_t ce_count;
380 uint32_t ue_count;
381 uint32_t de_count;
382 uint32_t ce_overflow_count;
383 uint32_t ue_overflow_count;
384 uint32_t de_overflow_count;
385 uint32_t reserved[6];
386 } block[RAS_TELEMETRY_GPU_BLOCK_COUNT];
387};
388
389struct amdsriov_ras_telemetry {
390 struct amd_sriov_ras_telemetry_header header;
391
392 union {
393 struct amd_sriov_ras_telemetry_error_count error_count;
394 } body;
395};
396
397/* version data stored in MAILBOX_MSGBUF_RCV_DW1 for future expansion */
398enum amd_sriov_gpu_init_data_version {
399 GPU_INIT_DATA_READY_V1 = 1,
400};
401
402#pragma pack(pop) // Restore previous packing option
403
404/* checksum function between host and guest */
405unsigned int amd_sriov_msg_checksum(void *obj, unsigned long obj_size, unsigned int key,
406 unsigned int checksum);
407
408/* assertion at compile time */
409#ifdef __linux__
410#define stringification(s) _stringification(s)
411#define _stringification(s) #s
412
413_Static_assert(
414 sizeof(struct amd_sriov_msg_vf2pf_info) == AMD_SRIOV_MSG_SIZE_KB << 10,
415 "amd_sriov_msg_vf2pf_info must be " stringification(AMD_SRIOV_MSG_SIZE_KB) " KB");
416
417_Static_assert(
418 sizeof(struct amd_sriov_msg_pf2vf_info) == AMD_SRIOV_MSG_SIZE_KB << 10,
419 "amd_sriov_msg_pf2vf_info must be " stringification(AMD_SRIOV_MSG_SIZE_KB) " KB");
420
421_Static_assert(AMD_SRIOV_MSG_RESERVE_UCODE % 4 == 0,
422 "AMD_SRIOV_MSG_RESERVE_UCODE must be multiple of 4");
423
424_Static_assert(AMD_SRIOV_MSG_RESERVE_UCODE > AMD_SRIOV_UCODE_ID__MAX,
425 "AMD_SRIOV_MSG_RESERVE_UCODE must be bigger than AMD_SRIOV_UCODE_ID__MAX");
426
427#undef _stringification
428#undef stringification
429#endif
430
431#endif /* AMDGV_SRIOV_MSG__H_ */