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1/*
2 * Copyright (c) 2018-2021 Advanced Micro Devices, Inc. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a copy
5 * of this software and associated documentation files (the "Software"), to deal
6 * in the Software without restriction, including without limitation the rights
7 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
8 * copies of the Software, and to permit persons to whom the Software is
9 * furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
17 * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
19 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
20 * THE SOFTWARE.
21 */
22
23#ifndef AMDGV_SRIOV_MSG__H_
24#define AMDGV_SRIOV_MSG__H_
25
26/* unit in kilobytes */
27#define AMD_SRIOV_MSG_VBIOS_OFFSET 0
28#define AMD_SRIOV_MSG_VBIOS_SIZE_KB 64
29#define AMD_SRIOV_MSG_DATAEXCHANGE_OFFSET_KB AMD_SRIOV_MSG_VBIOS_SIZE_KB
30#define AMD_SRIOV_MSG_DATAEXCHANGE_SIZE_KB 4
31
32/*
33 * layout
34 * 0 64KB 65KB 66KB
35 * | VBIOS | PF2VF | VF2PF | Bad Page | ...
36 * | 64KB | 1KB | 1KB |
37 */
38#define AMD_SRIOV_MSG_SIZE_KB 1
39#define AMD_SRIOV_MSG_PF2VF_OFFSET_KB AMD_SRIOV_MSG_DATAEXCHANGE_OFFSET_KB
40#define AMD_SRIOV_MSG_VF2PF_OFFSET_KB (AMD_SRIOV_MSG_PF2VF_OFFSET_KB + AMD_SRIOV_MSG_SIZE_KB)
41#define AMD_SRIOV_MSG_BAD_PAGE_OFFSET_KB (AMD_SRIOV_MSG_VF2PF_OFFSET_KB + AMD_SRIOV_MSG_SIZE_KB)
42
43/*
44 * PF2VF history log:
45 * v1 defined in amdgim
46 * v2 current
47 *
48 * VF2PF history log:
49 * v1 defined in amdgim
50 * v2 defined in amdgim
51 * v3 current
52 */
53#define AMD_SRIOV_MSG_FW_VRAM_PF2VF_VER 2
54#define AMD_SRIOV_MSG_FW_VRAM_VF2PF_VER 3
55
56#define AMD_SRIOV_MSG_RESERVE_UCODE 24
57
58#define AMD_SRIOV_MSG_RESERVE_VCN_INST 4
59
60enum amd_sriov_ucode_engine_id {
61 AMD_SRIOV_UCODE_ID_VCE = 0,
62 AMD_SRIOV_UCODE_ID_UVD,
63 AMD_SRIOV_UCODE_ID_MC,
64 AMD_SRIOV_UCODE_ID_ME,
65 AMD_SRIOV_UCODE_ID_PFP,
66 AMD_SRIOV_UCODE_ID_CE,
67 AMD_SRIOV_UCODE_ID_RLC,
68 AMD_SRIOV_UCODE_ID_RLC_SRLC,
69 AMD_SRIOV_UCODE_ID_RLC_SRLG,
70 AMD_SRIOV_UCODE_ID_RLC_SRLS,
71 AMD_SRIOV_UCODE_ID_MEC,
72 AMD_SRIOV_UCODE_ID_MEC2,
73 AMD_SRIOV_UCODE_ID_IMU,
74 AMD_SRIOV_UCODE_ID_SOS,
75 AMD_SRIOV_UCODE_ID_ASD,
76 AMD_SRIOV_UCODE_ID_TA_RAS,
77 AMD_SRIOV_UCODE_ID_TA_XGMI,
78 AMD_SRIOV_UCODE_ID_SMC,
79 AMD_SRIOV_UCODE_ID_SDMA,
80 AMD_SRIOV_UCODE_ID_SDMA2,
81 AMD_SRIOV_UCODE_ID_VCN,
82 AMD_SRIOV_UCODE_ID_DMCU,
83 AMD_SRIOV_UCODE_ID__MAX
84};
85
86#pragma pack(push, 1) // PF2VF / VF2PF data areas are byte packed
87
88union amd_sriov_msg_feature_flags {
89 struct {
90 uint32_t error_log_collect : 1;
91 uint32_t host_load_ucodes : 1;
92 uint32_t host_flr_vramlost : 1;
93 uint32_t mm_bw_management : 1;
94 uint32_t pp_one_vf_mode : 1;
95 uint32_t reg_indirect_acc : 1;
96 uint32_t reserved : 26;
97 } flags;
98 uint32_t all;
99};
100
101union amd_sriov_reg_access_flags {
102 struct {
103 uint32_t vf_reg_access_ih : 1;
104 uint32_t vf_reg_access_mmhub : 1;
105 uint32_t vf_reg_access_gc : 1;
106 uint32_t reserved : 29;
107 } flags;
108 uint32_t all;
109};
110
111union amd_sriov_msg_os_info {
112 struct {
113 uint32_t windows : 1;
114 uint32_t reserved : 31;
115 } info;
116 uint32_t all;
117};
118
119struct amd_sriov_msg_uuid_info {
120 union {
121 struct {
122 uint32_t did : 16;
123 uint32_t fcn : 8;
124 uint32_t asic_7 : 8;
125 };
126 uint32_t time_low;
127 };
128
129 struct {
130 uint32_t time_mid : 16;
131 uint32_t time_high : 12;
132 uint32_t version : 4;
133 };
134
135 struct {
136 struct {
137 uint8_t clk_seq_hi : 6;
138 uint8_t variant : 2;
139 };
140 union {
141 uint8_t clk_seq_low;
142 uint8_t asic_6;
143 };
144 uint16_t asic_4;
145 };
146
147 uint32_t asic_0;
148};
149
150struct amd_sriov_msg_pf2vf_info_header {
151 /* the total structure size in byte */
152 uint32_t size;
153 /* version of this structure, written by the HOST */
154 uint32_t version;
155 /* reserved */
156 uint32_t reserved[2];
157};
158
159#define AMD_SRIOV_MSG_PF2VF_INFO_FILLED_SIZE (48)
160struct amd_sriov_msg_pf2vf_info {
161 /* header contains size and version */
162 struct amd_sriov_msg_pf2vf_info_header header;
163 /* use private key from mailbox 2 to create checksum */
164 uint32_t checksum;
165 /* The features flags of the HOST driver supports */
166 union amd_sriov_msg_feature_flags feature_flags;
167 /* (max_width * max_height * fps) / (16 * 16) */
168 uint32_t hevc_enc_max_mb_per_second;
169 /* (max_width * max_height) / (16 * 16) */
170 uint32_t hevc_enc_max_mb_per_frame;
171 /* (max_width * max_height * fps) / (16 * 16) */
172 uint32_t avc_enc_max_mb_per_second;
173 /* (max_width * max_height) / (16 * 16) */
174 uint32_t avc_enc_max_mb_per_frame;
175 /* MEC FW position in BYTE from the start of VF visible frame buffer */
176 uint64_t mecfw_offset;
177 /* MEC FW size in BYTE */
178 uint32_t mecfw_size;
179 /* UVD FW position in BYTE from the start of VF visible frame buffer */
180 uint64_t uvdfw_offset;
181 /* UVD FW size in BYTE */
182 uint32_t uvdfw_size;
183 /* VCE FW position in BYTE from the start of VF visible frame buffer */
184 uint64_t vcefw_offset;
185 /* VCE FW size in BYTE */
186 uint32_t vcefw_size;
187 /* Bad pages block position in BYTE */
188 uint32_t bp_block_offset_low;
189 uint32_t bp_block_offset_high;
190 /* Bad pages block size in BYTE */
191 uint32_t bp_block_size;
192 /* frequency for VF to update the VF2PF area in msec, 0 = manual */
193 uint32_t vf2pf_update_interval_ms;
194 /* identification in ROCm SMI */
195 uint64_t uuid;
196 uint32_t fcn_idx;
197 /* flags to indicate which register access method VF should use */
198 union amd_sriov_reg_access_flags reg_access_flags;
199 /* MM BW management */
200 struct {
201 uint32_t decode_max_dimension_pixels;
202 uint32_t decode_max_frame_pixels;
203 uint32_t encode_max_dimension_pixels;
204 uint32_t encode_max_frame_pixels;
205 } mm_bw_management[AMD_SRIOV_MSG_RESERVE_VCN_INST];
206 /* UUID info */
207 struct amd_sriov_msg_uuid_info uuid_info;
208 /* PCIE atomic ops support flag */
209 uint32_t pcie_atomic_ops_support_flags;
210 /* reserved */
211 uint32_t reserved[256 - AMD_SRIOV_MSG_PF2VF_INFO_FILLED_SIZE];
212};
213
214struct amd_sriov_msg_vf2pf_info_header {
215 /* the total structure size in byte */
216 uint32_t size;
217 /* version of this structure, written by the guest */
218 uint32_t version;
219 /* reserved */
220 uint32_t reserved[2];
221};
222
223#define AMD_SRIOV_MSG_VF2PF_INFO_FILLED_SIZE (70)
224struct amd_sriov_msg_vf2pf_info {
225 /* header contains size and version */
226 struct amd_sriov_msg_vf2pf_info_header header;
227 uint32_t checksum;
228 /* driver version */
229 uint8_t driver_version[64];
230 /* driver certification, 1=WHQL, 0=None */
231 uint32_t driver_cert;
232 /* guest OS type and version */
233 union amd_sriov_msg_os_info os_info;
234 /* guest fb information in the unit of MB */
235 uint32_t fb_usage;
236 /* guest gfx engine usage percentage */
237 uint32_t gfx_usage;
238 /* guest gfx engine health percentage */
239 uint32_t gfx_health;
240 /* guest compute engine usage percentage */
241 uint32_t compute_usage;
242 /* guest compute engine health percentage */
243 uint32_t compute_health;
244 /* guest avc engine usage percentage. 0xffff means N/A */
245 uint32_t avc_enc_usage;
246 /* guest avc engine health percentage. 0xffff means N/A */
247 uint32_t avc_enc_health;
248 /* guest hevc engine usage percentage. 0xffff means N/A */
249 uint32_t hevc_enc_usage;
250 /* guest hevc engine usage percentage. 0xffff means N/A */
251 uint32_t hevc_enc_health;
252 /* combined encode/decode usage */
253 uint32_t encode_usage;
254 uint32_t decode_usage;
255 /* Version of PF2VF that VF understands */
256 uint32_t pf2vf_version_required;
257 /* additional FB usage */
258 uint32_t fb_vis_usage;
259 uint32_t fb_vis_size;
260 uint32_t fb_size;
261 /* guest ucode data, each one is 1.25 Dword */
262 struct {
263 uint8_t id;
264 uint32_t version;
265 } ucode_info[AMD_SRIOV_MSG_RESERVE_UCODE];
266 uint64_t dummy_page_addr;
267
268 /* reserved */
269 uint32_t reserved[256 - AMD_SRIOV_MSG_VF2PF_INFO_FILLED_SIZE];
270};
271
272/* mailbox message send from guest to host */
273enum amd_sriov_mailbox_request_message {
274 MB_REQ_MSG_REQ_GPU_INIT_ACCESS = 1,
275 MB_REQ_MSG_REL_GPU_INIT_ACCESS,
276 MB_REQ_MSG_REQ_GPU_FINI_ACCESS,
277 MB_REQ_MSG_REL_GPU_FINI_ACCESS,
278 MB_REQ_MSG_REQ_GPU_RESET_ACCESS,
279 MB_REQ_MSG_REQ_GPU_INIT_DATA,
280
281 MB_REQ_MSG_LOG_VF_ERROR = 200,
282};
283
284/* mailbox message send from host to guest */
285enum amd_sriov_mailbox_response_message {
286 MB_RES_MSG_CLR_MSG_BUF = 0,
287 MB_RES_MSG_READY_TO_ACCESS_GPU = 1,
288 MB_RES_MSG_FLR_NOTIFICATION,
289 MB_RES_MSG_FLR_NOTIFICATION_COMPLETION,
290 MB_RES_MSG_SUCCESS,
291 MB_RES_MSG_FAIL,
292 MB_RES_MSG_QUERY_ALIVE,
293 MB_RES_MSG_GPU_INIT_DATA_READY,
294
295 MB_RES_MSG_TEXT_MESSAGE = 255
296};
297
298/* version data stored in MAILBOX_MSGBUF_RCV_DW1 for future expansion */
299enum amd_sriov_gpu_init_data_version {
300 GPU_INIT_DATA_READY_V1 = 1,
301};
302
303#pragma pack(pop) // Restore previous packing option
304
305/* checksum function between host and guest */
306unsigned int amd_sriov_msg_checksum(void *obj, unsigned long obj_size, unsigned int key,
307 unsigned int checksum);
308
309/* assertion at compile time */
310#ifdef __linux__
311#define stringification(s) _stringification(s)
312#define _stringification(s) #s
313
314_Static_assert(
315 sizeof(struct amd_sriov_msg_vf2pf_info) == AMD_SRIOV_MSG_SIZE_KB << 10,
316 "amd_sriov_msg_vf2pf_info must be " stringification(AMD_SRIOV_MSG_SIZE_KB) " KB");
317
318_Static_assert(
319 sizeof(struct amd_sriov_msg_pf2vf_info) == AMD_SRIOV_MSG_SIZE_KB << 10,
320 "amd_sriov_msg_pf2vf_info must be " stringification(AMD_SRIOV_MSG_SIZE_KB) " KB");
321
322_Static_assert(AMD_SRIOV_MSG_RESERVE_UCODE % 4 == 0,
323 "AMD_SRIOV_MSG_RESERVE_UCODE must be multiple of 4");
324
325_Static_assert(AMD_SRIOV_MSG_RESERVE_UCODE > AMD_SRIOV_UCODE_ID__MAX,
326 "AMD_SRIOV_MSG_RESERVE_UCODE must be bigger than AMD_SRIOV_UCODE_ID__MAX");
327
328#undef _stringification
329#undef stringification
330#endif
331
332#endif /* AMDGV_SRIOV_MSG__H_ */