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1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Core pinctrl/GPIO driver for Intel GPIO controllers
4 *
5 * Copyright (C) 2015, Intel Corporation
6 * Authors: Mathias Nyman <mathias.nyman@linux.intel.com>
7 * Mika Westerberg <mika.westerberg@linux.intel.com>
8 */
9
10#ifndef PINCTRL_INTEL_H
11#define PINCTRL_INTEL_H
12
13#include <linux/gpio/driver.h>
14#include <linux/irq.h>
15#include <linux/pm.h>
16#include <linux/spinlock_types.h>
17
18struct pinctrl_pin_desc;
19struct platform_device;
20struct device;
21
22/**
23 * struct intel_pingroup - Description about group of pins
24 * @name: Name of the groups
25 * @pins: All pins in this group
26 * @npins: Number of pins in this groups
27 * @mode: Native mode in which the group is muxed out @pins. Used if @modes
28 * is %NULL.
29 * @modes: If not %NULL this will hold mode for each pin in @pins
30 */
31struct intel_pingroup {
32 const char *name;
33 const unsigned int *pins;
34 size_t npins;
35 unsigned short mode;
36 const unsigned int *modes;
37};
38
39/**
40 * struct intel_function - Description about a function
41 * @name: Name of the function
42 * @groups: An array of groups for this function
43 * @ngroups: Number of groups in @groups
44 */
45struct intel_function {
46 const char *name;
47 const char * const *groups;
48 size_t ngroups;
49};
50
51/**
52 * struct intel_padgroup - Hardware pad group information
53 * @reg_num: GPI_IS register number
54 * @base: Starting pin of this group
55 * @size: Size of this group (maximum is 32).
56 * @gpio_base: Starting GPIO base of this group
57 * @padown_num: PAD_OWN register number (assigned by the core driver)
58 *
59 * If pad groups of a community are not the same size, use this structure
60 * to specify them.
61 */
62struct intel_padgroup {
63 unsigned int reg_num;
64 unsigned int base;
65 unsigned int size;
66 int gpio_base;
67 unsigned int padown_num;
68};
69
70/**
71 * enum - Special treatment for GPIO base in pad group
72 *
73 * @INTEL_GPIO_BASE_ZERO: force GPIO base to be 0
74 * @INTEL_GPIO_BASE_NOMAP: no GPIO mapping should be created
75 * @INTEL_GPIO_BASE_MATCH: matches with starting pin number
76 */
77enum {
78 INTEL_GPIO_BASE_ZERO = -2,
79 INTEL_GPIO_BASE_NOMAP = -1,
80 INTEL_GPIO_BASE_MATCH = 0,
81};
82
83/**
84 * struct intel_community - Intel pin community description
85 * @barno: MMIO BAR number where registers for this community reside
86 * @padown_offset: Register offset of PAD_OWN register from @regs. If %0
87 * then there is no support for owner.
88 * @padcfglock_offset: Register offset of PADCFGLOCK from @regs. If %0 then
89 * locking is not supported.
90 * @hostown_offset: Register offset of HOSTSW_OWN from @regs. If %0 then it
91 * is assumed that the host owns the pin (rather than
92 * ACPI).
93 * @is_offset: Register offset of GPI_IS from @regs.
94 * @ie_offset: Register offset of GPI_IE from @regs.
95 * @features: Additional features supported by the hardware
96 * @pin_base: Starting pin of pins in this community
97 * @npins: Number of pins in this community
98 * @gpp_size: Maximum number of pads in each group, such as PADCFGLOCK,
99 * HOSTSW_OWN, GPI_IS, GPI_IE. Used when @gpps is %NULL.
100 * @gpp_num_padown_regs: Number of pad registers each pad group consumes at
101 * minimum. Use %0 if the number of registers can be
102 * determined by the size of the group.
103 * @gpps: Pad groups if the controller has variable size pad groups
104 * @ngpps: Number of pad groups in this community
105 * @pad_map: Optional non-linear mapping of the pads
106 * @nirqs: Optional total number of IRQs this community can generate
107 * @acpi_space_id: Optional address space ID for ACPI OpRegion handler
108 * @regs: Community specific common registers (reserved for core driver)
109 * @pad_regs: Community specific pad registers (reserved for core driver)
110 *
111 * In some of Intel GPIO host controllers this driver supports each pad group
112 * is of equal size (except the last one). In that case the driver can just
113 * fill in @gpp_size field and let the core driver to handle the rest. If
114 * the controller has pad groups of variable size the client driver can
115 * pass custom @gpps and @ngpps instead.
116 */
117struct intel_community {
118 unsigned int barno;
119 unsigned int padown_offset;
120 unsigned int padcfglock_offset;
121 unsigned int hostown_offset;
122 unsigned int is_offset;
123 unsigned int ie_offset;
124 unsigned int features;
125 unsigned int pin_base;
126 size_t npins;
127 unsigned int gpp_size;
128 unsigned int gpp_num_padown_regs;
129 const struct intel_padgroup *gpps;
130 size_t ngpps;
131 const unsigned int *pad_map;
132 unsigned short nirqs;
133 unsigned short acpi_space_id;
134
135 /* Reserved for the core driver */
136 void __iomem *regs;
137 void __iomem *pad_regs;
138};
139
140/* Additional features supported by the hardware */
141#define PINCTRL_FEATURE_DEBOUNCE BIT(0)
142#define PINCTRL_FEATURE_1K_PD BIT(1)
143
144/**
145 * PIN_GROUP - Declare a pin group
146 * @n: Name of the group
147 * @p: An array of pins this group consists
148 * @m: Mode which the pins are put when this group is active. Can be either
149 * a single integer or an array of integers in which case mode is per
150 * pin.
151 */
152#define PIN_GROUP(n, p, m) \
153 { \
154 .name = (n), \
155 .pins = (p), \
156 .npins = ARRAY_SIZE((p)), \
157 .mode = __builtin_choose_expr( \
158 __builtin_constant_p((m)), (m), 0), \
159 .modes = __builtin_choose_expr( \
160 __builtin_constant_p((m)), NULL, (m)), \
161 }
162
163#define FUNCTION(n, g) \
164 { \
165 .name = (n), \
166 .groups = (g), \
167 .ngroups = ARRAY_SIZE((g)), \
168 }
169
170/**
171 * struct intel_pinctrl_soc_data - Intel pin controller per-SoC configuration
172 * @uid: ACPI _UID for the probe driver use if needed
173 * @pins: Array if pins this pinctrl controls
174 * @npins: Number of pins in the array
175 * @groups: Array of pin groups
176 * @ngroups: Number of groups in the array
177 * @functions: Array of functions
178 * @nfunctions: Number of functions in the array
179 * @communities: Array of communities this pinctrl handles
180 * @ncommunities: Number of communities in the array
181 *
182 * The @communities is used as a template by the core driver. It will make
183 * copy of all communities and fill in rest of the information.
184 */
185struct intel_pinctrl_soc_data {
186 const char *uid;
187 const struct pinctrl_pin_desc *pins;
188 size_t npins;
189 const struct intel_pingroup *groups;
190 size_t ngroups;
191 const struct intel_function *functions;
192 size_t nfunctions;
193 const struct intel_community *communities;
194 size_t ncommunities;
195};
196
197struct intel_pad_context;
198struct intel_community_context;
199
200/**
201 * struct intel_pinctrl_context - context to be saved during suspend-resume
202 * @pads: Opaque context per pad (driver dependent)
203 * @communities: Opaque context per community (driver dependent)
204 */
205struct intel_pinctrl_context {
206 struct intel_pad_context *pads;
207 struct intel_community_context *communities;
208};
209
210/**
211 * struct intel_pinctrl - Intel pinctrl private structure
212 * @dev: Pointer to the device structure
213 * @lock: Lock to serialize register access
214 * @pctldesc: Pin controller description
215 * @pctldev: Pointer to the pin controller device
216 * @chip: GPIO chip in this pin controller
217 * @irqchip: IRQ chip in this pin controller
218 * @soc: SoC/PCH specific pin configuration data
219 * @communities: All communities in this pin controller
220 * @ncommunities: Number of communities in this pin controller
221 * @context: Configuration saved over system sleep
222 * @irq: pinctrl/GPIO chip irq number
223 */
224struct intel_pinctrl {
225 struct device *dev;
226 raw_spinlock_t lock;
227 struct pinctrl_desc pctldesc;
228 struct pinctrl_dev *pctldev;
229 struct gpio_chip chip;
230 struct irq_chip irqchip;
231 const struct intel_pinctrl_soc_data *soc;
232 struct intel_community *communities;
233 size_t ncommunities;
234 struct intel_pinctrl_context context;
235 int irq;
236};
237
238int intel_pinctrl_probe_by_hid(struct platform_device *pdev);
239int intel_pinctrl_probe_by_uid(struct platform_device *pdev);
240
241#ifdef CONFIG_PM_SLEEP
242int intel_pinctrl_suspend_noirq(struct device *dev);
243int intel_pinctrl_resume_noirq(struct device *dev);
244#endif
245
246#define INTEL_PINCTRL_PM_OPS(_name) \
247const struct dev_pm_ops _name = { \
248 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(intel_pinctrl_suspend_noirq, \
249 intel_pinctrl_resume_noirq) \
250}
251
252#endif /* PINCTRL_INTEL_H */
1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Core pinctrl/GPIO driver for Intel GPIO controllers
4 *
5 * Copyright (C) 2015, Intel Corporation
6 * Authors: Mathias Nyman <mathias.nyman@linux.intel.com>
7 * Mika Westerberg <mika.westerberg@linux.intel.com>
8 */
9
10#ifndef PINCTRL_INTEL_H
11#define PINCTRL_INTEL_H
12
13#include <linux/array_size.h>
14#include <linux/bits.h>
15#include <linux/compiler_types.h>
16#include <linux/gpio/driver.h>
17#include <linux/irq.h>
18#include <linux/pm.h>
19#include <linux/pinctrl/pinctrl.h>
20#include <linux/spinlock_types.h>
21
22struct platform_device;
23struct device;
24
25/**
26 * struct intel_pingroup - Description about group of pins
27 * @grp: Generic data of the pin group (name and pins)
28 * @mode: Native mode in which the group is muxed out @pins. Used if @modes is %NULL.
29 * @modes: If not %NULL this will hold mode for each pin in @pins
30 */
31struct intel_pingroup {
32 struct pingroup grp;
33 unsigned short mode;
34 const unsigned int *modes;
35};
36
37/**
38 * struct intel_function - Description about a function
39 * @func: Generic data of the pin function (name and groups of pins)
40 */
41struct intel_function {
42 struct pinfunction func;
43};
44
45#define INTEL_PINCTRL_MAX_GPP_SIZE 32
46
47/**
48 * struct intel_padgroup - Hardware pad group information
49 * @reg_num: GPI_IS register number
50 * @base: Starting pin of this group
51 * @size: Size of this group (maximum is %INTEL_PINCTRL_MAX_GPP_SIZE).
52 * @gpio_base: Starting GPIO base of this group
53 * @padown_num: PAD_OWN register number (assigned by the core driver)
54 *
55 * If pad groups of a community are not the same size, use this structure
56 * to specify them.
57 */
58struct intel_padgroup {
59 unsigned int reg_num;
60 unsigned int base;
61 unsigned int size;
62 int gpio_base;
63 unsigned int padown_num;
64};
65
66/**
67 * enum - Special treatment for GPIO base in pad group
68 *
69 * @INTEL_GPIO_BASE_ZERO: force GPIO base to be 0
70 * @INTEL_GPIO_BASE_NOMAP: no GPIO mapping should be created
71 * @INTEL_GPIO_BASE_MATCH: matches with starting pin number
72 */
73enum {
74 INTEL_GPIO_BASE_ZERO = -2,
75 INTEL_GPIO_BASE_NOMAP = -1,
76 INTEL_GPIO_BASE_MATCH = 0,
77};
78
79/**
80 * struct intel_community - Intel pin community description
81 * @barno: MMIO BAR number where registers for this community reside
82 * @padown_offset: Register offset of PAD_OWN register from @regs. If %0
83 * then there is no support for owner.
84 * @padcfglock_offset: Register offset of PADCFGLOCK from @regs. If %0 then
85 * locking is not supported.
86 * @hostown_offset: Register offset of HOSTSW_OWN from @regs. If %0 then it
87 * is assumed that the host owns the pin (rather than
88 * ACPI).
89 * @is_offset: Register offset of GPI_IS from @regs.
90 * @ie_offset: Register offset of GPI_IE from @regs.
91 * @features: Additional features supported by the hardware
92 * @pin_base: Starting pin of pins in this community
93 * @npins: Number of pins in this community
94 * @gpp_size: Maximum number of pads in each group, such as PADCFGLOCK,
95 * HOSTSW_OWN, GPI_IS, GPI_IE. Used when @gpps is %NULL.
96 * @gpp_num_padown_regs: Number of pad registers each pad group consumes at
97 * minimum. Used when @gpps is %NULL.
98 * @gpps: Pad groups if the controller has variable size pad groups
99 * @ngpps: Number of pad groups in this community
100 * @pad_map: Optional non-linear mapping of the pads
101 * @nirqs: Optional total number of IRQs this community can generate
102 * @acpi_space_id: Optional address space ID for ACPI OpRegion handler
103 * @regs: Community specific common registers (reserved for core driver)
104 * @pad_regs: Community specific pad registers (reserved for core driver)
105 *
106 * In older Intel GPIO host controllers, this driver supports, each pad group
107 * is of equal size (except the last one). In that case the driver can just
108 * fill in @gpp_size and @gpp_num_padown_regs fields and let the core driver
109 * to handle the rest.
110 *
111 * In newer Intel GPIO host controllers each pad group is of variable size,
112 * so the client driver can pass custom @gpps and @ngpps instead.
113 */
114struct intel_community {
115 unsigned int barno;
116 unsigned int padown_offset;
117 unsigned int padcfglock_offset;
118 unsigned int hostown_offset;
119 unsigned int is_offset;
120 unsigned int ie_offset;
121 unsigned int features;
122 unsigned int pin_base;
123 size_t npins;
124 unsigned int gpp_size;
125 unsigned int gpp_num_padown_regs;
126 const struct intel_padgroup *gpps;
127 size_t ngpps;
128 const unsigned int *pad_map;
129 unsigned short nirqs;
130 unsigned short acpi_space_id;
131
132 /* Reserved for the core driver */
133 void __iomem *regs;
134 void __iomem *pad_regs;
135};
136
137/* Additional features supported by the hardware */
138#define PINCTRL_FEATURE_DEBOUNCE BIT(0)
139#define PINCTRL_FEATURE_1K_PD BIT(1)
140#define PINCTRL_FEATURE_GPIO_HW_INFO BIT(2)
141#define PINCTRL_FEATURE_PWM BIT(3)
142#define PINCTRL_FEATURE_BLINK BIT(4)
143#define PINCTRL_FEATURE_EXP BIT(5)
144
145#define __INTEL_COMMUNITY(b, s, e, g, n, gs, gn, soc) \
146 { \
147 .barno = (b), \
148 .padown_offset = soc ## _PAD_OWN, \
149 .padcfglock_offset = soc ## _PADCFGLOCK, \
150 .hostown_offset = soc ## _HOSTSW_OWN, \
151 .is_offset = soc ## _GPI_IS, \
152 .ie_offset = soc ## _GPI_IE, \
153 .gpp_size = (gs), \
154 .gpp_num_padown_regs = (gn), \
155 .pin_base = (s), \
156 .npins = ((e) - (s) + 1), \
157 .gpps = (g), \
158 .ngpps = (n), \
159 }
160
161#define INTEL_COMMUNITY_GPPS(b, s, e, g, soc) \
162 __INTEL_COMMUNITY(b, s, e, g, ARRAY_SIZE(g), 0, 0, soc)
163
164#define INTEL_COMMUNITY_SIZE(b, s, e, gs, gn, soc) \
165 __INTEL_COMMUNITY(b, s, e, NULL, 0, gs, gn, soc)
166
167/**
168 * PIN_GROUP - Declare a pin group
169 * @n: Name of the group
170 * @p: An array of pins this group consists
171 * @m: Mode which the pins are put when this group is active. Can be either
172 * a single integer or an array of integers in which case mode is per
173 * pin.
174 */
175#define PIN_GROUP(n, p, m) \
176 { \
177 .grp = PINCTRL_PINGROUP((n), (p), ARRAY_SIZE((p))), \
178 .mode = __builtin_choose_expr(__builtin_constant_p((m)), (m), 0), \
179 .modes = __builtin_choose_expr(__builtin_constant_p((m)), NULL, (m)), \
180 }
181
182#define PIN_GROUP_GPIO(n, p, m) \
183 PIN_GROUP(n, p, m), \
184 PIN_GROUP(n "_gpio", p, 0)
185
186#define FUNCTION(n, g) \
187 { \
188 .func = PINCTRL_PINFUNCTION((n), (g), ARRAY_SIZE(g)), \
189 }
190
191/**
192 * struct intel_pinctrl_soc_data - Intel pin controller per-SoC configuration
193 * @uid: ACPI _UID for the probe driver use if needed
194 * @pins: Array if pins this pinctrl controls
195 * @npins: Number of pins in the array
196 * @groups: Array of pin groups
197 * @ngroups: Number of groups in the array
198 * @functions: Array of functions
199 * @nfunctions: Number of functions in the array
200 * @communities: Array of communities this pinctrl handles
201 * @ncommunities: Number of communities in the array
202 *
203 * The @communities is used as a template by the core driver. It will make
204 * copy of all communities and fill in rest of the information.
205 */
206struct intel_pinctrl_soc_data {
207 const char *uid;
208 const struct pinctrl_pin_desc *pins;
209 size_t npins;
210 const struct intel_pingroup *groups;
211 size_t ngroups;
212 const struct intel_function *functions;
213 size_t nfunctions;
214 const struct intel_community *communities;
215 size_t ncommunities;
216};
217
218const struct intel_pinctrl_soc_data *intel_pinctrl_get_soc_data(struct platform_device *pdev);
219
220struct intel_pad_context;
221struct intel_community_context;
222
223/**
224 * struct intel_pinctrl_context - context to be saved during suspend-resume
225 * @pads: Opaque context per pad (driver dependent)
226 * @communities: Opaque context per community (driver dependent)
227 */
228struct intel_pinctrl_context {
229 struct intel_pad_context *pads;
230 struct intel_community_context *communities;
231};
232
233/**
234 * struct intel_pinctrl - Intel pinctrl private structure
235 * @dev: Pointer to the device structure
236 * @lock: Lock to serialize register access
237 * @pctldesc: Pin controller description
238 * @pctldev: Pointer to the pin controller device
239 * @chip: GPIO chip in this pin controller
240 * @soc: SoC/PCH specific pin configuration data
241 * @communities: All communities in this pin controller
242 * @ncommunities: Number of communities in this pin controller
243 * @context: Configuration saved over system sleep
244 * @irq: pinctrl/GPIO chip irq number
245 */
246struct intel_pinctrl {
247 struct device *dev;
248 raw_spinlock_t lock;
249 struct pinctrl_desc pctldesc;
250 struct pinctrl_dev *pctldev;
251 struct gpio_chip chip;
252 const struct intel_pinctrl_soc_data *soc;
253 struct intel_community *communities;
254 size_t ncommunities;
255 struct intel_pinctrl_context context;
256 int irq;
257};
258
259int intel_pinctrl_probe(struct platform_device *pdev,
260 const struct intel_pinctrl_soc_data *soc_data);
261
262int intel_pinctrl_probe_by_hid(struct platform_device *pdev);
263int intel_pinctrl_probe_by_uid(struct platform_device *pdev);
264
265extern const struct dev_pm_ops intel_pinctrl_pm_ops;
266
267const struct intel_community *intel_get_community(const struct intel_pinctrl *pctrl,
268 unsigned int pin);
269
270int intel_get_groups_count(struct pinctrl_dev *pctldev);
271const char *intel_get_group_name(struct pinctrl_dev *pctldev, unsigned int group);
272int intel_get_group_pins(struct pinctrl_dev *pctldev, unsigned int group,
273 const unsigned int **pins, unsigned int *npins);
274
275int intel_get_functions_count(struct pinctrl_dev *pctldev);
276const char *intel_get_function_name(struct pinctrl_dev *pctldev, unsigned int function);
277int intel_get_function_groups(struct pinctrl_dev *pctldev, unsigned int function,
278 const char * const **groups, unsigned int * const ngroups);
279
280#endif /* PINCTRL_INTEL_H */