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1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Core pinctrl/GPIO driver for Intel GPIO controllers
4 *
5 * Copyright (C) 2015, Intel Corporation
6 * Authors: Mathias Nyman <mathias.nyman@linux.intel.com>
7 * Mika Westerberg <mika.westerberg@linux.intel.com>
8 */
9
10#ifndef PINCTRL_INTEL_H
11#define PINCTRL_INTEL_H
12
13#include <linux/gpio/driver.h>
14#include <linux/irq.h>
15#include <linux/pm.h>
16#include <linux/spinlock_types.h>
17
18struct pinctrl_pin_desc;
19struct platform_device;
20struct device;
21
22/**
23 * struct intel_pingroup - Description about group of pins
24 * @name: Name of the groups
25 * @pins: All pins in this group
26 * @npins: Number of pins in this groups
27 * @mode: Native mode in which the group is muxed out @pins. Used if @modes
28 * is %NULL.
29 * @modes: If not %NULL this will hold mode for each pin in @pins
30 */
31struct intel_pingroup {
32 const char *name;
33 const unsigned int *pins;
34 size_t npins;
35 unsigned short mode;
36 const unsigned int *modes;
37};
38
39/**
40 * struct intel_function - Description about a function
41 * @name: Name of the function
42 * @groups: An array of groups for this function
43 * @ngroups: Number of groups in @groups
44 */
45struct intel_function {
46 const char *name;
47 const char * const *groups;
48 size_t ngroups;
49};
50
51/**
52 * struct intel_padgroup - Hardware pad group information
53 * @reg_num: GPI_IS register number
54 * @base: Starting pin of this group
55 * @size: Size of this group (maximum is 32).
56 * @gpio_base: Starting GPIO base of this group
57 * @padown_num: PAD_OWN register number (assigned by the core driver)
58 *
59 * If pad groups of a community are not the same size, use this structure
60 * to specify them.
61 */
62struct intel_padgroup {
63 unsigned int reg_num;
64 unsigned int base;
65 unsigned int size;
66 int gpio_base;
67 unsigned int padown_num;
68};
69
70/**
71 * enum - Special treatment for GPIO base in pad group
72 *
73 * @INTEL_GPIO_BASE_ZERO: force GPIO base to be 0
74 * @INTEL_GPIO_BASE_NOMAP: no GPIO mapping should be created
75 * @INTEL_GPIO_BASE_MATCH: matches with starting pin number
76 */
77enum {
78 INTEL_GPIO_BASE_ZERO = -2,
79 INTEL_GPIO_BASE_NOMAP = -1,
80 INTEL_GPIO_BASE_MATCH = 0,
81};
82
83/**
84 * struct intel_community - Intel pin community description
85 * @barno: MMIO BAR number where registers for this community reside
86 * @padown_offset: Register offset of PAD_OWN register from @regs. If %0
87 * then there is no support for owner.
88 * @padcfglock_offset: Register offset of PADCFGLOCK from @regs. If %0 then
89 * locking is not supported.
90 * @hostown_offset: Register offset of HOSTSW_OWN from @regs. If %0 then it
91 * is assumed that the host owns the pin (rather than
92 * ACPI).
93 * @is_offset: Register offset of GPI_IS from @regs.
94 * @ie_offset: Register offset of GPI_IE from @regs.
95 * @features: Additional features supported by the hardware
96 * @pin_base: Starting pin of pins in this community
97 * @npins: Number of pins in this community
98 * @gpp_size: Maximum number of pads in each group, such as PADCFGLOCK,
99 * HOSTSW_OWN, GPI_IS, GPI_IE. Used when @gpps is %NULL.
100 * @gpp_num_padown_regs: Number of pad registers each pad group consumes at
101 * minimum. Use %0 if the number of registers can be
102 * determined by the size of the group.
103 * @gpps: Pad groups if the controller has variable size pad groups
104 * @ngpps: Number of pad groups in this community
105 * @pad_map: Optional non-linear mapping of the pads
106 * @nirqs: Optional total number of IRQs this community can generate
107 * @acpi_space_id: Optional address space ID for ACPI OpRegion handler
108 * @regs: Community specific common registers (reserved for core driver)
109 * @pad_regs: Community specific pad registers (reserved for core driver)
110 *
111 * In some of Intel GPIO host controllers this driver supports each pad group
112 * is of equal size (except the last one). In that case the driver can just
113 * fill in @gpp_size field and let the core driver to handle the rest. If
114 * the controller has pad groups of variable size the client driver can
115 * pass custom @gpps and @ngpps instead.
116 */
117struct intel_community {
118 unsigned int barno;
119 unsigned int padown_offset;
120 unsigned int padcfglock_offset;
121 unsigned int hostown_offset;
122 unsigned int is_offset;
123 unsigned int ie_offset;
124 unsigned int features;
125 unsigned int pin_base;
126 size_t npins;
127 unsigned int gpp_size;
128 unsigned int gpp_num_padown_regs;
129 const struct intel_padgroup *gpps;
130 size_t ngpps;
131 const unsigned int *pad_map;
132 unsigned short nirqs;
133 unsigned short acpi_space_id;
134
135 /* Reserved for the core driver */
136 void __iomem *regs;
137 void __iomem *pad_regs;
138};
139
140/* Additional features supported by the hardware */
141#define PINCTRL_FEATURE_DEBOUNCE BIT(0)
142#define PINCTRL_FEATURE_1K_PD BIT(1)
143
144/**
145 * PIN_GROUP - Declare a pin group
146 * @n: Name of the group
147 * @p: An array of pins this group consists
148 * @m: Mode which the pins are put when this group is active. Can be either
149 * a single integer or an array of integers in which case mode is per
150 * pin.
151 */
152#define PIN_GROUP(n, p, m) \
153 { \
154 .name = (n), \
155 .pins = (p), \
156 .npins = ARRAY_SIZE((p)), \
157 .mode = __builtin_choose_expr( \
158 __builtin_constant_p((m)), (m), 0), \
159 .modes = __builtin_choose_expr( \
160 __builtin_constant_p((m)), NULL, (m)), \
161 }
162
163#define FUNCTION(n, g) \
164 { \
165 .name = (n), \
166 .groups = (g), \
167 .ngroups = ARRAY_SIZE((g)), \
168 }
169
170/**
171 * struct intel_pinctrl_soc_data - Intel pin controller per-SoC configuration
172 * @uid: ACPI _UID for the probe driver use if needed
173 * @pins: Array if pins this pinctrl controls
174 * @npins: Number of pins in the array
175 * @groups: Array of pin groups
176 * @ngroups: Number of groups in the array
177 * @functions: Array of functions
178 * @nfunctions: Number of functions in the array
179 * @communities: Array of communities this pinctrl handles
180 * @ncommunities: Number of communities in the array
181 *
182 * The @communities is used as a template by the core driver. It will make
183 * copy of all communities and fill in rest of the information.
184 */
185struct intel_pinctrl_soc_data {
186 const char *uid;
187 const struct pinctrl_pin_desc *pins;
188 size_t npins;
189 const struct intel_pingroup *groups;
190 size_t ngroups;
191 const struct intel_function *functions;
192 size_t nfunctions;
193 const struct intel_community *communities;
194 size_t ncommunities;
195};
196
197struct intel_pad_context;
198struct intel_community_context;
199
200/**
201 * struct intel_pinctrl_context - context to be saved during suspend-resume
202 * @pads: Opaque context per pad (driver dependent)
203 * @communities: Opaque context per community (driver dependent)
204 */
205struct intel_pinctrl_context {
206 struct intel_pad_context *pads;
207 struct intel_community_context *communities;
208};
209
210/**
211 * struct intel_pinctrl - Intel pinctrl private structure
212 * @dev: Pointer to the device structure
213 * @lock: Lock to serialize register access
214 * @pctldesc: Pin controller description
215 * @pctldev: Pointer to the pin controller device
216 * @chip: GPIO chip in this pin controller
217 * @irqchip: IRQ chip in this pin controller
218 * @soc: SoC/PCH specific pin configuration data
219 * @communities: All communities in this pin controller
220 * @ncommunities: Number of communities in this pin controller
221 * @context: Configuration saved over system sleep
222 * @irq: pinctrl/GPIO chip irq number
223 */
224struct intel_pinctrl {
225 struct device *dev;
226 raw_spinlock_t lock;
227 struct pinctrl_desc pctldesc;
228 struct pinctrl_dev *pctldev;
229 struct gpio_chip chip;
230 struct irq_chip irqchip;
231 const struct intel_pinctrl_soc_data *soc;
232 struct intel_community *communities;
233 size_t ncommunities;
234 struct intel_pinctrl_context context;
235 int irq;
236};
237
238int intel_pinctrl_probe_by_hid(struct platform_device *pdev);
239int intel_pinctrl_probe_by_uid(struct platform_device *pdev);
240
241#ifdef CONFIG_PM_SLEEP
242int intel_pinctrl_suspend_noirq(struct device *dev);
243int intel_pinctrl_resume_noirq(struct device *dev);
244#endif
245
246#define INTEL_PINCTRL_PM_OPS(_name) \
247const struct dev_pm_ops _name = { \
248 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(intel_pinctrl_suspend_noirq, \
249 intel_pinctrl_resume_noirq) \
250}
251
252#endif /* PINCTRL_INTEL_H */
1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Core pinctrl/GPIO driver for Intel GPIO controllers
4 *
5 * Copyright (C) 2015, Intel Corporation
6 * Authors: Mathias Nyman <mathias.nyman@linux.intel.com>
7 * Mika Westerberg <mika.westerberg@linux.intel.com>
8 */
9
10#ifndef PINCTRL_INTEL_H
11#define PINCTRL_INTEL_H
12
13#include <linux/pm.h>
14
15struct pinctrl_pin_desc;
16struct platform_device;
17struct device;
18
19/**
20 * struct intel_pingroup - Description about group of pins
21 * @name: Name of the groups
22 * @pins: All pins in this group
23 * @npins: Number of pins in this groups
24 * @mode: Native mode in which the group is muxed out @pins. Used if @modes
25 * is %NULL.
26 * @modes: If not %NULL this will hold mode for each pin in @pins
27 */
28struct intel_pingroup {
29 const char *name;
30 const unsigned int *pins;
31 size_t npins;
32 unsigned short mode;
33 const unsigned int *modes;
34};
35
36/**
37 * struct intel_function - Description about a function
38 * @name: Name of the function
39 * @groups: An array of groups for this function
40 * @ngroups: Number of groups in @groups
41 */
42struct intel_function {
43 const char *name;
44 const char * const *groups;
45 size_t ngroups;
46};
47
48/**
49 * struct intel_padgroup - Hardware pad group information
50 * @reg_num: GPI_IS register number
51 * @base: Starting pin of this group
52 * @size: Size of this group (maximum is 32).
53 * @gpio_base: Starting GPIO base of this group (%0 if matches with @base,
54 * and %-1 if no GPIO mapping should be created)
55 * @padown_num: PAD_OWN register number (assigned by the core driver)
56 *
57 * If pad groups of a community are not the same size, use this structure
58 * to specify them.
59 */
60struct intel_padgroup {
61 unsigned int reg_num;
62 unsigned int base;
63 unsigned int size;
64 int gpio_base;
65 unsigned int padown_num;
66};
67
68/**
69 * struct intel_community - Intel pin community description
70 * @barno: MMIO BAR number where registers for this community reside
71 * @padown_offset: Register offset of PAD_OWN register from @regs. If %0
72 * then there is no support for owner.
73 * @padcfglock_offset: Register offset of PADCFGLOCK from @regs. If %0 then
74 * locking is not supported.
75 * @hostown_offset: Register offset of HOSTSW_OWN from @regs. If %0 then it
76 * is assumed that the host owns the pin (rather than
77 * ACPI).
78 * @is_offset: Register offset of GPI_IS from @regs.
79 * @ie_offset: Register offset of GPI_IE from @regs.
80 * @features: Additional features supported by the hardware
81 * @pin_base: Starting pin of pins in this community
82 * @gpp_size: Maximum number of pads in each group, such as PADCFGLOCK,
83 * HOSTSW_OWN, GPI_IS, GPI_IE, etc. Used when @gpps is %NULL.
84 * @gpp_num_padown_regs: Number of pad registers each pad group consumes at
85 * minimum. Use %0 if the number of registers can be
86 * determined by the size of the group.
87 * @npins: Number of pins in this community
88 * @gpps: Pad groups if the controller has variable size pad groups
89 * @ngpps: Number of pad groups in this community
90 * @pad_map: Optional non-linear mapping of the pads
91 * @regs: Community specific common registers (reserved for core driver)
92 * @pad_regs: Community specific pad registers (reserved for core driver)
93 *
94 * Most Intel GPIO host controllers this driver supports each pad group is
95 * of equal size (except the last one). In that case the driver can just
96 * fill in @gpp_size field and let the core driver to handle the rest. If
97 * the controller has pad groups of variable size the client driver can
98 * pass custom @gpps and @ngpps instead.
99 */
100struct intel_community {
101 unsigned int barno;
102 unsigned int padown_offset;
103 unsigned int padcfglock_offset;
104 unsigned int hostown_offset;
105 unsigned int is_offset;
106 unsigned int ie_offset;
107 unsigned int features;
108 unsigned int pin_base;
109 unsigned int gpp_size;
110 unsigned int gpp_num_padown_regs;
111 size_t npins;
112 const struct intel_padgroup *gpps;
113 size_t ngpps;
114 const unsigned int *pad_map;
115 /* Reserved for the core driver */
116 void __iomem *regs;
117 void __iomem *pad_regs;
118};
119
120/* Additional features supported by the hardware */
121#define PINCTRL_FEATURE_DEBOUNCE BIT(0)
122#define PINCTRL_FEATURE_1K_PD BIT(1)
123
124/**
125 * PIN_GROUP - Declare a pin group
126 * @n: Name of the group
127 * @p: An array of pins this group consists
128 * @m: Mode which the pins are put when this group is active. Can be either
129 * a single integer or an array of integers in which case mode is per
130 * pin.
131 */
132#define PIN_GROUP(n, p, m) \
133 { \
134 .name = (n), \
135 .pins = (p), \
136 .npins = ARRAY_SIZE((p)), \
137 .mode = __builtin_choose_expr( \
138 __builtin_constant_p((m)), (m), 0), \
139 .modes = __builtin_choose_expr( \
140 __builtin_constant_p((m)), NULL, (m)), \
141 }
142
143#define FUNCTION(n, g) \
144 { \
145 .name = (n), \
146 .groups = (g), \
147 .ngroups = ARRAY_SIZE((g)), \
148 }
149
150/**
151 * struct intel_pinctrl_soc_data - Intel pin controller per-SoC configuration
152 * @uid: ACPI _UID for the probe driver use if needed
153 * @pins: Array if pins this pinctrl controls
154 * @npins: Number of pins in the array
155 * @groups: Array of pin groups
156 * @ngroups: Number of groups in the array
157 * @functions: Array of functions
158 * @nfunctions: Number of functions in the array
159 * @communities: Array of communities this pinctrl handles
160 * @ncommunities: Number of communities in the array
161 *
162 * The @communities is used as a template by the core driver. It will make
163 * copy of all communities and fill in rest of the information.
164 */
165struct intel_pinctrl_soc_data {
166 const char *uid;
167 const struct pinctrl_pin_desc *pins;
168 size_t npins;
169 const struct intel_pingroup *groups;
170 size_t ngroups;
171 const struct intel_function *functions;
172 size_t nfunctions;
173 const struct intel_community *communities;
174 size_t ncommunities;
175};
176
177int intel_pinctrl_probe_by_hid(struct platform_device *pdev);
178int intel_pinctrl_probe_by_uid(struct platform_device *pdev);
179
180#ifdef CONFIG_PM_SLEEP
181int intel_pinctrl_suspend_noirq(struct device *dev);
182int intel_pinctrl_resume_noirq(struct device *dev);
183#endif
184
185#define INTEL_PINCTRL_PM_OPS(_name) \
186const struct dev_pm_ops _name = { \
187 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(intel_pinctrl_suspend_noirq, \
188 intel_pinctrl_resume_noirq) \
189}
190
191#endif /* PINCTRL_INTEL_H */