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1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28#include <linux/dma-fence-array.h>
29#include <linux/interval_tree_generic.h>
30#include <linux/idr.h>
31
32#include <drm/amdgpu_drm.h>
33#include "amdgpu.h"
34#include "amdgpu_trace.h"
35#include "amdgpu_amdkfd.h"
36#include "amdgpu_gmc.h"
37#include "amdgpu_xgmi.h"
38
39/**
40 * DOC: GPUVM
41 *
42 * GPUVM is similar to the legacy gart on older asics, however
43 * rather than there being a single global gart table
44 * for the entire GPU, there are multiple VM page tables active
45 * at any given time. The VM page tables can contain a mix
46 * vram pages and system memory pages and system memory pages
47 * can be mapped as snooped (cached system pages) or unsnooped
48 * (uncached system pages).
49 * Each VM has an ID associated with it and there is a page table
50 * associated with each VMID. When execting a command buffer,
51 * the kernel tells the the ring what VMID to use for that command
52 * buffer. VMIDs are allocated dynamically as commands are submitted.
53 * The userspace drivers maintain their own address space and the kernel
54 * sets up their pages tables accordingly when they submit their
55 * command buffers and a VMID is assigned.
56 * Cayman/Trinity support up to 8 active VMs at any given time;
57 * SI supports 16.
58 */
59
60#define START(node) ((node)->start)
61#define LAST(node) ((node)->last)
62
63INTERVAL_TREE_DEFINE(struct amdgpu_bo_va_mapping, rb, uint64_t, __subtree_last,
64 START, LAST, static, amdgpu_vm_it)
65
66#undef START
67#undef LAST
68
69/**
70 * struct amdgpu_prt_cb - Helper to disable partial resident texture feature from a fence callback
71 */
72struct amdgpu_prt_cb {
73
74 /**
75 * @adev: amdgpu device
76 */
77 struct amdgpu_device *adev;
78
79 /**
80 * @cb: callback
81 */
82 struct dma_fence_cb cb;
83};
84
85/*
86 * vm eviction_lock can be taken in MMU notifiers. Make sure no reclaim-FS
87 * happens while holding this lock anywhere to prevent deadlocks when
88 * an MMU notifier runs in reclaim-FS context.
89 */
90static inline void amdgpu_vm_eviction_lock(struct amdgpu_vm *vm)
91{
92 mutex_lock(&vm->eviction_lock);
93 vm->saved_flags = memalloc_nofs_save();
94}
95
96static inline int amdgpu_vm_eviction_trylock(struct amdgpu_vm *vm)
97{
98 if (mutex_trylock(&vm->eviction_lock)) {
99 vm->saved_flags = memalloc_nofs_save();
100 return 1;
101 }
102 return 0;
103}
104
105static inline void amdgpu_vm_eviction_unlock(struct amdgpu_vm *vm)
106{
107 memalloc_nofs_restore(vm->saved_flags);
108 mutex_unlock(&vm->eviction_lock);
109}
110
111/**
112 * amdgpu_vm_level_shift - return the addr shift for each level
113 *
114 * @adev: amdgpu_device pointer
115 * @level: VMPT level
116 *
117 * Returns:
118 * The number of bits the pfn needs to be right shifted for a level.
119 */
120static unsigned amdgpu_vm_level_shift(struct amdgpu_device *adev,
121 unsigned level)
122{
123 switch (level) {
124 case AMDGPU_VM_PDB2:
125 case AMDGPU_VM_PDB1:
126 case AMDGPU_VM_PDB0:
127 return 9 * (AMDGPU_VM_PDB0 - level) +
128 adev->vm_manager.block_size;
129 case AMDGPU_VM_PTB:
130 return 0;
131 default:
132 return ~0;
133 }
134}
135
136/**
137 * amdgpu_vm_num_entries - return the number of entries in a PD/PT
138 *
139 * @adev: amdgpu_device pointer
140 * @level: VMPT level
141 *
142 * Returns:
143 * The number of entries in a page directory or page table.
144 */
145static unsigned amdgpu_vm_num_entries(struct amdgpu_device *adev,
146 unsigned level)
147{
148 unsigned shift = amdgpu_vm_level_shift(adev,
149 adev->vm_manager.root_level);
150
151 if (level == adev->vm_manager.root_level)
152 /* For the root directory */
153 return round_up(adev->vm_manager.max_pfn, 1ULL << shift)
154 >> shift;
155 else if (level != AMDGPU_VM_PTB)
156 /* Everything in between */
157 return 512;
158 else
159 /* For the page tables on the leaves */
160 return AMDGPU_VM_PTE_COUNT(adev);
161}
162
163/**
164 * amdgpu_vm_num_ats_entries - return the number of ATS entries in the root PD
165 *
166 * @adev: amdgpu_device pointer
167 *
168 * Returns:
169 * The number of entries in the root page directory which needs the ATS setting.
170 */
171static unsigned amdgpu_vm_num_ats_entries(struct amdgpu_device *adev)
172{
173 unsigned shift;
174
175 shift = amdgpu_vm_level_shift(adev, adev->vm_manager.root_level);
176 return AMDGPU_GMC_HOLE_START >> (shift + AMDGPU_GPU_PAGE_SHIFT);
177}
178
179/**
180 * amdgpu_vm_entries_mask - the mask to get the entry number of a PD/PT
181 *
182 * @adev: amdgpu_device pointer
183 * @level: VMPT level
184 *
185 * Returns:
186 * The mask to extract the entry number of a PD/PT from an address.
187 */
188static uint32_t amdgpu_vm_entries_mask(struct amdgpu_device *adev,
189 unsigned int level)
190{
191 if (level <= adev->vm_manager.root_level)
192 return 0xffffffff;
193 else if (level != AMDGPU_VM_PTB)
194 return 0x1ff;
195 else
196 return AMDGPU_VM_PTE_COUNT(adev) - 1;
197}
198
199/**
200 * amdgpu_vm_bo_size - returns the size of the BOs in bytes
201 *
202 * @adev: amdgpu_device pointer
203 * @level: VMPT level
204 *
205 * Returns:
206 * The size of the BO for a page directory or page table in bytes.
207 */
208static unsigned amdgpu_vm_bo_size(struct amdgpu_device *adev, unsigned level)
209{
210 return AMDGPU_GPU_PAGE_ALIGN(amdgpu_vm_num_entries(adev, level) * 8);
211}
212
213/**
214 * amdgpu_vm_bo_evicted - vm_bo is evicted
215 *
216 * @vm_bo: vm_bo which is evicted
217 *
218 * State for PDs/PTs and per VM BOs which are not at the location they should
219 * be.
220 */
221static void amdgpu_vm_bo_evicted(struct amdgpu_vm_bo_base *vm_bo)
222{
223 struct amdgpu_vm *vm = vm_bo->vm;
224 struct amdgpu_bo *bo = vm_bo->bo;
225
226 vm_bo->moved = true;
227 if (bo->tbo.type == ttm_bo_type_kernel)
228 list_move(&vm_bo->vm_status, &vm->evicted);
229 else
230 list_move_tail(&vm_bo->vm_status, &vm->evicted);
231}
232/**
233 * amdgpu_vm_bo_moved - vm_bo is moved
234 *
235 * @vm_bo: vm_bo which is moved
236 *
237 * State for per VM BOs which are moved, but that change is not yet reflected
238 * in the page tables.
239 */
240static void amdgpu_vm_bo_moved(struct amdgpu_vm_bo_base *vm_bo)
241{
242 list_move(&vm_bo->vm_status, &vm_bo->vm->moved);
243}
244
245/**
246 * amdgpu_vm_bo_idle - vm_bo is idle
247 *
248 * @vm_bo: vm_bo which is now idle
249 *
250 * State for PDs/PTs and per VM BOs which have gone through the state machine
251 * and are now idle.
252 */
253static void amdgpu_vm_bo_idle(struct amdgpu_vm_bo_base *vm_bo)
254{
255 list_move(&vm_bo->vm_status, &vm_bo->vm->idle);
256 vm_bo->moved = false;
257}
258
259/**
260 * amdgpu_vm_bo_invalidated - vm_bo is invalidated
261 *
262 * @vm_bo: vm_bo which is now invalidated
263 *
264 * State for normal BOs which are invalidated and that change not yet reflected
265 * in the PTs.
266 */
267static void amdgpu_vm_bo_invalidated(struct amdgpu_vm_bo_base *vm_bo)
268{
269 spin_lock(&vm_bo->vm->invalidated_lock);
270 list_move(&vm_bo->vm_status, &vm_bo->vm->invalidated);
271 spin_unlock(&vm_bo->vm->invalidated_lock);
272}
273
274/**
275 * amdgpu_vm_bo_relocated - vm_bo is reloacted
276 *
277 * @vm_bo: vm_bo which is relocated
278 *
279 * State for PDs/PTs which needs to update their parent PD.
280 * For the root PD, just move to idle state.
281 */
282static void amdgpu_vm_bo_relocated(struct amdgpu_vm_bo_base *vm_bo)
283{
284 if (vm_bo->bo->parent)
285 list_move(&vm_bo->vm_status, &vm_bo->vm->relocated);
286 else
287 amdgpu_vm_bo_idle(vm_bo);
288}
289
290/**
291 * amdgpu_vm_bo_done - vm_bo is done
292 *
293 * @vm_bo: vm_bo which is now done
294 *
295 * State for normal BOs which are invalidated and that change has been updated
296 * in the PTs.
297 */
298static void amdgpu_vm_bo_done(struct amdgpu_vm_bo_base *vm_bo)
299{
300 spin_lock(&vm_bo->vm->invalidated_lock);
301 list_del_init(&vm_bo->vm_status);
302 spin_unlock(&vm_bo->vm->invalidated_lock);
303}
304
305/**
306 * amdgpu_vm_bo_base_init - Adds bo to the list of bos associated with the vm
307 *
308 * @base: base structure for tracking BO usage in a VM
309 * @vm: vm to which bo is to be added
310 * @bo: amdgpu buffer object
311 *
312 * Initialize a bo_va_base structure and add it to the appropriate lists
313 *
314 */
315static void amdgpu_vm_bo_base_init(struct amdgpu_vm_bo_base *base,
316 struct amdgpu_vm *vm,
317 struct amdgpu_bo *bo)
318{
319 base->vm = vm;
320 base->bo = bo;
321 base->next = NULL;
322 INIT_LIST_HEAD(&base->vm_status);
323
324 if (!bo)
325 return;
326 base->next = bo->vm_bo;
327 bo->vm_bo = base;
328
329 if (bo->tbo.base.resv != vm->root.base.bo->tbo.base.resv)
330 return;
331
332 vm->bulk_moveable = false;
333 if (bo->tbo.type == ttm_bo_type_kernel && bo->parent)
334 amdgpu_vm_bo_relocated(base);
335 else
336 amdgpu_vm_bo_idle(base);
337
338 if (bo->preferred_domains &
339 amdgpu_mem_type_to_domain(bo->tbo.mem.mem_type))
340 return;
341
342 /*
343 * we checked all the prerequisites, but it looks like this per vm bo
344 * is currently evicted. add the bo to the evicted list to make sure it
345 * is validated on next vm use to avoid fault.
346 * */
347 amdgpu_vm_bo_evicted(base);
348}
349
350/**
351 * amdgpu_vm_pt_parent - get the parent page directory
352 *
353 * @pt: child page table
354 *
355 * Helper to get the parent entry for the child page table. NULL if we are at
356 * the root page directory.
357 */
358static struct amdgpu_vm_pt *amdgpu_vm_pt_parent(struct amdgpu_vm_pt *pt)
359{
360 struct amdgpu_bo *parent = pt->base.bo->parent;
361
362 if (!parent)
363 return NULL;
364
365 return container_of(parent->vm_bo, struct amdgpu_vm_pt, base);
366}
367
368/*
369 * amdgpu_vm_pt_cursor - state for for_each_amdgpu_vm_pt
370 */
371struct amdgpu_vm_pt_cursor {
372 uint64_t pfn;
373 struct amdgpu_vm_pt *parent;
374 struct amdgpu_vm_pt *entry;
375 unsigned level;
376};
377
378/**
379 * amdgpu_vm_pt_start - start PD/PT walk
380 *
381 * @adev: amdgpu_device pointer
382 * @vm: amdgpu_vm structure
383 * @start: start address of the walk
384 * @cursor: state to initialize
385 *
386 * Initialize a amdgpu_vm_pt_cursor to start a walk.
387 */
388static void amdgpu_vm_pt_start(struct amdgpu_device *adev,
389 struct amdgpu_vm *vm, uint64_t start,
390 struct amdgpu_vm_pt_cursor *cursor)
391{
392 cursor->pfn = start;
393 cursor->parent = NULL;
394 cursor->entry = &vm->root;
395 cursor->level = adev->vm_manager.root_level;
396}
397
398/**
399 * amdgpu_vm_pt_descendant - go to child node
400 *
401 * @adev: amdgpu_device pointer
402 * @cursor: current state
403 *
404 * Walk to the child node of the current node.
405 * Returns:
406 * True if the walk was possible, false otherwise.
407 */
408static bool amdgpu_vm_pt_descendant(struct amdgpu_device *adev,
409 struct amdgpu_vm_pt_cursor *cursor)
410{
411 unsigned mask, shift, idx;
412
413 if (!cursor->entry->entries)
414 return false;
415
416 BUG_ON(!cursor->entry->base.bo);
417 mask = amdgpu_vm_entries_mask(adev, cursor->level);
418 shift = amdgpu_vm_level_shift(adev, cursor->level);
419
420 ++cursor->level;
421 idx = (cursor->pfn >> shift) & mask;
422 cursor->parent = cursor->entry;
423 cursor->entry = &cursor->entry->entries[idx];
424 return true;
425}
426
427/**
428 * amdgpu_vm_pt_sibling - go to sibling node
429 *
430 * @adev: amdgpu_device pointer
431 * @cursor: current state
432 *
433 * Walk to the sibling node of the current node.
434 * Returns:
435 * True if the walk was possible, false otherwise.
436 */
437static bool amdgpu_vm_pt_sibling(struct amdgpu_device *adev,
438 struct amdgpu_vm_pt_cursor *cursor)
439{
440 unsigned shift, num_entries;
441
442 /* Root doesn't have a sibling */
443 if (!cursor->parent)
444 return false;
445
446 /* Go to our parents and see if we got a sibling */
447 shift = amdgpu_vm_level_shift(adev, cursor->level - 1);
448 num_entries = amdgpu_vm_num_entries(adev, cursor->level - 1);
449
450 if (cursor->entry == &cursor->parent->entries[num_entries - 1])
451 return false;
452
453 cursor->pfn += 1ULL << shift;
454 cursor->pfn &= ~((1ULL << shift) - 1);
455 ++cursor->entry;
456 return true;
457}
458
459/**
460 * amdgpu_vm_pt_ancestor - go to parent node
461 *
462 * @cursor: current state
463 *
464 * Walk to the parent node of the current node.
465 * Returns:
466 * True if the walk was possible, false otherwise.
467 */
468static bool amdgpu_vm_pt_ancestor(struct amdgpu_vm_pt_cursor *cursor)
469{
470 if (!cursor->parent)
471 return false;
472
473 --cursor->level;
474 cursor->entry = cursor->parent;
475 cursor->parent = amdgpu_vm_pt_parent(cursor->parent);
476 return true;
477}
478
479/**
480 * amdgpu_vm_pt_next - get next PD/PT in hieratchy
481 *
482 * @adev: amdgpu_device pointer
483 * @cursor: current state
484 *
485 * Walk the PD/PT tree to the next node.
486 */
487static void amdgpu_vm_pt_next(struct amdgpu_device *adev,
488 struct amdgpu_vm_pt_cursor *cursor)
489{
490 /* First try a newborn child */
491 if (amdgpu_vm_pt_descendant(adev, cursor))
492 return;
493
494 /* If that didn't worked try to find a sibling */
495 while (!amdgpu_vm_pt_sibling(adev, cursor)) {
496 /* No sibling, go to our parents and grandparents */
497 if (!amdgpu_vm_pt_ancestor(cursor)) {
498 cursor->pfn = ~0ll;
499 return;
500 }
501 }
502}
503
504/**
505 * amdgpu_vm_pt_first_dfs - start a deep first search
506 *
507 * @adev: amdgpu_device structure
508 * @vm: amdgpu_vm structure
509 * @start: optional cursor to start with
510 * @cursor: state to initialize
511 *
512 * Starts a deep first traversal of the PD/PT tree.
513 */
514static void amdgpu_vm_pt_first_dfs(struct amdgpu_device *adev,
515 struct amdgpu_vm *vm,
516 struct amdgpu_vm_pt_cursor *start,
517 struct amdgpu_vm_pt_cursor *cursor)
518{
519 if (start)
520 *cursor = *start;
521 else
522 amdgpu_vm_pt_start(adev, vm, 0, cursor);
523 while (amdgpu_vm_pt_descendant(adev, cursor));
524}
525
526/**
527 * amdgpu_vm_pt_continue_dfs - check if the deep first search should continue
528 *
529 * @start: starting point for the search
530 * @entry: current entry
531 *
532 * Returns:
533 * True when the search should continue, false otherwise.
534 */
535static bool amdgpu_vm_pt_continue_dfs(struct amdgpu_vm_pt_cursor *start,
536 struct amdgpu_vm_pt *entry)
537{
538 return entry && (!start || entry != start->entry);
539}
540
541/**
542 * amdgpu_vm_pt_next_dfs - get the next node for a deep first search
543 *
544 * @adev: amdgpu_device structure
545 * @cursor: current state
546 *
547 * Move the cursor to the next node in a deep first search.
548 */
549static void amdgpu_vm_pt_next_dfs(struct amdgpu_device *adev,
550 struct amdgpu_vm_pt_cursor *cursor)
551{
552 if (!cursor->entry)
553 return;
554
555 if (!cursor->parent)
556 cursor->entry = NULL;
557 else if (amdgpu_vm_pt_sibling(adev, cursor))
558 while (amdgpu_vm_pt_descendant(adev, cursor));
559 else
560 amdgpu_vm_pt_ancestor(cursor);
561}
562
563/*
564 * for_each_amdgpu_vm_pt_dfs_safe - safe deep first search of all PDs/PTs
565 */
566#define for_each_amdgpu_vm_pt_dfs_safe(adev, vm, start, cursor, entry) \
567 for (amdgpu_vm_pt_first_dfs((adev), (vm), (start), &(cursor)), \
568 (entry) = (cursor).entry, amdgpu_vm_pt_next_dfs((adev), &(cursor));\
569 amdgpu_vm_pt_continue_dfs((start), (entry)); \
570 (entry) = (cursor).entry, amdgpu_vm_pt_next_dfs((adev), &(cursor)))
571
572/**
573 * amdgpu_vm_get_pd_bo - add the VM PD to a validation list
574 *
575 * @vm: vm providing the BOs
576 * @validated: head of validation list
577 * @entry: entry to add
578 *
579 * Add the page directory to the list of BOs to
580 * validate for command submission.
581 */
582void amdgpu_vm_get_pd_bo(struct amdgpu_vm *vm,
583 struct list_head *validated,
584 struct amdgpu_bo_list_entry *entry)
585{
586 entry->priority = 0;
587 entry->tv.bo = &vm->root.base.bo->tbo;
588 /* Two for VM updates, one for TTM and one for the CS job */
589 entry->tv.num_shared = 4;
590 entry->user_pages = NULL;
591 list_add(&entry->tv.head, validated);
592}
593
594/**
595 * amdgpu_vm_del_from_lru_notify - update bulk_moveable flag
596 *
597 * @bo: BO which was removed from the LRU
598 *
599 * Make sure the bulk_moveable flag is updated when a BO is removed from the
600 * LRU.
601 */
602void amdgpu_vm_del_from_lru_notify(struct ttm_buffer_object *bo)
603{
604 struct amdgpu_bo *abo;
605 struct amdgpu_vm_bo_base *bo_base;
606
607 if (!amdgpu_bo_is_amdgpu_bo(bo))
608 return;
609
610 if (bo->mem.placement & TTM_PL_FLAG_NO_EVICT)
611 return;
612
613 abo = ttm_to_amdgpu_bo(bo);
614 if (!abo->parent)
615 return;
616 for (bo_base = abo->vm_bo; bo_base; bo_base = bo_base->next) {
617 struct amdgpu_vm *vm = bo_base->vm;
618
619 if (abo->tbo.base.resv == vm->root.base.bo->tbo.base.resv)
620 vm->bulk_moveable = false;
621 }
622
623}
624/**
625 * amdgpu_vm_move_to_lru_tail - move all BOs to the end of LRU
626 *
627 * @adev: amdgpu device pointer
628 * @vm: vm providing the BOs
629 *
630 * Move all BOs to the end of LRU and remember their positions to put them
631 * together.
632 */
633void amdgpu_vm_move_to_lru_tail(struct amdgpu_device *adev,
634 struct amdgpu_vm *vm)
635{
636 struct amdgpu_vm_bo_base *bo_base;
637
638 if (vm->bulk_moveable) {
639 spin_lock(&ttm_bo_glob.lru_lock);
640 ttm_bo_bulk_move_lru_tail(&vm->lru_bulk_move);
641 spin_unlock(&ttm_bo_glob.lru_lock);
642 return;
643 }
644
645 memset(&vm->lru_bulk_move, 0, sizeof(vm->lru_bulk_move));
646
647 spin_lock(&ttm_bo_glob.lru_lock);
648 list_for_each_entry(bo_base, &vm->idle, vm_status) {
649 struct amdgpu_bo *bo = bo_base->bo;
650
651 if (!bo->parent)
652 continue;
653
654 ttm_bo_move_to_lru_tail(&bo->tbo, &vm->lru_bulk_move);
655 if (bo->shadow)
656 ttm_bo_move_to_lru_tail(&bo->shadow->tbo,
657 &vm->lru_bulk_move);
658 }
659 spin_unlock(&ttm_bo_glob.lru_lock);
660
661 vm->bulk_moveable = true;
662}
663
664/**
665 * amdgpu_vm_validate_pt_bos - validate the page table BOs
666 *
667 * @adev: amdgpu device pointer
668 * @vm: vm providing the BOs
669 * @validate: callback to do the validation
670 * @param: parameter for the validation callback
671 *
672 * Validate the page table BOs on command submission if neccessary.
673 *
674 * Returns:
675 * Validation result.
676 */
677int amdgpu_vm_validate_pt_bos(struct amdgpu_device *adev, struct amdgpu_vm *vm,
678 int (*validate)(void *p, struct amdgpu_bo *bo),
679 void *param)
680{
681 struct amdgpu_vm_bo_base *bo_base, *tmp;
682 int r;
683
684 vm->bulk_moveable &= list_empty(&vm->evicted);
685
686 list_for_each_entry_safe(bo_base, tmp, &vm->evicted, vm_status) {
687 struct amdgpu_bo *bo = bo_base->bo;
688
689 r = validate(param, bo);
690 if (r)
691 return r;
692
693 if (bo->tbo.type != ttm_bo_type_kernel) {
694 amdgpu_vm_bo_moved(bo_base);
695 } else {
696 vm->update_funcs->map_table(bo);
697 amdgpu_vm_bo_relocated(bo_base);
698 }
699 }
700
701 amdgpu_vm_eviction_lock(vm);
702 vm->evicting = false;
703 amdgpu_vm_eviction_unlock(vm);
704
705 return 0;
706}
707
708/**
709 * amdgpu_vm_ready - check VM is ready for updates
710 *
711 * @vm: VM to check
712 *
713 * Check if all VM PDs/PTs are ready for updates
714 *
715 * Returns:
716 * True if eviction list is empty.
717 */
718bool amdgpu_vm_ready(struct amdgpu_vm *vm)
719{
720 return list_empty(&vm->evicted);
721}
722
723/**
724 * amdgpu_vm_clear_bo - initially clear the PDs/PTs
725 *
726 * @adev: amdgpu_device pointer
727 * @vm: VM to clear BO from
728 * @bo: BO to clear
729 * @immediate: use an immediate update
730 *
731 * Root PD needs to be reserved when calling this.
732 *
733 * Returns:
734 * 0 on success, errno otherwise.
735 */
736static int amdgpu_vm_clear_bo(struct amdgpu_device *adev,
737 struct amdgpu_vm *vm,
738 struct amdgpu_bo *bo,
739 bool immediate)
740{
741 struct ttm_operation_ctx ctx = { true, false };
742 unsigned level = adev->vm_manager.root_level;
743 struct amdgpu_vm_update_params params;
744 struct amdgpu_bo *ancestor = bo;
745 unsigned entries, ats_entries;
746 uint64_t addr;
747 int r;
748
749 /* Figure out our place in the hierarchy */
750 if (ancestor->parent) {
751 ++level;
752 while (ancestor->parent->parent) {
753 ++level;
754 ancestor = ancestor->parent;
755 }
756 }
757
758 entries = amdgpu_bo_size(bo) / 8;
759 if (!vm->pte_support_ats) {
760 ats_entries = 0;
761
762 } else if (!bo->parent) {
763 ats_entries = amdgpu_vm_num_ats_entries(adev);
764 ats_entries = min(ats_entries, entries);
765 entries -= ats_entries;
766
767 } else {
768 struct amdgpu_vm_pt *pt;
769
770 pt = container_of(ancestor->vm_bo, struct amdgpu_vm_pt, base);
771 ats_entries = amdgpu_vm_num_ats_entries(adev);
772 if ((pt - vm->root.entries) >= ats_entries) {
773 ats_entries = 0;
774 } else {
775 ats_entries = entries;
776 entries = 0;
777 }
778 }
779
780 r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
781 if (r)
782 return r;
783
784 if (bo->shadow) {
785 r = ttm_bo_validate(&bo->shadow->tbo, &bo->shadow->placement,
786 &ctx);
787 if (r)
788 return r;
789 }
790
791 r = vm->update_funcs->map_table(bo);
792 if (r)
793 return r;
794
795 memset(¶ms, 0, sizeof(params));
796 params.adev = adev;
797 params.vm = vm;
798 params.immediate = immediate;
799
800 r = vm->update_funcs->prepare(¶ms, NULL, AMDGPU_SYNC_EXPLICIT);
801 if (r)
802 return r;
803
804 addr = 0;
805 if (ats_entries) {
806 uint64_t value = 0, flags;
807
808 flags = AMDGPU_PTE_DEFAULT_ATC;
809 if (level != AMDGPU_VM_PTB) {
810 /* Handle leaf PDEs as PTEs */
811 flags |= AMDGPU_PDE_PTE;
812 amdgpu_gmc_get_vm_pde(adev, level, &value, &flags);
813 }
814
815 r = vm->update_funcs->update(¶ms, bo, addr, 0, ats_entries,
816 value, flags);
817 if (r)
818 return r;
819
820 addr += ats_entries * 8;
821 }
822
823 if (entries) {
824 uint64_t value = 0, flags = 0;
825
826 if (adev->asic_type >= CHIP_VEGA10) {
827 if (level != AMDGPU_VM_PTB) {
828 /* Handle leaf PDEs as PTEs */
829 flags |= AMDGPU_PDE_PTE;
830 amdgpu_gmc_get_vm_pde(adev, level,
831 &value, &flags);
832 } else {
833 /* Workaround for fault priority problem on GMC9 */
834 flags = AMDGPU_PTE_EXECUTABLE;
835 }
836 }
837
838 r = vm->update_funcs->update(¶ms, bo, addr, 0, entries,
839 value, flags);
840 if (r)
841 return r;
842 }
843
844 return vm->update_funcs->commit(¶ms, NULL);
845}
846
847/**
848 * amdgpu_vm_bo_param - fill in parameters for PD/PT allocation
849 *
850 * @adev: amdgpu_device pointer
851 * @vm: requesting vm
852 * @level: the page table level
853 * @immediate: use a immediate update
854 * @bp: resulting BO allocation parameters
855 */
856static void amdgpu_vm_bo_param(struct amdgpu_device *adev, struct amdgpu_vm *vm,
857 int level, bool immediate,
858 struct amdgpu_bo_param *bp)
859{
860 memset(bp, 0, sizeof(*bp));
861
862 bp->size = amdgpu_vm_bo_size(adev, level);
863 bp->byte_align = AMDGPU_GPU_PAGE_SIZE;
864 bp->domain = AMDGPU_GEM_DOMAIN_VRAM;
865 bp->domain = amdgpu_bo_get_preferred_pin_domain(adev, bp->domain);
866 bp->flags = AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS |
867 AMDGPU_GEM_CREATE_CPU_GTT_USWC;
868 if (vm->use_cpu_for_update)
869 bp->flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
870 else if (!vm->root.base.bo || vm->root.base.bo->shadow)
871 bp->flags |= AMDGPU_GEM_CREATE_SHADOW;
872 bp->type = ttm_bo_type_kernel;
873 bp->no_wait_gpu = immediate;
874 if (vm->root.base.bo)
875 bp->resv = vm->root.base.bo->tbo.base.resv;
876}
877
878/**
879 * amdgpu_vm_alloc_pts - Allocate a specific page table
880 *
881 * @adev: amdgpu_device pointer
882 * @vm: VM to allocate page tables for
883 * @cursor: Which page table to allocate
884 * @immediate: use an immediate update
885 *
886 * Make sure a specific page table or directory is allocated.
887 *
888 * Returns:
889 * 1 if page table needed to be allocated, 0 if page table was already
890 * allocated, negative errno if an error occurred.
891 */
892static int amdgpu_vm_alloc_pts(struct amdgpu_device *adev,
893 struct amdgpu_vm *vm,
894 struct amdgpu_vm_pt_cursor *cursor,
895 bool immediate)
896{
897 struct amdgpu_vm_pt *entry = cursor->entry;
898 struct amdgpu_bo_param bp;
899 struct amdgpu_bo *pt;
900 int r;
901
902 if (cursor->level < AMDGPU_VM_PTB && !entry->entries) {
903 unsigned num_entries;
904
905 num_entries = amdgpu_vm_num_entries(adev, cursor->level);
906 entry->entries = kvmalloc_array(num_entries,
907 sizeof(*entry->entries),
908 GFP_KERNEL | __GFP_ZERO);
909 if (!entry->entries)
910 return -ENOMEM;
911 }
912
913 if (entry->base.bo)
914 return 0;
915
916 amdgpu_vm_bo_param(adev, vm, cursor->level, immediate, &bp);
917
918 r = amdgpu_bo_create(adev, &bp, &pt);
919 if (r)
920 return r;
921
922 /* Keep a reference to the root directory to avoid
923 * freeing them up in the wrong order.
924 */
925 pt->parent = amdgpu_bo_ref(cursor->parent->base.bo);
926 amdgpu_vm_bo_base_init(&entry->base, vm, pt);
927
928 r = amdgpu_vm_clear_bo(adev, vm, pt, immediate);
929 if (r)
930 goto error_free_pt;
931
932 return 0;
933
934error_free_pt:
935 amdgpu_bo_unref(&pt->shadow);
936 amdgpu_bo_unref(&pt);
937 return r;
938}
939
940/**
941 * amdgpu_vm_free_table - fre one PD/PT
942 *
943 * @entry: PDE to free
944 */
945static void amdgpu_vm_free_table(struct amdgpu_vm_pt *entry)
946{
947 if (entry->base.bo) {
948 entry->base.bo->vm_bo = NULL;
949 list_del(&entry->base.vm_status);
950 amdgpu_bo_unref(&entry->base.bo->shadow);
951 amdgpu_bo_unref(&entry->base.bo);
952 }
953 kvfree(entry->entries);
954 entry->entries = NULL;
955}
956
957/**
958 * amdgpu_vm_free_pts - free PD/PT levels
959 *
960 * @adev: amdgpu device structure
961 * @vm: amdgpu vm structure
962 * @start: optional cursor where to start freeing PDs/PTs
963 *
964 * Free the page directory or page table level and all sub levels.
965 */
966static void amdgpu_vm_free_pts(struct amdgpu_device *adev,
967 struct amdgpu_vm *vm,
968 struct amdgpu_vm_pt_cursor *start)
969{
970 struct amdgpu_vm_pt_cursor cursor;
971 struct amdgpu_vm_pt *entry;
972
973 vm->bulk_moveable = false;
974
975 for_each_amdgpu_vm_pt_dfs_safe(adev, vm, start, cursor, entry)
976 amdgpu_vm_free_table(entry);
977
978 if (start)
979 amdgpu_vm_free_table(start->entry);
980}
981
982/**
983 * amdgpu_vm_check_compute_bug - check whether asic has compute vm bug
984 *
985 * @adev: amdgpu_device pointer
986 */
987void amdgpu_vm_check_compute_bug(struct amdgpu_device *adev)
988{
989 const struct amdgpu_ip_block *ip_block;
990 bool has_compute_vm_bug;
991 struct amdgpu_ring *ring;
992 int i;
993
994 has_compute_vm_bug = false;
995
996 ip_block = amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_GFX);
997 if (ip_block) {
998 /* Compute has a VM bug for GFX version < 7.
999 Compute has a VM bug for GFX 8 MEC firmware version < 673.*/
1000 if (ip_block->version->major <= 7)
1001 has_compute_vm_bug = true;
1002 else if (ip_block->version->major == 8)
1003 if (adev->gfx.mec_fw_version < 673)
1004 has_compute_vm_bug = true;
1005 }
1006
1007 for (i = 0; i < adev->num_rings; i++) {
1008 ring = adev->rings[i];
1009 if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE)
1010 /* only compute rings */
1011 ring->has_compute_vm_bug = has_compute_vm_bug;
1012 else
1013 ring->has_compute_vm_bug = false;
1014 }
1015}
1016
1017/**
1018 * amdgpu_vm_need_pipeline_sync - Check if pipe sync is needed for job.
1019 *
1020 * @ring: ring on which the job will be submitted
1021 * @job: job to submit
1022 *
1023 * Returns:
1024 * True if sync is needed.
1025 */
1026bool amdgpu_vm_need_pipeline_sync(struct amdgpu_ring *ring,
1027 struct amdgpu_job *job)
1028{
1029 struct amdgpu_device *adev = ring->adev;
1030 unsigned vmhub = ring->funcs->vmhub;
1031 struct amdgpu_vmid_mgr *id_mgr = &adev->vm_manager.id_mgr[vmhub];
1032 struct amdgpu_vmid *id;
1033 bool gds_switch_needed;
1034 bool vm_flush_needed = job->vm_needs_flush || ring->has_compute_vm_bug;
1035
1036 if (job->vmid == 0)
1037 return false;
1038 id = &id_mgr->ids[job->vmid];
1039 gds_switch_needed = ring->funcs->emit_gds_switch && (
1040 id->gds_base != job->gds_base ||
1041 id->gds_size != job->gds_size ||
1042 id->gws_base != job->gws_base ||
1043 id->gws_size != job->gws_size ||
1044 id->oa_base != job->oa_base ||
1045 id->oa_size != job->oa_size);
1046
1047 if (amdgpu_vmid_had_gpu_reset(adev, id))
1048 return true;
1049
1050 return vm_flush_needed || gds_switch_needed;
1051}
1052
1053/**
1054 * amdgpu_vm_flush - hardware flush the vm
1055 *
1056 * @ring: ring to use for flush
1057 * @job: related job
1058 * @need_pipe_sync: is pipe sync needed
1059 *
1060 * Emit a VM flush when it is necessary.
1061 *
1062 * Returns:
1063 * 0 on success, errno otherwise.
1064 */
1065int amdgpu_vm_flush(struct amdgpu_ring *ring, struct amdgpu_job *job,
1066 bool need_pipe_sync)
1067{
1068 struct amdgpu_device *adev = ring->adev;
1069 unsigned vmhub = ring->funcs->vmhub;
1070 struct amdgpu_vmid_mgr *id_mgr = &adev->vm_manager.id_mgr[vmhub];
1071 struct amdgpu_vmid *id = &id_mgr->ids[job->vmid];
1072 bool gds_switch_needed = ring->funcs->emit_gds_switch && (
1073 id->gds_base != job->gds_base ||
1074 id->gds_size != job->gds_size ||
1075 id->gws_base != job->gws_base ||
1076 id->gws_size != job->gws_size ||
1077 id->oa_base != job->oa_base ||
1078 id->oa_size != job->oa_size);
1079 bool vm_flush_needed = job->vm_needs_flush;
1080 struct dma_fence *fence = NULL;
1081 bool pasid_mapping_needed = false;
1082 unsigned patch_offset = 0;
1083 bool update_spm_vmid_needed = (job->vm && (job->vm->reserved_vmid[vmhub] != NULL));
1084 int r;
1085
1086 if (update_spm_vmid_needed && adev->gfx.rlc.funcs->update_spm_vmid)
1087 adev->gfx.rlc.funcs->update_spm_vmid(adev, job->vmid);
1088
1089 if (amdgpu_vmid_had_gpu_reset(adev, id)) {
1090 gds_switch_needed = true;
1091 vm_flush_needed = true;
1092 pasid_mapping_needed = true;
1093 }
1094
1095 mutex_lock(&id_mgr->lock);
1096 if (id->pasid != job->pasid || !id->pasid_mapping ||
1097 !dma_fence_is_signaled(id->pasid_mapping))
1098 pasid_mapping_needed = true;
1099 mutex_unlock(&id_mgr->lock);
1100
1101 gds_switch_needed &= !!ring->funcs->emit_gds_switch;
1102 vm_flush_needed &= !!ring->funcs->emit_vm_flush &&
1103 job->vm_pd_addr != AMDGPU_BO_INVALID_OFFSET;
1104 pasid_mapping_needed &= adev->gmc.gmc_funcs->emit_pasid_mapping &&
1105 ring->funcs->emit_wreg;
1106
1107 if (!vm_flush_needed && !gds_switch_needed && !need_pipe_sync)
1108 return 0;
1109
1110 if (ring->funcs->init_cond_exec)
1111 patch_offset = amdgpu_ring_init_cond_exec(ring);
1112
1113 if (need_pipe_sync)
1114 amdgpu_ring_emit_pipeline_sync(ring);
1115
1116 if (vm_flush_needed) {
1117 trace_amdgpu_vm_flush(ring, job->vmid, job->vm_pd_addr);
1118 amdgpu_ring_emit_vm_flush(ring, job->vmid, job->vm_pd_addr);
1119 }
1120
1121 if (pasid_mapping_needed)
1122 amdgpu_gmc_emit_pasid_mapping(ring, job->vmid, job->pasid);
1123
1124 if (vm_flush_needed || pasid_mapping_needed) {
1125 r = amdgpu_fence_emit(ring, &fence, 0);
1126 if (r)
1127 return r;
1128 }
1129
1130 if (vm_flush_needed) {
1131 mutex_lock(&id_mgr->lock);
1132 dma_fence_put(id->last_flush);
1133 id->last_flush = dma_fence_get(fence);
1134 id->current_gpu_reset_count =
1135 atomic_read(&adev->gpu_reset_counter);
1136 mutex_unlock(&id_mgr->lock);
1137 }
1138
1139 if (pasid_mapping_needed) {
1140 mutex_lock(&id_mgr->lock);
1141 id->pasid = job->pasid;
1142 dma_fence_put(id->pasid_mapping);
1143 id->pasid_mapping = dma_fence_get(fence);
1144 mutex_unlock(&id_mgr->lock);
1145 }
1146 dma_fence_put(fence);
1147
1148 if (ring->funcs->emit_gds_switch && gds_switch_needed) {
1149 id->gds_base = job->gds_base;
1150 id->gds_size = job->gds_size;
1151 id->gws_base = job->gws_base;
1152 id->gws_size = job->gws_size;
1153 id->oa_base = job->oa_base;
1154 id->oa_size = job->oa_size;
1155 amdgpu_ring_emit_gds_switch(ring, job->vmid, job->gds_base,
1156 job->gds_size, job->gws_base,
1157 job->gws_size, job->oa_base,
1158 job->oa_size);
1159 }
1160
1161 if (ring->funcs->patch_cond_exec)
1162 amdgpu_ring_patch_cond_exec(ring, patch_offset);
1163
1164 /* the double SWITCH_BUFFER here *cannot* be skipped by COND_EXEC */
1165 if (ring->funcs->emit_switch_buffer) {
1166 amdgpu_ring_emit_switch_buffer(ring);
1167 amdgpu_ring_emit_switch_buffer(ring);
1168 }
1169 return 0;
1170}
1171
1172/**
1173 * amdgpu_vm_bo_find - find the bo_va for a specific vm & bo
1174 *
1175 * @vm: requested vm
1176 * @bo: requested buffer object
1177 *
1178 * Find @bo inside the requested vm.
1179 * Search inside the @bos vm list for the requested vm
1180 * Returns the found bo_va or NULL if none is found
1181 *
1182 * Object has to be reserved!
1183 *
1184 * Returns:
1185 * Found bo_va or NULL.
1186 */
1187struct amdgpu_bo_va *amdgpu_vm_bo_find(struct amdgpu_vm *vm,
1188 struct amdgpu_bo *bo)
1189{
1190 struct amdgpu_vm_bo_base *base;
1191
1192 for (base = bo->vm_bo; base; base = base->next) {
1193 if (base->vm != vm)
1194 continue;
1195
1196 return container_of(base, struct amdgpu_bo_va, base);
1197 }
1198 return NULL;
1199}
1200
1201/**
1202 * amdgpu_vm_map_gart - Resolve gart mapping of addr
1203 *
1204 * @pages_addr: optional DMA address to use for lookup
1205 * @addr: the unmapped addr
1206 *
1207 * Look up the physical address of the page that the pte resolves
1208 * to.
1209 *
1210 * Returns:
1211 * The pointer for the page table entry.
1212 */
1213uint64_t amdgpu_vm_map_gart(const dma_addr_t *pages_addr, uint64_t addr)
1214{
1215 uint64_t result;
1216
1217 /* page table offset */
1218 result = pages_addr[addr >> PAGE_SHIFT];
1219
1220 /* in case cpu page size != gpu page size*/
1221 result |= addr & (~PAGE_MASK);
1222
1223 result &= 0xFFFFFFFFFFFFF000ULL;
1224
1225 return result;
1226}
1227
1228/**
1229 * amdgpu_vm_update_pde - update a single level in the hierarchy
1230 *
1231 * @params: parameters for the update
1232 * @vm: requested vm
1233 * @entry: entry to update
1234 *
1235 * Makes sure the requested entry in parent is up to date.
1236 */
1237static int amdgpu_vm_update_pde(struct amdgpu_vm_update_params *params,
1238 struct amdgpu_vm *vm,
1239 struct amdgpu_vm_pt *entry)
1240{
1241 struct amdgpu_vm_pt *parent = amdgpu_vm_pt_parent(entry);
1242 struct amdgpu_bo *bo = parent->base.bo, *pbo;
1243 uint64_t pde, pt, flags;
1244 unsigned level;
1245
1246 for (level = 0, pbo = bo->parent; pbo; ++level)
1247 pbo = pbo->parent;
1248
1249 level += params->adev->vm_manager.root_level;
1250 amdgpu_gmc_get_pde_for_bo(entry->base.bo, level, &pt, &flags);
1251 pde = (entry - parent->entries) * 8;
1252 return vm->update_funcs->update(params, bo, pde, pt, 1, 0, flags);
1253}
1254
1255/**
1256 * amdgpu_vm_invalidate_pds - mark all PDs as invalid
1257 *
1258 * @adev: amdgpu_device pointer
1259 * @vm: related vm
1260 *
1261 * Mark all PD level as invalid after an error.
1262 */
1263static void amdgpu_vm_invalidate_pds(struct amdgpu_device *adev,
1264 struct amdgpu_vm *vm)
1265{
1266 struct amdgpu_vm_pt_cursor cursor;
1267 struct amdgpu_vm_pt *entry;
1268
1269 for_each_amdgpu_vm_pt_dfs_safe(adev, vm, NULL, cursor, entry)
1270 if (entry->base.bo && !entry->base.moved)
1271 amdgpu_vm_bo_relocated(&entry->base);
1272}
1273
1274/**
1275 * amdgpu_vm_update_pdes - make sure that all directories are valid
1276 *
1277 * @adev: amdgpu_device pointer
1278 * @vm: requested vm
1279 * @immediate: submit immediately to the paging queue
1280 *
1281 * Makes sure all directories are up to date.
1282 *
1283 * Returns:
1284 * 0 for success, error for failure.
1285 */
1286int amdgpu_vm_update_pdes(struct amdgpu_device *adev,
1287 struct amdgpu_vm *vm, bool immediate)
1288{
1289 struct amdgpu_vm_update_params params;
1290 int r;
1291
1292 if (list_empty(&vm->relocated))
1293 return 0;
1294
1295 memset(¶ms, 0, sizeof(params));
1296 params.adev = adev;
1297 params.vm = vm;
1298 params.immediate = immediate;
1299
1300 r = vm->update_funcs->prepare(¶ms, NULL, AMDGPU_SYNC_EXPLICIT);
1301 if (r)
1302 return r;
1303
1304 while (!list_empty(&vm->relocated)) {
1305 struct amdgpu_vm_pt *entry;
1306
1307 entry = list_first_entry(&vm->relocated, struct amdgpu_vm_pt,
1308 base.vm_status);
1309 amdgpu_vm_bo_idle(&entry->base);
1310
1311 r = amdgpu_vm_update_pde(¶ms, vm, entry);
1312 if (r)
1313 goto error;
1314 }
1315
1316 r = vm->update_funcs->commit(¶ms, &vm->last_update);
1317 if (r)
1318 goto error;
1319 return 0;
1320
1321error:
1322 amdgpu_vm_invalidate_pds(adev, vm);
1323 return r;
1324}
1325
1326/*
1327 * amdgpu_vm_update_flags - figure out flags for PTE updates
1328 *
1329 * Make sure to set the right flags for the PTEs at the desired level.
1330 */
1331static void amdgpu_vm_update_flags(struct amdgpu_vm_update_params *params,
1332 struct amdgpu_bo *bo, unsigned level,
1333 uint64_t pe, uint64_t addr,
1334 unsigned count, uint32_t incr,
1335 uint64_t flags)
1336
1337{
1338 if (level != AMDGPU_VM_PTB) {
1339 flags |= AMDGPU_PDE_PTE;
1340 amdgpu_gmc_get_vm_pde(params->adev, level, &addr, &flags);
1341
1342 } else if (params->adev->asic_type >= CHIP_VEGA10 &&
1343 !(flags & AMDGPU_PTE_VALID) &&
1344 !(flags & AMDGPU_PTE_PRT)) {
1345
1346 /* Workaround for fault priority problem on GMC9 */
1347 flags |= AMDGPU_PTE_EXECUTABLE;
1348 }
1349
1350 params->vm->update_funcs->update(params, bo, pe, addr, count, incr,
1351 flags);
1352}
1353
1354/**
1355 * amdgpu_vm_fragment - get fragment for PTEs
1356 *
1357 * @params: see amdgpu_vm_update_params definition
1358 * @start: first PTE to handle
1359 * @end: last PTE to handle
1360 * @flags: hw mapping flags
1361 * @frag: resulting fragment size
1362 * @frag_end: end of this fragment
1363 *
1364 * Returns the first possible fragment for the start and end address.
1365 */
1366static void amdgpu_vm_fragment(struct amdgpu_vm_update_params *params,
1367 uint64_t start, uint64_t end, uint64_t flags,
1368 unsigned int *frag, uint64_t *frag_end)
1369{
1370 /**
1371 * The MC L1 TLB supports variable sized pages, based on a fragment
1372 * field in the PTE. When this field is set to a non-zero value, page
1373 * granularity is increased from 4KB to (1 << (12 + frag)). The PTE
1374 * flags are considered valid for all PTEs within the fragment range
1375 * and corresponding mappings are assumed to be physically contiguous.
1376 *
1377 * The L1 TLB can store a single PTE for the whole fragment,
1378 * significantly increasing the space available for translation
1379 * caching. This leads to large improvements in throughput when the
1380 * TLB is under pressure.
1381 *
1382 * The L2 TLB distributes small and large fragments into two
1383 * asymmetric partitions. The large fragment cache is significantly
1384 * larger. Thus, we try to use large fragments wherever possible.
1385 * Userspace can support this by aligning virtual base address and
1386 * allocation size to the fragment size.
1387 *
1388 * Starting with Vega10 the fragment size only controls the L1. The L2
1389 * is now directly feed with small/huge/giant pages from the walker.
1390 */
1391 unsigned max_frag;
1392
1393 if (params->adev->asic_type < CHIP_VEGA10)
1394 max_frag = params->adev->vm_manager.fragment_size;
1395 else
1396 max_frag = 31;
1397
1398 /* system pages are non continuously */
1399 if (params->pages_addr) {
1400 *frag = 0;
1401 *frag_end = end;
1402 return;
1403 }
1404
1405 /* This intentionally wraps around if no bit is set */
1406 *frag = min((unsigned)ffs(start) - 1, (unsigned)fls64(end - start) - 1);
1407 if (*frag >= max_frag) {
1408 *frag = max_frag;
1409 *frag_end = end & ~((1ULL << max_frag) - 1);
1410 } else {
1411 *frag_end = start + (1 << *frag);
1412 }
1413}
1414
1415/**
1416 * amdgpu_vm_update_ptes - make sure that page tables are valid
1417 *
1418 * @params: see amdgpu_vm_update_params definition
1419 * @start: start of GPU address range
1420 * @end: end of GPU address range
1421 * @dst: destination address to map to, the next dst inside the function
1422 * @flags: mapping flags
1423 *
1424 * Update the page tables in the range @start - @end.
1425 *
1426 * Returns:
1427 * 0 for success, -EINVAL for failure.
1428 */
1429static int amdgpu_vm_update_ptes(struct amdgpu_vm_update_params *params,
1430 uint64_t start, uint64_t end,
1431 uint64_t dst, uint64_t flags)
1432{
1433 struct amdgpu_device *adev = params->adev;
1434 struct amdgpu_vm_pt_cursor cursor;
1435 uint64_t frag_start = start, frag_end;
1436 unsigned int frag;
1437 int r;
1438
1439 /* figure out the initial fragment */
1440 amdgpu_vm_fragment(params, frag_start, end, flags, &frag, &frag_end);
1441
1442 /* walk over the address space and update the PTs */
1443 amdgpu_vm_pt_start(adev, params->vm, start, &cursor);
1444 while (cursor.pfn < end) {
1445 unsigned shift, parent_shift, mask;
1446 uint64_t incr, entry_end, pe_start;
1447 struct amdgpu_bo *pt;
1448
1449 if (!params->unlocked) {
1450 /* make sure that the page tables covering the
1451 * address range are actually allocated
1452 */
1453 r = amdgpu_vm_alloc_pts(params->adev, params->vm,
1454 &cursor, params->immediate);
1455 if (r)
1456 return r;
1457 }
1458
1459 shift = amdgpu_vm_level_shift(adev, cursor.level);
1460 parent_shift = amdgpu_vm_level_shift(adev, cursor.level - 1);
1461 if (params->unlocked) {
1462 /* Unlocked updates are only allowed on the leaves */
1463 if (amdgpu_vm_pt_descendant(adev, &cursor))
1464 continue;
1465 } else if (adev->asic_type < CHIP_VEGA10 &&
1466 (flags & AMDGPU_PTE_VALID)) {
1467 /* No huge page support before GMC v9 */
1468 if (cursor.level != AMDGPU_VM_PTB) {
1469 if (!amdgpu_vm_pt_descendant(adev, &cursor))
1470 return -ENOENT;
1471 continue;
1472 }
1473 } else if (frag < shift) {
1474 /* We can't use this level when the fragment size is
1475 * smaller than the address shift. Go to the next
1476 * child entry and try again.
1477 */
1478 if (amdgpu_vm_pt_descendant(adev, &cursor))
1479 continue;
1480 } else if (frag >= parent_shift) {
1481 /* If the fragment size is even larger than the parent
1482 * shift we should go up one level and check it again.
1483 */
1484 if (!amdgpu_vm_pt_ancestor(&cursor))
1485 return -EINVAL;
1486 continue;
1487 }
1488
1489 pt = cursor.entry->base.bo;
1490 if (!pt) {
1491 /* We need all PDs and PTs for mapping something, */
1492 if (flags & AMDGPU_PTE_VALID)
1493 return -ENOENT;
1494
1495 /* but unmapping something can happen at a higher
1496 * level.
1497 */
1498 if (!amdgpu_vm_pt_ancestor(&cursor))
1499 return -EINVAL;
1500
1501 pt = cursor.entry->base.bo;
1502 shift = parent_shift;
1503 }
1504
1505 /* Looks good so far, calculate parameters for the update */
1506 incr = (uint64_t)AMDGPU_GPU_PAGE_SIZE << shift;
1507 mask = amdgpu_vm_entries_mask(adev, cursor.level);
1508 pe_start = ((cursor.pfn >> shift) & mask) * 8;
1509 entry_end = ((uint64_t)mask + 1) << shift;
1510 entry_end += cursor.pfn & ~(entry_end - 1);
1511 entry_end = min(entry_end, end);
1512
1513 do {
1514 uint64_t upd_end = min(entry_end, frag_end);
1515 unsigned nptes = (upd_end - frag_start) >> shift;
1516
1517 /* This can happen when we set higher level PDs to
1518 * silent to stop fault floods.
1519 */
1520 nptes = max(nptes, 1u);
1521 amdgpu_vm_update_flags(params, pt, cursor.level,
1522 pe_start, dst, nptes, incr,
1523 flags | AMDGPU_PTE_FRAG(frag));
1524
1525 pe_start += nptes * 8;
1526 dst += (uint64_t)nptes * AMDGPU_GPU_PAGE_SIZE << shift;
1527
1528 frag_start = upd_end;
1529 if (frag_start >= frag_end) {
1530 /* figure out the next fragment */
1531 amdgpu_vm_fragment(params, frag_start, end,
1532 flags, &frag, &frag_end);
1533 if (frag < shift)
1534 break;
1535 }
1536 } while (frag_start < entry_end);
1537
1538 if (amdgpu_vm_pt_descendant(adev, &cursor)) {
1539 /* Free all child entries.
1540 * Update the tables with the flags and addresses and free up subsequent
1541 * tables in the case of huge pages or freed up areas.
1542 * This is the maximum you can free, because all other page tables are not
1543 * completely covered by the range and so potentially still in use.
1544 */
1545 while (cursor.pfn < frag_start) {
1546 amdgpu_vm_free_pts(adev, params->vm, &cursor);
1547 amdgpu_vm_pt_next(adev, &cursor);
1548 }
1549
1550 } else if (frag >= shift) {
1551 /* or just move on to the next on the same level. */
1552 amdgpu_vm_pt_next(adev, &cursor);
1553 }
1554 }
1555
1556 return 0;
1557}
1558
1559/**
1560 * amdgpu_vm_bo_update_mapping - update a mapping in the vm page table
1561 *
1562 * @adev: amdgpu_device pointer
1563 * @vm: requested vm
1564 * @immediate: immediate submission in a page fault
1565 * @unlocked: unlocked invalidation during MM callback
1566 * @resv: fences we need to sync to
1567 * @start: start of mapped range
1568 * @last: last mapped entry
1569 * @flags: flags for the entries
1570 * @addr: addr to set the area to
1571 * @pages_addr: DMA addresses to use for mapping
1572 * @fence: optional resulting fence
1573 *
1574 * Fill in the page table entries between @start and @last.
1575 *
1576 * Returns:
1577 * 0 for success, -EINVAL for failure.
1578 */
1579static int amdgpu_vm_bo_update_mapping(struct amdgpu_device *adev,
1580 struct amdgpu_vm *vm, bool immediate,
1581 bool unlocked, struct dma_resv *resv,
1582 uint64_t start, uint64_t last,
1583 uint64_t flags, uint64_t addr,
1584 dma_addr_t *pages_addr,
1585 struct dma_fence **fence)
1586{
1587 struct amdgpu_vm_update_params params;
1588 enum amdgpu_sync_mode sync_mode;
1589 int r;
1590
1591 memset(¶ms, 0, sizeof(params));
1592 params.adev = adev;
1593 params.vm = vm;
1594 params.immediate = immediate;
1595 params.pages_addr = pages_addr;
1596 params.unlocked = unlocked;
1597
1598 /* Implicitly sync to command submissions in the same VM before
1599 * unmapping. Sync to moving fences before mapping.
1600 */
1601 if (!(flags & AMDGPU_PTE_VALID))
1602 sync_mode = AMDGPU_SYNC_EQ_OWNER;
1603 else
1604 sync_mode = AMDGPU_SYNC_EXPLICIT;
1605
1606 amdgpu_vm_eviction_lock(vm);
1607 if (vm->evicting) {
1608 r = -EBUSY;
1609 goto error_unlock;
1610 }
1611
1612 if (!unlocked && !dma_fence_is_signaled(vm->last_unlocked)) {
1613 struct dma_fence *tmp = dma_fence_get_stub();
1614
1615 amdgpu_bo_fence(vm->root.base.bo, vm->last_unlocked, true);
1616 swap(vm->last_unlocked, tmp);
1617 dma_fence_put(tmp);
1618 }
1619
1620 r = vm->update_funcs->prepare(¶ms, resv, sync_mode);
1621 if (r)
1622 goto error_unlock;
1623
1624 r = amdgpu_vm_update_ptes(¶ms, start, last + 1, addr, flags);
1625 if (r)
1626 goto error_unlock;
1627
1628 r = vm->update_funcs->commit(¶ms, fence);
1629
1630error_unlock:
1631 amdgpu_vm_eviction_unlock(vm);
1632 return r;
1633}
1634
1635/**
1636 * amdgpu_vm_bo_split_mapping - split a mapping into smaller chunks
1637 *
1638 * @adev: amdgpu_device pointer
1639 * @resv: fences we need to sync to
1640 * @pages_addr: DMA addresses to use for mapping
1641 * @vm: requested vm
1642 * @mapping: mapped range and flags to use for the update
1643 * @flags: HW flags for the mapping
1644 * @bo_adev: amdgpu_device pointer that bo actually been allocated
1645 * @nodes: array of drm_mm_nodes with the MC addresses
1646 * @fence: optional resulting fence
1647 *
1648 * Split the mapping into smaller chunks so that each update fits
1649 * into a SDMA IB.
1650 *
1651 * Returns:
1652 * 0 for success, -EINVAL for failure.
1653 */
1654static int amdgpu_vm_bo_split_mapping(struct amdgpu_device *adev,
1655 struct dma_resv *resv,
1656 dma_addr_t *pages_addr,
1657 struct amdgpu_vm *vm,
1658 struct amdgpu_bo_va_mapping *mapping,
1659 uint64_t flags,
1660 struct amdgpu_device *bo_adev,
1661 struct drm_mm_node *nodes,
1662 struct dma_fence **fence)
1663{
1664 unsigned min_linear_pages = 1 << adev->vm_manager.fragment_size;
1665 uint64_t pfn, start = mapping->start;
1666 int r;
1667
1668 /* normally,bo_va->flags only contians READABLE and WIRTEABLE bit go here
1669 * but in case of something, we filter the flags in first place
1670 */
1671 if (!(mapping->flags & AMDGPU_PTE_READABLE))
1672 flags &= ~AMDGPU_PTE_READABLE;
1673 if (!(mapping->flags & AMDGPU_PTE_WRITEABLE))
1674 flags &= ~AMDGPU_PTE_WRITEABLE;
1675
1676 /* Apply ASIC specific mapping flags */
1677 amdgpu_gmc_get_vm_pte(adev, mapping, &flags);
1678
1679 trace_amdgpu_vm_bo_update(mapping);
1680
1681 pfn = mapping->offset >> PAGE_SHIFT;
1682 if (nodes) {
1683 while (pfn >= nodes->size) {
1684 pfn -= nodes->size;
1685 ++nodes;
1686 }
1687 }
1688
1689 do {
1690 dma_addr_t *dma_addr = NULL;
1691 uint64_t max_entries;
1692 uint64_t addr, last;
1693
1694 if (nodes) {
1695 addr = nodes->start << PAGE_SHIFT;
1696 max_entries = (nodes->size - pfn) *
1697 AMDGPU_GPU_PAGES_IN_CPU_PAGE;
1698 } else {
1699 addr = 0;
1700 max_entries = S64_MAX;
1701 }
1702
1703 if (pages_addr) {
1704 uint64_t count;
1705
1706 for (count = 1;
1707 count < max_entries / AMDGPU_GPU_PAGES_IN_CPU_PAGE;
1708 ++count) {
1709 uint64_t idx = pfn + count;
1710
1711 if (pages_addr[idx] !=
1712 (pages_addr[idx - 1] + PAGE_SIZE))
1713 break;
1714 }
1715
1716 if (count < min_linear_pages) {
1717 addr = pfn << PAGE_SHIFT;
1718 dma_addr = pages_addr;
1719 } else {
1720 addr = pages_addr[pfn];
1721 max_entries = count *
1722 AMDGPU_GPU_PAGES_IN_CPU_PAGE;
1723 }
1724
1725 } else if (flags & (AMDGPU_PTE_VALID | AMDGPU_PTE_PRT)) {
1726 addr += bo_adev->vm_manager.vram_base_offset;
1727 addr += pfn << PAGE_SHIFT;
1728 }
1729
1730 last = min((uint64_t)mapping->last, start + max_entries - 1);
1731 r = amdgpu_vm_bo_update_mapping(adev, vm, false, false, resv,
1732 start, last, flags, addr,
1733 dma_addr, fence);
1734 if (r)
1735 return r;
1736
1737 pfn += (last - start + 1) / AMDGPU_GPU_PAGES_IN_CPU_PAGE;
1738 if (nodes && nodes->size == pfn) {
1739 pfn = 0;
1740 ++nodes;
1741 }
1742 start = last + 1;
1743
1744 } while (unlikely(start != mapping->last + 1));
1745
1746 return 0;
1747}
1748
1749/**
1750 * amdgpu_vm_bo_update - update all BO mappings in the vm page table
1751 *
1752 * @adev: amdgpu_device pointer
1753 * @bo_va: requested BO and VM object
1754 * @clear: if true clear the entries
1755 *
1756 * Fill in the page table entries for @bo_va.
1757 *
1758 * Returns:
1759 * 0 for success, -EINVAL for failure.
1760 */
1761int amdgpu_vm_bo_update(struct amdgpu_device *adev, struct amdgpu_bo_va *bo_va,
1762 bool clear)
1763{
1764 struct amdgpu_bo *bo = bo_va->base.bo;
1765 struct amdgpu_vm *vm = bo_va->base.vm;
1766 struct amdgpu_bo_va_mapping *mapping;
1767 dma_addr_t *pages_addr = NULL;
1768 struct ttm_mem_reg *mem;
1769 struct drm_mm_node *nodes;
1770 struct dma_fence **last_update;
1771 struct dma_resv *resv;
1772 uint64_t flags;
1773 struct amdgpu_device *bo_adev = adev;
1774 int r;
1775
1776 if (clear || !bo) {
1777 mem = NULL;
1778 nodes = NULL;
1779 resv = vm->root.base.bo->tbo.base.resv;
1780 } else {
1781 struct ttm_dma_tt *ttm;
1782
1783 mem = &bo->tbo.mem;
1784 nodes = mem->mm_node;
1785 if (mem->mem_type == TTM_PL_TT) {
1786 ttm = container_of(bo->tbo.ttm, struct ttm_dma_tt, ttm);
1787 pages_addr = ttm->dma_address;
1788 }
1789 resv = bo->tbo.base.resv;
1790 }
1791
1792 if (bo) {
1793 flags = amdgpu_ttm_tt_pte_flags(adev, bo->tbo.ttm, mem);
1794
1795 if (amdgpu_bo_encrypted(bo))
1796 flags |= AMDGPU_PTE_TMZ;
1797
1798 bo_adev = amdgpu_ttm_adev(bo->tbo.bdev);
1799 } else {
1800 flags = 0x0;
1801 }
1802
1803 if (clear || (bo && bo->tbo.base.resv ==
1804 vm->root.base.bo->tbo.base.resv))
1805 last_update = &vm->last_update;
1806 else
1807 last_update = &bo_va->last_pt_update;
1808
1809 if (!clear && bo_va->base.moved) {
1810 bo_va->base.moved = false;
1811 list_splice_init(&bo_va->valids, &bo_va->invalids);
1812
1813 } else if (bo_va->cleared != clear) {
1814 list_splice_init(&bo_va->valids, &bo_va->invalids);
1815 }
1816
1817 list_for_each_entry(mapping, &bo_va->invalids, list) {
1818 r = amdgpu_vm_bo_split_mapping(adev, resv, pages_addr, vm,
1819 mapping, flags, bo_adev, nodes,
1820 last_update);
1821 if (r)
1822 return r;
1823 }
1824
1825 /* If the BO is not in its preferred location add it back to
1826 * the evicted list so that it gets validated again on the
1827 * next command submission.
1828 */
1829 if (bo && bo->tbo.base.resv == vm->root.base.bo->tbo.base.resv) {
1830 uint32_t mem_type = bo->tbo.mem.mem_type;
1831
1832 if (!(bo->preferred_domains &
1833 amdgpu_mem_type_to_domain(mem_type)))
1834 amdgpu_vm_bo_evicted(&bo_va->base);
1835 else
1836 amdgpu_vm_bo_idle(&bo_va->base);
1837 } else {
1838 amdgpu_vm_bo_done(&bo_va->base);
1839 }
1840
1841 list_splice_init(&bo_va->invalids, &bo_va->valids);
1842 bo_va->cleared = clear;
1843
1844 if (trace_amdgpu_vm_bo_mapping_enabled()) {
1845 list_for_each_entry(mapping, &bo_va->valids, list)
1846 trace_amdgpu_vm_bo_mapping(mapping);
1847 }
1848
1849 return 0;
1850}
1851
1852/**
1853 * amdgpu_vm_update_prt_state - update the global PRT state
1854 *
1855 * @adev: amdgpu_device pointer
1856 */
1857static void amdgpu_vm_update_prt_state(struct amdgpu_device *adev)
1858{
1859 unsigned long flags;
1860 bool enable;
1861
1862 spin_lock_irqsave(&adev->vm_manager.prt_lock, flags);
1863 enable = !!atomic_read(&adev->vm_manager.num_prt_users);
1864 adev->gmc.gmc_funcs->set_prt(adev, enable);
1865 spin_unlock_irqrestore(&adev->vm_manager.prt_lock, flags);
1866}
1867
1868/**
1869 * amdgpu_vm_prt_get - add a PRT user
1870 *
1871 * @adev: amdgpu_device pointer
1872 */
1873static void amdgpu_vm_prt_get(struct amdgpu_device *adev)
1874{
1875 if (!adev->gmc.gmc_funcs->set_prt)
1876 return;
1877
1878 if (atomic_inc_return(&adev->vm_manager.num_prt_users) == 1)
1879 amdgpu_vm_update_prt_state(adev);
1880}
1881
1882/**
1883 * amdgpu_vm_prt_put - drop a PRT user
1884 *
1885 * @adev: amdgpu_device pointer
1886 */
1887static void amdgpu_vm_prt_put(struct amdgpu_device *adev)
1888{
1889 if (atomic_dec_return(&adev->vm_manager.num_prt_users) == 0)
1890 amdgpu_vm_update_prt_state(adev);
1891}
1892
1893/**
1894 * amdgpu_vm_prt_cb - callback for updating the PRT status
1895 *
1896 * @fence: fence for the callback
1897 * @_cb: the callback function
1898 */
1899static void amdgpu_vm_prt_cb(struct dma_fence *fence, struct dma_fence_cb *_cb)
1900{
1901 struct amdgpu_prt_cb *cb = container_of(_cb, struct amdgpu_prt_cb, cb);
1902
1903 amdgpu_vm_prt_put(cb->adev);
1904 kfree(cb);
1905}
1906
1907/**
1908 * amdgpu_vm_add_prt_cb - add callback for updating the PRT status
1909 *
1910 * @adev: amdgpu_device pointer
1911 * @fence: fence for the callback
1912 */
1913static void amdgpu_vm_add_prt_cb(struct amdgpu_device *adev,
1914 struct dma_fence *fence)
1915{
1916 struct amdgpu_prt_cb *cb;
1917
1918 if (!adev->gmc.gmc_funcs->set_prt)
1919 return;
1920
1921 cb = kmalloc(sizeof(struct amdgpu_prt_cb), GFP_KERNEL);
1922 if (!cb) {
1923 /* Last resort when we are OOM */
1924 if (fence)
1925 dma_fence_wait(fence, false);
1926
1927 amdgpu_vm_prt_put(adev);
1928 } else {
1929 cb->adev = adev;
1930 if (!fence || dma_fence_add_callback(fence, &cb->cb,
1931 amdgpu_vm_prt_cb))
1932 amdgpu_vm_prt_cb(fence, &cb->cb);
1933 }
1934}
1935
1936/**
1937 * amdgpu_vm_free_mapping - free a mapping
1938 *
1939 * @adev: amdgpu_device pointer
1940 * @vm: requested vm
1941 * @mapping: mapping to be freed
1942 * @fence: fence of the unmap operation
1943 *
1944 * Free a mapping and make sure we decrease the PRT usage count if applicable.
1945 */
1946static void amdgpu_vm_free_mapping(struct amdgpu_device *adev,
1947 struct amdgpu_vm *vm,
1948 struct amdgpu_bo_va_mapping *mapping,
1949 struct dma_fence *fence)
1950{
1951 if (mapping->flags & AMDGPU_PTE_PRT)
1952 amdgpu_vm_add_prt_cb(adev, fence);
1953 kfree(mapping);
1954}
1955
1956/**
1957 * amdgpu_vm_prt_fini - finish all prt mappings
1958 *
1959 * @adev: amdgpu_device pointer
1960 * @vm: requested vm
1961 *
1962 * Register a cleanup callback to disable PRT support after VM dies.
1963 */
1964static void amdgpu_vm_prt_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm)
1965{
1966 struct dma_resv *resv = vm->root.base.bo->tbo.base.resv;
1967 struct dma_fence *excl, **shared;
1968 unsigned i, shared_count;
1969 int r;
1970
1971 r = dma_resv_get_fences_rcu(resv, &excl,
1972 &shared_count, &shared);
1973 if (r) {
1974 /* Not enough memory to grab the fence list, as last resort
1975 * block for all the fences to complete.
1976 */
1977 dma_resv_wait_timeout_rcu(resv, true, false,
1978 MAX_SCHEDULE_TIMEOUT);
1979 return;
1980 }
1981
1982 /* Add a callback for each fence in the reservation object */
1983 amdgpu_vm_prt_get(adev);
1984 amdgpu_vm_add_prt_cb(adev, excl);
1985
1986 for (i = 0; i < shared_count; ++i) {
1987 amdgpu_vm_prt_get(adev);
1988 amdgpu_vm_add_prt_cb(adev, shared[i]);
1989 }
1990
1991 kfree(shared);
1992}
1993
1994/**
1995 * amdgpu_vm_clear_freed - clear freed BOs in the PT
1996 *
1997 * @adev: amdgpu_device pointer
1998 * @vm: requested vm
1999 * @fence: optional resulting fence (unchanged if no work needed to be done
2000 * or if an error occurred)
2001 *
2002 * Make sure all freed BOs are cleared in the PT.
2003 * PTs have to be reserved and mutex must be locked!
2004 *
2005 * Returns:
2006 * 0 for success.
2007 *
2008 */
2009int amdgpu_vm_clear_freed(struct amdgpu_device *adev,
2010 struct amdgpu_vm *vm,
2011 struct dma_fence **fence)
2012{
2013 struct dma_resv *resv = vm->root.base.bo->tbo.base.resv;
2014 struct amdgpu_bo_va_mapping *mapping;
2015 uint64_t init_pte_value = 0;
2016 struct dma_fence *f = NULL;
2017 int r;
2018
2019 while (!list_empty(&vm->freed)) {
2020 mapping = list_first_entry(&vm->freed,
2021 struct amdgpu_bo_va_mapping, list);
2022 list_del(&mapping->list);
2023
2024 if (vm->pte_support_ats &&
2025 mapping->start < AMDGPU_GMC_HOLE_START)
2026 init_pte_value = AMDGPU_PTE_DEFAULT_ATC;
2027
2028 r = amdgpu_vm_bo_update_mapping(adev, vm, false, false, resv,
2029 mapping->start, mapping->last,
2030 init_pte_value, 0, NULL, &f);
2031 amdgpu_vm_free_mapping(adev, vm, mapping, f);
2032 if (r) {
2033 dma_fence_put(f);
2034 return r;
2035 }
2036 }
2037
2038 if (fence && f) {
2039 dma_fence_put(*fence);
2040 *fence = f;
2041 } else {
2042 dma_fence_put(f);
2043 }
2044
2045 return 0;
2046
2047}
2048
2049/**
2050 * amdgpu_vm_handle_moved - handle moved BOs in the PT
2051 *
2052 * @adev: amdgpu_device pointer
2053 * @vm: requested vm
2054 *
2055 * Make sure all BOs which are moved are updated in the PTs.
2056 *
2057 * Returns:
2058 * 0 for success.
2059 *
2060 * PTs have to be reserved!
2061 */
2062int amdgpu_vm_handle_moved(struct amdgpu_device *adev,
2063 struct amdgpu_vm *vm)
2064{
2065 struct amdgpu_bo_va *bo_va, *tmp;
2066 struct dma_resv *resv;
2067 bool clear;
2068 int r;
2069
2070 list_for_each_entry_safe(bo_va, tmp, &vm->moved, base.vm_status) {
2071 /* Per VM BOs never need to bo cleared in the page tables */
2072 r = amdgpu_vm_bo_update(adev, bo_va, false);
2073 if (r)
2074 return r;
2075 }
2076
2077 spin_lock(&vm->invalidated_lock);
2078 while (!list_empty(&vm->invalidated)) {
2079 bo_va = list_first_entry(&vm->invalidated, struct amdgpu_bo_va,
2080 base.vm_status);
2081 resv = bo_va->base.bo->tbo.base.resv;
2082 spin_unlock(&vm->invalidated_lock);
2083
2084 /* Try to reserve the BO to avoid clearing its ptes */
2085 if (!amdgpu_vm_debug && dma_resv_trylock(resv))
2086 clear = false;
2087 /* Somebody else is using the BO right now */
2088 else
2089 clear = true;
2090
2091 r = amdgpu_vm_bo_update(adev, bo_va, clear);
2092 if (r)
2093 return r;
2094
2095 if (!clear)
2096 dma_resv_unlock(resv);
2097 spin_lock(&vm->invalidated_lock);
2098 }
2099 spin_unlock(&vm->invalidated_lock);
2100
2101 return 0;
2102}
2103
2104/**
2105 * amdgpu_vm_bo_add - add a bo to a specific vm
2106 *
2107 * @adev: amdgpu_device pointer
2108 * @vm: requested vm
2109 * @bo: amdgpu buffer object
2110 *
2111 * Add @bo into the requested vm.
2112 * Add @bo to the list of bos associated with the vm
2113 *
2114 * Returns:
2115 * Newly added bo_va or NULL for failure
2116 *
2117 * Object has to be reserved!
2118 */
2119struct amdgpu_bo_va *amdgpu_vm_bo_add(struct amdgpu_device *adev,
2120 struct amdgpu_vm *vm,
2121 struct amdgpu_bo *bo)
2122{
2123 struct amdgpu_bo_va *bo_va;
2124
2125 bo_va = kzalloc(sizeof(struct amdgpu_bo_va), GFP_KERNEL);
2126 if (bo_va == NULL) {
2127 return NULL;
2128 }
2129 amdgpu_vm_bo_base_init(&bo_va->base, vm, bo);
2130
2131 bo_va->ref_count = 1;
2132 INIT_LIST_HEAD(&bo_va->valids);
2133 INIT_LIST_HEAD(&bo_va->invalids);
2134
2135 if (bo && amdgpu_xgmi_same_hive(adev, amdgpu_ttm_adev(bo->tbo.bdev)) &&
2136 (bo->preferred_domains & AMDGPU_GEM_DOMAIN_VRAM)) {
2137 bo_va->is_xgmi = true;
2138 /* Power up XGMI if it can be potentially used */
2139 amdgpu_xgmi_set_pstate(adev, AMDGPU_XGMI_PSTATE_MAX_VEGA20);
2140 }
2141
2142 return bo_va;
2143}
2144
2145
2146/**
2147 * amdgpu_vm_bo_insert_mapping - insert a new mapping
2148 *
2149 * @adev: amdgpu_device pointer
2150 * @bo_va: bo_va to store the address
2151 * @mapping: the mapping to insert
2152 *
2153 * Insert a new mapping into all structures.
2154 */
2155static void amdgpu_vm_bo_insert_map(struct amdgpu_device *adev,
2156 struct amdgpu_bo_va *bo_va,
2157 struct amdgpu_bo_va_mapping *mapping)
2158{
2159 struct amdgpu_vm *vm = bo_va->base.vm;
2160 struct amdgpu_bo *bo = bo_va->base.bo;
2161
2162 mapping->bo_va = bo_va;
2163 list_add(&mapping->list, &bo_va->invalids);
2164 amdgpu_vm_it_insert(mapping, &vm->va);
2165
2166 if (mapping->flags & AMDGPU_PTE_PRT)
2167 amdgpu_vm_prt_get(adev);
2168
2169 if (bo && bo->tbo.base.resv == vm->root.base.bo->tbo.base.resv &&
2170 !bo_va->base.moved) {
2171 list_move(&bo_va->base.vm_status, &vm->moved);
2172 }
2173 trace_amdgpu_vm_bo_map(bo_va, mapping);
2174}
2175
2176/**
2177 * amdgpu_vm_bo_map - map bo inside a vm
2178 *
2179 * @adev: amdgpu_device pointer
2180 * @bo_va: bo_va to store the address
2181 * @saddr: where to map the BO
2182 * @offset: requested offset in the BO
2183 * @size: BO size in bytes
2184 * @flags: attributes of pages (read/write/valid/etc.)
2185 *
2186 * Add a mapping of the BO at the specefied addr into the VM.
2187 *
2188 * Returns:
2189 * 0 for success, error for failure.
2190 *
2191 * Object has to be reserved and unreserved outside!
2192 */
2193int amdgpu_vm_bo_map(struct amdgpu_device *adev,
2194 struct amdgpu_bo_va *bo_va,
2195 uint64_t saddr, uint64_t offset,
2196 uint64_t size, uint64_t flags)
2197{
2198 struct amdgpu_bo_va_mapping *mapping, *tmp;
2199 struct amdgpu_bo *bo = bo_va->base.bo;
2200 struct amdgpu_vm *vm = bo_va->base.vm;
2201 uint64_t eaddr;
2202
2203 /* validate the parameters */
2204 if (saddr & AMDGPU_GPU_PAGE_MASK || offset & AMDGPU_GPU_PAGE_MASK ||
2205 size == 0 || size & AMDGPU_GPU_PAGE_MASK)
2206 return -EINVAL;
2207
2208 /* make sure object fit at this offset */
2209 eaddr = saddr + size - 1;
2210 if (saddr >= eaddr ||
2211 (bo && offset + size > amdgpu_bo_size(bo)) ||
2212 (eaddr >= adev->vm_manager.max_pfn << AMDGPU_GPU_PAGE_SHIFT))
2213 return -EINVAL;
2214
2215 saddr /= AMDGPU_GPU_PAGE_SIZE;
2216 eaddr /= AMDGPU_GPU_PAGE_SIZE;
2217
2218 tmp = amdgpu_vm_it_iter_first(&vm->va, saddr, eaddr);
2219 if (tmp) {
2220 /* bo and tmp overlap, invalid addr */
2221 dev_err(adev->dev, "bo %p va 0x%010Lx-0x%010Lx conflict with "
2222 "0x%010Lx-0x%010Lx\n", bo, saddr, eaddr,
2223 tmp->start, tmp->last + 1);
2224 return -EINVAL;
2225 }
2226
2227 mapping = kmalloc(sizeof(*mapping), GFP_KERNEL);
2228 if (!mapping)
2229 return -ENOMEM;
2230
2231 mapping->start = saddr;
2232 mapping->last = eaddr;
2233 mapping->offset = offset;
2234 mapping->flags = flags;
2235
2236 amdgpu_vm_bo_insert_map(adev, bo_va, mapping);
2237
2238 return 0;
2239}
2240
2241/**
2242 * amdgpu_vm_bo_replace_map - map bo inside a vm, replacing existing mappings
2243 *
2244 * @adev: amdgpu_device pointer
2245 * @bo_va: bo_va to store the address
2246 * @saddr: where to map the BO
2247 * @offset: requested offset in the BO
2248 * @size: BO size in bytes
2249 * @flags: attributes of pages (read/write/valid/etc.)
2250 *
2251 * Add a mapping of the BO at the specefied addr into the VM. Replace existing
2252 * mappings as we do so.
2253 *
2254 * Returns:
2255 * 0 for success, error for failure.
2256 *
2257 * Object has to be reserved and unreserved outside!
2258 */
2259int amdgpu_vm_bo_replace_map(struct amdgpu_device *adev,
2260 struct amdgpu_bo_va *bo_va,
2261 uint64_t saddr, uint64_t offset,
2262 uint64_t size, uint64_t flags)
2263{
2264 struct amdgpu_bo_va_mapping *mapping;
2265 struct amdgpu_bo *bo = bo_va->base.bo;
2266 uint64_t eaddr;
2267 int r;
2268
2269 /* validate the parameters */
2270 if (saddr & AMDGPU_GPU_PAGE_MASK || offset & AMDGPU_GPU_PAGE_MASK ||
2271 size == 0 || size & AMDGPU_GPU_PAGE_MASK)
2272 return -EINVAL;
2273
2274 /* make sure object fit at this offset */
2275 eaddr = saddr + size - 1;
2276 if (saddr >= eaddr ||
2277 (bo && offset + size > amdgpu_bo_size(bo)) ||
2278 (eaddr >= adev->vm_manager.max_pfn << AMDGPU_GPU_PAGE_SHIFT))
2279 return -EINVAL;
2280
2281 /* Allocate all the needed memory */
2282 mapping = kmalloc(sizeof(*mapping), GFP_KERNEL);
2283 if (!mapping)
2284 return -ENOMEM;
2285
2286 r = amdgpu_vm_bo_clear_mappings(adev, bo_va->base.vm, saddr, size);
2287 if (r) {
2288 kfree(mapping);
2289 return r;
2290 }
2291
2292 saddr /= AMDGPU_GPU_PAGE_SIZE;
2293 eaddr /= AMDGPU_GPU_PAGE_SIZE;
2294
2295 mapping->start = saddr;
2296 mapping->last = eaddr;
2297 mapping->offset = offset;
2298 mapping->flags = flags;
2299
2300 amdgpu_vm_bo_insert_map(adev, bo_va, mapping);
2301
2302 return 0;
2303}
2304
2305/**
2306 * amdgpu_vm_bo_unmap - remove bo mapping from vm
2307 *
2308 * @adev: amdgpu_device pointer
2309 * @bo_va: bo_va to remove the address from
2310 * @saddr: where to the BO is mapped
2311 *
2312 * Remove a mapping of the BO at the specefied addr from the VM.
2313 *
2314 * Returns:
2315 * 0 for success, error for failure.
2316 *
2317 * Object has to be reserved and unreserved outside!
2318 */
2319int amdgpu_vm_bo_unmap(struct amdgpu_device *adev,
2320 struct amdgpu_bo_va *bo_va,
2321 uint64_t saddr)
2322{
2323 struct amdgpu_bo_va_mapping *mapping;
2324 struct amdgpu_vm *vm = bo_va->base.vm;
2325 bool valid = true;
2326
2327 saddr /= AMDGPU_GPU_PAGE_SIZE;
2328
2329 list_for_each_entry(mapping, &bo_va->valids, list) {
2330 if (mapping->start == saddr)
2331 break;
2332 }
2333
2334 if (&mapping->list == &bo_va->valids) {
2335 valid = false;
2336
2337 list_for_each_entry(mapping, &bo_va->invalids, list) {
2338 if (mapping->start == saddr)
2339 break;
2340 }
2341
2342 if (&mapping->list == &bo_va->invalids)
2343 return -ENOENT;
2344 }
2345
2346 list_del(&mapping->list);
2347 amdgpu_vm_it_remove(mapping, &vm->va);
2348 mapping->bo_va = NULL;
2349 trace_amdgpu_vm_bo_unmap(bo_va, mapping);
2350
2351 if (valid)
2352 list_add(&mapping->list, &vm->freed);
2353 else
2354 amdgpu_vm_free_mapping(adev, vm, mapping,
2355 bo_va->last_pt_update);
2356
2357 return 0;
2358}
2359
2360/**
2361 * amdgpu_vm_bo_clear_mappings - remove all mappings in a specific range
2362 *
2363 * @adev: amdgpu_device pointer
2364 * @vm: VM structure to use
2365 * @saddr: start of the range
2366 * @size: size of the range
2367 *
2368 * Remove all mappings in a range, split them as appropriate.
2369 *
2370 * Returns:
2371 * 0 for success, error for failure.
2372 */
2373int amdgpu_vm_bo_clear_mappings(struct amdgpu_device *adev,
2374 struct amdgpu_vm *vm,
2375 uint64_t saddr, uint64_t size)
2376{
2377 struct amdgpu_bo_va_mapping *before, *after, *tmp, *next;
2378 LIST_HEAD(removed);
2379 uint64_t eaddr;
2380
2381 eaddr = saddr + size - 1;
2382 saddr /= AMDGPU_GPU_PAGE_SIZE;
2383 eaddr /= AMDGPU_GPU_PAGE_SIZE;
2384
2385 /* Allocate all the needed memory */
2386 before = kzalloc(sizeof(*before), GFP_KERNEL);
2387 if (!before)
2388 return -ENOMEM;
2389 INIT_LIST_HEAD(&before->list);
2390
2391 after = kzalloc(sizeof(*after), GFP_KERNEL);
2392 if (!after) {
2393 kfree(before);
2394 return -ENOMEM;
2395 }
2396 INIT_LIST_HEAD(&after->list);
2397
2398 /* Now gather all removed mappings */
2399 tmp = amdgpu_vm_it_iter_first(&vm->va, saddr, eaddr);
2400 while (tmp) {
2401 /* Remember mapping split at the start */
2402 if (tmp->start < saddr) {
2403 before->start = tmp->start;
2404 before->last = saddr - 1;
2405 before->offset = tmp->offset;
2406 before->flags = tmp->flags;
2407 before->bo_va = tmp->bo_va;
2408 list_add(&before->list, &tmp->bo_va->invalids);
2409 }
2410
2411 /* Remember mapping split at the end */
2412 if (tmp->last > eaddr) {
2413 after->start = eaddr + 1;
2414 after->last = tmp->last;
2415 after->offset = tmp->offset;
2416 after->offset += after->start - tmp->start;
2417 after->flags = tmp->flags;
2418 after->bo_va = tmp->bo_va;
2419 list_add(&after->list, &tmp->bo_va->invalids);
2420 }
2421
2422 list_del(&tmp->list);
2423 list_add(&tmp->list, &removed);
2424
2425 tmp = amdgpu_vm_it_iter_next(tmp, saddr, eaddr);
2426 }
2427
2428 /* And free them up */
2429 list_for_each_entry_safe(tmp, next, &removed, list) {
2430 amdgpu_vm_it_remove(tmp, &vm->va);
2431 list_del(&tmp->list);
2432
2433 if (tmp->start < saddr)
2434 tmp->start = saddr;
2435 if (tmp->last > eaddr)
2436 tmp->last = eaddr;
2437
2438 tmp->bo_va = NULL;
2439 list_add(&tmp->list, &vm->freed);
2440 trace_amdgpu_vm_bo_unmap(NULL, tmp);
2441 }
2442
2443 /* Insert partial mapping before the range */
2444 if (!list_empty(&before->list)) {
2445 amdgpu_vm_it_insert(before, &vm->va);
2446 if (before->flags & AMDGPU_PTE_PRT)
2447 amdgpu_vm_prt_get(adev);
2448 } else {
2449 kfree(before);
2450 }
2451
2452 /* Insert partial mapping after the range */
2453 if (!list_empty(&after->list)) {
2454 amdgpu_vm_it_insert(after, &vm->va);
2455 if (after->flags & AMDGPU_PTE_PRT)
2456 amdgpu_vm_prt_get(adev);
2457 } else {
2458 kfree(after);
2459 }
2460
2461 return 0;
2462}
2463
2464/**
2465 * amdgpu_vm_bo_lookup_mapping - find mapping by address
2466 *
2467 * @vm: the requested VM
2468 * @addr: the address
2469 *
2470 * Find a mapping by it's address.
2471 *
2472 * Returns:
2473 * The amdgpu_bo_va_mapping matching for addr or NULL
2474 *
2475 */
2476struct amdgpu_bo_va_mapping *amdgpu_vm_bo_lookup_mapping(struct amdgpu_vm *vm,
2477 uint64_t addr)
2478{
2479 return amdgpu_vm_it_iter_first(&vm->va, addr, addr);
2480}
2481
2482/**
2483 * amdgpu_vm_bo_trace_cs - trace all reserved mappings
2484 *
2485 * @vm: the requested vm
2486 * @ticket: CS ticket
2487 *
2488 * Trace all mappings of BOs reserved during a command submission.
2489 */
2490void amdgpu_vm_bo_trace_cs(struct amdgpu_vm *vm, struct ww_acquire_ctx *ticket)
2491{
2492 struct amdgpu_bo_va_mapping *mapping;
2493
2494 if (!trace_amdgpu_vm_bo_cs_enabled())
2495 return;
2496
2497 for (mapping = amdgpu_vm_it_iter_first(&vm->va, 0, U64_MAX); mapping;
2498 mapping = amdgpu_vm_it_iter_next(mapping, 0, U64_MAX)) {
2499 if (mapping->bo_va && mapping->bo_va->base.bo) {
2500 struct amdgpu_bo *bo;
2501
2502 bo = mapping->bo_va->base.bo;
2503 if (dma_resv_locking_ctx(bo->tbo.base.resv) !=
2504 ticket)
2505 continue;
2506 }
2507
2508 trace_amdgpu_vm_bo_cs(mapping);
2509 }
2510}
2511
2512/**
2513 * amdgpu_vm_bo_rmv - remove a bo to a specific vm
2514 *
2515 * @adev: amdgpu_device pointer
2516 * @bo_va: requested bo_va
2517 *
2518 * Remove @bo_va->bo from the requested vm.
2519 *
2520 * Object have to be reserved!
2521 */
2522void amdgpu_vm_bo_rmv(struct amdgpu_device *adev,
2523 struct amdgpu_bo_va *bo_va)
2524{
2525 struct amdgpu_bo_va_mapping *mapping, *next;
2526 struct amdgpu_bo *bo = bo_va->base.bo;
2527 struct amdgpu_vm *vm = bo_va->base.vm;
2528 struct amdgpu_vm_bo_base **base;
2529
2530 if (bo) {
2531 if (bo->tbo.base.resv == vm->root.base.bo->tbo.base.resv)
2532 vm->bulk_moveable = false;
2533
2534 for (base = &bo_va->base.bo->vm_bo; *base;
2535 base = &(*base)->next) {
2536 if (*base != &bo_va->base)
2537 continue;
2538
2539 *base = bo_va->base.next;
2540 break;
2541 }
2542 }
2543
2544 spin_lock(&vm->invalidated_lock);
2545 list_del(&bo_va->base.vm_status);
2546 spin_unlock(&vm->invalidated_lock);
2547
2548 list_for_each_entry_safe(mapping, next, &bo_va->valids, list) {
2549 list_del(&mapping->list);
2550 amdgpu_vm_it_remove(mapping, &vm->va);
2551 mapping->bo_va = NULL;
2552 trace_amdgpu_vm_bo_unmap(bo_va, mapping);
2553 list_add(&mapping->list, &vm->freed);
2554 }
2555 list_for_each_entry_safe(mapping, next, &bo_va->invalids, list) {
2556 list_del(&mapping->list);
2557 amdgpu_vm_it_remove(mapping, &vm->va);
2558 amdgpu_vm_free_mapping(adev, vm, mapping,
2559 bo_va->last_pt_update);
2560 }
2561
2562 dma_fence_put(bo_va->last_pt_update);
2563
2564 if (bo && bo_va->is_xgmi)
2565 amdgpu_xgmi_set_pstate(adev, AMDGPU_XGMI_PSTATE_MIN);
2566
2567 kfree(bo_va);
2568}
2569
2570/**
2571 * amdgpu_vm_evictable - check if we can evict a VM
2572 *
2573 * @bo: A page table of the VM.
2574 *
2575 * Check if it is possible to evict a VM.
2576 */
2577bool amdgpu_vm_evictable(struct amdgpu_bo *bo)
2578{
2579 struct amdgpu_vm_bo_base *bo_base = bo->vm_bo;
2580
2581 /* Page tables of a destroyed VM can go away immediately */
2582 if (!bo_base || !bo_base->vm)
2583 return true;
2584
2585 /* Don't evict VM page tables while they are busy */
2586 if (!dma_resv_test_signaled_rcu(bo->tbo.base.resv, true))
2587 return false;
2588
2589 /* Try to block ongoing updates */
2590 if (!amdgpu_vm_eviction_trylock(bo_base->vm))
2591 return false;
2592
2593 /* Don't evict VM page tables while they are updated */
2594 if (!dma_fence_is_signaled(bo_base->vm->last_unlocked)) {
2595 amdgpu_vm_eviction_unlock(bo_base->vm);
2596 return false;
2597 }
2598
2599 bo_base->vm->evicting = true;
2600 amdgpu_vm_eviction_unlock(bo_base->vm);
2601 return true;
2602}
2603
2604/**
2605 * amdgpu_vm_bo_invalidate - mark the bo as invalid
2606 *
2607 * @adev: amdgpu_device pointer
2608 * @bo: amdgpu buffer object
2609 * @evicted: is the BO evicted
2610 *
2611 * Mark @bo as invalid.
2612 */
2613void amdgpu_vm_bo_invalidate(struct amdgpu_device *adev,
2614 struct amdgpu_bo *bo, bool evicted)
2615{
2616 struct amdgpu_vm_bo_base *bo_base;
2617
2618 /* shadow bo doesn't have bo base, its validation needs its parent */
2619 if (bo->parent && bo->parent->shadow == bo)
2620 bo = bo->parent;
2621
2622 for (bo_base = bo->vm_bo; bo_base; bo_base = bo_base->next) {
2623 struct amdgpu_vm *vm = bo_base->vm;
2624
2625 if (evicted && bo->tbo.base.resv == vm->root.base.bo->tbo.base.resv) {
2626 amdgpu_vm_bo_evicted(bo_base);
2627 continue;
2628 }
2629
2630 if (bo_base->moved)
2631 continue;
2632 bo_base->moved = true;
2633
2634 if (bo->tbo.type == ttm_bo_type_kernel)
2635 amdgpu_vm_bo_relocated(bo_base);
2636 else if (bo->tbo.base.resv == vm->root.base.bo->tbo.base.resv)
2637 amdgpu_vm_bo_moved(bo_base);
2638 else
2639 amdgpu_vm_bo_invalidated(bo_base);
2640 }
2641}
2642
2643/**
2644 * amdgpu_vm_get_block_size - calculate VM page table size as power of two
2645 *
2646 * @vm_size: VM size
2647 *
2648 * Returns:
2649 * VM page table as power of two
2650 */
2651static uint32_t amdgpu_vm_get_block_size(uint64_t vm_size)
2652{
2653 /* Total bits covered by PD + PTs */
2654 unsigned bits = ilog2(vm_size) + 18;
2655
2656 /* Make sure the PD is 4K in size up to 8GB address space.
2657 Above that split equal between PD and PTs */
2658 if (vm_size <= 8)
2659 return (bits - 9);
2660 else
2661 return ((bits + 3) / 2);
2662}
2663
2664/**
2665 * amdgpu_vm_adjust_size - adjust vm size, block size and fragment size
2666 *
2667 * @adev: amdgpu_device pointer
2668 * @min_vm_size: the minimum vm size in GB if it's set auto
2669 * @fragment_size_default: Default PTE fragment size
2670 * @max_level: max VMPT level
2671 * @max_bits: max address space size in bits
2672 *
2673 */
2674void amdgpu_vm_adjust_size(struct amdgpu_device *adev, uint32_t min_vm_size,
2675 uint32_t fragment_size_default, unsigned max_level,
2676 unsigned max_bits)
2677{
2678 unsigned int max_size = 1 << (max_bits - 30);
2679 unsigned int vm_size;
2680 uint64_t tmp;
2681
2682 /* adjust vm size first */
2683 if (amdgpu_vm_size != -1) {
2684 vm_size = amdgpu_vm_size;
2685 if (vm_size > max_size) {
2686 dev_warn(adev->dev, "VM size (%d) too large, max is %u GB\n",
2687 amdgpu_vm_size, max_size);
2688 vm_size = max_size;
2689 }
2690 } else {
2691 struct sysinfo si;
2692 unsigned int phys_ram_gb;
2693
2694 /* Optimal VM size depends on the amount of physical
2695 * RAM available. Underlying requirements and
2696 * assumptions:
2697 *
2698 * - Need to map system memory and VRAM from all GPUs
2699 * - VRAM from other GPUs not known here
2700 * - Assume VRAM <= system memory
2701 * - On GFX8 and older, VM space can be segmented for
2702 * different MTYPEs
2703 * - Need to allow room for fragmentation, guard pages etc.
2704 *
2705 * This adds up to a rough guess of system memory x3.
2706 * Round up to power of two to maximize the available
2707 * VM size with the given page table size.
2708 */
2709 si_meminfo(&si);
2710 phys_ram_gb = ((uint64_t)si.totalram * si.mem_unit +
2711 (1 << 30) - 1) >> 30;
2712 vm_size = roundup_pow_of_two(
2713 min(max(phys_ram_gb * 3, min_vm_size), max_size));
2714 }
2715
2716 adev->vm_manager.max_pfn = (uint64_t)vm_size << 18;
2717
2718 tmp = roundup_pow_of_two(adev->vm_manager.max_pfn);
2719 if (amdgpu_vm_block_size != -1)
2720 tmp >>= amdgpu_vm_block_size - 9;
2721 tmp = DIV_ROUND_UP(fls64(tmp) - 1, 9) - 1;
2722 adev->vm_manager.num_level = min(max_level, (unsigned)tmp);
2723 switch (adev->vm_manager.num_level) {
2724 case 3:
2725 adev->vm_manager.root_level = AMDGPU_VM_PDB2;
2726 break;
2727 case 2:
2728 adev->vm_manager.root_level = AMDGPU_VM_PDB1;
2729 break;
2730 case 1:
2731 adev->vm_manager.root_level = AMDGPU_VM_PDB0;
2732 break;
2733 default:
2734 dev_err(adev->dev, "VMPT only supports 2~4+1 levels\n");
2735 }
2736 /* block size depends on vm size and hw setup*/
2737 if (amdgpu_vm_block_size != -1)
2738 adev->vm_manager.block_size =
2739 min((unsigned)amdgpu_vm_block_size, max_bits
2740 - AMDGPU_GPU_PAGE_SHIFT
2741 - 9 * adev->vm_manager.num_level);
2742 else if (adev->vm_manager.num_level > 1)
2743 adev->vm_manager.block_size = 9;
2744 else
2745 adev->vm_manager.block_size = amdgpu_vm_get_block_size(tmp);
2746
2747 if (amdgpu_vm_fragment_size == -1)
2748 adev->vm_manager.fragment_size = fragment_size_default;
2749 else
2750 adev->vm_manager.fragment_size = amdgpu_vm_fragment_size;
2751
2752 DRM_INFO("vm size is %u GB, %u levels, block size is %u-bit, fragment size is %u-bit\n",
2753 vm_size, adev->vm_manager.num_level + 1,
2754 adev->vm_manager.block_size,
2755 adev->vm_manager.fragment_size);
2756}
2757
2758/**
2759 * amdgpu_vm_wait_idle - wait for the VM to become idle
2760 *
2761 * @vm: VM object to wait for
2762 * @timeout: timeout to wait for VM to become idle
2763 */
2764long amdgpu_vm_wait_idle(struct amdgpu_vm *vm, long timeout)
2765{
2766 timeout = dma_resv_wait_timeout_rcu(vm->root.base.bo->tbo.base.resv,
2767 true, true, timeout);
2768 if (timeout <= 0)
2769 return timeout;
2770
2771 return dma_fence_wait_timeout(vm->last_unlocked, true, timeout);
2772}
2773
2774/**
2775 * amdgpu_vm_init - initialize a vm instance
2776 *
2777 * @adev: amdgpu_device pointer
2778 * @vm: requested vm
2779 * @vm_context: Indicates if it GFX or Compute context
2780 * @pasid: Process address space identifier
2781 *
2782 * Init @vm fields.
2783 *
2784 * Returns:
2785 * 0 for success, error for failure.
2786 */
2787int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm,
2788 int vm_context, unsigned int pasid)
2789{
2790 struct amdgpu_bo_param bp;
2791 struct amdgpu_bo *root;
2792 int r, i;
2793
2794 vm->va = RB_ROOT_CACHED;
2795 for (i = 0; i < AMDGPU_MAX_VMHUBS; i++)
2796 vm->reserved_vmid[i] = NULL;
2797 INIT_LIST_HEAD(&vm->evicted);
2798 INIT_LIST_HEAD(&vm->relocated);
2799 INIT_LIST_HEAD(&vm->moved);
2800 INIT_LIST_HEAD(&vm->idle);
2801 INIT_LIST_HEAD(&vm->invalidated);
2802 spin_lock_init(&vm->invalidated_lock);
2803 INIT_LIST_HEAD(&vm->freed);
2804
2805
2806 /* create scheduler entities for page table updates */
2807 r = drm_sched_entity_init(&vm->immediate, DRM_SCHED_PRIORITY_NORMAL,
2808 adev->vm_manager.vm_pte_scheds,
2809 adev->vm_manager.vm_pte_num_scheds, NULL);
2810 if (r)
2811 return r;
2812
2813 r = drm_sched_entity_init(&vm->delayed, DRM_SCHED_PRIORITY_NORMAL,
2814 adev->vm_manager.vm_pte_scheds,
2815 adev->vm_manager.vm_pte_num_scheds, NULL);
2816 if (r)
2817 goto error_free_immediate;
2818
2819 vm->pte_support_ats = false;
2820 vm->is_compute_context = false;
2821
2822 if (vm_context == AMDGPU_VM_CONTEXT_COMPUTE) {
2823 vm->use_cpu_for_update = !!(adev->vm_manager.vm_update_mode &
2824 AMDGPU_VM_USE_CPU_FOR_COMPUTE);
2825
2826 if (adev->asic_type == CHIP_RAVEN)
2827 vm->pte_support_ats = true;
2828 } else {
2829 vm->use_cpu_for_update = !!(adev->vm_manager.vm_update_mode &
2830 AMDGPU_VM_USE_CPU_FOR_GFX);
2831 }
2832 DRM_DEBUG_DRIVER("VM update mode is %s\n",
2833 vm->use_cpu_for_update ? "CPU" : "SDMA");
2834 WARN_ONCE((vm->use_cpu_for_update &&
2835 !amdgpu_gmc_vram_full_visible(&adev->gmc)),
2836 "CPU update of VM recommended only for large BAR system\n");
2837
2838 if (vm->use_cpu_for_update)
2839 vm->update_funcs = &amdgpu_vm_cpu_funcs;
2840 else
2841 vm->update_funcs = &amdgpu_vm_sdma_funcs;
2842 vm->last_update = NULL;
2843 vm->last_unlocked = dma_fence_get_stub();
2844
2845 mutex_init(&vm->eviction_lock);
2846 vm->evicting = false;
2847
2848 amdgpu_vm_bo_param(adev, vm, adev->vm_manager.root_level, false, &bp);
2849 if (vm_context == AMDGPU_VM_CONTEXT_COMPUTE)
2850 bp.flags &= ~AMDGPU_GEM_CREATE_SHADOW;
2851 r = amdgpu_bo_create(adev, &bp, &root);
2852 if (r)
2853 goto error_free_delayed;
2854
2855 r = amdgpu_bo_reserve(root, true);
2856 if (r)
2857 goto error_free_root;
2858
2859 r = dma_resv_reserve_shared(root->tbo.base.resv, 1);
2860 if (r)
2861 goto error_unreserve;
2862
2863 amdgpu_vm_bo_base_init(&vm->root.base, vm, root);
2864
2865 r = amdgpu_vm_clear_bo(adev, vm, root, false);
2866 if (r)
2867 goto error_unreserve;
2868
2869 amdgpu_bo_unreserve(vm->root.base.bo);
2870
2871 if (pasid) {
2872 unsigned long flags;
2873
2874 spin_lock_irqsave(&adev->vm_manager.pasid_lock, flags);
2875 r = idr_alloc(&adev->vm_manager.pasid_idr, vm, pasid, pasid + 1,
2876 GFP_ATOMIC);
2877 spin_unlock_irqrestore(&adev->vm_manager.pasid_lock, flags);
2878 if (r < 0)
2879 goto error_free_root;
2880
2881 vm->pasid = pasid;
2882 }
2883
2884 INIT_KFIFO(vm->faults);
2885
2886 return 0;
2887
2888error_unreserve:
2889 amdgpu_bo_unreserve(vm->root.base.bo);
2890
2891error_free_root:
2892 amdgpu_bo_unref(&vm->root.base.bo->shadow);
2893 amdgpu_bo_unref(&vm->root.base.bo);
2894 vm->root.base.bo = NULL;
2895
2896error_free_delayed:
2897 dma_fence_put(vm->last_unlocked);
2898 drm_sched_entity_destroy(&vm->delayed);
2899
2900error_free_immediate:
2901 drm_sched_entity_destroy(&vm->immediate);
2902
2903 return r;
2904}
2905
2906/**
2907 * amdgpu_vm_check_clean_reserved - check if a VM is clean
2908 *
2909 * @adev: amdgpu_device pointer
2910 * @vm: the VM to check
2911 *
2912 * check all entries of the root PD, if any subsequent PDs are allocated,
2913 * it means there are page table creating and filling, and is no a clean
2914 * VM
2915 *
2916 * Returns:
2917 * 0 if this VM is clean
2918 */
2919static int amdgpu_vm_check_clean_reserved(struct amdgpu_device *adev,
2920 struct amdgpu_vm *vm)
2921{
2922 enum amdgpu_vm_level root = adev->vm_manager.root_level;
2923 unsigned int entries = amdgpu_vm_num_entries(adev, root);
2924 unsigned int i = 0;
2925
2926 if (!(vm->root.entries))
2927 return 0;
2928
2929 for (i = 0; i < entries; i++) {
2930 if (vm->root.entries[i].base.bo)
2931 return -EINVAL;
2932 }
2933
2934 return 0;
2935}
2936
2937/**
2938 * amdgpu_vm_make_compute - Turn a GFX VM into a compute VM
2939 *
2940 * @adev: amdgpu_device pointer
2941 * @vm: requested vm
2942 * @pasid: pasid to use
2943 *
2944 * This only works on GFX VMs that don't have any BOs added and no
2945 * page tables allocated yet.
2946 *
2947 * Changes the following VM parameters:
2948 * - use_cpu_for_update
2949 * - pte_supports_ats
2950 * - pasid (old PASID is released, because compute manages its own PASIDs)
2951 *
2952 * Reinitializes the page directory to reflect the changed ATS
2953 * setting.
2954 *
2955 * Returns:
2956 * 0 for success, -errno for errors.
2957 */
2958int amdgpu_vm_make_compute(struct amdgpu_device *adev, struct amdgpu_vm *vm,
2959 unsigned int pasid)
2960{
2961 bool pte_support_ats = (adev->asic_type == CHIP_RAVEN);
2962 int r;
2963
2964 r = amdgpu_bo_reserve(vm->root.base.bo, true);
2965 if (r)
2966 return r;
2967
2968 /* Sanity checks */
2969 r = amdgpu_vm_check_clean_reserved(adev, vm);
2970 if (r)
2971 goto unreserve_bo;
2972
2973 if (pasid) {
2974 unsigned long flags;
2975
2976 spin_lock_irqsave(&adev->vm_manager.pasid_lock, flags);
2977 r = idr_alloc(&adev->vm_manager.pasid_idr, vm, pasid, pasid + 1,
2978 GFP_ATOMIC);
2979 spin_unlock_irqrestore(&adev->vm_manager.pasid_lock, flags);
2980
2981 if (r == -ENOSPC)
2982 goto unreserve_bo;
2983 r = 0;
2984 }
2985
2986 /* Check if PD needs to be reinitialized and do it before
2987 * changing any other state, in case it fails.
2988 */
2989 if (pte_support_ats != vm->pte_support_ats) {
2990 vm->pte_support_ats = pte_support_ats;
2991 r = amdgpu_vm_clear_bo(adev, vm, vm->root.base.bo, false);
2992 if (r)
2993 goto free_idr;
2994 }
2995
2996 /* Update VM state */
2997 vm->use_cpu_for_update = !!(adev->vm_manager.vm_update_mode &
2998 AMDGPU_VM_USE_CPU_FOR_COMPUTE);
2999 DRM_DEBUG_DRIVER("VM update mode is %s\n",
3000 vm->use_cpu_for_update ? "CPU" : "SDMA");
3001 WARN_ONCE((vm->use_cpu_for_update &&
3002 !amdgpu_gmc_vram_full_visible(&adev->gmc)),
3003 "CPU update of VM recommended only for large BAR system\n");
3004
3005 if (vm->use_cpu_for_update) {
3006 /* Sync with last SDMA update/clear before switching to CPU */
3007 r = amdgpu_bo_sync_wait(vm->root.base.bo,
3008 AMDGPU_FENCE_OWNER_UNDEFINED, true);
3009 if (r)
3010 goto free_idr;
3011
3012 vm->update_funcs = &amdgpu_vm_cpu_funcs;
3013 } else {
3014 vm->update_funcs = &amdgpu_vm_sdma_funcs;
3015 }
3016 dma_fence_put(vm->last_update);
3017 vm->last_update = NULL;
3018 vm->is_compute_context = true;
3019
3020 if (vm->pasid) {
3021 unsigned long flags;
3022
3023 spin_lock_irqsave(&adev->vm_manager.pasid_lock, flags);
3024 idr_remove(&adev->vm_manager.pasid_idr, vm->pasid);
3025 spin_unlock_irqrestore(&adev->vm_manager.pasid_lock, flags);
3026
3027 /* Free the original amdgpu allocated pasid
3028 * Will be replaced with kfd allocated pasid
3029 */
3030 amdgpu_pasid_free(vm->pasid);
3031 vm->pasid = 0;
3032 }
3033
3034 /* Free the shadow bo for compute VM */
3035 amdgpu_bo_unref(&vm->root.base.bo->shadow);
3036
3037 if (pasid)
3038 vm->pasid = pasid;
3039
3040 goto unreserve_bo;
3041
3042free_idr:
3043 if (pasid) {
3044 unsigned long flags;
3045
3046 spin_lock_irqsave(&adev->vm_manager.pasid_lock, flags);
3047 idr_remove(&adev->vm_manager.pasid_idr, pasid);
3048 spin_unlock_irqrestore(&adev->vm_manager.pasid_lock, flags);
3049 }
3050unreserve_bo:
3051 amdgpu_bo_unreserve(vm->root.base.bo);
3052 return r;
3053}
3054
3055/**
3056 * amdgpu_vm_release_compute - release a compute vm
3057 * @adev: amdgpu_device pointer
3058 * @vm: a vm turned into compute vm by calling amdgpu_vm_make_compute
3059 *
3060 * This is a correspondant of amdgpu_vm_make_compute. It decouples compute
3061 * pasid from vm. Compute should stop use of vm after this call.
3062 */
3063void amdgpu_vm_release_compute(struct amdgpu_device *adev, struct amdgpu_vm *vm)
3064{
3065 if (vm->pasid) {
3066 unsigned long flags;
3067
3068 spin_lock_irqsave(&adev->vm_manager.pasid_lock, flags);
3069 idr_remove(&adev->vm_manager.pasid_idr, vm->pasid);
3070 spin_unlock_irqrestore(&adev->vm_manager.pasid_lock, flags);
3071 }
3072 vm->pasid = 0;
3073 vm->is_compute_context = false;
3074}
3075
3076/**
3077 * amdgpu_vm_fini - tear down a vm instance
3078 *
3079 * @adev: amdgpu_device pointer
3080 * @vm: requested vm
3081 *
3082 * Tear down @vm.
3083 * Unbind the VM and remove all bos from the vm bo list
3084 */
3085void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm)
3086{
3087 struct amdgpu_bo_va_mapping *mapping, *tmp;
3088 bool prt_fini_needed = !!adev->gmc.gmc_funcs->set_prt;
3089 struct amdgpu_bo *root;
3090 int i;
3091
3092 amdgpu_amdkfd_gpuvm_destroy_cb(adev, vm);
3093
3094 root = amdgpu_bo_ref(vm->root.base.bo);
3095 amdgpu_bo_reserve(root, true);
3096 if (vm->pasid) {
3097 unsigned long flags;
3098
3099 spin_lock_irqsave(&adev->vm_manager.pasid_lock, flags);
3100 idr_remove(&adev->vm_manager.pasid_idr, vm->pasid);
3101 spin_unlock_irqrestore(&adev->vm_manager.pasid_lock, flags);
3102 vm->pasid = 0;
3103 }
3104
3105 dma_fence_wait(vm->last_unlocked, false);
3106 dma_fence_put(vm->last_unlocked);
3107
3108 list_for_each_entry_safe(mapping, tmp, &vm->freed, list) {
3109 if (mapping->flags & AMDGPU_PTE_PRT && prt_fini_needed) {
3110 amdgpu_vm_prt_fini(adev, vm);
3111 prt_fini_needed = false;
3112 }
3113
3114 list_del(&mapping->list);
3115 amdgpu_vm_free_mapping(adev, vm, mapping, NULL);
3116 }
3117
3118 amdgpu_vm_free_pts(adev, vm, NULL);
3119 amdgpu_bo_unreserve(root);
3120 amdgpu_bo_unref(&root);
3121 WARN_ON(vm->root.base.bo);
3122
3123 drm_sched_entity_destroy(&vm->immediate);
3124 drm_sched_entity_destroy(&vm->delayed);
3125
3126 if (!RB_EMPTY_ROOT(&vm->va.rb_root)) {
3127 dev_err(adev->dev, "still active bo inside vm\n");
3128 }
3129 rbtree_postorder_for_each_entry_safe(mapping, tmp,
3130 &vm->va.rb_root, rb) {
3131 /* Don't remove the mapping here, we don't want to trigger a
3132 * rebalance and the tree is about to be destroyed anyway.
3133 */
3134 list_del(&mapping->list);
3135 kfree(mapping);
3136 }
3137
3138 dma_fence_put(vm->last_update);
3139 for (i = 0; i < AMDGPU_MAX_VMHUBS; i++)
3140 amdgpu_vmid_free_reserved(adev, vm, i);
3141}
3142
3143/**
3144 * amdgpu_vm_manager_init - init the VM manager
3145 *
3146 * @adev: amdgpu_device pointer
3147 *
3148 * Initialize the VM manager structures
3149 */
3150void amdgpu_vm_manager_init(struct amdgpu_device *adev)
3151{
3152 unsigned i;
3153
3154 amdgpu_vmid_mgr_init(adev);
3155
3156 adev->vm_manager.fence_context =
3157 dma_fence_context_alloc(AMDGPU_MAX_RINGS);
3158 for (i = 0; i < AMDGPU_MAX_RINGS; ++i)
3159 adev->vm_manager.seqno[i] = 0;
3160
3161 spin_lock_init(&adev->vm_manager.prt_lock);
3162 atomic_set(&adev->vm_manager.num_prt_users, 0);
3163
3164 /* If not overridden by the user, by default, only in large BAR systems
3165 * Compute VM tables will be updated by CPU
3166 */
3167#ifdef CONFIG_X86_64
3168 if (amdgpu_vm_update_mode == -1) {
3169 if (amdgpu_gmc_vram_full_visible(&adev->gmc))
3170 adev->vm_manager.vm_update_mode =
3171 AMDGPU_VM_USE_CPU_FOR_COMPUTE;
3172 else
3173 adev->vm_manager.vm_update_mode = 0;
3174 } else
3175 adev->vm_manager.vm_update_mode = amdgpu_vm_update_mode;
3176#else
3177 adev->vm_manager.vm_update_mode = 0;
3178#endif
3179
3180 idr_init(&adev->vm_manager.pasid_idr);
3181 spin_lock_init(&adev->vm_manager.pasid_lock);
3182}
3183
3184/**
3185 * amdgpu_vm_manager_fini - cleanup VM manager
3186 *
3187 * @adev: amdgpu_device pointer
3188 *
3189 * Cleanup the VM manager and free resources.
3190 */
3191void amdgpu_vm_manager_fini(struct amdgpu_device *adev)
3192{
3193 WARN_ON(!idr_is_empty(&adev->vm_manager.pasid_idr));
3194 idr_destroy(&adev->vm_manager.pasid_idr);
3195
3196 amdgpu_vmid_mgr_fini(adev);
3197}
3198
3199/**
3200 * amdgpu_vm_ioctl - Manages VMID reservation for vm hubs.
3201 *
3202 * @dev: drm device pointer
3203 * @data: drm_amdgpu_vm
3204 * @filp: drm file pointer
3205 *
3206 * Returns:
3207 * 0 for success, -errno for errors.
3208 */
3209int amdgpu_vm_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
3210{
3211 union drm_amdgpu_vm *args = data;
3212 struct amdgpu_device *adev = dev->dev_private;
3213 struct amdgpu_fpriv *fpriv = filp->driver_priv;
3214 long timeout = msecs_to_jiffies(2000);
3215 int r;
3216
3217 switch (args->in.op) {
3218 case AMDGPU_VM_OP_RESERVE_VMID:
3219 /* We only have requirement to reserve vmid from gfxhub */
3220 r = amdgpu_vmid_alloc_reserved(adev, &fpriv->vm,
3221 AMDGPU_GFXHUB_0);
3222 if (r)
3223 return r;
3224 break;
3225 case AMDGPU_VM_OP_UNRESERVE_VMID:
3226 if (amdgpu_sriov_runtime(adev))
3227 timeout = 8 * timeout;
3228
3229 /* Wait vm idle to make sure the vmid set in SPM_VMID is
3230 * not referenced anymore.
3231 */
3232 r = amdgpu_bo_reserve(fpriv->vm.root.base.bo, true);
3233 if (r)
3234 return r;
3235
3236 r = amdgpu_vm_wait_idle(&fpriv->vm, timeout);
3237 if (r < 0)
3238 return r;
3239
3240 amdgpu_bo_unreserve(fpriv->vm.root.base.bo);
3241 amdgpu_vmid_free_reserved(adev, &fpriv->vm, AMDGPU_GFXHUB_0);
3242 break;
3243 default:
3244 return -EINVAL;
3245 }
3246
3247 return 0;
3248}
3249
3250/**
3251 * amdgpu_vm_get_task_info - Extracts task info for a PASID.
3252 *
3253 * @adev: drm device pointer
3254 * @pasid: PASID identifier for VM
3255 * @task_info: task_info to fill.
3256 */
3257void amdgpu_vm_get_task_info(struct amdgpu_device *adev, unsigned int pasid,
3258 struct amdgpu_task_info *task_info)
3259{
3260 struct amdgpu_vm *vm;
3261 unsigned long flags;
3262
3263 spin_lock_irqsave(&adev->vm_manager.pasid_lock, flags);
3264
3265 vm = idr_find(&adev->vm_manager.pasid_idr, pasid);
3266 if (vm)
3267 *task_info = vm->task_info;
3268
3269 spin_unlock_irqrestore(&adev->vm_manager.pasid_lock, flags);
3270}
3271
3272/**
3273 * amdgpu_vm_set_task_info - Sets VMs task info.
3274 *
3275 * @vm: vm for which to set the info
3276 */
3277void amdgpu_vm_set_task_info(struct amdgpu_vm *vm)
3278{
3279 if (vm->task_info.pid)
3280 return;
3281
3282 vm->task_info.pid = current->pid;
3283 get_task_comm(vm->task_info.task_name, current);
3284
3285 if (current->group_leader->mm != current->mm)
3286 return;
3287
3288 vm->task_info.tgid = current->group_leader->pid;
3289 get_task_comm(vm->task_info.process_name, current->group_leader);
3290}
3291
3292/**
3293 * amdgpu_vm_handle_fault - graceful handling of VM faults.
3294 * @adev: amdgpu device pointer
3295 * @pasid: PASID of the VM
3296 * @addr: Address of the fault
3297 *
3298 * Try to gracefully handle a VM fault. Return true if the fault was handled and
3299 * shouldn't be reported any more.
3300 */
3301bool amdgpu_vm_handle_fault(struct amdgpu_device *adev, unsigned int pasid,
3302 uint64_t addr)
3303{
3304 struct amdgpu_bo *root;
3305 uint64_t value, flags;
3306 struct amdgpu_vm *vm;
3307 long r;
3308
3309 spin_lock(&adev->vm_manager.pasid_lock);
3310 vm = idr_find(&adev->vm_manager.pasid_idr, pasid);
3311 if (vm)
3312 root = amdgpu_bo_ref(vm->root.base.bo);
3313 else
3314 root = NULL;
3315 spin_unlock(&adev->vm_manager.pasid_lock);
3316
3317 if (!root)
3318 return false;
3319
3320 r = amdgpu_bo_reserve(root, true);
3321 if (r)
3322 goto error_unref;
3323
3324 /* Double check that the VM still exists */
3325 spin_lock(&adev->vm_manager.pasid_lock);
3326 vm = idr_find(&adev->vm_manager.pasid_idr, pasid);
3327 if (vm && vm->root.base.bo != root)
3328 vm = NULL;
3329 spin_unlock(&adev->vm_manager.pasid_lock);
3330 if (!vm)
3331 goto error_unlock;
3332
3333 addr /= AMDGPU_GPU_PAGE_SIZE;
3334 flags = AMDGPU_PTE_VALID | AMDGPU_PTE_SNOOPED |
3335 AMDGPU_PTE_SYSTEM;
3336
3337 if (vm->is_compute_context) {
3338 /* Intentionally setting invalid PTE flag
3339 * combination to force a no-retry-fault
3340 */
3341 flags = AMDGPU_PTE_EXECUTABLE | AMDGPU_PDE_PTE |
3342 AMDGPU_PTE_TF;
3343 value = 0;
3344
3345 } else if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_NEVER) {
3346 /* Redirect the access to the dummy page */
3347 value = adev->dummy_page_addr;
3348 flags |= AMDGPU_PTE_EXECUTABLE | AMDGPU_PTE_READABLE |
3349 AMDGPU_PTE_WRITEABLE;
3350
3351 } else {
3352 /* Let the hw retry silently on the PTE */
3353 value = 0;
3354 }
3355
3356 r = amdgpu_vm_bo_update_mapping(adev, vm, true, false, NULL, addr,
3357 addr + 1, flags, value, NULL, NULL);
3358 if (r)
3359 goto error_unlock;
3360
3361 r = amdgpu_vm_update_pdes(adev, vm, true);
3362
3363error_unlock:
3364 amdgpu_bo_unreserve(root);
3365 if (r < 0)
3366 DRM_ERROR("Can't handle page fault (%ld)\n", r);
3367
3368error_unref:
3369 amdgpu_bo_unref(&root);
3370
3371 return false;
3372}
1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28
29#include <linux/dma-fence-array.h>
30#include <linux/interval_tree_generic.h>
31#include <linux/idr.h>
32#include <linux/dma-buf.h>
33
34#include <drm/amdgpu_drm.h>
35#include <drm/drm_drv.h>
36#include <drm/ttm/ttm_tt.h>
37#include <drm/drm_exec.h>
38#include "amdgpu.h"
39#include "amdgpu_trace.h"
40#include "amdgpu_amdkfd.h"
41#include "amdgpu_gmc.h"
42#include "amdgpu_xgmi.h"
43#include "amdgpu_dma_buf.h"
44#include "amdgpu_res_cursor.h"
45#include "kfd_svm.h"
46
47/**
48 * DOC: GPUVM
49 *
50 * GPUVM is the MMU functionality provided on the GPU.
51 * GPUVM is similar to the legacy GART on older asics, however
52 * rather than there being a single global GART table
53 * for the entire GPU, there can be multiple GPUVM page tables active
54 * at any given time. The GPUVM page tables can contain a mix
55 * VRAM pages and system pages (both memory and MMIO) and system pages
56 * can be mapped as snooped (cached system pages) or unsnooped
57 * (uncached system pages).
58 *
59 * Each active GPUVM has an ID associated with it and there is a page table
60 * linked with each VMID. When executing a command buffer,
61 * the kernel tells the engine what VMID to use for that command
62 * buffer. VMIDs are allocated dynamically as commands are submitted.
63 * The userspace drivers maintain their own address space and the kernel
64 * sets up their pages tables accordingly when they submit their
65 * command buffers and a VMID is assigned.
66 * The hardware supports up to 16 active GPUVMs at any given time.
67 *
68 * Each GPUVM is represented by a 1-2 or 1-5 level page table, depending
69 * on the ASIC family. GPUVM supports RWX attributes on each page as well
70 * as other features such as encryption and caching attributes.
71 *
72 * VMID 0 is special. It is the GPUVM used for the kernel driver. In
73 * addition to an aperture managed by a page table, VMID 0 also has
74 * several other apertures. There is an aperture for direct access to VRAM
75 * and there is a legacy AGP aperture which just forwards accesses directly
76 * to the matching system physical addresses (or IOVAs when an IOMMU is
77 * present). These apertures provide direct access to these memories without
78 * incurring the overhead of a page table. VMID 0 is used by the kernel
79 * driver for tasks like memory management.
80 *
81 * GPU clients (i.e., engines on the GPU) use GPUVM VMIDs to access memory.
82 * For user applications, each application can have their own unique GPUVM
83 * address space. The application manages the address space and the kernel
84 * driver manages the GPUVM page tables for each process. If an GPU client
85 * accesses an invalid page, it will generate a GPU page fault, similar to
86 * accessing an invalid page on a CPU.
87 */
88
89#define START(node) ((node)->start)
90#define LAST(node) ((node)->last)
91
92INTERVAL_TREE_DEFINE(struct amdgpu_bo_va_mapping, rb, uint64_t, __subtree_last,
93 START, LAST, static, amdgpu_vm_it)
94
95#undef START
96#undef LAST
97
98/**
99 * struct amdgpu_prt_cb - Helper to disable partial resident texture feature from a fence callback
100 */
101struct amdgpu_prt_cb {
102
103 /**
104 * @adev: amdgpu device
105 */
106 struct amdgpu_device *adev;
107
108 /**
109 * @cb: callback
110 */
111 struct dma_fence_cb cb;
112};
113
114/**
115 * struct amdgpu_vm_tlb_seq_struct - Helper to increment the TLB flush sequence
116 */
117struct amdgpu_vm_tlb_seq_struct {
118 /**
119 * @vm: pointer to the amdgpu_vm structure to set the fence sequence on
120 */
121 struct amdgpu_vm *vm;
122
123 /**
124 * @cb: callback
125 */
126 struct dma_fence_cb cb;
127};
128
129/**
130 * amdgpu_vm_set_pasid - manage pasid and vm ptr mapping
131 *
132 * @adev: amdgpu_device pointer
133 * @vm: amdgpu_vm pointer
134 * @pasid: the pasid the VM is using on this GPU
135 *
136 * Set the pasid this VM is using on this GPU, can also be used to remove the
137 * pasid by passing in zero.
138 *
139 */
140int amdgpu_vm_set_pasid(struct amdgpu_device *adev, struct amdgpu_vm *vm,
141 u32 pasid)
142{
143 int r;
144
145 if (vm->pasid == pasid)
146 return 0;
147
148 if (vm->pasid) {
149 r = xa_err(xa_erase_irq(&adev->vm_manager.pasids, vm->pasid));
150 if (r < 0)
151 return r;
152
153 vm->pasid = 0;
154 }
155
156 if (pasid) {
157 r = xa_err(xa_store_irq(&adev->vm_manager.pasids, pasid, vm,
158 GFP_KERNEL));
159 if (r < 0)
160 return r;
161
162 vm->pasid = pasid;
163 }
164
165
166 return 0;
167}
168
169/**
170 * amdgpu_vm_bo_evicted - vm_bo is evicted
171 *
172 * @vm_bo: vm_bo which is evicted
173 *
174 * State for PDs/PTs and per VM BOs which are not at the location they should
175 * be.
176 */
177static void amdgpu_vm_bo_evicted(struct amdgpu_vm_bo_base *vm_bo)
178{
179 struct amdgpu_vm *vm = vm_bo->vm;
180 struct amdgpu_bo *bo = vm_bo->bo;
181
182 vm_bo->moved = true;
183 spin_lock(&vm_bo->vm->status_lock);
184 if (bo->tbo.type == ttm_bo_type_kernel)
185 list_move(&vm_bo->vm_status, &vm->evicted);
186 else
187 list_move_tail(&vm_bo->vm_status, &vm->evicted);
188 spin_unlock(&vm_bo->vm->status_lock);
189}
190/**
191 * amdgpu_vm_bo_moved - vm_bo is moved
192 *
193 * @vm_bo: vm_bo which is moved
194 *
195 * State for per VM BOs which are moved, but that change is not yet reflected
196 * in the page tables.
197 */
198static void amdgpu_vm_bo_moved(struct amdgpu_vm_bo_base *vm_bo)
199{
200 spin_lock(&vm_bo->vm->status_lock);
201 list_move(&vm_bo->vm_status, &vm_bo->vm->moved);
202 spin_unlock(&vm_bo->vm->status_lock);
203}
204
205/**
206 * amdgpu_vm_bo_idle - vm_bo is idle
207 *
208 * @vm_bo: vm_bo which is now idle
209 *
210 * State for PDs/PTs and per VM BOs which have gone through the state machine
211 * and are now idle.
212 */
213static void amdgpu_vm_bo_idle(struct amdgpu_vm_bo_base *vm_bo)
214{
215 spin_lock(&vm_bo->vm->status_lock);
216 list_move(&vm_bo->vm_status, &vm_bo->vm->idle);
217 spin_unlock(&vm_bo->vm->status_lock);
218 vm_bo->moved = false;
219}
220
221/**
222 * amdgpu_vm_bo_invalidated - vm_bo is invalidated
223 *
224 * @vm_bo: vm_bo which is now invalidated
225 *
226 * State for normal BOs which are invalidated and that change not yet reflected
227 * in the PTs.
228 */
229static void amdgpu_vm_bo_invalidated(struct amdgpu_vm_bo_base *vm_bo)
230{
231 spin_lock(&vm_bo->vm->status_lock);
232 list_move(&vm_bo->vm_status, &vm_bo->vm->invalidated);
233 spin_unlock(&vm_bo->vm->status_lock);
234}
235
236/**
237 * amdgpu_vm_bo_evicted_user - vm_bo is evicted
238 *
239 * @vm_bo: vm_bo which is evicted
240 *
241 * State for BOs used by user mode queues which are not at the location they
242 * should be.
243 */
244static void amdgpu_vm_bo_evicted_user(struct amdgpu_vm_bo_base *vm_bo)
245{
246 vm_bo->moved = true;
247 spin_lock(&vm_bo->vm->status_lock);
248 list_move(&vm_bo->vm_status, &vm_bo->vm->evicted_user);
249 spin_unlock(&vm_bo->vm->status_lock);
250}
251
252/**
253 * amdgpu_vm_bo_relocated - vm_bo is reloacted
254 *
255 * @vm_bo: vm_bo which is relocated
256 *
257 * State for PDs/PTs which needs to update their parent PD.
258 * For the root PD, just move to idle state.
259 */
260static void amdgpu_vm_bo_relocated(struct amdgpu_vm_bo_base *vm_bo)
261{
262 if (vm_bo->bo->parent) {
263 spin_lock(&vm_bo->vm->status_lock);
264 list_move(&vm_bo->vm_status, &vm_bo->vm->relocated);
265 spin_unlock(&vm_bo->vm->status_lock);
266 } else {
267 amdgpu_vm_bo_idle(vm_bo);
268 }
269}
270
271/**
272 * amdgpu_vm_bo_done - vm_bo is done
273 *
274 * @vm_bo: vm_bo which is now done
275 *
276 * State for normal BOs which are invalidated and that change has been updated
277 * in the PTs.
278 */
279static void amdgpu_vm_bo_done(struct amdgpu_vm_bo_base *vm_bo)
280{
281 spin_lock(&vm_bo->vm->status_lock);
282 list_move(&vm_bo->vm_status, &vm_bo->vm->done);
283 spin_unlock(&vm_bo->vm->status_lock);
284}
285
286/**
287 * amdgpu_vm_bo_reset_state_machine - reset the vm_bo state machine
288 * @vm: the VM which state machine to reset
289 *
290 * Move all vm_bo object in the VM into a state where they will be updated
291 * again during validation.
292 */
293static void amdgpu_vm_bo_reset_state_machine(struct amdgpu_vm *vm)
294{
295 struct amdgpu_vm_bo_base *vm_bo, *tmp;
296
297 spin_lock(&vm->status_lock);
298 list_splice_init(&vm->done, &vm->invalidated);
299 list_for_each_entry(vm_bo, &vm->invalidated, vm_status)
300 vm_bo->moved = true;
301 list_for_each_entry_safe(vm_bo, tmp, &vm->idle, vm_status) {
302 struct amdgpu_bo *bo = vm_bo->bo;
303
304 vm_bo->moved = true;
305 if (!bo || bo->tbo.type != ttm_bo_type_kernel)
306 list_move(&vm_bo->vm_status, &vm_bo->vm->moved);
307 else if (bo->parent)
308 list_move(&vm_bo->vm_status, &vm_bo->vm->relocated);
309 }
310 spin_unlock(&vm->status_lock);
311}
312
313/**
314 * amdgpu_vm_bo_base_init - Adds bo to the list of bos associated with the vm
315 *
316 * @base: base structure for tracking BO usage in a VM
317 * @vm: vm to which bo is to be added
318 * @bo: amdgpu buffer object
319 *
320 * Initialize a bo_va_base structure and add it to the appropriate lists
321 *
322 */
323void amdgpu_vm_bo_base_init(struct amdgpu_vm_bo_base *base,
324 struct amdgpu_vm *vm, struct amdgpu_bo *bo)
325{
326 base->vm = vm;
327 base->bo = bo;
328 base->next = NULL;
329 INIT_LIST_HEAD(&base->vm_status);
330
331 if (!bo)
332 return;
333 base->next = bo->vm_bo;
334 bo->vm_bo = base;
335
336 if (!amdgpu_vm_is_bo_always_valid(vm, bo))
337 return;
338
339 dma_resv_assert_held(vm->root.bo->tbo.base.resv);
340
341 ttm_bo_set_bulk_move(&bo->tbo, &vm->lru_bulk_move);
342 if (bo->tbo.type == ttm_bo_type_kernel && bo->parent)
343 amdgpu_vm_bo_relocated(base);
344 else
345 amdgpu_vm_bo_idle(base);
346
347 if (bo->preferred_domains &
348 amdgpu_mem_type_to_domain(bo->tbo.resource->mem_type))
349 return;
350
351 /*
352 * we checked all the prerequisites, but it looks like this per vm bo
353 * is currently evicted. add the bo to the evicted list to make sure it
354 * is validated on next vm use to avoid fault.
355 * */
356 amdgpu_vm_bo_evicted(base);
357}
358
359/**
360 * amdgpu_vm_lock_pd - lock PD in drm_exec
361 *
362 * @vm: vm providing the BOs
363 * @exec: drm execution context
364 * @num_fences: number of extra fences to reserve
365 *
366 * Lock the VM root PD in the DRM execution context.
367 */
368int amdgpu_vm_lock_pd(struct amdgpu_vm *vm, struct drm_exec *exec,
369 unsigned int num_fences)
370{
371 /* We need at least two fences for the VM PD/PT updates */
372 return drm_exec_prepare_obj(exec, &vm->root.bo->tbo.base,
373 2 + num_fences);
374}
375
376/**
377 * amdgpu_vm_move_to_lru_tail - move all BOs to the end of LRU
378 *
379 * @adev: amdgpu device pointer
380 * @vm: vm providing the BOs
381 *
382 * Move all BOs to the end of LRU and remember their positions to put them
383 * together.
384 */
385void amdgpu_vm_move_to_lru_tail(struct amdgpu_device *adev,
386 struct amdgpu_vm *vm)
387{
388 spin_lock(&adev->mman.bdev.lru_lock);
389 ttm_lru_bulk_move_tail(&vm->lru_bulk_move);
390 spin_unlock(&adev->mman.bdev.lru_lock);
391}
392
393/* Create scheduler entities for page table updates */
394static int amdgpu_vm_init_entities(struct amdgpu_device *adev,
395 struct amdgpu_vm *vm)
396{
397 int r;
398
399 r = drm_sched_entity_init(&vm->immediate, DRM_SCHED_PRIORITY_NORMAL,
400 adev->vm_manager.vm_pte_scheds,
401 adev->vm_manager.vm_pte_num_scheds, NULL);
402 if (r)
403 goto error;
404
405 return drm_sched_entity_init(&vm->delayed, DRM_SCHED_PRIORITY_NORMAL,
406 adev->vm_manager.vm_pte_scheds,
407 adev->vm_manager.vm_pte_num_scheds, NULL);
408
409error:
410 drm_sched_entity_destroy(&vm->immediate);
411 return r;
412}
413
414/* Destroy the entities for page table updates again */
415static void amdgpu_vm_fini_entities(struct amdgpu_vm *vm)
416{
417 drm_sched_entity_destroy(&vm->immediate);
418 drm_sched_entity_destroy(&vm->delayed);
419}
420
421/**
422 * amdgpu_vm_generation - return the page table re-generation counter
423 * @adev: the amdgpu_device
424 * @vm: optional VM to check, might be NULL
425 *
426 * Returns a page table re-generation token to allow checking if submissions
427 * are still valid to use this VM. The VM parameter might be NULL in which case
428 * just the VRAM lost counter will be used.
429 */
430uint64_t amdgpu_vm_generation(struct amdgpu_device *adev, struct amdgpu_vm *vm)
431{
432 uint64_t result = (u64)atomic_read(&adev->vram_lost_counter) << 32;
433
434 if (!vm)
435 return result;
436
437 result += lower_32_bits(vm->generation);
438 /* Add one if the page tables will be re-generated on next CS */
439 if (drm_sched_entity_error(&vm->delayed))
440 ++result;
441
442 return result;
443}
444
445/**
446 * amdgpu_vm_validate - validate evicted BOs tracked in the VM
447 *
448 * @adev: amdgpu device pointer
449 * @vm: vm providing the BOs
450 * @ticket: optional reservation ticket used to reserve the VM
451 * @validate: callback to do the validation
452 * @param: parameter for the validation callback
453 *
454 * Validate the page table BOs and per-VM BOs on command submission if
455 * necessary. If a ticket is given, also try to validate evicted user queue
456 * BOs. They must already be reserved with the given ticket.
457 *
458 * Returns:
459 * Validation result.
460 */
461int amdgpu_vm_validate(struct amdgpu_device *adev, struct amdgpu_vm *vm,
462 struct ww_acquire_ctx *ticket,
463 int (*validate)(void *p, struct amdgpu_bo *bo),
464 void *param)
465{
466 uint64_t new_vm_generation = amdgpu_vm_generation(adev, vm);
467 struct amdgpu_vm_bo_base *bo_base;
468 struct amdgpu_bo *bo;
469 int r;
470
471 if (vm->generation != new_vm_generation) {
472 vm->generation = new_vm_generation;
473 amdgpu_vm_bo_reset_state_machine(vm);
474 amdgpu_vm_fini_entities(vm);
475 r = amdgpu_vm_init_entities(adev, vm);
476 if (r)
477 return r;
478 }
479
480 spin_lock(&vm->status_lock);
481 while (!list_empty(&vm->evicted)) {
482 bo_base = list_first_entry(&vm->evicted,
483 struct amdgpu_vm_bo_base,
484 vm_status);
485 spin_unlock(&vm->status_lock);
486
487 bo = bo_base->bo;
488
489 r = validate(param, bo);
490 if (r)
491 return r;
492
493 if (bo->tbo.type != ttm_bo_type_kernel) {
494 amdgpu_vm_bo_moved(bo_base);
495 } else {
496 vm->update_funcs->map_table(to_amdgpu_bo_vm(bo));
497 amdgpu_vm_bo_relocated(bo_base);
498 }
499 spin_lock(&vm->status_lock);
500 }
501 while (ticket && !list_empty(&vm->evicted_user)) {
502 bo_base = list_first_entry(&vm->evicted_user,
503 struct amdgpu_vm_bo_base,
504 vm_status);
505 spin_unlock(&vm->status_lock);
506
507 bo = bo_base->bo;
508
509 if (dma_resv_locking_ctx(bo->tbo.base.resv) != ticket) {
510 struct amdgpu_task_info *ti = amdgpu_vm_get_task_info_vm(vm);
511
512 pr_warn_ratelimited("Evicted user BO is not reserved\n");
513 if (ti) {
514 pr_warn_ratelimited("pid %d\n", ti->pid);
515 amdgpu_vm_put_task_info(ti);
516 }
517
518 return -EINVAL;
519 }
520
521 r = validate(param, bo);
522 if (r)
523 return r;
524
525 amdgpu_vm_bo_invalidated(bo_base);
526
527 spin_lock(&vm->status_lock);
528 }
529 spin_unlock(&vm->status_lock);
530
531 amdgpu_vm_eviction_lock(vm);
532 vm->evicting = false;
533 amdgpu_vm_eviction_unlock(vm);
534
535 return 0;
536}
537
538/**
539 * amdgpu_vm_ready - check VM is ready for updates
540 *
541 * @vm: VM to check
542 *
543 * Check if all VM PDs/PTs are ready for updates
544 *
545 * Returns:
546 * True if VM is not evicting.
547 */
548bool amdgpu_vm_ready(struct amdgpu_vm *vm)
549{
550 bool empty;
551 bool ret;
552
553 amdgpu_vm_eviction_lock(vm);
554 ret = !vm->evicting;
555 amdgpu_vm_eviction_unlock(vm);
556
557 spin_lock(&vm->status_lock);
558 empty = list_empty(&vm->evicted);
559 spin_unlock(&vm->status_lock);
560
561 return ret && empty;
562}
563
564/**
565 * amdgpu_vm_check_compute_bug - check whether asic has compute vm bug
566 *
567 * @adev: amdgpu_device pointer
568 */
569void amdgpu_vm_check_compute_bug(struct amdgpu_device *adev)
570{
571 const struct amdgpu_ip_block *ip_block;
572 bool has_compute_vm_bug;
573 struct amdgpu_ring *ring;
574 int i;
575
576 has_compute_vm_bug = false;
577
578 ip_block = amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_GFX);
579 if (ip_block) {
580 /* Compute has a VM bug for GFX version < 7.
581 Compute has a VM bug for GFX 8 MEC firmware version < 673.*/
582 if (ip_block->version->major <= 7)
583 has_compute_vm_bug = true;
584 else if (ip_block->version->major == 8)
585 if (adev->gfx.mec_fw_version < 673)
586 has_compute_vm_bug = true;
587 }
588
589 for (i = 0; i < adev->num_rings; i++) {
590 ring = adev->rings[i];
591 if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE)
592 /* only compute rings */
593 ring->has_compute_vm_bug = has_compute_vm_bug;
594 else
595 ring->has_compute_vm_bug = false;
596 }
597}
598
599/**
600 * amdgpu_vm_need_pipeline_sync - Check if pipe sync is needed for job.
601 *
602 * @ring: ring on which the job will be submitted
603 * @job: job to submit
604 *
605 * Returns:
606 * True if sync is needed.
607 */
608bool amdgpu_vm_need_pipeline_sync(struct amdgpu_ring *ring,
609 struct amdgpu_job *job)
610{
611 struct amdgpu_device *adev = ring->adev;
612 unsigned vmhub = ring->vm_hub;
613 struct amdgpu_vmid_mgr *id_mgr = &adev->vm_manager.id_mgr[vmhub];
614
615 if (job->vmid == 0)
616 return false;
617
618 if (job->vm_needs_flush || ring->has_compute_vm_bug)
619 return true;
620
621 if (ring->funcs->emit_gds_switch && job->gds_switch_needed)
622 return true;
623
624 if (amdgpu_vmid_had_gpu_reset(adev, &id_mgr->ids[job->vmid]))
625 return true;
626
627 return false;
628}
629
630/**
631 * amdgpu_vm_flush - hardware flush the vm
632 *
633 * @ring: ring to use for flush
634 * @job: related job
635 * @need_pipe_sync: is pipe sync needed
636 *
637 * Emit a VM flush when it is necessary.
638 *
639 * Returns:
640 * 0 on success, errno otherwise.
641 */
642int amdgpu_vm_flush(struct amdgpu_ring *ring, struct amdgpu_job *job,
643 bool need_pipe_sync)
644{
645 struct amdgpu_device *adev = ring->adev;
646 unsigned vmhub = ring->vm_hub;
647 struct amdgpu_vmid_mgr *id_mgr = &adev->vm_manager.id_mgr[vmhub];
648 struct amdgpu_vmid *id = &id_mgr->ids[job->vmid];
649 bool spm_update_needed = job->spm_update_needed;
650 bool gds_switch_needed = ring->funcs->emit_gds_switch &&
651 job->gds_switch_needed;
652 bool vm_flush_needed = job->vm_needs_flush;
653 struct dma_fence *fence = NULL;
654 bool pasid_mapping_needed = false;
655 unsigned int patch;
656 int r;
657
658 if (amdgpu_vmid_had_gpu_reset(adev, id)) {
659 gds_switch_needed = true;
660 vm_flush_needed = true;
661 pasid_mapping_needed = true;
662 spm_update_needed = true;
663 }
664
665 mutex_lock(&id_mgr->lock);
666 if (id->pasid != job->pasid || !id->pasid_mapping ||
667 !dma_fence_is_signaled(id->pasid_mapping))
668 pasid_mapping_needed = true;
669 mutex_unlock(&id_mgr->lock);
670
671 gds_switch_needed &= !!ring->funcs->emit_gds_switch;
672 vm_flush_needed &= !!ring->funcs->emit_vm_flush &&
673 job->vm_pd_addr != AMDGPU_BO_INVALID_OFFSET;
674 pasid_mapping_needed &= adev->gmc.gmc_funcs->emit_pasid_mapping &&
675 ring->funcs->emit_wreg;
676
677 if (!vm_flush_needed && !gds_switch_needed && !need_pipe_sync &&
678 !(job->enforce_isolation && !job->vmid))
679 return 0;
680
681 amdgpu_ring_ib_begin(ring);
682 if (ring->funcs->init_cond_exec)
683 patch = amdgpu_ring_init_cond_exec(ring,
684 ring->cond_exe_gpu_addr);
685
686 if (need_pipe_sync)
687 amdgpu_ring_emit_pipeline_sync(ring);
688
689 if (adev->gfx.enable_cleaner_shader &&
690 ring->funcs->emit_cleaner_shader &&
691 job->enforce_isolation)
692 ring->funcs->emit_cleaner_shader(ring);
693
694 if (vm_flush_needed) {
695 trace_amdgpu_vm_flush(ring, job->vmid, job->vm_pd_addr);
696 amdgpu_ring_emit_vm_flush(ring, job->vmid, job->vm_pd_addr);
697 }
698
699 if (pasid_mapping_needed)
700 amdgpu_gmc_emit_pasid_mapping(ring, job->vmid, job->pasid);
701
702 if (spm_update_needed && adev->gfx.rlc.funcs->update_spm_vmid)
703 adev->gfx.rlc.funcs->update_spm_vmid(adev, ring, job->vmid);
704
705 if (!ring->is_mes_queue && ring->funcs->emit_gds_switch &&
706 gds_switch_needed) {
707 amdgpu_ring_emit_gds_switch(ring, job->vmid, job->gds_base,
708 job->gds_size, job->gws_base,
709 job->gws_size, job->oa_base,
710 job->oa_size);
711 }
712
713 if (vm_flush_needed || pasid_mapping_needed) {
714 r = amdgpu_fence_emit(ring, &fence, NULL, 0);
715 if (r)
716 return r;
717 }
718
719 if (vm_flush_needed) {
720 mutex_lock(&id_mgr->lock);
721 dma_fence_put(id->last_flush);
722 id->last_flush = dma_fence_get(fence);
723 id->current_gpu_reset_count =
724 atomic_read(&adev->gpu_reset_counter);
725 mutex_unlock(&id_mgr->lock);
726 }
727
728 if (pasid_mapping_needed) {
729 mutex_lock(&id_mgr->lock);
730 id->pasid = job->pasid;
731 dma_fence_put(id->pasid_mapping);
732 id->pasid_mapping = dma_fence_get(fence);
733 mutex_unlock(&id_mgr->lock);
734 }
735 dma_fence_put(fence);
736
737 amdgpu_ring_patch_cond_exec(ring, patch);
738
739 /* the double SWITCH_BUFFER here *cannot* be skipped by COND_EXEC */
740 if (ring->funcs->emit_switch_buffer) {
741 amdgpu_ring_emit_switch_buffer(ring);
742 amdgpu_ring_emit_switch_buffer(ring);
743 }
744
745 amdgpu_ring_ib_end(ring);
746 return 0;
747}
748
749/**
750 * amdgpu_vm_bo_find - find the bo_va for a specific vm & bo
751 *
752 * @vm: requested vm
753 * @bo: requested buffer object
754 *
755 * Find @bo inside the requested vm.
756 * Search inside the @bos vm list for the requested vm
757 * Returns the found bo_va or NULL if none is found
758 *
759 * Object has to be reserved!
760 *
761 * Returns:
762 * Found bo_va or NULL.
763 */
764struct amdgpu_bo_va *amdgpu_vm_bo_find(struct amdgpu_vm *vm,
765 struct amdgpu_bo *bo)
766{
767 struct amdgpu_vm_bo_base *base;
768
769 for (base = bo->vm_bo; base; base = base->next) {
770 if (base->vm != vm)
771 continue;
772
773 return container_of(base, struct amdgpu_bo_va, base);
774 }
775 return NULL;
776}
777
778/**
779 * amdgpu_vm_map_gart - Resolve gart mapping of addr
780 *
781 * @pages_addr: optional DMA address to use for lookup
782 * @addr: the unmapped addr
783 *
784 * Look up the physical address of the page that the pte resolves
785 * to.
786 *
787 * Returns:
788 * The pointer for the page table entry.
789 */
790uint64_t amdgpu_vm_map_gart(const dma_addr_t *pages_addr, uint64_t addr)
791{
792 uint64_t result;
793
794 /* page table offset */
795 result = pages_addr[addr >> PAGE_SHIFT];
796
797 /* in case cpu page size != gpu page size*/
798 result |= addr & (~PAGE_MASK);
799
800 result &= 0xFFFFFFFFFFFFF000ULL;
801
802 return result;
803}
804
805/**
806 * amdgpu_vm_update_pdes - make sure that all directories are valid
807 *
808 * @adev: amdgpu_device pointer
809 * @vm: requested vm
810 * @immediate: submit immediately to the paging queue
811 *
812 * Makes sure all directories are up to date.
813 *
814 * Returns:
815 * 0 for success, error for failure.
816 */
817int amdgpu_vm_update_pdes(struct amdgpu_device *adev,
818 struct amdgpu_vm *vm, bool immediate)
819{
820 struct amdgpu_vm_update_params params;
821 struct amdgpu_vm_bo_base *entry;
822 bool flush_tlb_needed = false;
823 LIST_HEAD(relocated);
824 int r, idx;
825
826 spin_lock(&vm->status_lock);
827 list_splice_init(&vm->relocated, &relocated);
828 spin_unlock(&vm->status_lock);
829
830 if (list_empty(&relocated))
831 return 0;
832
833 if (!drm_dev_enter(adev_to_drm(adev), &idx))
834 return -ENODEV;
835
836 memset(¶ms, 0, sizeof(params));
837 params.adev = adev;
838 params.vm = vm;
839 params.immediate = immediate;
840
841 r = vm->update_funcs->prepare(¶ms, NULL);
842 if (r)
843 goto error;
844
845 list_for_each_entry(entry, &relocated, vm_status) {
846 /* vm_flush_needed after updating moved PDEs */
847 flush_tlb_needed |= entry->moved;
848
849 r = amdgpu_vm_pde_update(¶ms, entry);
850 if (r)
851 goto error;
852 }
853
854 r = vm->update_funcs->commit(¶ms, &vm->last_update);
855 if (r)
856 goto error;
857
858 if (flush_tlb_needed)
859 atomic64_inc(&vm->tlb_seq);
860
861 while (!list_empty(&relocated)) {
862 entry = list_first_entry(&relocated, struct amdgpu_vm_bo_base,
863 vm_status);
864 amdgpu_vm_bo_idle(entry);
865 }
866
867error:
868 drm_dev_exit(idx);
869 return r;
870}
871
872/**
873 * amdgpu_vm_tlb_seq_cb - make sure to increment tlb sequence
874 * @fence: unused
875 * @cb: the callback structure
876 *
877 * Increments the tlb sequence to make sure that future CS execute a VM flush.
878 */
879static void amdgpu_vm_tlb_seq_cb(struct dma_fence *fence,
880 struct dma_fence_cb *cb)
881{
882 struct amdgpu_vm_tlb_seq_struct *tlb_cb;
883
884 tlb_cb = container_of(cb, typeof(*tlb_cb), cb);
885 atomic64_inc(&tlb_cb->vm->tlb_seq);
886 kfree(tlb_cb);
887}
888
889/**
890 * amdgpu_vm_tlb_flush - prepare TLB flush
891 *
892 * @params: parameters for update
893 * @fence: input fence to sync TLB flush with
894 * @tlb_cb: the callback structure
895 *
896 * Increments the tlb sequence to make sure that future CS execute a VM flush.
897 */
898static void
899amdgpu_vm_tlb_flush(struct amdgpu_vm_update_params *params,
900 struct dma_fence **fence,
901 struct amdgpu_vm_tlb_seq_struct *tlb_cb)
902{
903 struct amdgpu_vm *vm = params->vm;
904
905 tlb_cb->vm = vm;
906 if (!fence || !*fence) {
907 amdgpu_vm_tlb_seq_cb(NULL, &tlb_cb->cb);
908 return;
909 }
910
911 if (!dma_fence_add_callback(*fence, &tlb_cb->cb,
912 amdgpu_vm_tlb_seq_cb)) {
913 dma_fence_put(vm->last_tlb_flush);
914 vm->last_tlb_flush = dma_fence_get(*fence);
915 } else {
916 amdgpu_vm_tlb_seq_cb(NULL, &tlb_cb->cb);
917 }
918
919 /* Prepare a TLB flush fence to be attached to PTs */
920 if (!params->unlocked && vm->is_compute_context) {
921 amdgpu_vm_tlb_fence_create(params->adev, vm, fence);
922
923 /* Makes sure no PD/PT is freed before the flush */
924 dma_resv_add_fence(vm->root.bo->tbo.base.resv, *fence,
925 DMA_RESV_USAGE_BOOKKEEP);
926 }
927}
928
929/**
930 * amdgpu_vm_update_range - update a range in the vm page table
931 *
932 * @adev: amdgpu_device pointer to use for commands
933 * @vm: the VM to update the range
934 * @immediate: immediate submission in a page fault
935 * @unlocked: unlocked invalidation during MM callback
936 * @flush_tlb: trigger tlb invalidation after update completed
937 * @allow_override: change MTYPE for local NUMA nodes
938 * @sync: fences we need to sync to
939 * @start: start of mapped range
940 * @last: last mapped entry
941 * @flags: flags for the entries
942 * @offset: offset into nodes and pages_addr
943 * @vram_base: base for vram mappings
944 * @res: ttm_resource to map
945 * @pages_addr: DMA addresses to use for mapping
946 * @fence: optional resulting fence
947 *
948 * Fill in the page table entries between @start and @last.
949 *
950 * Returns:
951 * 0 for success, negative erro code for failure.
952 */
953int amdgpu_vm_update_range(struct amdgpu_device *adev, struct amdgpu_vm *vm,
954 bool immediate, bool unlocked, bool flush_tlb,
955 bool allow_override, struct amdgpu_sync *sync,
956 uint64_t start, uint64_t last, uint64_t flags,
957 uint64_t offset, uint64_t vram_base,
958 struct ttm_resource *res, dma_addr_t *pages_addr,
959 struct dma_fence **fence)
960{
961 struct amdgpu_vm_tlb_seq_struct *tlb_cb;
962 struct amdgpu_vm_update_params params;
963 struct amdgpu_res_cursor cursor;
964 int r, idx;
965
966 if (!drm_dev_enter(adev_to_drm(adev), &idx))
967 return -ENODEV;
968
969 tlb_cb = kmalloc(sizeof(*tlb_cb), GFP_KERNEL);
970 if (!tlb_cb) {
971 drm_dev_exit(idx);
972 return -ENOMEM;
973 }
974
975 /* Vega20+XGMI where PTEs get inadvertently cached in L2 texture cache,
976 * heavy-weight flush TLB unconditionally.
977 */
978 flush_tlb |= adev->gmc.xgmi.num_physical_nodes &&
979 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 0);
980
981 /*
982 * On GFX8 and older any 8 PTE block with a valid bit set enters the TLB
983 */
984 flush_tlb |= amdgpu_ip_version(adev, GC_HWIP, 0) < IP_VERSION(9, 0, 0);
985
986 memset(¶ms, 0, sizeof(params));
987 params.adev = adev;
988 params.vm = vm;
989 params.immediate = immediate;
990 params.pages_addr = pages_addr;
991 params.unlocked = unlocked;
992 params.needs_flush = flush_tlb;
993 params.allow_override = allow_override;
994 INIT_LIST_HEAD(¶ms.tlb_flush_waitlist);
995
996 amdgpu_vm_eviction_lock(vm);
997 if (vm->evicting) {
998 r = -EBUSY;
999 goto error_free;
1000 }
1001
1002 if (!unlocked && !dma_fence_is_signaled(vm->last_unlocked)) {
1003 struct dma_fence *tmp = dma_fence_get_stub();
1004
1005 amdgpu_bo_fence(vm->root.bo, vm->last_unlocked, true);
1006 swap(vm->last_unlocked, tmp);
1007 dma_fence_put(tmp);
1008 }
1009
1010 r = vm->update_funcs->prepare(¶ms, sync);
1011 if (r)
1012 goto error_free;
1013
1014 amdgpu_res_first(pages_addr ? NULL : res, offset,
1015 (last - start + 1) * AMDGPU_GPU_PAGE_SIZE, &cursor);
1016 while (cursor.remaining) {
1017 uint64_t tmp, num_entries, addr;
1018
1019 num_entries = cursor.size >> AMDGPU_GPU_PAGE_SHIFT;
1020 if (pages_addr) {
1021 bool contiguous = true;
1022
1023 if (num_entries > AMDGPU_GPU_PAGES_IN_CPU_PAGE) {
1024 uint64_t pfn = cursor.start >> PAGE_SHIFT;
1025 uint64_t count;
1026
1027 contiguous = pages_addr[pfn + 1] ==
1028 pages_addr[pfn] + PAGE_SIZE;
1029
1030 tmp = num_entries /
1031 AMDGPU_GPU_PAGES_IN_CPU_PAGE;
1032 for (count = 2; count < tmp; ++count) {
1033 uint64_t idx = pfn + count;
1034
1035 if (contiguous != (pages_addr[idx] ==
1036 pages_addr[idx - 1] + PAGE_SIZE))
1037 break;
1038 }
1039 if (!contiguous)
1040 count--;
1041 num_entries = count *
1042 AMDGPU_GPU_PAGES_IN_CPU_PAGE;
1043 }
1044
1045 if (!contiguous) {
1046 addr = cursor.start;
1047 params.pages_addr = pages_addr;
1048 } else {
1049 addr = pages_addr[cursor.start >> PAGE_SHIFT];
1050 params.pages_addr = NULL;
1051 }
1052
1053 } else if (flags & (AMDGPU_PTE_VALID | AMDGPU_PTE_PRT_FLAG(adev))) {
1054 addr = vram_base + cursor.start;
1055 } else {
1056 addr = 0;
1057 }
1058
1059 tmp = start + num_entries;
1060 r = amdgpu_vm_ptes_update(¶ms, start, tmp, addr, flags);
1061 if (r)
1062 goto error_free;
1063
1064 amdgpu_res_next(&cursor, num_entries * AMDGPU_GPU_PAGE_SIZE);
1065 start = tmp;
1066 }
1067
1068 r = vm->update_funcs->commit(¶ms, fence);
1069 if (r)
1070 goto error_free;
1071
1072 if (params.needs_flush) {
1073 amdgpu_vm_tlb_flush(¶ms, fence, tlb_cb);
1074 tlb_cb = NULL;
1075 }
1076
1077 amdgpu_vm_pt_free_list(adev, ¶ms);
1078
1079error_free:
1080 kfree(tlb_cb);
1081 amdgpu_vm_eviction_unlock(vm);
1082 drm_dev_exit(idx);
1083 return r;
1084}
1085
1086static void amdgpu_vm_bo_get_memory(struct amdgpu_bo_va *bo_va,
1087 struct amdgpu_mem_stats *stats,
1088 unsigned int size)
1089{
1090 struct amdgpu_vm *vm = bo_va->base.vm;
1091 struct amdgpu_bo *bo = bo_va->base.bo;
1092
1093 if (!bo)
1094 return;
1095
1096 /*
1097 * For now ignore BOs which are currently locked and potentially
1098 * changing their location.
1099 */
1100 if (!amdgpu_vm_is_bo_always_valid(vm, bo) &&
1101 !dma_resv_trylock(bo->tbo.base.resv))
1102 return;
1103
1104 amdgpu_bo_get_memory(bo, stats, size);
1105 if (!amdgpu_vm_is_bo_always_valid(vm, bo))
1106 dma_resv_unlock(bo->tbo.base.resv);
1107}
1108
1109void amdgpu_vm_get_memory(struct amdgpu_vm *vm,
1110 struct amdgpu_mem_stats *stats,
1111 unsigned int size)
1112{
1113 struct amdgpu_bo_va *bo_va, *tmp;
1114
1115 spin_lock(&vm->status_lock);
1116 list_for_each_entry_safe(bo_va, tmp, &vm->idle, base.vm_status)
1117 amdgpu_vm_bo_get_memory(bo_va, stats, size);
1118
1119 list_for_each_entry_safe(bo_va, tmp, &vm->evicted, base.vm_status)
1120 amdgpu_vm_bo_get_memory(bo_va, stats, size);
1121
1122 list_for_each_entry_safe(bo_va, tmp, &vm->relocated, base.vm_status)
1123 amdgpu_vm_bo_get_memory(bo_va, stats, size);
1124
1125 list_for_each_entry_safe(bo_va, tmp, &vm->moved, base.vm_status)
1126 amdgpu_vm_bo_get_memory(bo_va, stats, size);
1127
1128 list_for_each_entry_safe(bo_va, tmp, &vm->invalidated, base.vm_status)
1129 amdgpu_vm_bo_get_memory(bo_va, stats, size);
1130
1131 list_for_each_entry_safe(bo_va, tmp, &vm->done, base.vm_status)
1132 amdgpu_vm_bo_get_memory(bo_va, stats, size);
1133 spin_unlock(&vm->status_lock);
1134}
1135
1136/**
1137 * amdgpu_vm_bo_update - update all BO mappings in the vm page table
1138 *
1139 * @adev: amdgpu_device pointer
1140 * @bo_va: requested BO and VM object
1141 * @clear: if true clear the entries
1142 *
1143 * Fill in the page table entries for @bo_va.
1144 *
1145 * Returns:
1146 * 0 for success, -EINVAL for failure.
1147 */
1148int amdgpu_vm_bo_update(struct amdgpu_device *adev, struct amdgpu_bo_va *bo_va,
1149 bool clear)
1150{
1151 struct amdgpu_bo *bo = bo_va->base.bo;
1152 struct amdgpu_vm *vm = bo_va->base.vm;
1153 struct amdgpu_bo_va_mapping *mapping;
1154 struct dma_fence **last_update;
1155 dma_addr_t *pages_addr = NULL;
1156 struct ttm_resource *mem;
1157 struct amdgpu_sync sync;
1158 bool flush_tlb = clear;
1159 uint64_t vram_base;
1160 uint64_t flags;
1161 bool uncached;
1162 int r;
1163
1164 amdgpu_sync_create(&sync);
1165 if (clear) {
1166 mem = NULL;
1167
1168 /* Implicitly sync to command submissions in the same VM before
1169 * unmapping.
1170 */
1171 r = amdgpu_sync_resv(adev, &sync, vm->root.bo->tbo.base.resv,
1172 AMDGPU_SYNC_EQ_OWNER, vm);
1173 if (r)
1174 goto error_free;
1175 if (bo) {
1176 r = amdgpu_sync_kfd(&sync, bo->tbo.base.resv);
1177 if (r)
1178 goto error_free;
1179 }
1180 } else if (!bo) {
1181 mem = NULL;
1182
1183 /* PRT map operations don't need to sync to anything. */
1184
1185 } else {
1186 struct drm_gem_object *obj = &bo->tbo.base;
1187
1188 if (obj->import_attach && bo_va->is_xgmi) {
1189 struct dma_buf *dma_buf = obj->import_attach->dmabuf;
1190 struct drm_gem_object *gobj = dma_buf->priv;
1191 struct amdgpu_bo *abo = gem_to_amdgpu_bo(gobj);
1192
1193 if (abo->tbo.resource &&
1194 abo->tbo.resource->mem_type == TTM_PL_VRAM)
1195 bo = gem_to_amdgpu_bo(gobj);
1196 }
1197 mem = bo->tbo.resource;
1198 if (mem && (mem->mem_type == TTM_PL_TT ||
1199 mem->mem_type == AMDGPU_PL_PREEMPT))
1200 pages_addr = bo->tbo.ttm->dma_address;
1201
1202 /* Implicitly sync to moving fences before mapping anything */
1203 r = amdgpu_sync_resv(adev, &sync, bo->tbo.base.resv,
1204 AMDGPU_SYNC_EXPLICIT, vm);
1205 if (r)
1206 goto error_free;
1207 }
1208
1209 if (bo) {
1210 struct amdgpu_device *bo_adev;
1211
1212 flags = amdgpu_ttm_tt_pte_flags(adev, bo->tbo.ttm, mem);
1213
1214 if (amdgpu_bo_encrypted(bo))
1215 flags |= AMDGPU_PTE_TMZ;
1216
1217 bo_adev = amdgpu_ttm_adev(bo->tbo.bdev);
1218 vram_base = bo_adev->vm_manager.vram_base_offset;
1219 uncached = (bo->flags & AMDGPU_GEM_CREATE_UNCACHED) != 0;
1220 } else {
1221 flags = 0x0;
1222 vram_base = 0;
1223 uncached = false;
1224 }
1225
1226 if (clear || amdgpu_vm_is_bo_always_valid(vm, bo))
1227 last_update = &vm->last_update;
1228 else
1229 last_update = &bo_va->last_pt_update;
1230
1231 if (!clear && bo_va->base.moved) {
1232 flush_tlb = true;
1233 list_splice_init(&bo_va->valids, &bo_va->invalids);
1234
1235 } else if (bo_va->cleared != clear) {
1236 list_splice_init(&bo_va->valids, &bo_va->invalids);
1237 }
1238
1239 list_for_each_entry(mapping, &bo_va->invalids, list) {
1240 uint64_t update_flags = flags;
1241
1242 /* normally,bo_va->flags only contians READABLE and WIRTEABLE bit go here
1243 * but in case of something, we filter the flags in first place
1244 */
1245 if (!(mapping->flags & AMDGPU_PTE_READABLE))
1246 update_flags &= ~AMDGPU_PTE_READABLE;
1247 if (!(mapping->flags & AMDGPU_PTE_WRITEABLE))
1248 update_flags &= ~AMDGPU_PTE_WRITEABLE;
1249
1250 /* Apply ASIC specific mapping flags */
1251 amdgpu_gmc_get_vm_pte(adev, mapping, &update_flags);
1252
1253 trace_amdgpu_vm_bo_update(mapping);
1254
1255 r = amdgpu_vm_update_range(adev, vm, false, false, flush_tlb,
1256 !uncached, &sync, mapping->start,
1257 mapping->last, update_flags,
1258 mapping->offset, vram_base, mem,
1259 pages_addr, last_update);
1260 if (r)
1261 goto error_free;
1262 }
1263
1264 /* If the BO is not in its preferred location add it back to
1265 * the evicted list so that it gets validated again on the
1266 * next command submission.
1267 */
1268 if (amdgpu_vm_is_bo_always_valid(vm, bo)) {
1269 if (bo->tbo.resource &&
1270 !(bo->preferred_domains &
1271 amdgpu_mem_type_to_domain(bo->tbo.resource->mem_type)))
1272 amdgpu_vm_bo_evicted(&bo_va->base);
1273 else
1274 amdgpu_vm_bo_idle(&bo_va->base);
1275 } else {
1276 amdgpu_vm_bo_done(&bo_va->base);
1277 }
1278
1279 list_splice_init(&bo_va->invalids, &bo_va->valids);
1280 bo_va->cleared = clear;
1281 bo_va->base.moved = false;
1282
1283 if (trace_amdgpu_vm_bo_mapping_enabled()) {
1284 list_for_each_entry(mapping, &bo_va->valids, list)
1285 trace_amdgpu_vm_bo_mapping(mapping);
1286 }
1287
1288error_free:
1289 amdgpu_sync_free(&sync);
1290 return r;
1291}
1292
1293/**
1294 * amdgpu_vm_update_prt_state - update the global PRT state
1295 *
1296 * @adev: amdgpu_device pointer
1297 */
1298static void amdgpu_vm_update_prt_state(struct amdgpu_device *adev)
1299{
1300 unsigned long flags;
1301 bool enable;
1302
1303 spin_lock_irqsave(&adev->vm_manager.prt_lock, flags);
1304 enable = !!atomic_read(&adev->vm_manager.num_prt_users);
1305 adev->gmc.gmc_funcs->set_prt(adev, enable);
1306 spin_unlock_irqrestore(&adev->vm_manager.prt_lock, flags);
1307}
1308
1309/**
1310 * amdgpu_vm_prt_get - add a PRT user
1311 *
1312 * @adev: amdgpu_device pointer
1313 */
1314static void amdgpu_vm_prt_get(struct amdgpu_device *adev)
1315{
1316 if (!adev->gmc.gmc_funcs->set_prt)
1317 return;
1318
1319 if (atomic_inc_return(&adev->vm_manager.num_prt_users) == 1)
1320 amdgpu_vm_update_prt_state(adev);
1321}
1322
1323/**
1324 * amdgpu_vm_prt_put - drop a PRT user
1325 *
1326 * @adev: amdgpu_device pointer
1327 */
1328static void amdgpu_vm_prt_put(struct amdgpu_device *adev)
1329{
1330 if (atomic_dec_return(&adev->vm_manager.num_prt_users) == 0)
1331 amdgpu_vm_update_prt_state(adev);
1332}
1333
1334/**
1335 * amdgpu_vm_prt_cb - callback for updating the PRT status
1336 *
1337 * @fence: fence for the callback
1338 * @_cb: the callback function
1339 */
1340static void amdgpu_vm_prt_cb(struct dma_fence *fence, struct dma_fence_cb *_cb)
1341{
1342 struct amdgpu_prt_cb *cb = container_of(_cb, struct amdgpu_prt_cb, cb);
1343
1344 amdgpu_vm_prt_put(cb->adev);
1345 kfree(cb);
1346}
1347
1348/**
1349 * amdgpu_vm_add_prt_cb - add callback for updating the PRT status
1350 *
1351 * @adev: amdgpu_device pointer
1352 * @fence: fence for the callback
1353 */
1354static void amdgpu_vm_add_prt_cb(struct amdgpu_device *adev,
1355 struct dma_fence *fence)
1356{
1357 struct amdgpu_prt_cb *cb;
1358
1359 if (!adev->gmc.gmc_funcs->set_prt)
1360 return;
1361
1362 cb = kmalloc(sizeof(struct amdgpu_prt_cb), GFP_KERNEL);
1363 if (!cb) {
1364 /* Last resort when we are OOM */
1365 if (fence)
1366 dma_fence_wait(fence, false);
1367
1368 amdgpu_vm_prt_put(adev);
1369 } else {
1370 cb->adev = adev;
1371 if (!fence || dma_fence_add_callback(fence, &cb->cb,
1372 amdgpu_vm_prt_cb))
1373 amdgpu_vm_prt_cb(fence, &cb->cb);
1374 }
1375}
1376
1377/**
1378 * amdgpu_vm_free_mapping - free a mapping
1379 *
1380 * @adev: amdgpu_device pointer
1381 * @vm: requested vm
1382 * @mapping: mapping to be freed
1383 * @fence: fence of the unmap operation
1384 *
1385 * Free a mapping and make sure we decrease the PRT usage count if applicable.
1386 */
1387static void amdgpu_vm_free_mapping(struct amdgpu_device *adev,
1388 struct amdgpu_vm *vm,
1389 struct amdgpu_bo_va_mapping *mapping,
1390 struct dma_fence *fence)
1391{
1392 if (mapping->flags & AMDGPU_PTE_PRT_FLAG(adev))
1393 amdgpu_vm_add_prt_cb(adev, fence);
1394 kfree(mapping);
1395}
1396
1397/**
1398 * amdgpu_vm_prt_fini - finish all prt mappings
1399 *
1400 * @adev: amdgpu_device pointer
1401 * @vm: requested vm
1402 *
1403 * Register a cleanup callback to disable PRT support after VM dies.
1404 */
1405static void amdgpu_vm_prt_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm)
1406{
1407 struct dma_resv *resv = vm->root.bo->tbo.base.resv;
1408 struct dma_resv_iter cursor;
1409 struct dma_fence *fence;
1410
1411 dma_resv_for_each_fence(&cursor, resv, DMA_RESV_USAGE_BOOKKEEP, fence) {
1412 /* Add a callback for each fence in the reservation object */
1413 amdgpu_vm_prt_get(adev);
1414 amdgpu_vm_add_prt_cb(adev, fence);
1415 }
1416}
1417
1418/**
1419 * amdgpu_vm_clear_freed - clear freed BOs in the PT
1420 *
1421 * @adev: amdgpu_device pointer
1422 * @vm: requested vm
1423 * @fence: optional resulting fence (unchanged if no work needed to be done
1424 * or if an error occurred)
1425 *
1426 * Make sure all freed BOs are cleared in the PT.
1427 * PTs have to be reserved and mutex must be locked!
1428 *
1429 * Returns:
1430 * 0 for success.
1431 *
1432 */
1433int amdgpu_vm_clear_freed(struct amdgpu_device *adev,
1434 struct amdgpu_vm *vm,
1435 struct dma_fence **fence)
1436{
1437 struct amdgpu_bo_va_mapping *mapping;
1438 struct dma_fence *f = NULL;
1439 struct amdgpu_sync sync;
1440 int r;
1441
1442
1443 /*
1444 * Implicitly sync to command submissions in the same VM before
1445 * unmapping.
1446 */
1447 amdgpu_sync_create(&sync);
1448 r = amdgpu_sync_resv(adev, &sync, vm->root.bo->tbo.base.resv,
1449 AMDGPU_SYNC_EQ_OWNER, vm);
1450 if (r)
1451 goto error_free;
1452
1453 while (!list_empty(&vm->freed)) {
1454 mapping = list_first_entry(&vm->freed,
1455 struct amdgpu_bo_va_mapping, list);
1456 list_del(&mapping->list);
1457
1458 r = amdgpu_vm_update_range(adev, vm, false, false, true, false,
1459 &sync, mapping->start, mapping->last,
1460 0, 0, 0, NULL, NULL, &f);
1461 amdgpu_vm_free_mapping(adev, vm, mapping, f);
1462 if (r) {
1463 dma_fence_put(f);
1464 goto error_free;
1465 }
1466 }
1467
1468 if (fence && f) {
1469 dma_fence_put(*fence);
1470 *fence = f;
1471 } else {
1472 dma_fence_put(f);
1473 }
1474
1475error_free:
1476 amdgpu_sync_free(&sync);
1477 return r;
1478
1479}
1480
1481/**
1482 * amdgpu_vm_handle_moved - handle moved BOs in the PT
1483 *
1484 * @adev: amdgpu_device pointer
1485 * @vm: requested vm
1486 * @ticket: optional reservation ticket used to reserve the VM
1487 *
1488 * Make sure all BOs which are moved are updated in the PTs.
1489 *
1490 * Returns:
1491 * 0 for success.
1492 *
1493 * PTs have to be reserved!
1494 */
1495int amdgpu_vm_handle_moved(struct amdgpu_device *adev,
1496 struct amdgpu_vm *vm,
1497 struct ww_acquire_ctx *ticket)
1498{
1499 struct amdgpu_bo_va *bo_va;
1500 struct dma_resv *resv;
1501 bool clear, unlock;
1502 int r;
1503
1504 spin_lock(&vm->status_lock);
1505 while (!list_empty(&vm->moved)) {
1506 bo_va = list_first_entry(&vm->moved, struct amdgpu_bo_va,
1507 base.vm_status);
1508 spin_unlock(&vm->status_lock);
1509
1510 /* Per VM BOs never need to bo cleared in the page tables */
1511 r = amdgpu_vm_bo_update(adev, bo_va, false);
1512 if (r)
1513 return r;
1514 spin_lock(&vm->status_lock);
1515 }
1516
1517 while (!list_empty(&vm->invalidated)) {
1518 bo_va = list_first_entry(&vm->invalidated, struct amdgpu_bo_va,
1519 base.vm_status);
1520 resv = bo_va->base.bo->tbo.base.resv;
1521 spin_unlock(&vm->status_lock);
1522
1523 /* Try to reserve the BO to avoid clearing its ptes */
1524 if (!adev->debug_vm && dma_resv_trylock(resv)) {
1525 clear = false;
1526 unlock = true;
1527 /* The caller is already holding the reservation lock */
1528 } else if (ticket && dma_resv_locking_ctx(resv) == ticket) {
1529 clear = false;
1530 unlock = false;
1531 /* Somebody else is using the BO right now */
1532 } else {
1533 clear = true;
1534 unlock = false;
1535 }
1536
1537 r = amdgpu_vm_bo_update(adev, bo_va, clear);
1538
1539 if (unlock)
1540 dma_resv_unlock(resv);
1541 if (r)
1542 return r;
1543
1544 /* Remember evicted DMABuf imports in compute VMs for later
1545 * validation
1546 */
1547 if (vm->is_compute_context &&
1548 bo_va->base.bo->tbo.base.import_attach &&
1549 (!bo_va->base.bo->tbo.resource ||
1550 bo_va->base.bo->tbo.resource->mem_type == TTM_PL_SYSTEM))
1551 amdgpu_vm_bo_evicted_user(&bo_va->base);
1552
1553 spin_lock(&vm->status_lock);
1554 }
1555 spin_unlock(&vm->status_lock);
1556
1557 return 0;
1558}
1559
1560/**
1561 * amdgpu_vm_flush_compute_tlb - Flush TLB on compute VM
1562 *
1563 * @adev: amdgpu_device pointer
1564 * @vm: requested vm
1565 * @flush_type: flush type
1566 * @xcc_mask: mask of XCCs that belong to the compute partition in need of a TLB flush.
1567 *
1568 * Flush TLB if needed for a compute VM.
1569 *
1570 * Returns:
1571 * 0 for success.
1572 */
1573int amdgpu_vm_flush_compute_tlb(struct amdgpu_device *adev,
1574 struct amdgpu_vm *vm,
1575 uint32_t flush_type,
1576 uint32_t xcc_mask)
1577{
1578 uint64_t tlb_seq = amdgpu_vm_tlb_seq(vm);
1579 bool all_hub = false;
1580 int xcc = 0, r = 0;
1581
1582 WARN_ON_ONCE(!vm->is_compute_context);
1583
1584 /*
1585 * It can be that we race and lose here, but that is extremely unlikely
1586 * and the worst thing which could happen is that we flush the changes
1587 * into the TLB once more which is harmless.
1588 */
1589 if (atomic64_xchg(&vm->kfd_last_flushed_seq, tlb_seq) == tlb_seq)
1590 return 0;
1591
1592 if (adev->family == AMDGPU_FAMILY_AI ||
1593 adev->family == AMDGPU_FAMILY_RV)
1594 all_hub = true;
1595
1596 for_each_inst(xcc, xcc_mask) {
1597 r = amdgpu_gmc_flush_gpu_tlb_pasid(adev, vm->pasid, flush_type,
1598 all_hub, xcc);
1599 if (r)
1600 break;
1601 }
1602 return r;
1603}
1604
1605/**
1606 * amdgpu_vm_bo_add - add a bo to a specific vm
1607 *
1608 * @adev: amdgpu_device pointer
1609 * @vm: requested vm
1610 * @bo: amdgpu buffer object
1611 *
1612 * Add @bo into the requested vm.
1613 * Add @bo to the list of bos associated with the vm
1614 *
1615 * Returns:
1616 * Newly added bo_va or NULL for failure
1617 *
1618 * Object has to be reserved!
1619 */
1620struct amdgpu_bo_va *amdgpu_vm_bo_add(struct amdgpu_device *adev,
1621 struct amdgpu_vm *vm,
1622 struct amdgpu_bo *bo)
1623{
1624 struct amdgpu_bo_va *bo_va;
1625
1626 bo_va = kzalloc(sizeof(struct amdgpu_bo_va), GFP_KERNEL);
1627 if (bo_va == NULL) {
1628 return NULL;
1629 }
1630 amdgpu_vm_bo_base_init(&bo_va->base, vm, bo);
1631
1632 bo_va->ref_count = 1;
1633 bo_va->last_pt_update = dma_fence_get_stub();
1634 INIT_LIST_HEAD(&bo_va->valids);
1635 INIT_LIST_HEAD(&bo_va->invalids);
1636
1637 if (!bo)
1638 return bo_va;
1639
1640 dma_resv_assert_held(bo->tbo.base.resv);
1641 if (amdgpu_dmabuf_is_xgmi_accessible(adev, bo)) {
1642 bo_va->is_xgmi = true;
1643 /* Power up XGMI if it can be potentially used */
1644 amdgpu_xgmi_set_pstate(adev, AMDGPU_XGMI_PSTATE_MAX_VEGA20);
1645 }
1646
1647 return bo_va;
1648}
1649
1650
1651/**
1652 * amdgpu_vm_bo_insert_map - insert a new mapping
1653 *
1654 * @adev: amdgpu_device pointer
1655 * @bo_va: bo_va to store the address
1656 * @mapping: the mapping to insert
1657 *
1658 * Insert a new mapping into all structures.
1659 */
1660static void amdgpu_vm_bo_insert_map(struct amdgpu_device *adev,
1661 struct amdgpu_bo_va *bo_va,
1662 struct amdgpu_bo_va_mapping *mapping)
1663{
1664 struct amdgpu_vm *vm = bo_va->base.vm;
1665 struct amdgpu_bo *bo = bo_va->base.bo;
1666
1667 mapping->bo_va = bo_va;
1668 list_add(&mapping->list, &bo_va->invalids);
1669 amdgpu_vm_it_insert(mapping, &vm->va);
1670
1671 if (mapping->flags & AMDGPU_PTE_PRT_FLAG(adev))
1672 amdgpu_vm_prt_get(adev);
1673
1674 if (amdgpu_vm_is_bo_always_valid(vm, bo) && !bo_va->base.moved)
1675 amdgpu_vm_bo_moved(&bo_va->base);
1676
1677 trace_amdgpu_vm_bo_map(bo_va, mapping);
1678}
1679
1680/* Validate operation parameters to prevent potential abuse */
1681static int amdgpu_vm_verify_parameters(struct amdgpu_device *adev,
1682 struct amdgpu_bo *bo,
1683 uint64_t saddr,
1684 uint64_t offset,
1685 uint64_t size)
1686{
1687 uint64_t tmp, lpfn;
1688
1689 if (saddr & AMDGPU_GPU_PAGE_MASK
1690 || offset & AMDGPU_GPU_PAGE_MASK
1691 || size & AMDGPU_GPU_PAGE_MASK)
1692 return -EINVAL;
1693
1694 if (check_add_overflow(saddr, size, &tmp)
1695 || check_add_overflow(offset, size, &tmp)
1696 || size == 0 /* which also leads to end < begin */)
1697 return -EINVAL;
1698
1699 /* make sure object fit at this offset */
1700 if (bo && offset + size > amdgpu_bo_size(bo))
1701 return -EINVAL;
1702
1703 /* Ensure last pfn not exceed max_pfn */
1704 lpfn = (saddr + size - 1) >> AMDGPU_GPU_PAGE_SHIFT;
1705 if (lpfn >= adev->vm_manager.max_pfn)
1706 return -EINVAL;
1707
1708 return 0;
1709}
1710
1711/**
1712 * amdgpu_vm_bo_map - map bo inside a vm
1713 *
1714 * @adev: amdgpu_device pointer
1715 * @bo_va: bo_va to store the address
1716 * @saddr: where to map the BO
1717 * @offset: requested offset in the BO
1718 * @size: BO size in bytes
1719 * @flags: attributes of pages (read/write/valid/etc.)
1720 *
1721 * Add a mapping of the BO at the specefied addr into the VM.
1722 *
1723 * Returns:
1724 * 0 for success, error for failure.
1725 *
1726 * Object has to be reserved and unreserved outside!
1727 */
1728int amdgpu_vm_bo_map(struct amdgpu_device *adev,
1729 struct amdgpu_bo_va *bo_va,
1730 uint64_t saddr, uint64_t offset,
1731 uint64_t size, uint64_t flags)
1732{
1733 struct amdgpu_bo_va_mapping *mapping, *tmp;
1734 struct amdgpu_bo *bo = bo_va->base.bo;
1735 struct amdgpu_vm *vm = bo_va->base.vm;
1736 uint64_t eaddr;
1737 int r;
1738
1739 r = amdgpu_vm_verify_parameters(adev, bo, saddr, offset, size);
1740 if (r)
1741 return r;
1742
1743 saddr /= AMDGPU_GPU_PAGE_SIZE;
1744 eaddr = saddr + (size - 1) / AMDGPU_GPU_PAGE_SIZE;
1745
1746 tmp = amdgpu_vm_it_iter_first(&vm->va, saddr, eaddr);
1747 if (tmp) {
1748 /* bo and tmp overlap, invalid addr */
1749 dev_err(adev->dev, "bo %p va 0x%010Lx-0x%010Lx conflict with "
1750 "0x%010Lx-0x%010Lx\n", bo, saddr, eaddr,
1751 tmp->start, tmp->last + 1);
1752 return -EINVAL;
1753 }
1754
1755 mapping = kmalloc(sizeof(*mapping), GFP_KERNEL);
1756 if (!mapping)
1757 return -ENOMEM;
1758
1759 mapping->start = saddr;
1760 mapping->last = eaddr;
1761 mapping->offset = offset;
1762 mapping->flags = flags;
1763
1764 amdgpu_vm_bo_insert_map(adev, bo_va, mapping);
1765
1766 return 0;
1767}
1768
1769/**
1770 * amdgpu_vm_bo_replace_map - map bo inside a vm, replacing existing mappings
1771 *
1772 * @adev: amdgpu_device pointer
1773 * @bo_va: bo_va to store the address
1774 * @saddr: where to map the BO
1775 * @offset: requested offset in the BO
1776 * @size: BO size in bytes
1777 * @flags: attributes of pages (read/write/valid/etc.)
1778 *
1779 * Add a mapping of the BO at the specefied addr into the VM. Replace existing
1780 * mappings as we do so.
1781 *
1782 * Returns:
1783 * 0 for success, error for failure.
1784 *
1785 * Object has to be reserved and unreserved outside!
1786 */
1787int amdgpu_vm_bo_replace_map(struct amdgpu_device *adev,
1788 struct amdgpu_bo_va *bo_va,
1789 uint64_t saddr, uint64_t offset,
1790 uint64_t size, uint64_t flags)
1791{
1792 struct amdgpu_bo_va_mapping *mapping;
1793 struct amdgpu_bo *bo = bo_va->base.bo;
1794 uint64_t eaddr;
1795 int r;
1796
1797 r = amdgpu_vm_verify_parameters(adev, bo, saddr, offset, size);
1798 if (r)
1799 return r;
1800
1801 /* Allocate all the needed memory */
1802 mapping = kmalloc(sizeof(*mapping), GFP_KERNEL);
1803 if (!mapping)
1804 return -ENOMEM;
1805
1806 r = amdgpu_vm_bo_clear_mappings(adev, bo_va->base.vm, saddr, size);
1807 if (r) {
1808 kfree(mapping);
1809 return r;
1810 }
1811
1812 saddr /= AMDGPU_GPU_PAGE_SIZE;
1813 eaddr = saddr + (size - 1) / AMDGPU_GPU_PAGE_SIZE;
1814
1815 mapping->start = saddr;
1816 mapping->last = eaddr;
1817 mapping->offset = offset;
1818 mapping->flags = flags;
1819
1820 amdgpu_vm_bo_insert_map(adev, bo_va, mapping);
1821
1822 return 0;
1823}
1824
1825/**
1826 * amdgpu_vm_bo_unmap - remove bo mapping from vm
1827 *
1828 * @adev: amdgpu_device pointer
1829 * @bo_va: bo_va to remove the address from
1830 * @saddr: where to the BO is mapped
1831 *
1832 * Remove a mapping of the BO at the specefied addr from the VM.
1833 *
1834 * Returns:
1835 * 0 for success, error for failure.
1836 *
1837 * Object has to be reserved and unreserved outside!
1838 */
1839int amdgpu_vm_bo_unmap(struct amdgpu_device *adev,
1840 struct amdgpu_bo_va *bo_va,
1841 uint64_t saddr)
1842{
1843 struct amdgpu_bo_va_mapping *mapping;
1844 struct amdgpu_vm *vm = bo_va->base.vm;
1845 bool valid = true;
1846
1847 saddr /= AMDGPU_GPU_PAGE_SIZE;
1848
1849 list_for_each_entry(mapping, &bo_va->valids, list) {
1850 if (mapping->start == saddr)
1851 break;
1852 }
1853
1854 if (&mapping->list == &bo_va->valids) {
1855 valid = false;
1856
1857 list_for_each_entry(mapping, &bo_va->invalids, list) {
1858 if (mapping->start == saddr)
1859 break;
1860 }
1861
1862 if (&mapping->list == &bo_va->invalids)
1863 return -ENOENT;
1864 }
1865
1866 list_del(&mapping->list);
1867 amdgpu_vm_it_remove(mapping, &vm->va);
1868 mapping->bo_va = NULL;
1869 trace_amdgpu_vm_bo_unmap(bo_va, mapping);
1870
1871 if (valid)
1872 list_add(&mapping->list, &vm->freed);
1873 else
1874 amdgpu_vm_free_mapping(adev, vm, mapping,
1875 bo_va->last_pt_update);
1876
1877 return 0;
1878}
1879
1880/**
1881 * amdgpu_vm_bo_clear_mappings - remove all mappings in a specific range
1882 *
1883 * @adev: amdgpu_device pointer
1884 * @vm: VM structure to use
1885 * @saddr: start of the range
1886 * @size: size of the range
1887 *
1888 * Remove all mappings in a range, split them as appropriate.
1889 *
1890 * Returns:
1891 * 0 for success, error for failure.
1892 */
1893int amdgpu_vm_bo_clear_mappings(struct amdgpu_device *adev,
1894 struct amdgpu_vm *vm,
1895 uint64_t saddr, uint64_t size)
1896{
1897 struct amdgpu_bo_va_mapping *before, *after, *tmp, *next;
1898 LIST_HEAD(removed);
1899 uint64_t eaddr;
1900 int r;
1901
1902 r = amdgpu_vm_verify_parameters(adev, NULL, saddr, 0, size);
1903 if (r)
1904 return r;
1905
1906 saddr /= AMDGPU_GPU_PAGE_SIZE;
1907 eaddr = saddr + (size - 1) / AMDGPU_GPU_PAGE_SIZE;
1908
1909 /* Allocate all the needed memory */
1910 before = kzalloc(sizeof(*before), GFP_KERNEL);
1911 if (!before)
1912 return -ENOMEM;
1913 INIT_LIST_HEAD(&before->list);
1914
1915 after = kzalloc(sizeof(*after), GFP_KERNEL);
1916 if (!after) {
1917 kfree(before);
1918 return -ENOMEM;
1919 }
1920 INIT_LIST_HEAD(&after->list);
1921
1922 /* Now gather all removed mappings */
1923 tmp = amdgpu_vm_it_iter_first(&vm->va, saddr, eaddr);
1924 while (tmp) {
1925 /* Remember mapping split at the start */
1926 if (tmp->start < saddr) {
1927 before->start = tmp->start;
1928 before->last = saddr - 1;
1929 before->offset = tmp->offset;
1930 before->flags = tmp->flags;
1931 before->bo_va = tmp->bo_va;
1932 list_add(&before->list, &tmp->bo_va->invalids);
1933 }
1934
1935 /* Remember mapping split at the end */
1936 if (tmp->last > eaddr) {
1937 after->start = eaddr + 1;
1938 after->last = tmp->last;
1939 after->offset = tmp->offset;
1940 after->offset += (after->start - tmp->start) << PAGE_SHIFT;
1941 after->flags = tmp->flags;
1942 after->bo_va = tmp->bo_va;
1943 list_add(&after->list, &tmp->bo_va->invalids);
1944 }
1945
1946 list_del(&tmp->list);
1947 list_add(&tmp->list, &removed);
1948
1949 tmp = amdgpu_vm_it_iter_next(tmp, saddr, eaddr);
1950 }
1951
1952 /* And free them up */
1953 list_for_each_entry_safe(tmp, next, &removed, list) {
1954 amdgpu_vm_it_remove(tmp, &vm->va);
1955 list_del(&tmp->list);
1956
1957 if (tmp->start < saddr)
1958 tmp->start = saddr;
1959 if (tmp->last > eaddr)
1960 tmp->last = eaddr;
1961
1962 tmp->bo_va = NULL;
1963 list_add(&tmp->list, &vm->freed);
1964 trace_amdgpu_vm_bo_unmap(NULL, tmp);
1965 }
1966
1967 /* Insert partial mapping before the range */
1968 if (!list_empty(&before->list)) {
1969 struct amdgpu_bo *bo = before->bo_va->base.bo;
1970
1971 amdgpu_vm_it_insert(before, &vm->va);
1972 if (before->flags & AMDGPU_PTE_PRT_FLAG(adev))
1973 amdgpu_vm_prt_get(adev);
1974
1975 if (amdgpu_vm_is_bo_always_valid(vm, bo) &&
1976 !before->bo_va->base.moved)
1977 amdgpu_vm_bo_moved(&before->bo_va->base);
1978 } else {
1979 kfree(before);
1980 }
1981
1982 /* Insert partial mapping after the range */
1983 if (!list_empty(&after->list)) {
1984 struct amdgpu_bo *bo = after->bo_va->base.bo;
1985
1986 amdgpu_vm_it_insert(after, &vm->va);
1987 if (after->flags & AMDGPU_PTE_PRT_FLAG(adev))
1988 amdgpu_vm_prt_get(adev);
1989
1990 if (amdgpu_vm_is_bo_always_valid(vm, bo) &&
1991 !after->bo_va->base.moved)
1992 amdgpu_vm_bo_moved(&after->bo_va->base);
1993 } else {
1994 kfree(after);
1995 }
1996
1997 return 0;
1998}
1999
2000/**
2001 * amdgpu_vm_bo_lookup_mapping - find mapping by address
2002 *
2003 * @vm: the requested VM
2004 * @addr: the address
2005 *
2006 * Find a mapping by it's address.
2007 *
2008 * Returns:
2009 * The amdgpu_bo_va_mapping matching for addr or NULL
2010 *
2011 */
2012struct amdgpu_bo_va_mapping *amdgpu_vm_bo_lookup_mapping(struct amdgpu_vm *vm,
2013 uint64_t addr)
2014{
2015 return amdgpu_vm_it_iter_first(&vm->va, addr, addr);
2016}
2017
2018/**
2019 * amdgpu_vm_bo_trace_cs - trace all reserved mappings
2020 *
2021 * @vm: the requested vm
2022 * @ticket: CS ticket
2023 *
2024 * Trace all mappings of BOs reserved during a command submission.
2025 */
2026void amdgpu_vm_bo_trace_cs(struct amdgpu_vm *vm, struct ww_acquire_ctx *ticket)
2027{
2028 struct amdgpu_bo_va_mapping *mapping;
2029
2030 if (!trace_amdgpu_vm_bo_cs_enabled())
2031 return;
2032
2033 for (mapping = amdgpu_vm_it_iter_first(&vm->va, 0, U64_MAX); mapping;
2034 mapping = amdgpu_vm_it_iter_next(mapping, 0, U64_MAX)) {
2035 if (mapping->bo_va && mapping->bo_va->base.bo) {
2036 struct amdgpu_bo *bo;
2037
2038 bo = mapping->bo_va->base.bo;
2039 if (dma_resv_locking_ctx(bo->tbo.base.resv) !=
2040 ticket)
2041 continue;
2042 }
2043
2044 trace_amdgpu_vm_bo_cs(mapping);
2045 }
2046}
2047
2048/**
2049 * amdgpu_vm_bo_del - remove a bo from a specific vm
2050 *
2051 * @adev: amdgpu_device pointer
2052 * @bo_va: requested bo_va
2053 *
2054 * Remove @bo_va->bo from the requested vm.
2055 *
2056 * Object have to be reserved!
2057 */
2058void amdgpu_vm_bo_del(struct amdgpu_device *adev,
2059 struct amdgpu_bo_va *bo_va)
2060{
2061 struct amdgpu_bo_va_mapping *mapping, *next;
2062 struct amdgpu_bo *bo = bo_va->base.bo;
2063 struct amdgpu_vm *vm = bo_va->base.vm;
2064 struct amdgpu_vm_bo_base **base;
2065
2066 dma_resv_assert_held(vm->root.bo->tbo.base.resv);
2067
2068 if (bo) {
2069 dma_resv_assert_held(bo->tbo.base.resv);
2070 if (amdgpu_vm_is_bo_always_valid(vm, bo))
2071 ttm_bo_set_bulk_move(&bo->tbo, NULL);
2072
2073 for (base = &bo_va->base.bo->vm_bo; *base;
2074 base = &(*base)->next) {
2075 if (*base != &bo_va->base)
2076 continue;
2077
2078 *base = bo_va->base.next;
2079 break;
2080 }
2081 }
2082
2083 spin_lock(&vm->status_lock);
2084 list_del(&bo_va->base.vm_status);
2085 spin_unlock(&vm->status_lock);
2086
2087 list_for_each_entry_safe(mapping, next, &bo_va->valids, list) {
2088 list_del(&mapping->list);
2089 amdgpu_vm_it_remove(mapping, &vm->va);
2090 mapping->bo_va = NULL;
2091 trace_amdgpu_vm_bo_unmap(bo_va, mapping);
2092 list_add(&mapping->list, &vm->freed);
2093 }
2094 list_for_each_entry_safe(mapping, next, &bo_va->invalids, list) {
2095 list_del(&mapping->list);
2096 amdgpu_vm_it_remove(mapping, &vm->va);
2097 amdgpu_vm_free_mapping(adev, vm, mapping,
2098 bo_va->last_pt_update);
2099 }
2100
2101 dma_fence_put(bo_va->last_pt_update);
2102
2103 if (bo && bo_va->is_xgmi)
2104 amdgpu_xgmi_set_pstate(adev, AMDGPU_XGMI_PSTATE_MIN);
2105
2106 kfree(bo_va);
2107}
2108
2109/**
2110 * amdgpu_vm_evictable - check if we can evict a VM
2111 *
2112 * @bo: A page table of the VM.
2113 *
2114 * Check if it is possible to evict a VM.
2115 */
2116bool amdgpu_vm_evictable(struct amdgpu_bo *bo)
2117{
2118 struct amdgpu_vm_bo_base *bo_base = bo->vm_bo;
2119
2120 /* Page tables of a destroyed VM can go away immediately */
2121 if (!bo_base || !bo_base->vm)
2122 return true;
2123
2124 /* Don't evict VM page tables while they are busy */
2125 if (!dma_resv_test_signaled(bo->tbo.base.resv, DMA_RESV_USAGE_BOOKKEEP))
2126 return false;
2127
2128 /* Try to block ongoing updates */
2129 if (!amdgpu_vm_eviction_trylock(bo_base->vm))
2130 return false;
2131
2132 /* Don't evict VM page tables while they are updated */
2133 if (!dma_fence_is_signaled(bo_base->vm->last_unlocked)) {
2134 amdgpu_vm_eviction_unlock(bo_base->vm);
2135 return false;
2136 }
2137
2138 bo_base->vm->evicting = true;
2139 amdgpu_vm_eviction_unlock(bo_base->vm);
2140 return true;
2141}
2142
2143/**
2144 * amdgpu_vm_bo_invalidate - mark the bo as invalid
2145 *
2146 * @adev: amdgpu_device pointer
2147 * @bo: amdgpu buffer object
2148 * @evicted: is the BO evicted
2149 *
2150 * Mark @bo as invalid.
2151 */
2152void amdgpu_vm_bo_invalidate(struct amdgpu_device *adev,
2153 struct amdgpu_bo *bo, bool evicted)
2154{
2155 struct amdgpu_vm_bo_base *bo_base;
2156
2157 for (bo_base = bo->vm_bo; bo_base; bo_base = bo_base->next) {
2158 struct amdgpu_vm *vm = bo_base->vm;
2159
2160 if (evicted && amdgpu_vm_is_bo_always_valid(vm, bo)) {
2161 amdgpu_vm_bo_evicted(bo_base);
2162 continue;
2163 }
2164
2165 if (bo_base->moved)
2166 continue;
2167 bo_base->moved = true;
2168
2169 if (bo->tbo.type == ttm_bo_type_kernel)
2170 amdgpu_vm_bo_relocated(bo_base);
2171 else if (amdgpu_vm_is_bo_always_valid(vm, bo))
2172 amdgpu_vm_bo_moved(bo_base);
2173 else
2174 amdgpu_vm_bo_invalidated(bo_base);
2175 }
2176}
2177
2178/**
2179 * amdgpu_vm_get_block_size - calculate VM page table size as power of two
2180 *
2181 * @vm_size: VM size
2182 *
2183 * Returns:
2184 * VM page table as power of two
2185 */
2186static uint32_t amdgpu_vm_get_block_size(uint64_t vm_size)
2187{
2188 /* Total bits covered by PD + PTs */
2189 unsigned bits = ilog2(vm_size) + 18;
2190
2191 /* Make sure the PD is 4K in size up to 8GB address space.
2192 Above that split equal between PD and PTs */
2193 if (vm_size <= 8)
2194 return (bits - 9);
2195 else
2196 return ((bits + 3) / 2);
2197}
2198
2199/**
2200 * amdgpu_vm_adjust_size - adjust vm size, block size and fragment size
2201 *
2202 * @adev: amdgpu_device pointer
2203 * @min_vm_size: the minimum vm size in GB if it's set auto
2204 * @fragment_size_default: Default PTE fragment size
2205 * @max_level: max VMPT level
2206 * @max_bits: max address space size in bits
2207 *
2208 */
2209void amdgpu_vm_adjust_size(struct amdgpu_device *adev, uint32_t min_vm_size,
2210 uint32_t fragment_size_default, unsigned max_level,
2211 unsigned max_bits)
2212{
2213 unsigned int max_size = 1 << (max_bits - 30);
2214 unsigned int vm_size;
2215 uint64_t tmp;
2216
2217 /* adjust vm size first */
2218 if (amdgpu_vm_size != -1) {
2219 vm_size = amdgpu_vm_size;
2220 if (vm_size > max_size) {
2221 dev_warn(adev->dev, "VM size (%d) too large, max is %u GB\n",
2222 amdgpu_vm_size, max_size);
2223 vm_size = max_size;
2224 }
2225 } else {
2226 struct sysinfo si;
2227 unsigned int phys_ram_gb;
2228
2229 /* Optimal VM size depends on the amount of physical
2230 * RAM available. Underlying requirements and
2231 * assumptions:
2232 *
2233 * - Need to map system memory and VRAM from all GPUs
2234 * - VRAM from other GPUs not known here
2235 * - Assume VRAM <= system memory
2236 * - On GFX8 and older, VM space can be segmented for
2237 * different MTYPEs
2238 * - Need to allow room for fragmentation, guard pages etc.
2239 *
2240 * This adds up to a rough guess of system memory x3.
2241 * Round up to power of two to maximize the available
2242 * VM size with the given page table size.
2243 */
2244 si_meminfo(&si);
2245 phys_ram_gb = ((uint64_t)si.totalram * si.mem_unit +
2246 (1 << 30) - 1) >> 30;
2247 vm_size = roundup_pow_of_two(
2248 clamp(phys_ram_gb * 3, min_vm_size, max_size));
2249 }
2250
2251 adev->vm_manager.max_pfn = (uint64_t)vm_size << 18;
2252
2253 tmp = roundup_pow_of_two(adev->vm_manager.max_pfn);
2254 if (amdgpu_vm_block_size != -1)
2255 tmp >>= amdgpu_vm_block_size - 9;
2256 tmp = DIV_ROUND_UP(fls64(tmp) - 1, 9) - 1;
2257 adev->vm_manager.num_level = min_t(unsigned int, max_level, tmp);
2258 switch (adev->vm_manager.num_level) {
2259 case 3:
2260 adev->vm_manager.root_level = AMDGPU_VM_PDB2;
2261 break;
2262 case 2:
2263 adev->vm_manager.root_level = AMDGPU_VM_PDB1;
2264 break;
2265 case 1:
2266 adev->vm_manager.root_level = AMDGPU_VM_PDB0;
2267 break;
2268 default:
2269 dev_err(adev->dev, "VMPT only supports 2~4+1 levels\n");
2270 }
2271 /* block size depends on vm size and hw setup*/
2272 if (amdgpu_vm_block_size != -1)
2273 adev->vm_manager.block_size =
2274 min((unsigned)amdgpu_vm_block_size, max_bits
2275 - AMDGPU_GPU_PAGE_SHIFT
2276 - 9 * adev->vm_manager.num_level);
2277 else if (adev->vm_manager.num_level > 1)
2278 adev->vm_manager.block_size = 9;
2279 else
2280 adev->vm_manager.block_size = amdgpu_vm_get_block_size(tmp);
2281
2282 if (amdgpu_vm_fragment_size == -1)
2283 adev->vm_manager.fragment_size = fragment_size_default;
2284 else
2285 adev->vm_manager.fragment_size = amdgpu_vm_fragment_size;
2286
2287 DRM_INFO("vm size is %u GB, %u levels, block size is %u-bit, fragment size is %u-bit\n",
2288 vm_size, adev->vm_manager.num_level + 1,
2289 adev->vm_manager.block_size,
2290 adev->vm_manager.fragment_size);
2291}
2292
2293/**
2294 * amdgpu_vm_wait_idle - wait for the VM to become idle
2295 *
2296 * @vm: VM object to wait for
2297 * @timeout: timeout to wait for VM to become idle
2298 */
2299long amdgpu_vm_wait_idle(struct amdgpu_vm *vm, long timeout)
2300{
2301 timeout = dma_resv_wait_timeout(vm->root.bo->tbo.base.resv,
2302 DMA_RESV_USAGE_BOOKKEEP,
2303 true, timeout);
2304 if (timeout <= 0)
2305 return timeout;
2306
2307 return dma_fence_wait_timeout(vm->last_unlocked, true, timeout);
2308}
2309
2310static void amdgpu_vm_destroy_task_info(struct kref *kref)
2311{
2312 struct amdgpu_task_info *ti = container_of(kref, struct amdgpu_task_info, refcount);
2313
2314 kfree(ti);
2315}
2316
2317static inline struct amdgpu_vm *
2318amdgpu_vm_get_vm_from_pasid(struct amdgpu_device *adev, u32 pasid)
2319{
2320 struct amdgpu_vm *vm;
2321 unsigned long flags;
2322
2323 xa_lock_irqsave(&adev->vm_manager.pasids, flags);
2324 vm = xa_load(&adev->vm_manager.pasids, pasid);
2325 xa_unlock_irqrestore(&adev->vm_manager.pasids, flags);
2326
2327 return vm;
2328}
2329
2330/**
2331 * amdgpu_vm_put_task_info - reference down the vm task_info ptr
2332 *
2333 * @task_info: task_info struct under discussion.
2334 *
2335 * frees the vm task_info ptr at the last put
2336 */
2337void amdgpu_vm_put_task_info(struct amdgpu_task_info *task_info)
2338{
2339 kref_put(&task_info->refcount, amdgpu_vm_destroy_task_info);
2340}
2341
2342/**
2343 * amdgpu_vm_get_task_info_vm - Extracts task info for a vm.
2344 *
2345 * @vm: VM to get info from
2346 *
2347 * Returns the reference counted task_info structure, which must be
2348 * referenced down with amdgpu_vm_put_task_info.
2349 */
2350struct amdgpu_task_info *
2351amdgpu_vm_get_task_info_vm(struct amdgpu_vm *vm)
2352{
2353 struct amdgpu_task_info *ti = NULL;
2354
2355 if (vm) {
2356 ti = vm->task_info;
2357 kref_get(&vm->task_info->refcount);
2358 }
2359
2360 return ti;
2361}
2362
2363/**
2364 * amdgpu_vm_get_task_info_pasid - Extracts task info for a PASID.
2365 *
2366 * @adev: drm device pointer
2367 * @pasid: PASID identifier for VM
2368 *
2369 * Returns the reference counted task_info structure, which must be
2370 * referenced down with amdgpu_vm_put_task_info.
2371 */
2372struct amdgpu_task_info *
2373amdgpu_vm_get_task_info_pasid(struct amdgpu_device *adev, u32 pasid)
2374{
2375 return amdgpu_vm_get_task_info_vm(
2376 amdgpu_vm_get_vm_from_pasid(adev, pasid));
2377}
2378
2379static int amdgpu_vm_create_task_info(struct amdgpu_vm *vm)
2380{
2381 vm->task_info = kzalloc(sizeof(struct amdgpu_task_info), GFP_KERNEL);
2382 if (!vm->task_info)
2383 return -ENOMEM;
2384
2385 kref_init(&vm->task_info->refcount);
2386 return 0;
2387}
2388
2389/**
2390 * amdgpu_vm_set_task_info - Sets VMs task info.
2391 *
2392 * @vm: vm for which to set the info
2393 */
2394void amdgpu_vm_set_task_info(struct amdgpu_vm *vm)
2395{
2396 if (!vm->task_info)
2397 return;
2398
2399 if (vm->task_info->pid == current->pid)
2400 return;
2401
2402 vm->task_info->pid = current->pid;
2403 get_task_comm(vm->task_info->task_name, current);
2404
2405 if (current->group_leader->mm != current->mm)
2406 return;
2407
2408 vm->task_info->tgid = current->group_leader->pid;
2409 get_task_comm(vm->task_info->process_name, current->group_leader);
2410}
2411
2412/**
2413 * amdgpu_vm_init - initialize a vm instance
2414 *
2415 * @adev: amdgpu_device pointer
2416 * @vm: requested vm
2417 * @xcp_id: GPU partition selection id
2418 *
2419 * Init @vm fields.
2420 *
2421 * Returns:
2422 * 0 for success, error for failure.
2423 */
2424int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm,
2425 int32_t xcp_id)
2426{
2427 struct amdgpu_bo *root_bo;
2428 struct amdgpu_bo_vm *root;
2429 int r, i;
2430
2431 vm->va = RB_ROOT_CACHED;
2432 for (i = 0; i < AMDGPU_MAX_VMHUBS; i++)
2433 vm->reserved_vmid[i] = NULL;
2434 INIT_LIST_HEAD(&vm->evicted);
2435 INIT_LIST_HEAD(&vm->evicted_user);
2436 INIT_LIST_HEAD(&vm->relocated);
2437 INIT_LIST_HEAD(&vm->moved);
2438 INIT_LIST_HEAD(&vm->idle);
2439 INIT_LIST_HEAD(&vm->invalidated);
2440 spin_lock_init(&vm->status_lock);
2441 INIT_LIST_HEAD(&vm->freed);
2442 INIT_LIST_HEAD(&vm->done);
2443 INIT_LIST_HEAD(&vm->pt_freed);
2444 INIT_WORK(&vm->pt_free_work, amdgpu_vm_pt_free_work);
2445 INIT_KFIFO(vm->faults);
2446
2447 r = amdgpu_vm_init_entities(adev, vm);
2448 if (r)
2449 return r;
2450
2451 ttm_lru_bulk_move_init(&vm->lru_bulk_move);
2452
2453 vm->is_compute_context = false;
2454
2455 vm->use_cpu_for_update = !!(adev->vm_manager.vm_update_mode &
2456 AMDGPU_VM_USE_CPU_FOR_GFX);
2457
2458 DRM_DEBUG_DRIVER("VM update mode is %s\n",
2459 vm->use_cpu_for_update ? "CPU" : "SDMA");
2460 WARN_ONCE((vm->use_cpu_for_update &&
2461 !amdgpu_gmc_vram_full_visible(&adev->gmc)),
2462 "CPU update of VM recommended only for large BAR system\n");
2463
2464 if (vm->use_cpu_for_update)
2465 vm->update_funcs = &amdgpu_vm_cpu_funcs;
2466 else
2467 vm->update_funcs = &amdgpu_vm_sdma_funcs;
2468
2469 vm->last_update = dma_fence_get_stub();
2470 vm->last_unlocked = dma_fence_get_stub();
2471 vm->last_tlb_flush = dma_fence_get_stub();
2472 vm->generation = amdgpu_vm_generation(adev, NULL);
2473
2474 mutex_init(&vm->eviction_lock);
2475 vm->evicting = false;
2476 vm->tlb_fence_context = dma_fence_context_alloc(1);
2477
2478 r = amdgpu_vm_pt_create(adev, vm, adev->vm_manager.root_level,
2479 false, &root, xcp_id);
2480 if (r)
2481 goto error_free_delayed;
2482
2483 root_bo = amdgpu_bo_ref(&root->bo);
2484 r = amdgpu_bo_reserve(root_bo, true);
2485 if (r) {
2486 amdgpu_bo_unref(&root_bo);
2487 goto error_free_delayed;
2488 }
2489
2490 amdgpu_vm_bo_base_init(&vm->root, vm, root_bo);
2491 r = dma_resv_reserve_fences(root_bo->tbo.base.resv, 1);
2492 if (r)
2493 goto error_free_root;
2494
2495 r = amdgpu_vm_pt_clear(adev, vm, root, false);
2496 if (r)
2497 goto error_free_root;
2498
2499 r = amdgpu_vm_create_task_info(vm);
2500 if (r)
2501 DRM_DEBUG("Failed to create task info for VM\n");
2502
2503 amdgpu_bo_unreserve(vm->root.bo);
2504 amdgpu_bo_unref(&root_bo);
2505
2506 return 0;
2507
2508error_free_root:
2509 amdgpu_vm_pt_free_root(adev, vm);
2510 amdgpu_bo_unreserve(vm->root.bo);
2511 amdgpu_bo_unref(&root_bo);
2512
2513error_free_delayed:
2514 dma_fence_put(vm->last_tlb_flush);
2515 dma_fence_put(vm->last_unlocked);
2516 ttm_lru_bulk_move_fini(&adev->mman.bdev, &vm->lru_bulk_move);
2517 amdgpu_vm_fini_entities(vm);
2518
2519 return r;
2520}
2521
2522/**
2523 * amdgpu_vm_make_compute - Turn a GFX VM into a compute VM
2524 *
2525 * @adev: amdgpu_device pointer
2526 * @vm: requested vm
2527 *
2528 * This only works on GFX VMs that don't have any BOs added and no
2529 * page tables allocated yet.
2530 *
2531 * Changes the following VM parameters:
2532 * - use_cpu_for_update
2533 * - pte_supports_ats
2534 *
2535 * Reinitializes the page directory to reflect the changed ATS
2536 * setting.
2537 *
2538 * Returns:
2539 * 0 for success, -errno for errors.
2540 */
2541int amdgpu_vm_make_compute(struct amdgpu_device *adev, struct amdgpu_vm *vm)
2542{
2543 int r;
2544
2545 r = amdgpu_bo_reserve(vm->root.bo, true);
2546 if (r)
2547 return r;
2548
2549 /* Update VM state */
2550 vm->use_cpu_for_update = !!(adev->vm_manager.vm_update_mode &
2551 AMDGPU_VM_USE_CPU_FOR_COMPUTE);
2552 DRM_DEBUG_DRIVER("VM update mode is %s\n",
2553 vm->use_cpu_for_update ? "CPU" : "SDMA");
2554 WARN_ONCE((vm->use_cpu_for_update &&
2555 !amdgpu_gmc_vram_full_visible(&adev->gmc)),
2556 "CPU update of VM recommended only for large BAR system\n");
2557
2558 if (vm->use_cpu_for_update) {
2559 /* Sync with last SDMA update/clear before switching to CPU */
2560 r = amdgpu_bo_sync_wait(vm->root.bo,
2561 AMDGPU_FENCE_OWNER_UNDEFINED, true);
2562 if (r)
2563 goto unreserve_bo;
2564
2565 vm->update_funcs = &amdgpu_vm_cpu_funcs;
2566 r = amdgpu_vm_pt_map_tables(adev, vm);
2567 if (r)
2568 goto unreserve_bo;
2569
2570 } else {
2571 vm->update_funcs = &amdgpu_vm_sdma_funcs;
2572 }
2573
2574 dma_fence_put(vm->last_update);
2575 vm->last_update = dma_fence_get_stub();
2576 vm->is_compute_context = true;
2577
2578unreserve_bo:
2579 amdgpu_bo_unreserve(vm->root.bo);
2580 return r;
2581}
2582
2583/**
2584 * amdgpu_vm_release_compute - release a compute vm
2585 * @adev: amdgpu_device pointer
2586 * @vm: a vm turned into compute vm by calling amdgpu_vm_make_compute
2587 *
2588 * This is a correspondant of amdgpu_vm_make_compute. It decouples compute
2589 * pasid from vm. Compute should stop use of vm after this call.
2590 */
2591void amdgpu_vm_release_compute(struct amdgpu_device *adev, struct amdgpu_vm *vm)
2592{
2593 amdgpu_vm_set_pasid(adev, vm, 0);
2594 vm->is_compute_context = false;
2595}
2596
2597/**
2598 * amdgpu_vm_fini - tear down a vm instance
2599 *
2600 * @adev: amdgpu_device pointer
2601 * @vm: requested vm
2602 *
2603 * Tear down @vm.
2604 * Unbind the VM and remove all bos from the vm bo list
2605 */
2606void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm)
2607{
2608 struct amdgpu_bo_va_mapping *mapping, *tmp;
2609 bool prt_fini_needed = !!adev->gmc.gmc_funcs->set_prt;
2610 struct amdgpu_bo *root;
2611 unsigned long flags;
2612 int i;
2613
2614 amdgpu_amdkfd_gpuvm_destroy_cb(adev, vm);
2615
2616 flush_work(&vm->pt_free_work);
2617
2618 root = amdgpu_bo_ref(vm->root.bo);
2619 amdgpu_bo_reserve(root, true);
2620 amdgpu_vm_put_task_info(vm->task_info);
2621 amdgpu_vm_set_pasid(adev, vm, 0);
2622 dma_fence_wait(vm->last_unlocked, false);
2623 dma_fence_put(vm->last_unlocked);
2624 dma_fence_wait(vm->last_tlb_flush, false);
2625 /* Make sure that all fence callbacks have completed */
2626 spin_lock_irqsave(vm->last_tlb_flush->lock, flags);
2627 spin_unlock_irqrestore(vm->last_tlb_flush->lock, flags);
2628 dma_fence_put(vm->last_tlb_flush);
2629
2630 list_for_each_entry_safe(mapping, tmp, &vm->freed, list) {
2631 if (mapping->flags & AMDGPU_PTE_PRT_FLAG(adev) && prt_fini_needed) {
2632 amdgpu_vm_prt_fini(adev, vm);
2633 prt_fini_needed = false;
2634 }
2635
2636 list_del(&mapping->list);
2637 amdgpu_vm_free_mapping(adev, vm, mapping, NULL);
2638 }
2639
2640 amdgpu_vm_pt_free_root(adev, vm);
2641 amdgpu_bo_unreserve(root);
2642 amdgpu_bo_unref(&root);
2643 WARN_ON(vm->root.bo);
2644
2645 amdgpu_vm_fini_entities(vm);
2646
2647 if (!RB_EMPTY_ROOT(&vm->va.rb_root)) {
2648 dev_err(adev->dev, "still active bo inside vm\n");
2649 }
2650 rbtree_postorder_for_each_entry_safe(mapping, tmp,
2651 &vm->va.rb_root, rb) {
2652 /* Don't remove the mapping here, we don't want to trigger a
2653 * rebalance and the tree is about to be destroyed anyway.
2654 */
2655 list_del(&mapping->list);
2656 kfree(mapping);
2657 }
2658
2659 dma_fence_put(vm->last_update);
2660
2661 for (i = 0; i < AMDGPU_MAX_VMHUBS; i++) {
2662 if (vm->reserved_vmid[i]) {
2663 amdgpu_vmid_free_reserved(adev, i);
2664 vm->reserved_vmid[i] = false;
2665 }
2666 }
2667
2668 ttm_lru_bulk_move_fini(&adev->mman.bdev, &vm->lru_bulk_move);
2669}
2670
2671/**
2672 * amdgpu_vm_manager_init - init the VM manager
2673 *
2674 * @adev: amdgpu_device pointer
2675 *
2676 * Initialize the VM manager structures
2677 */
2678void amdgpu_vm_manager_init(struct amdgpu_device *adev)
2679{
2680 unsigned i;
2681
2682 /* Concurrent flushes are only possible starting with Vega10 and
2683 * are broken on Navi10 and Navi14.
2684 */
2685 adev->vm_manager.concurrent_flush = !(adev->asic_type < CHIP_VEGA10 ||
2686 adev->asic_type == CHIP_NAVI10 ||
2687 adev->asic_type == CHIP_NAVI14);
2688 amdgpu_vmid_mgr_init(adev);
2689
2690 adev->vm_manager.fence_context =
2691 dma_fence_context_alloc(AMDGPU_MAX_RINGS);
2692 for (i = 0; i < AMDGPU_MAX_RINGS; ++i)
2693 adev->vm_manager.seqno[i] = 0;
2694
2695 spin_lock_init(&adev->vm_manager.prt_lock);
2696 atomic_set(&adev->vm_manager.num_prt_users, 0);
2697
2698 /* If not overridden by the user, by default, only in large BAR systems
2699 * Compute VM tables will be updated by CPU
2700 */
2701#ifdef CONFIG_X86_64
2702 if (amdgpu_vm_update_mode == -1) {
2703 /* For asic with VF MMIO access protection
2704 * avoid using CPU for VM table updates
2705 */
2706 if (amdgpu_gmc_vram_full_visible(&adev->gmc) &&
2707 !amdgpu_sriov_vf_mmio_access_protection(adev))
2708 adev->vm_manager.vm_update_mode =
2709 AMDGPU_VM_USE_CPU_FOR_COMPUTE;
2710 else
2711 adev->vm_manager.vm_update_mode = 0;
2712 } else
2713 adev->vm_manager.vm_update_mode = amdgpu_vm_update_mode;
2714#else
2715 adev->vm_manager.vm_update_mode = 0;
2716#endif
2717
2718 xa_init_flags(&adev->vm_manager.pasids, XA_FLAGS_LOCK_IRQ);
2719}
2720
2721/**
2722 * amdgpu_vm_manager_fini - cleanup VM manager
2723 *
2724 * @adev: amdgpu_device pointer
2725 *
2726 * Cleanup the VM manager and free resources.
2727 */
2728void amdgpu_vm_manager_fini(struct amdgpu_device *adev)
2729{
2730 WARN_ON(!xa_empty(&adev->vm_manager.pasids));
2731 xa_destroy(&adev->vm_manager.pasids);
2732
2733 amdgpu_vmid_mgr_fini(adev);
2734}
2735
2736/**
2737 * amdgpu_vm_ioctl - Manages VMID reservation for vm hubs.
2738 *
2739 * @dev: drm device pointer
2740 * @data: drm_amdgpu_vm
2741 * @filp: drm file pointer
2742 *
2743 * Returns:
2744 * 0 for success, -errno for errors.
2745 */
2746int amdgpu_vm_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
2747{
2748 union drm_amdgpu_vm *args = data;
2749 struct amdgpu_device *adev = drm_to_adev(dev);
2750 struct amdgpu_fpriv *fpriv = filp->driver_priv;
2751
2752 /* No valid flags defined yet */
2753 if (args->in.flags)
2754 return -EINVAL;
2755
2756 switch (args->in.op) {
2757 case AMDGPU_VM_OP_RESERVE_VMID:
2758 /* We only have requirement to reserve vmid from gfxhub */
2759 if (!fpriv->vm.reserved_vmid[AMDGPU_GFXHUB(0)]) {
2760 amdgpu_vmid_alloc_reserved(adev, AMDGPU_GFXHUB(0));
2761 fpriv->vm.reserved_vmid[AMDGPU_GFXHUB(0)] = true;
2762 }
2763
2764 break;
2765 case AMDGPU_VM_OP_UNRESERVE_VMID:
2766 if (fpriv->vm.reserved_vmid[AMDGPU_GFXHUB(0)]) {
2767 amdgpu_vmid_free_reserved(adev, AMDGPU_GFXHUB(0));
2768 fpriv->vm.reserved_vmid[AMDGPU_GFXHUB(0)] = false;
2769 }
2770 break;
2771 default:
2772 return -EINVAL;
2773 }
2774
2775 return 0;
2776}
2777
2778/**
2779 * amdgpu_vm_handle_fault - graceful handling of VM faults.
2780 * @adev: amdgpu device pointer
2781 * @pasid: PASID of the VM
2782 * @ts: Timestamp of the fault
2783 * @vmid: VMID, only used for GFX 9.4.3.
2784 * @node_id: Node_id received in IH cookie. Only applicable for
2785 * GFX 9.4.3.
2786 * @addr: Address of the fault
2787 * @write_fault: true is write fault, false is read fault
2788 *
2789 * Try to gracefully handle a VM fault. Return true if the fault was handled and
2790 * shouldn't be reported any more.
2791 */
2792bool amdgpu_vm_handle_fault(struct amdgpu_device *adev, u32 pasid,
2793 u32 vmid, u32 node_id, uint64_t addr, uint64_t ts,
2794 bool write_fault)
2795{
2796 bool is_compute_context = false;
2797 struct amdgpu_bo *root;
2798 unsigned long irqflags;
2799 uint64_t value, flags;
2800 struct amdgpu_vm *vm;
2801 int r;
2802
2803 xa_lock_irqsave(&adev->vm_manager.pasids, irqflags);
2804 vm = xa_load(&adev->vm_manager.pasids, pasid);
2805 if (vm) {
2806 root = amdgpu_bo_ref(vm->root.bo);
2807 is_compute_context = vm->is_compute_context;
2808 } else {
2809 root = NULL;
2810 }
2811 xa_unlock_irqrestore(&adev->vm_manager.pasids, irqflags);
2812
2813 if (!root)
2814 return false;
2815
2816 addr /= AMDGPU_GPU_PAGE_SIZE;
2817
2818 if (is_compute_context && !svm_range_restore_pages(adev, pasid, vmid,
2819 node_id, addr, ts, write_fault)) {
2820 amdgpu_bo_unref(&root);
2821 return true;
2822 }
2823
2824 r = amdgpu_bo_reserve(root, true);
2825 if (r)
2826 goto error_unref;
2827
2828 /* Double check that the VM still exists */
2829 xa_lock_irqsave(&adev->vm_manager.pasids, irqflags);
2830 vm = xa_load(&adev->vm_manager.pasids, pasid);
2831 if (vm && vm->root.bo != root)
2832 vm = NULL;
2833 xa_unlock_irqrestore(&adev->vm_manager.pasids, irqflags);
2834 if (!vm)
2835 goto error_unlock;
2836
2837 flags = AMDGPU_PTE_VALID | AMDGPU_PTE_SNOOPED |
2838 AMDGPU_PTE_SYSTEM;
2839
2840 if (is_compute_context) {
2841 /* Intentionally setting invalid PTE flag
2842 * combination to force a no-retry-fault
2843 */
2844 flags = AMDGPU_VM_NORETRY_FLAGS;
2845 value = 0;
2846 } else if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_NEVER) {
2847 /* Redirect the access to the dummy page */
2848 value = adev->dummy_page_addr;
2849 flags |= AMDGPU_PTE_EXECUTABLE | AMDGPU_PTE_READABLE |
2850 AMDGPU_PTE_WRITEABLE;
2851
2852 } else {
2853 /* Let the hw retry silently on the PTE */
2854 value = 0;
2855 }
2856
2857 r = dma_resv_reserve_fences(root->tbo.base.resv, 1);
2858 if (r) {
2859 pr_debug("failed %d to reserve fence slot\n", r);
2860 goto error_unlock;
2861 }
2862
2863 r = amdgpu_vm_update_range(adev, vm, true, false, false, false,
2864 NULL, addr, addr, flags, value, 0, NULL, NULL, NULL);
2865 if (r)
2866 goto error_unlock;
2867
2868 r = amdgpu_vm_update_pdes(adev, vm, true);
2869
2870error_unlock:
2871 amdgpu_bo_unreserve(root);
2872 if (r < 0)
2873 DRM_ERROR("Can't handle page fault (%d)\n", r);
2874
2875error_unref:
2876 amdgpu_bo_unref(&root);
2877
2878 return false;
2879}
2880
2881#if defined(CONFIG_DEBUG_FS)
2882/**
2883 * amdgpu_debugfs_vm_bo_info - print BO info for the VM
2884 *
2885 * @vm: Requested VM for printing BO info
2886 * @m: debugfs file
2887 *
2888 * Print BO information in debugfs file for the VM
2889 */
2890void amdgpu_debugfs_vm_bo_info(struct amdgpu_vm *vm, struct seq_file *m)
2891{
2892 struct amdgpu_bo_va *bo_va, *tmp;
2893 u64 total_idle = 0;
2894 u64 total_evicted = 0;
2895 u64 total_relocated = 0;
2896 u64 total_moved = 0;
2897 u64 total_invalidated = 0;
2898 u64 total_done = 0;
2899 unsigned int total_idle_objs = 0;
2900 unsigned int total_evicted_objs = 0;
2901 unsigned int total_relocated_objs = 0;
2902 unsigned int total_moved_objs = 0;
2903 unsigned int total_invalidated_objs = 0;
2904 unsigned int total_done_objs = 0;
2905 unsigned int id = 0;
2906
2907 spin_lock(&vm->status_lock);
2908 seq_puts(m, "\tIdle BOs:\n");
2909 list_for_each_entry_safe(bo_va, tmp, &vm->idle, base.vm_status) {
2910 if (!bo_va->base.bo)
2911 continue;
2912 total_idle += amdgpu_bo_print_info(id++, bo_va->base.bo, m);
2913 }
2914 total_idle_objs = id;
2915 id = 0;
2916
2917 seq_puts(m, "\tEvicted BOs:\n");
2918 list_for_each_entry_safe(bo_va, tmp, &vm->evicted, base.vm_status) {
2919 if (!bo_va->base.bo)
2920 continue;
2921 total_evicted += amdgpu_bo_print_info(id++, bo_va->base.bo, m);
2922 }
2923 total_evicted_objs = id;
2924 id = 0;
2925
2926 seq_puts(m, "\tRelocated BOs:\n");
2927 list_for_each_entry_safe(bo_va, tmp, &vm->relocated, base.vm_status) {
2928 if (!bo_va->base.bo)
2929 continue;
2930 total_relocated += amdgpu_bo_print_info(id++, bo_va->base.bo, m);
2931 }
2932 total_relocated_objs = id;
2933 id = 0;
2934
2935 seq_puts(m, "\tMoved BOs:\n");
2936 list_for_each_entry_safe(bo_va, tmp, &vm->moved, base.vm_status) {
2937 if (!bo_va->base.bo)
2938 continue;
2939 total_moved += amdgpu_bo_print_info(id++, bo_va->base.bo, m);
2940 }
2941 total_moved_objs = id;
2942 id = 0;
2943
2944 seq_puts(m, "\tInvalidated BOs:\n");
2945 list_for_each_entry_safe(bo_va, tmp, &vm->invalidated, base.vm_status) {
2946 if (!bo_va->base.bo)
2947 continue;
2948 total_invalidated += amdgpu_bo_print_info(id++, bo_va->base.bo, m);
2949 }
2950 total_invalidated_objs = id;
2951 id = 0;
2952
2953 seq_puts(m, "\tDone BOs:\n");
2954 list_for_each_entry_safe(bo_va, tmp, &vm->done, base.vm_status) {
2955 if (!bo_va->base.bo)
2956 continue;
2957 total_done += amdgpu_bo_print_info(id++, bo_va->base.bo, m);
2958 }
2959 spin_unlock(&vm->status_lock);
2960 total_done_objs = id;
2961
2962 seq_printf(m, "\tTotal idle size: %12lld\tobjs:\t%d\n", total_idle,
2963 total_idle_objs);
2964 seq_printf(m, "\tTotal evicted size: %12lld\tobjs:\t%d\n", total_evicted,
2965 total_evicted_objs);
2966 seq_printf(m, "\tTotal relocated size: %12lld\tobjs:\t%d\n", total_relocated,
2967 total_relocated_objs);
2968 seq_printf(m, "\tTotal moved size: %12lld\tobjs:\t%d\n", total_moved,
2969 total_moved_objs);
2970 seq_printf(m, "\tTotal invalidated size: %12lld\tobjs:\t%d\n", total_invalidated,
2971 total_invalidated_objs);
2972 seq_printf(m, "\tTotal done size: %12lld\tobjs:\t%d\n", total_done,
2973 total_done_objs);
2974}
2975#endif
2976
2977/**
2978 * amdgpu_vm_update_fault_cache - update cached fault into.
2979 * @adev: amdgpu device pointer
2980 * @pasid: PASID of the VM
2981 * @addr: Address of the fault
2982 * @status: GPUVM fault status register
2983 * @vmhub: which vmhub got the fault
2984 *
2985 * Cache the fault info for later use by userspace in debugging.
2986 */
2987void amdgpu_vm_update_fault_cache(struct amdgpu_device *adev,
2988 unsigned int pasid,
2989 uint64_t addr,
2990 uint32_t status,
2991 unsigned int vmhub)
2992{
2993 struct amdgpu_vm *vm;
2994 unsigned long flags;
2995
2996 xa_lock_irqsave(&adev->vm_manager.pasids, flags);
2997
2998 vm = xa_load(&adev->vm_manager.pasids, pasid);
2999 /* Don't update the fault cache if status is 0. In the multiple
3000 * fault case, subsequent faults will return a 0 status which is
3001 * useless for userspace and replaces the useful fault status, so
3002 * only update if status is non-0.
3003 */
3004 if (vm && status) {
3005 vm->fault_info.addr = addr;
3006 vm->fault_info.status = status;
3007 /*
3008 * Update the fault information globally for later usage
3009 * when vm could be stale or freed.
3010 */
3011 adev->vm_manager.fault_info.addr = addr;
3012 adev->vm_manager.fault_info.vmhub = vmhub;
3013 adev->vm_manager.fault_info.status = status;
3014
3015 if (AMDGPU_IS_GFXHUB(vmhub)) {
3016 vm->fault_info.vmhub = AMDGPU_VMHUB_TYPE_GFX;
3017 vm->fault_info.vmhub |=
3018 (vmhub - AMDGPU_GFXHUB_START) << AMDGPU_VMHUB_IDX_SHIFT;
3019 } else if (AMDGPU_IS_MMHUB0(vmhub)) {
3020 vm->fault_info.vmhub = AMDGPU_VMHUB_TYPE_MM0;
3021 vm->fault_info.vmhub |=
3022 (vmhub - AMDGPU_MMHUB0_START) << AMDGPU_VMHUB_IDX_SHIFT;
3023 } else if (AMDGPU_IS_MMHUB1(vmhub)) {
3024 vm->fault_info.vmhub = AMDGPU_VMHUB_TYPE_MM1;
3025 vm->fault_info.vmhub |=
3026 (vmhub - AMDGPU_MMHUB1_START) << AMDGPU_VMHUB_IDX_SHIFT;
3027 } else {
3028 WARN_ONCE(1, "Invalid vmhub %u\n", vmhub);
3029 }
3030 }
3031 xa_unlock_irqrestore(&adev->vm_manager.pasids, flags);
3032}
3033
3034/**
3035 * amdgpu_vm_is_bo_always_valid - check if the BO is VM always valid
3036 *
3037 * @vm: VM to test against.
3038 * @bo: BO to be tested.
3039 *
3040 * Returns true if the BO shares the dma_resv object with the root PD and is
3041 * always guaranteed to be valid inside the VM.
3042 */
3043bool amdgpu_vm_is_bo_always_valid(struct amdgpu_vm *vm, struct amdgpu_bo *bo)
3044{
3045 return bo && bo->tbo.base.resv == vm->root.bo->tbo.base.resv;
3046}