Loading...
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * linux/drivers/clocksource/arm_arch_timer.c
4 *
5 * Copyright (C) 2011 ARM Ltd.
6 * All Rights Reserved
7 */
8
9#define pr_fmt(fmt) "arch_timer: " fmt
10
11#include <linux/init.h>
12#include <linux/kernel.h>
13#include <linux/device.h>
14#include <linux/smp.h>
15#include <linux/cpu.h>
16#include <linux/cpu_pm.h>
17#include <linux/clockchips.h>
18#include <linux/clocksource.h>
19#include <linux/interrupt.h>
20#include <linux/of_irq.h>
21#include <linux/of_address.h>
22#include <linux/io.h>
23#include <linux/slab.h>
24#include <linux/sched/clock.h>
25#include <linux/sched_clock.h>
26#include <linux/acpi.h>
27
28#include <asm/arch_timer.h>
29#include <asm/virt.h>
30
31#include <clocksource/arm_arch_timer.h>
32
33#define CNTTIDR 0x08
34#define CNTTIDR_VIRT(n) (BIT(1) << ((n) * 4))
35
36#define CNTACR(n) (0x40 + ((n) * 4))
37#define CNTACR_RPCT BIT(0)
38#define CNTACR_RVCT BIT(1)
39#define CNTACR_RFRQ BIT(2)
40#define CNTACR_RVOFF BIT(3)
41#define CNTACR_RWVT BIT(4)
42#define CNTACR_RWPT BIT(5)
43
44#define CNTVCT_LO 0x08
45#define CNTVCT_HI 0x0c
46#define CNTFRQ 0x10
47#define CNTP_TVAL 0x28
48#define CNTP_CTL 0x2c
49#define CNTV_TVAL 0x38
50#define CNTV_CTL 0x3c
51
52static unsigned arch_timers_present __initdata;
53
54static void __iomem *arch_counter_base;
55
56struct arch_timer {
57 void __iomem *base;
58 struct clock_event_device evt;
59};
60
61#define to_arch_timer(e) container_of(e, struct arch_timer, evt)
62
63static u32 arch_timer_rate;
64static int arch_timer_ppi[ARCH_TIMER_MAX_TIMER_PPI];
65
66static struct clock_event_device __percpu *arch_timer_evt;
67
68static enum arch_timer_ppi_nr arch_timer_uses_ppi = ARCH_TIMER_VIRT_PPI;
69static bool arch_timer_c3stop;
70static bool arch_timer_mem_use_virtual;
71static bool arch_counter_suspend_stop;
72#ifdef CONFIG_GENERIC_GETTIMEOFDAY
73static enum vdso_clock_mode vdso_default = VDSO_CLOCKMODE_ARCHTIMER;
74#else
75static enum vdso_clock_mode vdso_default = VDSO_CLOCKMODE_NONE;
76#endif /* CONFIG_GENERIC_GETTIMEOFDAY */
77
78static cpumask_t evtstrm_available = CPU_MASK_NONE;
79static bool evtstrm_enable = IS_ENABLED(CONFIG_ARM_ARCH_TIMER_EVTSTREAM);
80
81static int __init early_evtstrm_cfg(char *buf)
82{
83 return strtobool(buf, &evtstrm_enable);
84}
85early_param("clocksource.arm_arch_timer.evtstrm", early_evtstrm_cfg);
86
87/*
88 * Architected system timer support.
89 */
90
91static __always_inline
92void arch_timer_reg_write(int access, enum arch_timer_reg reg, u32 val,
93 struct clock_event_device *clk)
94{
95 if (access == ARCH_TIMER_MEM_PHYS_ACCESS) {
96 struct arch_timer *timer = to_arch_timer(clk);
97 switch (reg) {
98 case ARCH_TIMER_REG_CTRL:
99 writel_relaxed(val, timer->base + CNTP_CTL);
100 break;
101 case ARCH_TIMER_REG_TVAL:
102 writel_relaxed(val, timer->base + CNTP_TVAL);
103 break;
104 }
105 } else if (access == ARCH_TIMER_MEM_VIRT_ACCESS) {
106 struct arch_timer *timer = to_arch_timer(clk);
107 switch (reg) {
108 case ARCH_TIMER_REG_CTRL:
109 writel_relaxed(val, timer->base + CNTV_CTL);
110 break;
111 case ARCH_TIMER_REG_TVAL:
112 writel_relaxed(val, timer->base + CNTV_TVAL);
113 break;
114 }
115 } else {
116 arch_timer_reg_write_cp15(access, reg, val);
117 }
118}
119
120static __always_inline
121u32 arch_timer_reg_read(int access, enum arch_timer_reg reg,
122 struct clock_event_device *clk)
123{
124 u32 val;
125
126 if (access == ARCH_TIMER_MEM_PHYS_ACCESS) {
127 struct arch_timer *timer = to_arch_timer(clk);
128 switch (reg) {
129 case ARCH_TIMER_REG_CTRL:
130 val = readl_relaxed(timer->base + CNTP_CTL);
131 break;
132 case ARCH_TIMER_REG_TVAL:
133 val = readl_relaxed(timer->base + CNTP_TVAL);
134 break;
135 }
136 } else if (access == ARCH_TIMER_MEM_VIRT_ACCESS) {
137 struct arch_timer *timer = to_arch_timer(clk);
138 switch (reg) {
139 case ARCH_TIMER_REG_CTRL:
140 val = readl_relaxed(timer->base + CNTV_CTL);
141 break;
142 case ARCH_TIMER_REG_TVAL:
143 val = readl_relaxed(timer->base + CNTV_TVAL);
144 break;
145 }
146 } else {
147 val = arch_timer_reg_read_cp15(access, reg);
148 }
149
150 return val;
151}
152
153static notrace u64 arch_counter_get_cntpct_stable(void)
154{
155 return __arch_counter_get_cntpct_stable();
156}
157
158static notrace u64 arch_counter_get_cntpct(void)
159{
160 return __arch_counter_get_cntpct();
161}
162
163static notrace u64 arch_counter_get_cntvct_stable(void)
164{
165 return __arch_counter_get_cntvct_stable();
166}
167
168static notrace u64 arch_counter_get_cntvct(void)
169{
170 return __arch_counter_get_cntvct();
171}
172
173/*
174 * Default to cp15 based access because arm64 uses this function for
175 * sched_clock() before DT is probed and the cp15 method is guaranteed
176 * to exist on arm64. arm doesn't use this before DT is probed so even
177 * if we don't have the cp15 accessors we won't have a problem.
178 */
179u64 (*arch_timer_read_counter)(void) = arch_counter_get_cntvct;
180EXPORT_SYMBOL_GPL(arch_timer_read_counter);
181
182static u64 arch_counter_read(struct clocksource *cs)
183{
184 return arch_timer_read_counter();
185}
186
187static u64 arch_counter_read_cc(const struct cyclecounter *cc)
188{
189 return arch_timer_read_counter();
190}
191
192static struct clocksource clocksource_counter = {
193 .name = "arch_sys_counter",
194 .rating = 400,
195 .read = arch_counter_read,
196 .mask = CLOCKSOURCE_MASK(56),
197 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
198};
199
200static struct cyclecounter cyclecounter __ro_after_init = {
201 .read = arch_counter_read_cc,
202 .mask = CLOCKSOURCE_MASK(56),
203};
204
205struct ate_acpi_oem_info {
206 char oem_id[ACPI_OEM_ID_SIZE + 1];
207 char oem_table_id[ACPI_OEM_TABLE_ID_SIZE + 1];
208 u32 oem_revision;
209};
210
211#ifdef CONFIG_FSL_ERRATUM_A008585
212/*
213 * The number of retries is an arbitrary value well beyond the highest number
214 * of iterations the loop has been observed to take.
215 */
216#define __fsl_a008585_read_reg(reg) ({ \
217 u64 _old, _new; \
218 int _retries = 200; \
219 \
220 do { \
221 _old = read_sysreg(reg); \
222 _new = read_sysreg(reg); \
223 _retries--; \
224 } while (unlikely(_old != _new) && _retries); \
225 \
226 WARN_ON_ONCE(!_retries); \
227 _new; \
228})
229
230static u32 notrace fsl_a008585_read_cntp_tval_el0(void)
231{
232 return __fsl_a008585_read_reg(cntp_tval_el0);
233}
234
235static u32 notrace fsl_a008585_read_cntv_tval_el0(void)
236{
237 return __fsl_a008585_read_reg(cntv_tval_el0);
238}
239
240static u64 notrace fsl_a008585_read_cntpct_el0(void)
241{
242 return __fsl_a008585_read_reg(cntpct_el0);
243}
244
245static u64 notrace fsl_a008585_read_cntvct_el0(void)
246{
247 return __fsl_a008585_read_reg(cntvct_el0);
248}
249#endif
250
251#ifdef CONFIG_HISILICON_ERRATUM_161010101
252/*
253 * Verify whether the value of the second read is larger than the first by
254 * less than 32 is the only way to confirm the value is correct, so clear the
255 * lower 5 bits to check whether the difference is greater than 32 or not.
256 * Theoretically the erratum should not occur more than twice in succession
257 * when reading the system counter, but it is possible that some interrupts
258 * may lead to more than twice read errors, triggering the warning, so setting
259 * the number of retries far beyond the number of iterations the loop has been
260 * observed to take.
261 */
262#define __hisi_161010101_read_reg(reg) ({ \
263 u64 _old, _new; \
264 int _retries = 50; \
265 \
266 do { \
267 _old = read_sysreg(reg); \
268 _new = read_sysreg(reg); \
269 _retries--; \
270 } while (unlikely((_new - _old) >> 5) && _retries); \
271 \
272 WARN_ON_ONCE(!_retries); \
273 _new; \
274})
275
276static u32 notrace hisi_161010101_read_cntp_tval_el0(void)
277{
278 return __hisi_161010101_read_reg(cntp_tval_el0);
279}
280
281static u32 notrace hisi_161010101_read_cntv_tval_el0(void)
282{
283 return __hisi_161010101_read_reg(cntv_tval_el0);
284}
285
286static u64 notrace hisi_161010101_read_cntpct_el0(void)
287{
288 return __hisi_161010101_read_reg(cntpct_el0);
289}
290
291static u64 notrace hisi_161010101_read_cntvct_el0(void)
292{
293 return __hisi_161010101_read_reg(cntvct_el0);
294}
295
296static struct ate_acpi_oem_info hisi_161010101_oem_info[] = {
297 /*
298 * Note that trailing spaces are required to properly match
299 * the OEM table information.
300 */
301 {
302 .oem_id = "HISI ",
303 .oem_table_id = "HIP05 ",
304 .oem_revision = 0,
305 },
306 {
307 .oem_id = "HISI ",
308 .oem_table_id = "HIP06 ",
309 .oem_revision = 0,
310 },
311 {
312 .oem_id = "HISI ",
313 .oem_table_id = "HIP07 ",
314 .oem_revision = 0,
315 },
316 { /* Sentinel indicating the end of the OEM array */ },
317};
318#endif
319
320#ifdef CONFIG_ARM64_ERRATUM_858921
321static u64 notrace arm64_858921_read_cntpct_el0(void)
322{
323 u64 old, new;
324
325 old = read_sysreg(cntpct_el0);
326 new = read_sysreg(cntpct_el0);
327 return (((old ^ new) >> 32) & 1) ? old : new;
328}
329
330static u64 notrace arm64_858921_read_cntvct_el0(void)
331{
332 u64 old, new;
333
334 old = read_sysreg(cntvct_el0);
335 new = read_sysreg(cntvct_el0);
336 return (((old ^ new) >> 32) & 1) ? old : new;
337}
338#endif
339
340#ifdef CONFIG_SUN50I_ERRATUM_UNKNOWN1
341/*
342 * The low bits of the counter registers are indeterminate while bit 10 or
343 * greater is rolling over. Since the counter value can jump both backward
344 * (7ff -> 000 -> 800) and forward (7ff -> fff -> 800), ignore register values
345 * with all ones or all zeros in the low bits. Bound the loop by the maximum
346 * number of CPU cycles in 3 consecutive 24 MHz counter periods.
347 */
348#define __sun50i_a64_read_reg(reg) ({ \
349 u64 _val; \
350 int _retries = 150; \
351 \
352 do { \
353 _val = read_sysreg(reg); \
354 _retries--; \
355 } while (((_val + 1) & GENMASK(9, 0)) <= 1 && _retries); \
356 \
357 WARN_ON_ONCE(!_retries); \
358 _val; \
359})
360
361static u64 notrace sun50i_a64_read_cntpct_el0(void)
362{
363 return __sun50i_a64_read_reg(cntpct_el0);
364}
365
366static u64 notrace sun50i_a64_read_cntvct_el0(void)
367{
368 return __sun50i_a64_read_reg(cntvct_el0);
369}
370
371static u32 notrace sun50i_a64_read_cntp_tval_el0(void)
372{
373 return read_sysreg(cntp_cval_el0) - sun50i_a64_read_cntpct_el0();
374}
375
376static u32 notrace sun50i_a64_read_cntv_tval_el0(void)
377{
378 return read_sysreg(cntv_cval_el0) - sun50i_a64_read_cntvct_el0();
379}
380#endif
381
382#ifdef CONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND
383DEFINE_PER_CPU(const struct arch_timer_erratum_workaround *, timer_unstable_counter_workaround);
384EXPORT_SYMBOL_GPL(timer_unstable_counter_workaround);
385
386static atomic_t timer_unstable_counter_workaround_in_use = ATOMIC_INIT(0);
387
388static void erratum_set_next_event_tval_generic(const int access, unsigned long evt,
389 struct clock_event_device *clk)
390{
391 unsigned long ctrl;
392 u64 cval;
393
394 ctrl = arch_timer_reg_read(access, ARCH_TIMER_REG_CTRL, clk);
395 ctrl |= ARCH_TIMER_CTRL_ENABLE;
396 ctrl &= ~ARCH_TIMER_CTRL_IT_MASK;
397
398 if (access == ARCH_TIMER_PHYS_ACCESS) {
399 cval = evt + arch_counter_get_cntpct();
400 write_sysreg(cval, cntp_cval_el0);
401 } else {
402 cval = evt + arch_counter_get_cntvct();
403 write_sysreg(cval, cntv_cval_el0);
404 }
405
406 arch_timer_reg_write(access, ARCH_TIMER_REG_CTRL, ctrl, clk);
407}
408
409static __maybe_unused int erratum_set_next_event_tval_virt(unsigned long evt,
410 struct clock_event_device *clk)
411{
412 erratum_set_next_event_tval_generic(ARCH_TIMER_VIRT_ACCESS, evt, clk);
413 return 0;
414}
415
416static __maybe_unused int erratum_set_next_event_tval_phys(unsigned long evt,
417 struct clock_event_device *clk)
418{
419 erratum_set_next_event_tval_generic(ARCH_TIMER_PHYS_ACCESS, evt, clk);
420 return 0;
421}
422
423static const struct arch_timer_erratum_workaround ool_workarounds[] = {
424#ifdef CONFIG_FSL_ERRATUM_A008585
425 {
426 .match_type = ate_match_dt,
427 .id = "fsl,erratum-a008585",
428 .desc = "Freescale erratum a005858",
429 .read_cntp_tval_el0 = fsl_a008585_read_cntp_tval_el0,
430 .read_cntv_tval_el0 = fsl_a008585_read_cntv_tval_el0,
431 .read_cntpct_el0 = fsl_a008585_read_cntpct_el0,
432 .read_cntvct_el0 = fsl_a008585_read_cntvct_el0,
433 .set_next_event_phys = erratum_set_next_event_tval_phys,
434 .set_next_event_virt = erratum_set_next_event_tval_virt,
435 },
436#endif
437#ifdef CONFIG_HISILICON_ERRATUM_161010101
438 {
439 .match_type = ate_match_dt,
440 .id = "hisilicon,erratum-161010101",
441 .desc = "HiSilicon erratum 161010101",
442 .read_cntp_tval_el0 = hisi_161010101_read_cntp_tval_el0,
443 .read_cntv_tval_el0 = hisi_161010101_read_cntv_tval_el0,
444 .read_cntpct_el0 = hisi_161010101_read_cntpct_el0,
445 .read_cntvct_el0 = hisi_161010101_read_cntvct_el0,
446 .set_next_event_phys = erratum_set_next_event_tval_phys,
447 .set_next_event_virt = erratum_set_next_event_tval_virt,
448 },
449 {
450 .match_type = ate_match_acpi_oem_info,
451 .id = hisi_161010101_oem_info,
452 .desc = "HiSilicon erratum 161010101",
453 .read_cntp_tval_el0 = hisi_161010101_read_cntp_tval_el0,
454 .read_cntv_tval_el0 = hisi_161010101_read_cntv_tval_el0,
455 .read_cntpct_el0 = hisi_161010101_read_cntpct_el0,
456 .read_cntvct_el0 = hisi_161010101_read_cntvct_el0,
457 .set_next_event_phys = erratum_set_next_event_tval_phys,
458 .set_next_event_virt = erratum_set_next_event_tval_virt,
459 },
460#endif
461#ifdef CONFIG_ARM64_ERRATUM_858921
462 {
463 .match_type = ate_match_local_cap_id,
464 .id = (void *)ARM64_WORKAROUND_858921,
465 .desc = "ARM erratum 858921",
466 .read_cntpct_el0 = arm64_858921_read_cntpct_el0,
467 .read_cntvct_el0 = arm64_858921_read_cntvct_el0,
468 },
469#endif
470#ifdef CONFIG_SUN50I_ERRATUM_UNKNOWN1
471 {
472 .match_type = ate_match_dt,
473 .id = "allwinner,erratum-unknown1",
474 .desc = "Allwinner erratum UNKNOWN1",
475 .read_cntp_tval_el0 = sun50i_a64_read_cntp_tval_el0,
476 .read_cntv_tval_el0 = sun50i_a64_read_cntv_tval_el0,
477 .read_cntpct_el0 = sun50i_a64_read_cntpct_el0,
478 .read_cntvct_el0 = sun50i_a64_read_cntvct_el0,
479 .set_next_event_phys = erratum_set_next_event_tval_phys,
480 .set_next_event_virt = erratum_set_next_event_tval_virt,
481 },
482#endif
483#ifdef CONFIG_ARM64_ERRATUM_1418040
484 {
485 .match_type = ate_match_local_cap_id,
486 .id = (void *)ARM64_WORKAROUND_1418040,
487 .desc = "ARM erratum 1418040",
488 .disable_compat_vdso = true,
489 },
490#endif
491};
492
493typedef bool (*ate_match_fn_t)(const struct arch_timer_erratum_workaround *,
494 const void *);
495
496static
497bool arch_timer_check_dt_erratum(const struct arch_timer_erratum_workaround *wa,
498 const void *arg)
499{
500 const struct device_node *np = arg;
501
502 return of_property_read_bool(np, wa->id);
503}
504
505static
506bool arch_timer_check_local_cap_erratum(const struct arch_timer_erratum_workaround *wa,
507 const void *arg)
508{
509 return this_cpu_has_cap((uintptr_t)wa->id);
510}
511
512
513static
514bool arch_timer_check_acpi_oem_erratum(const struct arch_timer_erratum_workaround *wa,
515 const void *arg)
516{
517 static const struct ate_acpi_oem_info empty_oem_info = {};
518 const struct ate_acpi_oem_info *info = wa->id;
519 const struct acpi_table_header *table = arg;
520
521 /* Iterate over the ACPI OEM info array, looking for a match */
522 while (memcmp(info, &empty_oem_info, sizeof(*info))) {
523 if (!memcmp(info->oem_id, table->oem_id, ACPI_OEM_ID_SIZE) &&
524 !memcmp(info->oem_table_id, table->oem_table_id, ACPI_OEM_TABLE_ID_SIZE) &&
525 info->oem_revision == table->oem_revision)
526 return true;
527
528 info++;
529 }
530
531 return false;
532}
533
534static const struct arch_timer_erratum_workaround *
535arch_timer_iterate_errata(enum arch_timer_erratum_match_type type,
536 ate_match_fn_t match_fn,
537 void *arg)
538{
539 int i;
540
541 for (i = 0; i < ARRAY_SIZE(ool_workarounds); i++) {
542 if (ool_workarounds[i].match_type != type)
543 continue;
544
545 if (match_fn(&ool_workarounds[i], arg))
546 return &ool_workarounds[i];
547 }
548
549 return NULL;
550}
551
552static
553void arch_timer_enable_workaround(const struct arch_timer_erratum_workaround *wa,
554 bool local)
555{
556 int i;
557
558 if (local) {
559 __this_cpu_write(timer_unstable_counter_workaround, wa);
560 } else {
561 for_each_possible_cpu(i)
562 per_cpu(timer_unstable_counter_workaround, i) = wa;
563 }
564
565 if (wa->read_cntvct_el0 || wa->read_cntpct_el0)
566 atomic_set(&timer_unstable_counter_workaround_in_use, 1);
567
568 /*
569 * Don't use the vdso fastpath if errata require using the
570 * out-of-line counter accessor. We may change our mind pretty
571 * late in the game (with a per-CPU erratum, for example), so
572 * change both the default value and the vdso itself.
573 */
574 if (wa->read_cntvct_el0) {
575 clocksource_counter.vdso_clock_mode = VDSO_CLOCKMODE_NONE;
576 vdso_default = VDSO_CLOCKMODE_NONE;
577 } else if (wa->disable_compat_vdso && vdso_default != VDSO_CLOCKMODE_NONE) {
578 vdso_default = VDSO_CLOCKMODE_ARCHTIMER_NOCOMPAT;
579 clocksource_counter.vdso_clock_mode = vdso_default;
580 }
581}
582
583static void arch_timer_check_ool_workaround(enum arch_timer_erratum_match_type type,
584 void *arg)
585{
586 const struct arch_timer_erratum_workaround *wa, *__wa;
587 ate_match_fn_t match_fn = NULL;
588 bool local = false;
589
590 switch (type) {
591 case ate_match_dt:
592 match_fn = arch_timer_check_dt_erratum;
593 break;
594 case ate_match_local_cap_id:
595 match_fn = arch_timer_check_local_cap_erratum;
596 local = true;
597 break;
598 case ate_match_acpi_oem_info:
599 match_fn = arch_timer_check_acpi_oem_erratum;
600 break;
601 default:
602 WARN_ON(1);
603 return;
604 }
605
606 wa = arch_timer_iterate_errata(type, match_fn, arg);
607 if (!wa)
608 return;
609
610 __wa = __this_cpu_read(timer_unstable_counter_workaround);
611 if (__wa && wa != __wa)
612 pr_warn("Can't enable workaround for %s (clashes with %s\n)",
613 wa->desc, __wa->desc);
614
615 if (__wa)
616 return;
617
618 arch_timer_enable_workaround(wa, local);
619 pr_info("Enabling %s workaround for %s\n",
620 local ? "local" : "global", wa->desc);
621}
622
623static bool arch_timer_this_cpu_has_cntvct_wa(void)
624{
625 return has_erratum_handler(read_cntvct_el0);
626}
627
628static bool arch_timer_counter_has_wa(void)
629{
630 return atomic_read(&timer_unstable_counter_workaround_in_use);
631}
632#else
633#define arch_timer_check_ool_workaround(t,a) do { } while(0)
634#define arch_timer_this_cpu_has_cntvct_wa() ({false;})
635#define arch_timer_counter_has_wa() ({false;})
636#endif /* CONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND */
637
638static __always_inline irqreturn_t timer_handler(const int access,
639 struct clock_event_device *evt)
640{
641 unsigned long ctrl;
642
643 ctrl = arch_timer_reg_read(access, ARCH_TIMER_REG_CTRL, evt);
644 if (ctrl & ARCH_TIMER_CTRL_IT_STAT) {
645 ctrl |= ARCH_TIMER_CTRL_IT_MASK;
646 arch_timer_reg_write(access, ARCH_TIMER_REG_CTRL, ctrl, evt);
647 evt->event_handler(evt);
648 return IRQ_HANDLED;
649 }
650
651 return IRQ_NONE;
652}
653
654static irqreturn_t arch_timer_handler_virt(int irq, void *dev_id)
655{
656 struct clock_event_device *evt = dev_id;
657
658 return timer_handler(ARCH_TIMER_VIRT_ACCESS, evt);
659}
660
661static irqreturn_t arch_timer_handler_phys(int irq, void *dev_id)
662{
663 struct clock_event_device *evt = dev_id;
664
665 return timer_handler(ARCH_TIMER_PHYS_ACCESS, evt);
666}
667
668static irqreturn_t arch_timer_handler_phys_mem(int irq, void *dev_id)
669{
670 struct clock_event_device *evt = dev_id;
671
672 return timer_handler(ARCH_TIMER_MEM_PHYS_ACCESS, evt);
673}
674
675static irqreturn_t arch_timer_handler_virt_mem(int irq, void *dev_id)
676{
677 struct clock_event_device *evt = dev_id;
678
679 return timer_handler(ARCH_TIMER_MEM_VIRT_ACCESS, evt);
680}
681
682static __always_inline int timer_shutdown(const int access,
683 struct clock_event_device *clk)
684{
685 unsigned long ctrl;
686
687 ctrl = arch_timer_reg_read(access, ARCH_TIMER_REG_CTRL, clk);
688 ctrl &= ~ARCH_TIMER_CTRL_ENABLE;
689 arch_timer_reg_write(access, ARCH_TIMER_REG_CTRL, ctrl, clk);
690
691 return 0;
692}
693
694static int arch_timer_shutdown_virt(struct clock_event_device *clk)
695{
696 return timer_shutdown(ARCH_TIMER_VIRT_ACCESS, clk);
697}
698
699static int arch_timer_shutdown_phys(struct clock_event_device *clk)
700{
701 return timer_shutdown(ARCH_TIMER_PHYS_ACCESS, clk);
702}
703
704static int arch_timer_shutdown_virt_mem(struct clock_event_device *clk)
705{
706 return timer_shutdown(ARCH_TIMER_MEM_VIRT_ACCESS, clk);
707}
708
709static int arch_timer_shutdown_phys_mem(struct clock_event_device *clk)
710{
711 return timer_shutdown(ARCH_TIMER_MEM_PHYS_ACCESS, clk);
712}
713
714static __always_inline void set_next_event(const int access, unsigned long evt,
715 struct clock_event_device *clk)
716{
717 unsigned long ctrl;
718 ctrl = arch_timer_reg_read(access, ARCH_TIMER_REG_CTRL, clk);
719 ctrl |= ARCH_TIMER_CTRL_ENABLE;
720 ctrl &= ~ARCH_TIMER_CTRL_IT_MASK;
721 arch_timer_reg_write(access, ARCH_TIMER_REG_TVAL, evt, clk);
722 arch_timer_reg_write(access, ARCH_TIMER_REG_CTRL, ctrl, clk);
723}
724
725static int arch_timer_set_next_event_virt(unsigned long evt,
726 struct clock_event_device *clk)
727{
728 set_next_event(ARCH_TIMER_VIRT_ACCESS, evt, clk);
729 return 0;
730}
731
732static int arch_timer_set_next_event_phys(unsigned long evt,
733 struct clock_event_device *clk)
734{
735 set_next_event(ARCH_TIMER_PHYS_ACCESS, evt, clk);
736 return 0;
737}
738
739static int arch_timer_set_next_event_virt_mem(unsigned long evt,
740 struct clock_event_device *clk)
741{
742 set_next_event(ARCH_TIMER_MEM_VIRT_ACCESS, evt, clk);
743 return 0;
744}
745
746static int arch_timer_set_next_event_phys_mem(unsigned long evt,
747 struct clock_event_device *clk)
748{
749 set_next_event(ARCH_TIMER_MEM_PHYS_ACCESS, evt, clk);
750 return 0;
751}
752
753static void __arch_timer_setup(unsigned type,
754 struct clock_event_device *clk)
755{
756 clk->features = CLOCK_EVT_FEAT_ONESHOT;
757
758 if (type == ARCH_TIMER_TYPE_CP15) {
759 typeof(clk->set_next_event) sne;
760
761 arch_timer_check_ool_workaround(ate_match_local_cap_id, NULL);
762
763 if (arch_timer_c3stop)
764 clk->features |= CLOCK_EVT_FEAT_C3STOP;
765 clk->name = "arch_sys_timer";
766 clk->rating = 450;
767 clk->cpumask = cpumask_of(smp_processor_id());
768 clk->irq = arch_timer_ppi[arch_timer_uses_ppi];
769 switch (arch_timer_uses_ppi) {
770 case ARCH_TIMER_VIRT_PPI:
771 clk->set_state_shutdown = arch_timer_shutdown_virt;
772 clk->set_state_oneshot_stopped = arch_timer_shutdown_virt;
773 sne = erratum_handler(set_next_event_virt);
774 break;
775 case ARCH_TIMER_PHYS_SECURE_PPI:
776 case ARCH_TIMER_PHYS_NONSECURE_PPI:
777 case ARCH_TIMER_HYP_PPI:
778 clk->set_state_shutdown = arch_timer_shutdown_phys;
779 clk->set_state_oneshot_stopped = arch_timer_shutdown_phys;
780 sne = erratum_handler(set_next_event_phys);
781 break;
782 default:
783 BUG();
784 }
785
786 clk->set_next_event = sne;
787 } else {
788 clk->features |= CLOCK_EVT_FEAT_DYNIRQ;
789 clk->name = "arch_mem_timer";
790 clk->rating = 400;
791 clk->cpumask = cpu_possible_mask;
792 if (arch_timer_mem_use_virtual) {
793 clk->set_state_shutdown = arch_timer_shutdown_virt_mem;
794 clk->set_state_oneshot_stopped = arch_timer_shutdown_virt_mem;
795 clk->set_next_event =
796 arch_timer_set_next_event_virt_mem;
797 } else {
798 clk->set_state_shutdown = arch_timer_shutdown_phys_mem;
799 clk->set_state_oneshot_stopped = arch_timer_shutdown_phys_mem;
800 clk->set_next_event =
801 arch_timer_set_next_event_phys_mem;
802 }
803 }
804
805 clk->set_state_shutdown(clk);
806
807 clockevents_config_and_register(clk, arch_timer_rate, 0xf, 0x7fffffff);
808}
809
810static void arch_timer_evtstrm_enable(int divider)
811{
812 u32 cntkctl = arch_timer_get_cntkctl();
813
814 cntkctl &= ~ARCH_TIMER_EVT_TRIGGER_MASK;
815 /* Set the divider and enable virtual event stream */
816 cntkctl |= (divider << ARCH_TIMER_EVT_TRIGGER_SHIFT)
817 | ARCH_TIMER_VIRT_EVT_EN;
818 arch_timer_set_cntkctl(cntkctl);
819 arch_timer_set_evtstrm_feature();
820 cpumask_set_cpu(smp_processor_id(), &evtstrm_available);
821}
822
823static void arch_timer_configure_evtstream(void)
824{
825 int evt_stream_div, pos;
826
827 /* Find the closest power of two to the divisor */
828 evt_stream_div = arch_timer_rate / ARCH_TIMER_EVT_STREAM_FREQ;
829 pos = fls(evt_stream_div);
830 if (pos > 1 && !(evt_stream_div & (1 << (pos - 2))))
831 pos--;
832 /* enable event stream */
833 arch_timer_evtstrm_enable(min(pos, 15));
834}
835
836static void arch_counter_set_user_access(void)
837{
838 u32 cntkctl = arch_timer_get_cntkctl();
839
840 /* Disable user access to the timers and both counters */
841 /* Also disable virtual event stream */
842 cntkctl &= ~(ARCH_TIMER_USR_PT_ACCESS_EN
843 | ARCH_TIMER_USR_VT_ACCESS_EN
844 | ARCH_TIMER_USR_VCT_ACCESS_EN
845 | ARCH_TIMER_VIRT_EVT_EN
846 | ARCH_TIMER_USR_PCT_ACCESS_EN);
847
848 /*
849 * Enable user access to the virtual counter if it doesn't
850 * need to be workaround. The vdso may have been already
851 * disabled though.
852 */
853 if (arch_timer_this_cpu_has_cntvct_wa())
854 pr_info("CPU%d: Trapping CNTVCT access\n", smp_processor_id());
855 else
856 cntkctl |= ARCH_TIMER_USR_VCT_ACCESS_EN;
857
858 arch_timer_set_cntkctl(cntkctl);
859}
860
861static bool arch_timer_has_nonsecure_ppi(void)
862{
863 return (arch_timer_uses_ppi == ARCH_TIMER_PHYS_SECURE_PPI &&
864 arch_timer_ppi[ARCH_TIMER_PHYS_NONSECURE_PPI]);
865}
866
867static u32 check_ppi_trigger(int irq)
868{
869 u32 flags = irq_get_trigger_type(irq);
870
871 if (flags != IRQF_TRIGGER_HIGH && flags != IRQF_TRIGGER_LOW) {
872 pr_warn("WARNING: Invalid trigger for IRQ%d, assuming level low\n", irq);
873 pr_warn("WARNING: Please fix your firmware\n");
874 flags = IRQF_TRIGGER_LOW;
875 }
876
877 return flags;
878}
879
880static int arch_timer_starting_cpu(unsigned int cpu)
881{
882 struct clock_event_device *clk = this_cpu_ptr(arch_timer_evt);
883 u32 flags;
884
885 __arch_timer_setup(ARCH_TIMER_TYPE_CP15, clk);
886
887 flags = check_ppi_trigger(arch_timer_ppi[arch_timer_uses_ppi]);
888 enable_percpu_irq(arch_timer_ppi[arch_timer_uses_ppi], flags);
889
890 if (arch_timer_has_nonsecure_ppi()) {
891 flags = check_ppi_trigger(arch_timer_ppi[ARCH_TIMER_PHYS_NONSECURE_PPI]);
892 enable_percpu_irq(arch_timer_ppi[ARCH_TIMER_PHYS_NONSECURE_PPI],
893 flags);
894 }
895
896 arch_counter_set_user_access();
897 if (evtstrm_enable)
898 arch_timer_configure_evtstream();
899
900 return 0;
901}
902
903static int validate_timer_rate(void)
904{
905 if (!arch_timer_rate)
906 return -EINVAL;
907
908 /* Arch timer frequency < 1MHz can cause trouble */
909 WARN_ON(arch_timer_rate < 1000000);
910
911 return 0;
912}
913
914/*
915 * For historical reasons, when probing with DT we use whichever (non-zero)
916 * rate was probed first, and don't verify that others match. If the first node
917 * probed has a clock-frequency property, this overrides the HW register.
918 */
919static void arch_timer_of_configure_rate(u32 rate, struct device_node *np)
920{
921 /* Who has more than one independent system counter? */
922 if (arch_timer_rate)
923 return;
924
925 if (of_property_read_u32(np, "clock-frequency", &arch_timer_rate))
926 arch_timer_rate = rate;
927
928 /* Check the timer frequency. */
929 if (validate_timer_rate())
930 pr_warn("frequency not available\n");
931}
932
933static void arch_timer_banner(unsigned type)
934{
935 pr_info("%s%s%s timer(s) running at %lu.%02luMHz (%s%s%s).\n",
936 type & ARCH_TIMER_TYPE_CP15 ? "cp15" : "",
937 type == (ARCH_TIMER_TYPE_CP15 | ARCH_TIMER_TYPE_MEM) ?
938 " and " : "",
939 type & ARCH_TIMER_TYPE_MEM ? "mmio" : "",
940 (unsigned long)arch_timer_rate / 1000000,
941 (unsigned long)(arch_timer_rate / 10000) % 100,
942 type & ARCH_TIMER_TYPE_CP15 ?
943 (arch_timer_uses_ppi == ARCH_TIMER_VIRT_PPI) ? "virt" : "phys" :
944 "",
945 type == (ARCH_TIMER_TYPE_CP15 | ARCH_TIMER_TYPE_MEM) ? "/" : "",
946 type & ARCH_TIMER_TYPE_MEM ?
947 arch_timer_mem_use_virtual ? "virt" : "phys" :
948 "");
949}
950
951u32 arch_timer_get_rate(void)
952{
953 return arch_timer_rate;
954}
955
956bool arch_timer_evtstrm_available(void)
957{
958 /*
959 * We might get called from a preemptible context. This is fine
960 * because availability of the event stream should be always the same
961 * for a preemptible context and context where we might resume a task.
962 */
963 return cpumask_test_cpu(raw_smp_processor_id(), &evtstrm_available);
964}
965
966static u64 arch_counter_get_cntvct_mem(void)
967{
968 u32 vct_lo, vct_hi, tmp_hi;
969
970 do {
971 vct_hi = readl_relaxed(arch_counter_base + CNTVCT_HI);
972 vct_lo = readl_relaxed(arch_counter_base + CNTVCT_LO);
973 tmp_hi = readl_relaxed(arch_counter_base + CNTVCT_HI);
974 } while (vct_hi != tmp_hi);
975
976 return ((u64) vct_hi << 32) | vct_lo;
977}
978
979static struct arch_timer_kvm_info arch_timer_kvm_info;
980
981struct arch_timer_kvm_info *arch_timer_get_kvm_info(void)
982{
983 return &arch_timer_kvm_info;
984}
985
986static void __init arch_counter_register(unsigned type)
987{
988 u64 start_count;
989
990 /* Register the CP15 based counter if we have one */
991 if (type & ARCH_TIMER_TYPE_CP15) {
992 u64 (*rd)(void);
993
994 if ((IS_ENABLED(CONFIG_ARM64) && !is_hyp_mode_available()) ||
995 arch_timer_uses_ppi == ARCH_TIMER_VIRT_PPI) {
996 if (arch_timer_counter_has_wa())
997 rd = arch_counter_get_cntvct_stable;
998 else
999 rd = arch_counter_get_cntvct;
1000 } else {
1001 if (arch_timer_counter_has_wa())
1002 rd = arch_counter_get_cntpct_stable;
1003 else
1004 rd = arch_counter_get_cntpct;
1005 }
1006
1007 arch_timer_read_counter = rd;
1008 clocksource_counter.vdso_clock_mode = vdso_default;
1009 } else {
1010 arch_timer_read_counter = arch_counter_get_cntvct_mem;
1011 }
1012
1013 if (!arch_counter_suspend_stop)
1014 clocksource_counter.flags |= CLOCK_SOURCE_SUSPEND_NONSTOP;
1015 start_count = arch_timer_read_counter();
1016 clocksource_register_hz(&clocksource_counter, arch_timer_rate);
1017 cyclecounter.mult = clocksource_counter.mult;
1018 cyclecounter.shift = clocksource_counter.shift;
1019 timecounter_init(&arch_timer_kvm_info.timecounter,
1020 &cyclecounter, start_count);
1021
1022 /* 56 bits minimum, so we assume worst case rollover */
1023 sched_clock_register(arch_timer_read_counter, 56, arch_timer_rate);
1024}
1025
1026static void arch_timer_stop(struct clock_event_device *clk)
1027{
1028 pr_debug("disable IRQ%d cpu #%d\n", clk->irq, smp_processor_id());
1029
1030 disable_percpu_irq(arch_timer_ppi[arch_timer_uses_ppi]);
1031 if (arch_timer_has_nonsecure_ppi())
1032 disable_percpu_irq(arch_timer_ppi[ARCH_TIMER_PHYS_NONSECURE_PPI]);
1033
1034 clk->set_state_shutdown(clk);
1035}
1036
1037static int arch_timer_dying_cpu(unsigned int cpu)
1038{
1039 struct clock_event_device *clk = this_cpu_ptr(arch_timer_evt);
1040
1041 cpumask_clear_cpu(smp_processor_id(), &evtstrm_available);
1042
1043 arch_timer_stop(clk);
1044 return 0;
1045}
1046
1047#ifdef CONFIG_CPU_PM
1048static DEFINE_PER_CPU(unsigned long, saved_cntkctl);
1049static int arch_timer_cpu_pm_notify(struct notifier_block *self,
1050 unsigned long action, void *hcpu)
1051{
1052 if (action == CPU_PM_ENTER) {
1053 __this_cpu_write(saved_cntkctl, arch_timer_get_cntkctl());
1054
1055 cpumask_clear_cpu(smp_processor_id(), &evtstrm_available);
1056 } else if (action == CPU_PM_ENTER_FAILED || action == CPU_PM_EXIT) {
1057 arch_timer_set_cntkctl(__this_cpu_read(saved_cntkctl));
1058
1059 if (arch_timer_have_evtstrm_feature())
1060 cpumask_set_cpu(smp_processor_id(), &evtstrm_available);
1061 }
1062 return NOTIFY_OK;
1063}
1064
1065static struct notifier_block arch_timer_cpu_pm_notifier = {
1066 .notifier_call = arch_timer_cpu_pm_notify,
1067};
1068
1069static int __init arch_timer_cpu_pm_init(void)
1070{
1071 return cpu_pm_register_notifier(&arch_timer_cpu_pm_notifier);
1072}
1073
1074static void __init arch_timer_cpu_pm_deinit(void)
1075{
1076 WARN_ON(cpu_pm_unregister_notifier(&arch_timer_cpu_pm_notifier));
1077}
1078
1079#else
1080static int __init arch_timer_cpu_pm_init(void)
1081{
1082 return 0;
1083}
1084
1085static void __init arch_timer_cpu_pm_deinit(void)
1086{
1087}
1088#endif
1089
1090static int __init arch_timer_register(void)
1091{
1092 int err;
1093 int ppi;
1094
1095 arch_timer_evt = alloc_percpu(struct clock_event_device);
1096 if (!arch_timer_evt) {
1097 err = -ENOMEM;
1098 goto out;
1099 }
1100
1101 ppi = arch_timer_ppi[arch_timer_uses_ppi];
1102 switch (arch_timer_uses_ppi) {
1103 case ARCH_TIMER_VIRT_PPI:
1104 err = request_percpu_irq(ppi, arch_timer_handler_virt,
1105 "arch_timer", arch_timer_evt);
1106 break;
1107 case ARCH_TIMER_PHYS_SECURE_PPI:
1108 case ARCH_TIMER_PHYS_NONSECURE_PPI:
1109 err = request_percpu_irq(ppi, arch_timer_handler_phys,
1110 "arch_timer", arch_timer_evt);
1111 if (!err && arch_timer_has_nonsecure_ppi()) {
1112 ppi = arch_timer_ppi[ARCH_TIMER_PHYS_NONSECURE_PPI];
1113 err = request_percpu_irq(ppi, arch_timer_handler_phys,
1114 "arch_timer", arch_timer_evt);
1115 if (err)
1116 free_percpu_irq(arch_timer_ppi[ARCH_TIMER_PHYS_SECURE_PPI],
1117 arch_timer_evt);
1118 }
1119 break;
1120 case ARCH_TIMER_HYP_PPI:
1121 err = request_percpu_irq(ppi, arch_timer_handler_phys,
1122 "arch_timer", arch_timer_evt);
1123 break;
1124 default:
1125 BUG();
1126 }
1127
1128 if (err) {
1129 pr_err("can't register interrupt %d (%d)\n", ppi, err);
1130 goto out_free;
1131 }
1132
1133 err = arch_timer_cpu_pm_init();
1134 if (err)
1135 goto out_unreg_notify;
1136
1137 /* Register and immediately configure the timer on the boot CPU */
1138 err = cpuhp_setup_state(CPUHP_AP_ARM_ARCH_TIMER_STARTING,
1139 "clockevents/arm/arch_timer:starting",
1140 arch_timer_starting_cpu, arch_timer_dying_cpu);
1141 if (err)
1142 goto out_unreg_cpupm;
1143 return 0;
1144
1145out_unreg_cpupm:
1146 arch_timer_cpu_pm_deinit();
1147
1148out_unreg_notify:
1149 free_percpu_irq(arch_timer_ppi[arch_timer_uses_ppi], arch_timer_evt);
1150 if (arch_timer_has_nonsecure_ppi())
1151 free_percpu_irq(arch_timer_ppi[ARCH_TIMER_PHYS_NONSECURE_PPI],
1152 arch_timer_evt);
1153
1154out_free:
1155 free_percpu(arch_timer_evt);
1156out:
1157 return err;
1158}
1159
1160static int __init arch_timer_mem_register(void __iomem *base, unsigned int irq)
1161{
1162 int ret;
1163 irq_handler_t func;
1164 struct arch_timer *t;
1165
1166 t = kzalloc(sizeof(*t), GFP_KERNEL);
1167 if (!t)
1168 return -ENOMEM;
1169
1170 t->base = base;
1171 t->evt.irq = irq;
1172 __arch_timer_setup(ARCH_TIMER_TYPE_MEM, &t->evt);
1173
1174 if (arch_timer_mem_use_virtual)
1175 func = arch_timer_handler_virt_mem;
1176 else
1177 func = arch_timer_handler_phys_mem;
1178
1179 ret = request_irq(irq, func, IRQF_TIMER, "arch_mem_timer", &t->evt);
1180 if (ret) {
1181 pr_err("Failed to request mem timer irq\n");
1182 kfree(t);
1183 }
1184
1185 return ret;
1186}
1187
1188static const struct of_device_id arch_timer_of_match[] __initconst = {
1189 { .compatible = "arm,armv7-timer", },
1190 { .compatible = "arm,armv8-timer", },
1191 {},
1192};
1193
1194static const struct of_device_id arch_timer_mem_of_match[] __initconst = {
1195 { .compatible = "arm,armv7-timer-mem", },
1196 {},
1197};
1198
1199static bool __init arch_timer_needs_of_probing(void)
1200{
1201 struct device_node *dn;
1202 bool needs_probing = false;
1203 unsigned int mask = ARCH_TIMER_TYPE_CP15 | ARCH_TIMER_TYPE_MEM;
1204
1205 /* We have two timers, and both device-tree nodes are probed. */
1206 if ((arch_timers_present & mask) == mask)
1207 return false;
1208
1209 /*
1210 * Only one type of timer is probed,
1211 * check if we have another type of timer node in device-tree.
1212 */
1213 if (arch_timers_present & ARCH_TIMER_TYPE_CP15)
1214 dn = of_find_matching_node(NULL, arch_timer_mem_of_match);
1215 else
1216 dn = of_find_matching_node(NULL, arch_timer_of_match);
1217
1218 if (dn && of_device_is_available(dn))
1219 needs_probing = true;
1220
1221 of_node_put(dn);
1222
1223 return needs_probing;
1224}
1225
1226static int __init arch_timer_common_init(void)
1227{
1228 arch_timer_banner(arch_timers_present);
1229 arch_counter_register(arch_timers_present);
1230 return arch_timer_arch_init();
1231}
1232
1233/**
1234 * arch_timer_select_ppi() - Select suitable PPI for the current system.
1235 *
1236 * If HYP mode is available, we know that the physical timer
1237 * has been configured to be accessible from PL1. Use it, so
1238 * that a guest can use the virtual timer instead.
1239 *
1240 * On ARMv8.1 with VH extensions, the kernel runs in HYP. VHE
1241 * accesses to CNTP_*_EL1 registers are silently redirected to
1242 * their CNTHP_*_EL2 counterparts, and use a different PPI
1243 * number.
1244 *
1245 * If no interrupt provided for virtual timer, we'll have to
1246 * stick to the physical timer. It'd better be accessible...
1247 * For arm64 we never use the secure interrupt.
1248 *
1249 * Return: a suitable PPI type for the current system.
1250 */
1251static enum arch_timer_ppi_nr __init arch_timer_select_ppi(void)
1252{
1253 if (is_kernel_in_hyp_mode())
1254 return ARCH_TIMER_HYP_PPI;
1255
1256 if (!is_hyp_mode_available() && arch_timer_ppi[ARCH_TIMER_VIRT_PPI])
1257 return ARCH_TIMER_VIRT_PPI;
1258
1259 if (IS_ENABLED(CONFIG_ARM64))
1260 return ARCH_TIMER_PHYS_NONSECURE_PPI;
1261
1262 return ARCH_TIMER_PHYS_SECURE_PPI;
1263}
1264
1265static void __init arch_timer_populate_kvm_info(void)
1266{
1267 arch_timer_kvm_info.virtual_irq = arch_timer_ppi[ARCH_TIMER_VIRT_PPI];
1268 if (is_kernel_in_hyp_mode())
1269 arch_timer_kvm_info.physical_irq = arch_timer_ppi[ARCH_TIMER_PHYS_NONSECURE_PPI];
1270}
1271
1272static int __init arch_timer_of_init(struct device_node *np)
1273{
1274 int i, ret;
1275 u32 rate;
1276
1277 if (arch_timers_present & ARCH_TIMER_TYPE_CP15) {
1278 pr_warn("multiple nodes in dt, skipping\n");
1279 return 0;
1280 }
1281
1282 arch_timers_present |= ARCH_TIMER_TYPE_CP15;
1283 for (i = ARCH_TIMER_PHYS_SECURE_PPI; i < ARCH_TIMER_MAX_TIMER_PPI; i++)
1284 arch_timer_ppi[i] = irq_of_parse_and_map(np, i);
1285
1286 arch_timer_populate_kvm_info();
1287
1288 rate = arch_timer_get_cntfrq();
1289 arch_timer_of_configure_rate(rate, np);
1290
1291 arch_timer_c3stop = !of_property_read_bool(np, "always-on");
1292
1293 /* Check for globally applicable workarounds */
1294 arch_timer_check_ool_workaround(ate_match_dt, np);
1295
1296 /*
1297 * If we cannot rely on firmware initializing the timer registers then
1298 * we should use the physical timers instead.
1299 */
1300 if (IS_ENABLED(CONFIG_ARM) &&
1301 of_property_read_bool(np, "arm,cpu-registers-not-fw-configured"))
1302 arch_timer_uses_ppi = ARCH_TIMER_PHYS_SECURE_PPI;
1303 else
1304 arch_timer_uses_ppi = arch_timer_select_ppi();
1305
1306 if (!arch_timer_ppi[arch_timer_uses_ppi]) {
1307 pr_err("No interrupt available, giving up\n");
1308 return -EINVAL;
1309 }
1310
1311 /* On some systems, the counter stops ticking when in suspend. */
1312 arch_counter_suspend_stop = of_property_read_bool(np,
1313 "arm,no-tick-in-suspend");
1314
1315 ret = arch_timer_register();
1316 if (ret)
1317 return ret;
1318
1319 if (arch_timer_needs_of_probing())
1320 return 0;
1321
1322 return arch_timer_common_init();
1323}
1324TIMER_OF_DECLARE(armv7_arch_timer, "arm,armv7-timer", arch_timer_of_init);
1325TIMER_OF_DECLARE(armv8_arch_timer, "arm,armv8-timer", arch_timer_of_init);
1326
1327static u32 __init
1328arch_timer_mem_frame_get_cntfrq(struct arch_timer_mem_frame *frame)
1329{
1330 void __iomem *base;
1331 u32 rate;
1332
1333 base = ioremap(frame->cntbase, frame->size);
1334 if (!base) {
1335 pr_err("Unable to map frame @ %pa\n", &frame->cntbase);
1336 return 0;
1337 }
1338
1339 rate = readl_relaxed(base + CNTFRQ);
1340
1341 iounmap(base);
1342
1343 return rate;
1344}
1345
1346static struct arch_timer_mem_frame * __init
1347arch_timer_mem_find_best_frame(struct arch_timer_mem *timer_mem)
1348{
1349 struct arch_timer_mem_frame *frame, *best_frame = NULL;
1350 void __iomem *cntctlbase;
1351 u32 cnttidr;
1352 int i;
1353
1354 cntctlbase = ioremap(timer_mem->cntctlbase, timer_mem->size);
1355 if (!cntctlbase) {
1356 pr_err("Can't map CNTCTLBase @ %pa\n",
1357 &timer_mem->cntctlbase);
1358 return NULL;
1359 }
1360
1361 cnttidr = readl_relaxed(cntctlbase + CNTTIDR);
1362
1363 /*
1364 * Try to find a virtual capable frame. Otherwise fall back to a
1365 * physical capable frame.
1366 */
1367 for (i = 0; i < ARCH_TIMER_MEM_MAX_FRAMES; i++) {
1368 u32 cntacr = CNTACR_RFRQ | CNTACR_RWPT | CNTACR_RPCT |
1369 CNTACR_RWVT | CNTACR_RVOFF | CNTACR_RVCT;
1370
1371 frame = &timer_mem->frame[i];
1372 if (!frame->valid)
1373 continue;
1374
1375 /* Try enabling everything, and see what sticks */
1376 writel_relaxed(cntacr, cntctlbase + CNTACR(i));
1377 cntacr = readl_relaxed(cntctlbase + CNTACR(i));
1378
1379 if ((cnttidr & CNTTIDR_VIRT(i)) &&
1380 !(~cntacr & (CNTACR_RWVT | CNTACR_RVCT))) {
1381 best_frame = frame;
1382 arch_timer_mem_use_virtual = true;
1383 break;
1384 }
1385
1386 if (~cntacr & (CNTACR_RWPT | CNTACR_RPCT))
1387 continue;
1388
1389 best_frame = frame;
1390 }
1391
1392 iounmap(cntctlbase);
1393
1394 return best_frame;
1395}
1396
1397static int __init
1398arch_timer_mem_frame_register(struct arch_timer_mem_frame *frame)
1399{
1400 void __iomem *base;
1401 int ret, irq = 0;
1402
1403 if (arch_timer_mem_use_virtual)
1404 irq = frame->virt_irq;
1405 else
1406 irq = frame->phys_irq;
1407
1408 if (!irq) {
1409 pr_err("Frame missing %s irq.\n",
1410 arch_timer_mem_use_virtual ? "virt" : "phys");
1411 return -EINVAL;
1412 }
1413
1414 if (!request_mem_region(frame->cntbase, frame->size,
1415 "arch_mem_timer"))
1416 return -EBUSY;
1417
1418 base = ioremap(frame->cntbase, frame->size);
1419 if (!base) {
1420 pr_err("Can't map frame's registers\n");
1421 return -ENXIO;
1422 }
1423
1424 ret = arch_timer_mem_register(base, irq);
1425 if (ret) {
1426 iounmap(base);
1427 return ret;
1428 }
1429
1430 arch_counter_base = base;
1431 arch_timers_present |= ARCH_TIMER_TYPE_MEM;
1432
1433 return 0;
1434}
1435
1436static int __init arch_timer_mem_of_init(struct device_node *np)
1437{
1438 struct arch_timer_mem *timer_mem;
1439 struct arch_timer_mem_frame *frame;
1440 struct device_node *frame_node;
1441 struct resource res;
1442 int ret = -EINVAL;
1443 u32 rate;
1444
1445 timer_mem = kzalloc(sizeof(*timer_mem), GFP_KERNEL);
1446 if (!timer_mem)
1447 return -ENOMEM;
1448
1449 if (of_address_to_resource(np, 0, &res))
1450 goto out;
1451 timer_mem->cntctlbase = res.start;
1452 timer_mem->size = resource_size(&res);
1453
1454 for_each_available_child_of_node(np, frame_node) {
1455 u32 n;
1456 struct arch_timer_mem_frame *frame;
1457
1458 if (of_property_read_u32(frame_node, "frame-number", &n)) {
1459 pr_err(FW_BUG "Missing frame-number.\n");
1460 of_node_put(frame_node);
1461 goto out;
1462 }
1463 if (n >= ARCH_TIMER_MEM_MAX_FRAMES) {
1464 pr_err(FW_BUG "Wrong frame-number, only 0-%u are permitted.\n",
1465 ARCH_TIMER_MEM_MAX_FRAMES - 1);
1466 of_node_put(frame_node);
1467 goto out;
1468 }
1469 frame = &timer_mem->frame[n];
1470
1471 if (frame->valid) {
1472 pr_err(FW_BUG "Duplicated frame-number.\n");
1473 of_node_put(frame_node);
1474 goto out;
1475 }
1476
1477 if (of_address_to_resource(frame_node, 0, &res)) {
1478 of_node_put(frame_node);
1479 goto out;
1480 }
1481 frame->cntbase = res.start;
1482 frame->size = resource_size(&res);
1483
1484 frame->virt_irq = irq_of_parse_and_map(frame_node,
1485 ARCH_TIMER_VIRT_SPI);
1486 frame->phys_irq = irq_of_parse_and_map(frame_node,
1487 ARCH_TIMER_PHYS_SPI);
1488
1489 frame->valid = true;
1490 }
1491
1492 frame = arch_timer_mem_find_best_frame(timer_mem);
1493 if (!frame) {
1494 pr_err("Unable to find a suitable frame in timer @ %pa\n",
1495 &timer_mem->cntctlbase);
1496 ret = -EINVAL;
1497 goto out;
1498 }
1499
1500 rate = arch_timer_mem_frame_get_cntfrq(frame);
1501 arch_timer_of_configure_rate(rate, np);
1502
1503 ret = arch_timer_mem_frame_register(frame);
1504 if (!ret && !arch_timer_needs_of_probing())
1505 ret = arch_timer_common_init();
1506out:
1507 kfree(timer_mem);
1508 return ret;
1509}
1510TIMER_OF_DECLARE(armv7_arch_timer_mem, "arm,armv7-timer-mem",
1511 arch_timer_mem_of_init);
1512
1513#ifdef CONFIG_ACPI_GTDT
1514static int __init
1515arch_timer_mem_verify_cntfrq(struct arch_timer_mem *timer_mem)
1516{
1517 struct arch_timer_mem_frame *frame;
1518 u32 rate;
1519 int i;
1520
1521 for (i = 0; i < ARCH_TIMER_MEM_MAX_FRAMES; i++) {
1522 frame = &timer_mem->frame[i];
1523
1524 if (!frame->valid)
1525 continue;
1526
1527 rate = arch_timer_mem_frame_get_cntfrq(frame);
1528 if (rate == arch_timer_rate)
1529 continue;
1530
1531 pr_err(FW_BUG "CNTFRQ mismatch: frame @ %pa: (0x%08lx), CPU: (0x%08lx)\n",
1532 &frame->cntbase,
1533 (unsigned long)rate, (unsigned long)arch_timer_rate);
1534
1535 return -EINVAL;
1536 }
1537
1538 return 0;
1539}
1540
1541static int __init arch_timer_mem_acpi_init(int platform_timer_count)
1542{
1543 struct arch_timer_mem *timers, *timer;
1544 struct arch_timer_mem_frame *frame, *best_frame = NULL;
1545 int timer_count, i, ret = 0;
1546
1547 timers = kcalloc(platform_timer_count, sizeof(*timers),
1548 GFP_KERNEL);
1549 if (!timers)
1550 return -ENOMEM;
1551
1552 ret = acpi_arch_timer_mem_init(timers, &timer_count);
1553 if (ret || !timer_count)
1554 goto out;
1555
1556 /*
1557 * While unlikely, it's theoretically possible that none of the frames
1558 * in a timer expose the combination of feature we want.
1559 */
1560 for (i = 0; i < timer_count; i++) {
1561 timer = &timers[i];
1562
1563 frame = arch_timer_mem_find_best_frame(timer);
1564 if (!best_frame)
1565 best_frame = frame;
1566
1567 ret = arch_timer_mem_verify_cntfrq(timer);
1568 if (ret) {
1569 pr_err("Disabling MMIO timers due to CNTFRQ mismatch\n");
1570 goto out;
1571 }
1572
1573 if (!best_frame) /* implies !frame */
1574 /*
1575 * Only complain about missing suitable frames if we
1576 * haven't already found one in a previous iteration.
1577 */
1578 pr_err("Unable to find a suitable frame in timer @ %pa\n",
1579 &timer->cntctlbase);
1580 }
1581
1582 if (best_frame)
1583 ret = arch_timer_mem_frame_register(best_frame);
1584out:
1585 kfree(timers);
1586 return ret;
1587}
1588
1589/* Initialize per-processor generic timer and memory-mapped timer(if present) */
1590static int __init arch_timer_acpi_init(struct acpi_table_header *table)
1591{
1592 int ret, platform_timer_count;
1593
1594 if (arch_timers_present & ARCH_TIMER_TYPE_CP15) {
1595 pr_warn("already initialized, skipping\n");
1596 return -EINVAL;
1597 }
1598
1599 arch_timers_present |= ARCH_TIMER_TYPE_CP15;
1600
1601 ret = acpi_gtdt_init(table, &platform_timer_count);
1602 if (ret)
1603 return ret;
1604
1605 arch_timer_ppi[ARCH_TIMER_PHYS_NONSECURE_PPI] =
1606 acpi_gtdt_map_ppi(ARCH_TIMER_PHYS_NONSECURE_PPI);
1607
1608 arch_timer_ppi[ARCH_TIMER_VIRT_PPI] =
1609 acpi_gtdt_map_ppi(ARCH_TIMER_VIRT_PPI);
1610
1611 arch_timer_ppi[ARCH_TIMER_HYP_PPI] =
1612 acpi_gtdt_map_ppi(ARCH_TIMER_HYP_PPI);
1613
1614 arch_timer_populate_kvm_info();
1615
1616 /*
1617 * When probing via ACPI, we have no mechanism to override the sysreg
1618 * CNTFRQ value. This *must* be correct.
1619 */
1620 arch_timer_rate = arch_timer_get_cntfrq();
1621 ret = validate_timer_rate();
1622 if (ret) {
1623 pr_err(FW_BUG "frequency not available.\n");
1624 return ret;
1625 }
1626
1627 arch_timer_uses_ppi = arch_timer_select_ppi();
1628 if (!arch_timer_ppi[arch_timer_uses_ppi]) {
1629 pr_err("No interrupt available, giving up\n");
1630 return -EINVAL;
1631 }
1632
1633 /* Always-on capability */
1634 arch_timer_c3stop = acpi_gtdt_c3stop(arch_timer_uses_ppi);
1635
1636 /* Check for globally applicable workarounds */
1637 arch_timer_check_ool_workaround(ate_match_acpi_oem_info, table);
1638
1639 ret = arch_timer_register();
1640 if (ret)
1641 return ret;
1642
1643 if (platform_timer_count &&
1644 arch_timer_mem_acpi_init(platform_timer_count))
1645 pr_err("Failed to initialize memory-mapped timer.\n");
1646
1647 return arch_timer_common_init();
1648}
1649TIMER_ACPI_DECLARE(arch_timer, ACPI_SIG_GTDT, arch_timer_acpi_init);
1650#endif
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * linux/drivers/clocksource/arm_arch_timer.c
4 *
5 * Copyright (C) 2011 ARM Ltd.
6 * All Rights Reserved
7 */
8
9#define pr_fmt(fmt) "arch_timer: " fmt
10
11#include <linux/init.h>
12#include <linux/kernel.h>
13#include <linux/device.h>
14#include <linux/smp.h>
15#include <linux/cpu.h>
16#include <linux/cpu_pm.h>
17#include <linux/clockchips.h>
18#include <linux/clocksource.h>
19#include <linux/clocksource_ids.h>
20#include <linux/interrupt.h>
21#include <linux/kstrtox.h>
22#include <linux/of_irq.h>
23#include <linux/of_address.h>
24#include <linux/io.h>
25#include <linux/slab.h>
26#include <linux/sched/clock.h>
27#include <linux/sched_clock.h>
28#include <linux/acpi.h>
29#include <linux/arm-smccc.h>
30#include <linux/ptp_kvm.h>
31
32#include <asm/arch_timer.h>
33#include <asm/virt.h>
34
35#include <clocksource/arm_arch_timer.h>
36
37#define CNTTIDR 0x08
38#define CNTTIDR_VIRT(n) (BIT(1) << ((n) * 4))
39
40#define CNTACR(n) (0x40 + ((n) * 4))
41#define CNTACR_RPCT BIT(0)
42#define CNTACR_RVCT BIT(1)
43#define CNTACR_RFRQ BIT(2)
44#define CNTACR_RVOFF BIT(3)
45#define CNTACR_RWVT BIT(4)
46#define CNTACR_RWPT BIT(5)
47
48#define CNTPCT_LO 0x00
49#define CNTVCT_LO 0x08
50#define CNTFRQ 0x10
51#define CNTP_CVAL_LO 0x20
52#define CNTP_CTL 0x2c
53#define CNTV_CVAL_LO 0x30
54#define CNTV_CTL 0x3c
55
56/*
57 * The minimum amount of time a generic counter is guaranteed to not roll over
58 * (40 years)
59 */
60#define MIN_ROLLOVER_SECS (40ULL * 365 * 24 * 3600)
61
62static unsigned arch_timers_present __initdata;
63
64struct arch_timer {
65 void __iomem *base;
66 struct clock_event_device evt;
67};
68
69static struct arch_timer *arch_timer_mem __ro_after_init;
70
71#define to_arch_timer(e) container_of(e, struct arch_timer, evt)
72
73static u32 arch_timer_rate __ro_after_init;
74static int arch_timer_ppi[ARCH_TIMER_MAX_TIMER_PPI] __ro_after_init;
75
76static const char *arch_timer_ppi_names[ARCH_TIMER_MAX_TIMER_PPI] = {
77 [ARCH_TIMER_PHYS_SECURE_PPI] = "sec-phys",
78 [ARCH_TIMER_PHYS_NONSECURE_PPI] = "phys",
79 [ARCH_TIMER_VIRT_PPI] = "virt",
80 [ARCH_TIMER_HYP_PPI] = "hyp-phys",
81 [ARCH_TIMER_HYP_VIRT_PPI] = "hyp-virt",
82};
83
84static struct clock_event_device __percpu *arch_timer_evt;
85
86static enum arch_timer_ppi_nr arch_timer_uses_ppi __ro_after_init = ARCH_TIMER_VIRT_PPI;
87static bool arch_timer_c3stop __ro_after_init;
88static bool arch_timer_mem_use_virtual __ro_after_init;
89static bool arch_counter_suspend_stop __ro_after_init;
90#ifdef CONFIG_GENERIC_GETTIMEOFDAY
91static enum vdso_clock_mode vdso_default = VDSO_CLOCKMODE_ARCHTIMER;
92#else
93static enum vdso_clock_mode vdso_default = VDSO_CLOCKMODE_NONE;
94#endif /* CONFIG_GENERIC_GETTIMEOFDAY */
95
96static cpumask_t evtstrm_available = CPU_MASK_NONE;
97static bool evtstrm_enable __ro_after_init = IS_ENABLED(CONFIG_ARM_ARCH_TIMER_EVTSTREAM);
98
99static int __init early_evtstrm_cfg(char *buf)
100{
101 return kstrtobool(buf, &evtstrm_enable);
102}
103early_param("clocksource.arm_arch_timer.evtstrm", early_evtstrm_cfg);
104
105/*
106 * Makes an educated guess at a valid counter width based on the Generic Timer
107 * specification. Of note:
108 * 1) the system counter is at least 56 bits wide
109 * 2) a roll-over time of not less than 40 years
110 *
111 * See 'ARM DDI 0487G.a D11.1.2 ("The system counter")' for more details.
112 */
113static int arch_counter_get_width(void)
114{
115 u64 min_cycles = MIN_ROLLOVER_SECS * arch_timer_rate;
116
117 /* guarantee the returned width is within the valid range */
118 return clamp_val(ilog2(min_cycles - 1) + 1, 56, 64);
119}
120
121/*
122 * Architected system timer support.
123 */
124
125static __always_inline
126void arch_timer_reg_write(int access, enum arch_timer_reg reg, u64 val,
127 struct clock_event_device *clk)
128{
129 if (access == ARCH_TIMER_MEM_PHYS_ACCESS) {
130 struct arch_timer *timer = to_arch_timer(clk);
131 switch (reg) {
132 case ARCH_TIMER_REG_CTRL:
133 writel_relaxed((u32)val, timer->base + CNTP_CTL);
134 break;
135 case ARCH_TIMER_REG_CVAL:
136 /*
137 * Not guaranteed to be atomic, so the timer
138 * must be disabled at this point.
139 */
140 writeq_relaxed(val, timer->base + CNTP_CVAL_LO);
141 break;
142 default:
143 BUILD_BUG();
144 }
145 } else if (access == ARCH_TIMER_MEM_VIRT_ACCESS) {
146 struct arch_timer *timer = to_arch_timer(clk);
147 switch (reg) {
148 case ARCH_TIMER_REG_CTRL:
149 writel_relaxed((u32)val, timer->base + CNTV_CTL);
150 break;
151 case ARCH_TIMER_REG_CVAL:
152 /* Same restriction as above */
153 writeq_relaxed(val, timer->base + CNTV_CVAL_LO);
154 break;
155 default:
156 BUILD_BUG();
157 }
158 } else {
159 arch_timer_reg_write_cp15(access, reg, val);
160 }
161}
162
163static __always_inline
164u32 arch_timer_reg_read(int access, enum arch_timer_reg reg,
165 struct clock_event_device *clk)
166{
167 u32 val;
168
169 if (access == ARCH_TIMER_MEM_PHYS_ACCESS) {
170 struct arch_timer *timer = to_arch_timer(clk);
171 switch (reg) {
172 case ARCH_TIMER_REG_CTRL:
173 val = readl_relaxed(timer->base + CNTP_CTL);
174 break;
175 default:
176 BUILD_BUG();
177 }
178 } else if (access == ARCH_TIMER_MEM_VIRT_ACCESS) {
179 struct arch_timer *timer = to_arch_timer(clk);
180 switch (reg) {
181 case ARCH_TIMER_REG_CTRL:
182 val = readl_relaxed(timer->base + CNTV_CTL);
183 break;
184 default:
185 BUILD_BUG();
186 }
187 } else {
188 val = arch_timer_reg_read_cp15(access, reg);
189 }
190
191 return val;
192}
193
194static noinstr u64 raw_counter_get_cntpct_stable(void)
195{
196 return __arch_counter_get_cntpct_stable();
197}
198
199static notrace u64 arch_counter_get_cntpct_stable(void)
200{
201 u64 val;
202 preempt_disable_notrace();
203 val = __arch_counter_get_cntpct_stable();
204 preempt_enable_notrace();
205 return val;
206}
207
208static noinstr u64 arch_counter_get_cntpct(void)
209{
210 return __arch_counter_get_cntpct();
211}
212
213static noinstr u64 raw_counter_get_cntvct_stable(void)
214{
215 return __arch_counter_get_cntvct_stable();
216}
217
218static notrace u64 arch_counter_get_cntvct_stable(void)
219{
220 u64 val;
221 preempt_disable_notrace();
222 val = __arch_counter_get_cntvct_stable();
223 preempt_enable_notrace();
224 return val;
225}
226
227static noinstr u64 arch_counter_get_cntvct(void)
228{
229 return __arch_counter_get_cntvct();
230}
231
232/*
233 * Default to cp15 based access because arm64 uses this function for
234 * sched_clock() before DT is probed and the cp15 method is guaranteed
235 * to exist on arm64. arm doesn't use this before DT is probed so even
236 * if we don't have the cp15 accessors we won't have a problem.
237 */
238u64 (*arch_timer_read_counter)(void) __ro_after_init = arch_counter_get_cntvct;
239EXPORT_SYMBOL_GPL(arch_timer_read_counter);
240
241static u64 arch_counter_read(struct clocksource *cs)
242{
243 return arch_timer_read_counter();
244}
245
246static u64 arch_counter_read_cc(const struct cyclecounter *cc)
247{
248 return arch_timer_read_counter();
249}
250
251static struct clocksource clocksource_counter = {
252 .name = "arch_sys_counter",
253 .id = CSID_ARM_ARCH_COUNTER,
254 .rating = 400,
255 .read = arch_counter_read,
256 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
257};
258
259static struct cyclecounter cyclecounter __ro_after_init = {
260 .read = arch_counter_read_cc,
261};
262
263struct ate_acpi_oem_info {
264 char oem_id[ACPI_OEM_ID_SIZE + 1];
265 char oem_table_id[ACPI_OEM_TABLE_ID_SIZE + 1];
266 u32 oem_revision;
267};
268
269#ifdef CONFIG_FSL_ERRATUM_A008585
270/*
271 * The number of retries is an arbitrary value well beyond the highest number
272 * of iterations the loop has been observed to take.
273 */
274#define __fsl_a008585_read_reg(reg) ({ \
275 u64 _old, _new; \
276 int _retries = 200; \
277 \
278 do { \
279 _old = read_sysreg(reg); \
280 _new = read_sysreg(reg); \
281 _retries--; \
282 } while (unlikely(_old != _new) && _retries); \
283 \
284 WARN_ON_ONCE(!_retries); \
285 _new; \
286})
287
288static u64 notrace fsl_a008585_read_cntpct_el0(void)
289{
290 return __fsl_a008585_read_reg(cntpct_el0);
291}
292
293static u64 notrace fsl_a008585_read_cntvct_el0(void)
294{
295 return __fsl_a008585_read_reg(cntvct_el0);
296}
297#endif
298
299#ifdef CONFIG_HISILICON_ERRATUM_161010101
300/*
301 * Verify whether the value of the second read is larger than the first by
302 * less than 32 is the only way to confirm the value is correct, so clear the
303 * lower 5 bits to check whether the difference is greater than 32 or not.
304 * Theoretically the erratum should not occur more than twice in succession
305 * when reading the system counter, but it is possible that some interrupts
306 * may lead to more than twice read errors, triggering the warning, so setting
307 * the number of retries far beyond the number of iterations the loop has been
308 * observed to take.
309 */
310#define __hisi_161010101_read_reg(reg) ({ \
311 u64 _old, _new; \
312 int _retries = 50; \
313 \
314 do { \
315 _old = read_sysreg(reg); \
316 _new = read_sysreg(reg); \
317 _retries--; \
318 } while (unlikely((_new - _old) >> 5) && _retries); \
319 \
320 WARN_ON_ONCE(!_retries); \
321 _new; \
322})
323
324static u64 notrace hisi_161010101_read_cntpct_el0(void)
325{
326 return __hisi_161010101_read_reg(cntpct_el0);
327}
328
329static u64 notrace hisi_161010101_read_cntvct_el0(void)
330{
331 return __hisi_161010101_read_reg(cntvct_el0);
332}
333
334static const struct ate_acpi_oem_info hisi_161010101_oem_info[] = {
335 /*
336 * Note that trailing spaces are required to properly match
337 * the OEM table information.
338 */
339 {
340 .oem_id = "HISI ",
341 .oem_table_id = "HIP05 ",
342 .oem_revision = 0,
343 },
344 {
345 .oem_id = "HISI ",
346 .oem_table_id = "HIP06 ",
347 .oem_revision = 0,
348 },
349 {
350 .oem_id = "HISI ",
351 .oem_table_id = "HIP07 ",
352 .oem_revision = 0,
353 },
354 { /* Sentinel indicating the end of the OEM array */ },
355};
356#endif
357
358#ifdef CONFIG_ARM64_ERRATUM_858921
359static u64 notrace arm64_858921_read_cntpct_el0(void)
360{
361 u64 old, new;
362
363 old = read_sysreg(cntpct_el0);
364 new = read_sysreg(cntpct_el0);
365 return (((old ^ new) >> 32) & 1) ? old : new;
366}
367
368static u64 notrace arm64_858921_read_cntvct_el0(void)
369{
370 u64 old, new;
371
372 old = read_sysreg(cntvct_el0);
373 new = read_sysreg(cntvct_el0);
374 return (((old ^ new) >> 32) & 1) ? old : new;
375}
376#endif
377
378#ifdef CONFIG_SUN50I_ERRATUM_UNKNOWN1
379/*
380 * The low bits of the counter registers are indeterminate while bit 10 or
381 * greater is rolling over. Since the counter value can jump both backward
382 * (7ff -> 000 -> 800) and forward (7ff -> fff -> 800), ignore register values
383 * with all ones or all zeros in the low bits. Bound the loop by the maximum
384 * number of CPU cycles in 3 consecutive 24 MHz counter periods.
385 */
386#define __sun50i_a64_read_reg(reg) ({ \
387 u64 _val; \
388 int _retries = 150; \
389 \
390 do { \
391 _val = read_sysreg(reg); \
392 _retries--; \
393 } while (((_val + 1) & GENMASK(8, 0)) <= 1 && _retries); \
394 \
395 WARN_ON_ONCE(!_retries); \
396 _val; \
397})
398
399static u64 notrace sun50i_a64_read_cntpct_el0(void)
400{
401 return __sun50i_a64_read_reg(cntpct_el0);
402}
403
404static u64 notrace sun50i_a64_read_cntvct_el0(void)
405{
406 return __sun50i_a64_read_reg(cntvct_el0);
407}
408#endif
409
410#ifdef CONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND
411DEFINE_PER_CPU(const struct arch_timer_erratum_workaround *, timer_unstable_counter_workaround);
412EXPORT_SYMBOL_GPL(timer_unstable_counter_workaround);
413
414static atomic_t timer_unstable_counter_workaround_in_use = ATOMIC_INIT(0);
415
416/*
417 * Force the inlining of this function so that the register accesses
418 * can be themselves correctly inlined.
419 */
420static __always_inline
421void erratum_set_next_event_generic(const int access, unsigned long evt,
422 struct clock_event_device *clk)
423{
424 unsigned long ctrl;
425 u64 cval;
426
427 ctrl = arch_timer_reg_read(access, ARCH_TIMER_REG_CTRL, clk);
428 ctrl |= ARCH_TIMER_CTRL_ENABLE;
429 ctrl &= ~ARCH_TIMER_CTRL_IT_MASK;
430
431 if (access == ARCH_TIMER_PHYS_ACCESS) {
432 cval = evt + arch_counter_get_cntpct_stable();
433 write_sysreg(cval, cntp_cval_el0);
434 } else {
435 cval = evt + arch_counter_get_cntvct_stable();
436 write_sysreg(cval, cntv_cval_el0);
437 }
438
439 arch_timer_reg_write(access, ARCH_TIMER_REG_CTRL, ctrl, clk);
440}
441
442static __maybe_unused int erratum_set_next_event_virt(unsigned long evt,
443 struct clock_event_device *clk)
444{
445 erratum_set_next_event_generic(ARCH_TIMER_VIRT_ACCESS, evt, clk);
446 return 0;
447}
448
449static __maybe_unused int erratum_set_next_event_phys(unsigned long evt,
450 struct clock_event_device *clk)
451{
452 erratum_set_next_event_generic(ARCH_TIMER_PHYS_ACCESS, evt, clk);
453 return 0;
454}
455
456static const struct arch_timer_erratum_workaround ool_workarounds[] = {
457#ifdef CONFIG_FSL_ERRATUM_A008585
458 {
459 .match_type = ate_match_dt,
460 .id = "fsl,erratum-a008585",
461 .desc = "Freescale erratum a005858",
462 .read_cntpct_el0 = fsl_a008585_read_cntpct_el0,
463 .read_cntvct_el0 = fsl_a008585_read_cntvct_el0,
464 .set_next_event_phys = erratum_set_next_event_phys,
465 .set_next_event_virt = erratum_set_next_event_virt,
466 },
467#endif
468#ifdef CONFIG_HISILICON_ERRATUM_161010101
469 {
470 .match_type = ate_match_dt,
471 .id = "hisilicon,erratum-161010101",
472 .desc = "HiSilicon erratum 161010101",
473 .read_cntpct_el0 = hisi_161010101_read_cntpct_el0,
474 .read_cntvct_el0 = hisi_161010101_read_cntvct_el0,
475 .set_next_event_phys = erratum_set_next_event_phys,
476 .set_next_event_virt = erratum_set_next_event_virt,
477 },
478 {
479 .match_type = ate_match_acpi_oem_info,
480 .id = hisi_161010101_oem_info,
481 .desc = "HiSilicon erratum 161010101",
482 .read_cntpct_el0 = hisi_161010101_read_cntpct_el0,
483 .read_cntvct_el0 = hisi_161010101_read_cntvct_el0,
484 .set_next_event_phys = erratum_set_next_event_phys,
485 .set_next_event_virt = erratum_set_next_event_virt,
486 },
487#endif
488#ifdef CONFIG_ARM64_ERRATUM_858921
489 {
490 .match_type = ate_match_local_cap_id,
491 .id = (void *)ARM64_WORKAROUND_858921,
492 .desc = "ARM erratum 858921",
493 .read_cntpct_el0 = arm64_858921_read_cntpct_el0,
494 .read_cntvct_el0 = arm64_858921_read_cntvct_el0,
495 .set_next_event_phys = erratum_set_next_event_phys,
496 .set_next_event_virt = erratum_set_next_event_virt,
497 },
498#endif
499#ifdef CONFIG_SUN50I_ERRATUM_UNKNOWN1
500 {
501 .match_type = ate_match_dt,
502 .id = "allwinner,erratum-unknown1",
503 .desc = "Allwinner erratum UNKNOWN1",
504 .read_cntpct_el0 = sun50i_a64_read_cntpct_el0,
505 .read_cntvct_el0 = sun50i_a64_read_cntvct_el0,
506 .set_next_event_phys = erratum_set_next_event_phys,
507 .set_next_event_virt = erratum_set_next_event_virt,
508 },
509#endif
510#ifdef CONFIG_ARM64_ERRATUM_1418040
511 {
512 .match_type = ate_match_local_cap_id,
513 .id = (void *)ARM64_WORKAROUND_1418040,
514 .desc = "ARM erratum 1418040",
515 .disable_compat_vdso = true,
516 },
517#endif
518};
519
520typedef bool (*ate_match_fn_t)(const struct arch_timer_erratum_workaround *,
521 const void *);
522
523static
524bool arch_timer_check_dt_erratum(const struct arch_timer_erratum_workaround *wa,
525 const void *arg)
526{
527 const struct device_node *np = arg;
528
529 return of_property_read_bool(np, wa->id);
530}
531
532static
533bool arch_timer_check_local_cap_erratum(const struct arch_timer_erratum_workaround *wa,
534 const void *arg)
535{
536 return this_cpu_has_cap((uintptr_t)wa->id);
537}
538
539
540static
541bool arch_timer_check_acpi_oem_erratum(const struct arch_timer_erratum_workaround *wa,
542 const void *arg)
543{
544 static const struct ate_acpi_oem_info empty_oem_info = {};
545 const struct ate_acpi_oem_info *info = wa->id;
546 const struct acpi_table_header *table = arg;
547
548 /* Iterate over the ACPI OEM info array, looking for a match */
549 while (memcmp(info, &empty_oem_info, sizeof(*info))) {
550 if (!memcmp(info->oem_id, table->oem_id, ACPI_OEM_ID_SIZE) &&
551 !memcmp(info->oem_table_id, table->oem_table_id, ACPI_OEM_TABLE_ID_SIZE) &&
552 info->oem_revision == table->oem_revision)
553 return true;
554
555 info++;
556 }
557
558 return false;
559}
560
561static const struct arch_timer_erratum_workaround *
562arch_timer_iterate_errata(enum arch_timer_erratum_match_type type,
563 ate_match_fn_t match_fn,
564 void *arg)
565{
566 int i;
567
568 for (i = 0; i < ARRAY_SIZE(ool_workarounds); i++) {
569 if (ool_workarounds[i].match_type != type)
570 continue;
571
572 if (match_fn(&ool_workarounds[i], arg))
573 return &ool_workarounds[i];
574 }
575
576 return NULL;
577}
578
579static
580void arch_timer_enable_workaround(const struct arch_timer_erratum_workaround *wa,
581 bool local)
582{
583 int i;
584
585 if (local) {
586 __this_cpu_write(timer_unstable_counter_workaround, wa);
587 } else {
588 for_each_possible_cpu(i)
589 per_cpu(timer_unstable_counter_workaround, i) = wa;
590 }
591
592 if (wa->read_cntvct_el0 || wa->read_cntpct_el0)
593 atomic_set(&timer_unstable_counter_workaround_in_use, 1);
594
595 /*
596 * Don't use the vdso fastpath if errata require using the
597 * out-of-line counter accessor. We may change our mind pretty
598 * late in the game (with a per-CPU erratum, for example), so
599 * change both the default value and the vdso itself.
600 */
601 if (wa->read_cntvct_el0) {
602 clocksource_counter.vdso_clock_mode = VDSO_CLOCKMODE_NONE;
603 vdso_default = VDSO_CLOCKMODE_NONE;
604 } else if (wa->disable_compat_vdso && vdso_default != VDSO_CLOCKMODE_NONE) {
605 vdso_default = VDSO_CLOCKMODE_ARCHTIMER_NOCOMPAT;
606 clocksource_counter.vdso_clock_mode = vdso_default;
607 }
608}
609
610static void arch_timer_check_ool_workaround(enum arch_timer_erratum_match_type type,
611 void *arg)
612{
613 const struct arch_timer_erratum_workaround *wa, *__wa;
614 ate_match_fn_t match_fn = NULL;
615 bool local = false;
616
617 switch (type) {
618 case ate_match_dt:
619 match_fn = arch_timer_check_dt_erratum;
620 break;
621 case ate_match_local_cap_id:
622 match_fn = arch_timer_check_local_cap_erratum;
623 local = true;
624 break;
625 case ate_match_acpi_oem_info:
626 match_fn = arch_timer_check_acpi_oem_erratum;
627 break;
628 default:
629 WARN_ON(1);
630 return;
631 }
632
633 wa = arch_timer_iterate_errata(type, match_fn, arg);
634 if (!wa)
635 return;
636
637 __wa = __this_cpu_read(timer_unstable_counter_workaround);
638 if (__wa && wa != __wa)
639 pr_warn("Can't enable workaround for %s (clashes with %s\n)",
640 wa->desc, __wa->desc);
641
642 if (__wa)
643 return;
644
645 arch_timer_enable_workaround(wa, local);
646 pr_info("Enabling %s workaround for %s\n",
647 local ? "local" : "global", wa->desc);
648}
649
650static bool arch_timer_this_cpu_has_cntvct_wa(void)
651{
652 return has_erratum_handler(read_cntvct_el0);
653}
654
655static bool arch_timer_counter_has_wa(void)
656{
657 return atomic_read(&timer_unstable_counter_workaround_in_use);
658}
659#else
660#define arch_timer_check_ool_workaround(t,a) do { } while(0)
661#define arch_timer_this_cpu_has_cntvct_wa() ({false;})
662#define arch_timer_counter_has_wa() ({false;})
663#endif /* CONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND */
664
665static __always_inline irqreturn_t timer_handler(const int access,
666 struct clock_event_device *evt)
667{
668 unsigned long ctrl;
669
670 ctrl = arch_timer_reg_read(access, ARCH_TIMER_REG_CTRL, evt);
671 if (ctrl & ARCH_TIMER_CTRL_IT_STAT) {
672 ctrl |= ARCH_TIMER_CTRL_IT_MASK;
673 arch_timer_reg_write(access, ARCH_TIMER_REG_CTRL, ctrl, evt);
674 evt->event_handler(evt);
675 return IRQ_HANDLED;
676 }
677
678 return IRQ_NONE;
679}
680
681static irqreturn_t arch_timer_handler_virt(int irq, void *dev_id)
682{
683 struct clock_event_device *evt = dev_id;
684
685 return timer_handler(ARCH_TIMER_VIRT_ACCESS, evt);
686}
687
688static irqreturn_t arch_timer_handler_phys(int irq, void *dev_id)
689{
690 struct clock_event_device *evt = dev_id;
691
692 return timer_handler(ARCH_TIMER_PHYS_ACCESS, evt);
693}
694
695static irqreturn_t arch_timer_handler_phys_mem(int irq, void *dev_id)
696{
697 struct clock_event_device *evt = dev_id;
698
699 return timer_handler(ARCH_TIMER_MEM_PHYS_ACCESS, evt);
700}
701
702static irqreturn_t arch_timer_handler_virt_mem(int irq, void *dev_id)
703{
704 struct clock_event_device *evt = dev_id;
705
706 return timer_handler(ARCH_TIMER_MEM_VIRT_ACCESS, evt);
707}
708
709static __always_inline int arch_timer_shutdown(const int access,
710 struct clock_event_device *clk)
711{
712 unsigned long ctrl;
713
714 ctrl = arch_timer_reg_read(access, ARCH_TIMER_REG_CTRL, clk);
715 ctrl &= ~ARCH_TIMER_CTRL_ENABLE;
716 arch_timer_reg_write(access, ARCH_TIMER_REG_CTRL, ctrl, clk);
717
718 return 0;
719}
720
721static int arch_timer_shutdown_virt(struct clock_event_device *clk)
722{
723 return arch_timer_shutdown(ARCH_TIMER_VIRT_ACCESS, clk);
724}
725
726static int arch_timer_shutdown_phys(struct clock_event_device *clk)
727{
728 return arch_timer_shutdown(ARCH_TIMER_PHYS_ACCESS, clk);
729}
730
731static int arch_timer_shutdown_virt_mem(struct clock_event_device *clk)
732{
733 return arch_timer_shutdown(ARCH_TIMER_MEM_VIRT_ACCESS, clk);
734}
735
736static int arch_timer_shutdown_phys_mem(struct clock_event_device *clk)
737{
738 return arch_timer_shutdown(ARCH_TIMER_MEM_PHYS_ACCESS, clk);
739}
740
741static __always_inline void set_next_event(const int access, unsigned long evt,
742 struct clock_event_device *clk)
743{
744 unsigned long ctrl;
745 u64 cnt;
746
747 ctrl = arch_timer_reg_read(access, ARCH_TIMER_REG_CTRL, clk);
748 ctrl |= ARCH_TIMER_CTRL_ENABLE;
749 ctrl &= ~ARCH_TIMER_CTRL_IT_MASK;
750
751 if (access == ARCH_TIMER_PHYS_ACCESS)
752 cnt = __arch_counter_get_cntpct();
753 else
754 cnt = __arch_counter_get_cntvct();
755
756 arch_timer_reg_write(access, ARCH_TIMER_REG_CVAL, evt + cnt, clk);
757 arch_timer_reg_write(access, ARCH_TIMER_REG_CTRL, ctrl, clk);
758}
759
760static int arch_timer_set_next_event_virt(unsigned long evt,
761 struct clock_event_device *clk)
762{
763 set_next_event(ARCH_TIMER_VIRT_ACCESS, evt, clk);
764 return 0;
765}
766
767static int arch_timer_set_next_event_phys(unsigned long evt,
768 struct clock_event_device *clk)
769{
770 set_next_event(ARCH_TIMER_PHYS_ACCESS, evt, clk);
771 return 0;
772}
773
774static noinstr u64 arch_counter_get_cnt_mem(struct arch_timer *t, int offset_lo)
775{
776 u32 cnt_lo, cnt_hi, tmp_hi;
777
778 do {
779 cnt_hi = __le32_to_cpu((__le32 __force)__raw_readl(t->base + offset_lo + 4));
780 cnt_lo = __le32_to_cpu((__le32 __force)__raw_readl(t->base + offset_lo));
781 tmp_hi = __le32_to_cpu((__le32 __force)__raw_readl(t->base + offset_lo + 4));
782 } while (cnt_hi != tmp_hi);
783
784 return ((u64) cnt_hi << 32) | cnt_lo;
785}
786
787static __always_inline void set_next_event_mem(const int access, unsigned long evt,
788 struct clock_event_device *clk)
789{
790 struct arch_timer *timer = to_arch_timer(clk);
791 unsigned long ctrl;
792 u64 cnt;
793
794 ctrl = arch_timer_reg_read(access, ARCH_TIMER_REG_CTRL, clk);
795
796 /* Timer must be disabled before programming CVAL */
797 if (ctrl & ARCH_TIMER_CTRL_ENABLE) {
798 ctrl &= ~ARCH_TIMER_CTRL_ENABLE;
799 arch_timer_reg_write(access, ARCH_TIMER_REG_CTRL, ctrl, clk);
800 }
801
802 ctrl |= ARCH_TIMER_CTRL_ENABLE;
803 ctrl &= ~ARCH_TIMER_CTRL_IT_MASK;
804
805 if (access == ARCH_TIMER_MEM_VIRT_ACCESS)
806 cnt = arch_counter_get_cnt_mem(timer, CNTVCT_LO);
807 else
808 cnt = arch_counter_get_cnt_mem(timer, CNTPCT_LO);
809
810 arch_timer_reg_write(access, ARCH_TIMER_REG_CVAL, evt + cnt, clk);
811 arch_timer_reg_write(access, ARCH_TIMER_REG_CTRL, ctrl, clk);
812}
813
814static int arch_timer_set_next_event_virt_mem(unsigned long evt,
815 struct clock_event_device *clk)
816{
817 set_next_event_mem(ARCH_TIMER_MEM_VIRT_ACCESS, evt, clk);
818 return 0;
819}
820
821static int arch_timer_set_next_event_phys_mem(unsigned long evt,
822 struct clock_event_device *clk)
823{
824 set_next_event_mem(ARCH_TIMER_MEM_PHYS_ACCESS, evt, clk);
825 return 0;
826}
827
828static u64 __arch_timer_check_delta(void)
829{
830#ifdef CONFIG_ARM64
831 const struct midr_range broken_cval_midrs[] = {
832 /*
833 * XGene-1 implements CVAL in terms of TVAL, meaning
834 * that the maximum timer range is 32bit. Shame on them.
835 *
836 * Note that TVAL is signed, thus has only 31 of its
837 * 32 bits to express magnitude.
838 */
839 MIDR_REV_RANGE(MIDR_CPU_MODEL(ARM_CPU_IMP_APM,
840 APM_CPU_PART_XGENE),
841 APM_CPU_VAR_POTENZA, 0x0, 0xf),
842 {},
843 };
844
845 if (is_midr_in_range_list(read_cpuid_id(), broken_cval_midrs)) {
846 pr_warn_once("Broken CNTx_CVAL_EL1, using 31 bit TVAL instead.\n");
847 return CLOCKSOURCE_MASK(31);
848 }
849#endif
850 return CLOCKSOURCE_MASK(arch_counter_get_width());
851}
852
853static void __arch_timer_setup(unsigned type,
854 struct clock_event_device *clk)
855{
856 u64 max_delta;
857
858 clk->features = CLOCK_EVT_FEAT_ONESHOT;
859
860 if (type == ARCH_TIMER_TYPE_CP15) {
861 typeof(clk->set_next_event) sne;
862
863 arch_timer_check_ool_workaround(ate_match_local_cap_id, NULL);
864
865 if (arch_timer_c3stop)
866 clk->features |= CLOCK_EVT_FEAT_C3STOP;
867 clk->name = "arch_sys_timer";
868 clk->rating = 450;
869 clk->cpumask = cpumask_of(smp_processor_id());
870 clk->irq = arch_timer_ppi[arch_timer_uses_ppi];
871 switch (arch_timer_uses_ppi) {
872 case ARCH_TIMER_VIRT_PPI:
873 clk->set_state_shutdown = arch_timer_shutdown_virt;
874 clk->set_state_oneshot_stopped = arch_timer_shutdown_virt;
875 sne = erratum_handler(set_next_event_virt);
876 break;
877 case ARCH_TIMER_PHYS_SECURE_PPI:
878 case ARCH_TIMER_PHYS_NONSECURE_PPI:
879 case ARCH_TIMER_HYP_PPI:
880 clk->set_state_shutdown = arch_timer_shutdown_phys;
881 clk->set_state_oneshot_stopped = arch_timer_shutdown_phys;
882 sne = erratum_handler(set_next_event_phys);
883 break;
884 default:
885 BUG();
886 }
887
888 clk->set_next_event = sne;
889 max_delta = __arch_timer_check_delta();
890 } else {
891 clk->features |= CLOCK_EVT_FEAT_DYNIRQ;
892 clk->name = "arch_mem_timer";
893 clk->rating = 400;
894 clk->cpumask = cpu_possible_mask;
895 if (arch_timer_mem_use_virtual) {
896 clk->set_state_shutdown = arch_timer_shutdown_virt_mem;
897 clk->set_state_oneshot_stopped = arch_timer_shutdown_virt_mem;
898 clk->set_next_event =
899 arch_timer_set_next_event_virt_mem;
900 } else {
901 clk->set_state_shutdown = arch_timer_shutdown_phys_mem;
902 clk->set_state_oneshot_stopped = arch_timer_shutdown_phys_mem;
903 clk->set_next_event =
904 arch_timer_set_next_event_phys_mem;
905 }
906
907 max_delta = CLOCKSOURCE_MASK(56);
908 }
909
910 clk->set_state_shutdown(clk);
911
912 clockevents_config_and_register(clk, arch_timer_rate, 0xf, max_delta);
913}
914
915static void arch_timer_evtstrm_enable(unsigned int divider)
916{
917 u32 cntkctl = arch_timer_get_cntkctl();
918
919#ifdef CONFIG_ARM64
920 /* ECV is likely to require a large divider. Use the EVNTIS flag. */
921 if (cpus_have_final_cap(ARM64_HAS_ECV) && divider > 15) {
922 cntkctl |= ARCH_TIMER_EVT_INTERVAL_SCALE;
923 divider -= 8;
924 }
925#endif
926
927 divider = min(divider, 15U);
928 cntkctl &= ~ARCH_TIMER_EVT_TRIGGER_MASK;
929 /* Set the divider and enable virtual event stream */
930 cntkctl |= (divider << ARCH_TIMER_EVT_TRIGGER_SHIFT)
931 | ARCH_TIMER_VIRT_EVT_EN;
932 arch_timer_set_cntkctl(cntkctl);
933 arch_timer_set_evtstrm_feature();
934 cpumask_set_cpu(smp_processor_id(), &evtstrm_available);
935}
936
937static void arch_timer_configure_evtstream(void)
938{
939 int evt_stream_div, lsb;
940
941 /*
942 * As the event stream can at most be generated at half the frequency
943 * of the counter, use half the frequency when computing the divider.
944 */
945 evt_stream_div = arch_timer_rate / ARCH_TIMER_EVT_STREAM_FREQ / 2;
946
947 /*
948 * Find the closest power of two to the divisor. If the adjacent bit
949 * of lsb (last set bit, starts from 0) is set, then we use (lsb + 1).
950 */
951 lsb = fls(evt_stream_div) - 1;
952 if (lsb > 0 && (evt_stream_div & BIT(lsb - 1)))
953 lsb++;
954
955 /* enable event stream */
956 arch_timer_evtstrm_enable(max(0, lsb));
957}
958
959static int arch_timer_evtstrm_starting_cpu(unsigned int cpu)
960{
961 arch_timer_configure_evtstream();
962 return 0;
963}
964
965static int arch_timer_evtstrm_dying_cpu(unsigned int cpu)
966{
967 cpumask_clear_cpu(smp_processor_id(), &evtstrm_available);
968 return 0;
969}
970
971static int __init arch_timer_evtstrm_register(void)
972{
973 if (!arch_timer_evt || !evtstrm_enable)
974 return 0;
975
976 return cpuhp_setup_state(CPUHP_AP_ARM_ARCH_TIMER_EVTSTRM_STARTING,
977 "clockevents/arm/arch_timer_evtstrm:starting",
978 arch_timer_evtstrm_starting_cpu,
979 arch_timer_evtstrm_dying_cpu);
980}
981core_initcall(arch_timer_evtstrm_register);
982
983static void arch_counter_set_user_access(void)
984{
985 u32 cntkctl = arch_timer_get_cntkctl();
986
987 /* Disable user access to the timers and both counters */
988 /* Also disable virtual event stream */
989 cntkctl &= ~(ARCH_TIMER_USR_PT_ACCESS_EN
990 | ARCH_TIMER_USR_VT_ACCESS_EN
991 | ARCH_TIMER_USR_VCT_ACCESS_EN
992 | ARCH_TIMER_VIRT_EVT_EN
993 | ARCH_TIMER_USR_PCT_ACCESS_EN);
994
995 /*
996 * Enable user access to the virtual counter if it doesn't
997 * need to be workaround. The vdso may have been already
998 * disabled though.
999 */
1000 if (arch_timer_this_cpu_has_cntvct_wa())
1001 pr_info("CPU%d: Trapping CNTVCT access\n", smp_processor_id());
1002 else
1003 cntkctl |= ARCH_TIMER_USR_VCT_ACCESS_EN;
1004
1005 arch_timer_set_cntkctl(cntkctl);
1006}
1007
1008static bool arch_timer_has_nonsecure_ppi(void)
1009{
1010 return (arch_timer_uses_ppi == ARCH_TIMER_PHYS_SECURE_PPI &&
1011 arch_timer_ppi[ARCH_TIMER_PHYS_NONSECURE_PPI]);
1012}
1013
1014static u32 check_ppi_trigger(int irq)
1015{
1016 u32 flags = irq_get_trigger_type(irq);
1017
1018 if (flags != IRQF_TRIGGER_HIGH && flags != IRQF_TRIGGER_LOW) {
1019 pr_warn("WARNING: Invalid trigger for IRQ%d, assuming level low\n", irq);
1020 pr_warn("WARNING: Please fix your firmware\n");
1021 flags = IRQF_TRIGGER_LOW;
1022 }
1023
1024 return flags;
1025}
1026
1027static int arch_timer_starting_cpu(unsigned int cpu)
1028{
1029 struct clock_event_device *clk = this_cpu_ptr(arch_timer_evt);
1030 u32 flags;
1031
1032 __arch_timer_setup(ARCH_TIMER_TYPE_CP15, clk);
1033
1034 flags = check_ppi_trigger(arch_timer_ppi[arch_timer_uses_ppi]);
1035 enable_percpu_irq(arch_timer_ppi[arch_timer_uses_ppi], flags);
1036
1037 if (arch_timer_has_nonsecure_ppi()) {
1038 flags = check_ppi_trigger(arch_timer_ppi[ARCH_TIMER_PHYS_NONSECURE_PPI]);
1039 enable_percpu_irq(arch_timer_ppi[ARCH_TIMER_PHYS_NONSECURE_PPI],
1040 flags);
1041 }
1042
1043 arch_counter_set_user_access();
1044
1045 return 0;
1046}
1047
1048static int validate_timer_rate(void)
1049{
1050 if (!arch_timer_rate)
1051 return -EINVAL;
1052
1053 /* Arch timer frequency < 1MHz can cause trouble */
1054 WARN_ON(arch_timer_rate < 1000000);
1055
1056 return 0;
1057}
1058
1059/*
1060 * For historical reasons, when probing with DT we use whichever (non-zero)
1061 * rate was probed first, and don't verify that others match. If the first node
1062 * probed has a clock-frequency property, this overrides the HW register.
1063 */
1064static void __init arch_timer_of_configure_rate(u32 rate, struct device_node *np)
1065{
1066 /* Who has more than one independent system counter? */
1067 if (arch_timer_rate)
1068 return;
1069
1070 if (of_property_read_u32(np, "clock-frequency", &arch_timer_rate))
1071 arch_timer_rate = rate;
1072
1073 /* Check the timer frequency. */
1074 if (validate_timer_rate())
1075 pr_warn("frequency not available\n");
1076}
1077
1078static void __init arch_timer_banner(unsigned type)
1079{
1080 pr_info("%s%s%s timer(s) running at %lu.%02luMHz (%s%s%s).\n",
1081 type & ARCH_TIMER_TYPE_CP15 ? "cp15" : "",
1082 type == (ARCH_TIMER_TYPE_CP15 | ARCH_TIMER_TYPE_MEM) ?
1083 " and " : "",
1084 type & ARCH_TIMER_TYPE_MEM ? "mmio" : "",
1085 (unsigned long)arch_timer_rate / 1000000,
1086 (unsigned long)(arch_timer_rate / 10000) % 100,
1087 type & ARCH_TIMER_TYPE_CP15 ?
1088 (arch_timer_uses_ppi == ARCH_TIMER_VIRT_PPI) ? "virt" : "phys" :
1089 "",
1090 type == (ARCH_TIMER_TYPE_CP15 | ARCH_TIMER_TYPE_MEM) ? "/" : "",
1091 type & ARCH_TIMER_TYPE_MEM ?
1092 arch_timer_mem_use_virtual ? "virt" : "phys" :
1093 "");
1094}
1095
1096u32 arch_timer_get_rate(void)
1097{
1098 return arch_timer_rate;
1099}
1100
1101bool arch_timer_evtstrm_available(void)
1102{
1103 /*
1104 * We might get called from a preemptible context. This is fine
1105 * because availability of the event stream should be always the same
1106 * for a preemptible context and context where we might resume a task.
1107 */
1108 return cpumask_test_cpu(raw_smp_processor_id(), &evtstrm_available);
1109}
1110
1111static noinstr u64 arch_counter_get_cntvct_mem(void)
1112{
1113 return arch_counter_get_cnt_mem(arch_timer_mem, CNTVCT_LO);
1114}
1115
1116static struct arch_timer_kvm_info arch_timer_kvm_info;
1117
1118struct arch_timer_kvm_info *arch_timer_get_kvm_info(void)
1119{
1120 return &arch_timer_kvm_info;
1121}
1122
1123static void __init arch_counter_register(unsigned type)
1124{
1125 u64 (*scr)(void);
1126 u64 start_count;
1127 int width;
1128
1129 /* Register the CP15 based counter if we have one */
1130 if (type & ARCH_TIMER_TYPE_CP15) {
1131 u64 (*rd)(void);
1132
1133 if ((IS_ENABLED(CONFIG_ARM64) && !is_hyp_mode_available()) ||
1134 arch_timer_uses_ppi == ARCH_TIMER_VIRT_PPI) {
1135 if (arch_timer_counter_has_wa()) {
1136 rd = arch_counter_get_cntvct_stable;
1137 scr = raw_counter_get_cntvct_stable;
1138 } else {
1139 rd = arch_counter_get_cntvct;
1140 scr = arch_counter_get_cntvct;
1141 }
1142 } else {
1143 if (arch_timer_counter_has_wa()) {
1144 rd = arch_counter_get_cntpct_stable;
1145 scr = raw_counter_get_cntpct_stable;
1146 } else {
1147 rd = arch_counter_get_cntpct;
1148 scr = arch_counter_get_cntpct;
1149 }
1150 }
1151
1152 arch_timer_read_counter = rd;
1153 clocksource_counter.vdso_clock_mode = vdso_default;
1154 } else {
1155 arch_timer_read_counter = arch_counter_get_cntvct_mem;
1156 scr = arch_counter_get_cntvct_mem;
1157 }
1158
1159 width = arch_counter_get_width();
1160 clocksource_counter.mask = CLOCKSOURCE_MASK(width);
1161 cyclecounter.mask = CLOCKSOURCE_MASK(width);
1162
1163 if (!arch_counter_suspend_stop)
1164 clocksource_counter.flags |= CLOCK_SOURCE_SUSPEND_NONSTOP;
1165 start_count = arch_timer_read_counter();
1166 clocksource_register_hz(&clocksource_counter, arch_timer_rate);
1167 cyclecounter.mult = clocksource_counter.mult;
1168 cyclecounter.shift = clocksource_counter.shift;
1169 timecounter_init(&arch_timer_kvm_info.timecounter,
1170 &cyclecounter, start_count);
1171
1172 sched_clock_register(scr, width, arch_timer_rate);
1173}
1174
1175static void arch_timer_stop(struct clock_event_device *clk)
1176{
1177 pr_debug("disable IRQ%d cpu #%d\n", clk->irq, smp_processor_id());
1178
1179 disable_percpu_irq(arch_timer_ppi[arch_timer_uses_ppi]);
1180 if (arch_timer_has_nonsecure_ppi())
1181 disable_percpu_irq(arch_timer_ppi[ARCH_TIMER_PHYS_NONSECURE_PPI]);
1182}
1183
1184static int arch_timer_dying_cpu(unsigned int cpu)
1185{
1186 struct clock_event_device *clk = this_cpu_ptr(arch_timer_evt);
1187
1188 arch_timer_stop(clk);
1189 return 0;
1190}
1191
1192#ifdef CONFIG_CPU_PM
1193static DEFINE_PER_CPU(unsigned long, saved_cntkctl);
1194static int arch_timer_cpu_pm_notify(struct notifier_block *self,
1195 unsigned long action, void *hcpu)
1196{
1197 if (action == CPU_PM_ENTER) {
1198 __this_cpu_write(saved_cntkctl, arch_timer_get_cntkctl());
1199
1200 cpumask_clear_cpu(smp_processor_id(), &evtstrm_available);
1201 } else if (action == CPU_PM_ENTER_FAILED || action == CPU_PM_EXIT) {
1202 arch_timer_set_cntkctl(__this_cpu_read(saved_cntkctl));
1203
1204 if (arch_timer_have_evtstrm_feature())
1205 cpumask_set_cpu(smp_processor_id(), &evtstrm_available);
1206 }
1207 return NOTIFY_OK;
1208}
1209
1210static struct notifier_block arch_timer_cpu_pm_notifier = {
1211 .notifier_call = arch_timer_cpu_pm_notify,
1212};
1213
1214static int __init arch_timer_cpu_pm_init(void)
1215{
1216 return cpu_pm_register_notifier(&arch_timer_cpu_pm_notifier);
1217}
1218
1219static void __init arch_timer_cpu_pm_deinit(void)
1220{
1221 WARN_ON(cpu_pm_unregister_notifier(&arch_timer_cpu_pm_notifier));
1222}
1223
1224#else
1225static int __init arch_timer_cpu_pm_init(void)
1226{
1227 return 0;
1228}
1229
1230static void __init arch_timer_cpu_pm_deinit(void)
1231{
1232}
1233#endif
1234
1235static int __init arch_timer_register(void)
1236{
1237 int err;
1238 int ppi;
1239
1240 arch_timer_evt = alloc_percpu(struct clock_event_device);
1241 if (!arch_timer_evt) {
1242 err = -ENOMEM;
1243 goto out;
1244 }
1245
1246 ppi = arch_timer_ppi[arch_timer_uses_ppi];
1247 switch (arch_timer_uses_ppi) {
1248 case ARCH_TIMER_VIRT_PPI:
1249 err = request_percpu_irq(ppi, arch_timer_handler_virt,
1250 "arch_timer", arch_timer_evt);
1251 break;
1252 case ARCH_TIMER_PHYS_SECURE_PPI:
1253 case ARCH_TIMER_PHYS_NONSECURE_PPI:
1254 err = request_percpu_irq(ppi, arch_timer_handler_phys,
1255 "arch_timer", arch_timer_evt);
1256 if (!err && arch_timer_has_nonsecure_ppi()) {
1257 ppi = arch_timer_ppi[ARCH_TIMER_PHYS_NONSECURE_PPI];
1258 err = request_percpu_irq(ppi, arch_timer_handler_phys,
1259 "arch_timer", arch_timer_evt);
1260 if (err)
1261 free_percpu_irq(arch_timer_ppi[ARCH_TIMER_PHYS_SECURE_PPI],
1262 arch_timer_evt);
1263 }
1264 break;
1265 case ARCH_TIMER_HYP_PPI:
1266 err = request_percpu_irq(ppi, arch_timer_handler_phys,
1267 "arch_timer", arch_timer_evt);
1268 break;
1269 default:
1270 BUG();
1271 }
1272
1273 if (err) {
1274 pr_err("can't register interrupt %d (%d)\n", ppi, err);
1275 goto out_free;
1276 }
1277
1278 err = arch_timer_cpu_pm_init();
1279 if (err)
1280 goto out_unreg_notify;
1281
1282 /* Register and immediately configure the timer on the boot CPU */
1283 err = cpuhp_setup_state(CPUHP_AP_ARM_ARCH_TIMER_STARTING,
1284 "clockevents/arm/arch_timer:starting",
1285 arch_timer_starting_cpu, arch_timer_dying_cpu);
1286 if (err)
1287 goto out_unreg_cpupm;
1288 return 0;
1289
1290out_unreg_cpupm:
1291 arch_timer_cpu_pm_deinit();
1292
1293out_unreg_notify:
1294 free_percpu_irq(arch_timer_ppi[arch_timer_uses_ppi], arch_timer_evt);
1295 if (arch_timer_has_nonsecure_ppi())
1296 free_percpu_irq(arch_timer_ppi[ARCH_TIMER_PHYS_NONSECURE_PPI],
1297 arch_timer_evt);
1298
1299out_free:
1300 free_percpu(arch_timer_evt);
1301 arch_timer_evt = NULL;
1302out:
1303 return err;
1304}
1305
1306static int __init arch_timer_mem_register(void __iomem *base, unsigned int irq)
1307{
1308 int ret;
1309 irq_handler_t func;
1310
1311 arch_timer_mem = kzalloc(sizeof(*arch_timer_mem), GFP_KERNEL);
1312 if (!arch_timer_mem)
1313 return -ENOMEM;
1314
1315 arch_timer_mem->base = base;
1316 arch_timer_mem->evt.irq = irq;
1317 __arch_timer_setup(ARCH_TIMER_TYPE_MEM, &arch_timer_mem->evt);
1318
1319 if (arch_timer_mem_use_virtual)
1320 func = arch_timer_handler_virt_mem;
1321 else
1322 func = arch_timer_handler_phys_mem;
1323
1324 ret = request_irq(irq, func, IRQF_TIMER, "arch_mem_timer", &arch_timer_mem->evt);
1325 if (ret) {
1326 pr_err("Failed to request mem timer irq\n");
1327 kfree(arch_timer_mem);
1328 arch_timer_mem = NULL;
1329 }
1330
1331 return ret;
1332}
1333
1334static const struct of_device_id arch_timer_of_match[] __initconst = {
1335 { .compatible = "arm,armv7-timer", },
1336 { .compatible = "arm,armv8-timer", },
1337 {},
1338};
1339
1340static const struct of_device_id arch_timer_mem_of_match[] __initconst = {
1341 { .compatible = "arm,armv7-timer-mem", },
1342 {},
1343};
1344
1345static bool __init arch_timer_needs_of_probing(void)
1346{
1347 struct device_node *dn;
1348 bool needs_probing = false;
1349 unsigned int mask = ARCH_TIMER_TYPE_CP15 | ARCH_TIMER_TYPE_MEM;
1350
1351 /* We have two timers, and both device-tree nodes are probed. */
1352 if ((arch_timers_present & mask) == mask)
1353 return false;
1354
1355 /*
1356 * Only one type of timer is probed,
1357 * check if we have another type of timer node in device-tree.
1358 */
1359 if (arch_timers_present & ARCH_TIMER_TYPE_CP15)
1360 dn = of_find_matching_node(NULL, arch_timer_mem_of_match);
1361 else
1362 dn = of_find_matching_node(NULL, arch_timer_of_match);
1363
1364 if (dn && of_device_is_available(dn))
1365 needs_probing = true;
1366
1367 of_node_put(dn);
1368
1369 return needs_probing;
1370}
1371
1372static int __init arch_timer_common_init(void)
1373{
1374 arch_timer_banner(arch_timers_present);
1375 arch_counter_register(arch_timers_present);
1376 return arch_timer_arch_init();
1377}
1378
1379/**
1380 * arch_timer_select_ppi() - Select suitable PPI for the current system.
1381 *
1382 * If HYP mode is available, we know that the physical timer
1383 * has been configured to be accessible from PL1. Use it, so
1384 * that a guest can use the virtual timer instead.
1385 *
1386 * On ARMv8.1 with VH extensions, the kernel runs in HYP. VHE
1387 * accesses to CNTP_*_EL1 registers are silently redirected to
1388 * their CNTHP_*_EL2 counterparts, and use a different PPI
1389 * number.
1390 *
1391 * If no interrupt provided for virtual timer, we'll have to
1392 * stick to the physical timer. It'd better be accessible...
1393 * For arm64 we never use the secure interrupt.
1394 *
1395 * Return: a suitable PPI type for the current system.
1396 */
1397static enum arch_timer_ppi_nr __init arch_timer_select_ppi(void)
1398{
1399 if (is_kernel_in_hyp_mode())
1400 return ARCH_TIMER_HYP_PPI;
1401
1402 if (!is_hyp_mode_available() && arch_timer_ppi[ARCH_TIMER_VIRT_PPI])
1403 return ARCH_TIMER_VIRT_PPI;
1404
1405 if (IS_ENABLED(CONFIG_ARM64))
1406 return ARCH_TIMER_PHYS_NONSECURE_PPI;
1407
1408 return ARCH_TIMER_PHYS_SECURE_PPI;
1409}
1410
1411static void __init arch_timer_populate_kvm_info(void)
1412{
1413 arch_timer_kvm_info.virtual_irq = arch_timer_ppi[ARCH_TIMER_VIRT_PPI];
1414 if (is_kernel_in_hyp_mode())
1415 arch_timer_kvm_info.physical_irq = arch_timer_ppi[ARCH_TIMER_PHYS_NONSECURE_PPI];
1416}
1417
1418static int __init arch_timer_of_init(struct device_node *np)
1419{
1420 int i, irq, ret;
1421 u32 rate;
1422 bool has_names;
1423
1424 if (arch_timers_present & ARCH_TIMER_TYPE_CP15) {
1425 pr_warn("multiple nodes in dt, skipping\n");
1426 return 0;
1427 }
1428
1429 arch_timers_present |= ARCH_TIMER_TYPE_CP15;
1430
1431 has_names = of_property_present(np, "interrupt-names");
1432
1433 for (i = ARCH_TIMER_PHYS_SECURE_PPI; i < ARCH_TIMER_MAX_TIMER_PPI; i++) {
1434 if (has_names)
1435 irq = of_irq_get_byname(np, arch_timer_ppi_names[i]);
1436 else
1437 irq = of_irq_get(np, i);
1438 if (irq > 0)
1439 arch_timer_ppi[i] = irq;
1440 }
1441
1442 arch_timer_populate_kvm_info();
1443
1444 rate = arch_timer_get_cntfrq();
1445 arch_timer_of_configure_rate(rate, np);
1446
1447 arch_timer_c3stop = !of_property_read_bool(np, "always-on");
1448
1449 /* Check for globally applicable workarounds */
1450 arch_timer_check_ool_workaround(ate_match_dt, np);
1451
1452 /*
1453 * If we cannot rely on firmware initializing the timer registers then
1454 * we should use the physical timers instead.
1455 */
1456 if (IS_ENABLED(CONFIG_ARM) &&
1457 of_property_read_bool(np, "arm,cpu-registers-not-fw-configured"))
1458 arch_timer_uses_ppi = ARCH_TIMER_PHYS_SECURE_PPI;
1459 else
1460 arch_timer_uses_ppi = arch_timer_select_ppi();
1461
1462 if (!arch_timer_ppi[arch_timer_uses_ppi]) {
1463 pr_err("No interrupt available, giving up\n");
1464 return -EINVAL;
1465 }
1466
1467 /* On some systems, the counter stops ticking when in suspend. */
1468 arch_counter_suspend_stop = of_property_read_bool(np,
1469 "arm,no-tick-in-suspend");
1470
1471 ret = arch_timer_register();
1472 if (ret)
1473 return ret;
1474
1475 if (arch_timer_needs_of_probing())
1476 return 0;
1477
1478 return arch_timer_common_init();
1479}
1480TIMER_OF_DECLARE(armv7_arch_timer, "arm,armv7-timer", arch_timer_of_init);
1481TIMER_OF_DECLARE(armv8_arch_timer, "arm,armv8-timer", arch_timer_of_init);
1482
1483static u32 __init
1484arch_timer_mem_frame_get_cntfrq(struct arch_timer_mem_frame *frame)
1485{
1486 void __iomem *base;
1487 u32 rate;
1488
1489 base = ioremap(frame->cntbase, frame->size);
1490 if (!base) {
1491 pr_err("Unable to map frame @ %pa\n", &frame->cntbase);
1492 return 0;
1493 }
1494
1495 rate = readl_relaxed(base + CNTFRQ);
1496
1497 iounmap(base);
1498
1499 return rate;
1500}
1501
1502static struct arch_timer_mem_frame * __init
1503arch_timer_mem_find_best_frame(struct arch_timer_mem *timer_mem)
1504{
1505 struct arch_timer_mem_frame *frame, *best_frame = NULL;
1506 void __iomem *cntctlbase;
1507 u32 cnttidr;
1508 int i;
1509
1510 cntctlbase = ioremap(timer_mem->cntctlbase, timer_mem->size);
1511 if (!cntctlbase) {
1512 pr_err("Can't map CNTCTLBase @ %pa\n",
1513 &timer_mem->cntctlbase);
1514 return NULL;
1515 }
1516
1517 cnttidr = readl_relaxed(cntctlbase + CNTTIDR);
1518
1519 /*
1520 * Try to find a virtual capable frame. Otherwise fall back to a
1521 * physical capable frame.
1522 */
1523 for (i = 0; i < ARCH_TIMER_MEM_MAX_FRAMES; i++) {
1524 u32 cntacr = CNTACR_RFRQ | CNTACR_RWPT | CNTACR_RPCT |
1525 CNTACR_RWVT | CNTACR_RVOFF | CNTACR_RVCT;
1526
1527 frame = &timer_mem->frame[i];
1528 if (!frame->valid)
1529 continue;
1530
1531 /* Try enabling everything, and see what sticks */
1532 writel_relaxed(cntacr, cntctlbase + CNTACR(i));
1533 cntacr = readl_relaxed(cntctlbase + CNTACR(i));
1534
1535 if ((cnttidr & CNTTIDR_VIRT(i)) &&
1536 !(~cntacr & (CNTACR_RWVT | CNTACR_RVCT))) {
1537 best_frame = frame;
1538 arch_timer_mem_use_virtual = true;
1539 break;
1540 }
1541
1542 if (~cntacr & (CNTACR_RWPT | CNTACR_RPCT))
1543 continue;
1544
1545 best_frame = frame;
1546 }
1547
1548 iounmap(cntctlbase);
1549
1550 return best_frame;
1551}
1552
1553static int __init
1554arch_timer_mem_frame_register(struct arch_timer_mem_frame *frame)
1555{
1556 void __iomem *base;
1557 int ret, irq;
1558
1559 if (arch_timer_mem_use_virtual)
1560 irq = frame->virt_irq;
1561 else
1562 irq = frame->phys_irq;
1563
1564 if (!irq) {
1565 pr_err("Frame missing %s irq.\n",
1566 arch_timer_mem_use_virtual ? "virt" : "phys");
1567 return -EINVAL;
1568 }
1569
1570 if (!request_mem_region(frame->cntbase, frame->size,
1571 "arch_mem_timer"))
1572 return -EBUSY;
1573
1574 base = ioremap(frame->cntbase, frame->size);
1575 if (!base) {
1576 pr_err("Can't map frame's registers\n");
1577 return -ENXIO;
1578 }
1579
1580 ret = arch_timer_mem_register(base, irq);
1581 if (ret) {
1582 iounmap(base);
1583 return ret;
1584 }
1585
1586 arch_timers_present |= ARCH_TIMER_TYPE_MEM;
1587
1588 return 0;
1589}
1590
1591static int __init arch_timer_mem_of_init(struct device_node *np)
1592{
1593 struct arch_timer_mem *timer_mem;
1594 struct arch_timer_mem_frame *frame;
1595 struct resource res;
1596 int ret = -EINVAL;
1597 u32 rate;
1598
1599 timer_mem = kzalloc(sizeof(*timer_mem), GFP_KERNEL);
1600 if (!timer_mem)
1601 return -ENOMEM;
1602
1603 if (of_address_to_resource(np, 0, &res))
1604 goto out;
1605 timer_mem->cntctlbase = res.start;
1606 timer_mem->size = resource_size(&res);
1607
1608 for_each_available_child_of_node_scoped(np, frame_node) {
1609 u32 n;
1610 struct arch_timer_mem_frame *frame;
1611
1612 if (of_property_read_u32(frame_node, "frame-number", &n)) {
1613 pr_err(FW_BUG "Missing frame-number.\n");
1614 goto out;
1615 }
1616 if (n >= ARCH_TIMER_MEM_MAX_FRAMES) {
1617 pr_err(FW_BUG "Wrong frame-number, only 0-%u are permitted.\n",
1618 ARCH_TIMER_MEM_MAX_FRAMES - 1);
1619 goto out;
1620 }
1621 frame = &timer_mem->frame[n];
1622
1623 if (frame->valid) {
1624 pr_err(FW_BUG "Duplicated frame-number.\n");
1625 goto out;
1626 }
1627
1628 if (of_address_to_resource(frame_node, 0, &res))
1629 goto out;
1630
1631 frame->cntbase = res.start;
1632 frame->size = resource_size(&res);
1633
1634 frame->virt_irq = irq_of_parse_and_map(frame_node,
1635 ARCH_TIMER_VIRT_SPI);
1636 frame->phys_irq = irq_of_parse_and_map(frame_node,
1637 ARCH_TIMER_PHYS_SPI);
1638
1639 frame->valid = true;
1640 }
1641
1642 frame = arch_timer_mem_find_best_frame(timer_mem);
1643 if (!frame) {
1644 pr_err("Unable to find a suitable frame in timer @ %pa\n",
1645 &timer_mem->cntctlbase);
1646 ret = -EINVAL;
1647 goto out;
1648 }
1649
1650 rate = arch_timer_mem_frame_get_cntfrq(frame);
1651 arch_timer_of_configure_rate(rate, np);
1652
1653 ret = arch_timer_mem_frame_register(frame);
1654 if (!ret && !arch_timer_needs_of_probing())
1655 ret = arch_timer_common_init();
1656out:
1657 kfree(timer_mem);
1658 return ret;
1659}
1660TIMER_OF_DECLARE(armv7_arch_timer_mem, "arm,armv7-timer-mem",
1661 arch_timer_mem_of_init);
1662
1663#ifdef CONFIG_ACPI_GTDT
1664static int __init
1665arch_timer_mem_verify_cntfrq(struct arch_timer_mem *timer_mem)
1666{
1667 struct arch_timer_mem_frame *frame;
1668 u32 rate;
1669 int i;
1670
1671 for (i = 0; i < ARCH_TIMER_MEM_MAX_FRAMES; i++) {
1672 frame = &timer_mem->frame[i];
1673
1674 if (!frame->valid)
1675 continue;
1676
1677 rate = arch_timer_mem_frame_get_cntfrq(frame);
1678 if (rate == arch_timer_rate)
1679 continue;
1680
1681 pr_err(FW_BUG "CNTFRQ mismatch: frame @ %pa: (0x%08lx), CPU: (0x%08lx)\n",
1682 &frame->cntbase,
1683 (unsigned long)rate, (unsigned long)arch_timer_rate);
1684
1685 return -EINVAL;
1686 }
1687
1688 return 0;
1689}
1690
1691static int __init arch_timer_mem_acpi_init(int platform_timer_count)
1692{
1693 struct arch_timer_mem *timers, *timer;
1694 struct arch_timer_mem_frame *frame, *best_frame = NULL;
1695 int timer_count, i, ret = 0;
1696
1697 timers = kcalloc(platform_timer_count, sizeof(*timers),
1698 GFP_KERNEL);
1699 if (!timers)
1700 return -ENOMEM;
1701
1702 ret = acpi_arch_timer_mem_init(timers, &timer_count);
1703 if (ret || !timer_count)
1704 goto out;
1705
1706 /*
1707 * While unlikely, it's theoretically possible that none of the frames
1708 * in a timer expose the combination of feature we want.
1709 */
1710 for (i = 0; i < timer_count; i++) {
1711 timer = &timers[i];
1712
1713 frame = arch_timer_mem_find_best_frame(timer);
1714 if (!best_frame)
1715 best_frame = frame;
1716
1717 ret = arch_timer_mem_verify_cntfrq(timer);
1718 if (ret) {
1719 pr_err("Disabling MMIO timers due to CNTFRQ mismatch\n");
1720 goto out;
1721 }
1722
1723 if (!best_frame) /* implies !frame */
1724 /*
1725 * Only complain about missing suitable frames if we
1726 * haven't already found one in a previous iteration.
1727 */
1728 pr_err("Unable to find a suitable frame in timer @ %pa\n",
1729 &timer->cntctlbase);
1730 }
1731
1732 if (best_frame)
1733 ret = arch_timer_mem_frame_register(best_frame);
1734out:
1735 kfree(timers);
1736 return ret;
1737}
1738
1739/* Initialize per-processor generic timer and memory-mapped timer(if present) */
1740static int __init arch_timer_acpi_init(struct acpi_table_header *table)
1741{
1742 int ret, platform_timer_count;
1743
1744 if (arch_timers_present & ARCH_TIMER_TYPE_CP15) {
1745 pr_warn("already initialized, skipping\n");
1746 return -EINVAL;
1747 }
1748
1749 arch_timers_present |= ARCH_TIMER_TYPE_CP15;
1750
1751 ret = acpi_gtdt_init(table, &platform_timer_count);
1752 if (ret)
1753 return ret;
1754
1755 arch_timer_ppi[ARCH_TIMER_PHYS_NONSECURE_PPI] =
1756 acpi_gtdt_map_ppi(ARCH_TIMER_PHYS_NONSECURE_PPI);
1757
1758 arch_timer_ppi[ARCH_TIMER_VIRT_PPI] =
1759 acpi_gtdt_map_ppi(ARCH_TIMER_VIRT_PPI);
1760
1761 arch_timer_ppi[ARCH_TIMER_HYP_PPI] =
1762 acpi_gtdt_map_ppi(ARCH_TIMER_HYP_PPI);
1763
1764 arch_timer_populate_kvm_info();
1765
1766 /*
1767 * When probing via ACPI, we have no mechanism to override the sysreg
1768 * CNTFRQ value. This *must* be correct.
1769 */
1770 arch_timer_rate = arch_timer_get_cntfrq();
1771 ret = validate_timer_rate();
1772 if (ret) {
1773 pr_err(FW_BUG "frequency not available.\n");
1774 return ret;
1775 }
1776
1777 arch_timer_uses_ppi = arch_timer_select_ppi();
1778 if (!arch_timer_ppi[arch_timer_uses_ppi]) {
1779 pr_err("No interrupt available, giving up\n");
1780 return -EINVAL;
1781 }
1782
1783 /* Always-on capability */
1784 arch_timer_c3stop = acpi_gtdt_c3stop(arch_timer_uses_ppi);
1785
1786 /* Check for globally applicable workarounds */
1787 arch_timer_check_ool_workaround(ate_match_acpi_oem_info, table);
1788
1789 ret = arch_timer_register();
1790 if (ret)
1791 return ret;
1792
1793 if (platform_timer_count &&
1794 arch_timer_mem_acpi_init(platform_timer_count))
1795 pr_err("Failed to initialize memory-mapped timer.\n");
1796
1797 return arch_timer_common_init();
1798}
1799TIMER_ACPI_DECLARE(arch_timer, ACPI_SIG_GTDT, arch_timer_acpi_init);
1800#endif
1801
1802int kvm_arch_ptp_get_crosststamp(u64 *cycle, struct timespec64 *ts,
1803 enum clocksource_ids *cs_id)
1804{
1805 struct arm_smccc_res hvc_res;
1806 u32 ptp_counter;
1807 ktime_t ktime;
1808
1809 if (!IS_ENABLED(CONFIG_HAVE_ARM_SMCCC_DISCOVERY))
1810 return -EOPNOTSUPP;
1811
1812 if (arch_timer_uses_ppi == ARCH_TIMER_VIRT_PPI)
1813 ptp_counter = KVM_PTP_VIRT_COUNTER;
1814 else
1815 ptp_counter = KVM_PTP_PHYS_COUNTER;
1816
1817 arm_smccc_1_1_invoke(ARM_SMCCC_VENDOR_HYP_KVM_PTP_FUNC_ID,
1818 ptp_counter, &hvc_res);
1819
1820 if ((int)(hvc_res.a0) < 0)
1821 return -EOPNOTSUPP;
1822
1823 ktime = (u64)hvc_res.a0 << 32 | hvc_res.a1;
1824 *ts = ktime_to_timespec64(ktime);
1825 if (cycle)
1826 *cycle = (u64)hvc_res.a2 << 32 | hvc_res.a3;
1827 if (cs_id)
1828 *cs_id = CSID_ARM_ARCH_COUNTER;
1829
1830 return 0;
1831}
1832EXPORT_SYMBOL_GPL(kvm_arch_ptp_get_crosststamp);