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1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 *
4 * patch_hdmi.c - routines for HDMI/DisplayPort codecs
5 *
6 * Copyright(c) 2008-2010 Intel Corporation. All rights reserved.
7 * Copyright (c) 2006 ATI Technologies Inc.
8 * Copyright (c) 2008 NVIDIA Corp. All rights reserved.
9 * Copyright (c) 2008 Wei Ni <wni@nvidia.com>
10 * Copyright (c) 2013 Anssi Hannula <anssi.hannula@iki.fi>
11 *
12 * Authors:
13 * Wu Fengguang <wfg@linux.intel.com>
14 *
15 * Maintained by:
16 * Wu Fengguang <wfg@linux.intel.com>
17 */
18
19#include <linux/init.h>
20#include <linux/delay.h>
21#include <linux/pci.h>
22#include <linux/slab.h>
23#include <linux/module.h>
24#include <linux/pm_runtime.h>
25#include <sound/core.h>
26#include <sound/jack.h>
27#include <sound/asoundef.h>
28#include <sound/tlv.h>
29#include <sound/hdaudio.h>
30#include <sound/hda_i915.h>
31#include <sound/hda_chmap.h>
32#include <sound/hda_codec.h>
33#include "hda_local.h"
34#include "hda_jack.h"
35#include "hda_controller.h"
36
37static bool static_hdmi_pcm;
38module_param(static_hdmi_pcm, bool, 0644);
39MODULE_PARM_DESC(static_hdmi_pcm, "Don't restrict PCM parameters per ELD info");
40
41static bool enable_acomp = true;
42module_param(enable_acomp, bool, 0444);
43MODULE_PARM_DESC(enable_acomp, "Enable audio component binding (default=yes)");
44
45static bool enable_silent_stream =
46IS_ENABLED(CONFIG_SND_HDA_INTEL_HDMI_SILENT_STREAM);
47module_param(enable_silent_stream, bool, 0644);
48MODULE_PARM_DESC(enable_silent_stream, "Enable Silent Stream for HDMI devices");
49
50struct hdmi_spec_per_cvt {
51 hda_nid_t cvt_nid;
52 int assigned;
53 unsigned int channels_min;
54 unsigned int channels_max;
55 u32 rates;
56 u64 formats;
57 unsigned int maxbps;
58};
59
60/* max. connections to a widget */
61#define HDA_MAX_CONNECTIONS 32
62
63struct hdmi_spec_per_pin {
64 hda_nid_t pin_nid;
65 int dev_id;
66 /* pin idx, different device entries on the same pin use the same idx */
67 int pin_nid_idx;
68 int num_mux_nids;
69 hda_nid_t mux_nids[HDA_MAX_CONNECTIONS];
70 int mux_idx;
71 hda_nid_t cvt_nid;
72
73 struct hda_codec *codec;
74 struct hdmi_eld sink_eld;
75 struct mutex lock;
76 struct delayed_work work;
77 struct hdmi_pcm *pcm; /* pointer to spec->pcm_rec[n] dynamically*/
78 int pcm_idx; /* which pcm is attached. -1 means no pcm is attached */
79 int repoll_count;
80 bool setup; /* the stream has been set up by prepare callback */
81 int channels; /* current number of channels */
82 bool non_pcm;
83 bool chmap_set; /* channel-map override by ALSA API? */
84 unsigned char chmap[8]; /* ALSA API channel-map */
85#ifdef CONFIG_SND_PROC_FS
86 struct snd_info_entry *proc_entry;
87#endif
88};
89
90/* operations used by generic code that can be overridden by patches */
91struct hdmi_ops {
92 int (*pin_get_eld)(struct hda_codec *codec, hda_nid_t pin_nid,
93 int dev_id, unsigned char *buf, int *eld_size);
94
95 void (*pin_setup_infoframe)(struct hda_codec *codec, hda_nid_t pin_nid,
96 int dev_id,
97 int ca, int active_channels, int conn_type);
98
99 /* enable/disable HBR (HD passthrough) */
100 int (*pin_hbr_setup)(struct hda_codec *codec, hda_nid_t pin_nid,
101 int dev_id, bool hbr);
102
103 int (*setup_stream)(struct hda_codec *codec, hda_nid_t cvt_nid,
104 hda_nid_t pin_nid, int dev_id, u32 stream_tag,
105 int format);
106
107 void (*pin_cvt_fixup)(struct hda_codec *codec,
108 struct hdmi_spec_per_pin *per_pin,
109 hda_nid_t cvt_nid);
110};
111
112struct hdmi_pcm {
113 struct hda_pcm *pcm;
114 struct snd_jack *jack;
115 struct snd_kcontrol *eld_ctl;
116};
117
118struct hdmi_spec {
119 struct hda_codec *codec;
120 int num_cvts;
121 struct snd_array cvts; /* struct hdmi_spec_per_cvt */
122 hda_nid_t cvt_nids[4]; /* only for haswell fix */
123
124 /*
125 * num_pins is the number of virtual pins
126 * for example, there are 3 pins, and each pin
127 * has 4 device entries, then the num_pins is 12
128 */
129 int num_pins;
130 /*
131 * num_nids is the number of real pins
132 * In the above example, num_nids is 3
133 */
134 int num_nids;
135 /*
136 * dev_num is the number of device entries
137 * on each pin.
138 * In the above example, dev_num is 4
139 */
140 int dev_num;
141 struct snd_array pins; /* struct hdmi_spec_per_pin */
142 struct hdmi_pcm pcm_rec[16];
143 struct mutex pcm_lock;
144 struct mutex bind_lock; /* for audio component binding */
145 /* pcm_bitmap means which pcms have been assigned to pins*/
146 unsigned long pcm_bitmap;
147 int pcm_used; /* counter of pcm_rec[] */
148 /* bitmap shows whether the pcm is opened in user space
149 * bit 0 means the first playback PCM (PCM3);
150 * bit 1 means the second playback PCM, and so on.
151 */
152 unsigned long pcm_in_use;
153
154 struct hdmi_eld temp_eld;
155 struct hdmi_ops ops;
156
157 bool dyn_pin_out;
158 bool dyn_pcm_assign;
159 bool intel_hsw_fixup; /* apply Intel platform-specific fixups */
160 /*
161 * Non-generic VIA/NVIDIA specific
162 */
163 struct hda_multi_out multiout;
164 struct hda_pcm_stream pcm_playback;
165
166 bool use_acomp_notifier; /* use eld_notify callback for hotplug */
167 bool acomp_registered; /* audio component registered in this driver */
168 bool force_connect; /* force connectivity */
169 struct drm_audio_component_audio_ops drm_audio_ops;
170 int (*port2pin)(struct hda_codec *, int); /* reverse port/pin mapping */
171
172 struct hdac_chmap chmap;
173 hda_nid_t vendor_nid;
174 const int *port_map;
175 int port_num;
176 bool send_silent_stream; /* Flag to enable silent stream feature */
177};
178
179#ifdef CONFIG_SND_HDA_COMPONENT
180static inline bool codec_has_acomp(struct hda_codec *codec)
181{
182 struct hdmi_spec *spec = codec->spec;
183 return spec->use_acomp_notifier;
184}
185#else
186#define codec_has_acomp(codec) false
187#endif
188
189struct hdmi_audio_infoframe {
190 u8 type; /* 0x84 */
191 u8 ver; /* 0x01 */
192 u8 len; /* 0x0a */
193
194 u8 checksum;
195
196 u8 CC02_CT47; /* CC in bits 0:2, CT in 4:7 */
197 u8 SS01_SF24;
198 u8 CXT04;
199 u8 CA;
200 u8 LFEPBL01_LSV36_DM_INH7;
201};
202
203struct dp_audio_infoframe {
204 u8 type; /* 0x84 */
205 u8 len; /* 0x1b */
206 u8 ver; /* 0x11 << 2 */
207
208 u8 CC02_CT47; /* match with HDMI infoframe from this on */
209 u8 SS01_SF24;
210 u8 CXT04;
211 u8 CA;
212 u8 LFEPBL01_LSV36_DM_INH7;
213};
214
215union audio_infoframe {
216 struct hdmi_audio_infoframe hdmi;
217 struct dp_audio_infoframe dp;
218 u8 bytes[0];
219};
220
221/*
222 * HDMI routines
223 */
224
225#define get_pin(spec, idx) \
226 ((struct hdmi_spec_per_pin *)snd_array_elem(&spec->pins, idx))
227#define get_cvt(spec, idx) \
228 ((struct hdmi_spec_per_cvt *)snd_array_elem(&spec->cvts, idx))
229/* obtain hdmi_pcm object assigned to idx */
230#define get_hdmi_pcm(spec, idx) (&(spec)->pcm_rec[idx])
231/* obtain hda_pcm object assigned to idx */
232#define get_pcm_rec(spec, idx) (get_hdmi_pcm(spec, idx)->pcm)
233
234static int pin_id_to_pin_index(struct hda_codec *codec,
235 hda_nid_t pin_nid, int dev_id)
236{
237 struct hdmi_spec *spec = codec->spec;
238 int pin_idx;
239 struct hdmi_spec_per_pin *per_pin;
240
241 /*
242 * (dev_id == -1) means it is NON-MST pin
243 * return the first virtual pin on this port
244 */
245 if (dev_id == -1)
246 dev_id = 0;
247
248 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
249 per_pin = get_pin(spec, pin_idx);
250 if ((per_pin->pin_nid == pin_nid) &&
251 (per_pin->dev_id == dev_id))
252 return pin_idx;
253 }
254
255 codec_warn(codec, "HDMI: pin nid %d not registered\n", pin_nid);
256 return -EINVAL;
257}
258
259static int hinfo_to_pcm_index(struct hda_codec *codec,
260 struct hda_pcm_stream *hinfo)
261{
262 struct hdmi_spec *spec = codec->spec;
263 int pcm_idx;
264
265 for (pcm_idx = 0; pcm_idx < spec->pcm_used; pcm_idx++)
266 if (get_pcm_rec(spec, pcm_idx)->stream == hinfo)
267 return pcm_idx;
268
269 codec_warn(codec, "HDMI: hinfo %p not tied to a PCM\n", hinfo);
270 return -EINVAL;
271}
272
273static int hinfo_to_pin_index(struct hda_codec *codec,
274 struct hda_pcm_stream *hinfo)
275{
276 struct hdmi_spec *spec = codec->spec;
277 struct hdmi_spec_per_pin *per_pin;
278 int pin_idx;
279
280 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
281 per_pin = get_pin(spec, pin_idx);
282 if (per_pin->pcm &&
283 per_pin->pcm->pcm->stream == hinfo)
284 return pin_idx;
285 }
286
287 codec_dbg(codec, "HDMI: hinfo %p (pcm %d) not registered\n", hinfo,
288 hinfo_to_pcm_index(codec, hinfo));
289 return -EINVAL;
290}
291
292static struct hdmi_spec_per_pin *pcm_idx_to_pin(struct hdmi_spec *spec,
293 int pcm_idx)
294{
295 int i;
296 struct hdmi_spec_per_pin *per_pin;
297
298 for (i = 0; i < spec->num_pins; i++) {
299 per_pin = get_pin(spec, i);
300 if (per_pin->pcm_idx == pcm_idx)
301 return per_pin;
302 }
303 return NULL;
304}
305
306static int cvt_nid_to_cvt_index(struct hda_codec *codec, hda_nid_t cvt_nid)
307{
308 struct hdmi_spec *spec = codec->spec;
309 int cvt_idx;
310
311 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++)
312 if (get_cvt(spec, cvt_idx)->cvt_nid == cvt_nid)
313 return cvt_idx;
314
315 codec_warn(codec, "HDMI: cvt nid %d not registered\n", cvt_nid);
316 return -EINVAL;
317}
318
319static int hdmi_eld_ctl_info(struct snd_kcontrol *kcontrol,
320 struct snd_ctl_elem_info *uinfo)
321{
322 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
323 struct hdmi_spec *spec = codec->spec;
324 struct hdmi_spec_per_pin *per_pin;
325 struct hdmi_eld *eld;
326 int pcm_idx;
327
328 uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES;
329
330 pcm_idx = kcontrol->private_value;
331 mutex_lock(&spec->pcm_lock);
332 per_pin = pcm_idx_to_pin(spec, pcm_idx);
333 if (!per_pin) {
334 /* no pin is bound to the pcm */
335 uinfo->count = 0;
336 goto unlock;
337 }
338 eld = &per_pin->sink_eld;
339 uinfo->count = eld->eld_valid ? eld->eld_size : 0;
340
341 unlock:
342 mutex_unlock(&spec->pcm_lock);
343 return 0;
344}
345
346static int hdmi_eld_ctl_get(struct snd_kcontrol *kcontrol,
347 struct snd_ctl_elem_value *ucontrol)
348{
349 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
350 struct hdmi_spec *spec = codec->spec;
351 struct hdmi_spec_per_pin *per_pin;
352 struct hdmi_eld *eld;
353 int pcm_idx;
354 int err = 0;
355
356 pcm_idx = kcontrol->private_value;
357 mutex_lock(&spec->pcm_lock);
358 per_pin = pcm_idx_to_pin(spec, pcm_idx);
359 if (!per_pin) {
360 /* no pin is bound to the pcm */
361 memset(ucontrol->value.bytes.data, 0,
362 ARRAY_SIZE(ucontrol->value.bytes.data));
363 goto unlock;
364 }
365
366 eld = &per_pin->sink_eld;
367 if (eld->eld_size > ARRAY_SIZE(ucontrol->value.bytes.data) ||
368 eld->eld_size > ELD_MAX_SIZE) {
369 snd_BUG();
370 err = -EINVAL;
371 goto unlock;
372 }
373
374 memset(ucontrol->value.bytes.data, 0,
375 ARRAY_SIZE(ucontrol->value.bytes.data));
376 if (eld->eld_valid)
377 memcpy(ucontrol->value.bytes.data, eld->eld_buffer,
378 eld->eld_size);
379
380 unlock:
381 mutex_unlock(&spec->pcm_lock);
382 return err;
383}
384
385static const struct snd_kcontrol_new eld_bytes_ctl = {
386 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE |
387 SNDRV_CTL_ELEM_ACCESS_SKIP_CHECK,
388 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
389 .name = "ELD",
390 .info = hdmi_eld_ctl_info,
391 .get = hdmi_eld_ctl_get,
392};
393
394static int hdmi_create_eld_ctl(struct hda_codec *codec, int pcm_idx,
395 int device)
396{
397 struct snd_kcontrol *kctl;
398 struct hdmi_spec *spec = codec->spec;
399 int err;
400
401 kctl = snd_ctl_new1(&eld_bytes_ctl, codec);
402 if (!kctl)
403 return -ENOMEM;
404 kctl->private_value = pcm_idx;
405 kctl->id.device = device;
406
407 /* no pin nid is associated with the kctl now
408 * tbd: associate pin nid to eld ctl later
409 */
410 err = snd_hda_ctl_add(codec, 0, kctl);
411 if (err < 0)
412 return err;
413
414 get_hdmi_pcm(spec, pcm_idx)->eld_ctl = kctl;
415 return 0;
416}
417
418#ifdef BE_PARANOID
419static void hdmi_get_dip_index(struct hda_codec *codec, hda_nid_t pin_nid,
420 int *packet_index, int *byte_index)
421{
422 int val;
423
424 val = snd_hda_codec_read(codec, pin_nid, 0,
425 AC_VERB_GET_HDMI_DIP_INDEX, 0);
426
427 *packet_index = val >> 5;
428 *byte_index = val & 0x1f;
429}
430#endif
431
432static void hdmi_set_dip_index(struct hda_codec *codec, hda_nid_t pin_nid,
433 int packet_index, int byte_index)
434{
435 int val;
436
437 val = (packet_index << 5) | (byte_index & 0x1f);
438
439 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_INDEX, val);
440}
441
442static void hdmi_write_dip_byte(struct hda_codec *codec, hda_nid_t pin_nid,
443 unsigned char val)
444{
445 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_DATA, val);
446}
447
448static void hdmi_init_pin(struct hda_codec *codec, hda_nid_t pin_nid)
449{
450 struct hdmi_spec *spec = codec->spec;
451 int pin_out;
452
453 /* Unmute */
454 if (get_wcaps(codec, pin_nid) & AC_WCAP_OUT_AMP)
455 snd_hda_codec_write(codec, pin_nid, 0,
456 AC_VERB_SET_AMP_GAIN_MUTE, AMP_OUT_UNMUTE);
457
458 if (spec->dyn_pin_out)
459 /* Disable pin out until stream is active */
460 pin_out = 0;
461 else
462 /* Enable pin out: some machines with GM965 gets broken output
463 * when the pin is disabled or changed while using with HDMI
464 */
465 pin_out = PIN_OUT;
466
467 snd_hda_codec_write(codec, pin_nid, 0,
468 AC_VERB_SET_PIN_WIDGET_CONTROL, pin_out);
469}
470
471/*
472 * ELD proc files
473 */
474
475#ifdef CONFIG_SND_PROC_FS
476static void print_eld_info(struct snd_info_entry *entry,
477 struct snd_info_buffer *buffer)
478{
479 struct hdmi_spec_per_pin *per_pin = entry->private_data;
480
481 mutex_lock(&per_pin->lock);
482 snd_hdmi_print_eld_info(&per_pin->sink_eld, buffer);
483 mutex_unlock(&per_pin->lock);
484}
485
486static void write_eld_info(struct snd_info_entry *entry,
487 struct snd_info_buffer *buffer)
488{
489 struct hdmi_spec_per_pin *per_pin = entry->private_data;
490
491 mutex_lock(&per_pin->lock);
492 snd_hdmi_write_eld_info(&per_pin->sink_eld, buffer);
493 mutex_unlock(&per_pin->lock);
494}
495
496static int eld_proc_new(struct hdmi_spec_per_pin *per_pin, int index)
497{
498 char name[32];
499 struct hda_codec *codec = per_pin->codec;
500 struct snd_info_entry *entry;
501 int err;
502
503 snprintf(name, sizeof(name), "eld#%d.%d", codec->addr, index);
504 err = snd_card_proc_new(codec->card, name, &entry);
505 if (err < 0)
506 return err;
507
508 snd_info_set_text_ops(entry, per_pin, print_eld_info);
509 entry->c.text.write = write_eld_info;
510 entry->mode |= 0200;
511 per_pin->proc_entry = entry;
512
513 return 0;
514}
515
516static void eld_proc_free(struct hdmi_spec_per_pin *per_pin)
517{
518 if (!per_pin->codec->bus->shutdown) {
519 snd_info_free_entry(per_pin->proc_entry);
520 per_pin->proc_entry = NULL;
521 }
522}
523#else
524static inline int eld_proc_new(struct hdmi_spec_per_pin *per_pin,
525 int index)
526{
527 return 0;
528}
529static inline void eld_proc_free(struct hdmi_spec_per_pin *per_pin)
530{
531}
532#endif
533
534/*
535 * Audio InfoFrame routines
536 */
537
538/*
539 * Enable Audio InfoFrame Transmission
540 */
541static void hdmi_start_infoframe_trans(struct hda_codec *codec,
542 hda_nid_t pin_nid)
543{
544 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
545 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_XMIT,
546 AC_DIPXMIT_BEST);
547}
548
549/*
550 * Disable Audio InfoFrame Transmission
551 */
552static void hdmi_stop_infoframe_trans(struct hda_codec *codec,
553 hda_nid_t pin_nid)
554{
555 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
556 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_XMIT,
557 AC_DIPXMIT_DISABLE);
558}
559
560static void hdmi_debug_dip_size(struct hda_codec *codec, hda_nid_t pin_nid)
561{
562#ifdef CONFIG_SND_DEBUG_VERBOSE
563 int i;
564 int size;
565
566 size = snd_hdmi_get_eld_size(codec, pin_nid);
567 codec_dbg(codec, "HDMI: ELD buf size is %d\n", size);
568
569 for (i = 0; i < 8; i++) {
570 size = snd_hda_codec_read(codec, pin_nid, 0,
571 AC_VERB_GET_HDMI_DIP_SIZE, i);
572 codec_dbg(codec, "HDMI: DIP GP[%d] buf size is %d\n", i, size);
573 }
574#endif
575}
576
577static void hdmi_clear_dip_buffers(struct hda_codec *codec, hda_nid_t pin_nid)
578{
579#ifdef BE_PARANOID
580 int i, j;
581 int size;
582 int pi, bi;
583 for (i = 0; i < 8; i++) {
584 size = snd_hda_codec_read(codec, pin_nid, 0,
585 AC_VERB_GET_HDMI_DIP_SIZE, i);
586 if (size == 0)
587 continue;
588
589 hdmi_set_dip_index(codec, pin_nid, i, 0x0);
590 for (j = 1; j < 1000; j++) {
591 hdmi_write_dip_byte(codec, pin_nid, 0x0);
592 hdmi_get_dip_index(codec, pin_nid, &pi, &bi);
593 if (pi != i)
594 codec_dbg(codec, "dip index %d: %d != %d\n",
595 bi, pi, i);
596 if (bi == 0) /* byte index wrapped around */
597 break;
598 }
599 codec_dbg(codec,
600 "HDMI: DIP GP[%d] buf reported size=%d, written=%d\n",
601 i, size, j);
602 }
603#endif
604}
605
606static void hdmi_checksum_audio_infoframe(struct hdmi_audio_infoframe *hdmi_ai)
607{
608 u8 *bytes = (u8 *)hdmi_ai;
609 u8 sum = 0;
610 int i;
611
612 hdmi_ai->checksum = 0;
613
614 for (i = 0; i < sizeof(*hdmi_ai); i++)
615 sum += bytes[i];
616
617 hdmi_ai->checksum = -sum;
618}
619
620static void hdmi_fill_audio_infoframe(struct hda_codec *codec,
621 hda_nid_t pin_nid,
622 u8 *dip, int size)
623{
624 int i;
625
626 hdmi_debug_dip_size(codec, pin_nid);
627 hdmi_clear_dip_buffers(codec, pin_nid); /* be paranoid */
628
629 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
630 for (i = 0; i < size; i++)
631 hdmi_write_dip_byte(codec, pin_nid, dip[i]);
632}
633
634static bool hdmi_infoframe_uptodate(struct hda_codec *codec, hda_nid_t pin_nid,
635 u8 *dip, int size)
636{
637 u8 val;
638 int i;
639
640 if (snd_hda_codec_read(codec, pin_nid, 0, AC_VERB_GET_HDMI_DIP_XMIT, 0)
641 != AC_DIPXMIT_BEST)
642 return false;
643
644 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
645 for (i = 0; i < size; i++) {
646 val = snd_hda_codec_read(codec, pin_nid, 0,
647 AC_VERB_GET_HDMI_DIP_DATA, 0);
648 if (val != dip[i])
649 return false;
650 }
651
652 return true;
653}
654
655static int hdmi_pin_get_eld(struct hda_codec *codec, hda_nid_t nid,
656 int dev_id, unsigned char *buf, int *eld_size)
657{
658 snd_hda_set_dev_select(codec, nid, dev_id);
659
660 return snd_hdmi_get_eld(codec, nid, buf, eld_size);
661}
662
663static void hdmi_pin_setup_infoframe(struct hda_codec *codec,
664 hda_nid_t pin_nid, int dev_id,
665 int ca, int active_channels,
666 int conn_type)
667{
668 union audio_infoframe ai;
669
670 memset(&ai, 0, sizeof(ai));
671 if (conn_type == 0) { /* HDMI */
672 struct hdmi_audio_infoframe *hdmi_ai = &ai.hdmi;
673
674 hdmi_ai->type = 0x84;
675 hdmi_ai->ver = 0x01;
676 hdmi_ai->len = 0x0a;
677 hdmi_ai->CC02_CT47 = active_channels - 1;
678 hdmi_ai->CA = ca;
679 hdmi_checksum_audio_infoframe(hdmi_ai);
680 } else if (conn_type == 1) { /* DisplayPort */
681 struct dp_audio_infoframe *dp_ai = &ai.dp;
682
683 dp_ai->type = 0x84;
684 dp_ai->len = 0x1b;
685 dp_ai->ver = 0x11 << 2;
686 dp_ai->CC02_CT47 = active_channels - 1;
687 dp_ai->CA = ca;
688 } else {
689 codec_dbg(codec, "HDMI: unknown connection type at pin %d\n",
690 pin_nid);
691 return;
692 }
693
694 snd_hda_set_dev_select(codec, pin_nid, dev_id);
695
696 /*
697 * sizeof(ai) is used instead of sizeof(*hdmi_ai) or
698 * sizeof(*dp_ai) to avoid partial match/update problems when
699 * the user switches between HDMI/DP monitors.
700 */
701 if (!hdmi_infoframe_uptodate(codec, pin_nid, ai.bytes,
702 sizeof(ai))) {
703 codec_dbg(codec,
704 "hdmi_pin_setup_infoframe: pin=%d channels=%d ca=0x%02x\n",
705 pin_nid,
706 active_channels, ca);
707 hdmi_stop_infoframe_trans(codec, pin_nid);
708 hdmi_fill_audio_infoframe(codec, pin_nid,
709 ai.bytes, sizeof(ai));
710 hdmi_start_infoframe_trans(codec, pin_nid);
711 }
712}
713
714static void hdmi_setup_audio_infoframe(struct hda_codec *codec,
715 struct hdmi_spec_per_pin *per_pin,
716 bool non_pcm)
717{
718 struct hdmi_spec *spec = codec->spec;
719 struct hdac_chmap *chmap = &spec->chmap;
720 hda_nid_t pin_nid = per_pin->pin_nid;
721 int dev_id = per_pin->dev_id;
722 int channels = per_pin->channels;
723 int active_channels;
724 struct hdmi_eld *eld;
725 int ca;
726
727 if (!channels)
728 return;
729
730 snd_hda_set_dev_select(codec, pin_nid, dev_id);
731
732 /* some HW (e.g. HSW+) needs reprogramming the amp at each time */
733 if (get_wcaps(codec, pin_nid) & AC_WCAP_OUT_AMP)
734 snd_hda_codec_write(codec, pin_nid, 0,
735 AC_VERB_SET_AMP_GAIN_MUTE,
736 AMP_OUT_UNMUTE);
737
738 eld = &per_pin->sink_eld;
739
740 ca = snd_hdac_channel_allocation(&codec->core,
741 eld->info.spk_alloc, channels,
742 per_pin->chmap_set, non_pcm, per_pin->chmap);
743
744 active_channels = snd_hdac_get_active_channels(ca);
745
746 chmap->ops.set_channel_count(&codec->core, per_pin->cvt_nid,
747 active_channels);
748
749 /*
750 * always configure channel mapping, it may have been changed by the
751 * user in the meantime
752 */
753 snd_hdac_setup_channel_mapping(&spec->chmap,
754 pin_nid, non_pcm, ca, channels,
755 per_pin->chmap, per_pin->chmap_set);
756
757 spec->ops.pin_setup_infoframe(codec, pin_nid, dev_id,
758 ca, active_channels, eld->info.conn_type);
759
760 per_pin->non_pcm = non_pcm;
761}
762
763/*
764 * Unsolicited events
765 */
766
767static void hdmi_present_sense(struct hdmi_spec_per_pin *per_pin, int repoll);
768
769static void check_presence_and_report(struct hda_codec *codec, hda_nid_t nid,
770 int dev_id)
771{
772 struct hdmi_spec *spec = codec->spec;
773 int pin_idx = pin_id_to_pin_index(codec, nid, dev_id);
774
775 if (pin_idx < 0)
776 return;
777 mutex_lock(&spec->pcm_lock);
778 hdmi_present_sense(get_pin(spec, pin_idx), 1);
779 mutex_unlock(&spec->pcm_lock);
780}
781
782static void jack_callback(struct hda_codec *codec,
783 struct hda_jack_callback *jack)
784{
785 /* stop polling when notification is enabled */
786 if (codec_has_acomp(codec))
787 return;
788
789 check_presence_and_report(codec, jack->nid, jack->dev_id);
790}
791
792static void hdmi_intrinsic_event(struct hda_codec *codec, unsigned int res,
793 struct hda_jack_tbl *jack)
794{
795 jack->jack_dirty = 1;
796
797 codec_dbg(codec,
798 "HDMI hot plug event: Codec=%d Pin=%d Device=%d Inactive=%d Presence_Detect=%d ELD_Valid=%d\n",
799 codec->addr, jack->nid, jack->dev_id, !!(res & AC_UNSOL_RES_IA),
800 !!(res & AC_UNSOL_RES_PD), !!(res & AC_UNSOL_RES_ELDV));
801
802 check_presence_and_report(codec, jack->nid, jack->dev_id);
803}
804
805static void hdmi_non_intrinsic_event(struct hda_codec *codec, unsigned int res)
806{
807 int tag = res >> AC_UNSOL_RES_TAG_SHIFT;
808 int subtag = (res & AC_UNSOL_RES_SUBTAG) >> AC_UNSOL_RES_SUBTAG_SHIFT;
809 int cp_state = !!(res & AC_UNSOL_RES_CP_STATE);
810 int cp_ready = !!(res & AC_UNSOL_RES_CP_READY);
811
812 codec_info(codec,
813 "HDMI CP event: CODEC=%d TAG=%d SUBTAG=0x%x CP_STATE=%d CP_READY=%d\n",
814 codec->addr,
815 tag,
816 subtag,
817 cp_state,
818 cp_ready);
819
820 /* TODO */
821 if (cp_state) {
822 ;
823 }
824 if (cp_ready) {
825 ;
826 }
827}
828
829
830static void hdmi_unsol_event(struct hda_codec *codec, unsigned int res)
831{
832 int tag = res >> AC_UNSOL_RES_TAG_SHIFT;
833 int subtag = (res & AC_UNSOL_RES_SUBTAG) >> AC_UNSOL_RES_SUBTAG_SHIFT;
834 struct hda_jack_tbl *jack;
835
836 if (codec_has_acomp(codec))
837 return;
838
839 if (codec->dp_mst) {
840 int dev_entry =
841 (res & AC_UNSOL_RES_DE) >> AC_UNSOL_RES_DE_SHIFT;
842
843 jack = snd_hda_jack_tbl_get_from_tag(codec, tag, dev_entry);
844 } else {
845 jack = snd_hda_jack_tbl_get_from_tag(codec, tag, 0);
846 }
847
848 if (!jack) {
849 codec_dbg(codec, "Unexpected HDMI event tag 0x%x\n", tag);
850 return;
851 }
852
853 if (subtag == 0)
854 hdmi_intrinsic_event(codec, res, jack);
855 else
856 hdmi_non_intrinsic_event(codec, res);
857}
858
859static void haswell_verify_D0(struct hda_codec *codec,
860 hda_nid_t cvt_nid, hda_nid_t nid)
861{
862 int pwr;
863
864 /* For Haswell, the converter 1/2 may keep in D3 state after bootup,
865 * thus pins could only choose converter 0 for use. Make sure the
866 * converters are in correct power state */
867 if (!snd_hda_check_power_state(codec, cvt_nid, AC_PWRST_D0))
868 snd_hda_codec_write(codec, cvt_nid, 0, AC_VERB_SET_POWER_STATE, AC_PWRST_D0);
869
870 if (!snd_hda_check_power_state(codec, nid, AC_PWRST_D0)) {
871 snd_hda_codec_write(codec, nid, 0, AC_VERB_SET_POWER_STATE,
872 AC_PWRST_D0);
873 msleep(40);
874 pwr = snd_hda_codec_read(codec, nid, 0, AC_VERB_GET_POWER_STATE, 0);
875 pwr = (pwr & AC_PWRST_ACTUAL) >> AC_PWRST_ACTUAL_SHIFT;
876 codec_dbg(codec, "Haswell HDMI audio: Power for pin 0x%x is now D%d\n", nid, pwr);
877 }
878}
879
880/*
881 * Callbacks
882 */
883
884/* HBR should be Non-PCM, 8 channels */
885#define is_hbr_format(format) \
886 ((format & AC_FMT_TYPE_NON_PCM) && (format & AC_FMT_CHAN_MASK) == 7)
887
888static int hdmi_pin_hbr_setup(struct hda_codec *codec, hda_nid_t pin_nid,
889 int dev_id, bool hbr)
890{
891 int pinctl, new_pinctl;
892
893 if (snd_hda_query_pin_caps(codec, pin_nid) & AC_PINCAP_HBR) {
894 snd_hda_set_dev_select(codec, pin_nid, dev_id);
895 pinctl = snd_hda_codec_read(codec, pin_nid, 0,
896 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
897
898 if (pinctl < 0)
899 return hbr ? -EINVAL : 0;
900
901 new_pinctl = pinctl & ~AC_PINCTL_EPT;
902 if (hbr)
903 new_pinctl |= AC_PINCTL_EPT_HBR;
904 else
905 new_pinctl |= AC_PINCTL_EPT_NATIVE;
906
907 codec_dbg(codec,
908 "hdmi_pin_hbr_setup: NID=0x%x, %spinctl=0x%x\n",
909 pin_nid,
910 pinctl == new_pinctl ? "" : "new-",
911 new_pinctl);
912
913 if (pinctl != new_pinctl)
914 snd_hda_codec_write(codec, pin_nid, 0,
915 AC_VERB_SET_PIN_WIDGET_CONTROL,
916 new_pinctl);
917 } else if (hbr)
918 return -EINVAL;
919
920 return 0;
921}
922
923static int hdmi_setup_stream(struct hda_codec *codec, hda_nid_t cvt_nid,
924 hda_nid_t pin_nid, int dev_id,
925 u32 stream_tag, int format)
926{
927 struct hdmi_spec *spec = codec->spec;
928 unsigned int param;
929 int err;
930
931 err = spec->ops.pin_hbr_setup(codec, pin_nid, dev_id,
932 is_hbr_format(format));
933
934 if (err) {
935 codec_dbg(codec, "hdmi_setup_stream: HBR is not supported\n");
936 return err;
937 }
938
939 if (spec->intel_hsw_fixup) {
940
941 /*
942 * on recent platforms IEC Coding Type is required for HBR
943 * support, read current Digital Converter settings and set
944 * ICT bitfield if needed.
945 */
946 param = snd_hda_codec_read(codec, cvt_nid, 0,
947 AC_VERB_GET_DIGI_CONVERT_1, 0);
948
949 param = (param >> 16) & ~(AC_DIG3_ICT);
950
951 /* on recent platforms ICT mode is required for HBR support */
952 if (is_hbr_format(format))
953 param |= 0x1;
954
955 snd_hda_codec_write(codec, cvt_nid, 0,
956 AC_VERB_SET_DIGI_CONVERT_3, param);
957 }
958
959 snd_hda_codec_setup_stream(codec, cvt_nid, stream_tag, 0, format);
960 return 0;
961}
962
963/* Try to find an available converter
964 * If pin_idx is less then zero, just try to find an available converter.
965 * Otherwise, try to find an available converter and get the cvt mux index
966 * of the pin.
967 */
968static int hdmi_choose_cvt(struct hda_codec *codec,
969 int pin_idx, int *cvt_id)
970{
971 struct hdmi_spec *spec = codec->spec;
972 struct hdmi_spec_per_pin *per_pin;
973 struct hdmi_spec_per_cvt *per_cvt = NULL;
974 int cvt_idx, mux_idx = 0;
975
976 /* pin_idx < 0 means no pin will be bound to the converter */
977 if (pin_idx < 0)
978 per_pin = NULL;
979 else
980 per_pin = get_pin(spec, pin_idx);
981
982 /* Dynamically assign converter to stream */
983 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) {
984 per_cvt = get_cvt(spec, cvt_idx);
985
986 /* Must not already be assigned */
987 if (per_cvt->assigned)
988 continue;
989 if (per_pin == NULL)
990 break;
991 /* Must be in pin's mux's list of converters */
992 for (mux_idx = 0; mux_idx < per_pin->num_mux_nids; mux_idx++)
993 if (per_pin->mux_nids[mux_idx] == per_cvt->cvt_nid)
994 break;
995 /* Not in mux list */
996 if (mux_idx == per_pin->num_mux_nids)
997 continue;
998 break;
999 }
1000
1001 /* No free converters */
1002 if (cvt_idx == spec->num_cvts)
1003 return -EBUSY;
1004
1005 if (per_pin != NULL)
1006 per_pin->mux_idx = mux_idx;
1007
1008 if (cvt_id)
1009 *cvt_id = cvt_idx;
1010
1011 return 0;
1012}
1013
1014/* Assure the pin select the right convetor */
1015static void intel_verify_pin_cvt_connect(struct hda_codec *codec,
1016 struct hdmi_spec_per_pin *per_pin)
1017{
1018 hda_nid_t pin_nid = per_pin->pin_nid;
1019 int mux_idx, curr;
1020
1021 mux_idx = per_pin->mux_idx;
1022 curr = snd_hda_codec_read(codec, pin_nid, 0,
1023 AC_VERB_GET_CONNECT_SEL, 0);
1024 if (curr != mux_idx)
1025 snd_hda_codec_write_cache(codec, pin_nid, 0,
1026 AC_VERB_SET_CONNECT_SEL,
1027 mux_idx);
1028}
1029
1030/* get the mux index for the converter of the pins
1031 * converter's mux index is the same for all pins on Intel platform
1032 */
1033static int intel_cvt_id_to_mux_idx(struct hdmi_spec *spec,
1034 hda_nid_t cvt_nid)
1035{
1036 int i;
1037
1038 for (i = 0; i < spec->num_cvts; i++)
1039 if (spec->cvt_nids[i] == cvt_nid)
1040 return i;
1041 return -EINVAL;
1042}
1043
1044/* Intel HDMI workaround to fix audio routing issue:
1045 * For some Intel display codecs, pins share the same connection list.
1046 * So a conveter can be selected by multiple pins and playback on any of these
1047 * pins will generate sound on the external display, because audio flows from
1048 * the same converter to the display pipeline. Also muting one pin may make
1049 * other pins have no sound output.
1050 * So this function assures that an assigned converter for a pin is not selected
1051 * by any other pins.
1052 */
1053static void intel_not_share_assigned_cvt(struct hda_codec *codec,
1054 hda_nid_t pin_nid,
1055 int dev_id, int mux_idx)
1056{
1057 struct hdmi_spec *spec = codec->spec;
1058 hda_nid_t nid;
1059 int cvt_idx, curr;
1060 struct hdmi_spec_per_cvt *per_cvt;
1061 struct hdmi_spec_per_pin *per_pin;
1062 int pin_idx;
1063
1064 /* configure the pins connections */
1065 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
1066 int dev_id_saved;
1067 int dev_num;
1068
1069 per_pin = get_pin(spec, pin_idx);
1070 /*
1071 * pin not connected to monitor
1072 * no need to operate on it
1073 */
1074 if (!per_pin->pcm)
1075 continue;
1076
1077 if ((per_pin->pin_nid == pin_nid) &&
1078 (per_pin->dev_id == dev_id))
1079 continue;
1080
1081 /*
1082 * if per_pin->dev_id >= dev_num,
1083 * snd_hda_get_dev_select() will fail,
1084 * and the following operation is unpredictable.
1085 * So skip this situation.
1086 */
1087 dev_num = snd_hda_get_num_devices(codec, per_pin->pin_nid) + 1;
1088 if (per_pin->dev_id >= dev_num)
1089 continue;
1090
1091 nid = per_pin->pin_nid;
1092
1093 /*
1094 * Calling this function should not impact
1095 * on the device entry selection
1096 * So let's save the dev id for each pin,
1097 * and restore it when return
1098 */
1099 dev_id_saved = snd_hda_get_dev_select(codec, nid);
1100 snd_hda_set_dev_select(codec, nid, per_pin->dev_id);
1101 curr = snd_hda_codec_read(codec, nid, 0,
1102 AC_VERB_GET_CONNECT_SEL, 0);
1103 if (curr != mux_idx) {
1104 snd_hda_set_dev_select(codec, nid, dev_id_saved);
1105 continue;
1106 }
1107
1108
1109 /* choose an unassigned converter. The conveters in the
1110 * connection list are in the same order as in the codec.
1111 */
1112 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) {
1113 per_cvt = get_cvt(spec, cvt_idx);
1114 if (!per_cvt->assigned) {
1115 codec_dbg(codec,
1116 "choose cvt %d for pin nid %d\n",
1117 cvt_idx, nid);
1118 snd_hda_codec_write_cache(codec, nid, 0,
1119 AC_VERB_SET_CONNECT_SEL,
1120 cvt_idx);
1121 break;
1122 }
1123 }
1124 snd_hda_set_dev_select(codec, nid, dev_id_saved);
1125 }
1126}
1127
1128/* A wrapper of intel_not_share_asigned_cvt() */
1129static void intel_not_share_assigned_cvt_nid(struct hda_codec *codec,
1130 hda_nid_t pin_nid, int dev_id, hda_nid_t cvt_nid)
1131{
1132 int mux_idx;
1133 struct hdmi_spec *spec = codec->spec;
1134
1135 /* On Intel platform, the mapping of converter nid to
1136 * mux index of the pins are always the same.
1137 * The pin nid may be 0, this means all pins will not
1138 * share the converter.
1139 */
1140 mux_idx = intel_cvt_id_to_mux_idx(spec, cvt_nid);
1141 if (mux_idx >= 0)
1142 intel_not_share_assigned_cvt(codec, pin_nid, dev_id, mux_idx);
1143}
1144
1145/* skeleton caller of pin_cvt_fixup ops */
1146static void pin_cvt_fixup(struct hda_codec *codec,
1147 struct hdmi_spec_per_pin *per_pin,
1148 hda_nid_t cvt_nid)
1149{
1150 struct hdmi_spec *spec = codec->spec;
1151
1152 if (spec->ops.pin_cvt_fixup)
1153 spec->ops.pin_cvt_fixup(codec, per_pin, cvt_nid);
1154}
1155
1156/* called in hdmi_pcm_open when no pin is assigned to the PCM
1157 * in dyn_pcm_assign mode.
1158 */
1159static int hdmi_pcm_open_no_pin(struct hda_pcm_stream *hinfo,
1160 struct hda_codec *codec,
1161 struct snd_pcm_substream *substream)
1162{
1163 struct hdmi_spec *spec = codec->spec;
1164 struct snd_pcm_runtime *runtime = substream->runtime;
1165 int cvt_idx, pcm_idx;
1166 struct hdmi_spec_per_cvt *per_cvt = NULL;
1167 int err;
1168
1169 pcm_idx = hinfo_to_pcm_index(codec, hinfo);
1170 if (pcm_idx < 0)
1171 return -EINVAL;
1172
1173 err = hdmi_choose_cvt(codec, -1, &cvt_idx);
1174 if (err)
1175 return err;
1176
1177 per_cvt = get_cvt(spec, cvt_idx);
1178 per_cvt->assigned = 1;
1179 hinfo->nid = per_cvt->cvt_nid;
1180
1181 pin_cvt_fixup(codec, NULL, per_cvt->cvt_nid);
1182
1183 set_bit(pcm_idx, &spec->pcm_in_use);
1184 /* todo: setup spdif ctls assign */
1185
1186 /* Initially set the converter's capabilities */
1187 hinfo->channels_min = per_cvt->channels_min;
1188 hinfo->channels_max = per_cvt->channels_max;
1189 hinfo->rates = per_cvt->rates;
1190 hinfo->formats = per_cvt->formats;
1191 hinfo->maxbps = per_cvt->maxbps;
1192
1193 /* Store the updated parameters */
1194 runtime->hw.channels_min = hinfo->channels_min;
1195 runtime->hw.channels_max = hinfo->channels_max;
1196 runtime->hw.formats = hinfo->formats;
1197 runtime->hw.rates = hinfo->rates;
1198
1199 snd_pcm_hw_constraint_step(substream->runtime, 0,
1200 SNDRV_PCM_HW_PARAM_CHANNELS, 2);
1201 return 0;
1202}
1203
1204/*
1205 * HDA PCM callbacks
1206 */
1207static int hdmi_pcm_open(struct hda_pcm_stream *hinfo,
1208 struct hda_codec *codec,
1209 struct snd_pcm_substream *substream)
1210{
1211 struct hdmi_spec *spec = codec->spec;
1212 struct snd_pcm_runtime *runtime = substream->runtime;
1213 int pin_idx, cvt_idx, pcm_idx;
1214 struct hdmi_spec_per_pin *per_pin;
1215 struct hdmi_eld *eld;
1216 struct hdmi_spec_per_cvt *per_cvt = NULL;
1217 int err;
1218
1219 /* Validate hinfo */
1220 pcm_idx = hinfo_to_pcm_index(codec, hinfo);
1221 if (pcm_idx < 0)
1222 return -EINVAL;
1223
1224 mutex_lock(&spec->pcm_lock);
1225 pin_idx = hinfo_to_pin_index(codec, hinfo);
1226 if (!spec->dyn_pcm_assign) {
1227 if (snd_BUG_ON(pin_idx < 0)) {
1228 err = -EINVAL;
1229 goto unlock;
1230 }
1231 } else {
1232 /* no pin is assigned to the PCM
1233 * PA need pcm open successfully when probe
1234 */
1235 if (pin_idx < 0) {
1236 err = hdmi_pcm_open_no_pin(hinfo, codec, substream);
1237 goto unlock;
1238 }
1239 }
1240
1241 err = hdmi_choose_cvt(codec, pin_idx, &cvt_idx);
1242 if (err < 0)
1243 goto unlock;
1244
1245 per_cvt = get_cvt(spec, cvt_idx);
1246 /* Claim converter */
1247 per_cvt->assigned = 1;
1248
1249 set_bit(pcm_idx, &spec->pcm_in_use);
1250 per_pin = get_pin(spec, pin_idx);
1251 per_pin->cvt_nid = per_cvt->cvt_nid;
1252 hinfo->nid = per_cvt->cvt_nid;
1253
1254 /* flip stripe flag for the assigned stream if supported */
1255 if (get_wcaps(codec, per_cvt->cvt_nid) & AC_WCAP_STRIPE)
1256 azx_stream(get_azx_dev(substream))->stripe = 1;
1257
1258 snd_hda_set_dev_select(codec, per_pin->pin_nid, per_pin->dev_id);
1259 snd_hda_codec_write_cache(codec, per_pin->pin_nid, 0,
1260 AC_VERB_SET_CONNECT_SEL,
1261 per_pin->mux_idx);
1262
1263 /* configure unused pins to choose other converters */
1264 pin_cvt_fixup(codec, per_pin, 0);
1265
1266 snd_hda_spdif_ctls_assign(codec, pcm_idx, per_cvt->cvt_nid);
1267
1268 /* Initially set the converter's capabilities */
1269 hinfo->channels_min = per_cvt->channels_min;
1270 hinfo->channels_max = per_cvt->channels_max;
1271 hinfo->rates = per_cvt->rates;
1272 hinfo->formats = per_cvt->formats;
1273 hinfo->maxbps = per_cvt->maxbps;
1274
1275 eld = &per_pin->sink_eld;
1276 /* Restrict capabilities by ELD if this isn't disabled */
1277 if (!static_hdmi_pcm && eld->eld_valid) {
1278 snd_hdmi_eld_update_pcm_info(&eld->info, hinfo);
1279 if (hinfo->channels_min > hinfo->channels_max ||
1280 !hinfo->rates || !hinfo->formats) {
1281 per_cvt->assigned = 0;
1282 hinfo->nid = 0;
1283 snd_hda_spdif_ctls_unassign(codec, pcm_idx);
1284 err = -ENODEV;
1285 goto unlock;
1286 }
1287 }
1288
1289 /* Store the updated parameters */
1290 runtime->hw.channels_min = hinfo->channels_min;
1291 runtime->hw.channels_max = hinfo->channels_max;
1292 runtime->hw.formats = hinfo->formats;
1293 runtime->hw.rates = hinfo->rates;
1294
1295 snd_pcm_hw_constraint_step(substream->runtime, 0,
1296 SNDRV_PCM_HW_PARAM_CHANNELS, 2);
1297 unlock:
1298 mutex_unlock(&spec->pcm_lock);
1299 return err;
1300}
1301
1302/*
1303 * HDA/HDMI auto parsing
1304 */
1305static int hdmi_read_pin_conn(struct hda_codec *codec, int pin_idx)
1306{
1307 struct hdmi_spec *spec = codec->spec;
1308 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
1309 hda_nid_t pin_nid = per_pin->pin_nid;
1310 int dev_id = per_pin->dev_id;
1311 int conns;
1312
1313 if (!(get_wcaps(codec, pin_nid) & AC_WCAP_CONN_LIST)) {
1314 codec_warn(codec,
1315 "HDMI: pin %d wcaps %#x does not support connection list\n",
1316 pin_nid, get_wcaps(codec, pin_nid));
1317 return -EINVAL;
1318 }
1319
1320 snd_hda_set_dev_select(codec, pin_nid, dev_id);
1321
1322 if (spec->intel_hsw_fixup) {
1323 conns = spec->num_cvts;
1324 memcpy(per_pin->mux_nids, spec->cvt_nids,
1325 sizeof(hda_nid_t) * conns);
1326 } else {
1327 conns = snd_hda_get_raw_connections(codec, pin_nid,
1328 per_pin->mux_nids,
1329 HDA_MAX_CONNECTIONS);
1330 }
1331
1332 /* all the device entries on the same pin have the same conn list */
1333 per_pin->num_mux_nids = conns;
1334
1335 return 0;
1336}
1337
1338static int hdmi_find_pcm_slot(struct hdmi_spec *spec,
1339 struct hdmi_spec_per_pin *per_pin)
1340{
1341 int i;
1342
1343 /*
1344 * generic_hdmi_build_pcms() may allocate extra PCMs on some
1345 * platforms (with maximum of 'num_nids + dev_num - 1')
1346 *
1347 * The per_pin of pin_nid_idx=n and dev_id=m prefers to get pcm-n
1348 * if m==0. This guarantees that dynamic pcm assignments are compatible
1349 * with the legacy static per_pin-pcm assignment that existed in the
1350 * days before DP-MST.
1351 *
1352 * Intel DP-MST prefers this legacy behavior for compatibility, too.
1353 *
1354 * per_pin of m!=0 prefers to get pcm=(num_nids + (m - 1)).
1355 */
1356
1357 if (per_pin->dev_id == 0 || spec->intel_hsw_fixup) {
1358 if (!test_bit(per_pin->pin_nid_idx, &spec->pcm_bitmap))
1359 return per_pin->pin_nid_idx;
1360 } else {
1361 i = spec->num_nids + (per_pin->dev_id - 1);
1362 if (i < spec->pcm_used && !(test_bit(i, &spec->pcm_bitmap)))
1363 return i;
1364 }
1365
1366 /* have a second try; check the area over num_nids */
1367 for (i = spec->num_nids; i < spec->pcm_used; i++) {
1368 if (!test_bit(i, &spec->pcm_bitmap))
1369 return i;
1370 }
1371
1372 /* the last try; check the empty slots in pins */
1373 for (i = 0; i < spec->num_nids; i++) {
1374 if (!test_bit(i, &spec->pcm_bitmap))
1375 return i;
1376 }
1377 return -EBUSY;
1378}
1379
1380static void hdmi_attach_hda_pcm(struct hdmi_spec *spec,
1381 struct hdmi_spec_per_pin *per_pin)
1382{
1383 int idx;
1384
1385 /* pcm already be attached to the pin */
1386 if (per_pin->pcm)
1387 return;
1388 idx = hdmi_find_pcm_slot(spec, per_pin);
1389 if (idx == -EBUSY)
1390 return;
1391 per_pin->pcm_idx = idx;
1392 per_pin->pcm = get_hdmi_pcm(spec, idx);
1393 set_bit(idx, &spec->pcm_bitmap);
1394}
1395
1396static void hdmi_detach_hda_pcm(struct hdmi_spec *spec,
1397 struct hdmi_spec_per_pin *per_pin)
1398{
1399 int idx;
1400
1401 /* pcm already be detached from the pin */
1402 if (!per_pin->pcm)
1403 return;
1404 idx = per_pin->pcm_idx;
1405 per_pin->pcm_idx = -1;
1406 per_pin->pcm = NULL;
1407 if (idx >= 0 && idx < spec->pcm_used)
1408 clear_bit(idx, &spec->pcm_bitmap);
1409}
1410
1411static int hdmi_get_pin_cvt_mux(struct hdmi_spec *spec,
1412 struct hdmi_spec_per_pin *per_pin, hda_nid_t cvt_nid)
1413{
1414 int mux_idx;
1415
1416 for (mux_idx = 0; mux_idx < per_pin->num_mux_nids; mux_idx++)
1417 if (per_pin->mux_nids[mux_idx] == cvt_nid)
1418 break;
1419 return mux_idx;
1420}
1421
1422static bool check_non_pcm_per_cvt(struct hda_codec *codec, hda_nid_t cvt_nid);
1423
1424static void hdmi_pcm_setup_pin(struct hdmi_spec *spec,
1425 struct hdmi_spec_per_pin *per_pin)
1426{
1427 struct hda_codec *codec = per_pin->codec;
1428 struct hda_pcm *pcm;
1429 struct hda_pcm_stream *hinfo;
1430 struct snd_pcm_substream *substream;
1431 int mux_idx;
1432 bool non_pcm;
1433
1434 if (per_pin->pcm_idx >= 0 && per_pin->pcm_idx < spec->pcm_used)
1435 pcm = get_pcm_rec(spec, per_pin->pcm_idx);
1436 else
1437 return;
1438 if (!pcm->pcm)
1439 return;
1440 if (!test_bit(per_pin->pcm_idx, &spec->pcm_in_use))
1441 return;
1442
1443 /* hdmi audio only uses playback and one substream */
1444 hinfo = pcm->stream;
1445 substream = pcm->pcm->streams[0].substream;
1446
1447 per_pin->cvt_nid = hinfo->nid;
1448
1449 mux_idx = hdmi_get_pin_cvt_mux(spec, per_pin, hinfo->nid);
1450 if (mux_idx < per_pin->num_mux_nids) {
1451 snd_hda_set_dev_select(codec, per_pin->pin_nid,
1452 per_pin->dev_id);
1453 snd_hda_codec_write_cache(codec, per_pin->pin_nid, 0,
1454 AC_VERB_SET_CONNECT_SEL,
1455 mux_idx);
1456 }
1457 snd_hda_spdif_ctls_assign(codec, per_pin->pcm_idx, hinfo->nid);
1458
1459 non_pcm = check_non_pcm_per_cvt(codec, hinfo->nid);
1460 if (substream->runtime)
1461 per_pin->channels = substream->runtime->channels;
1462 per_pin->setup = true;
1463 per_pin->mux_idx = mux_idx;
1464
1465 hdmi_setup_audio_infoframe(codec, per_pin, non_pcm);
1466}
1467
1468static void hdmi_pcm_reset_pin(struct hdmi_spec *spec,
1469 struct hdmi_spec_per_pin *per_pin)
1470{
1471 if (per_pin->pcm_idx >= 0 && per_pin->pcm_idx < spec->pcm_used)
1472 snd_hda_spdif_ctls_unassign(per_pin->codec, per_pin->pcm_idx);
1473
1474 per_pin->chmap_set = false;
1475 memset(per_pin->chmap, 0, sizeof(per_pin->chmap));
1476
1477 per_pin->setup = false;
1478 per_pin->channels = 0;
1479}
1480
1481static struct snd_jack *pin_idx_to_pcm_jack(struct hda_codec *codec,
1482 struct hdmi_spec_per_pin *per_pin)
1483{
1484 struct hdmi_spec *spec = codec->spec;
1485
1486 if (per_pin->pcm_idx >= 0)
1487 return spec->pcm_rec[per_pin->pcm_idx].jack;
1488 else
1489 return NULL;
1490}
1491
1492/* update per_pin ELD from the given new ELD;
1493 * setup info frame and notification accordingly
1494 * also notify ELD kctl and report jack status changes
1495 */
1496static void update_eld(struct hda_codec *codec,
1497 struct hdmi_spec_per_pin *per_pin,
1498 struct hdmi_eld *eld,
1499 int repoll)
1500{
1501 struct hdmi_eld *pin_eld = &per_pin->sink_eld;
1502 struct hdmi_spec *spec = codec->spec;
1503 struct snd_jack *pcm_jack;
1504 bool old_eld_valid = pin_eld->eld_valid;
1505 bool eld_changed;
1506 int pcm_idx;
1507
1508 if (eld->eld_valid) {
1509 if (eld->eld_size <= 0 ||
1510 snd_hdmi_parse_eld(codec, &eld->info, eld->eld_buffer,
1511 eld->eld_size) < 0) {
1512 eld->eld_valid = false;
1513 if (repoll) {
1514 schedule_delayed_work(&per_pin->work,
1515 msecs_to_jiffies(300));
1516 return;
1517 }
1518 }
1519 }
1520
1521 if (!eld->eld_valid || eld->eld_size <= 0) {
1522 eld->eld_valid = false;
1523 eld->eld_size = 0;
1524 }
1525
1526 /* for monitor disconnection, save pcm_idx firstly */
1527 pcm_idx = per_pin->pcm_idx;
1528
1529 /*
1530 * pcm_idx >=0 before update_eld() means it is in monitor
1531 * disconnected event. Jack must be fetched before update_eld().
1532 */
1533 pcm_jack = pin_idx_to_pcm_jack(codec, per_pin);
1534
1535 if (spec->dyn_pcm_assign) {
1536 if (eld->eld_valid) {
1537 hdmi_attach_hda_pcm(spec, per_pin);
1538 hdmi_pcm_setup_pin(spec, per_pin);
1539 } else {
1540 hdmi_pcm_reset_pin(spec, per_pin);
1541 hdmi_detach_hda_pcm(spec, per_pin);
1542 }
1543 }
1544 /* if pcm_idx == -1, it means this is in monitor connection event
1545 * we can get the correct pcm_idx now.
1546 */
1547 if (pcm_idx == -1)
1548 pcm_idx = per_pin->pcm_idx;
1549 if (!pcm_jack)
1550 pcm_jack = pin_idx_to_pcm_jack(codec, per_pin);
1551
1552 if (eld->eld_valid)
1553 snd_hdmi_show_eld(codec, &eld->info);
1554
1555 eld_changed = (pin_eld->eld_valid != eld->eld_valid);
1556 eld_changed |= (pin_eld->monitor_present != eld->monitor_present);
1557 if (!eld_changed && eld->eld_valid && pin_eld->eld_valid)
1558 if (pin_eld->eld_size != eld->eld_size ||
1559 memcmp(pin_eld->eld_buffer, eld->eld_buffer,
1560 eld->eld_size) != 0)
1561 eld_changed = true;
1562
1563 if (eld_changed) {
1564 pin_eld->monitor_present = eld->monitor_present;
1565 pin_eld->eld_valid = eld->eld_valid;
1566 pin_eld->eld_size = eld->eld_size;
1567 if (eld->eld_valid)
1568 memcpy(pin_eld->eld_buffer, eld->eld_buffer,
1569 eld->eld_size);
1570 pin_eld->info = eld->info;
1571 }
1572
1573 /*
1574 * Re-setup pin and infoframe. This is needed e.g. when
1575 * - sink is first plugged-in
1576 * - transcoder can change during stream playback on Haswell
1577 * and this can make HW reset converter selection on a pin.
1578 */
1579 if (eld->eld_valid && !old_eld_valid && per_pin->setup) {
1580 pin_cvt_fixup(codec, per_pin, 0);
1581 hdmi_setup_audio_infoframe(codec, per_pin, per_pin->non_pcm);
1582 }
1583
1584 if (eld_changed && pcm_idx >= 0)
1585 snd_ctl_notify(codec->card,
1586 SNDRV_CTL_EVENT_MASK_VALUE |
1587 SNDRV_CTL_EVENT_MASK_INFO,
1588 &get_hdmi_pcm(spec, pcm_idx)->eld_ctl->id);
1589
1590 if (eld_changed && pcm_jack)
1591 snd_jack_report(pcm_jack,
1592 (eld->monitor_present && eld->eld_valid) ?
1593 SND_JACK_AVOUT : 0);
1594}
1595
1596/* update ELD and jack state via HD-audio verbs */
1597static void hdmi_present_sense_via_verbs(struct hdmi_spec_per_pin *per_pin,
1598 int repoll)
1599{
1600 struct hda_codec *codec = per_pin->codec;
1601 struct hdmi_spec *spec = codec->spec;
1602 struct hdmi_eld *eld = &spec->temp_eld;
1603 hda_nid_t pin_nid = per_pin->pin_nid;
1604 int dev_id = per_pin->dev_id;
1605 /*
1606 * Always execute a GetPinSense verb here, even when called from
1607 * hdmi_intrinsic_event; for some NVIDIA HW, the unsolicited
1608 * response's PD bit is not the real PD value, but indicates that
1609 * the real PD value changed. An older version of the HD-audio
1610 * specification worked this way. Hence, we just ignore the data in
1611 * the unsolicited response to avoid custom WARs.
1612 */
1613 int present;
1614 int ret;
1615
1616 ret = snd_hda_power_up_pm(codec);
1617 if (ret < 0 && pm_runtime_suspended(hda_codec_dev(codec)))
1618 goto out;
1619
1620 present = snd_hda_jack_pin_sense(codec, pin_nid, dev_id);
1621
1622 mutex_lock(&per_pin->lock);
1623 eld->monitor_present = !!(present & AC_PINSENSE_PRESENCE);
1624 if (eld->monitor_present)
1625 eld->eld_valid = !!(present & AC_PINSENSE_ELDV);
1626 else
1627 eld->eld_valid = false;
1628
1629 codec_dbg(codec,
1630 "HDMI status: Codec=%d Pin=%d Presence_Detect=%d ELD_Valid=%d\n",
1631 codec->addr, pin_nid, eld->monitor_present, eld->eld_valid);
1632
1633 if (eld->eld_valid) {
1634 if (spec->ops.pin_get_eld(codec, pin_nid, dev_id,
1635 eld->eld_buffer, &eld->eld_size) < 0)
1636 eld->eld_valid = false;
1637 }
1638
1639 update_eld(codec, per_pin, eld, repoll);
1640 mutex_unlock(&per_pin->lock);
1641 out:
1642 snd_hda_power_down_pm(codec);
1643}
1644
1645static void silent_stream_enable(struct hda_codec *codec,
1646 struct hdmi_spec_per_pin *per_pin)
1647{
1648 unsigned int newval, oldval;
1649
1650 codec_dbg(codec, "hdmi: enabling silent stream for NID %d\n",
1651 per_pin->pin_nid);
1652
1653 mutex_lock(&per_pin->lock);
1654
1655 if (!per_pin->channels)
1656 per_pin->channels = 2;
1657
1658 oldval = snd_hda_codec_read(codec, per_pin->pin_nid, 0,
1659 AC_VERB_GET_CONV, 0);
1660 newval = (oldval & 0xF0) | 0xF;
1661 snd_hda_codec_write(codec, per_pin->pin_nid, 0,
1662 AC_VERB_SET_CHANNEL_STREAMID, newval);
1663
1664 hdmi_setup_audio_infoframe(codec, per_pin, per_pin->non_pcm);
1665
1666 mutex_unlock(&per_pin->lock);
1667}
1668
1669/* update ELD and jack state via audio component */
1670static void sync_eld_via_acomp(struct hda_codec *codec,
1671 struct hdmi_spec_per_pin *per_pin)
1672{
1673 struct hdmi_spec *spec = codec->spec;
1674 struct hdmi_eld *eld = &spec->temp_eld;
1675 bool monitor_prev, monitor_next;
1676
1677 mutex_lock(&per_pin->lock);
1678 eld->monitor_present = false;
1679 monitor_prev = per_pin->sink_eld.monitor_present;
1680 eld->eld_size = snd_hdac_acomp_get_eld(&codec->core, per_pin->pin_nid,
1681 per_pin->dev_id, &eld->monitor_present,
1682 eld->eld_buffer, ELD_MAX_SIZE);
1683 eld->eld_valid = (eld->eld_size > 0);
1684 update_eld(codec, per_pin, eld, 0);
1685 monitor_next = per_pin->sink_eld.monitor_present;
1686 mutex_unlock(&per_pin->lock);
1687
1688 /*
1689 * Power-up will call hdmi_present_sense, so the PM calls
1690 * have to be done without mutex held.
1691 */
1692
1693 if (spec->send_silent_stream) {
1694 int pm_ret;
1695
1696 if (!monitor_prev && monitor_next) {
1697 pm_ret = snd_hda_power_up_pm(codec);
1698 if (pm_ret < 0)
1699 codec_err(codec,
1700 "Monitor plugged-in, Failed to power up codec ret=[%d]\n",
1701 pm_ret);
1702 silent_stream_enable(codec, per_pin);
1703 } else if (monitor_prev && !monitor_next) {
1704 pm_ret = snd_hda_power_down_pm(codec);
1705 if (pm_ret < 0)
1706 codec_err(codec,
1707 "Monitor plugged-out, Failed to power down codec ret=[%d]\n",
1708 pm_ret);
1709 }
1710 }
1711}
1712
1713static void hdmi_present_sense(struct hdmi_spec_per_pin *per_pin, int repoll)
1714{
1715 struct hda_codec *codec = per_pin->codec;
1716
1717 if (!codec_has_acomp(codec))
1718 hdmi_present_sense_via_verbs(per_pin, repoll);
1719 else
1720 sync_eld_via_acomp(codec, per_pin);
1721}
1722
1723static void hdmi_repoll_eld(struct work_struct *work)
1724{
1725 struct hdmi_spec_per_pin *per_pin =
1726 container_of(to_delayed_work(work), struct hdmi_spec_per_pin, work);
1727 struct hda_codec *codec = per_pin->codec;
1728 struct hdmi_spec *spec = codec->spec;
1729 struct hda_jack_tbl *jack;
1730
1731 jack = snd_hda_jack_tbl_get_mst(codec, per_pin->pin_nid,
1732 per_pin->dev_id);
1733 if (jack)
1734 jack->jack_dirty = 1;
1735
1736 if (per_pin->repoll_count++ > 6)
1737 per_pin->repoll_count = 0;
1738
1739 mutex_lock(&spec->pcm_lock);
1740 hdmi_present_sense(per_pin, per_pin->repoll_count);
1741 mutex_unlock(&spec->pcm_lock);
1742}
1743
1744static int hdmi_add_pin(struct hda_codec *codec, hda_nid_t pin_nid)
1745{
1746 struct hdmi_spec *spec = codec->spec;
1747 unsigned int caps, config;
1748 int pin_idx;
1749 struct hdmi_spec_per_pin *per_pin;
1750 int err;
1751 int dev_num, i;
1752
1753 caps = snd_hda_query_pin_caps(codec, pin_nid);
1754 if (!(caps & (AC_PINCAP_HDMI | AC_PINCAP_DP)))
1755 return 0;
1756
1757 /*
1758 * For DP MST audio, Configuration Default is the same for
1759 * all device entries on the same pin
1760 */
1761 config = snd_hda_codec_get_pincfg(codec, pin_nid);
1762 if (get_defcfg_connect(config) == AC_JACK_PORT_NONE &&
1763 !spec->force_connect)
1764 return 0;
1765
1766 /*
1767 * To simplify the implementation, malloc all
1768 * the virtual pins in the initialization statically
1769 */
1770 if (spec->intel_hsw_fixup) {
1771 /*
1772 * On Intel platforms, device entries number is
1773 * changed dynamically. If there is a DP MST
1774 * hub connected, the device entries number is 3.
1775 * Otherwise, it is 1.
1776 * Here we manually set dev_num to 3, so that
1777 * we can initialize all the device entries when
1778 * bootup statically.
1779 */
1780 dev_num = 3;
1781 spec->dev_num = 3;
1782 } else if (spec->dyn_pcm_assign && codec->dp_mst) {
1783 dev_num = snd_hda_get_num_devices(codec, pin_nid) + 1;
1784 /*
1785 * spec->dev_num is the maxinum number of device entries
1786 * among all the pins
1787 */
1788 spec->dev_num = (spec->dev_num > dev_num) ?
1789 spec->dev_num : dev_num;
1790 } else {
1791 /*
1792 * If the platform doesn't support DP MST,
1793 * manually set dev_num to 1. This means
1794 * the pin has only one device entry.
1795 */
1796 dev_num = 1;
1797 spec->dev_num = 1;
1798 }
1799
1800 for (i = 0; i < dev_num; i++) {
1801 pin_idx = spec->num_pins;
1802 per_pin = snd_array_new(&spec->pins);
1803
1804 if (!per_pin)
1805 return -ENOMEM;
1806
1807 if (spec->dyn_pcm_assign) {
1808 per_pin->pcm = NULL;
1809 per_pin->pcm_idx = -1;
1810 } else {
1811 per_pin->pcm = get_hdmi_pcm(spec, pin_idx);
1812 per_pin->pcm_idx = pin_idx;
1813 }
1814 per_pin->pin_nid = pin_nid;
1815 per_pin->pin_nid_idx = spec->num_nids;
1816 per_pin->dev_id = i;
1817 per_pin->non_pcm = false;
1818 snd_hda_set_dev_select(codec, pin_nid, i);
1819 err = hdmi_read_pin_conn(codec, pin_idx);
1820 if (err < 0)
1821 return err;
1822 spec->num_pins++;
1823 }
1824 spec->num_nids++;
1825
1826 return 0;
1827}
1828
1829static int hdmi_add_cvt(struct hda_codec *codec, hda_nid_t cvt_nid)
1830{
1831 struct hdmi_spec *spec = codec->spec;
1832 struct hdmi_spec_per_cvt *per_cvt;
1833 unsigned int chans;
1834 int err;
1835
1836 chans = get_wcaps(codec, cvt_nid);
1837 chans = get_wcaps_channels(chans);
1838
1839 per_cvt = snd_array_new(&spec->cvts);
1840 if (!per_cvt)
1841 return -ENOMEM;
1842
1843 per_cvt->cvt_nid = cvt_nid;
1844 per_cvt->channels_min = 2;
1845 if (chans <= 16) {
1846 per_cvt->channels_max = chans;
1847 if (chans > spec->chmap.channels_max)
1848 spec->chmap.channels_max = chans;
1849 }
1850
1851 err = snd_hda_query_supported_pcm(codec, cvt_nid,
1852 &per_cvt->rates,
1853 &per_cvt->formats,
1854 &per_cvt->maxbps);
1855 if (err < 0)
1856 return err;
1857
1858 if (spec->num_cvts < ARRAY_SIZE(spec->cvt_nids))
1859 spec->cvt_nids[spec->num_cvts] = cvt_nid;
1860 spec->num_cvts++;
1861
1862 return 0;
1863}
1864
1865static const struct snd_pci_quirk force_connect_list[] = {
1866 SND_PCI_QUIRK(0x103c, 0x870f, "HP", 1),
1867 SND_PCI_QUIRK(0x103c, 0x871a, "HP", 1),
1868 {}
1869};
1870
1871static int hdmi_parse_codec(struct hda_codec *codec)
1872{
1873 struct hdmi_spec *spec = codec->spec;
1874 hda_nid_t start_nid;
1875 unsigned int caps;
1876 int i, nodes;
1877 const struct snd_pci_quirk *q;
1878
1879 nodes = snd_hda_get_sub_nodes(codec, codec->core.afg, &start_nid);
1880 if (!start_nid || nodes < 0) {
1881 codec_warn(codec, "HDMI: failed to get afg sub nodes\n");
1882 return -EINVAL;
1883 }
1884
1885 q = snd_pci_quirk_lookup(codec->bus->pci, force_connect_list);
1886
1887 if (q && q->value)
1888 spec->force_connect = true;
1889
1890 /*
1891 * hdmi_add_pin() assumes total amount of converters to
1892 * be known, so first discover all converters
1893 */
1894 for (i = 0; i < nodes; i++) {
1895 hda_nid_t nid = start_nid + i;
1896
1897 caps = get_wcaps(codec, nid);
1898
1899 if (!(caps & AC_WCAP_DIGITAL))
1900 continue;
1901
1902 if (get_wcaps_type(caps) == AC_WID_AUD_OUT)
1903 hdmi_add_cvt(codec, nid);
1904 }
1905
1906 /* discover audio pins */
1907 for (i = 0; i < nodes; i++) {
1908 hda_nid_t nid = start_nid + i;
1909
1910 caps = get_wcaps(codec, nid);
1911
1912 if (!(caps & AC_WCAP_DIGITAL))
1913 continue;
1914
1915 if (get_wcaps_type(caps) == AC_WID_PIN)
1916 hdmi_add_pin(codec, nid);
1917 }
1918
1919 return 0;
1920}
1921
1922/*
1923 */
1924static bool check_non_pcm_per_cvt(struct hda_codec *codec, hda_nid_t cvt_nid)
1925{
1926 struct hda_spdif_out *spdif;
1927 bool non_pcm;
1928
1929 mutex_lock(&codec->spdif_mutex);
1930 spdif = snd_hda_spdif_out_of_nid(codec, cvt_nid);
1931 /* Add sanity check to pass klockwork check.
1932 * This should never happen.
1933 */
1934 if (WARN_ON(spdif == NULL)) {
1935 mutex_unlock(&codec->spdif_mutex);
1936 return true;
1937 }
1938 non_pcm = !!(spdif->status & IEC958_AES0_NONAUDIO);
1939 mutex_unlock(&codec->spdif_mutex);
1940 return non_pcm;
1941}
1942
1943/*
1944 * HDMI callbacks
1945 */
1946
1947static int generic_hdmi_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
1948 struct hda_codec *codec,
1949 unsigned int stream_tag,
1950 unsigned int format,
1951 struct snd_pcm_substream *substream)
1952{
1953 hda_nid_t cvt_nid = hinfo->nid;
1954 struct hdmi_spec *spec = codec->spec;
1955 int pin_idx;
1956 struct hdmi_spec_per_pin *per_pin;
1957 struct snd_pcm_runtime *runtime = substream->runtime;
1958 bool non_pcm;
1959 int pinctl, stripe;
1960 int err = 0;
1961
1962 mutex_lock(&spec->pcm_lock);
1963 pin_idx = hinfo_to_pin_index(codec, hinfo);
1964 if (spec->dyn_pcm_assign && pin_idx < 0) {
1965 /* when dyn_pcm_assign and pcm is not bound to a pin
1966 * skip pin setup and return 0 to make audio playback
1967 * be ongoing
1968 */
1969 pin_cvt_fixup(codec, NULL, cvt_nid);
1970 snd_hda_codec_setup_stream(codec, cvt_nid,
1971 stream_tag, 0, format);
1972 goto unlock;
1973 }
1974
1975 if (snd_BUG_ON(pin_idx < 0)) {
1976 err = -EINVAL;
1977 goto unlock;
1978 }
1979 per_pin = get_pin(spec, pin_idx);
1980
1981 /* Verify pin:cvt selections to avoid silent audio after S3.
1982 * After S3, the audio driver restores pin:cvt selections
1983 * but this can happen before gfx is ready and such selection
1984 * is overlooked by HW. Thus multiple pins can share a same
1985 * default convertor and mute control will affect each other,
1986 * which can cause a resumed audio playback become silent
1987 * after S3.
1988 */
1989 pin_cvt_fixup(codec, per_pin, 0);
1990
1991 /* Call sync_audio_rate to set the N/CTS/M manually if necessary */
1992 /* Todo: add DP1.2 MST audio support later */
1993 if (codec_has_acomp(codec))
1994 snd_hdac_sync_audio_rate(&codec->core, per_pin->pin_nid,
1995 per_pin->dev_id, runtime->rate);
1996
1997 non_pcm = check_non_pcm_per_cvt(codec, cvt_nid);
1998 mutex_lock(&per_pin->lock);
1999 per_pin->channels = substream->runtime->channels;
2000 per_pin->setup = true;
2001
2002 if (get_wcaps(codec, cvt_nid) & AC_WCAP_STRIPE) {
2003 stripe = snd_hdac_get_stream_stripe_ctl(&codec->bus->core,
2004 substream);
2005 snd_hda_codec_write(codec, cvt_nid, 0,
2006 AC_VERB_SET_STRIPE_CONTROL,
2007 stripe);
2008 }
2009
2010 hdmi_setup_audio_infoframe(codec, per_pin, non_pcm);
2011 mutex_unlock(&per_pin->lock);
2012 if (spec->dyn_pin_out) {
2013 snd_hda_set_dev_select(codec, per_pin->pin_nid,
2014 per_pin->dev_id);
2015 pinctl = snd_hda_codec_read(codec, per_pin->pin_nid, 0,
2016 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
2017 snd_hda_codec_write(codec, per_pin->pin_nid, 0,
2018 AC_VERB_SET_PIN_WIDGET_CONTROL,
2019 pinctl | PIN_OUT);
2020 }
2021
2022 /* snd_hda_set_dev_select() has been called before */
2023 err = spec->ops.setup_stream(codec, cvt_nid, per_pin->pin_nid,
2024 per_pin->dev_id, stream_tag, format);
2025 unlock:
2026 mutex_unlock(&spec->pcm_lock);
2027 return err;
2028}
2029
2030static int generic_hdmi_playback_pcm_cleanup(struct hda_pcm_stream *hinfo,
2031 struct hda_codec *codec,
2032 struct snd_pcm_substream *substream)
2033{
2034 snd_hda_codec_cleanup_stream(codec, hinfo->nid);
2035 return 0;
2036}
2037
2038static int hdmi_pcm_close(struct hda_pcm_stream *hinfo,
2039 struct hda_codec *codec,
2040 struct snd_pcm_substream *substream)
2041{
2042 struct hdmi_spec *spec = codec->spec;
2043 int cvt_idx, pin_idx, pcm_idx;
2044 struct hdmi_spec_per_cvt *per_cvt;
2045 struct hdmi_spec_per_pin *per_pin;
2046 int pinctl;
2047 int err = 0;
2048
2049 if (hinfo->nid) {
2050 pcm_idx = hinfo_to_pcm_index(codec, hinfo);
2051 if (snd_BUG_ON(pcm_idx < 0))
2052 return -EINVAL;
2053 cvt_idx = cvt_nid_to_cvt_index(codec, hinfo->nid);
2054 if (snd_BUG_ON(cvt_idx < 0))
2055 return -EINVAL;
2056 per_cvt = get_cvt(spec, cvt_idx);
2057
2058 snd_BUG_ON(!per_cvt->assigned);
2059 per_cvt->assigned = 0;
2060 hinfo->nid = 0;
2061
2062 azx_stream(get_azx_dev(substream))->stripe = 0;
2063
2064 mutex_lock(&spec->pcm_lock);
2065 snd_hda_spdif_ctls_unassign(codec, pcm_idx);
2066 clear_bit(pcm_idx, &spec->pcm_in_use);
2067 pin_idx = hinfo_to_pin_index(codec, hinfo);
2068 if (spec->dyn_pcm_assign && pin_idx < 0)
2069 goto unlock;
2070
2071 if (snd_BUG_ON(pin_idx < 0)) {
2072 err = -EINVAL;
2073 goto unlock;
2074 }
2075 per_pin = get_pin(spec, pin_idx);
2076
2077 if (spec->dyn_pin_out) {
2078 snd_hda_set_dev_select(codec, per_pin->pin_nid,
2079 per_pin->dev_id);
2080 pinctl = snd_hda_codec_read(codec, per_pin->pin_nid, 0,
2081 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
2082 snd_hda_codec_write(codec, per_pin->pin_nid, 0,
2083 AC_VERB_SET_PIN_WIDGET_CONTROL,
2084 pinctl & ~PIN_OUT);
2085 }
2086
2087 mutex_lock(&per_pin->lock);
2088 per_pin->chmap_set = false;
2089 memset(per_pin->chmap, 0, sizeof(per_pin->chmap));
2090
2091 per_pin->setup = false;
2092 per_pin->channels = 0;
2093 mutex_unlock(&per_pin->lock);
2094 unlock:
2095 mutex_unlock(&spec->pcm_lock);
2096 }
2097
2098 return err;
2099}
2100
2101static const struct hda_pcm_ops generic_ops = {
2102 .open = hdmi_pcm_open,
2103 .close = hdmi_pcm_close,
2104 .prepare = generic_hdmi_playback_pcm_prepare,
2105 .cleanup = generic_hdmi_playback_pcm_cleanup,
2106};
2107
2108static int hdmi_get_spk_alloc(struct hdac_device *hdac, int pcm_idx)
2109{
2110 struct hda_codec *codec = hdac_to_hda_codec(hdac);
2111 struct hdmi_spec *spec = codec->spec;
2112 struct hdmi_spec_per_pin *per_pin = pcm_idx_to_pin(spec, pcm_idx);
2113
2114 if (!per_pin)
2115 return 0;
2116
2117 return per_pin->sink_eld.info.spk_alloc;
2118}
2119
2120static void hdmi_get_chmap(struct hdac_device *hdac, int pcm_idx,
2121 unsigned char *chmap)
2122{
2123 struct hda_codec *codec = hdac_to_hda_codec(hdac);
2124 struct hdmi_spec *spec = codec->spec;
2125 struct hdmi_spec_per_pin *per_pin = pcm_idx_to_pin(spec, pcm_idx);
2126
2127 /* chmap is already set to 0 in caller */
2128 if (!per_pin)
2129 return;
2130
2131 memcpy(chmap, per_pin->chmap, ARRAY_SIZE(per_pin->chmap));
2132}
2133
2134static void hdmi_set_chmap(struct hdac_device *hdac, int pcm_idx,
2135 unsigned char *chmap, int prepared)
2136{
2137 struct hda_codec *codec = hdac_to_hda_codec(hdac);
2138 struct hdmi_spec *spec = codec->spec;
2139 struct hdmi_spec_per_pin *per_pin = pcm_idx_to_pin(spec, pcm_idx);
2140
2141 if (!per_pin)
2142 return;
2143 mutex_lock(&per_pin->lock);
2144 per_pin->chmap_set = true;
2145 memcpy(per_pin->chmap, chmap, ARRAY_SIZE(per_pin->chmap));
2146 if (prepared)
2147 hdmi_setup_audio_infoframe(codec, per_pin, per_pin->non_pcm);
2148 mutex_unlock(&per_pin->lock);
2149}
2150
2151static bool is_hdmi_pcm_attached(struct hdac_device *hdac, int pcm_idx)
2152{
2153 struct hda_codec *codec = hdac_to_hda_codec(hdac);
2154 struct hdmi_spec *spec = codec->spec;
2155 struct hdmi_spec_per_pin *per_pin = pcm_idx_to_pin(spec, pcm_idx);
2156
2157 return per_pin ? true:false;
2158}
2159
2160static int generic_hdmi_build_pcms(struct hda_codec *codec)
2161{
2162 struct hdmi_spec *spec = codec->spec;
2163 int idx, pcm_num;
2164
2165 /*
2166 * for non-mst mode, pcm number is the same as before
2167 * for DP MST mode without extra PCM, pcm number is same
2168 * for DP MST mode with extra PCMs, pcm number is
2169 * (nid number + dev_num - 1)
2170 * dev_num is the device entry number in a pin
2171 */
2172
2173 if (codec->mst_no_extra_pcms)
2174 pcm_num = spec->num_nids;
2175 else
2176 pcm_num = spec->num_nids + spec->dev_num - 1;
2177
2178 codec_dbg(codec, "hdmi: pcm_num set to %d\n", pcm_num);
2179
2180 for (idx = 0; idx < pcm_num; idx++) {
2181 struct hda_pcm *info;
2182 struct hda_pcm_stream *pstr;
2183
2184 info = snd_hda_codec_pcm_new(codec, "HDMI %d", idx);
2185 if (!info)
2186 return -ENOMEM;
2187
2188 spec->pcm_rec[idx].pcm = info;
2189 spec->pcm_used++;
2190 info->pcm_type = HDA_PCM_TYPE_HDMI;
2191 info->own_chmap = true;
2192
2193 pstr = &info->stream[SNDRV_PCM_STREAM_PLAYBACK];
2194 pstr->substreams = 1;
2195 pstr->ops = generic_ops;
2196 /* pcm number is less than 16 */
2197 if (spec->pcm_used >= 16)
2198 break;
2199 /* other pstr fields are set in open */
2200 }
2201
2202 return 0;
2203}
2204
2205static void free_hdmi_jack_priv(struct snd_jack *jack)
2206{
2207 struct hdmi_pcm *pcm = jack->private_data;
2208
2209 pcm->jack = NULL;
2210}
2211
2212static int generic_hdmi_build_jack(struct hda_codec *codec, int pcm_idx)
2213{
2214 char hdmi_str[32] = "HDMI/DP";
2215 struct hdmi_spec *spec = codec->spec;
2216 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pcm_idx);
2217 struct snd_jack *jack;
2218 int pcmdev = get_pcm_rec(spec, pcm_idx)->device;
2219 int err;
2220
2221 if (pcmdev > 0)
2222 sprintf(hdmi_str + strlen(hdmi_str), ",pcm=%d", pcmdev);
2223 if (!spec->dyn_pcm_assign &&
2224 !is_jack_detectable(codec, per_pin->pin_nid))
2225 strncat(hdmi_str, " Phantom",
2226 sizeof(hdmi_str) - strlen(hdmi_str) - 1);
2227
2228 err = snd_jack_new(codec->card, hdmi_str, SND_JACK_AVOUT, &jack,
2229 true, false);
2230 if (err < 0)
2231 return err;
2232
2233 spec->pcm_rec[pcm_idx].jack = jack;
2234 jack->private_data = &spec->pcm_rec[pcm_idx];
2235 jack->private_free = free_hdmi_jack_priv;
2236 return 0;
2237}
2238
2239static int generic_hdmi_build_controls(struct hda_codec *codec)
2240{
2241 struct hdmi_spec *spec = codec->spec;
2242 int dev, err;
2243 int pin_idx, pcm_idx;
2244
2245 for (pcm_idx = 0; pcm_idx < spec->pcm_used; pcm_idx++) {
2246 if (!get_pcm_rec(spec, pcm_idx)->pcm) {
2247 /* no PCM: mark this for skipping permanently */
2248 set_bit(pcm_idx, &spec->pcm_bitmap);
2249 continue;
2250 }
2251
2252 err = generic_hdmi_build_jack(codec, pcm_idx);
2253 if (err < 0)
2254 return err;
2255
2256 /* create the spdif for each pcm
2257 * pin will be bound when monitor is connected
2258 */
2259 if (spec->dyn_pcm_assign)
2260 err = snd_hda_create_dig_out_ctls(codec,
2261 0, spec->cvt_nids[0],
2262 HDA_PCM_TYPE_HDMI);
2263 else {
2264 struct hdmi_spec_per_pin *per_pin =
2265 get_pin(spec, pcm_idx);
2266 err = snd_hda_create_dig_out_ctls(codec,
2267 per_pin->pin_nid,
2268 per_pin->mux_nids[0],
2269 HDA_PCM_TYPE_HDMI);
2270 }
2271 if (err < 0)
2272 return err;
2273 snd_hda_spdif_ctls_unassign(codec, pcm_idx);
2274
2275 dev = get_pcm_rec(spec, pcm_idx)->device;
2276 if (dev != SNDRV_PCM_INVALID_DEVICE) {
2277 /* add control for ELD Bytes */
2278 err = hdmi_create_eld_ctl(codec, pcm_idx, dev);
2279 if (err < 0)
2280 return err;
2281 }
2282 }
2283
2284 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2285 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2286 struct hdmi_eld *pin_eld = &per_pin->sink_eld;
2287
2288 pin_eld->eld_valid = false;
2289 hdmi_present_sense(per_pin, 0);
2290 }
2291
2292 /* add channel maps */
2293 for (pcm_idx = 0; pcm_idx < spec->pcm_used; pcm_idx++) {
2294 struct hda_pcm *pcm;
2295
2296 pcm = get_pcm_rec(spec, pcm_idx);
2297 if (!pcm || !pcm->pcm)
2298 break;
2299 err = snd_hdac_add_chmap_ctls(pcm->pcm, pcm_idx, &spec->chmap);
2300 if (err < 0)
2301 return err;
2302 }
2303
2304 return 0;
2305}
2306
2307static int generic_hdmi_init_per_pins(struct hda_codec *codec)
2308{
2309 struct hdmi_spec *spec = codec->spec;
2310 int pin_idx;
2311
2312 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2313 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2314
2315 per_pin->codec = codec;
2316 mutex_init(&per_pin->lock);
2317 INIT_DELAYED_WORK(&per_pin->work, hdmi_repoll_eld);
2318 eld_proc_new(per_pin, pin_idx);
2319 }
2320 return 0;
2321}
2322
2323static int generic_hdmi_init(struct hda_codec *codec)
2324{
2325 struct hdmi_spec *spec = codec->spec;
2326 int pin_idx;
2327
2328 mutex_lock(&spec->bind_lock);
2329 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2330 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2331 hda_nid_t pin_nid = per_pin->pin_nid;
2332 int dev_id = per_pin->dev_id;
2333
2334 snd_hda_set_dev_select(codec, pin_nid, dev_id);
2335 hdmi_init_pin(codec, pin_nid);
2336 if (codec_has_acomp(codec))
2337 continue;
2338 snd_hda_jack_detect_enable_callback_mst(codec, pin_nid, dev_id,
2339 jack_callback);
2340 }
2341 mutex_unlock(&spec->bind_lock);
2342 return 0;
2343}
2344
2345static void hdmi_array_init(struct hdmi_spec *spec, int nums)
2346{
2347 snd_array_init(&spec->pins, sizeof(struct hdmi_spec_per_pin), nums);
2348 snd_array_init(&spec->cvts, sizeof(struct hdmi_spec_per_cvt), nums);
2349}
2350
2351static void hdmi_array_free(struct hdmi_spec *spec)
2352{
2353 snd_array_free(&spec->pins);
2354 snd_array_free(&spec->cvts);
2355}
2356
2357static void generic_spec_free(struct hda_codec *codec)
2358{
2359 struct hdmi_spec *spec = codec->spec;
2360
2361 if (spec) {
2362 hdmi_array_free(spec);
2363 kfree(spec);
2364 codec->spec = NULL;
2365 }
2366 codec->dp_mst = false;
2367}
2368
2369static void generic_hdmi_free(struct hda_codec *codec)
2370{
2371 struct hdmi_spec *spec = codec->spec;
2372 int pin_idx, pcm_idx;
2373
2374 if (spec->acomp_registered) {
2375 snd_hdac_acomp_exit(&codec->bus->core);
2376 } else if (codec_has_acomp(codec)) {
2377 snd_hdac_acomp_register_notifier(&codec->bus->core, NULL);
2378 }
2379 codec->relaxed_resume = 0;
2380
2381 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2382 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2383 cancel_delayed_work_sync(&per_pin->work);
2384 eld_proc_free(per_pin);
2385 }
2386
2387 for (pcm_idx = 0; pcm_idx < spec->pcm_used; pcm_idx++) {
2388 if (spec->pcm_rec[pcm_idx].jack == NULL)
2389 continue;
2390 if (spec->dyn_pcm_assign)
2391 snd_device_free(codec->card,
2392 spec->pcm_rec[pcm_idx].jack);
2393 else
2394 spec->pcm_rec[pcm_idx].jack = NULL;
2395 }
2396
2397 generic_spec_free(codec);
2398}
2399
2400#ifdef CONFIG_PM
2401static int generic_hdmi_resume(struct hda_codec *codec)
2402{
2403 struct hdmi_spec *spec = codec->spec;
2404 int pin_idx;
2405
2406 codec->patch_ops.init(codec);
2407 snd_hda_regmap_sync(codec);
2408
2409 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2410 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2411 hdmi_present_sense(per_pin, 1);
2412 }
2413 return 0;
2414}
2415#endif
2416
2417static const struct hda_codec_ops generic_hdmi_patch_ops = {
2418 .init = generic_hdmi_init,
2419 .free = generic_hdmi_free,
2420 .build_pcms = generic_hdmi_build_pcms,
2421 .build_controls = generic_hdmi_build_controls,
2422 .unsol_event = hdmi_unsol_event,
2423#ifdef CONFIG_PM
2424 .resume = generic_hdmi_resume,
2425#endif
2426};
2427
2428static const struct hdmi_ops generic_standard_hdmi_ops = {
2429 .pin_get_eld = hdmi_pin_get_eld,
2430 .pin_setup_infoframe = hdmi_pin_setup_infoframe,
2431 .pin_hbr_setup = hdmi_pin_hbr_setup,
2432 .setup_stream = hdmi_setup_stream,
2433};
2434
2435/* allocate codec->spec and assign/initialize generic parser ops */
2436static int alloc_generic_hdmi(struct hda_codec *codec)
2437{
2438 struct hdmi_spec *spec;
2439
2440 spec = kzalloc(sizeof(*spec), GFP_KERNEL);
2441 if (!spec)
2442 return -ENOMEM;
2443
2444 spec->codec = codec;
2445 spec->ops = generic_standard_hdmi_ops;
2446 spec->dev_num = 1; /* initialize to 1 */
2447 mutex_init(&spec->pcm_lock);
2448 mutex_init(&spec->bind_lock);
2449 snd_hdac_register_chmap_ops(&codec->core, &spec->chmap);
2450
2451 spec->chmap.ops.get_chmap = hdmi_get_chmap;
2452 spec->chmap.ops.set_chmap = hdmi_set_chmap;
2453 spec->chmap.ops.is_pcm_attached = is_hdmi_pcm_attached;
2454 spec->chmap.ops.get_spk_alloc = hdmi_get_spk_alloc,
2455
2456 codec->spec = spec;
2457 hdmi_array_init(spec, 4);
2458
2459 codec->patch_ops = generic_hdmi_patch_ops;
2460
2461 return 0;
2462}
2463
2464/* generic HDMI parser */
2465static int patch_generic_hdmi(struct hda_codec *codec)
2466{
2467 int err;
2468
2469 err = alloc_generic_hdmi(codec);
2470 if (err < 0)
2471 return err;
2472
2473 err = hdmi_parse_codec(codec);
2474 if (err < 0) {
2475 generic_spec_free(codec);
2476 return err;
2477 }
2478
2479 generic_hdmi_init_per_pins(codec);
2480 return 0;
2481}
2482
2483/*
2484 * generic audio component binding
2485 */
2486
2487/* turn on / off the unsol event jack detection dynamically */
2488static void reprogram_jack_detect(struct hda_codec *codec, hda_nid_t nid,
2489 int dev_id, bool use_acomp)
2490{
2491 struct hda_jack_tbl *tbl;
2492
2493 tbl = snd_hda_jack_tbl_get_mst(codec, nid, dev_id);
2494 if (tbl) {
2495 /* clear unsol even if component notifier is used, or re-enable
2496 * if notifier is cleared
2497 */
2498 unsigned int val = use_acomp ? 0 : (AC_USRSP_EN | tbl->tag);
2499 snd_hda_codec_write_cache(codec, nid, 0,
2500 AC_VERB_SET_UNSOLICITED_ENABLE, val);
2501 }
2502}
2503
2504/* set up / clear component notifier dynamically */
2505static void generic_acomp_notifier_set(struct drm_audio_component *acomp,
2506 bool use_acomp)
2507{
2508 struct hdmi_spec *spec;
2509 int i;
2510
2511 spec = container_of(acomp->audio_ops, struct hdmi_spec, drm_audio_ops);
2512 mutex_lock(&spec->bind_lock);
2513 spec->use_acomp_notifier = use_acomp;
2514 spec->codec->relaxed_resume = use_acomp;
2515 spec->codec->bus->keep_power = 0;
2516 /* reprogram each jack detection logic depending on the notifier */
2517 for (i = 0; i < spec->num_pins; i++)
2518 reprogram_jack_detect(spec->codec,
2519 get_pin(spec, i)->pin_nid,
2520 get_pin(spec, i)->dev_id,
2521 use_acomp);
2522 mutex_unlock(&spec->bind_lock);
2523}
2524
2525/* enable / disable the notifier via master bind / unbind */
2526static int generic_acomp_master_bind(struct device *dev,
2527 struct drm_audio_component *acomp)
2528{
2529 generic_acomp_notifier_set(acomp, true);
2530 return 0;
2531}
2532
2533static void generic_acomp_master_unbind(struct device *dev,
2534 struct drm_audio_component *acomp)
2535{
2536 generic_acomp_notifier_set(acomp, false);
2537}
2538
2539/* check whether both HD-audio and DRM PCI devices belong to the same bus */
2540static int match_bound_vga(struct device *dev, int subtype, void *data)
2541{
2542 struct hdac_bus *bus = data;
2543 struct pci_dev *pci, *master;
2544
2545 if (!dev_is_pci(dev) || !dev_is_pci(bus->dev))
2546 return 0;
2547 master = to_pci_dev(bus->dev);
2548 pci = to_pci_dev(dev);
2549 return master->bus == pci->bus;
2550}
2551
2552/* audio component notifier for AMD/Nvidia HDMI codecs */
2553static void generic_acomp_pin_eld_notify(void *audio_ptr, int port, int dev_id)
2554{
2555 struct hda_codec *codec = audio_ptr;
2556 struct hdmi_spec *spec = codec->spec;
2557 hda_nid_t pin_nid = spec->port2pin(codec, port);
2558
2559 if (!pin_nid)
2560 return;
2561 if (get_wcaps_type(get_wcaps(codec, pin_nid)) != AC_WID_PIN)
2562 return;
2563 /* skip notification during system suspend (but not in runtime PM);
2564 * the state will be updated at resume
2565 */
2566 if (snd_power_get_state(codec->card) != SNDRV_CTL_POWER_D0)
2567 return;
2568 /* ditto during suspend/resume process itself */
2569 if (snd_hdac_is_in_pm(&codec->core))
2570 return;
2571
2572 check_presence_and_report(codec, pin_nid, dev_id);
2573}
2574
2575/* set up the private drm_audio_ops from the template */
2576static void setup_drm_audio_ops(struct hda_codec *codec,
2577 const struct drm_audio_component_audio_ops *ops)
2578{
2579 struct hdmi_spec *spec = codec->spec;
2580
2581 spec->drm_audio_ops.audio_ptr = codec;
2582 /* intel_audio_codec_enable() or intel_audio_codec_disable()
2583 * will call pin_eld_notify with using audio_ptr pointer
2584 * We need make sure audio_ptr is really setup
2585 */
2586 wmb();
2587 spec->drm_audio_ops.pin2port = ops->pin2port;
2588 spec->drm_audio_ops.pin_eld_notify = ops->pin_eld_notify;
2589 spec->drm_audio_ops.master_bind = ops->master_bind;
2590 spec->drm_audio_ops.master_unbind = ops->master_unbind;
2591}
2592
2593/* initialize the generic HDMI audio component */
2594static void generic_acomp_init(struct hda_codec *codec,
2595 const struct drm_audio_component_audio_ops *ops,
2596 int (*port2pin)(struct hda_codec *, int))
2597{
2598 struct hdmi_spec *spec = codec->spec;
2599
2600 if (!enable_acomp) {
2601 codec_info(codec, "audio component disabled by module option\n");
2602 return;
2603 }
2604
2605 spec->port2pin = port2pin;
2606 setup_drm_audio_ops(codec, ops);
2607 if (!snd_hdac_acomp_init(&codec->bus->core, &spec->drm_audio_ops,
2608 match_bound_vga, 0)) {
2609 spec->acomp_registered = true;
2610 }
2611}
2612
2613/*
2614 * Intel codec parsers and helpers
2615 */
2616
2617#define INTEL_GET_VENDOR_VERB 0xf81
2618#define INTEL_SET_VENDOR_VERB 0x781
2619#define INTEL_EN_DP12 0x02 /* enable DP 1.2 features */
2620#define INTEL_EN_ALL_PIN_CVTS 0x01 /* enable 2nd & 3rd pins and convertors */
2621
2622static void intel_haswell_enable_all_pins(struct hda_codec *codec,
2623 bool update_tree)
2624{
2625 unsigned int vendor_param;
2626 struct hdmi_spec *spec = codec->spec;
2627
2628 vendor_param = snd_hda_codec_read(codec, spec->vendor_nid, 0,
2629 INTEL_GET_VENDOR_VERB, 0);
2630 if (vendor_param == -1 || vendor_param & INTEL_EN_ALL_PIN_CVTS)
2631 return;
2632
2633 vendor_param |= INTEL_EN_ALL_PIN_CVTS;
2634 vendor_param = snd_hda_codec_read(codec, spec->vendor_nid, 0,
2635 INTEL_SET_VENDOR_VERB, vendor_param);
2636 if (vendor_param == -1)
2637 return;
2638
2639 if (update_tree)
2640 snd_hda_codec_update_widgets(codec);
2641}
2642
2643static void intel_haswell_fixup_enable_dp12(struct hda_codec *codec)
2644{
2645 unsigned int vendor_param;
2646 struct hdmi_spec *spec = codec->spec;
2647
2648 vendor_param = snd_hda_codec_read(codec, spec->vendor_nid, 0,
2649 INTEL_GET_VENDOR_VERB, 0);
2650 if (vendor_param == -1 || vendor_param & INTEL_EN_DP12)
2651 return;
2652
2653 /* enable DP1.2 mode */
2654 vendor_param |= INTEL_EN_DP12;
2655 snd_hdac_regmap_add_vendor_verb(&codec->core, INTEL_SET_VENDOR_VERB);
2656 snd_hda_codec_write_cache(codec, spec->vendor_nid, 0,
2657 INTEL_SET_VENDOR_VERB, vendor_param);
2658}
2659
2660/* Haswell needs to re-issue the vendor-specific verbs before turning to D0.
2661 * Otherwise you may get severe h/w communication errors.
2662 */
2663static void haswell_set_power_state(struct hda_codec *codec, hda_nid_t fg,
2664 unsigned int power_state)
2665{
2666 if (power_state == AC_PWRST_D0) {
2667 intel_haswell_enable_all_pins(codec, false);
2668 intel_haswell_fixup_enable_dp12(codec);
2669 }
2670
2671 snd_hda_codec_read(codec, fg, 0, AC_VERB_SET_POWER_STATE, power_state);
2672 snd_hda_codec_set_power_to_all(codec, fg, power_state);
2673}
2674
2675/* There is a fixed mapping between audio pin node and display port.
2676 * on SNB, IVY, HSW, BSW, SKL, BXT, KBL:
2677 * Pin Widget 5 - PORT B (port = 1 in i915 driver)
2678 * Pin Widget 6 - PORT C (port = 2 in i915 driver)
2679 * Pin Widget 7 - PORT D (port = 3 in i915 driver)
2680 *
2681 * on VLV, ILK:
2682 * Pin Widget 4 - PORT B (port = 1 in i915 driver)
2683 * Pin Widget 5 - PORT C (port = 2 in i915 driver)
2684 * Pin Widget 6 - PORT D (port = 3 in i915 driver)
2685 */
2686static int intel_base_nid(struct hda_codec *codec)
2687{
2688 switch (codec->core.vendor_id) {
2689 case 0x80860054: /* ILK */
2690 case 0x80862804: /* ILK */
2691 case 0x80862882: /* VLV */
2692 return 4;
2693 default:
2694 return 5;
2695 }
2696}
2697
2698static int intel_pin2port(void *audio_ptr, int pin_nid)
2699{
2700 struct hda_codec *codec = audio_ptr;
2701 struct hdmi_spec *spec = codec->spec;
2702 int base_nid, i;
2703
2704 if (!spec->port_num) {
2705 base_nid = intel_base_nid(codec);
2706 if (WARN_ON(pin_nid < base_nid || pin_nid >= base_nid + 3))
2707 return -1;
2708 return pin_nid - base_nid + 1;
2709 }
2710
2711 /*
2712 * looking for the pin number in the mapping table and return
2713 * the index which indicate the port number
2714 */
2715 for (i = 0; i < spec->port_num; i++) {
2716 if (pin_nid == spec->port_map[i])
2717 return i;
2718 }
2719
2720 codec_info(codec, "Can't find the HDMI/DP port for pin %d\n", pin_nid);
2721 return -1;
2722}
2723
2724static int intel_port2pin(struct hda_codec *codec, int port)
2725{
2726 struct hdmi_spec *spec = codec->spec;
2727
2728 if (!spec->port_num) {
2729 /* we assume only from port-B to port-D */
2730 if (port < 1 || port > 3)
2731 return 0;
2732 return port + intel_base_nid(codec) - 1;
2733 }
2734
2735 if (port < 0 || port >= spec->port_num)
2736 return 0;
2737 return spec->port_map[port];
2738}
2739
2740static void intel_pin_eld_notify(void *audio_ptr, int port, int pipe)
2741{
2742 struct hda_codec *codec = audio_ptr;
2743 int pin_nid;
2744 int dev_id = pipe;
2745
2746 pin_nid = intel_port2pin(codec, port);
2747 if (!pin_nid)
2748 return;
2749 /* skip notification during system suspend (but not in runtime PM);
2750 * the state will be updated at resume
2751 */
2752 if (snd_power_get_state(codec->card) != SNDRV_CTL_POWER_D0)
2753 return;
2754 /* ditto during suspend/resume process itself */
2755 if (snd_hdac_is_in_pm(&codec->core))
2756 return;
2757
2758 snd_hdac_i915_set_bclk(&codec->bus->core);
2759 check_presence_and_report(codec, pin_nid, dev_id);
2760}
2761
2762static const struct drm_audio_component_audio_ops intel_audio_ops = {
2763 .pin2port = intel_pin2port,
2764 .pin_eld_notify = intel_pin_eld_notify,
2765};
2766
2767/* register i915 component pin_eld_notify callback */
2768static void register_i915_notifier(struct hda_codec *codec)
2769{
2770 struct hdmi_spec *spec = codec->spec;
2771
2772 spec->use_acomp_notifier = true;
2773 spec->port2pin = intel_port2pin;
2774 setup_drm_audio_ops(codec, &intel_audio_ops);
2775 snd_hdac_acomp_register_notifier(&codec->bus->core,
2776 &spec->drm_audio_ops);
2777 /* no need for forcible resume for jack check thanks to notifier */
2778 codec->relaxed_resume = 1;
2779}
2780
2781/* setup_stream ops override for HSW+ */
2782static int i915_hsw_setup_stream(struct hda_codec *codec, hda_nid_t cvt_nid,
2783 hda_nid_t pin_nid, int dev_id, u32 stream_tag,
2784 int format)
2785{
2786 haswell_verify_D0(codec, cvt_nid, pin_nid);
2787 return hdmi_setup_stream(codec, cvt_nid, pin_nid, dev_id,
2788 stream_tag, format);
2789}
2790
2791/* pin_cvt_fixup ops override for HSW+ and VLV+ */
2792static void i915_pin_cvt_fixup(struct hda_codec *codec,
2793 struct hdmi_spec_per_pin *per_pin,
2794 hda_nid_t cvt_nid)
2795{
2796 if (per_pin) {
2797 haswell_verify_D0(codec, per_pin->cvt_nid, per_pin->pin_nid);
2798 snd_hda_set_dev_select(codec, per_pin->pin_nid,
2799 per_pin->dev_id);
2800 intel_verify_pin_cvt_connect(codec, per_pin);
2801 intel_not_share_assigned_cvt(codec, per_pin->pin_nid,
2802 per_pin->dev_id, per_pin->mux_idx);
2803 } else {
2804 intel_not_share_assigned_cvt_nid(codec, 0, 0, cvt_nid);
2805 }
2806}
2807
2808/* precondition and allocation for Intel codecs */
2809static int alloc_intel_hdmi(struct hda_codec *codec)
2810{
2811 int err;
2812
2813 /* requires i915 binding */
2814 if (!codec->bus->core.audio_component) {
2815 codec_info(codec, "No i915 binding for Intel HDMI/DP codec\n");
2816 /* set probe_id here to prevent generic fallback binding */
2817 codec->probe_id = HDA_CODEC_ID_SKIP_PROBE;
2818 return -ENODEV;
2819 }
2820
2821 err = alloc_generic_hdmi(codec);
2822 if (err < 0)
2823 return err;
2824 /* no need to handle unsol events */
2825 codec->patch_ops.unsol_event = NULL;
2826 return 0;
2827}
2828
2829/* parse and post-process for Intel codecs */
2830static int parse_intel_hdmi(struct hda_codec *codec)
2831{
2832 int err, retries = 3;
2833
2834 do {
2835 err = hdmi_parse_codec(codec);
2836 } while (err < 0 && retries--);
2837
2838 if (err < 0) {
2839 generic_spec_free(codec);
2840 return err;
2841 }
2842
2843 generic_hdmi_init_per_pins(codec);
2844 register_i915_notifier(codec);
2845 return 0;
2846}
2847
2848/* Intel Haswell and onwards; audio component with eld notifier */
2849static int intel_hsw_common_init(struct hda_codec *codec, hda_nid_t vendor_nid,
2850 const int *port_map, int port_num)
2851{
2852 struct hdmi_spec *spec;
2853 int err;
2854
2855 err = alloc_intel_hdmi(codec);
2856 if (err < 0)
2857 return err;
2858 spec = codec->spec;
2859 codec->dp_mst = true;
2860 spec->dyn_pcm_assign = true;
2861 spec->vendor_nid = vendor_nid;
2862 spec->port_map = port_map;
2863 spec->port_num = port_num;
2864 spec->intel_hsw_fixup = true;
2865
2866 intel_haswell_enable_all_pins(codec, true);
2867 intel_haswell_fixup_enable_dp12(codec);
2868
2869 codec->display_power_control = 1;
2870
2871 codec->patch_ops.set_power_state = haswell_set_power_state;
2872 codec->depop_delay = 0;
2873 codec->auto_runtime_pm = 1;
2874
2875 spec->ops.setup_stream = i915_hsw_setup_stream;
2876 spec->ops.pin_cvt_fixup = i915_pin_cvt_fixup;
2877
2878 /*
2879 * Enable silent stream feature, if it is enabled via
2880 * module param or Kconfig option
2881 */
2882 if (enable_silent_stream)
2883 spec->send_silent_stream = true;
2884
2885 return parse_intel_hdmi(codec);
2886}
2887
2888static int patch_i915_hsw_hdmi(struct hda_codec *codec)
2889{
2890 return intel_hsw_common_init(codec, 0x08, NULL, 0);
2891}
2892
2893static int patch_i915_glk_hdmi(struct hda_codec *codec)
2894{
2895 return intel_hsw_common_init(codec, 0x0b, NULL, 0);
2896}
2897
2898static int patch_i915_icl_hdmi(struct hda_codec *codec)
2899{
2900 /*
2901 * pin to port mapping table where the value indicate the pin number and
2902 * the index indicate the port number.
2903 */
2904 static const int map[] = {0x0, 0x4, 0x6, 0x8, 0xa, 0xb};
2905
2906 return intel_hsw_common_init(codec, 0x02, map, ARRAY_SIZE(map));
2907}
2908
2909static int patch_i915_tgl_hdmi(struct hda_codec *codec)
2910{
2911 /*
2912 * pin to port mapping table where the value indicate the pin number and
2913 * the index indicate the port number.
2914 */
2915 static const int map[] = {0x4, 0x6, 0x8, 0xa, 0xb, 0xc, 0xd, 0xe, 0xf};
2916
2917 return intel_hsw_common_init(codec, 0x02, map, ARRAY_SIZE(map));
2918}
2919
2920/* Intel Baytrail and Braswell; with eld notifier */
2921static int patch_i915_byt_hdmi(struct hda_codec *codec)
2922{
2923 struct hdmi_spec *spec;
2924 int err;
2925
2926 err = alloc_intel_hdmi(codec);
2927 if (err < 0)
2928 return err;
2929 spec = codec->spec;
2930
2931 /* For Valleyview/Cherryview, only the display codec is in the display
2932 * power well and can use link_power ops to request/release the power.
2933 */
2934 codec->display_power_control = 1;
2935
2936 codec->depop_delay = 0;
2937 codec->auto_runtime_pm = 1;
2938
2939 spec->ops.pin_cvt_fixup = i915_pin_cvt_fixup;
2940
2941 return parse_intel_hdmi(codec);
2942}
2943
2944/* Intel IronLake, SandyBridge and IvyBridge; with eld notifier */
2945static int patch_i915_cpt_hdmi(struct hda_codec *codec)
2946{
2947 int err;
2948
2949 err = alloc_intel_hdmi(codec);
2950 if (err < 0)
2951 return err;
2952 return parse_intel_hdmi(codec);
2953}
2954
2955/*
2956 * Shared non-generic implementations
2957 */
2958
2959static int simple_playback_build_pcms(struct hda_codec *codec)
2960{
2961 struct hdmi_spec *spec = codec->spec;
2962 struct hda_pcm *info;
2963 unsigned int chans;
2964 struct hda_pcm_stream *pstr;
2965 struct hdmi_spec_per_cvt *per_cvt;
2966
2967 per_cvt = get_cvt(spec, 0);
2968 chans = get_wcaps(codec, per_cvt->cvt_nid);
2969 chans = get_wcaps_channels(chans);
2970
2971 info = snd_hda_codec_pcm_new(codec, "HDMI 0");
2972 if (!info)
2973 return -ENOMEM;
2974 spec->pcm_rec[0].pcm = info;
2975 info->pcm_type = HDA_PCM_TYPE_HDMI;
2976 pstr = &info->stream[SNDRV_PCM_STREAM_PLAYBACK];
2977 *pstr = spec->pcm_playback;
2978 pstr->nid = per_cvt->cvt_nid;
2979 if (pstr->channels_max <= 2 && chans && chans <= 16)
2980 pstr->channels_max = chans;
2981
2982 return 0;
2983}
2984
2985/* unsolicited event for jack sensing */
2986static void simple_hdmi_unsol_event(struct hda_codec *codec,
2987 unsigned int res)
2988{
2989 snd_hda_jack_set_dirty_all(codec);
2990 snd_hda_jack_report_sync(codec);
2991}
2992
2993/* generic_hdmi_build_jack can be used for simple_hdmi, too,
2994 * as long as spec->pins[] is set correctly
2995 */
2996#define simple_hdmi_build_jack generic_hdmi_build_jack
2997
2998static int simple_playback_build_controls(struct hda_codec *codec)
2999{
3000 struct hdmi_spec *spec = codec->spec;
3001 struct hdmi_spec_per_cvt *per_cvt;
3002 int err;
3003
3004 per_cvt = get_cvt(spec, 0);
3005 err = snd_hda_create_dig_out_ctls(codec, per_cvt->cvt_nid,
3006 per_cvt->cvt_nid,
3007 HDA_PCM_TYPE_HDMI);
3008 if (err < 0)
3009 return err;
3010 return simple_hdmi_build_jack(codec, 0);
3011}
3012
3013static int simple_playback_init(struct hda_codec *codec)
3014{
3015 struct hdmi_spec *spec = codec->spec;
3016 struct hdmi_spec_per_pin *per_pin = get_pin(spec, 0);
3017 hda_nid_t pin = per_pin->pin_nid;
3018
3019 snd_hda_codec_write(codec, pin, 0,
3020 AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT);
3021 /* some codecs require to unmute the pin */
3022 if (get_wcaps(codec, pin) & AC_WCAP_OUT_AMP)
3023 snd_hda_codec_write(codec, pin, 0, AC_VERB_SET_AMP_GAIN_MUTE,
3024 AMP_OUT_UNMUTE);
3025 snd_hda_jack_detect_enable(codec, pin, per_pin->dev_id);
3026 return 0;
3027}
3028
3029static void simple_playback_free(struct hda_codec *codec)
3030{
3031 struct hdmi_spec *spec = codec->spec;
3032
3033 hdmi_array_free(spec);
3034 kfree(spec);
3035}
3036
3037/*
3038 * Nvidia specific implementations
3039 */
3040
3041#define Nv_VERB_SET_Channel_Allocation 0xF79
3042#define Nv_VERB_SET_Info_Frame_Checksum 0xF7A
3043#define Nv_VERB_SET_Audio_Protection_On 0xF98
3044#define Nv_VERB_SET_Audio_Protection_Off 0xF99
3045
3046#define nvhdmi_master_con_nid_7x 0x04
3047#define nvhdmi_master_pin_nid_7x 0x05
3048
3049static const hda_nid_t nvhdmi_con_nids_7x[4] = {
3050 /*front, rear, clfe, rear_surr */
3051 0x6, 0x8, 0xa, 0xc,
3052};
3053
3054static const struct hda_verb nvhdmi_basic_init_7x_2ch[] = {
3055 /* set audio protect on */
3056 { 0x1, Nv_VERB_SET_Audio_Protection_On, 0x1},
3057 /* enable digital output on pin widget */
3058 { 0x5, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
3059 {} /* terminator */
3060};
3061
3062static const struct hda_verb nvhdmi_basic_init_7x_8ch[] = {
3063 /* set audio protect on */
3064 { 0x1, Nv_VERB_SET_Audio_Protection_On, 0x1},
3065 /* enable digital output on pin widget */
3066 { 0x5, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
3067 { 0x7, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
3068 { 0x9, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
3069 { 0xb, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
3070 { 0xd, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
3071 {} /* terminator */
3072};
3073
3074#ifdef LIMITED_RATE_FMT_SUPPORT
3075/* support only the safe format and rate */
3076#define SUPPORTED_RATES SNDRV_PCM_RATE_48000
3077#define SUPPORTED_MAXBPS 16
3078#define SUPPORTED_FORMATS SNDRV_PCM_FMTBIT_S16_LE
3079#else
3080/* support all rates and formats */
3081#define SUPPORTED_RATES \
3082 (SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000 |\
3083 SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |\
3084 SNDRV_PCM_RATE_192000)
3085#define SUPPORTED_MAXBPS 24
3086#define SUPPORTED_FORMATS \
3087 (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE)
3088#endif
3089
3090static int nvhdmi_7x_init_2ch(struct hda_codec *codec)
3091{
3092 snd_hda_sequence_write(codec, nvhdmi_basic_init_7x_2ch);
3093 return 0;
3094}
3095
3096static int nvhdmi_7x_init_8ch(struct hda_codec *codec)
3097{
3098 snd_hda_sequence_write(codec, nvhdmi_basic_init_7x_8ch);
3099 return 0;
3100}
3101
3102static const unsigned int channels_2_6_8[] = {
3103 2, 6, 8
3104};
3105
3106static const unsigned int channels_2_8[] = {
3107 2, 8
3108};
3109
3110static const struct snd_pcm_hw_constraint_list hw_constraints_2_6_8_channels = {
3111 .count = ARRAY_SIZE(channels_2_6_8),
3112 .list = channels_2_6_8,
3113 .mask = 0,
3114};
3115
3116static const struct snd_pcm_hw_constraint_list hw_constraints_2_8_channels = {
3117 .count = ARRAY_SIZE(channels_2_8),
3118 .list = channels_2_8,
3119 .mask = 0,
3120};
3121
3122static int simple_playback_pcm_open(struct hda_pcm_stream *hinfo,
3123 struct hda_codec *codec,
3124 struct snd_pcm_substream *substream)
3125{
3126 struct hdmi_spec *spec = codec->spec;
3127 const struct snd_pcm_hw_constraint_list *hw_constraints_channels = NULL;
3128
3129 switch (codec->preset->vendor_id) {
3130 case 0x10de0002:
3131 case 0x10de0003:
3132 case 0x10de0005:
3133 case 0x10de0006:
3134 hw_constraints_channels = &hw_constraints_2_8_channels;
3135 break;
3136 case 0x10de0007:
3137 hw_constraints_channels = &hw_constraints_2_6_8_channels;
3138 break;
3139 default:
3140 break;
3141 }
3142
3143 if (hw_constraints_channels != NULL) {
3144 snd_pcm_hw_constraint_list(substream->runtime, 0,
3145 SNDRV_PCM_HW_PARAM_CHANNELS,
3146 hw_constraints_channels);
3147 } else {
3148 snd_pcm_hw_constraint_step(substream->runtime, 0,
3149 SNDRV_PCM_HW_PARAM_CHANNELS, 2);
3150 }
3151
3152 return snd_hda_multi_out_dig_open(codec, &spec->multiout);
3153}
3154
3155static int simple_playback_pcm_close(struct hda_pcm_stream *hinfo,
3156 struct hda_codec *codec,
3157 struct snd_pcm_substream *substream)
3158{
3159 struct hdmi_spec *spec = codec->spec;
3160 return snd_hda_multi_out_dig_close(codec, &spec->multiout);
3161}
3162
3163static int simple_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
3164 struct hda_codec *codec,
3165 unsigned int stream_tag,
3166 unsigned int format,
3167 struct snd_pcm_substream *substream)
3168{
3169 struct hdmi_spec *spec = codec->spec;
3170 return snd_hda_multi_out_dig_prepare(codec, &spec->multiout,
3171 stream_tag, format, substream);
3172}
3173
3174static const struct hda_pcm_stream simple_pcm_playback = {
3175 .substreams = 1,
3176 .channels_min = 2,
3177 .channels_max = 2,
3178 .ops = {
3179 .open = simple_playback_pcm_open,
3180 .close = simple_playback_pcm_close,
3181 .prepare = simple_playback_pcm_prepare
3182 },
3183};
3184
3185static const struct hda_codec_ops simple_hdmi_patch_ops = {
3186 .build_controls = simple_playback_build_controls,
3187 .build_pcms = simple_playback_build_pcms,
3188 .init = simple_playback_init,
3189 .free = simple_playback_free,
3190 .unsol_event = simple_hdmi_unsol_event,
3191};
3192
3193static int patch_simple_hdmi(struct hda_codec *codec,
3194 hda_nid_t cvt_nid, hda_nid_t pin_nid)
3195{
3196 struct hdmi_spec *spec;
3197 struct hdmi_spec_per_cvt *per_cvt;
3198 struct hdmi_spec_per_pin *per_pin;
3199
3200 spec = kzalloc(sizeof(*spec), GFP_KERNEL);
3201 if (!spec)
3202 return -ENOMEM;
3203
3204 spec->codec = codec;
3205 codec->spec = spec;
3206 hdmi_array_init(spec, 1);
3207
3208 spec->multiout.num_dacs = 0; /* no analog */
3209 spec->multiout.max_channels = 2;
3210 spec->multiout.dig_out_nid = cvt_nid;
3211 spec->num_cvts = 1;
3212 spec->num_pins = 1;
3213 per_pin = snd_array_new(&spec->pins);
3214 per_cvt = snd_array_new(&spec->cvts);
3215 if (!per_pin || !per_cvt) {
3216 simple_playback_free(codec);
3217 return -ENOMEM;
3218 }
3219 per_cvt->cvt_nid = cvt_nid;
3220 per_pin->pin_nid = pin_nid;
3221 spec->pcm_playback = simple_pcm_playback;
3222
3223 codec->patch_ops = simple_hdmi_patch_ops;
3224
3225 return 0;
3226}
3227
3228static void nvhdmi_8ch_7x_set_info_frame_parameters(struct hda_codec *codec,
3229 int channels)
3230{
3231 unsigned int chanmask;
3232 int chan = channels ? (channels - 1) : 1;
3233
3234 switch (channels) {
3235 default:
3236 case 0:
3237 case 2:
3238 chanmask = 0x00;
3239 break;
3240 case 4:
3241 chanmask = 0x08;
3242 break;
3243 case 6:
3244 chanmask = 0x0b;
3245 break;
3246 case 8:
3247 chanmask = 0x13;
3248 break;
3249 }
3250
3251 /* Set the audio infoframe channel allocation and checksum fields. The
3252 * channel count is computed implicitly by the hardware. */
3253 snd_hda_codec_write(codec, 0x1, 0,
3254 Nv_VERB_SET_Channel_Allocation, chanmask);
3255
3256 snd_hda_codec_write(codec, 0x1, 0,
3257 Nv_VERB_SET_Info_Frame_Checksum,
3258 (0x71 - chan - chanmask));
3259}
3260
3261static int nvhdmi_8ch_7x_pcm_close(struct hda_pcm_stream *hinfo,
3262 struct hda_codec *codec,
3263 struct snd_pcm_substream *substream)
3264{
3265 struct hdmi_spec *spec = codec->spec;
3266 int i;
3267
3268 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x,
3269 0, AC_VERB_SET_CHANNEL_STREAMID, 0);
3270 for (i = 0; i < 4; i++) {
3271 /* set the stream id */
3272 snd_hda_codec_write(codec, nvhdmi_con_nids_7x[i], 0,
3273 AC_VERB_SET_CHANNEL_STREAMID, 0);
3274 /* set the stream format */
3275 snd_hda_codec_write(codec, nvhdmi_con_nids_7x[i], 0,
3276 AC_VERB_SET_STREAM_FORMAT, 0);
3277 }
3278
3279 /* The audio hardware sends a channel count of 0x7 (8ch) when all the
3280 * streams are disabled. */
3281 nvhdmi_8ch_7x_set_info_frame_parameters(codec, 8);
3282
3283 return snd_hda_multi_out_dig_close(codec, &spec->multiout);
3284}
3285
3286static int nvhdmi_8ch_7x_pcm_prepare(struct hda_pcm_stream *hinfo,
3287 struct hda_codec *codec,
3288 unsigned int stream_tag,
3289 unsigned int format,
3290 struct snd_pcm_substream *substream)
3291{
3292 int chs;
3293 unsigned int dataDCC2, channel_id;
3294 int i;
3295 struct hdmi_spec *spec = codec->spec;
3296 struct hda_spdif_out *spdif;
3297 struct hdmi_spec_per_cvt *per_cvt;
3298
3299 mutex_lock(&codec->spdif_mutex);
3300 per_cvt = get_cvt(spec, 0);
3301 spdif = snd_hda_spdif_out_of_nid(codec, per_cvt->cvt_nid);
3302
3303 chs = substream->runtime->channels;
3304
3305 dataDCC2 = 0x2;
3306
3307 /* turn off SPDIF once; otherwise the IEC958 bits won't be updated */
3308 if (codec->spdif_status_reset && (spdif->ctls & AC_DIG1_ENABLE))
3309 snd_hda_codec_write(codec,
3310 nvhdmi_master_con_nid_7x,
3311 0,
3312 AC_VERB_SET_DIGI_CONVERT_1,
3313 spdif->ctls & ~AC_DIG1_ENABLE & 0xff);
3314
3315 /* set the stream id */
3316 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, 0,
3317 AC_VERB_SET_CHANNEL_STREAMID, (stream_tag << 4) | 0x0);
3318
3319 /* set the stream format */
3320 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, 0,
3321 AC_VERB_SET_STREAM_FORMAT, format);
3322
3323 /* turn on again (if needed) */
3324 /* enable and set the channel status audio/data flag */
3325 if (codec->spdif_status_reset && (spdif->ctls & AC_DIG1_ENABLE)) {
3326 snd_hda_codec_write(codec,
3327 nvhdmi_master_con_nid_7x,
3328 0,
3329 AC_VERB_SET_DIGI_CONVERT_1,
3330 spdif->ctls & 0xff);
3331 snd_hda_codec_write(codec,
3332 nvhdmi_master_con_nid_7x,
3333 0,
3334 AC_VERB_SET_DIGI_CONVERT_2, dataDCC2);
3335 }
3336
3337 for (i = 0; i < 4; i++) {
3338 if (chs == 2)
3339 channel_id = 0;
3340 else
3341 channel_id = i * 2;
3342
3343 /* turn off SPDIF once;
3344 *otherwise the IEC958 bits won't be updated
3345 */
3346 if (codec->spdif_status_reset &&
3347 (spdif->ctls & AC_DIG1_ENABLE))
3348 snd_hda_codec_write(codec,
3349 nvhdmi_con_nids_7x[i],
3350 0,
3351 AC_VERB_SET_DIGI_CONVERT_1,
3352 spdif->ctls & ~AC_DIG1_ENABLE & 0xff);
3353 /* set the stream id */
3354 snd_hda_codec_write(codec,
3355 nvhdmi_con_nids_7x[i],
3356 0,
3357 AC_VERB_SET_CHANNEL_STREAMID,
3358 (stream_tag << 4) | channel_id);
3359 /* set the stream format */
3360 snd_hda_codec_write(codec,
3361 nvhdmi_con_nids_7x[i],
3362 0,
3363 AC_VERB_SET_STREAM_FORMAT,
3364 format);
3365 /* turn on again (if needed) */
3366 /* enable and set the channel status audio/data flag */
3367 if (codec->spdif_status_reset &&
3368 (spdif->ctls & AC_DIG1_ENABLE)) {
3369 snd_hda_codec_write(codec,
3370 nvhdmi_con_nids_7x[i],
3371 0,
3372 AC_VERB_SET_DIGI_CONVERT_1,
3373 spdif->ctls & 0xff);
3374 snd_hda_codec_write(codec,
3375 nvhdmi_con_nids_7x[i],
3376 0,
3377 AC_VERB_SET_DIGI_CONVERT_2, dataDCC2);
3378 }
3379 }
3380
3381 nvhdmi_8ch_7x_set_info_frame_parameters(codec, chs);
3382
3383 mutex_unlock(&codec->spdif_mutex);
3384 return 0;
3385}
3386
3387static const struct hda_pcm_stream nvhdmi_pcm_playback_8ch_7x = {
3388 .substreams = 1,
3389 .channels_min = 2,
3390 .channels_max = 8,
3391 .nid = nvhdmi_master_con_nid_7x,
3392 .rates = SUPPORTED_RATES,
3393 .maxbps = SUPPORTED_MAXBPS,
3394 .formats = SUPPORTED_FORMATS,
3395 .ops = {
3396 .open = simple_playback_pcm_open,
3397 .close = nvhdmi_8ch_7x_pcm_close,
3398 .prepare = nvhdmi_8ch_7x_pcm_prepare
3399 },
3400};
3401
3402static int patch_nvhdmi_2ch(struct hda_codec *codec)
3403{
3404 struct hdmi_spec *spec;
3405 int err = patch_simple_hdmi(codec, nvhdmi_master_con_nid_7x,
3406 nvhdmi_master_pin_nid_7x);
3407 if (err < 0)
3408 return err;
3409
3410 codec->patch_ops.init = nvhdmi_7x_init_2ch;
3411 /* override the PCM rates, etc, as the codec doesn't give full list */
3412 spec = codec->spec;
3413 spec->pcm_playback.rates = SUPPORTED_RATES;
3414 spec->pcm_playback.maxbps = SUPPORTED_MAXBPS;
3415 spec->pcm_playback.formats = SUPPORTED_FORMATS;
3416 return 0;
3417}
3418
3419static int nvhdmi_7x_8ch_build_pcms(struct hda_codec *codec)
3420{
3421 struct hdmi_spec *spec = codec->spec;
3422 int err = simple_playback_build_pcms(codec);
3423 if (!err) {
3424 struct hda_pcm *info = get_pcm_rec(spec, 0);
3425 info->own_chmap = true;
3426 }
3427 return err;
3428}
3429
3430static int nvhdmi_7x_8ch_build_controls(struct hda_codec *codec)
3431{
3432 struct hdmi_spec *spec = codec->spec;
3433 struct hda_pcm *info;
3434 struct snd_pcm_chmap *chmap;
3435 int err;
3436
3437 err = simple_playback_build_controls(codec);
3438 if (err < 0)
3439 return err;
3440
3441 /* add channel maps */
3442 info = get_pcm_rec(spec, 0);
3443 err = snd_pcm_add_chmap_ctls(info->pcm,
3444 SNDRV_PCM_STREAM_PLAYBACK,
3445 snd_pcm_alt_chmaps, 8, 0, &chmap);
3446 if (err < 0)
3447 return err;
3448 switch (codec->preset->vendor_id) {
3449 case 0x10de0002:
3450 case 0x10de0003:
3451 case 0x10de0005:
3452 case 0x10de0006:
3453 chmap->channel_mask = (1U << 2) | (1U << 8);
3454 break;
3455 case 0x10de0007:
3456 chmap->channel_mask = (1U << 2) | (1U << 6) | (1U << 8);
3457 }
3458 return 0;
3459}
3460
3461static int patch_nvhdmi_8ch_7x(struct hda_codec *codec)
3462{
3463 struct hdmi_spec *spec;
3464 int err = patch_nvhdmi_2ch(codec);
3465 if (err < 0)
3466 return err;
3467 spec = codec->spec;
3468 spec->multiout.max_channels = 8;
3469 spec->pcm_playback = nvhdmi_pcm_playback_8ch_7x;
3470 codec->patch_ops.init = nvhdmi_7x_init_8ch;
3471 codec->patch_ops.build_pcms = nvhdmi_7x_8ch_build_pcms;
3472 codec->patch_ops.build_controls = nvhdmi_7x_8ch_build_controls;
3473
3474 /* Initialize the audio infoframe channel mask and checksum to something
3475 * valid */
3476 nvhdmi_8ch_7x_set_info_frame_parameters(codec, 8);
3477
3478 return 0;
3479}
3480
3481/*
3482 * NVIDIA codecs ignore ASP mapping for 2ch - confirmed on:
3483 * - 0x10de0015
3484 * - 0x10de0040
3485 */
3486static int nvhdmi_chmap_cea_alloc_validate_get_type(struct hdac_chmap *chmap,
3487 struct hdac_cea_channel_speaker_allocation *cap, int channels)
3488{
3489 if (cap->ca_index == 0x00 && channels == 2)
3490 return SNDRV_CTL_TLVT_CHMAP_FIXED;
3491
3492 /* If the speaker allocation matches the channel count, it is OK. */
3493 if (cap->channels != channels)
3494 return -1;
3495
3496 /* all channels are remappable freely */
3497 return SNDRV_CTL_TLVT_CHMAP_VAR;
3498}
3499
3500static int nvhdmi_chmap_validate(struct hdac_chmap *chmap,
3501 int ca, int chs, unsigned char *map)
3502{
3503 if (ca == 0x00 && (map[0] != SNDRV_CHMAP_FL || map[1] != SNDRV_CHMAP_FR))
3504 return -EINVAL;
3505
3506 return 0;
3507}
3508
3509/* map from pin NID to port; port is 0-based */
3510/* for Nvidia: assume widget NID starting from 4, with step 1 (4, 5, 6, ...) */
3511static int nvhdmi_pin2port(void *audio_ptr, int pin_nid)
3512{
3513 return pin_nid - 4;
3514}
3515
3516/* reverse-map from port to pin NID: see above */
3517static int nvhdmi_port2pin(struct hda_codec *codec, int port)
3518{
3519 return port + 4;
3520}
3521
3522static const struct drm_audio_component_audio_ops nvhdmi_audio_ops = {
3523 .pin2port = nvhdmi_pin2port,
3524 .pin_eld_notify = generic_acomp_pin_eld_notify,
3525 .master_bind = generic_acomp_master_bind,
3526 .master_unbind = generic_acomp_master_unbind,
3527};
3528
3529static int patch_nvhdmi(struct hda_codec *codec)
3530{
3531 struct hdmi_spec *spec;
3532 int err;
3533
3534 err = alloc_generic_hdmi(codec);
3535 if (err < 0)
3536 return err;
3537 codec->dp_mst = true;
3538
3539 spec = codec->spec;
3540 spec->dyn_pcm_assign = true;
3541
3542 err = hdmi_parse_codec(codec);
3543 if (err < 0) {
3544 generic_spec_free(codec);
3545 return err;
3546 }
3547
3548 generic_hdmi_init_per_pins(codec);
3549
3550 spec->dyn_pin_out = true;
3551
3552 spec->chmap.ops.chmap_cea_alloc_validate_get_type =
3553 nvhdmi_chmap_cea_alloc_validate_get_type;
3554 spec->chmap.ops.chmap_validate = nvhdmi_chmap_validate;
3555
3556 codec->link_down_at_suspend = 1;
3557
3558 generic_acomp_init(codec, &nvhdmi_audio_ops, nvhdmi_port2pin);
3559
3560 return 0;
3561}
3562
3563static int patch_nvhdmi_legacy(struct hda_codec *codec)
3564{
3565 struct hdmi_spec *spec;
3566 int err;
3567
3568 err = patch_generic_hdmi(codec);
3569 if (err)
3570 return err;
3571
3572 spec = codec->spec;
3573 spec->dyn_pin_out = true;
3574
3575 spec->chmap.ops.chmap_cea_alloc_validate_get_type =
3576 nvhdmi_chmap_cea_alloc_validate_get_type;
3577 spec->chmap.ops.chmap_validate = nvhdmi_chmap_validate;
3578
3579 codec->link_down_at_suspend = 1;
3580
3581 return 0;
3582}
3583
3584/*
3585 * The HDA codec on NVIDIA Tegra contains two scratch registers that are
3586 * accessed using vendor-defined verbs. These registers can be used for
3587 * interoperability between the HDA and HDMI drivers.
3588 */
3589
3590/* Audio Function Group node */
3591#define NVIDIA_AFG_NID 0x01
3592
3593/*
3594 * The SCRATCH0 register is used to notify the HDMI codec of changes in audio
3595 * format. On Tegra, bit 31 is used as a trigger that causes an interrupt to
3596 * be raised in the HDMI codec. The remainder of the bits is arbitrary. This
3597 * implementation stores the HDA format (see AC_FMT_*) in bits [15:0] and an
3598 * additional bit (at position 30) to signal the validity of the format.
3599 *
3600 * | 31 | 30 | 29 16 | 15 0 |
3601 * +---------+-------+--------+--------+
3602 * | TRIGGER | VALID | UNUSED | FORMAT |
3603 * +-----------------------------------|
3604 *
3605 * Note that for the trigger bit to take effect it needs to change value
3606 * (i.e. it needs to be toggled).
3607 */
3608#define NVIDIA_GET_SCRATCH0 0xfa6
3609#define NVIDIA_SET_SCRATCH0_BYTE0 0xfa7
3610#define NVIDIA_SET_SCRATCH0_BYTE1 0xfa8
3611#define NVIDIA_SET_SCRATCH0_BYTE2 0xfa9
3612#define NVIDIA_SET_SCRATCH0_BYTE3 0xfaa
3613#define NVIDIA_SCRATCH_TRIGGER (1 << 7)
3614#define NVIDIA_SCRATCH_VALID (1 << 6)
3615
3616#define NVIDIA_GET_SCRATCH1 0xfab
3617#define NVIDIA_SET_SCRATCH1_BYTE0 0xfac
3618#define NVIDIA_SET_SCRATCH1_BYTE1 0xfad
3619#define NVIDIA_SET_SCRATCH1_BYTE2 0xfae
3620#define NVIDIA_SET_SCRATCH1_BYTE3 0xfaf
3621
3622/*
3623 * The format parameter is the HDA audio format (see AC_FMT_*). If set to 0,
3624 * the format is invalidated so that the HDMI codec can be disabled.
3625 */
3626static void tegra_hdmi_set_format(struct hda_codec *codec, unsigned int format)
3627{
3628 unsigned int value;
3629
3630 /* bits [31:30] contain the trigger and valid bits */
3631 value = snd_hda_codec_read(codec, NVIDIA_AFG_NID, 0,
3632 NVIDIA_GET_SCRATCH0, 0);
3633 value = (value >> 24) & 0xff;
3634
3635 /* bits [15:0] are used to store the HDA format */
3636 snd_hda_codec_write(codec, NVIDIA_AFG_NID, 0,
3637 NVIDIA_SET_SCRATCH0_BYTE0,
3638 (format >> 0) & 0xff);
3639 snd_hda_codec_write(codec, NVIDIA_AFG_NID, 0,
3640 NVIDIA_SET_SCRATCH0_BYTE1,
3641 (format >> 8) & 0xff);
3642
3643 /* bits [16:24] are unused */
3644 snd_hda_codec_write(codec, NVIDIA_AFG_NID, 0,
3645 NVIDIA_SET_SCRATCH0_BYTE2, 0);
3646
3647 /*
3648 * Bit 30 signals that the data is valid and hence that HDMI audio can
3649 * be enabled.
3650 */
3651 if (format == 0)
3652 value &= ~NVIDIA_SCRATCH_VALID;
3653 else
3654 value |= NVIDIA_SCRATCH_VALID;
3655
3656 /*
3657 * Whenever the trigger bit is toggled, an interrupt is raised in the
3658 * HDMI codec. The HDMI driver will use that as trigger to update its
3659 * configuration.
3660 */
3661 value ^= NVIDIA_SCRATCH_TRIGGER;
3662
3663 snd_hda_codec_write(codec, NVIDIA_AFG_NID, 0,
3664 NVIDIA_SET_SCRATCH0_BYTE3, value);
3665}
3666
3667static int tegra_hdmi_pcm_prepare(struct hda_pcm_stream *hinfo,
3668 struct hda_codec *codec,
3669 unsigned int stream_tag,
3670 unsigned int format,
3671 struct snd_pcm_substream *substream)
3672{
3673 int err;
3674
3675 err = generic_hdmi_playback_pcm_prepare(hinfo, codec, stream_tag,
3676 format, substream);
3677 if (err < 0)
3678 return err;
3679
3680 /* notify the HDMI codec of the format change */
3681 tegra_hdmi_set_format(codec, format);
3682
3683 return 0;
3684}
3685
3686static int tegra_hdmi_pcm_cleanup(struct hda_pcm_stream *hinfo,
3687 struct hda_codec *codec,
3688 struct snd_pcm_substream *substream)
3689{
3690 /* invalidate the format in the HDMI codec */
3691 tegra_hdmi_set_format(codec, 0);
3692
3693 return generic_hdmi_playback_pcm_cleanup(hinfo, codec, substream);
3694}
3695
3696static struct hda_pcm *hda_find_pcm_by_type(struct hda_codec *codec, int type)
3697{
3698 struct hdmi_spec *spec = codec->spec;
3699 unsigned int i;
3700
3701 for (i = 0; i < spec->num_pins; i++) {
3702 struct hda_pcm *pcm = get_pcm_rec(spec, i);
3703
3704 if (pcm->pcm_type == type)
3705 return pcm;
3706 }
3707
3708 return NULL;
3709}
3710
3711static int tegra_hdmi_build_pcms(struct hda_codec *codec)
3712{
3713 struct hda_pcm_stream *stream;
3714 struct hda_pcm *pcm;
3715 int err;
3716
3717 err = generic_hdmi_build_pcms(codec);
3718 if (err < 0)
3719 return err;
3720
3721 pcm = hda_find_pcm_by_type(codec, HDA_PCM_TYPE_HDMI);
3722 if (!pcm)
3723 return -ENODEV;
3724
3725 /*
3726 * Override ->prepare() and ->cleanup() operations to notify the HDMI
3727 * codec about format changes.
3728 */
3729 stream = &pcm->stream[SNDRV_PCM_STREAM_PLAYBACK];
3730 stream->ops.prepare = tegra_hdmi_pcm_prepare;
3731 stream->ops.cleanup = tegra_hdmi_pcm_cleanup;
3732
3733 return 0;
3734}
3735
3736static int patch_tegra_hdmi(struct hda_codec *codec)
3737{
3738 struct hdmi_spec *spec;
3739 int err;
3740
3741 err = patch_generic_hdmi(codec);
3742 if (err)
3743 return err;
3744
3745 codec->patch_ops.build_pcms = tegra_hdmi_build_pcms;
3746 spec = codec->spec;
3747 spec->chmap.ops.chmap_cea_alloc_validate_get_type =
3748 nvhdmi_chmap_cea_alloc_validate_get_type;
3749 spec->chmap.ops.chmap_validate = nvhdmi_chmap_validate;
3750
3751 return 0;
3752}
3753
3754/*
3755 * ATI/AMD-specific implementations
3756 */
3757
3758#define is_amdhdmi_rev3_or_later(codec) \
3759 ((codec)->core.vendor_id == 0x1002aa01 && \
3760 ((codec)->core.revision_id & 0xff00) >= 0x0300)
3761#define has_amd_full_remap_support(codec) is_amdhdmi_rev3_or_later(codec)
3762
3763/* ATI/AMD specific HDA pin verbs, see the AMD HDA Verbs specification */
3764#define ATI_VERB_SET_CHANNEL_ALLOCATION 0x771
3765#define ATI_VERB_SET_DOWNMIX_INFO 0x772
3766#define ATI_VERB_SET_MULTICHANNEL_01 0x777
3767#define ATI_VERB_SET_MULTICHANNEL_23 0x778
3768#define ATI_VERB_SET_MULTICHANNEL_45 0x779
3769#define ATI_VERB_SET_MULTICHANNEL_67 0x77a
3770#define ATI_VERB_SET_HBR_CONTROL 0x77c
3771#define ATI_VERB_SET_MULTICHANNEL_1 0x785
3772#define ATI_VERB_SET_MULTICHANNEL_3 0x786
3773#define ATI_VERB_SET_MULTICHANNEL_5 0x787
3774#define ATI_VERB_SET_MULTICHANNEL_7 0x788
3775#define ATI_VERB_SET_MULTICHANNEL_MODE 0x789
3776#define ATI_VERB_GET_CHANNEL_ALLOCATION 0xf71
3777#define ATI_VERB_GET_DOWNMIX_INFO 0xf72
3778#define ATI_VERB_GET_MULTICHANNEL_01 0xf77
3779#define ATI_VERB_GET_MULTICHANNEL_23 0xf78
3780#define ATI_VERB_GET_MULTICHANNEL_45 0xf79
3781#define ATI_VERB_GET_MULTICHANNEL_67 0xf7a
3782#define ATI_VERB_GET_HBR_CONTROL 0xf7c
3783#define ATI_VERB_GET_MULTICHANNEL_1 0xf85
3784#define ATI_VERB_GET_MULTICHANNEL_3 0xf86
3785#define ATI_VERB_GET_MULTICHANNEL_5 0xf87
3786#define ATI_VERB_GET_MULTICHANNEL_7 0xf88
3787#define ATI_VERB_GET_MULTICHANNEL_MODE 0xf89
3788
3789/* AMD specific HDA cvt verbs */
3790#define ATI_VERB_SET_RAMP_RATE 0x770
3791#define ATI_VERB_GET_RAMP_RATE 0xf70
3792
3793#define ATI_OUT_ENABLE 0x1
3794
3795#define ATI_MULTICHANNEL_MODE_PAIRED 0
3796#define ATI_MULTICHANNEL_MODE_SINGLE 1
3797
3798#define ATI_HBR_CAPABLE 0x01
3799#define ATI_HBR_ENABLE 0x10
3800
3801static int atihdmi_pin_get_eld(struct hda_codec *codec, hda_nid_t nid,
3802 int dev_id, unsigned char *buf, int *eld_size)
3803{
3804 WARN_ON(dev_id != 0);
3805 /* call hda_eld.c ATI/AMD-specific function */
3806 return snd_hdmi_get_eld_ati(codec, nid, buf, eld_size,
3807 is_amdhdmi_rev3_or_later(codec));
3808}
3809
3810static void atihdmi_pin_setup_infoframe(struct hda_codec *codec,
3811 hda_nid_t pin_nid, int dev_id, int ca,
3812 int active_channels, int conn_type)
3813{
3814 WARN_ON(dev_id != 0);
3815 snd_hda_codec_write(codec, pin_nid, 0, ATI_VERB_SET_CHANNEL_ALLOCATION, ca);
3816}
3817
3818static int atihdmi_paired_swap_fc_lfe(int pos)
3819{
3820 /*
3821 * ATI/AMD have automatic FC/LFE swap built-in
3822 * when in pairwise mapping mode.
3823 */
3824
3825 switch (pos) {
3826 /* see channel_allocations[].speakers[] */
3827 case 2: return 3;
3828 case 3: return 2;
3829 default: break;
3830 }
3831
3832 return pos;
3833}
3834
3835static int atihdmi_paired_chmap_validate(struct hdac_chmap *chmap,
3836 int ca, int chs, unsigned char *map)
3837{
3838 struct hdac_cea_channel_speaker_allocation *cap;
3839 int i, j;
3840
3841 /* check that only channel pairs need to be remapped on old pre-rev3 ATI/AMD */
3842
3843 cap = snd_hdac_get_ch_alloc_from_ca(ca);
3844 for (i = 0; i < chs; ++i) {
3845 int mask = snd_hdac_chmap_to_spk_mask(map[i]);
3846 bool ok = false;
3847 bool companion_ok = false;
3848
3849 if (!mask)
3850 continue;
3851
3852 for (j = 0 + i % 2; j < 8; j += 2) {
3853 int chan_idx = 7 - atihdmi_paired_swap_fc_lfe(j);
3854 if (cap->speakers[chan_idx] == mask) {
3855 /* channel is in a supported position */
3856 ok = true;
3857
3858 if (i % 2 == 0 && i + 1 < chs) {
3859 /* even channel, check the odd companion */
3860 int comp_chan_idx = 7 - atihdmi_paired_swap_fc_lfe(j + 1);
3861 int comp_mask_req = snd_hdac_chmap_to_spk_mask(map[i+1]);
3862 int comp_mask_act = cap->speakers[comp_chan_idx];
3863
3864 if (comp_mask_req == comp_mask_act)
3865 companion_ok = true;
3866 else
3867 return -EINVAL;
3868 }
3869 break;
3870 }
3871 }
3872
3873 if (!ok)
3874 return -EINVAL;
3875
3876 if (companion_ok)
3877 i++; /* companion channel already checked */
3878 }
3879
3880 return 0;
3881}
3882
3883static int atihdmi_pin_set_slot_channel(struct hdac_device *hdac,
3884 hda_nid_t pin_nid, int hdmi_slot, int stream_channel)
3885{
3886 struct hda_codec *codec = hdac_to_hda_codec(hdac);
3887 int verb;
3888 int ati_channel_setup = 0;
3889
3890 if (hdmi_slot > 7)
3891 return -EINVAL;
3892
3893 if (!has_amd_full_remap_support(codec)) {
3894 hdmi_slot = atihdmi_paired_swap_fc_lfe(hdmi_slot);
3895
3896 /* In case this is an odd slot but without stream channel, do not
3897 * disable the slot since the corresponding even slot could have a
3898 * channel. In case neither have a channel, the slot pair will be
3899 * disabled when this function is called for the even slot. */
3900 if (hdmi_slot % 2 != 0 && stream_channel == 0xf)
3901 return 0;
3902
3903 hdmi_slot -= hdmi_slot % 2;
3904
3905 if (stream_channel != 0xf)
3906 stream_channel -= stream_channel % 2;
3907 }
3908
3909 verb = ATI_VERB_SET_MULTICHANNEL_01 + hdmi_slot/2 + (hdmi_slot % 2) * 0x00e;
3910
3911 /* ati_channel_setup format: [7..4] = stream_channel_id, [1] = mute, [0] = enable */
3912
3913 if (stream_channel != 0xf)
3914 ati_channel_setup = (stream_channel << 4) | ATI_OUT_ENABLE;
3915
3916 return snd_hda_codec_write(codec, pin_nid, 0, verb, ati_channel_setup);
3917}
3918
3919static int atihdmi_pin_get_slot_channel(struct hdac_device *hdac,
3920 hda_nid_t pin_nid, int asp_slot)
3921{
3922 struct hda_codec *codec = hdac_to_hda_codec(hdac);
3923 bool was_odd = false;
3924 int ati_asp_slot = asp_slot;
3925 int verb;
3926 int ati_channel_setup;
3927
3928 if (asp_slot > 7)
3929 return -EINVAL;
3930
3931 if (!has_amd_full_remap_support(codec)) {
3932 ati_asp_slot = atihdmi_paired_swap_fc_lfe(asp_slot);
3933 if (ati_asp_slot % 2 != 0) {
3934 ati_asp_slot -= 1;
3935 was_odd = true;
3936 }
3937 }
3938
3939 verb = ATI_VERB_GET_MULTICHANNEL_01 + ati_asp_slot/2 + (ati_asp_slot % 2) * 0x00e;
3940
3941 ati_channel_setup = snd_hda_codec_read(codec, pin_nid, 0, verb, 0);
3942
3943 if (!(ati_channel_setup & ATI_OUT_ENABLE))
3944 return 0xf;
3945
3946 return ((ati_channel_setup & 0xf0) >> 4) + !!was_odd;
3947}
3948
3949static int atihdmi_paired_chmap_cea_alloc_validate_get_type(
3950 struct hdac_chmap *chmap,
3951 struct hdac_cea_channel_speaker_allocation *cap,
3952 int channels)
3953{
3954 int c;
3955
3956 /*
3957 * Pre-rev3 ATI/AMD codecs operate in a paired channel mode, so
3958 * we need to take that into account (a single channel may take 2
3959 * channel slots if we need to carry a silent channel next to it).
3960 * On Rev3+ AMD codecs this function is not used.
3961 */
3962 int chanpairs = 0;
3963
3964 /* We only produce even-numbered channel count TLVs */
3965 if ((channels % 2) != 0)
3966 return -1;
3967
3968 for (c = 0; c < 7; c += 2) {
3969 if (cap->speakers[c] || cap->speakers[c+1])
3970 chanpairs++;
3971 }
3972
3973 if (chanpairs * 2 != channels)
3974 return -1;
3975
3976 return SNDRV_CTL_TLVT_CHMAP_PAIRED;
3977}
3978
3979static void atihdmi_paired_cea_alloc_to_tlv_chmap(struct hdac_chmap *hchmap,
3980 struct hdac_cea_channel_speaker_allocation *cap,
3981 unsigned int *chmap, int channels)
3982{
3983 /* produce paired maps for pre-rev3 ATI/AMD codecs */
3984 int count = 0;
3985 int c;
3986
3987 for (c = 7; c >= 0; c--) {
3988 int chan = 7 - atihdmi_paired_swap_fc_lfe(7 - c);
3989 int spk = cap->speakers[chan];
3990 if (!spk) {
3991 /* add N/A channel if the companion channel is occupied */
3992 if (cap->speakers[chan + (chan % 2 ? -1 : 1)])
3993 chmap[count++] = SNDRV_CHMAP_NA;
3994
3995 continue;
3996 }
3997
3998 chmap[count++] = snd_hdac_spk_to_chmap(spk);
3999 }
4000
4001 WARN_ON(count != channels);
4002}
4003
4004static int atihdmi_pin_hbr_setup(struct hda_codec *codec, hda_nid_t pin_nid,
4005 int dev_id, bool hbr)
4006{
4007 int hbr_ctl, hbr_ctl_new;
4008
4009 WARN_ON(dev_id != 0);
4010
4011 hbr_ctl = snd_hda_codec_read(codec, pin_nid, 0, ATI_VERB_GET_HBR_CONTROL, 0);
4012 if (hbr_ctl >= 0 && (hbr_ctl & ATI_HBR_CAPABLE)) {
4013 if (hbr)
4014 hbr_ctl_new = hbr_ctl | ATI_HBR_ENABLE;
4015 else
4016 hbr_ctl_new = hbr_ctl & ~ATI_HBR_ENABLE;
4017
4018 codec_dbg(codec,
4019 "atihdmi_pin_hbr_setup: NID=0x%x, %shbr-ctl=0x%x\n",
4020 pin_nid,
4021 hbr_ctl == hbr_ctl_new ? "" : "new-",
4022 hbr_ctl_new);
4023
4024 if (hbr_ctl != hbr_ctl_new)
4025 snd_hda_codec_write(codec, pin_nid, 0,
4026 ATI_VERB_SET_HBR_CONTROL,
4027 hbr_ctl_new);
4028
4029 } else if (hbr)
4030 return -EINVAL;
4031
4032 return 0;
4033}
4034
4035static int atihdmi_setup_stream(struct hda_codec *codec, hda_nid_t cvt_nid,
4036 hda_nid_t pin_nid, int dev_id,
4037 u32 stream_tag, int format)
4038{
4039 if (is_amdhdmi_rev3_or_later(codec)) {
4040 int ramp_rate = 180; /* default as per AMD spec */
4041 /* disable ramp-up/down for non-pcm as per AMD spec */
4042 if (format & AC_FMT_TYPE_NON_PCM)
4043 ramp_rate = 0;
4044
4045 snd_hda_codec_write(codec, cvt_nid, 0, ATI_VERB_SET_RAMP_RATE, ramp_rate);
4046 }
4047
4048 return hdmi_setup_stream(codec, cvt_nid, pin_nid, dev_id,
4049 stream_tag, format);
4050}
4051
4052
4053static int atihdmi_init(struct hda_codec *codec)
4054{
4055 struct hdmi_spec *spec = codec->spec;
4056 int pin_idx, err;
4057
4058 err = generic_hdmi_init(codec);
4059
4060 if (err)
4061 return err;
4062
4063 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
4064 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
4065
4066 /* make sure downmix information in infoframe is zero */
4067 snd_hda_codec_write(codec, per_pin->pin_nid, 0, ATI_VERB_SET_DOWNMIX_INFO, 0);
4068
4069 /* enable channel-wise remap mode if supported */
4070 if (has_amd_full_remap_support(codec))
4071 snd_hda_codec_write(codec, per_pin->pin_nid, 0,
4072 ATI_VERB_SET_MULTICHANNEL_MODE,
4073 ATI_MULTICHANNEL_MODE_SINGLE);
4074 }
4075 codec->auto_runtime_pm = 1;
4076
4077 return 0;
4078}
4079
4080/* map from pin NID to port; port is 0-based */
4081/* for AMD: assume widget NID starting from 3, with step 2 (3, 5, 7, ...) */
4082static int atihdmi_pin2port(void *audio_ptr, int pin_nid)
4083{
4084 return pin_nid / 2 - 1;
4085}
4086
4087/* reverse-map from port to pin NID: see above */
4088static int atihdmi_port2pin(struct hda_codec *codec, int port)
4089{
4090 return port * 2 + 3;
4091}
4092
4093static const struct drm_audio_component_audio_ops atihdmi_audio_ops = {
4094 .pin2port = atihdmi_pin2port,
4095 .pin_eld_notify = generic_acomp_pin_eld_notify,
4096 .master_bind = generic_acomp_master_bind,
4097 .master_unbind = generic_acomp_master_unbind,
4098};
4099
4100static int patch_atihdmi(struct hda_codec *codec)
4101{
4102 struct hdmi_spec *spec;
4103 struct hdmi_spec_per_cvt *per_cvt;
4104 int err, cvt_idx;
4105
4106 err = patch_generic_hdmi(codec);
4107
4108 if (err)
4109 return err;
4110
4111 codec->patch_ops.init = atihdmi_init;
4112
4113 spec = codec->spec;
4114
4115 spec->ops.pin_get_eld = atihdmi_pin_get_eld;
4116 spec->ops.pin_setup_infoframe = atihdmi_pin_setup_infoframe;
4117 spec->ops.pin_hbr_setup = atihdmi_pin_hbr_setup;
4118 spec->ops.setup_stream = atihdmi_setup_stream;
4119
4120 spec->chmap.ops.pin_get_slot_channel = atihdmi_pin_get_slot_channel;
4121 spec->chmap.ops.pin_set_slot_channel = atihdmi_pin_set_slot_channel;
4122
4123 if (!has_amd_full_remap_support(codec)) {
4124 /* override to ATI/AMD-specific versions with pairwise mapping */
4125 spec->chmap.ops.chmap_cea_alloc_validate_get_type =
4126 atihdmi_paired_chmap_cea_alloc_validate_get_type;
4127 spec->chmap.ops.cea_alloc_to_tlv_chmap =
4128 atihdmi_paired_cea_alloc_to_tlv_chmap;
4129 spec->chmap.ops.chmap_validate = atihdmi_paired_chmap_validate;
4130 }
4131
4132 /* ATI/AMD converters do not advertise all of their capabilities */
4133 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) {
4134 per_cvt = get_cvt(spec, cvt_idx);
4135 per_cvt->channels_max = max(per_cvt->channels_max, 8u);
4136 per_cvt->rates |= SUPPORTED_RATES;
4137 per_cvt->formats |= SUPPORTED_FORMATS;
4138 per_cvt->maxbps = max(per_cvt->maxbps, 24u);
4139 }
4140
4141 spec->chmap.channels_max = max(spec->chmap.channels_max, 8u);
4142
4143 /* AMD GPUs have neither EPSS nor CLKSTOP bits, hence preventing
4144 * the link-down as is. Tell the core to allow it.
4145 */
4146 codec->link_down_at_suspend = 1;
4147
4148 generic_acomp_init(codec, &atihdmi_audio_ops, atihdmi_port2pin);
4149
4150 return 0;
4151}
4152
4153/* VIA HDMI Implementation */
4154#define VIAHDMI_CVT_NID 0x02 /* audio converter1 */
4155#define VIAHDMI_PIN_NID 0x03 /* HDMI output pin1 */
4156
4157static int patch_via_hdmi(struct hda_codec *codec)
4158{
4159 return patch_simple_hdmi(codec, VIAHDMI_CVT_NID, VIAHDMI_PIN_NID);
4160}
4161
4162/*
4163 * patch entries
4164 */
4165static const struct hda_device_id snd_hda_id_hdmi[] = {
4166HDA_CODEC_ENTRY(0x1002793c, "RS600 HDMI", patch_atihdmi),
4167HDA_CODEC_ENTRY(0x10027919, "RS600 HDMI", patch_atihdmi),
4168HDA_CODEC_ENTRY(0x1002791a, "RS690/780 HDMI", patch_atihdmi),
4169HDA_CODEC_ENTRY(0x1002aa01, "R6xx HDMI", patch_atihdmi),
4170HDA_CODEC_ENTRY(0x10951390, "SiI1390 HDMI", patch_generic_hdmi),
4171HDA_CODEC_ENTRY(0x10951392, "SiI1392 HDMI", patch_generic_hdmi),
4172HDA_CODEC_ENTRY(0x17e80047, "Chrontel HDMI", patch_generic_hdmi),
4173HDA_CODEC_ENTRY(0x10de0001, "MCP73 HDMI", patch_nvhdmi_2ch),
4174HDA_CODEC_ENTRY(0x10de0002, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x),
4175HDA_CODEC_ENTRY(0x10de0003, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x),
4176HDA_CODEC_ENTRY(0x10de0004, "GPU 04 HDMI", patch_nvhdmi_8ch_7x),
4177HDA_CODEC_ENTRY(0x10de0005, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x),
4178HDA_CODEC_ENTRY(0x10de0006, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x),
4179HDA_CODEC_ENTRY(0x10de0007, "MCP79/7A HDMI", patch_nvhdmi_8ch_7x),
4180HDA_CODEC_ENTRY(0x10de0008, "GPU 08 HDMI/DP", patch_nvhdmi_legacy),
4181HDA_CODEC_ENTRY(0x10de0009, "GPU 09 HDMI/DP", patch_nvhdmi_legacy),
4182HDA_CODEC_ENTRY(0x10de000a, "GPU 0a HDMI/DP", patch_nvhdmi_legacy),
4183HDA_CODEC_ENTRY(0x10de000b, "GPU 0b HDMI/DP", patch_nvhdmi_legacy),
4184HDA_CODEC_ENTRY(0x10de000c, "MCP89 HDMI", patch_nvhdmi_legacy),
4185HDA_CODEC_ENTRY(0x10de000d, "GPU 0d HDMI/DP", patch_nvhdmi_legacy),
4186HDA_CODEC_ENTRY(0x10de0010, "GPU 10 HDMI/DP", patch_nvhdmi_legacy),
4187HDA_CODEC_ENTRY(0x10de0011, "GPU 11 HDMI/DP", patch_nvhdmi_legacy),
4188HDA_CODEC_ENTRY(0x10de0012, "GPU 12 HDMI/DP", patch_nvhdmi_legacy),
4189HDA_CODEC_ENTRY(0x10de0013, "GPU 13 HDMI/DP", patch_nvhdmi_legacy),
4190HDA_CODEC_ENTRY(0x10de0014, "GPU 14 HDMI/DP", patch_nvhdmi_legacy),
4191HDA_CODEC_ENTRY(0x10de0015, "GPU 15 HDMI/DP", patch_nvhdmi_legacy),
4192HDA_CODEC_ENTRY(0x10de0016, "GPU 16 HDMI/DP", patch_nvhdmi_legacy),
4193/* 17 is known to be absent */
4194HDA_CODEC_ENTRY(0x10de0018, "GPU 18 HDMI/DP", patch_nvhdmi_legacy),
4195HDA_CODEC_ENTRY(0x10de0019, "GPU 19 HDMI/DP", patch_nvhdmi_legacy),
4196HDA_CODEC_ENTRY(0x10de001a, "GPU 1a HDMI/DP", patch_nvhdmi_legacy),
4197HDA_CODEC_ENTRY(0x10de001b, "GPU 1b HDMI/DP", patch_nvhdmi_legacy),
4198HDA_CODEC_ENTRY(0x10de001c, "GPU 1c HDMI/DP", patch_nvhdmi_legacy),
4199HDA_CODEC_ENTRY(0x10de0020, "Tegra30 HDMI", patch_tegra_hdmi),
4200HDA_CODEC_ENTRY(0x10de0022, "Tegra114 HDMI", patch_tegra_hdmi),
4201HDA_CODEC_ENTRY(0x10de0028, "Tegra124 HDMI", patch_tegra_hdmi),
4202HDA_CODEC_ENTRY(0x10de0029, "Tegra210 HDMI/DP", patch_tegra_hdmi),
4203HDA_CODEC_ENTRY(0x10de002d, "Tegra186 HDMI/DP0", patch_tegra_hdmi),
4204HDA_CODEC_ENTRY(0x10de002e, "Tegra186 HDMI/DP1", patch_tegra_hdmi),
4205HDA_CODEC_ENTRY(0x10de002f, "Tegra194 HDMI/DP2", patch_tegra_hdmi),
4206HDA_CODEC_ENTRY(0x10de0030, "Tegra194 HDMI/DP3", patch_tegra_hdmi),
4207HDA_CODEC_ENTRY(0x10de0040, "GPU 40 HDMI/DP", patch_nvhdmi),
4208HDA_CODEC_ENTRY(0x10de0041, "GPU 41 HDMI/DP", patch_nvhdmi),
4209HDA_CODEC_ENTRY(0x10de0042, "GPU 42 HDMI/DP", patch_nvhdmi),
4210HDA_CODEC_ENTRY(0x10de0043, "GPU 43 HDMI/DP", patch_nvhdmi),
4211HDA_CODEC_ENTRY(0x10de0044, "GPU 44 HDMI/DP", patch_nvhdmi),
4212HDA_CODEC_ENTRY(0x10de0045, "GPU 45 HDMI/DP", patch_nvhdmi),
4213HDA_CODEC_ENTRY(0x10de0050, "GPU 50 HDMI/DP", patch_nvhdmi),
4214HDA_CODEC_ENTRY(0x10de0051, "GPU 51 HDMI/DP", patch_nvhdmi),
4215HDA_CODEC_ENTRY(0x10de0052, "GPU 52 HDMI/DP", patch_nvhdmi),
4216HDA_CODEC_ENTRY(0x10de0060, "GPU 60 HDMI/DP", patch_nvhdmi),
4217HDA_CODEC_ENTRY(0x10de0061, "GPU 61 HDMI/DP", patch_nvhdmi),
4218HDA_CODEC_ENTRY(0x10de0062, "GPU 62 HDMI/DP", patch_nvhdmi),
4219HDA_CODEC_ENTRY(0x10de0067, "MCP67 HDMI", patch_nvhdmi_2ch),
4220HDA_CODEC_ENTRY(0x10de0070, "GPU 70 HDMI/DP", patch_nvhdmi),
4221HDA_CODEC_ENTRY(0x10de0071, "GPU 71 HDMI/DP", patch_nvhdmi),
4222HDA_CODEC_ENTRY(0x10de0072, "GPU 72 HDMI/DP", patch_nvhdmi),
4223HDA_CODEC_ENTRY(0x10de0073, "GPU 73 HDMI/DP", patch_nvhdmi),
4224HDA_CODEC_ENTRY(0x10de0074, "GPU 74 HDMI/DP", patch_nvhdmi),
4225HDA_CODEC_ENTRY(0x10de0076, "GPU 76 HDMI/DP", patch_nvhdmi),
4226HDA_CODEC_ENTRY(0x10de007b, "GPU 7b HDMI/DP", patch_nvhdmi),
4227HDA_CODEC_ENTRY(0x10de007c, "GPU 7c HDMI/DP", patch_nvhdmi),
4228HDA_CODEC_ENTRY(0x10de007d, "GPU 7d HDMI/DP", patch_nvhdmi),
4229HDA_CODEC_ENTRY(0x10de007e, "GPU 7e HDMI/DP", patch_nvhdmi),
4230HDA_CODEC_ENTRY(0x10de0080, "GPU 80 HDMI/DP", patch_nvhdmi),
4231HDA_CODEC_ENTRY(0x10de0081, "GPU 81 HDMI/DP", patch_nvhdmi),
4232HDA_CODEC_ENTRY(0x10de0082, "GPU 82 HDMI/DP", patch_nvhdmi),
4233HDA_CODEC_ENTRY(0x10de0083, "GPU 83 HDMI/DP", patch_nvhdmi),
4234HDA_CODEC_ENTRY(0x10de0084, "GPU 84 HDMI/DP", patch_nvhdmi),
4235HDA_CODEC_ENTRY(0x10de0090, "GPU 90 HDMI/DP", patch_nvhdmi),
4236HDA_CODEC_ENTRY(0x10de0091, "GPU 91 HDMI/DP", patch_nvhdmi),
4237HDA_CODEC_ENTRY(0x10de0092, "GPU 92 HDMI/DP", patch_nvhdmi),
4238HDA_CODEC_ENTRY(0x10de0093, "GPU 93 HDMI/DP", patch_nvhdmi),
4239HDA_CODEC_ENTRY(0x10de0094, "GPU 94 HDMI/DP", patch_nvhdmi),
4240HDA_CODEC_ENTRY(0x10de0095, "GPU 95 HDMI/DP", patch_nvhdmi),
4241HDA_CODEC_ENTRY(0x10de0097, "GPU 97 HDMI/DP", patch_nvhdmi),
4242HDA_CODEC_ENTRY(0x10de0098, "GPU 98 HDMI/DP", patch_nvhdmi),
4243HDA_CODEC_ENTRY(0x10de0099, "GPU 99 HDMI/DP", patch_nvhdmi),
4244HDA_CODEC_ENTRY(0x10de009a, "GPU 9a HDMI/DP", patch_nvhdmi),
4245HDA_CODEC_ENTRY(0x10de009d, "GPU 9d HDMI/DP", patch_nvhdmi),
4246HDA_CODEC_ENTRY(0x10de009e, "GPU 9e HDMI/DP", patch_nvhdmi),
4247HDA_CODEC_ENTRY(0x10de009f, "GPU 9f HDMI/DP", patch_nvhdmi),
4248HDA_CODEC_ENTRY(0x10de00a0, "GPU a0 HDMI/DP", patch_nvhdmi),
4249HDA_CODEC_ENTRY(0x10de8001, "MCP73 HDMI", patch_nvhdmi_2ch),
4250HDA_CODEC_ENTRY(0x10de8067, "MCP67/68 HDMI", patch_nvhdmi_2ch),
4251HDA_CODEC_ENTRY(0x11069f80, "VX900 HDMI/DP", patch_via_hdmi),
4252HDA_CODEC_ENTRY(0x11069f81, "VX900 HDMI/DP", patch_via_hdmi),
4253HDA_CODEC_ENTRY(0x11069f84, "VX11 HDMI/DP", patch_generic_hdmi),
4254HDA_CODEC_ENTRY(0x11069f85, "VX11 HDMI/DP", patch_generic_hdmi),
4255HDA_CODEC_ENTRY(0x80860054, "IbexPeak HDMI", patch_i915_cpt_hdmi),
4256HDA_CODEC_ENTRY(0x80862800, "Geminilake HDMI", patch_i915_glk_hdmi),
4257HDA_CODEC_ENTRY(0x80862801, "Bearlake HDMI", patch_generic_hdmi),
4258HDA_CODEC_ENTRY(0x80862802, "Cantiga HDMI", patch_generic_hdmi),
4259HDA_CODEC_ENTRY(0x80862803, "Eaglelake HDMI", patch_generic_hdmi),
4260HDA_CODEC_ENTRY(0x80862804, "IbexPeak HDMI", patch_i915_cpt_hdmi),
4261HDA_CODEC_ENTRY(0x80862805, "CougarPoint HDMI", patch_i915_cpt_hdmi),
4262HDA_CODEC_ENTRY(0x80862806, "PantherPoint HDMI", patch_i915_cpt_hdmi),
4263HDA_CODEC_ENTRY(0x80862807, "Haswell HDMI", patch_i915_hsw_hdmi),
4264HDA_CODEC_ENTRY(0x80862808, "Broadwell HDMI", patch_i915_hsw_hdmi),
4265HDA_CODEC_ENTRY(0x80862809, "Skylake HDMI", patch_i915_hsw_hdmi),
4266HDA_CODEC_ENTRY(0x8086280a, "Broxton HDMI", patch_i915_hsw_hdmi),
4267HDA_CODEC_ENTRY(0x8086280b, "Kabylake HDMI", patch_i915_hsw_hdmi),
4268HDA_CODEC_ENTRY(0x8086280c, "Cannonlake HDMI", patch_i915_glk_hdmi),
4269HDA_CODEC_ENTRY(0x8086280d, "Geminilake HDMI", patch_i915_glk_hdmi),
4270HDA_CODEC_ENTRY(0x8086280f, "Icelake HDMI", patch_i915_icl_hdmi),
4271HDA_CODEC_ENTRY(0x80862812, "Tigerlake HDMI", patch_i915_tgl_hdmi),
4272HDA_CODEC_ENTRY(0x80862816, "Rocketlake HDMI", patch_i915_tgl_hdmi),
4273HDA_CODEC_ENTRY(0x8086281a, "Jasperlake HDMI", patch_i915_icl_hdmi),
4274HDA_CODEC_ENTRY(0x8086281b, "Elkhartlake HDMI", patch_i915_icl_hdmi),
4275HDA_CODEC_ENTRY(0x80862880, "CedarTrail HDMI", patch_generic_hdmi),
4276HDA_CODEC_ENTRY(0x80862882, "Valleyview2 HDMI", patch_i915_byt_hdmi),
4277HDA_CODEC_ENTRY(0x80862883, "Braswell HDMI", patch_i915_byt_hdmi),
4278HDA_CODEC_ENTRY(0x808629fb, "Crestline HDMI", patch_generic_hdmi),
4279/* special ID for generic HDMI */
4280HDA_CODEC_ENTRY(HDA_CODEC_ID_GENERIC_HDMI, "Generic HDMI", patch_generic_hdmi),
4281{} /* terminator */
4282};
4283MODULE_DEVICE_TABLE(hdaudio, snd_hda_id_hdmi);
4284
4285MODULE_LICENSE("GPL");
4286MODULE_DESCRIPTION("HDMI HD-audio codec");
4287MODULE_ALIAS("snd-hda-codec-intelhdmi");
4288MODULE_ALIAS("snd-hda-codec-nvhdmi");
4289MODULE_ALIAS("snd-hda-codec-atihdmi");
4290
4291static struct hda_codec_driver hdmi_driver = {
4292 .id = snd_hda_id_hdmi,
4293};
4294
4295module_hda_codec_driver(hdmi_driver);
1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 *
4 * patch_hdmi.c - routines for HDMI/DisplayPort codecs
5 *
6 * Copyright(c) 2008-2010 Intel Corporation. All rights reserved.
7 * Copyright (c) 2006 ATI Technologies Inc.
8 * Copyright (c) 2008 NVIDIA Corp. All rights reserved.
9 * Copyright (c) 2008 Wei Ni <wni@nvidia.com>
10 * Copyright (c) 2013 Anssi Hannula <anssi.hannula@iki.fi>
11 *
12 * Authors:
13 * Wu Fengguang <wfg@linux.intel.com>
14 *
15 * Maintained by:
16 * Wu Fengguang <wfg@linux.intel.com>
17 */
18
19#include <linux/init.h>
20#include <linux/delay.h>
21#include <linux/pci.h>
22#include <linux/slab.h>
23#include <linux/module.h>
24#include <linux/pm_runtime.h>
25#include <sound/core.h>
26#include <sound/jack.h>
27#include <sound/asoundef.h>
28#include <sound/tlv.h>
29#include <sound/hdaudio.h>
30#include <sound/hda_i915.h>
31#include <sound/hda_chmap.h>
32#include <sound/hda_codec.h>
33#include "hda_local.h"
34#include "hda_jack.h"
35
36static bool static_hdmi_pcm;
37module_param(static_hdmi_pcm, bool, 0644);
38MODULE_PARM_DESC(static_hdmi_pcm, "Don't restrict PCM parameters per ELD info");
39
40#define is_haswell(codec) ((codec)->core.vendor_id == 0x80862807)
41#define is_broadwell(codec) ((codec)->core.vendor_id == 0x80862808)
42#define is_skylake(codec) ((codec)->core.vendor_id == 0x80862809)
43#define is_broxton(codec) ((codec)->core.vendor_id == 0x8086280a)
44#define is_kabylake(codec) ((codec)->core.vendor_id == 0x8086280b)
45#define is_geminilake(codec) (((codec)->core.vendor_id == 0x8086280d) || \
46 ((codec)->core.vendor_id == 0x80862800))
47#define is_cannonlake(codec) ((codec)->core.vendor_id == 0x8086280c)
48#define is_icelake(codec) ((codec)->core.vendor_id == 0x8086280f)
49#define is_tigerlake(codec) ((codec)->core.vendor_id == 0x80862812)
50#define is_haswell_plus(codec) (is_haswell(codec) || is_broadwell(codec) \
51 || is_skylake(codec) || is_broxton(codec) \
52 || is_kabylake(codec) || is_geminilake(codec) \
53 || is_cannonlake(codec) || is_icelake(codec) \
54 || is_tigerlake(codec))
55#define is_valleyview(codec) ((codec)->core.vendor_id == 0x80862882)
56#define is_cherryview(codec) ((codec)->core.vendor_id == 0x80862883)
57#define is_valleyview_plus(codec) (is_valleyview(codec) || is_cherryview(codec))
58
59struct hdmi_spec_per_cvt {
60 hda_nid_t cvt_nid;
61 int assigned;
62 unsigned int channels_min;
63 unsigned int channels_max;
64 u32 rates;
65 u64 formats;
66 unsigned int maxbps;
67};
68
69/* max. connections to a widget */
70#define HDA_MAX_CONNECTIONS 32
71
72struct hdmi_spec_per_pin {
73 hda_nid_t pin_nid;
74 int dev_id;
75 /* pin idx, different device entries on the same pin use the same idx */
76 int pin_nid_idx;
77 int num_mux_nids;
78 hda_nid_t mux_nids[HDA_MAX_CONNECTIONS];
79 int mux_idx;
80 hda_nid_t cvt_nid;
81
82 struct hda_codec *codec;
83 struct hdmi_eld sink_eld;
84 struct mutex lock;
85 struct delayed_work work;
86 struct hdmi_pcm *pcm; /* pointer to spec->pcm_rec[n] dynamically*/
87 int pcm_idx; /* which pcm is attached. -1 means no pcm is attached */
88 int repoll_count;
89 bool setup; /* the stream has been set up by prepare callback */
90 int channels; /* current number of channels */
91 bool non_pcm;
92 bool chmap_set; /* channel-map override by ALSA API? */
93 unsigned char chmap[8]; /* ALSA API channel-map */
94#ifdef CONFIG_SND_PROC_FS
95 struct snd_info_entry *proc_entry;
96#endif
97};
98
99/* operations used by generic code that can be overridden by patches */
100struct hdmi_ops {
101 int (*pin_get_eld)(struct hda_codec *codec, hda_nid_t pin_nid,
102 unsigned char *buf, int *eld_size);
103
104 void (*pin_setup_infoframe)(struct hda_codec *codec, hda_nid_t pin_nid,
105 int ca, int active_channels, int conn_type);
106
107 /* enable/disable HBR (HD passthrough) */
108 int (*pin_hbr_setup)(struct hda_codec *codec, hda_nid_t pin_nid, bool hbr);
109
110 int (*setup_stream)(struct hda_codec *codec, hda_nid_t cvt_nid,
111 hda_nid_t pin_nid, u32 stream_tag, int format);
112
113 void (*pin_cvt_fixup)(struct hda_codec *codec,
114 struct hdmi_spec_per_pin *per_pin,
115 hda_nid_t cvt_nid);
116};
117
118struct hdmi_pcm {
119 struct hda_pcm *pcm;
120 struct snd_jack *jack;
121 struct snd_kcontrol *eld_ctl;
122};
123
124struct hdmi_spec {
125 struct hda_codec *codec;
126 int num_cvts;
127 struct snd_array cvts; /* struct hdmi_spec_per_cvt */
128 hda_nid_t cvt_nids[4]; /* only for haswell fix */
129
130 /*
131 * num_pins is the number of virtual pins
132 * for example, there are 3 pins, and each pin
133 * has 4 device entries, then the num_pins is 12
134 */
135 int num_pins;
136 /*
137 * num_nids is the number of real pins
138 * In the above example, num_nids is 3
139 */
140 int num_nids;
141 /*
142 * dev_num is the number of device entries
143 * on each pin.
144 * In the above example, dev_num is 4
145 */
146 int dev_num;
147 struct snd_array pins; /* struct hdmi_spec_per_pin */
148 struct hdmi_pcm pcm_rec[16];
149 struct mutex pcm_lock;
150 struct mutex bind_lock; /* for audio component binding */
151 /* pcm_bitmap means which pcms have been assigned to pins*/
152 unsigned long pcm_bitmap;
153 int pcm_used; /* counter of pcm_rec[] */
154 /* bitmap shows whether the pcm is opened in user space
155 * bit 0 means the first playback PCM (PCM3);
156 * bit 1 means the second playback PCM, and so on.
157 */
158 unsigned long pcm_in_use;
159
160 struct hdmi_eld temp_eld;
161 struct hdmi_ops ops;
162
163 bool dyn_pin_out;
164 bool dyn_pcm_assign;
165 /*
166 * Non-generic VIA/NVIDIA specific
167 */
168 struct hda_multi_out multiout;
169 struct hda_pcm_stream pcm_playback;
170
171 bool use_jack_detect; /* jack detection enabled */
172 bool use_acomp_notifier; /* use eld_notify callback for hotplug */
173 bool acomp_registered; /* audio component registered in this driver */
174 struct drm_audio_component_audio_ops drm_audio_ops;
175 int (*port2pin)(struct hda_codec *, int); /* reverse port/pin mapping */
176
177 struct hdac_chmap chmap;
178 hda_nid_t vendor_nid;
179 const int *port_map;
180 int port_num;
181};
182
183#ifdef CONFIG_SND_HDA_COMPONENT
184static inline bool codec_has_acomp(struct hda_codec *codec)
185{
186 struct hdmi_spec *spec = codec->spec;
187 return spec->use_acomp_notifier;
188}
189#else
190#define codec_has_acomp(codec) false
191#endif
192
193struct hdmi_audio_infoframe {
194 u8 type; /* 0x84 */
195 u8 ver; /* 0x01 */
196 u8 len; /* 0x0a */
197
198 u8 checksum;
199
200 u8 CC02_CT47; /* CC in bits 0:2, CT in 4:7 */
201 u8 SS01_SF24;
202 u8 CXT04;
203 u8 CA;
204 u8 LFEPBL01_LSV36_DM_INH7;
205};
206
207struct dp_audio_infoframe {
208 u8 type; /* 0x84 */
209 u8 len; /* 0x1b */
210 u8 ver; /* 0x11 << 2 */
211
212 u8 CC02_CT47; /* match with HDMI infoframe from this on */
213 u8 SS01_SF24;
214 u8 CXT04;
215 u8 CA;
216 u8 LFEPBL01_LSV36_DM_INH7;
217};
218
219union audio_infoframe {
220 struct hdmi_audio_infoframe hdmi;
221 struct dp_audio_infoframe dp;
222 u8 bytes[0];
223};
224
225/*
226 * HDMI routines
227 */
228
229#define get_pin(spec, idx) \
230 ((struct hdmi_spec_per_pin *)snd_array_elem(&spec->pins, idx))
231#define get_cvt(spec, idx) \
232 ((struct hdmi_spec_per_cvt *)snd_array_elem(&spec->cvts, idx))
233/* obtain hdmi_pcm object assigned to idx */
234#define get_hdmi_pcm(spec, idx) (&(spec)->pcm_rec[idx])
235/* obtain hda_pcm object assigned to idx */
236#define get_pcm_rec(spec, idx) (get_hdmi_pcm(spec, idx)->pcm)
237
238static int pin_id_to_pin_index(struct hda_codec *codec,
239 hda_nid_t pin_nid, int dev_id)
240{
241 struct hdmi_spec *spec = codec->spec;
242 int pin_idx;
243 struct hdmi_spec_per_pin *per_pin;
244
245 /*
246 * (dev_id == -1) means it is NON-MST pin
247 * return the first virtual pin on this port
248 */
249 if (dev_id == -1)
250 dev_id = 0;
251
252 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
253 per_pin = get_pin(spec, pin_idx);
254 if ((per_pin->pin_nid == pin_nid) &&
255 (per_pin->dev_id == dev_id))
256 return pin_idx;
257 }
258
259 codec_warn(codec, "HDMI: pin nid %d not registered\n", pin_nid);
260 return -EINVAL;
261}
262
263static int hinfo_to_pcm_index(struct hda_codec *codec,
264 struct hda_pcm_stream *hinfo)
265{
266 struct hdmi_spec *spec = codec->spec;
267 int pcm_idx;
268
269 for (pcm_idx = 0; pcm_idx < spec->pcm_used; pcm_idx++)
270 if (get_pcm_rec(spec, pcm_idx)->stream == hinfo)
271 return pcm_idx;
272
273 codec_warn(codec, "HDMI: hinfo %p not registered\n", hinfo);
274 return -EINVAL;
275}
276
277static int hinfo_to_pin_index(struct hda_codec *codec,
278 struct hda_pcm_stream *hinfo)
279{
280 struct hdmi_spec *spec = codec->spec;
281 struct hdmi_spec_per_pin *per_pin;
282 int pin_idx;
283
284 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
285 per_pin = get_pin(spec, pin_idx);
286 if (per_pin->pcm &&
287 per_pin->pcm->pcm->stream == hinfo)
288 return pin_idx;
289 }
290
291 codec_dbg(codec, "HDMI: hinfo %p not registered\n", hinfo);
292 return -EINVAL;
293}
294
295static struct hdmi_spec_per_pin *pcm_idx_to_pin(struct hdmi_spec *spec,
296 int pcm_idx)
297{
298 int i;
299 struct hdmi_spec_per_pin *per_pin;
300
301 for (i = 0; i < spec->num_pins; i++) {
302 per_pin = get_pin(spec, i);
303 if (per_pin->pcm_idx == pcm_idx)
304 return per_pin;
305 }
306 return NULL;
307}
308
309static int cvt_nid_to_cvt_index(struct hda_codec *codec, hda_nid_t cvt_nid)
310{
311 struct hdmi_spec *spec = codec->spec;
312 int cvt_idx;
313
314 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++)
315 if (get_cvt(spec, cvt_idx)->cvt_nid == cvt_nid)
316 return cvt_idx;
317
318 codec_warn(codec, "HDMI: cvt nid %d not registered\n", cvt_nid);
319 return -EINVAL;
320}
321
322static int hdmi_eld_ctl_info(struct snd_kcontrol *kcontrol,
323 struct snd_ctl_elem_info *uinfo)
324{
325 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
326 struct hdmi_spec *spec = codec->spec;
327 struct hdmi_spec_per_pin *per_pin;
328 struct hdmi_eld *eld;
329 int pcm_idx;
330
331 uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES;
332
333 pcm_idx = kcontrol->private_value;
334 mutex_lock(&spec->pcm_lock);
335 per_pin = pcm_idx_to_pin(spec, pcm_idx);
336 if (!per_pin) {
337 /* no pin is bound to the pcm */
338 uinfo->count = 0;
339 goto unlock;
340 }
341 eld = &per_pin->sink_eld;
342 uinfo->count = eld->eld_valid ? eld->eld_size : 0;
343
344 unlock:
345 mutex_unlock(&spec->pcm_lock);
346 return 0;
347}
348
349static int hdmi_eld_ctl_get(struct snd_kcontrol *kcontrol,
350 struct snd_ctl_elem_value *ucontrol)
351{
352 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
353 struct hdmi_spec *spec = codec->spec;
354 struct hdmi_spec_per_pin *per_pin;
355 struct hdmi_eld *eld;
356 int pcm_idx;
357 int err = 0;
358
359 pcm_idx = kcontrol->private_value;
360 mutex_lock(&spec->pcm_lock);
361 per_pin = pcm_idx_to_pin(spec, pcm_idx);
362 if (!per_pin) {
363 /* no pin is bound to the pcm */
364 memset(ucontrol->value.bytes.data, 0,
365 ARRAY_SIZE(ucontrol->value.bytes.data));
366 goto unlock;
367 }
368
369 eld = &per_pin->sink_eld;
370 if (eld->eld_size > ARRAY_SIZE(ucontrol->value.bytes.data) ||
371 eld->eld_size > ELD_MAX_SIZE) {
372 snd_BUG();
373 err = -EINVAL;
374 goto unlock;
375 }
376
377 memset(ucontrol->value.bytes.data, 0,
378 ARRAY_SIZE(ucontrol->value.bytes.data));
379 if (eld->eld_valid)
380 memcpy(ucontrol->value.bytes.data, eld->eld_buffer,
381 eld->eld_size);
382
383 unlock:
384 mutex_unlock(&spec->pcm_lock);
385 return err;
386}
387
388static const struct snd_kcontrol_new eld_bytes_ctl = {
389 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE,
390 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
391 .name = "ELD",
392 .info = hdmi_eld_ctl_info,
393 .get = hdmi_eld_ctl_get,
394};
395
396static int hdmi_create_eld_ctl(struct hda_codec *codec, int pcm_idx,
397 int device)
398{
399 struct snd_kcontrol *kctl;
400 struct hdmi_spec *spec = codec->spec;
401 int err;
402
403 kctl = snd_ctl_new1(&eld_bytes_ctl, codec);
404 if (!kctl)
405 return -ENOMEM;
406 kctl->private_value = pcm_idx;
407 kctl->id.device = device;
408
409 /* no pin nid is associated with the kctl now
410 * tbd: associate pin nid to eld ctl later
411 */
412 err = snd_hda_ctl_add(codec, 0, kctl);
413 if (err < 0)
414 return err;
415
416 get_hdmi_pcm(spec, pcm_idx)->eld_ctl = kctl;
417 return 0;
418}
419
420#ifdef BE_PARANOID
421static void hdmi_get_dip_index(struct hda_codec *codec, hda_nid_t pin_nid,
422 int *packet_index, int *byte_index)
423{
424 int val;
425
426 val = snd_hda_codec_read(codec, pin_nid, 0,
427 AC_VERB_GET_HDMI_DIP_INDEX, 0);
428
429 *packet_index = val >> 5;
430 *byte_index = val & 0x1f;
431}
432#endif
433
434static void hdmi_set_dip_index(struct hda_codec *codec, hda_nid_t pin_nid,
435 int packet_index, int byte_index)
436{
437 int val;
438
439 val = (packet_index << 5) | (byte_index & 0x1f);
440
441 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_INDEX, val);
442}
443
444static void hdmi_write_dip_byte(struct hda_codec *codec, hda_nid_t pin_nid,
445 unsigned char val)
446{
447 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_DATA, val);
448}
449
450static void hdmi_init_pin(struct hda_codec *codec, hda_nid_t pin_nid)
451{
452 struct hdmi_spec *spec = codec->spec;
453 int pin_out;
454
455 /* Unmute */
456 if (get_wcaps(codec, pin_nid) & AC_WCAP_OUT_AMP)
457 snd_hda_codec_write(codec, pin_nid, 0,
458 AC_VERB_SET_AMP_GAIN_MUTE, AMP_OUT_UNMUTE);
459
460 if (spec->dyn_pin_out)
461 /* Disable pin out until stream is active */
462 pin_out = 0;
463 else
464 /* Enable pin out: some machines with GM965 gets broken output
465 * when the pin is disabled or changed while using with HDMI
466 */
467 pin_out = PIN_OUT;
468
469 snd_hda_codec_write(codec, pin_nid, 0,
470 AC_VERB_SET_PIN_WIDGET_CONTROL, pin_out);
471}
472
473/*
474 * ELD proc files
475 */
476
477#ifdef CONFIG_SND_PROC_FS
478static void print_eld_info(struct snd_info_entry *entry,
479 struct snd_info_buffer *buffer)
480{
481 struct hdmi_spec_per_pin *per_pin = entry->private_data;
482
483 mutex_lock(&per_pin->lock);
484 snd_hdmi_print_eld_info(&per_pin->sink_eld, buffer);
485 mutex_unlock(&per_pin->lock);
486}
487
488static void write_eld_info(struct snd_info_entry *entry,
489 struct snd_info_buffer *buffer)
490{
491 struct hdmi_spec_per_pin *per_pin = entry->private_data;
492
493 mutex_lock(&per_pin->lock);
494 snd_hdmi_write_eld_info(&per_pin->sink_eld, buffer);
495 mutex_unlock(&per_pin->lock);
496}
497
498static int eld_proc_new(struct hdmi_spec_per_pin *per_pin, int index)
499{
500 char name[32];
501 struct hda_codec *codec = per_pin->codec;
502 struct snd_info_entry *entry;
503 int err;
504
505 snprintf(name, sizeof(name), "eld#%d.%d", codec->addr, index);
506 err = snd_card_proc_new(codec->card, name, &entry);
507 if (err < 0)
508 return err;
509
510 snd_info_set_text_ops(entry, per_pin, print_eld_info);
511 entry->c.text.write = write_eld_info;
512 entry->mode |= 0200;
513 per_pin->proc_entry = entry;
514
515 return 0;
516}
517
518static void eld_proc_free(struct hdmi_spec_per_pin *per_pin)
519{
520 if (!per_pin->codec->bus->shutdown) {
521 snd_info_free_entry(per_pin->proc_entry);
522 per_pin->proc_entry = NULL;
523 }
524}
525#else
526static inline int eld_proc_new(struct hdmi_spec_per_pin *per_pin,
527 int index)
528{
529 return 0;
530}
531static inline void eld_proc_free(struct hdmi_spec_per_pin *per_pin)
532{
533}
534#endif
535
536/*
537 * Audio InfoFrame routines
538 */
539
540/*
541 * Enable Audio InfoFrame Transmission
542 */
543static void hdmi_start_infoframe_trans(struct hda_codec *codec,
544 hda_nid_t pin_nid)
545{
546 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
547 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_XMIT,
548 AC_DIPXMIT_BEST);
549}
550
551/*
552 * Disable Audio InfoFrame Transmission
553 */
554static void hdmi_stop_infoframe_trans(struct hda_codec *codec,
555 hda_nid_t pin_nid)
556{
557 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
558 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_XMIT,
559 AC_DIPXMIT_DISABLE);
560}
561
562static void hdmi_debug_dip_size(struct hda_codec *codec, hda_nid_t pin_nid)
563{
564#ifdef CONFIG_SND_DEBUG_VERBOSE
565 int i;
566 int size;
567
568 size = snd_hdmi_get_eld_size(codec, pin_nid);
569 codec_dbg(codec, "HDMI: ELD buf size is %d\n", size);
570
571 for (i = 0; i < 8; i++) {
572 size = snd_hda_codec_read(codec, pin_nid, 0,
573 AC_VERB_GET_HDMI_DIP_SIZE, i);
574 codec_dbg(codec, "HDMI: DIP GP[%d] buf size is %d\n", i, size);
575 }
576#endif
577}
578
579static void hdmi_clear_dip_buffers(struct hda_codec *codec, hda_nid_t pin_nid)
580{
581#ifdef BE_PARANOID
582 int i, j;
583 int size;
584 int pi, bi;
585 for (i = 0; i < 8; i++) {
586 size = snd_hda_codec_read(codec, pin_nid, 0,
587 AC_VERB_GET_HDMI_DIP_SIZE, i);
588 if (size == 0)
589 continue;
590
591 hdmi_set_dip_index(codec, pin_nid, i, 0x0);
592 for (j = 1; j < 1000; j++) {
593 hdmi_write_dip_byte(codec, pin_nid, 0x0);
594 hdmi_get_dip_index(codec, pin_nid, &pi, &bi);
595 if (pi != i)
596 codec_dbg(codec, "dip index %d: %d != %d\n",
597 bi, pi, i);
598 if (bi == 0) /* byte index wrapped around */
599 break;
600 }
601 codec_dbg(codec,
602 "HDMI: DIP GP[%d] buf reported size=%d, written=%d\n",
603 i, size, j);
604 }
605#endif
606}
607
608static void hdmi_checksum_audio_infoframe(struct hdmi_audio_infoframe *hdmi_ai)
609{
610 u8 *bytes = (u8 *)hdmi_ai;
611 u8 sum = 0;
612 int i;
613
614 hdmi_ai->checksum = 0;
615
616 for (i = 0; i < sizeof(*hdmi_ai); i++)
617 sum += bytes[i];
618
619 hdmi_ai->checksum = -sum;
620}
621
622static void hdmi_fill_audio_infoframe(struct hda_codec *codec,
623 hda_nid_t pin_nid,
624 u8 *dip, int size)
625{
626 int i;
627
628 hdmi_debug_dip_size(codec, pin_nid);
629 hdmi_clear_dip_buffers(codec, pin_nid); /* be paranoid */
630
631 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
632 for (i = 0; i < size; i++)
633 hdmi_write_dip_byte(codec, pin_nid, dip[i]);
634}
635
636static bool hdmi_infoframe_uptodate(struct hda_codec *codec, hda_nid_t pin_nid,
637 u8 *dip, int size)
638{
639 u8 val;
640 int i;
641
642 if (snd_hda_codec_read(codec, pin_nid, 0, AC_VERB_GET_HDMI_DIP_XMIT, 0)
643 != AC_DIPXMIT_BEST)
644 return false;
645
646 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
647 for (i = 0; i < size; i++) {
648 val = snd_hda_codec_read(codec, pin_nid, 0,
649 AC_VERB_GET_HDMI_DIP_DATA, 0);
650 if (val != dip[i])
651 return false;
652 }
653
654 return true;
655}
656
657static void hdmi_pin_setup_infoframe(struct hda_codec *codec,
658 hda_nid_t pin_nid,
659 int ca, int active_channels,
660 int conn_type)
661{
662 union audio_infoframe ai;
663
664 memset(&ai, 0, sizeof(ai));
665 if (conn_type == 0) { /* HDMI */
666 struct hdmi_audio_infoframe *hdmi_ai = &ai.hdmi;
667
668 hdmi_ai->type = 0x84;
669 hdmi_ai->ver = 0x01;
670 hdmi_ai->len = 0x0a;
671 hdmi_ai->CC02_CT47 = active_channels - 1;
672 hdmi_ai->CA = ca;
673 hdmi_checksum_audio_infoframe(hdmi_ai);
674 } else if (conn_type == 1) { /* DisplayPort */
675 struct dp_audio_infoframe *dp_ai = &ai.dp;
676
677 dp_ai->type = 0x84;
678 dp_ai->len = 0x1b;
679 dp_ai->ver = 0x11 << 2;
680 dp_ai->CC02_CT47 = active_channels - 1;
681 dp_ai->CA = ca;
682 } else {
683 codec_dbg(codec, "HDMI: unknown connection type at pin %d\n",
684 pin_nid);
685 return;
686 }
687
688 /*
689 * sizeof(ai) is used instead of sizeof(*hdmi_ai) or
690 * sizeof(*dp_ai) to avoid partial match/update problems when
691 * the user switches between HDMI/DP monitors.
692 */
693 if (!hdmi_infoframe_uptodate(codec, pin_nid, ai.bytes,
694 sizeof(ai))) {
695 codec_dbg(codec,
696 "hdmi_pin_setup_infoframe: pin=%d channels=%d ca=0x%02x\n",
697 pin_nid,
698 active_channels, ca);
699 hdmi_stop_infoframe_trans(codec, pin_nid);
700 hdmi_fill_audio_infoframe(codec, pin_nid,
701 ai.bytes, sizeof(ai));
702 hdmi_start_infoframe_trans(codec, pin_nid);
703 }
704}
705
706static void hdmi_setup_audio_infoframe(struct hda_codec *codec,
707 struct hdmi_spec_per_pin *per_pin,
708 bool non_pcm)
709{
710 struct hdmi_spec *spec = codec->spec;
711 struct hdac_chmap *chmap = &spec->chmap;
712 hda_nid_t pin_nid = per_pin->pin_nid;
713 int channels = per_pin->channels;
714 int active_channels;
715 struct hdmi_eld *eld;
716 int ca;
717
718 if (!channels)
719 return;
720
721 /* some HW (e.g. HSW+) needs reprogramming the amp at each time */
722 if (get_wcaps(codec, pin_nid) & AC_WCAP_OUT_AMP)
723 snd_hda_codec_write(codec, pin_nid, 0,
724 AC_VERB_SET_AMP_GAIN_MUTE,
725 AMP_OUT_UNMUTE);
726
727 eld = &per_pin->sink_eld;
728
729 ca = snd_hdac_channel_allocation(&codec->core,
730 eld->info.spk_alloc, channels,
731 per_pin->chmap_set, non_pcm, per_pin->chmap);
732
733 active_channels = snd_hdac_get_active_channels(ca);
734
735 chmap->ops.set_channel_count(&codec->core, per_pin->cvt_nid,
736 active_channels);
737
738 /*
739 * always configure channel mapping, it may have been changed by the
740 * user in the meantime
741 */
742 snd_hdac_setup_channel_mapping(&spec->chmap,
743 pin_nid, non_pcm, ca, channels,
744 per_pin->chmap, per_pin->chmap_set);
745
746 spec->ops.pin_setup_infoframe(codec, pin_nid, ca, active_channels,
747 eld->info.conn_type);
748
749 per_pin->non_pcm = non_pcm;
750}
751
752/*
753 * Unsolicited events
754 */
755
756static bool hdmi_present_sense(struct hdmi_spec_per_pin *per_pin, int repoll);
757
758static void check_presence_and_report(struct hda_codec *codec, hda_nid_t nid,
759 int dev_id)
760{
761 struct hdmi_spec *spec = codec->spec;
762 int pin_idx = pin_id_to_pin_index(codec, nid, dev_id);
763
764 if (pin_idx < 0)
765 return;
766 mutex_lock(&spec->pcm_lock);
767 if (hdmi_present_sense(get_pin(spec, pin_idx), 1))
768 snd_hda_jack_report_sync(codec);
769 mutex_unlock(&spec->pcm_lock);
770}
771
772static void jack_callback(struct hda_codec *codec,
773 struct hda_jack_callback *jack)
774{
775 /* stop polling when notification is enabled */
776 if (codec_has_acomp(codec))
777 return;
778
779 /* hda_jack don't support DP MST */
780 check_presence_and_report(codec, jack->nid, 0);
781}
782
783static void hdmi_intrinsic_event(struct hda_codec *codec, unsigned int res)
784{
785 int tag = res >> AC_UNSOL_RES_TAG_SHIFT;
786 struct hda_jack_tbl *jack;
787 int dev_entry = (res & AC_UNSOL_RES_DE) >> AC_UNSOL_RES_DE_SHIFT;
788
789 /*
790 * assume DP MST uses dyn_pcm_assign and acomp and
791 * never comes here
792 * if DP MST supports unsol event, below code need
793 * consider dev_entry
794 */
795 jack = snd_hda_jack_tbl_get_from_tag(codec, tag);
796 if (!jack)
797 return;
798 jack->jack_dirty = 1;
799
800 codec_dbg(codec,
801 "HDMI hot plug event: Codec=%d Pin=%d Device=%d Inactive=%d Presence_Detect=%d ELD_Valid=%d\n",
802 codec->addr, jack->nid, dev_entry, !!(res & AC_UNSOL_RES_IA),
803 !!(res & AC_UNSOL_RES_PD), !!(res & AC_UNSOL_RES_ELDV));
804
805 /* hda_jack don't support DP MST */
806 check_presence_and_report(codec, jack->nid, 0);
807}
808
809static void hdmi_non_intrinsic_event(struct hda_codec *codec, unsigned int res)
810{
811 int tag = res >> AC_UNSOL_RES_TAG_SHIFT;
812 int subtag = (res & AC_UNSOL_RES_SUBTAG) >> AC_UNSOL_RES_SUBTAG_SHIFT;
813 int cp_state = !!(res & AC_UNSOL_RES_CP_STATE);
814 int cp_ready = !!(res & AC_UNSOL_RES_CP_READY);
815
816 codec_info(codec,
817 "HDMI CP event: CODEC=%d TAG=%d SUBTAG=0x%x CP_STATE=%d CP_READY=%d\n",
818 codec->addr,
819 tag,
820 subtag,
821 cp_state,
822 cp_ready);
823
824 /* TODO */
825 if (cp_state)
826 ;
827 if (cp_ready)
828 ;
829}
830
831
832static void hdmi_unsol_event(struct hda_codec *codec, unsigned int res)
833{
834 int tag = res >> AC_UNSOL_RES_TAG_SHIFT;
835 int subtag = (res & AC_UNSOL_RES_SUBTAG) >> AC_UNSOL_RES_SUBTAG_SHIFT;
836
837 if (codec_has_acomp(codec))
838 return;
839
840 if (!snd_hda_jack_tbl_get_from_tag(codec, tag)) {
841 codec_dbg(codec, "Unexpected HDMI event tag 0x%x\n", tag);
842 return;
843 }
844
845 if (subtag == 0)
846 hdmi_intrinsic_event(codec, res);
847 else
848 hdmi_non_intrinsic_event(codec, res);
849}
850
851static void haswell_verify_D0(struct hda_codec *codec,
852 hda_nid_t cvt_nid, hda_nid_t nid)
853{
854 int pwr;
855
856 /* For Haswell, the converter 1/2 may keep in D3 state after bootup,
857 * thus pins could only choose converter 0 for use. Make sure the
858 * converters are in correct power state */
859 if (!snd_hda_check_power_state(codec, cvt_nid, AC_PWRST_D0))
860 snd_hda_codec_write(codec, cvt_nid, 0, AC_VERB_SET_POWER_STATE, AC_PWRST_D0);
861
862 if (!snd_hda_check_power_state(codec, nid, AC_PWRST_D0)) {
863 snd_hda_codec_write(codec, nid, 0, AC_VERB_SET_POWER_STATE,
864 AC_PWRST_D0);
865 msleep(40);
866 pwr = snd_hda_codec_read(codec, nid, 0, AC_VERB_GET_POWER_STATE, 0);
867 pwr = (pwr & AC_PWRST_ACTUAL) >> AC_PWRST_ACTUAL_SHIFT;
868 codec_dbg(codec, "Haswell HDMI audio: Power for pin 0x%x is now D%d\n", nid, pwr);
869 }
870}
871
872/*
873 * Callbacks
874 */
875
876/* HBR should be Non-PCM, 8 channels */
877#define is_hbr_format(format) \
878 ((format & AC_FMT_TYPE_NON_PCM) && (format & AC_FMT_CHAN_MASK) == 7)
879
880static int hdmi_pin_hbr_setup(struct hda_codec *codec, hda_nid_t pin_nid,
881 bool hbr)
882{
883 int pinctl, new_pinctl;
884
885 if (snd_hda_query_pin_caps(codec, pin_nid) & AC_PINCAP_HBR) {
886 pinctl = snd_hda_codec_read(codec, pin_nid, 0,
887 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
888
889 if (pinctl < 0)
890 return hbr ? -EINVAL : 0;
891
892 new_pinctl = pinctl & ~AC_PINCTL_EPT;
893 if (hbr)
894 new_pinctl |= AC_PINCTL_EPT_HBR;
895 else
896 new_pinctl |= AC_PINCTL_EPT_NATIVE;
897
898 codec_dbg(codec,
899 "hdmi_pin_hbr_setup: NID=0x%x, %spinctl=0x%x\n",
900 pin_nid,
901 pinctl == new_pinctl ? "" : "new-",
902 new_pinctl);
903
904 if (pinctl != new_pinctl)
905 snd_hda_codec_write(codec, pin_nid, 0,
906 AC_VERB_SET_PIN_WIDGET_CONTROL,
907 new_pinctl);
908 } else if (hbr)
909 return -EINVAL;
910
911 return 0;
912}
913
914static int hdmi_setup_stream(struct hda_codec *codec, hda_nid_t cvt_nid,
915 hda_nid_t pin_nid, u32 stream_tag, int format)
916{
917 struct hdmi_spec *spec = codec->spec;
918 unsigned int param;
919 int err;
920
921 err = spec->ops.pin_hbr_setup(codec, pin_nid, is_hbr_format(format));
922
923 if (err) {
924 codec_dbg(codec, "hdmi_setup_stream: HBR is not supported\n");
925 return err;
926 }
927
928 if (is_haswell_plus(codec)) {
929
930 /*
931 * on recent platforms IEC Coding Type is required for HBR
932 * support, read current Digital Converter settings and set
933 * ICT bitfield if needed.
934 */
935 param = snd_hda_codec_read(codec, cvt_nid, 0,
936 AC_VERB_GET_DIGI_CONVERT_1, 0);
937
938 param = (param >> 16) & ~(AC_DIG3_ICT);
939
940 /* on recent platforms ICT mode is required for HBR support */
941 if (is_hbr_format(format))
942 param |= 0x1;
943
944 snd_hda_codec_write(codec, cvt_nid, 0,
945 AC_VERB_SET_DIGI_CONVERT_3, param);
946 }
947
948 snd_hda_codec_setup_stream(codec, cvt_nid, stream_tag, 0, format);
949 return 0;
950}
951
952/* Try to find an available converter
953 * If pin_idx is less then zero, just try to find an available converter.
954 * Otherwise, try to find an available converter and get the cvt mux index
955 * of the pin.
956 */
957static int hdmi_choose_cvt(struct hda_codec *codec,
958 int pin_idx, int *cvt_id)
959{
960 struct hdmi_spec *spec = codec->spec;
961 struct hdmi_spec_per_pin *per_pin;
962 struct hdmi_spec_per_cvt *per_cvt = NULL;
963 int cvt_idx, mux_idx = 0;
964
965 /* pin_idx < 0 means no pin will be bound to the converter */
966 if (pin_idx < 0)
967 per_pin = NULL;
968 else
969 per_pin = get_pin(spec, pin_idx);
970
971 /* Dynamically assign converter to stream */
972 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) {
973 per_cvt = get_cvt(spec, cvt_idx);
974
975 /* Must not already be assigned */
976 if (per_cvt->assigned)
977 continue;
978 if (per_pin == NULL)
979 break;
980 /* Must be in pin's mux's list of converters */
981 for (mux_idx = 0; mux_idx < per_pin->num_mux_nids; mux_idx++)
982 if (per_pin->mux_nids[mux_idx] == per_cvt->cvt_nid)
983 break;
984 /* Not in mux list */
985 if (mux_idx == per_pin->num_mux_nids)
986 continue;
987 break;
988 }
989
990 /* No free converters */
991 if (cvt_idx == spec->num_cvts)
992 return -EBUSY;
993
994 if (per_pin != NULL)
995 per_pin->mux_idx = mux_idx;
996
997 if (cvt_id)
998 *cvt_id = cvt_idx;
999
1000 return 0;
1001}
1002
1003/* Assure the pin select the right convetor */
1004static void intel_verify_pin_cvt_connect(struct hda_codec *codec,
1005 struct hdmi_spec_per_pin *per_pin)
1006{
1007 hda_nid_t pin_nid = per_pin->pin_nid;
1008 int mux_idx, curr;
1009
1010 mux_idx = per_pin->mux_idx;
1011 curr = snd_hda_codec_read(codec, pin_nid, 0,
1012 AC_VERB_GET_CONNECT_SEL, 0);
1013 if (curr != mux_idx)
1014 snd_hda_codec_write_cache(codec, pin_nid, 0,
1015 AC_VERB_SET_CONNECT_SEL,
1016 mux_idx);
1017}
1018
1019/* get the mux index for the converter of the pins
1020 * converter's mux index is the same for all pins on Intel platform
1021 */
1022static int intel_cvt_id_to_mux_idx(struct hdmi_spec *spec,
1023 hda_nid_t cvt_nid)
1024{
1025 int i;
1026
1027 for (i = 0; i < spec->num_cvts; i++)
1028 if (spec->cvt_nids[i] == cvt_nid)
1029 return i;
1030 return -EINVAL;
1031}
1032
1033/* Intel HDMI workaround to fix audio routing issue:
1034 * For some Intel display codecs, pins share the same connection list.
1035 * So a conveter can be selected by multiple pins and playback on any of these
1036 * pins will generate sound on the external display, because audio flows from
1037 * the same converter to the display pipeline. Also muting one pin may make
1038 * other pins have no sound output.
1039 * So this function assures that an assigned converter for a pin is not selected
1040 * by any other pins.
1041 */
1042static void intel_not_share_assigned_cvt(struct hda_codec *codec,
1043 hda_nid_t pin_nid,
1044 int dev_id, int mux_idx)
1045{
1046 struct hdmi_spec *spec = codec->spec;
1047 hda_nid_t nid;
1048 int cvt_idx, curr;
1049 struct hdmi_spec_per_cvt *per_cvt;
1050 struct hdmi_spec_per_pin *per_pin;
1051 int pin_idx;
1052
1053 /* configure the pins connections */
1054 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
1055 int dev_id_saved;
1056 int dev_num;
1057
1058 per_pin = get_pin(spec, pin_idx);
1059 /*
1060 * pin not connected to monitor
1061 * no need to operate on it
1062 */
1063 if (!per_pin->pcm)
1064 continue;
1065
1066 if ((per_pin->pin_nid == pin_nid) &&
1067 (per_pin->dev_id == dev_id))
1068 continue;
1069
1070 /*
1071 * if per_pin->dev_id >= dev_num,
1072 * snd_hda_get_dev_select() will fail,
1073 * and the following operation is unpredictable.
1074 * So skip this situation.
1075 */
1076 dev_num = snd_hda_get_num_devices(codec, per_pin->pin_nid) + 1;
1077 if (per_pin->dev_id >= dev_num)
1078 continue;
1079
1080 nid = per_pin->pin_nid;
1081
1082 /*
1083 * Calling this function should not impact
1084 * on the device entry selection
1085 * So let's save the dev id for each pin,
1086 * and restore it when return
1087 */
1088 dev_id_saved = snd_hda_get_dev_select(codec, nid);
1089 snd_hda_set_dev_select(codec, nid, per_pin->dev_id);
1090 curr = snd_hda_codec_read(codec, nid, 0,
1091 AC_VERB_GET_CONNECT_SEL, 0);
1092 if (curr != mux_idx) {
1093 snd_hda_set_dev_select(codec, nid, dev_id_saved);
1094 continue;
1095 }
1096
1097
1098 /* choose an unassigned converter. The conveters in the
1099 * connection list are in the same order as in the codec.
1100 */
1101 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) {
1102 per_cvt = get_cvt(spec, cvt_idx);
1103 if (!per_cvt->assigned) {
1104 codec_dbg(codec,
1105 "choose cvt %d for pin nid %d\n",
1106 cvt_idx, nid);
1107 snd_hda_codec_write_cache(codec, nid, 0,
1108 AC_VERB_SET_CONNECT_SEL,
1109 cvt_idx);
1110 break;
1111 }
1112 }
1113 snd_hda_set_dev_select(codec, nid, dev_id_saved);
1114 }
1115}
1116
1117/* A wrapper of intel_not_share_asigned_cvt() */
1118static void intel_not_share_assigned_cvt_nid(struct hda_codec *codec,
1119 hda_nid_t pin_nid, int dev_id, hda_nid_t cvt_nid)
1120{
1121 int mux_idx;
1122 struct hdmi_spec *spec = codec->spec;
1123
1124 /* On Intel platform, the mapping of converter nid to
1125 * mux index of the pins are always the same.
1126 * The pin nid may be 0, this means all pins will not
1127 * share the converter.
1128 */
1129 mux_idx = intel_cvt_id_to_mux_idx(spec, cvt_nid);
1130 if (mux_idx >= 0)
1131 intel_not_share_assigned_cvt(codec, pin_nid, dev_id, mux_idx);
1132}
1133
1134/* skeleton caller of pin_cvt_fixup ops */
1135static void pin_cvt_fixup(struct hda_codec *codec,
1136 struct hdmi_spec_per_pin *per_pin,
1137 hda_nid_t cvt_nid)
1138{
1139 struct hdmi_spec *spec = codec->spec;
1140
1141 if (spec->ops.pin_cvt_fixup)
1142 spec->ops.pin_cvt_fixup(codec, per_pin, cvt_nid);
1143}
1144
1145/* called in hdmi_pcm_open when no pin is assigned to the PCM
1146 * in dyn_pcm_assign mode.
1147 */
1148static int hdmi_pcm_open_no_pin(struct hda_pcm_stream *hinfo,
1149 struct hda_codec *codec,
1150 struct snd_pcm_substream *substream)
1151{
1152 struct hdmi_spec *spec = codec->spec;
1153 struct snd_pcm_runtime *runtime = substream->runtime;
1154 int cvt_idx, pcm_idx;
1155 struct hdmi_spec_per_cvt *per_cvt = NULL;
1156 int err;
1157
1158 pcm_idx = hinfo_to_pcm_index(codec, hinfo);
1159 if (pcm_idx < 0)
1160 return -EINVAL;
1161
1162 err = hdmi_choose_cvt(codec, -1, &cvt_idx);
1163 if (err)
1164 return err;
1165
1166 per_cvt = get_cvt(spec, cvt_idx);
1167 per_cvt->assigned = 1;
1168 hinfo->nid = per_cvt->cvt_nid;
1169
1170 pin_cvt_fixup(codec, NULL, per_cvt->cvt_nid);
1171
1172 set_bit(pcm_idx, &spec->pcm_in_use);
1173 /* todo: setup spdif ctls assign */
1174
1175 /* Initially set the converter's capabilities */
1176 hinfo->channels_min = per_cvt->channels_min;
1177 hinfo->channels_max = per_cvt->channels_max;
1178 hinfo->rates = per_cvt->rates;
1179 hinfo->formats = per_cvt->formats;
1180 hinfo->maxbps = per_cvt->maxbps;
1181
1182 /* Store the updated parameters */
1183 runtime->hw.channels_min = hinfo->channels_min;
1184 runtime->hw.channels_max = hinfo->channels_max;
1185 runtime->hw.formats = hinfo->formats;
1186 runtime->hw.rates = hinfo->rates;
1187
1188 snd_pcm_hw_constraint_step(substream->runtime, 0,
1189 SNDRV_PCM_HW_PARAM_CHANNELS, 2);
1190 return 0;
1191}
1192
1193/*
1194 * HDA PCM callbacks
1195 */
1196static int hdmi_pcm_open(struct hda_pcm_stream *hinfo,
1197 struct hda_codec *codec,
1198 struct snd_pcm_substream *substream)
1199{
1200 struct hdmi_spec *spec = codec->spec;
1201 struct snd_pcm_runtime *runtime = substream->runtime;
1202 int pin_idx, cvt_idx, pcm_idx;
1203 struct hdmi_spec_per_pin *per_pin;
1204 struct hdmi_eld *eld;
1205 struct hdmi_spec_per_cvt *per_cvt = NULL;
1206 int err;
1207
1208 /* Validate hinfo */
1209 pcm_idx = hinfo_to_pcm_index(codec, hinfo);
1210 if (pcm_idx < 0)
1211 return -EINVAL;
1212
1213 mutex_lock(&spec->pcm_lock);
1214 pin_idx = hinfo_to_pin_index(codec, hinfo);
1215 if (!spec->dyn_pcm_assign) {
1216 if (snd_BUG_ON(pin_idx < 0)) {
1217 err = -EINVAL;
1218 goto unlock;
1219 }
1220 } else {
1221 /* no pin is assigned to the PCM
1222 * PA need pcm open successfully when probe
1223 */
1224 if (pin_idx < 0) {
1225 err = hdmi_pcm_open_no_pin(hinfo, codec, substream);
1226 goto unlock;
1227 }
1228 }
1229
1230 err = hdmi_choose_cvt(codec, pin_idx, &cvt_idx);
1231 if (err < 0)
1232 goto unlock;
1233
1234 per_cvt = get_cvt(spec, cvt_idx);
1235 /* Claim converter */
1236 per_cvt->assigned = 1;
1237
1238 set_bit(pcm_idx, &spec->pcm_in_use);
1239 per_pin = get_pin(spec, pin_idx);
1240 per_pin->cvt_nid = per_cvt->cvt_nid;
1241 hinfo->nid = per_cvt->cvt_nid;
1242
1243 snd_hda_set_dev_select(codec, per_pin->pin_nid, per_pin->dev_id);
1244 snd_hda_codec_write_cache(codec, per_pin->pin_nid, 0,
1245 AC_VERB_SET_CONNECT_SEL,
1246 per_pin->mux_idx);
1247
1248 /* configure unused pins to choose other converters */
1249 pin_cvt_fixup(codec, per_pin, 0);
1250
1251 snd_hda_spdif_ctls_assign(codec, pcm_idx, per_cvt->cvt_nid);
1252
1253 /* Initially set the converter's capabilities */
1254 hinfo->channels_min = per_cvt->channels_min;
1255 hinfo->channels_max = per_cvt->channels_max;
1256 hinfo->rates = per_cvt->rates;
1257 hinfo->formats = per_cvt->formats;
1258 hinfo->maxbps = per_cvt->maxbps;
1259
1260 eld = &per_pin->sink_eld;
1261 /* Restrict capabilities by ELD if this isn't disabled */
1262 if (!static_hdmi_pcm && eld->eld_valid) {
1263 snd_hdmi_eld_update_pcm_info(&eld->info, hinfo);
1264 if (hinfo->channels_min > hinfo->channels_max ||
1265 !hinfo->rates || !hinfo->formats) {
1266 per_cvt->assigned = 0;
1267 hinfo->nid = 0;
1268 snd_hda_spdif_ctls_unassign(codec, pcm_idx);
1269 err = -ENODEV;
1270 goto unlock;
1271 }
1272 }
1273
1274 /* Store the updated parameters */
1275 runtime->hw.channels_min = hinfo->channels_min;
1276 runtime->hw.channels_max = hinfo->channels_max;
1277 runtime->hw.formats = hinfo->formats;
1278 runtime->hw.rates = hinfo->rates;
1279
1280 snd_pcm_hw_constraint_step(substream->runtime, 0,
1281 SNDRV_PCM_HW_PARAM_CHANNELS, 2);
1282 unlock:
1283 mutex_unlock(&spec->pcm_lock);
1284 return err;
1285}
1286
1287/*
1288 * HDA/HDMI auto parsing
1289 */
1290static int hdmi_read_pin_conn(struct hda_codec *codec, int pin_idx)
1291{
1292 struct hdmi_spec *spec = codec->spec;
1293 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
1294 hda_nid_t pin_nid = per_pin->pin_nid;
1295
1296 if (!(get_wcaps(codec, pin_nid) & AC_WCAP_CONN_LIST)) {
1297 codec_warn(codec,
1298 "HDMI: pin %d wcaps %#x does not support connection list\n",
1299 pin_nid, get_wcaps(codec, pin_nid));
1300 return -EINVAL;
1301 }
1302
1303 /* all the device entries on the same pin have the same conn list */
1304 per_pin->num_mux_nids = snd_hda_get_connections(codec, pin_nid,
1305 per_pin->mux_nids,
1306 HDA_MAX_CONNECTIONS);
1307
1308 return 0;
1309}
1310
1311static int hdmi_find_pcm_slot(struct hdmi_spec *spec,
1312 struct hdmi_spec_per_pin *per_pin)
1313{
1314 int i;
1315
1316 /* try the prefer PCM */
1317 if (!test_bit(per_pin->pin_nid_idx, &spec->pcm_bitmap))
1318 return per_pin->pin_nid_idx;
1319
1320 /* have a second try; check the "reserved area" over num_pins */
1321 for (i = spec->num_nids; i < spec->pcm_used; i++) {
1322 if (!test_bit(i, &spec->pcm_bitmap))
1323 return i;
1324 }
1325
1326 /* the last try; check the empty slots in pins */
1327 for (i = 0; i < spec->num_nids; i++) {
1328 if (!test_bit(i, &spec->pcm_bitmap))
1329 return i;
1330 }
1331 return -EBUSY;
1332}
1333
1334static void hdmi_attach_hda_pcm(struct hdmi_spec *spec,
1335 struct hdmi_spec_per_pin *per_pin)
1336{
1337 int idx;
1338
1339 /* pcm already be attached to the pin */
1340 if (per_pin->pcm)
1341 return;
1342 idx = hdmi_find_pcm_slot(spec, per_pin);
1343 if (idx == -EBUSY)
1344 return;
1345 per_pin->pcm_idx = idx;
1346 per_pin->pcm = get_hdmi_pcm(spec, idx);
1347 set_bit(idx, &spec->pcm_bitmap);
1348}
1349
1350static void hdmi_detach_hda_pcm(struct hdmi_spec *spec,
1351 struct hdmi_spec_per_pin *per_pin)
1352{
1353 int idx;
1354
1355 /* pcm already be detached from the pin */
1356 if (!per_pin->pcm)
1357 return;
1358 idx = per_pin->pcm_idx;
1359 per_pin->pcm_idx = -1;
1360 per_pin->pcm = NULL;
1361 if (idx >= 0 && idx < spec->pcm_used)
1362 clear_bit(idx, &spec->pcm_bitmap);
1363}
1364
1365static int hdmi_get_pin_cvt_mux(struct hdmi_spec *spec,
1366 struct hdmi_spec_per_pin *per_pin, hda_nid_t cvt_nid)
1367{
1368 int mux_idx;
1369
1370 for (mux_idx = 0; mux_idx < per_pin->num_mux_nids; mux_idx++)
1371 if (per_pin->mux_nids[mux_idx] == cvt_nid)
1372 break;
1373 return mux_idx;
1374}
1375
1376static bool check_non_pcm_per_cvt(struct hda_codec *codec, hda_nid_t cvt_nid);
1377
1378static void hdmi_pcm_setup_pin(struct hdmi_spec *spec,
1379 struct hdmi_spec_per_pin *per_pin)
1380{
1381 struct hda_codec *codec = per_pin->codec;
1382 struct hda_pcm *pcm;
1383 struct hda_pcm_stream *hinfo;
1384 struct snd_pcm_substream *substream;
1385 int mux_idx;
1386 bool non_pcm;
1387
1388 if (per_pin->pcm_idx >= 0 && per_pin->pcm_idx < spec->pcm_used)
1389 pcm = get_pcm_rec(spec, per_pin->pcm_idx);
1390 else
1391 return;
1392 if (!pcm->pcm)
1393 return;
1394 if (!test_bit(per_pin->pcm_idx, &spec->pcm_in_use))
1395 return;
1396
1397 /* hdmi audio only uses playback and one substream */
1398 hinfo = pcm->stream;
1399 substream = pcm->pcm->streams[0].substream;
1400
1401 per_pin->cvt_nid = hinfo->nid;
1402
1403 mux_idx = hdmi_get_pin_cvt_mux(spec, per_pin, hinfo->nid);
1404 if (mux_idx < per_pin->num_mux_nids) {
1405 snd_hda_set_dev_select(codec, per_pin->pin_nid,
1406 per_pin->dev_id);
1407 snd_hda_codec_write_cache(codec, per_pin->pin_nid, 0,
1408 AC_VERB_SET_CONNECT_SEL,
1409 mux_idx);
1410 }
1411 snd_hda_spdif_ctls_assign(codec, per_pin->pcm_idx, hinfo->nid);
1412
1413 non_pcm = check_non_pcm_per_cvt(codec, hinfo->nid);
1414 if (substream->runtime)
1415 per_pin->channels = substream->runtime->channels;
1416 per_pin->setup = true;
1417 per_pin->mux_idx = mux_idx;
1418
1419 hdmi_setup_audio_infoframe(codec, per_pin, non_pcm);
1420}
1421
1422static void hdmi_pcm_reset_pin(struct hdmi_spec *spec,
1423 struct hdmi_spec_per_pin *per_pin)
1424{
1425 if (per_pin->pcm_idx >= 0 && per_pin->pcm_idx < spec->pcm_used)
1426 snd_hda_spdif_ctls_unassign(per_pin->codec, per_pin->pcm_idx);
1427
1428 per_pin->chmap_set = false;
1429 memset(per_pin->chmap, 0, sizeof(per_pin->chmap));
1430
1431 per_pin->setup = false;
1432 per_pin->channels = 0;
1433}
1434
1435/* update per_pin ELD from the given new ELD;
1436 * setup info frame and notification accordingly
1437 */
1438static bool update_eld(struct hda_codec *codec,
1439 struct hdmi_spec_per_pin *per_pin,
1440 struct hdmi_eld *eld)
1441{
1442 struct hdmi_eld *pin_eld = &per_pin->sink_eld;
1443 struct hdmi_spec *spec = codec->spec;
1444 bool old_eld_valid = pin_eld->eld_valid;
1445 bool eld_changed;
1446 int pcm_idx;
1447
1448 /* for monitor disconnection, save pcm_idx firstly */
1449 pcm_idx = per_pin->pcm_idx;
1450 if (spec->dyn_pcm_assign) {
1451 if (eld->eld_valid) {
1452 hdmi_attach_hda_pcm(spec, per_pin);
1453 hdmi_pcm_setup_pin(spec, per_pin);
1454 } else {
1455 hdmi_pcm_reset_pin(spec, per_pin);
1456 hdmi_detach_hda_pcm(spec, per_pin);
1457 }
1458 }
1459 /* if pcm_idx == -1, it means this is in monitor connection event
1460 * we can get the correct pcm_idx now.
1461 */
1462 if (pcm_idx == -1)
1463 pcm_idx = per_pin->pcm_idx;
1464
1465 if (eld->eld_valid)
1466 snd_hdmi_show_eld(codec, &eld->info);
1467
1468 eld_changed = (pin_eld->eld_valid != eld->eld_valid);
1469 eld_changed |= (pin_eld->monitor_present != eld->monitor_present);
1470 if (!eld_changed && eld->eld_valid && pin_eld->eld_valid)
1471 if (pin_eld->eld_size != eld->eld_size ||
1472 memcmp(pin_eld->eld_buffer, eld->eld_buffer,
1473 eld->eld_size) != 0)
1474 eld_changed = true;
1475
1476 if (eld_changed) {
1477 pin_eld->monitor_present = eld->monitor_present;
1478 pin_eld->eld_valid = eld->eld_valid;
1479 pin_eld->eld_size = eld->eld_size;
1480 if (eld->eld_valid)
1481 memcpy(pin_eld->eld_buffer, eld->eld_buffer,
1482 eld->eld_size);
1483 pin_eld->info = eld->info;
1484 }
1485
1486 /*
1487 * Re-setup pin and infoframe. This is needed e.g. when
1488 * - sink is first plugged-in
1489 * - transcoder can change during stream playback on Haswell
1490 * and this can make HW reset converter selection on a pin.
1491 */
1492 if (eld->eld_valid && !old_eld_valid && per_pin->setup) {
1493 pin_cvt_fixup(codec, per_pin, 0);
1494 hdmi_setup_audio_infoframe(codec, per_pin, per_pin->non_pcm);
1495 }
1496
1497 if (eld_changed && pcm_idx >= 0)
1498 snd_ctl_notify(codec->card,
1499 SNDRV_CTL_EVENT_MASK_VALUE |
1500 SNDRV_CTL_EVENT_MASK_INFO,
1501 &get_hdmi_pcm(spec, pcm_idx)->eld_ctl->id);
1502 return eld_changed;
1503}
1504
1505/* update ELD and jack state via HD-audio verbs */
1506static bool hdmi_present_sense_via_verbs(struct hdmi_spec_per_pin *per_pin,
1507 int repoll)
1508{
1509 struct hda_jack_tbl *jack;
1510 struct hda_codec *codec = per_pin->codec;
1511 struct hdmi_spec *spec = codec->spec;
1512 struct hdmi_eld *eld = &spec->temp_eld;
1513 hda_nid_t pin_nid = per_pin->pin_nid;
1514 /*
1515 * Always execute a GetPinSense verb here, even when called from
1516 * hdmi_intrinsic_event; for some NVIDIA HW, the unsolicited
1517 * response's PD bit is not the real PD value, but indicates that
1518 * the real PD value changed. An older version of the HD-audio
1519 * specification worked this way. Hence, we just ignore the data in
1520 * the unsolicited response to avoid custom WARs.
1521 */
1522 int present;
1523 bool ret;
1524 bool do_repoll = false;
1525
1526 present = snd_hda_pin_sense(codec, pin_nid);
1527
1528 mutex_lock(&per_pin->lock);
1529 eld->monitor_present = !!(present & AC_PINSENSE_PRESENCE);
1530 if (eld->monitor_present)
1531 eld->eld_valid = !!(present & AC_PINSENSE_ELDV);
1532 else
1533 eld->eld_valid = false;
1534
1535 codec_dbg(codec,
1536 "HDMI status: Codec=%d Pin=%d Presence_Detect=%d ELD_Valid=%d\n",
1537 codec->addr, pin_nid, eld->monitor_present, eld->eld_valid);
1538
1539 if (eld->eld_valid) {
1540 if (spec->ops.pin_get_eld(codec, pin_nid, eld->eld_buffer,
1541 &eld->eld_size) < 0)
1542 eld->eld_valid = false;
1543 else {
1544 if (snd_hdmi_parse_eld(codec, &eld->info, eld->eld_buffer,
1545 eld->eld_size) < 0)
1546 eld->eld_valid = false;
1547 }
1548 if (!eld->eld_valid && repoll)
1549 do_repoll = true;
1550 }
1551
1552 if (do_repoll)
1553 schedule_delayed_work(&per_pin->work, msecs_to_jiffies(300));
1554 else
1555 update_eld(codec, per_pin, eld);
1556
1557 ret = !repoll || !eld->monitor_present || eld->eld_valid;
1558
1559 jack = snd_hda_jack_tbl_get(codec, pin_nid);
1560 if (jack) {
1561 jack->block_report = !ret;
1562 jack->pin_sense = (eld->monitor_present && eld->eld_valid) ?
1563 AC_PINSENSE_PRESENCE : 0;
1564 }
1565 mutex_unlock(&per_pin->lock);
1566 return ret;
1567}
1568
1569static struct snd_jack *pin_idx_to_jack(struct hda_codec *codec,
1570 struct hdmi_spec_per_pin *per_pin)
1571{
1572 struct hdmi_spec *spec = codec->spec;
1573 struct snd_jack *jack = NULL;
1574 struct hda_jack_tbl *jack_tbl;
1575
1576 /* if !dyn_pcm_assign, get jack from hda_jack_tbl
1577 * in !dyn_pcm_assign case, spec->pcm_rec[].jack is not
1578 * NULL even after snd_hda_jack_tbl_clear() is called to
1579 * free snd_jack. This may cause access invalid memory
1580 * when calling snd_jack_report
1581 */
1582 if (per_pin->pcm_idx >= 0 && spec->dyn_pcm_assign)
1583 jack = spec->pcm_rec[per_pin->pcm_idx].jack;
1584 else if (!spec->dyn_pcm_assign) {
1585 /*
1586 * jack tbl doesn't support DP MST
1587 * DP MST will use dyn_pcm_assign,
1588 * so DP MST will never come here
1589 */
1590 jack_tbl = snd_hda_jack_tbl_get(codec, per_pin->pin_nid);
1591 if (jack_tbl)
1592 jack = jack_tbl->jack;
1593 }
1594 return jack;
1595}
1596
1597/* update ELD and jack state via audio component */
1598static void sync_eld_via_acomp(struct hda_codec *codec,
1599 struct hdmi_spec_per_pin *per_pin)
1600{
1601 struct hdmi_spec *spec = codec->spec;
1602 struct hdmi_eld *eld = &spec->temp_eld;
1603 struct snd_jack *jack = NULL;
1604 bool changed;
1605 int size;
1606
1607 mutex_lock(&per_pin->lock);
1608 eld->monitor_present = false;
1609 size = snd_hdac_acomp_get_eld(&codec->core, per_pin->pin_nid,
1610 per_pin->dev_id, &eld->monitor_present,
1611 eld->eld_buffer, ELD_MAX_SIZE);
1612 if (size > 0) {
1613 size = min(size, ELD_MAX_SIZE);
1614 if (snd_hdmi_parse_eld(codec, &eld->info,
1615 eld->eld_buffer, size) < 0)
1616 size = -EINVAL;
1617 }
1618
1619 if (size > 0) {
1620 eld->eld_valid = true;
1621 eld->eld_size = size;
1622 } else {
1623 eld->eld_valid = false;
1624 eld->eld_size = 0;
1625 }
1626
1627 /* pcm_idx >=0 before update_eld() means it is in monitor
1628 * disconnected event. Jack must be fetched before update_eld()
1629 */
1630 jack = pin_idx_to_jack(codec, per_pin);
1631 changed = update_eld(codec, per_pin, eld);
1632 if (jack == NULL)
1633 jack = pin_idx_to_jack(codec, per_pin);
1634 if (changed && jack)
1635 snd_jack_report(jack,
1636 (eld->monitor_present && eld->eld_valid) ?
1637 SND_JACK_AVOUT : 0);
1638 mutex_unlock(&per_pin->lock);
1639}
1640
1641static bool hdmi_present_sense(struct hdmi_spec_per_pin *per_pin, int repoll)
1642{
1643 struct hda_codec *codec = per_pin->codec;
1644 int ret;
1645
1646 /* no temporary power up/down needed for component notifier */
1647 if (!codec_has_acomp(codec)) {
1648 ret = snd_hda_power_up_pm(codec);
1649 if (ret < 0 && pm_runtime_suspended(hda_codec_dev(codec))) {
1650 snd_hda_power_down_pm(codec);
1651 return false;
1652 }
1653 ret = hdmi_present_sense_via_verbs(per_pin, repoll);
1654 snd_hda_power_down_pm(codec);
1655 } else {
1656 sync_eld_via_acomp(codec, per_pin);
1657 ret = false; /* don't call snd_hda_jack_report_sync() */
1658 }
1659
1660 return ret;
1661}
1662
1663static void hdmi_repoll_eld(struct work_struct *work)
1664{
1665 struct hdmi_spec_per_pin *per_pin =
1666 container_of(to_delayed_work(work), struct hdmi_spec_per_pin, work);
1667 struct hda_codec *codec = per_pin->codec;
1668 struct hdmi_spec *spec = codec->spec;
1669 struct hda_jack_tbl *jack;
1670
1671 jack = snd_hda_jack_tbl_get(codec, per_pin->pin_nid);
1672 if (jack)
1673 jack->jack_dirty = 1;
1674
1675 if (per_pin->repoll_count++ > 6)
1676 per_pin->repoll_count = 0;
1677
1678 mutex_lock(&spec->pcm_lock);
1679 if (hdmi_present_sense(per_pin, per_pin->repoll_count))
1680 snd_hda_jack_report_sync(per_pin->codec);
1681 mutex_unlock(&spec->pcm_lock);
1682}
1683
1684static void intel_haswell_fixup_connect_list(struct hda_codec *codec,
1685 hda_nid_t nid);
1686
1687static int hdmi_add_pin(struct hda_codec *codec, hda_nid_t pin_nid)
1688{
1689 struct hdmi_spec *spec = codec->spec;
1690 unsigned int caps, config;
1691 int pin_idx;
1692 struct hdmi_spec_per_pin *per_pin;
1693 int err;
1694 int dev_num, i;
1695
1696 caps = snd_hda_query_pin_caps(codec, pin_nid);
1697 if (!(caps & (AC_PINCAP_HDMI | AC_PINCAP_DP)))
1698 return 0;
1699
1700 /*
1701 * For DP MST audio, Configuration Default is the same for
1702 * all device entries on the same pin
1703 */
1704 config = snd_hda_codec_get_pincfg(codec, pin_nid);
1705 if (get_defcfg_connect(config) == AC_JACK_PORT_NONE)
1706 return 0;
1707
1708 /*
1709 * To simplify the implementation, malloc all
1710 * the virtual pins in the initialization statically
1711 */
1712 if (is_haswell_plus(codec)) {
1713 /*
1714 * On Intel platforms, device entries number is
1715 * changed dynamically. If there is a DP MST
1716 * hub connected, the device entries number is 3.
1717 * Otherwise, it is 1.
1718 * Here we manually set dev_num to 3, so that
1719 * we can initialize all the device entries when
1720 * bootup statically.
1721 */
1722 dev_num = 3;
1723 spec->dev_num = 3;
1724 } else if (spec->dyn_pcm_assign && codec->dp_mst) {
1725 dev_num = snd_hda_get_num_devices(codec, pin_nid) + 1;
1726 /*
1727 * spec->dev_num is the maxinum number of device entries
1728 * among all the pins
1729 */
1730 spec->dev_num = (spec->dev_num > dev_num) ?
1731 spec->dev_num : dev_num;
1732 } else {
1733 /*
1734 * If the platform doesn't support DP MST,
1735 * manually set dev_num to 1. This means
1736 * the pin has only one device entry.
1737 */
1738 dev_num = 1;
1739 spec->dev_num = 1;
1740 }
1741
1742 for (i = 0; i < dev_num; i++) {
1743 pin_idx = spec->num_pins;
1744 per_pin = snd_array_new(&spec->pins);
1745
1746 if (!per_pin)
1747 return -ENOMEM;
1748
1749 if (spec->dyn_pcm_assign) {
1750 per_pin->pcm = NULL;
1751 per_pin->pcm_idx = -1;
1752 } else {
1753 per_pin->pcm = get_hdmi_pcm(spec, pin_idx);
1754 per_pin->pcm_idx = pin_idx;
1755 }
1756 per_pin->pin_nid = pin_nid;
1757 per_pin->pin_nid_idx = spec->num_nids;
1758 per_pin->dev_id = i;
1759 per_pin->non_pcm = false;
1760 snd_hda_set_dev_select(codec, pin_nid, i);
1761 if (is_haswell_plus(codec))
1762 intel_haswell_fixup_connect_list(codec, pin_nid);
1763 err = hdmi_read_pin_conn(codec, pin_idx);
1764 if (err < 0)
1765 return err;
1766 spec->num_pins++;
1767 }
1768 spec->num_nids++;
1769
1770 return 0;
1771}
1772
1773static int hdmi_add_cvt(struct hda_codec *codec, hda_nid_t cvt_nid)
1774{
1775 struct hdmi_spec *spec = codec->spec;
1776 struct hdmi_spec_per_cvt *per_cvt;
1777 unsigned int chans;
1778 int err;
1779
1780 chans = get_wcaps(codec, cvt_nid);
1781 chans = get_wcaps_channels(chans);
1782
1783 per_cvt = snd_array_new(&spec->cvts);
1784 if (!per_cvt)
1785 return -ENOMEM;
1786
1787 per_cvt->cvt_nid = cvt_nid;
1788 per_cvt->channels_min = 2;
1789 if (chans <= 16) {
1790 per_cvt->channels_max = chans;
1791 if (chans > spec->chmap.channels_max)
1792 spec->chmap.channels_max = chans;
1793 }
1794
1795 err = snd_hda_query_supported_pcm(codec, cvt_nid,
1796 &per_cvt->rates,
1797 &per_cvt->formats,
1798 &per_cvt->maxbps);
1799 if (err < 0)
1800 return err;
1801
1802 if (spec->num_cvts < ARRAY_SIZE(spec->cvt_nids))
1803 spec->cvt_nids[spec->num_cvts] = cvt_nid;
1804 spec->num_cvts++;
1805
1806 return 0;
1807}
1808
1809static int hdmi_parse_codec(struct hda_codec *codec)
1810{
1811 hda_nid_t nid;
1812 int i, nodes;
1813
1814 nodes = snd_hda_get_sub_nodes(codec, codec->core.afg, &nid);
1815 if (!nid || nodes < 0) {
1816 codec_warn(codec, "HDMI: failed to get afg sub nodes\n");
1817 return -EINVAL;
1818 }
1819
1820 for (i = 0; i < nodes; i++, nid++) {
1821 unsigned int caps;
1822 unsigned int type;
1823
1824 caps = get_wcaps(codec, nid);
1825 type = get_wcaps_type(caps);
1826
1827 if (!(caps & AC_WCAP_DIGITAL))
1828 continue;
1829
1830 switch (type) {
1831 case AC_WID_AUD_OUT:
1832 hdmi_add_cvt(codec, nid);
1833 break;
1834 case AC_WID_PIN:
1835 hdmi_add_pin(codec, nid);
1836 break;
1837 }
1838 }
1839
1840 return 0;
1841}
1842
1843/*
1844 */
1845static bool check_non_pcm_per_cvt(struct hda_codec *codec, hda_nid_t cvt_nid)
1846{
1847 struct hda_spdif_out *spdif;
1848 bool non_pcm;
1849
1850 mutex_lock(&codec->spdif_mutex);
1851 spdif = snd_hda_spdif_out_of_nid(codec, cvt_nid);
1852 /* Add sanity check to pass klockwork check.
1853 * This should never happen.
1854 */
1855 if (WARN_ON(spdif == NULL))
1856 return true;
1857 non_pcm = !!(spdif->status & IEC958_AES0_NONAUDIO);
1858 mutex_unlock(&codec->spdif_mutex);
1859 return non_pcm;
1860}
1861
1862/*
1863 * HDMI callbacks
1864 */
1865
1866static int generic_hdmi_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
1867 struct hda_codec *codec,
1868 unsigned int stream_tag,
1869 unsigned int format,
1870 struct snd_pcm_substream *substream)
1871{
1872 hda_nid_t cvt_nid = hinfo->nid;
1873 struct hdmi_spec *spec = codec->spec;
1874 int pin_idx;
1875 struct hdmi_spec_per_pin *per_pin;
1876 hda_nid_t pin_nid;
1877 struct snd_pcm_runtime *runtime = substream->runtime;
1878 bool non_pcm;
1879 int pinctl, stripe;
1880 int err = 0;
1881
1882 mutex_lock(&spec->pcm_lock);
1883 pin_idx = hinfo_to_pin_index(codec, hinfo);
1884 if (spec->dyn_pcm_assign && pin_idx < 0) {
1885 /* when dyn_pcm_assign and pcm is not bound to a pin
1886 * skip pin setup and return 0 to make audio playback
1887 * be ongoing
1888 */
1889 pin_cvt_fixup(codec, NULL, cvt_nid);
1890 snd_hda_codec_setup_stream(codec, cvt_nid,
1891 stream_tag, 0, format);
1892 goto unlock;
1893 }
1894
1895 if (snd_BUG_ON(pin_idx < 0)) {
1896 err = -EINVAL;
1897 goto unlock;
1898 }
1899 per_pin = get_pin(spec, pin_idx);
1900 pin_nid = per_pin->pin_nid;
1901
1902 /* Verify pin:cvt selections to avoid silent audio after S3.
1903 * After S3, the audio driver restores pin:cvt selections
1904 * but this can happen before gfx is ready and such selection
1905 * is overlooked by HW. Thus multiple pins can share a same
1906 * default convertor and mute control will affect each other,
1907 * which can cause a resumed audio playback become silent
1908 * after S3.
1909 */
1910 pin_cvt_fixup(codec, per_pin, 0);
1911
1912 /* Call sync_audio_rate to set the N/CTS/M manually if necessary */
1913 /* Todo: add DP1.2 MST audio support later */
1914 if (codec_has_acomp(codec))
1915 snd_hdac_sync_audio_rate(&codec->core, pin_nid, per_pin->dev_id,
1916 runtime->rate);
1917
1918 non_pcm = check_non_pcm_per_cvt(codec, cvt_nid);
1919 mutex_lock(&per_pin->lock);
1920 per_pin->channels = substream->runtime->channels;
1921 per_pin->setup = true;
1922
1923 if (get_wcaps(codec, cvt_nid) & AC_WCAP_STRIPE) {
1924 stripe = snd_hdac_get_stream_stripe_ctl(&codec->bus->core,
1925 substream);
1926 snd_hda_codec_write(codec, cvt_nid, 0,
1927 AC_VERB_SET_STRIPE_CONTROL,
1928 stripe);
1929 }
1930
1931 hdmi_setup_audio_infoframe(codec, per_pin, non_pcm);
1932 mutex_unlock(&per_pin->lock);
1933 if (spec->dyn_pin_out) {
1934 pinctl = snd_hda_codec_read(codec, pin_nid, 0,
1935 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
1936 snd_hda_codec_write(codec, pin_nid, 0,
1937 AC_VERB_SET_PIN_WIDGET_CONTROL,
1938 pinctl | PIN_OUT);
1939 }
1940
1941 /* snd_hda_set_dev_select() has been called before */
1942 err = spec->ops.setup_stream(codec, cvt_nid, pin_nid,
1943 stream_tag, format);
1944 unlock:
1945 mutex_unlock(&spec->pcm_lock);
1946 return err;
1947}
1948
1949static int generic_hdmi_playback_pcm_cleanup(struct hda_pcm_stream *hinfo,
1950 struct hda_codec *codec,
1951 struct snd_pcm_substream *substream)
1952{
1953 snd_hda_codec_cleanup_stream(codec, hinfo->nid);
1954 return 0;
1955}
1956
1957static int hdmi_pcm_close(struct hda_pcm_stream *hinfo,
1958 struct hda_codec *codec,
1959 struct snd_pcm_substream *substream)
1960{
1961 struct hdmi_spec *spec = codec->spec;
1962 int cvt_idx, pin_idx, pcm_idx;
1963 struct hdmi_spec_per_cvt *per_cvt;
1964 struct hdmi_spec_per_pin *per_pin;
1965 int pinctl;
1966 int err = 0;
1967
1968 if (hinfo->nid) {
1969 pcm_idx = hinfo_to_pcm_index(codec, hinfo);
1970 if (snd_BUG_ON(pcm_idx < 0))
1971 return -EINVAL;
1972 cvt_idx = cvt_nid_to_cvt_index(codec, hinfo->nid);
1973 if (snd_BUG_ON(cvt_idx < 0))
1974 return -EINVAL;
1975 per_cvt = get_cvt(spec, cvt_idx);
1976
1977 snd_BUG_ON(!per_cvt->assigned);
1978 per_cvt->assigned = 0;
1979 hinfo->nid = 0;
1980
1981 mutex_lock(&spec->pcm_lock);
1982 snd_hda_spdif_ctls_unassign(codec, pcm_idx);
1983 clear_bit(pcm_idx, &spec->pcm_in_use);
1984 pin_idx = hinfo_to_pin_index(codec, hinfo);
1985 if (spec->dyn_pcm_assign && pin_idx < 0)
1986 goto unlock;
1987
1988 if (snd_BUG_ON(pin_idx < 0)) {
1989 err = -EINVAL;
1990 goto unlock;
1991 }
1992 per_pin = get_pin(spec, pin_idx);
1993
1994 if (spec->dyn_pin_out) {
1995 pinctl = snd_hda_codec_read(codec, per_pin->pin_nid, 0,
1996 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
1997 snd_hda_codec_write(codec, per_pin->pin_nid, 0,
1998 AC_VERB_SET_PIN_WIDGET_CONTROL,
1999 pinctl & ~PIN_OUT);
2000 }
2001
2002 mutex_lock(&per_pin->lock);
2003 per_pin->chmap_set = false;
2004 memset(per_pin->chmap, 0, sizeof(per_pin->chmap));
2005
2006 per_pin->setup = false;
2007 per_pin->channels = 0;
2008 mutex_unlock(&per_pin->lock);
2009 unlock:
2010 mutex_unlock(&spec->pcm_lock);
2011 }
2012
2013 return err;
2014}
2015
2016static const struct hda_pcm_ops generic_ops = {
2017 .open = hdmi_pcm_open,
2018 .close = hdmi_pcm_close,
2019 .prepare = generic_hdmi_playback_pcm_prepare,
2020 .cleanup = generic_hdmi_playback_pcm_cleanup,
2021};
2022
2023static int hdmi_get_spk_alloc(struct hdac_device *hdac, int pcm_idx)
2024{
2025 struct hda_codec *codec = container_of(hdac, struct hda_codec, core);
2026 struct hdmi_spec *spec = codec->spec;
2027 struct hdmi_spec_per_pin *per_pin = pcm_idx_to_pin(spec, pcm_idx);
2028
2029 if (!per_pin)
2030 return 0;
2031
2032 return per_pin->sink_eld.info.spk_alloc;
2033}
2034
2035static void hdmi_get_chmap(struct hdac_device *hdac, int pcm_idx,
2036 unsigned char *chmap)
2037{
2038 struct hda_codec *codec = container_of(hdac, struct hda_codec, core);
2039 struct hdmi_spec *spec = codec->spec;
2040 struct hdmi_spec_per_pin *per_pin = pcm_idx_to_pin(spec, pcm_idx);
2041
2042 /* chmap is already set to 0 in caller */
2043 if (!per_pin)
2044 return;
2045
2046 memcpy(chmap, per_pin->chmap, ARRAY_SIZE(per_pin->chmap));
2047}
2048
2049static void hdmi_set_chmap(struct hdac_device *hdac, int pcm_idx,
2050 unsigned char *chmap, int prepared)
2051{
2052 struct hda_codec *codec = container_of(hdac, struct hda_codec, core);
2053 struct hdmi_spec *spec = codec->spec;
2054 struct hdmi_spec_per_pin *per_pin = pcm_idx_to_pin(spec, pcm_idx);
2055
2056 if (!per_pin)
2057 return;
2058 mutex_lock(&per_pin->lock);
2059 per_pin->chmap_set = true;
2060 memcpy(per_pin->chmap, chmap, ARRAY_SIZE(per_pin->chmap));
2061 if (prepared)
2062 hdmi_setup_audio_infoframe(codec, per_pin, per_pin->non_pcm);
2063 mutex_unlock(&per_pin->lock);
2064}
2065
2066static bool is_hdmi_pcm_attached(struct hdac_device *hdac, int pcm_idx)
2067{
2068 struct hda_codec *codec = container_of(hdac, struct hda_codec, core);
2069 struct hdmi_spec *spec = codec->spec;
2070 struct hdmi_spec_per_pin *per_pin = pcm_idx_to_pin(spec, pcm_idx);
2071
2072 return per_pin ? true:false;
2073}
2074
2075static int generic_hdmi_build_pcms(struct hda_codec *codec)
2076{
2077 struct hdmi_spec *spec = codec->spec;
2078 int idx;
2079
2080 /*
2081 * for non-mst mode, pcm number is the same as before
2082 * for DP MST mode, pcm number is (nid number + dev_num - 1)
2083 * dev_num is the device entry number in a pin
2084 *
2085 */
2086 for (idx = 0; idx < spec->num_nids + spec->dev_num - 1; idx++) {
2087 struct hda_pcm *info;
2088 struct hda_pcm_stream *pstr;
2089
2090 info = snd_hda_codec_pcm_new(codec, "HDMI %d", idx);
2091 if (!info)
2092 return -ENOMEM;
2093
2094 spec->pcm_rec[idx].pcm = info;
2095 spec->pcm_used++;
2096 info->pcm_type = HDA_PCM_TYPE_HDMI;
2097 info->own_chmap = true;
2098
2099 pstr = &info->stream[SNDRV_PCM_STREAM_PLAYBACK];
2100 pstr->substreams = 1;
2101 pstr->ops = generic_ops;
2102 /* pcm number is less than 16 */
2103 if (spec->pcm_used >= 16)
2104 break;
2105 /* other pstr fields are set in open */
2106 }
2107
2108 return 0;
2109}
2110
2111static void free_hdmi_jack_priv(struct snd_jack *jack)
2112{
2113 struct hdmi_pcm *pcm = jack->private_data;
2114
2115 pcm->jack = NULL;
2116}
2117
2118static int add_hdmi_jack_kctl(struct hda_codec *codec,
2119 struct hdmi_spec *spec,
2120 int pcm_idx,
2121 const char *name)
2122{
2123 struct snd_jack *jack;
2124 int err;
2125
2126 err = snd_jack_new(codec->card, name, SND_JACK_AVOUT, &jack,
2127 true, false);
2128 if (err < 0)
2129 return err;
2130
2131 spec->pcm_rec[pcm_idx].jack = jack;
2132 jack->private_data = &spec->pcm_rec[pcm_idx];
2133 jack->private_free = free_hdmi_jack_priv;
2134 return 0;
2135}
2136
2137static int generic_hdmi_build_jack(struct hda_codec *codec, int pcm_idx)
2138{
2139 char hdmi_str[32] = "HDMI/DP";
2140 struct hdmi_spec *spec = codec->spec;
2141 struct hdmi_spec_per_pin *per_pin;
2142 struct hda_jack_tbl *jack;
2143 int pcmdev = get_pcm_rec(spec, pcm_idx)->device;
2144 bool phantom_jack;
2145 int ret;
2146
2147 if (pcmdev > 0)
2148 sprintf(hdmi_str + strlen(hdmi_str), ",pcm=%d", pcmdev);
2149
2150 if (spec->dyn_pcm_assign)
2151 return add_hdmi_jack_kctl(codec, spec, pcm_idx, hdmi_str);
2152
2153 /* for !dyn_pcm_assign, we still use hda_jack for compatibility */
2154 /* if !dyn_pcm_assign, it must be non-MST mode.
2155 * This means pcms and pins are statically mapped.
2156 * And pcm_idx is pin_idx.
2157 */
2158 per_pin = get_pin(spec, pcm_idx);
2159 phantom_jack = !is_jack_detectable(codec, per_pin->pin_nid);
2160 if (phantom_jack)
2161 strncat(hdmi_str, " Phantom",
2162 sizeof(hdmi_str) - strlen(hdmi_str) - 1);
2163 ret = snd_hda_jack_add_kctl(codec, per_pin->pin_nid, hdmi_str,
2164 phantom_jack, 0, NULL);
2165 if (ret < 0)
2166 return ret;
2167 jack = snd_hda_jack_tbl_get(codec, per_pin->pin_nid);
2168 if (jack == NULL)
2169 return 0;
2170 /* assign jack->jack to pcm_rec[].jack to
2171 * align with dyn_pcm_assign mode
2172 */
2173 spec->pcm_rec[pcm_idx].jack = jack->jack;
2174 return 0;
2175}
2176
2177static int generic_hdmi_build_controls(struct hda_codec *codec)
2178{
2179 struct hdmi_spec *spec = codec->spec;
2180 int dev, err;
2181 int pin_idx, pcm_idx;
2182
2183 for (pcm_idx = 0; pcm_idx < spec->pcm_used; pcm_idx++) {
2184 if (!get_pcm_rec(spec, pcm_idx)->pcm) {
2185 /* no PCM: mark this for skipping permanently */
2186 set_bit(pcm_idx, &spec->pcm_bitmap);
2187 continue;
2188 }
2189
2190 err = generic_hdmi_build_jack(codec, pcm_idx);
2191 if (err < 0)
2192 return err;
2193
2194 /* create the spdif for each pcm
2195 * pin will be bound when monitor is connected
2196 */
2197 if (spec->dyn_pcm_assign)
2198 err = snd_hda_create_dig_out_ctls(codec,
2199 0, spec->cvt_nids[0],
2200 HDA_PCM_TYPE_HDMI);
2201 else {
2202 struct hdmi_spec_per_pin *per_pin =
2203 get_pin(spec, pcm_idx);
2204 err = snd_hda_create_dig_out_ctls(codec,
2205 per_pin->pin_nid,
2206 per_pin->mux_nids[0],
2207 HDA_PCM_TYPE_HDMI);
2208 }
2209 if (err < 0)
2210 return err;
2211 snd_hda_spdif_ctls_unassign(codec, pcm_idx);
2212
2213 dev = get_pcm_rec(spec, pcm_idx)->device;
2214 if (dev != SNDRV_PCM_INVALID_DEVICE) {
2215 /* add control for ELD Bytes */
2216 err = hdmi_create_eld_ctl(codec, pcm_idx, dev);
2217 if (err < 0)
2218 return err;
2219 }
2220 }
2221
2222 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2223 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2224
2225 hdmi_present_sense(per_pin, 0);
2226 }
2227
2228 /* add channel maps */
2229 for (pcm_idx = 0; pcm_idx < spec->pcm_used; pcm_idx++) {
2230 struct hda_pcm *pcm;
2231
2232 pcm = get_pcm_rec(spec, pcm_idx);
2233 if (!pcm || !pcm->pcm)
2234 break;
2235 err = snd_hdac_add_chmap_ctls(pcm->pcm, pcm_idx, &spec->chmap);
2236 if (err < 0)
2237 return err;
2238 }
2239
2240 return 0;
2241}
2242
2243static int generic_hdmi_init_per_pins(struct hda_codec *codec)
2244{
2245 struct hdmi_spec *spec = codec->spec;
2246 int pin_idx;
2247
2248 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2249 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2250
2251 per_pin->codec = codec;
2252 mutex_init(&per_pin->lock);
2253 INIT_DELAYED_WORK(&per_pin->work, hdmi_repoll_eld);
2254 eld_proc_new(per_pin, pin_idx);
2255 }
2256 return 0;
2257}
2258
2259static int generic_hdmi_init(struct hda_codec *codec)
2260{
2261 struct hdmi_spec *spec = codec->spec;
2262 int pin_idx;
2263
2264 mutex_lock(&spec->bind_lock);
2265 spec->use_jack_detect = !codec->jackpoll_interval;
2266 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2267 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2268 hda_nid_t pin_nid = per_pin->pin_nid;
2269 int dev_id = per_pin->dev_id;
2270
2271 snd_hda_set_dev_select(codec, pin_nid, dev_id);
2272 hdmi_init_pin(codec, pin_nid);
2273 if (codec_has_acomp(codec))
2274 continue;
2275 if (spec->use_jack_detect)
2276 snd_hda_jack_detect_enable(codec, pin_nid);
2277 else
2278 snd_hda_jack_detect_enable_callback(codec, pin_nid,
2279 jack_callback);
2280 }
2281 mutex_unlock(&spec->bind_lock);
2282 return 0;
2283}
2284
2285static void hdmi_array_init(struct hdmi_spec *spec, int nums)
2286{
2287 snd_array_init(&spec->pins, sizeof(struct hdmi_spec_per_pin), nums);
2288 snd_array_init(&spec->cvts, sizeof(struct hdmi_spec_per_cvt), nums);
2289}
2290
2291static void hdmi_array_free(struct hdmi_spec *spec)
2292{
2293 snd_array_free(&spec->pins);
2294 snd_array_free(&spec->cvts);
2295}
2296
2297static void generic_spec_free(struct hda_codec *codec)
2298{
2299 struct hdmi_spec *spec = codec->spec;
2300
2301 if (spec) {
2302 hdmi_array_free(spec);
2303 kfree(spec);
2304 codec->spec = NULL;
2305 }
2306 codec->dp_mst = false;
2307}
2308
2309static void generic_hdmi_free(struct hda_codec *codec)
2310{
2311 struct hdmi_spec *spec = codec->spec;
2312 int pin_idx, pcm_idx;
2313
2314 if (spec->acomp_registered) {
2315 snd_hdac_acomp_exit(&codec->bus->core);
2316 } else if (codec_has_acomp(codec)) {
2317 snd_hdac_acomp_register_notifier(&codec->bus->core, NULL);
2318 codec->relaxed_resume = 0;
2319 }
2320
2321 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2322 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2323 cancel_delayed_work_sync(&per_pin->work);
2324 eld_proc_free(per_pin);
2325 }
2326
2327 for (pcm_idx = 0; pcm_idx < spec->pcm_used; pcm_idx++) {
2328 if (spec->pcm_rec[pcm_idx].jack == NULL)
2329 continue;
2330 if (spec->dyn_pcm_assign)
2331 snd_device_free(codec->card,
2332 spec->pcm_rec[pcm_idx].jack);
2333 else
2334 spec->pcm_rec[pcm_idx].jack = NULL;
2335 }
2336
2337 generic_spec_free(codec);
2338}
2339
2340#ifdef CONFIG_PM
2341static int generic_hdmi_resume(struct hda_codec *codec)
2342{
2343 struct hdmi_spec *spec = codec->spec;
2344 int pin_idx;
2345
2346 codec->patch_ops.init(codec);
2347 regcache_sync(codec->core.regmap);
2348
2349 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2350 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2351 hdmi_present_sense(per_pin, 1);
2352 }
2353 return 0;
2354}
2355#endif
2356
2357static const struct hda_codec_ops generic_hdmi_patch_ops = {
2358 .init = generic_hdmi_init,
2359 .free = generic_hdmi_free,
2360 .build_pcms = generic_hdmi_build_pcms,
2361 .build_controls = generic_hdmi_build_controls,
2362 .unsol_event = hdmi_unsol_event,
2363#ifdef CONFIG_PM
2364 .resume = generic_hdmi_resume,
2365#endif
2366};
2367
2368static const struct hdmi_ops generic_standard_hdmi_ops = {
2369 .pin_get_eld = snd_hdmi_get_eld,
2370 .pin_setup_infoframe = hdmi_pin_setup_infoframe,
2371 .pin_hbr_setup = hdmi_pin_hbr_setup,
2372 .setup_stream = hdmi_setup_stream,
2373};
2374
2375/* allocate codec->spec and assign/initialize generic parser ops */
2376static int alloc_generic_hdmi(struct hda_codec *codec)
2377{
2378 struct hdmi_spec *spec;
2379
2380 spec = kzalloc(sizeof(*spec), GFP_KERNEL);
2381 if (!spec)
2382 return -ENOMEM;
2383
2384 spec->codec = codec;
2385 spec->ops = generic_standard_hdmi_ops;
2386 spec->dev_num = 1; /* initialize to 1 */
2387 mutex_init(&spec->pcm_lock);
2388 mutex_init(&spec->bind_lock);
2389 snd_hdac_register_chmap_ops(&codec->core, &spec->chmap);
2390
2391 spec->chmap.ops.get_chmap = hdmi_get_chmap;
2392 spec->chmap.ops.set_chmap = hdmi_set_chmap;
2393 spec->chmap.ops.is_pcm_attached = is_hdmi_pcm_attached;
2394 spec->chmap.ops.get_spk_alloc = hdmi_get_spk_alloc,
2395
2396 codec->spec = spec;
2397 hdmi_array_init(spec, 4);
2398
2399 codec->patch_ops = generic_hdmi_patch_ops;
2400
2401 return 0;
2402}
2403
2404/* generic HDMI parser */
2405static int patch_generic_hdmi(struct hda_codec *codec)
2406{
2407 int err;
2408
2409 err = alloc_generic_hdmi(codec);
2410 if (err < 0)
2411 return err;
2412
2413 err = hdmi_parse_codec(codec);
2414 if (err < 0) {
2415 generic_spec_free(codec);
2416 return err;
2417 }
2418
2419 generic_hdmi_init_per_pins(codec);
2420 return 0;
2421}
2422
2423/*
2424 * generic audio component binding
2425 */
2426
2427/* turn on / off the unsol event jack detection dynamically */
2428static void reprogram_jack_detect(struct hda_codec *codec, hda_nid_t nid,
2429 bool use_acomp)
2430{
2431 struct hda_jack_tbl *tbl;
2432
2433 tbl = snd_hda_jack_tbl_get(codec, nid);
2434 if (tbl) {
2435 /* clear unsol even if component notifier is used, or re-enable
2436 * if notifier is cleared
2437 */
2438 unsigned int val = use_acomp ? 0 : (AC_USRSP_EN | tbl->tag);
2439 snd_hda_codec_write_cache(codec, nid, 0,
2440 AC_VERB_SET_UNSOLICITED_ENABLE, val);
2441 } else {
2442 /* if no jack entry was defined beforehand, create a new one
2443 * at need (i.e. only when notifier is cleared)
2444 */
2445 if (!use_acomp)
2446 snd_hda_jack_detect_enable(codec, nid);
2447 }
2448}
2449
2450/* set up / clear component notifier dynamically */
2451static void generic_acomp_notifier_set(struct drm_audio_component *acomp,
2452 bool use_acomp)
2453{
2454 struct hdmi_spec *spec;
2455 int i;
2456
2457 spec = container_of(acomp->audio_ops, struct hdmi_spec, drm_audio_ops);
2458 mutex_lock(&spec->bind_lock);
2459 spec->use_acomp_notifier = use_acomp;
2460 spec->codec->relaxed_resume = use_acomp;
2461 /* reprogram each jack detection logic depending on the notifier */
2462 if (spec->use_jack_detect) {
2463 for (i = 0; i < spec->num_pins; i++)
2464 reprogram_jack_detect(spec->codec,
2465 get_pin(spec, i)->pin_nid,
2466 use_acomp);
2467 }
2468 mutex_unlock(&spec->bind_lock);
2469}
2470
2471/* enable / disable the notifier via master bind / unbind */
2472static int generic_acomp_master_bind(struct device *dev,
2473 struct drm_audio_component *acomp)
2474{
2475 generic_acomp_notifier_set(acomp, true);
2476 return 0;
2477}
2478
2479static void generic_acomp_master_unbind(struct device *dev,
2480 struct drm_audio_component *acomp)
2481{
2482 generic_acomp_notifier_set(acomp, false);
2483}
2484
2485/* check whether both HD-audio and DRM PCI devices belong to the same bus */
2486static int match_bound_vga(struct device *dev, int subtype, void *data)
2487{
2488 struct hdac_bus *bus = data;
2489 struct pci_dev *pci, *master;
2490
2491 if (!dev_is_pci(dev) || !dev_is_pci(bus->dev))
2492 return 0;
2493 master = to_pci_dev(bus->dev);
2494 pci = to_pci_dev(dev);
2495 return master->bus == pci->bus;
2496}
2497
2498/* audio component notifier for AMD/Nvidia HDMI codecs */
2499static void generic_acomp_pin_eld_notify(void *audio_ptr, int port, int dev_id)
2500{
2501 struct hda_codec *codec = audio_ptr;
2502 struct hdmi_spec *spec = codec->spec;
2503 hda_nid_t pin_nid = spec->port2pin(codec, port);
2504
2505 if (!pin_nid)
2506 return;
2507 if (get_wcaps_type(get_wcaps(codec, pin_nid)) != AC_WID_PIN)
2508 return;
2509 /* skip notification during system suspend (but not in runtime PM);
2510 * the state will be updated at resume
2511 */
2512 if (snd_power_get_state(codec->card) != SNDRV_CTL_POWER_D0)
2513 return;
2514 /* ditto during suspend/resume process itself */
2515 if (snd_hdac_is_in_pm(&codec->core))
2516 return;
2517
2518 check_presence_and_report(codec, pin_nid, dev_id);
2519}
2520
2521/* set up the private drm_audio_ops from the template */
2522static void setup_drm_audio_ops(struct hda_codec *codec,
2523 const struct drm_audio_component_audio_ops *ops)
2524{
2525 struct hdmi_spec *spec = codec->spec;
2526
2527 spec->drm_audio_ops.audio_ptr = codec;
2528 /* intel_audio_codec_enable() or intel_audio_codec_disable()
2529 * will call pin_eld_notify with using audio_ptr pointer
2530 * We need make sure audio_ptr is really setup
2531 */
2532 wmb();
2533 spec->drm_audio_ops.pin2port = ops->pin2port;
2534 spec->drm_audio_ops.pin_eld_notify = ops->pin_eld_notify;
2535 spec->drm_audio_ops.master_bind = ops->master_bind;
2536 spec->drm_audio_ops.master_unbind = ops->master_unbind;
2537}
2538
2539/* initialize the generic HDMI audio component */
2540static void generic_acomp_init(struct hda_codec *codec,
2541 const struct drm_audio_component_audio_ops *ops,
2542 int (*port2pin)(struct hda_codec *, int))
2543{
2544 struct hdmi_spec *spec = codec->spec;
2545
2546 spec->port2pin = port2pin;
2547 setup_drm_audio_ops(codec, ops);
2548 if (!snd_hdac_acomp_init(&codec->bus->core, &spec->drm_audio_ops,
2549 match_bound_vga, 0)) {
2550 spec->acomp_registered = true;
2551 codec->bus->keep_power = 0;
2552 }
2553}
2554
2555/*
2556 * Intel codec parsers and helpers
2557 */
2558
2559static void intel_haswell_fixup_connect_list(struct hda_codec *codec,
2560 hda_nid_t nid)
2561{
2562 struct hdmi_spec *spec = codec->spec;
2563 hda_nid_t conns[4];
2564 int nconns;
2565
2566 nconns = snd_hda_get_connections(codec, nid, conns, ARRAY_SIZE(conns));
2567 if (nconns == spec->num_cvts &&
2568 !memcmp(conns, spec->cvt_nids, spec->num_cvts * sizeof(hda_nid_t)))
2569 return;
2570
2571 /* override pins connection list */
2572 codec_dbg(codec, "hdmi: haswell: override pin connection 0x%x\n", nid);
2573 snd_hda_override_conn_list(codec, nid, spec->num_cvts, spec->cvt_nids);
2574}
2575
2576#define INTEL_GET_VENDOR_VERB 0xf81
2577#define INTEL_SET_VENDOR_VERB 0x781
2578#define INTEL_EN_DP12 0x02 /* enable DP 1.2 features */
2579#define INTEL_EN_ALL_PIN_CVTS 0x01 /* enable 2nd & 3rd pins and convertors */
2580
2581static void intel_haswell_enable_all_pins(struct hda_codec *codec,
2582 bool update_tree)
2583{
2584 unsigned int vendor_param;
2585 struct hdmi_spec *spec = codec->spec;
2586
2587 vendor_param = snd_hda_codec_read(codec, spec->vendor_nid, 0,
2588 INTEL_GET_VENDOR_VERB, 0);
2589 if (vendor_param == -1 || vendor_param & INTEL_EN_ALL_PIN_CVTS)
2590 return;
2591
2592 vendor_param |= INTEL_EN_ALL_PIN_CVTS;
2593 vendor_param = snd_hda_codec_read(codec, spec->vendor_nid, 0,
2594 INTEL_SET_VENDOR_VERB, vendor_param);
2595 if (vendor_param == -1)
2596 return;
2597
2598 if (update_tree)
2599 snd_hda_codec_update_widgets(codec);
2600}
2601
2602static void intel_haswell_fixup_enable_dp12(struct hda_codec *codec)
2603{
2604 unsigned int vendor_param;
2605 struct hdmi_spec *spec = codec->spec;
2606
2607 vendor_param = snd_hda_codec_read(codec, spec->vendor_nid, 0,
2608 INTEL_GET_VENDOR_VERB, 0);
2609 if (vendor_param == -1 || vendor_param & INTEL_EN_DP12)
2610 return;
2611
2612 /* enable DP1.2 mode */
2613 vendor_param |= INTEL_EN_DP12;
2614 snd_hdac_regmap_add_vendor_verb(&codec->core, INTEL_SET_VENDOR_VERB);
2615 snd_hda_codec_write_cache(codec, spec->vendor_nid, 0,
2616 INTEL_SET_VENDOR_VERB, vendor_param);
2617}
2618
2619/* Haswell needs to re-issue the vendor-specific verbs before turning to D0.
2620 * Otherwise you may get severe h/w communication errors.
2621 */
2622static void haswell_set_power_state(struct hda_codec *codec, hda_nid_t fg,
2623 unsigned int power_state)
2624{
2625 if (power_state == AC_PWRST_D0) {
2626 intel_haswell_enable_all_pins(codec, false);
2627 intel_haswell_fixup_enable_dp12(codec);
2628 }
2629
2630 snd_hda_codec_read(codec, fg, 0, AC_VERB_SET_POWER_STATE, power_state);
2631 snd_hda_codec_set_power_to_all(codec, fg, power_state);
2632}
2633
2634/* There is a fixed mapping between audio pin node and display port.
2635 * on SNB, IVY, HSW, BSW, SKL, BXT, KBL:
2636 * Pin Widget 5 - PORT B (port = 1 in i915 driver)
2637 * Pin Widget 6 - PORT C (port = 2 in i915 driver)
2638 * Pin Widget 7 - PORT D (port = 3 in i915 driver)
2639 *
2640 * on VLV, ILK:
2641 * Pin Widget 4 - PORT B (port = 1 in i915 driver)
2642 * Pin Widget 5 - PORT C (port = 2 in i915 driver)
2643 * Pin Widget 6 - PORT D (port = 3 in i915 driver)
2644 */
2645static int intel_base_nid(struct hda_codec *codec)
2646{
2647 switch (codec->core.vendor_id) {
2648 case 0x80860054: /* ILK */
2649 case 0x80862804: /* ILK */
2650 case 0x80862882: /* VLV */
2651 return 4;
2652 default:
2653 return 5;
2654 }
2655}
2656
2657static int intel_pin2port(void *audio_ptr, int pin_nid)
2658{
2659 struct hda_codec *codec = audio_ptr;
2660 struct hdmi_spec *spec = codec->spec;
2661 int base_nid, i;
2662
2663 if (!spec->port_num) {
2664 base_nid = intel_base_nid(codec);
2665 if (WARN_ON(pin_nid < base_nid || pin_nid >= base_nid + 3))
2666 return -1;
2667 return pin_nid - base_nid + 1; /* intel port is 1-based */
2668 }
2669
2670 /*
2671 * looking for the pin number in the mapping table and return
2672 * the index which indicate the port number
2673 */
2674 for (i = 0; i < spec->port_num; i++) {
2675 if (pin_nid == spec->port_map[i])
2676 return i + 1;
2677 }
2678
2679 /* return -1 if pin number exceeds our expectation */
2680 codec_info(codec, "Can't find the HDMI/DP port for pin %d\n", pin_nid);
2681 return -1;
2682}
2683
2684static int intel_port2pin(struct hda_codec *codec, int port)
2685{
2686 struct hdmi_spec *spec = codec->spec;
2687
2688 if (!spec->port_num) {
2689 /* we assume only from port-B to port-D */
2690 if (port < 1 || port > 3)
2691 return 0;
2692 /* intel port is 1-based */
2693 return port + intel_base_nid(codec) - 1;
2694 }
2695
2696 if (port < 1 || port > spec->port_num)
2697 return 0;
2698 return spec->port_map[port - 1];
2699}
2700
2701static void intel_pin_eld_notify(void *audio_ptr, int port, int pipe)
2702{
2703 struct hda_codec *codec = audio_ptr;
2704 int pin_nid;
2705 int dev_id = pipe;
2706
2707 pin_nid = intel_port2pin(codec, port);
2708 if (!pin_nid)
2709 return;
2710 /* skip notification during system suspend (but not in runtime PM);
2711 * the state will be updated at resume
2712 */
2713 if (snd_power_get_state(codec->card) != SNDRV_CTL_POWER_D0)
2714 return;
2715 /* ditto during suspend/resume process itself */
2716 if (snd_hdac_is_in_pm(&codec->core))
2717 return;
2718
2719 snd_hdac_i915_set_bclk(&codec->bus->core);
2720 check_presence_and_report(codec, pin_nid, dev_id);
2721}
2722
2723static const struct drm_audio_component_audio_ops intel_audio_ops = {
2724 .pin2port = intel_pin2port,
2725 .pin_eld_notify = intel_pin_eld_notify,
2726};
2727
2728/* register i915 component pin_eld_notify callback */
2729static void register_i915_notifier(struct hda_codec *codec)
2730{
2731 struct hdmi_spec *spec = codec->spec;
2732
2733 spec->use_acomp_notifier = true;
2734 spec->port2pin = intel_port2pin;
2735 setup_drm_audio_ops(codec, &intel_audio_ops);
2736 snd_hdac_acomp_register_notifier(&codec->bus->core,
2737 &spec->drm_audio_ops);
2738 /* no need for forcible resume for jack check thanks to notifier */
2739 codec->relaxed_resume = 1;
2740}
2741
2742/* setup_stream ops override for HSW+ */
2743static int i915_hsw_setup_stream(struct hda_codec *codec, hda_nid_t cvt_nid,
2744 hda_nid_t pin_nid, u32 stream_tag, int format)
2745{
2746 haswell_verify_D0(codec, cvt_nid, pin_nid);
2747 return hdmi_setup_stream(codec, cvt_nid, pin_nid, stream_tag, format);
2748}
2749
2750/* pin_cvt_fixup ops override for HSW+ and VLV+ */
2751static void i915_pin_cvt_fixup(struct hda_codec *codec,
2752 struct hdmi_spec_per_pin *per_pin,
2753 hda_nid_t cvt_nid)
2754{
2755 if (per_pin) {
2756 snd_hda_set_dev_select(codec, per_pin->pin_nid,
2757 per_pin->dev_id);
2758 intel_verify_pin_cvt_connect(codec, per_pin);
2759 intel_not_share_assigned_cvt(codec, per_pin->pin_nid,
2760 per_pin->dev_id, per_pin->mux_idx);
2761 } else {
2762 intel_not_share_assigned_cvt_nid(codec, 0, 0, cvt_nid);
2763 }
2764}
2765
2766/* precondition and allocation for Intel codecs */
2767static int alloc_intel_hdmi(struct hda_codec *codec)
2768{
2769 int err;
2770
2771 /* requires i915 binding */
2772 if (!codec->bus->core.audio_component) {
2773 codec_info(codec, "No i915 binding for Intel HDMI/DP codec\n");
2774 /* set probe_id here to prevent generic fallback binding */
2775 codec->probe_id = HDA_CODEC_ID_SKIP_PROBE;
2776 return -ENODEV;
2777 }
2778
2779 err = alloc_generic_hdmi(codec);
2780 if (err < 0)
2781 return err;
2782 /* no need to handle unsol events */
2783 codec->patch_ops.unsol_event = NULL;
2784 return 0;
2785}
2786
2787/* parse and post-process for Intel codecs */
2788static int parse_intel_hdmi(struct hda_codec *codec)
2789{
2790 int err;
2791
2792 err = hdmi_parse_codec(codec);
2793 if (err < 0) {
2794 generic_spec_free(codec);
2795 return err;
2796 }
2797
2798 generic_hdmi_init_per_pins(codec);
2799 register_i915_notifier(codec);
2800 return 0;
2801}
2802
2803/* Intel Haswell and onwards; audio component with eld notifier */
2804static int intel_hsw_common_init(struct hda_codec *codec, hda_nid_t vendor_nid,
2805 const int *port_map, int port_num)
2806{
2807 struct hdmi_spec *spec;
2808 int err;
2809
2810 err = alloc_intel_hdmi(codec);
2811 if (err < 0)
2812 return err;
2813 spec = codec->spec;
2814 codec->dp_mst = true;
2815 spec->dyn_pcm_assign = true;
2816 spec->vendor_nid = vendor_nid;
2817 spec->port_map = port_map;
2818 spec->port_num = port_num;
2819
2820 intel_haswell_enable_all_pins(codec, true);
2821 intel_haswell_fixup_enable_dp12(codec);
2822
2823 codec->display_power_control = 1;
2824
2825 codec->patch_ops.set_power_state = haswell_set_power_state;
2826 codec->depop_delay = 0;
2827 codec->auto_runtime_pm = 1;
2828
2829 spec->ops.setup_stream = i915_hsw_setup_stream;
2830 spec->ops.pin_cvt_fixup = i915_pin_cvt_fixup;
2831
2832 return parse_intel_hdmi(codec);
2833}
2834
2835static int patch_i915_hsw_hdmi(struct hda_codec *codec)
2836{
2837 return intel_hsw_common_init(codec, 0x08, NULL, 0);
2838}
2839
2840static int patch_i915_glk_hdmi(struct hda_codec *codec)
2841{
2842 return intel_hsw_common_init(codec, 0x0b, NULL, 0);
2843}
2844
2845static int patch_i915_icl_hdmi(struct hda_codec *codec)
2846{
2847 /*
2848 * pin to port mapping table where the value indicate the pin number and
2849 * the index indicate the port number with 1 base.
2850 */
2851 static const int map[] = {0x4, 0x6, 0x8, 0xa, 0xb};
2852
2853 return intel_hsw_common_init(codec, 0x02, map, ARRAY_SIZE(map));
2854}
2855
2856static int patch_i915_tgl_hdmi(struct hda_codec *codec)
2857{
2858 /*
2859 * pin to port mapping table where the value indicate the pin number and
2860 * the index indicate the port number with 1 base.
2861 */
2862 static const int map[] = {0x4, 0x6, 0x8, 0xa, 0xb, 0xc, 0xd, 0xe, 0xf};
2863
2864 return intel_hsw_common_init(codec, 0x02, map, ARRAY_SIZE(map));
2865}
2866
2867
2868/* Intel Baytrail and Braswell; with eld notifier */
2869static int patch_i915_byt_hdmi(struct hda_codec *codec)
2870{
2871 struct hdmi_spec *spec;
2872 int err;
2873
2874 err = alloc_intel_hdmi(codec);
2875 if (err < 0)
2876 return err;
2877 spec = codec->spec;
2878
2879 /* For Valleyview/Cherryview, only the display codec is in the display
2880 * power well and can use link_power ops to request/release the power.
2881 */
2882 codec->display_power_control = 1;
2883
2884 codec->depop_delay = 0;
2885 codec->auto_runtime_pm = 1;
2886
2887 spec->ops.pin_cvt_fixup = i915_pin_cvt_fixup;
2888
2889 return parse_intel_hdmi(codec);
2890}
2891
2892/* Intel IronLake, SandyBridge and IvyBridge; with eld notifier */
2893static int patch_i915_cpt_hdmi(struct hda_codec *codec)
2894{
2895 int err;
2896
2897 err = alloc_intel_hdmi(codec);
2898 if (err < 0)
2899 return err;
2900 return parse_intel_hdmi(codec);
2901}
2902
2903/*
2904 * Shared non-generic implementations
2905 */
2906
2907static int simple_playback_build_pcms(struct hda_codec *codec)
2908{
2909 struct hdmi_spec *spec = codec->spec;
2910 struct hda_pcm *info;
2911 unsigned int chans;
2912 struct hda_pcm_stream *pstr;
2913 struct hdmi_spec_per_cvt *per_cvt;
2914
2915 per_cvt = get_cvt(spec, 0);
2916 chans = get_wcaps(codec, per_cvt->cvt_nid);
2917 chans = get_wcaps_channels(chans);
2918
2919 info = snd_hda_codec_pcm_new(codec, "HDMI 0");
2920 if (!info)
2921 return -ENOMEM;
2922 spec->pcm_rec[0].pcm = info;
2923 info->pcm_type = HDA_PCM_TYPE_HDMI;
2924 pstr = &info->stream[SNDRV_PCM_STREAM_PLAYBACK];
2925 *pstr = spec->pcm_playback;
2926 pstr->nid = per_cvt->cvt_nid;
2927 if (pstr->channels_max <= 2 && chans && chans <= 16)
2928 pstr->channels_max = chans;
2929
2930 return 0;
2931}
2932
2933/* unsolicited event for jack sensing */
2934static void simple_hdmi_unsol_event(struct hda_codec *codec,
2935 unsigned int res)
2936{
2937 snd_hda_jack_set_dirty_all(codec);
2938 snd_hda_jack_report_sync(codec);
2939}
2940
2941/* generic_hdmi_build_jack can be used for simple_hdmi, too,
2942 * as long as spec->pins[] is set correctly
2943 */
2944#define simple_hdmi_build_jack generic_hdmi_build_jack
2945
2946static int simple_playback_build_controls(struct hda_codec *codec)
2947{
2948 struct hdmi_spec *spec = codec->spec;
2949 struct hdmi_spec_per_cvt *per_cvt;
2950 int err;
2951
2952 per_cvt = get_cvt(spec, 0);
2953 err = snd_hda_create_dig_out_ctls(codec, per_cvt->cvt_nid,
2954 per_cvt->cvt_nid,
2955 HDA_PCM_TYPE_HDMI);
2956 if (err < 0)
2957 return err;
2958 return simple_hdmi_build_jack(codec, 0);
2959}
2960
2961static int simple_playback_init(struct hda_codec *codec)
2962{
2963 struct hdmi_spec *spec = codec->spec;
2964 struct hdmi_spec_per_pin *per_pin = get_pin(spec, 0);
2965 hda_nid_t pin = per_pin->pin_nid;
2966
2967 snd_hda_codec_write(codec, pin, 0,
2968 AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT);
2969 /* some codecs require to unmute the pin */
2970 if (get_wcaps(codec, pin) & AC_WCAP_OUT_AMP)
2971 snd_hda_codec_write(codec, pin, 0, AC_VERB_SET_AMP_GAIN_MUTE,
2972 AMP_OUT_UNMUTE);
2973 snd_hda_jack_detect_enable(codec, pin);
2974 return 0;
2975}
2976
2977static void simple_playback_free(struct hda_codec *codec)
2978{
2979 struct hdmi_spec *spec = codec->spec;
2980
2981 hdmi_array_free(spec);
2982 kfree(spec);
2983}
2984
2985/*
2986 * Nvidia specific implementations
2987 */
2988
2989#define Nv_VERB_SET_Channel_Allocation 0xF79
2990#define Nv_VERB_SET_Info_Frame_Checksum 0xF7A
2991#define Nv_VERB_SET_Audio_Protection_On 0xF98
2992#define Nv_VERB_SET_Audio_Protection_Off 0xF99
2993
2994#define nvhdmi_master_con_nid_7x 0x04
2995#define nvhdmi_master_pin_nid_7x 0x05
2996
2997static const hda_nid_t nvhdmi_con_nids_7x[4] = {
2998 /*front, rear, clfe, rear_surr */
2999 0x6, 0x8, 0xa, 0xc,
3000};
3001
3002static const struct hda_verb nvhdmi_basic_init_7x_2ch[] = {
3003 /* set audio protect on */
3004 { 0x1, Nv_VERB_SET_Audio_Protection_On, 0x1},
3005 /* enable digital output on pin widget */
3006 { 0x5, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
3007 {} /* terminator */
3008};
3009
3010static const struct hda_verb nvhdmi_basic_init_7x_8ch[] = {
3011 /* set audio protect on */
3012 { 0x1, Nv_VERB_SET_Audio_Protection_On, 0x1},
3013 /* enable digital output on pin widget */
3014 { 0x5, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
3015 { 0x7, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
3016 { 0x9, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
3017 { 0xb, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
3018 { 0xd, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
3019 {} /* terminator */
3020};
3021
3022#ifdef LIMITED_RATE_FMT_SUPPORT
3023/* support only the safe format and rate */
3024#define SUPPORTED_RATES SNDRV_PCM_RATE_48000
3025#define SUPPORTED_MAXBPS 16
3026#define SUPPORTED_FORMATS SNDRV_PCM_FMTBIT_S16_LE
3027#else
3028/* support all rates and formats */
3029#define SUPPORTED_RATES \
3030 (SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000 |\
3031 SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |\
3032 SNDRV_PCM_RATE_192000)
3033#define SUPPORTED_MAXBPS 24
3034#define SUPPORTED_FORMATS \
3035 (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE)
3036#endif
3037
3038static int nvhdmi_7x_init_2ch(struct hda_codec *codec)
3039{
3040 snd_hda_sequence_write(codec, nvhdmi_basic_init_7x_2ch);
3041 return 0;
3042}
3043
3044static int nvhdmi_7x_init_8ch(struct hda_codec *codec)
3045{
3046 snd_hda_sequence_write(codec, nvhdmi_basic_init_7x_8ch);
3047 return 0;
3048}
3049
3050static const unsigned int channels_2_6_8[] = {
3051 2, 6, 8
3052};
3053
3054static const unsigned int channels_2_8[] = {
3055 2, 8
3056};
3057
3058static const struct snd_pcm_hw_constraint_list hw_constraints_2_6_8_channels = {
3059 .count = ARRAY_SIZE(channels_2_6_8),
3060 .list = channels_2_6_8,
3061 .mask = 0,
3062};
3063
3064static const struct snd_pcm_hw_constraint_list hw_constraints_2_8_channels = {
3065 .count = ARRAY_SIZE(channels_2_8),
3066 .list = channels_2_8,
3067 .mask = 0,
3068};
3069
3070static int simple_playback_pcm_open(struct hda_pcm_stream *hinfo,
3071 struct hda_codec *codec,
3072 struct snd_pcm_substream *substream)
3073{
3074 struct hdmi_spec *spec = codec->spec;
3075 const struct snd_pcm_hw_constraint_list *hw_constraints_channels = NULL;
3076
3077 switch (codec->preset->vendor_id) {
3078 case 0x10de0002:
3079 case 0x10de0003:
3080 case 0x10de0005:
3081 case 0x10de0006:
3082 hw_constraints_channels = &hw_constraints_2_8_channels;
3083 break;
3084 case 0x10de0007:
3085 hw_constraints_channels = &hw_constraints_2_6_8_channels;
3086 break;
3087 default:
3088 break;
3089 }
3090
3091 if (hw_constraints_channels != NULL) {
3092 snd_pcm_hw_constraint_list(substream->runtime, 0,
3093 SNDRV_PCM_HW_PARAM_CHANNELS,
3094 hw_constraints_channels);
3095 } else {
3096 snd_pcm_hw_constraint_step(substream->runtime, 0,
3097 SNDRV_PCM_HW_PARAM_CHANNELS, 2);
3098 }
3099
3100 return snd_hda_multi_out_dig_open(codec, &spec->multiout);
3101}
3102
3103static int simple_playback_pcm_close(struct hda_pcm_stream *hinfo,
3104 struct hda_codec *codec,
3105 struct snd_pcm_substream *substream)
3106{
3107 struct hdmi_spec *spec = codec->spec;
3108 return snd_hda_multi_out_dig_close(codec, &spec->multiout);
3109}
3110
3111static int simple_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
3112 struct hda_codec *codec,
3113 unsigned int stream_tag,
3114 unsigned int format,
3115 struct snd_pcm_substream *substream)
3116{
3117 struct hdmi_spec *spec = codec->spec;
3118 return snd_hda_multi_out_dig_prepare(codec, &spec->multiout,
3119 stream_tag, format, substream);
3120}
3121
3122static const struct hda_pcm_stream simple_pcm_playback = {
3123 .substreams = 1,
3124 .channels_min = 2,
3125 .channels_max = 2,
3126 .ops = {
3127 .open = simple_playback_pcm_open,
3128 .close = simple_playback_pcm_close,
3129 .prepare = simple_playback_pcm_prepare
3130 },
3131};
3132
3133static const struct hda_codec_ops simple_hdmi_patch_ops = {
3134 .build_controls = simple_playback_build_controls,
3135 .build_pcms = simple_playback_build_pcms,
3136 .init = simple_playback_init,
3137 .free = simple_playback_free,
3138 .unsol_event = simple_hdmi_unsol_event,
3139};
3140
3141static int patch_simple_hdmi(struct hda_codec *codec,
3142 hda_nid_t cvt_nid, hda_nid_t pin_nid)
3143{
3144 struct hdmi_spec *spec;
3145 struct hdmi_spec_per_cvt *per_cvt;
3146 struct hdmi_spec_per_pin *per_pin;
3147
3148 spec = kzalloc(sizeof(*spec), GFP_KERNEL);
3149 if (!spec)
3150 return -ENOMEM;
3151
3152 spec->codec = codec;
3153 codec->spec = spec;
3154 hdmi_array_init(spec, 1);
3155
3156 spec->multiout.num_dacs = 0; /* no analog */
3157 spec->multiout.max_channels = 2;
3158 spec->multiout.dig_out_nid = cvt_nid;
3159 spec->num_cvts = 1;
3160 spec->num_pins = 1;
3161 per_pin = snd_array_new(&spec->pins);
3162 per_cvt = snd_array_new(&spec->cvts);
3163 if (!per_pin || !per_cvt) {
3164 simple_playback_free(codec);
3165 return -ENOMEM;
3166 }
3167 per_cvt->cvt_nid = cvt_nid;
3168 per_pin->pin_nid = pin_nid;
3169 spec->pcm_playback = simple_pcm_playback;
3170
3171 codec->patch_ops = simple_hdmi_patch_ops;
3172
3173 return 0;
3174}
3175
3176static void nvhdmi_8ch_7x_set_info_frame_parameters(struct hda_codec *codec,
3177 int channels)
3178{
3179 unsigned int chanmask;
3180 int chan = channels ? (channels - 1) : 1;
3181
3182 switch (channels) {
3183 default:
3184 case 0:
3185 case 2:
3186 chanmask = 0x00;
3187 break;
3188 case 4:
3189 chanmask = 0x08;
3190 break;
3191 case 6:
3192 chanmask = 0x0b;
3193 break;
3194 case 8:
3195 chanmask = 0x13;
3196 break;
3197 }
3198
3199 /* Set the audio infoframe channel allocation and checksum fields. The
3200 * channel count is computed implicitly by the hardware. */
3201 snd_hda_codec_write(codec, 0x1, 0,
3202 Nv_VERB_SET_Channel_Allocation, chanmask);
3203
3204 snd_hda_codec_write(codec, 0x1, 0,
3205 Nv_VERB_SET_Info_Frame_Checksum,
3206 (0x71 - chan - chanmask));
3207}
3208
3209static int nvhdmi_8ch_7x_pcm_close(struct hda_pcm_stream *hinfo,
3210 struct hda_codec *codec,
3211 struct snd_pcm_substream *substream)
3212{
3213 struct hdmi_spec *spec = codec->spec;
3214 int i;
3215
3216 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x,
3217 0, AC_VERB_SET_CHANNEL_STREAMID, 0);
3218 for (i = 0; i < 4; i++) {
3219 /* set the stream id */
3220 snd_hda_codec_write(codec, nvhdmi_con_nids_7x[i], 0,
3221 AC_VERB_SET_CHANNEL_STREAMID, 0);
3222 /* set the stream format */
3223 snd_hda_codec_write(codec, nvhdmi_con_nids_7x[i], 0,
3224 AC_VERB_SET_STREAM_FORMAT, 0);
3225 }
3226
3227 /* The audio hardware sends a channel count of 0x7 (8ch) when all the
3228 * streams are disabled. */
3229 nvhdmi_8ch_7x_set_info_frame_parameters(codec, 8);
3230
3231 return snd_hda_multi_out_dig_close(codec, &spec->multiout);
3232}
3233
3234static int nvhdmi_8ch_7x_pcm_prepare(struct hda_pcm_stream *hinfo,
3235 struct hda_codec *codec,
3236 unsigned int stream_tag,
3237 unsigned int format,
3238 struct snd_pcm_substream *substream)
3239{
3240 int chs;
3241 unsigned int dataDCC2, channel_id;
3242 int i;
3243 struct hdmi_spec *spec = codec->spec;
3244 struct hda_spdif_out *spdif;
3245 struct hdmi_spec_per_cvt *per_cvt;
3246
3247 mutex_lock(&codec->spdif_mutex);
3248 per_cvt = get_cvt(spec, 0);
3249 spdif = snd_hda_spdif_out_of_nid(codec, per_cvt->cvt_nid);
3250
3251 chs = substream->runtime->channels;
3252
3253 dataDCC2 = 0x2;
3254
3255 /* turn off SPDIF once; otherwise the IEC958 bits won't be updated */
3256 if (codec->spdif_status_reset && (spdif->ctls & AC_DIG1_ENABLE))
3257 snd_hda_codec_write(codec,
3258 nvhdmi_master_con_nid_7x,
3259 0,
3260 AC_VERB_SET_DIGI_CONVERT_1,
3261 spdif->ctls & ~AC_DIG1_ENABLE & 0xff);
3262
3263 /* set the stream id */
3264 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, 0,
3265 AC_VERB_SET_CHANNEL_STREAMID, (stream_tag << 4) | 0x0);
3266
3267 /* set the stream format */
3268 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, 0,
3269 AC_VERB_SET_STREAM_FORMAT, format);
3270
3271 /* turn on again (if needed) */
3272 /* enable and set the channel status audio/data flag */
3273 if (codec->spdif_status_reset && (spdif->ctls & AC_DIG1_ENABLE)) {
3274 snd_hda_codec_write(codec,
3275 nvhdmi_master_con_nid_7x,
3276 0,
3277 AC_VERB_SET_DIGI_CONVERT_1,
3278 spdif->ctls & 0xff);
3279 snd_hda_codec_write(codec,
3280 nvhdmi_master_con_nid_7x,
3281 0,
3282 AC_VERB_SET_DIGI_CONVERT_2, dataDCC2);
3283 }
3284
3285 for (i = 0; i < 4; i++) {
3286 if (chs == 2)
3287 channel_id = 0;
3288 else
3289 channel_id = i * 2;
3290
3291 /* turn off SPDIF once;
3292 *otherwise the IEC958 bits won't be updated
3293 */
3294 if (codec->spdif_status_reset &&
3295 (spdif->ctls & AC_DIG1_ENABLE))
3296 snd_hda_codec_write(codec,
3297 nvhdmi_con_nids_7x[i],
3298 0,
3299 AC_VERB_SET_DIGI_CONVERT_1,
3300 spdif->ctls & ~AC_DIG1_ENABLE & 0xff);
3301 /* set the stream id */
3302 snd_hda_codec_write(codec,
3303 nvhdmi_con_nids_7x[i],
3304 0,
3305 AC_VERB_SET_CHANNEL_STREAMID,
3306 (stream_tag << 4) | channel_id);
3307 /* set the stream format */
3308 snd_hda_codec_write(codec,
3309 nvhdmi_con_nids_7x[i],
3310 0,
3311 AC_VERB_SET_STREAM_FORMAT,
3312 format);
3313 /* turn on again (if needed) */
3314 /* enable and set the channel status audio/data flag */
3315 if (codec->spdif_status_reset &&
3316 (spdif->ctls & AC_DIG1_ENABLE)) {
3317 snd_hda_codec_write(codec,
3318 nvhdmi_con_nids_7x[i],
3319 0,
3320 AC_VERB_SET_DIGI_CONVERT_1,
3321 spdif->ctls & 0xff);
3322 snd_hda_codec_write(codec,
3323 nvhdmi_con_nids_7x[i],
3324 0,
3325 AC_VERB_SET_DIGI_CONVERT_2, dataDCC2);
3326 }
3327 }
3328
3329 nvhdmi_8ch_7x_set_info_frame_parameters(codec, chs);
3330
3331 mutex_unlock(&codec->spdif_mutex);
3332 return 0;
3333}
3334
3335static const struct hda_pcm_stream nvhdmi_pcm_playback_8ch_7x = {
3336 .substreams = 1,
3337 .channels_min = 2,
3338 .channels_max = 8,
3339 .nid = nvhdmi_master_con_nid_7x,
3340 .rates = SUPPORTED_RATES,
3341 .maxbps = SUPPORTED_MAXBPS,
3342 .formats = SUPPORTED_FORMATS,
3343 .ops = {
3344 .open = simple_playback_pcm_open,
3345 .close = nvhdmi_8ch_7x_pcm_close,
3346 .prepare = nvhdmi_8ch_7x_pcm_prepare
3347 },
3348};
3349
3350static int patch_nvhdmi_2ch(struct hda_codec *codec)
3351{
3352 struct hdmi_spec *spec;
3353 int err = patch_simple_hdmi(codec, nvhdmi_master_con_nid_7x,
3354 nvhdmi_master_pin_nid_7x);
3355 if (err < 0)
3356 return err;
3357
3358 codec->patch_ops.init = nvhdmi_7x_init_2ch;
3359 /* override the PCM rates, etc, as the codec doesn't give full list */
3360 spec = codec->spec;
3361 spec->pcm_playback.rates = SUPPORTED_RATES;
3362 spec->pcm_playback.maxbps = SUPPORTED_MAXBPS;
3363 spec->pcm_playback.formats = SUPPORTED_FORMATS;
3364 return 0;
3365}
3366
3367static int nvhdmi_7x_8ch_build_pcms(struct hda_codec *codec)
3368{
3369 struct hdmi_spec *spec = codec->spec;
3370 int err = simple_playback_build_pcms(codec);
3371 if (!err) {
3372 struct hda_pcm *info = get_pcm_rec(spec, 0);
3373 info->own_chmap = true;
3374 }
3375 return err;
3376}
3377
3378static int nvhdmi_7x_8ch_build_controls(struct hda_codec *codec)
3379{
3380 struct hdmi_spec *spec = codec->spec;
3381 struct hda_pcm *info;
3382 struct snd_pcm_chmap *chmap;
3383 int err;
3384
3385 err = simple_playback_build_controls(codec);
3386 if (err < 0)
3387 return err;
3388
3389 /* add channel maps */
3390 info = get_pcm_rec(spec, 0);
3391 err = snd_pcm_add_chmap_ctls(info->pcm,
3392 SNDRV_PCM_STREAM_PLAYBACK,
3393 snd_pcm_alt_chmaps, 8, 0, &chmap);
3394 if (err < 0)
3395 return err;
3396 switch (codec->preset->vendor_id) {
3397 case 0x10de0002:
3398 case 0x10de0003:
3399 case 0x10de0005:
3400 case 0x10de0006:
3401 chmap->channel_mask = (1U << 2) | (1U << 8);
3402 break;
3403 case 0x10de0007:
3404 chmap->channel_mask = (1U << 2) | (1U << 6) | (1U << 8);
3405 }
3406 return 0;
3407}
3408
3409static int patch_nvhdmi_8ch_7x(struct hda_codec *codec)
3410{
3411 struct hdmi_spec *spec;
3412 int err = patch_nvhdmi_2ch(codec);
3413 if (err < 0)
3414 return err;
3415 spec = codec->spec;
3416 spec->multiout.max_channels = 8;
3417 spec->pcm_playback = nvhdmi_pcm_playback_8ch_7x;
3418 codec->patch_ops.init = nvhdmi_7x_init_8ch;
3419 codec->patch_ops.build_pcms = nvhdmi_7x_8ch_build_pcms;
3420 codec->patch_ops.build_controls = nvhdmi_7x_8ch_build_controls;
3421
3422 /* Initialize the audio infoframe channel mask and checksum to something
3423 * valid */
3424 nvhdmi_8ch_7x_set_info_frame_parameters(codec, 8);
3425
3426 return 0;
3427}
3428
3429/*
3430 * NVIDIA codecs ignore ASP mapping for 2ch - confirmed on:
3431 * - 0x10de0015
3432 * - 0x10de0040
3433 */
3434static int nvhdmi_chmap_cea_alloc_validate_get_type(struct hdac_chmap *chmap,
3435 struct hdac_cea_channel_speaker_allocation *cap, int channels)
3436{
3437 if (cap->ca_index == 0x00 && channels == 2)
3438 return SNDRV_CTL_TLVT_CHMAP_FIXED;
3439
3440 /* If the speaker allocation matches the channel count, it is OK. */
3441 if (cap->channels != channels)
3442 return -1;
3443
3444 /* all channels are remappable freely */
3445 return SNDRV_CTL_TLVT_CHMAP_VAR;
3446}
3447
3448static int nvhdmi_chmap_validate(struct hdac_chmap *chmap,
3449 int ca, int chs, unsigned char *map)
3450{
3451 if (ca == 0x00 && (map[0] != SNDRV_CHMAP_FL || map[1] != SNDRV_CHMAP_FR))
3452 return -EINVAL;
3453
3454 return 0;
3455}
3456
3457/* map from pin NID to port; port is 0-based */
3458/* for Nvidia: assume widget NID starting from 4, with step 1 (4, 5, 6, ...) */
3459static int nvhdmi_pin2port(void *audio_ptr, int pin_nid)
3460{
3461 return pin_nid - 4;
3462}
3463
3464/* reverse-map from port to pin NID: see above */
3465static int nvhdmi_port2pin(struct hda_codec *codec, int port)
3466{
3467 return port + 4;
3468}
3469
3470static const struct drm_audio_component_audio_ops nvhdmi_audio_ops = {
3471 .pin2port = nvhdmi_pin2port,
3472 .pin_eld_notify = generic_acomp_pin_eld_notify,
3473 .master_bind = generic_acomp_master_bind,
3474 .master_unbind = generic_acomp_master_unbind,
3475};
3476
3477static int patch_nvhdmi(struct hda_codec *codec)
3478{
3479 struct hdmi_spec *spec;
3480 int err;
3481
3482 err = patch_generic_hdmi(codec);
3483 if (err)
3484 return err;
3485
3486 spec = codec->spec;
3487 spec->dyn_pin_out = true;
3488
3489 spec->chmap.ops.chmap_cea_alloc_validate_get_type =
3490 nvhdmi_chmap_cea_alloc_validate_get_type;
3491 spec->chmap.ops.chmap_validate = nvhdmi_chmap_validate;
3492
3493 codec->link_down_at_suspend = 1;
3494
3495 generic_acomp_init(codec, &nvhdmi_audio_ops, nvhdmi_port2pin);
3496
3497 return 0;
3498}
3499
3500/*
3501 * The HDA codec on NVIDIA Tegra contains two scratch registers that are
3502 * accessed using vendor-defined verbs. These registers can be used for
3503 * interoperability between the HDA and HDMI drivers.
3504 */
3505
3506/* Audio Function Group node */
3507#define NVIDIA_AFG_NID 0x01
3508
3509/*
3510 * The SCRATCH0 register is used to notify the HDMI codec of changes in audio
3511 * format. On Tegra, bit 31 is used as a trigger that causes an interrupt to
3512 * be raised in the HDMI codec. The remainder of the bits is arbitrary. This
3513 * implementation stores the HDA format (see AC_FMT_*) in bits [15:0] and an
3514 * additional bit (at position 30) to signal the validity of the format.
3515 *
3516 * | 31 | 30 | 29 16 | 15 0 |
3517 * +---------+-------+--------+--------+
3518 * | TRIGGER | VALID | UNUSED | FORMAT |
3519 * +-----------------------------------|
3520 *
3521 * Note that for the trigger bit to take effect it needs to change value
3522 * (i.e. it needs to be toggled).
3523 */
3524#define NVIDIA_GET_SCRATCH0 0xfa6
3525#define NVIDIA_SET_SCRATCH0_BYTE0 0xfa7
3526#define NVIDIA_SET_SCRATCH0_BYTE1 0xfa8
3527#define NVIDIA_SET_SCRATCH0_BYTE2 0xfa9
3528#define NVIDIA_SET_SCRATCH0_BYTE3 0xfaa
3529#define NVIDIA_SCRATCH_TRIGGER (1 << 7)
3530#define NVIDIA_SCRATCH_VALID (1 << 6)
3531
3532#define NVIDIA_GET_SCRATCH1 0xfab
3533#define NVIDIA_SET_SCRATCH1_BYTE0 0xfac
3534#define NVIDIA_SET_SCRATCH1_BYTE1 0xfad
3535#define NVIDIA_SET_SCRATCH1_BYTE2 0xfae
3536#define NVIDIA_SET_SCRATCH1_BYTE3 0xfaf
3537
3538/*
3539 * The format parameter is the HDA audio format (see AC_FMT_*). If set to 0,
3540 * the format is invalidated so that the HDMI codec can be disabled.
3541 */
3542static void tegra_hdmi_set_format(struct hda_codec *codec, unsigned int format)
3543{
3544 unsigned int value;
3545
3546 /* bits [31:30] contain the trigger and valid bits */
3547 value = snd_hda_codec_read(codec, NVIDIA_AFG_NID, 0,
3548 NVIDIA_GET_SCRATCH0, 0);
3549 value = (value >> 24) & 0xff;
3550
3551 /* bits [15:0] are used to store the HDA format */
3552 snd_hda_codec_write(codec, NVIDIA_AFG_NID, 0,
3553 NVIDIA_SET_SCRATCH0_BYTE0,
3554 (format >> 0) & 0xff);
3555 snd_hda_codec_write(codec, NVIDIA_AFG_NID, 0,
3556 NVIDIA_SET_SCRATCH0_BYTE1,
3557 (format >> 8) & 0xff);
3558
3559 /* bits [16:24] are unused */
3560 snd_hda_codec_write(codec, NVIDIA_AFG_NID, 0,
3561 NVIDIA_SET_SCRATCH0_BYTE2, 0);
3562
3563 /*
3564 * Bit 30 signals that the data is valid and hence that HDMI audio can
3565 * be enabled.
3566 */
3567 if (format == 0)
3568 value &= ~NVIDIA_SCRATCH_VALID;
3569 else
3570 value |= NVIDIA_SCRATCH_VALID;
3571
3572 /*
3573 * Whenever the trigger bit is toggled, an interrupt is raised in the
3574 * HDMI codec. The HDMI driver will use that as trigger to update its
3575 * configuration.
3576 */
3577 value ^= NVIDIA_SCRATCH_TRIGGER;
3578
3579 snd_hda_codec_write(codec, NVIDIA_AFG_NID, 0,
3580 NVIDIA_SET_SCRATCH0_BYTE3, value);
3581}
3582
3583static int tegra_hdmi_pcm_prepare(struct hda_pcm_stream *hinfo,
3584 struct hda_codec *codec,
3585 unsigned int stream_tag,
3586 unsigned int format,
3587 struct snd_pcm_substream *substream)
3588{
3589 int err;
3590
3591 err = generic_hdmi_playback_pcm_prepare(hinfo, codec, stream_tag,
3592 format, substream);
3593 if (err < 0)
3594 return err;
3595
3596 /* notify the HDMI codec of the format change */
3597 tegra_hdmi_set_format(codec, format);
3598
3599 return 0;
3600}
3601
3602static int tegra_hdmi_pcm_cleanup(struct hda_pcm_stream *hinfo,
3603 struct hda_codec *codec,
3604 struct snd_pcm_substream *substream)
3605{
3606 /* invalidate the format in the HDMI codec */
3607 tegra_hdmi_set_format(codec, 0);
3608
3609 return generic_hdmi_playback_pcm_cleanup(hinfo, codec, substream);
3610}
3611
3612static struct hda_pcm *hda_find_pcm_by_type(struct hda_codec *codec, int type)
3613{
3614 struct hdmi_spec *spec = codec->spec;
3615 unsigned int i;
3616
3617 for (i = 0; i < spec->num_pins; i++) {
3618 struct hda_pcm *pcm = get_pcm_rec(spec, i);
3619
3620 if (pcm->pcm_type == type)
3621 return pcm;
3622 }
3623
3624 return NULL;
3625}
3626
3627static int tegra_hdmi_build_pcms(struct hda_codec *codec)
3628{
3629 struct hda_pcm_stream *stream;
3630 struct hda_pcm *pcm;
3631 int err;
3632
3633 err = generic_hdmi_build_pcms(codec);
3634 if (err < 0)
3635 return err;
3636
3637 pcm = hda_find_pcm_by_type(codec, HDA_PCM_TYPE_HDMI);
3638 if (!pcm)
3639 return -ENODEV;
3640
3641 /*
3642 * Override ->prepare() and ->cleanup() operations to notify the HDMI
3643 * codec about format changes.
3644 */
3645 stream = &pcm->stream[SNDRV_PCM_STREAM_PLAYBACK];
3646 stream->ops.prepare = tegra_hdmi_pcm_prepare;
3647 stream->ops.cleanup = tegra_hdmi_pcm_cleanup;
3648
3649 return 0;
3650}
3651
3652static int patch_tegra_hdmi(struct hda_codec *codec)
3653{
3654 int err;
3655
3656 err = patch_generic_hdmi(codec);
3657 if (err)
3658 return err;
3659
3660 codec->patch_ops.build_pcms = tegra_hdmi_build_pcms;
3661
3662 return 0;
3663}
3664
3665/*
3666 * ATI/AMD-specific implementations
3667 */
3668
3669#define is_amdhdmi_rev3_or_later(codec) \
3670 ((codec)->core.vendor_id == 0x1002aa01 && \
3671 ((codec)->core.revision_id & 0xff00) >= 0x0300)
3672#define has_amd_full_remap_support(codec) is_amdhdmi_rev3_or_later(codec)
3673
3674/* ATI/AMD specific HDA pin verbs, see the AMD HDA Verbs specification */
3675#define ATI_VERB_SET_CHANNEL_ALLOCATION 0x771
3676#define ATI_VERB_SET_DOWNMIX_INFO 0x772
3677#define ATI_VERB_SET_MULTICHANNEL_01 0x777
3678#define ATI_VERB_SET_MULTICHANNEL_23 0x778
3679#define ATI_VERB_SET_MULTICHANNEL_45 0x779
3680#define ATI_VERB_SET_MULTICHANNEL_67 0x77a
3681#define ATI_VERB_SET_HBR_CONTROL 0x77c
3682#define ATI_VERB_SET_MULTICHANNEL_1 0x785
3683#define ATI_VERB_SET_MULTICHANNEL_3 0x786
3684#define ATI_VERB_SET_MULTICHANNEL_5 0x787
3685#define ATI_VERB_SET_MULTICHANNEL_7 0x788
3686#define ATI_VERB_SET_MULTICHANNEL_MODE 0x789
3687#define ATI_VERB_GET_CHANNEL_ALLOCATION 0xf71
3688#define ATI_VERB_GET_DOWNMIX_INFO 0xf72
3689#define ATI_VERB_GET_MULTICHANNEL_01 0xf77
3690#define ATI_VERB_GET_MULTICHANNEL_23 0xf78
3691#define ATI_VERB_GET_MULTICHANNEL_45 0xf79
3692#define ATI_VERB_GET_MULTICHANNEL_67 0xf7a
3693#define ATI_VERB_GET_HBR_CONTROL 0xf7c
3694#define ATI_VERB_GET_MULTICHANNEL_1 0xf85
3695#define ATI_VERB_GET_MULTICHANNEL_3 0xf86
3696#define ATI_VERB_GET_MULTICHANNEL_5 0xf87
3697#define ATI_VERB_GET_MULTICHANNEL_7 0xf88
3698#define ATI_VERB_GET_MULTICHANNEL_MODE 0xf89
3699
3700/* AMD specific HDA cvt verbs */
3701#define ATI_VERB_SET_RAMP_RATE 0x770
3702#define ATI_VERB_GET_RAMP_RATE 0xf70
3703
3704#define ATI_OUT_ENABLE 0x1
3705
3706#define ATI_MULTICHANNEL_MODE_PAIRED 0
3707#define ATI_MULTICHANNEL_MODE_SINGLE 1
3708
3709#define ATI_HBR_CAPABLE 0x01
3710#define ATI_HBR_ENABLE 0x10
3711
3712static int atihdmi_pin_get_eld(struct hda_codec *codec, hda_nid_t nid,
3713 unsigned char *buf, int *eld_size)
3714{
3715 /* call hda_eld.c ATI/AMD-specific function */
3716 return snd_hdmi_get_eld_ati(codec, nid, buf, eld_size,
3717 is_amdhdmi_rev3_or_later(codec));
3718}
3719
3720static void atihdmi_pin_setup_infoframe(struct hda_codec *codec, hda_nid_t pin_nid, int ca,
3721 int active_channels, int conn_type)
3722{
3723 snd_hda_codec_write(codec, pin_nid, 0, ATI_VERB_SET_CHANNEL_ALLOCATION, ca);
3724}
3725
3726static int atihdmi_paired_swap_fc_lfe(int pos)
3727{
3728 /*
3729 * ATI/AMD have automatic FC/LFE swap built-in
3730 * when in pairwise mapping mode.
3731 */
3732
3733 switch (pos) {
3734 /* see channel_allocations[].speakers[] */
3735 case 2: return 3;
3736 case 3: return 2;
3737 default: break;
3738 }
3739
3740 return pos;
3741}
3742
3743static int atihdmi_paired_chmap_validate(struct hdac_chmap *chmap,
3744 int ca, int chs, unsigned char *map)
3745{
3746 struct hdac_cea_channel_speaker_allocation *cap;
3747 int i, j;
3748
3749 /* check that only channel pairs need to be remapped on old pre-rev3 ATI/AMD */
3750
3751 cap = snd_hdac_get_ch_alloc_from_ca(ca);
3752 for (i = 0; i < chs; ++i) {
3753 int mask = snd_hdac_chmap_to_spk_mask(map[i]);
3754 bool ok = false;
3755 bool companion_ok = false;
3756
3757 if (!mask)
3758 continue;
3759
3760 for (j = 0 + i % 2; j < 8; j += 2) {
3761 int chan_idx = 7 - atihdmi_paired_swap_fc_lfe(j);
3762 if (cap->speakers[chan_idx] == mask) {
3763 /* channel is in a supported position */
3764 ok = true;
3765
3766 if (i % 2 == 0 && i + 1 < chs) {
3767 /* even channel, check the odd companion */
3768 int comp_chan_idx = 7 - atihdmi_paired_swap_fc_lfe(j + 1);
3769 int comp_mask_req = snd_hdac_chmap_to_spk_mask(map[i+1]);
3770 int comp_mask_act = cap->speakers[comp_chan_idx];
3771
3772 if (comp_mask_req == comp_mask_act)
3773 companion_ok = true;
3774 else
3775 return -EINVAL;
3776 }
3777 break;
3778 }
3779 }
3780
3781 if (!ok)
3782 return -EINVAL;
3783
3784 if (companion_ok)
3785 i++; /* companion channel already checked */
3786 }
3787
3788 return 0;
3789}
3790
3791static int atihdmi_pin_set_slot_channel(struct hdac_device *hdac,
3792 hda_nid_t pin_nid, int hdmi_slot, int stream_channel)
3793{
3794 struct hda_codec *codec = container_of(hdac, struct hda_codec, core);
3795 int verb;
3796 int ati_channel_setup = 0;
3797
3798 if (hdmi_slot > 7)
3799 return -EINVAL;
3800
3801 if (!has_amd_full_remap_support(codec)) {
3802 hdmi_slot = atihdmi_paired_swap_fc_lfe(hdmi_slot);
3803
3804 /* In case this is an odd slot but without stream channel, do not
3805 * disable the slot since the corresponding even slot could have a
3806 * channel. In case neither have a channel, the slot pair will be
3807 * disabled when this function is called for the even slot. */
3808 if (hdmi_slot % 2 != 0 && stream_channel == 0xf)
3809 return 0;
3810
3811 hdmi_slot -= hdmi_slot % 2;
3812
3813 if (stream_channel != 0xf)
3814 stream_channel -= stream_channel % 2;
3815 }
3816
3817 verb = ATI_VERB_SET_MULTICHANNEL_01 + hdmi_slot/2 + (hdmi_slot % 2) * 0x00e;
3818
3819 /* ati_channel_setup format: [7..4] = stream_channel_id, [1] = mute, [0] = enable */
3820
3821 if (stream_channel != 0xf)
3822 ati_channel_setup = (stream_channel << 4) | ATI_OUT_ENABLE;
3823
3824 return snd_hda_codec_write(codec, pin_nid, 0, verb, ati_channel_setup);
3825}
3826
3827static int atihdmi_pin_get_slot_channel(struct hdac_device *hdac,
3828 hda_nid_t pin_nid, int asp_slot)
3829{
3830 struct hda_codec *codec = container_of(hdac, struct hda_codec, core);
3831 bool was_odd = false;
3832 int ati_asp_slot = asp_slot;
3833 int verb;
3834 int ati_channel_setup;
3835
3836 if (asp_slot > 7)
3837 return -EINVAL;
3838
3839 if (!has_amd_full_remap_support(codec)) {
3840 ati_asp_slot = atihdmi_paired_swap_fc_lfe(asp_slot);
3841 if (ati_asp_slot % 2 != 0) {
3842 ati_asp_slot -= 1;
3843 was_odd = true;
3844 }
3845 }
3846
3847 verb = ATI_VERB_GET_MULTICHANNEL_01 + ati_asp_slot/2 + (ati_asp_slot % 2) * 0x00e;
3848
3849 ati_channel_setup = snd_hda_codec_read(codec, pin_nid, 0, verb, 0);
3850
3851 if (!(ati_channel_setup & ATI_OUT_ENABLE))
3852 return 0xf;
3853
3854 return ((ati_channel_setup & 0xf0) >> 4) + !!was_odd;
3855}
3856
3857static int atihdmi_paired_chmap_cea_alloc_validate_get_type(
3858 struct hdac_chmap *chmap,
3859 struct hdac_cea_channel_speaker_allocation *cap,
3860 int channels)
3861{
3862 int c;
3863
3864 /*
3865 * Pre-rev3 ATI/AMD codecs operate in a paired channel mode, so
3866 * we need to take that into account (a single channel may take 2
3867 * channel slots if we need to carry a silent channel next to it).
3868 * On Rev3+ AMD codecs this function is not used.
3869 */
3870 int chanpairs = 0;
3871
3872 /* We only produce even-numbered channel count TLVs */
3873 if ((channels % 2) != 0)
3874 return -1;
3875
3876 for (c = 0; c < 7; c += 2) {
3877 if (cap->speakers[c] || cap->speakers[c+1])
3878 chanpairs++;
3879 }
3880
3881 if (chanpairs * 2 != channels)
3882 return -1;
3883
3884 return SNDRV_CTL_TLVT_CHMAP_PAIRED;
3885}
3886
3887static void atihdmi_paired_cea_alloc_to_tlv_chmap(struct hdac_chmap *hchmap,
3888 struct hdac_cea_channel_speaker_allocation *cap,
3889 unsigned int *chmap, int channels)
3890{
3891 /* produce paired maps for pre-rev3 ATI/AMD codecs */
3892 int count = 0;
3893 int c;
3894
3895 for (c = 7; c >= 0; c--) {
3896 int chan = 7 - atihdmi_paired_swap_fc_lfe(7 - c);
3897 int spk = cap->speakers[chan];
3898 if (!spk) {
3899 /* add N/A channel if the companion channel is occupied */
3900 if (cap->speakers[chan + (chan % 2 ? -1 : 1)])
3901 chmap[count++] = SNDRV_CHMAP_NA;
3902
3903 continue;
3904 }
3905
3906 chmap[count++] = snd_hdac_spk_to_chmap(spk);
3907 }
3908
3909 WARN_ON(count != channels);
3910}
3911
3912static int atihdmi_pin_hbr_setup(struct hda_codec *codec, hda_nid_t pin_nid,
3913 bool hbr)
3914{
3915 int hbr_ctl, hbr_ctl_new;
3916
3917 hbr_ctl = snd_hda_codec_read(codec, pin_nid, 0, ATI_VERB_GET_HBR_CONTROL, 0);
3918 if (hbr_ctl >= 0 && (hbr_ctl & ATI_HBR_CAPABLE)) {
3919 if (hbr)
3920 hbr_ctl_new = hbr_ctl | ATI_HBR_ENABLE;
3921 else
3922 hbr_ctl_new = hbr_ctl & ~ATI_HBR_ENABLE;
3923
3924 codec_dbg(codec,
3925 "atihdmi_pin_hbr_setup: NID=0x%x, %shbr-ctl=0x%x\n",
3926 pin_nid,
3927 hbr_ctl == hbr_ctl_new ? "" : "new-",
3928 hbr_ctl_new);
3929
3930 if (hbr_ctl != hbr_ctl_new)
3931 snd_hda_codec_write(codec, pin_nid, 0,
3932 ATI_VERB_SET_HBR_CONTROL,
3933 hbr_ctl_new);
3934
3935 } else if (hbr)
3936 return -EINVAL;
3937
3938 return 0;
3939}
3940
3941static int atihdmi_setup_stream(struct hda_codec *codec, hda_nid_t cvt_nid,
3942 hda_nid_t pin_nid, u32 stream_tag, int format)
3943{
3944
3945 if (is_amdhdmi_rev3_or_later(codec)) {
3946 int ramp_rate = 180; /* default as per AMD spec */
3947 /* disable ramp-up/down for non-pcm as per AMD spec */
3948 if (format & AC_FMT_TYPE_NON_PCM)
3949 ramp_rate = 0;
3950
3951 snd_hda_codec_write(codec, cvt_nid, 0, ATI_VERB_SET_RAMP_RATE, ramp_rate);
3952 }
3953
3954 return hdmi_setup_stream(codec, cvt_nid, pin_nid, stream_tag, format);
3955}
3956
3957
3958static int atihdmi_init(struct hda_codec *codec)
3959{
3960 struct hdmi_spec *spec = codec->spec;
3961 int pin_idx, err;
3962
3963 err = generic_hdmi_init(codec);
3964
3965 if (err)
3966 return err;
3967
3968 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
3969 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
3970
3971 /* make sure downmix information in infoframe is zero */
3972 snd_hda_codec_write(codec, per_pin->pin_nid, 0, ATI_VERB_SET_DOWNMIX_INFO, 0);
3973
3974 /* enable channel-wise remap mode if supported */
3975 if (has_amd_full_remap_support(codec))
3976 snd_hda_codec_write(codec, per_pin->pin_nid, 0,
3977 ATI_VERB_SET_MULTICHANNEL_MODE,
3978 ATI_MULTICHANNEL_MODE_SINGLE);
3979 }
3980
3981 return 0;
3982}
3983
3984/* map from pin NID to port; port is 0-based */
3985/* for AMD: assume widget NID starting from 3, with step 2 (3, 5, 7, ...) */
3986static int atihdmi_pin2port(void *audio_ptr, int pin_nid)
3987{
3988 return pin_nid / 2 - 1;
3989}
3990
3991/* reverse-map from port to pin NID: see above */
3992static int atihdmi_port2pin(struct hda_codec *codec, int port)
3993{
3994 return port * 2 + 3;
3995}
3996
3997static const struct drm_audio_component_audio_ops atihdmi_audio_ops = {
3998 .pin2port = atihdmi_pin2port,
3999 .pin_eld_notify = generic_acomp_pin_eld_notify,
4000 .master_bind = generic_acomp_master_bind,
4001 .master_unbind = generic_acomp_master_unbind,
4002};
4003
4004static int patch_atihdmi(struct hda_codec *codec)
4005{
4006 struct hdmi_spec *spec;
4007 struct hdmi_spec_per_cvt *per_cvt;
4008 int err, cvt_idx;
4009
4010 err = patch_generic_hdmi(codec);
4011
4012 if (err)
4013 return err;
4014
4015 codec->patch_ops.init = atihdmi_init;
4016
4017 spec = codec->spec;
4018
4019 spec->ops.pin_get_eld = atihdmi_pin_get_eld;
4020 spec->ops.pin_setup_infoframe = atihdmi_pin_setup_infoframe;
4021 spec->ops.pin_hbr_setup = atihdmi_pin_hbr_setup;
4022 spec->ops.setup_stream = atihdmi_setup_stream;
4023
4024 spec->chmap.ops.pin_get_slot_channel = atihdmi_pin_get_slot_channel;
4025 spec->chmap.ops.pin_set_slot_channel = atihdmi_pin_set_slot_channel;
4026
4027 if (!has_amd_full_remap_support(codec)) {
4028 /* override to ATI/AMD-specific versions with pairwise mapping */
4029 spec->chmap.ops.chmap_cea_alloc_validate_get_type =
4030 atihdmi_paired_chmap_cea_alloc_validate_get_type;
4031 spec->chmap.ops.cea_alloc_to_tlv_chmap =
4032 atihdmi_paired_cea_alloc_to_tlv_chmap;
4033 spec->chmap.ops.chmap_validate = atihdmi_paired_chmap_validate;
4034 }
4035
4036 /* ATI/AMD converters do not advertise all of their capabilities */
4037 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) {
4038 per_cvt = get_cvt(spec, cvt_idx);
4039 per_cvt->channels_max = max(per_cvt->channels_max, 8u);
4040 per_cvt->rates |= SUPPORTED_RATES;
4041 per_cvt->formats |= SUPPORTED_FORMATS;
4042 per_cvt->maxbps = max(per_cvt->maxbps, 24u);
4043 }
4044
4045 spec->chmap.channels_max = max(spec->chmap.channels_max, 8u);
4046
4047 /* AMD GPUs have neither EPSS nor CLKSTOP bits, hence preventing
4048 * the link-down as is. Tell the core to allow it.
4049 */
4050 codec->link_down_at_suspend = 1;
4051
4052 generic_acomp_init(codec, &atihdmi_audio_ops, atihdmi_port2pin);
4053
4054 return 0;
4055}
4056
4057/* VIA HDMI Implementation */
4058#define VIAHDMI_CVT_NID 0x02 /* audio converter1 */
4059#define VIAHDMI_PIN_NID 0x03 /* HDMI output pin1 */
4060
4061static int patch_via_hdmi(struct hda_codec *codec)
4062{
4063 return patch_simple_hdmi(codec, VIAHDMI_CVT_NID, VIAHDMI_PIN_NID);
4064}
4065
4066/*
4067 * patch entries
4068 */
4069static const struct hda_device_id snd_hda_id_hdmi[] = {
4070HDA_CODEC_ENTRY(0x1002793c, "RS600 HDMI", patch_atihdmi),
4071HDA_CODEC_ENTRY(0x10027919, "RS600 HDMI", patch_atihdmi),
4072HDA_CODEC_ENTRY(0x1002791a, "RS690/780 HDMI", patch_atihdmi),
4073HDA_CODEC_ENTRY(0x1002aa01, "R6xx HDMI", patch_atihdmi),
4074HDA_CODEC_ENTRY(0x10951390, "SiI1390 HDMI", patch_generic_hdmi),
4075HDA_CODEC_ENTRY(0x10951392, "SiI1392 HDMI", patch_generic_hdmi),
4076HDA_CODEC_ENTRY(0x17e80047, "Chrontel HDMI", patch_generic_hdmi),
4077HDA_CODEC_ENTRY(0x10de0001, "MCP73 HDMI", patch_nvhdmi_2ch),
4078HDA_CODEC_ENTRY(0x10de0002, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x),
4079HDA_CODEC_ENTRY(0x10de0003, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x),
4080HDA_CODEC_ENTRY(0x10de0004, "GPU 04 HDMI", patch_nvhdmi_8ch_7x),
4081HDA_CODEC_ENTRY(0x10de0005, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x),
4082HDA_CODEC_ENTRY(0x10de0006, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x),
4083HDA_CODEC_ENTRY(0x10de0007, "MCP79/7A HDMI", patch_nvhdmi_8ch_7x),
4084HDA_CODEC_ENTRY(0x10de0008, "GPU 08 HDMI/DP", patch_nvhdmi),
4085HDA_CODEC_ENTRY(0x10de0009, "GPU 09 HDMI/DP", patch_nvhdmi),
4086HDA_CODEC_ENTRY(0x10de000a, "GPU 0a HDMI/DP", patch_nvhdmi),
4087HDA_CODEC_ENTRY(0x10de000b, "GPU 0b HDMI/DP", patch_nvhdmi),
4088HDA_CODEC_ENTRY(0x10de000c, "MCP89 HDMI", patch_nvhdmi),
4089HDA_CODEC_ENTRY(0x10de000d, "GPU 0d HDMI/DP", patch_nvhdmi),
4090HDA_CODEC_ENTRY(0x10de0010, "GPU 10 HDMI/DP", patch_nvhdmi),
4091HDA_CODEC_ENTRY(0x10de0011, "GPU 11 HDMI/DP", patch_nvhdmi),
4092HDA_CODEC_ENTRY(0x10de0012, "GPU 12 HDMI/DP", patch_nvhdmi),
4093HDA_CODEC_ENTRY(0x10de0013, "GPU 13 HDMI/DP", patch_nvhdmi),
4094HDA_CODEC_ENTRY(0x10de0014, "GPU 14 HDMI/DP", patch_nvhdmi),
4095HDA_CODEC_ENTRY(0x10de0015, "GPU 15 HDMI/DP", patch_nvhdmi),
4096HDA_CODEC_ENTRY(0x10de0016, "GPU 16 HDMI/DP", patch_nvhdmi),
4097/* 17 is known to be absent */
4098HDA_CODEC_ENTRY(0x10de0018, "GPU 18 HDMI/DP", patch_nvhdmi),
4099HDA_CODEC_ENTRY(0x10de0019, "GPU 19 HDMI/DP", patch_nvhdmi),
4100HDA_CODEC_ENTRY(0x10de001a, "GPU 1a HDMI/DP", patch_nvhdmi),
4101HDA_CODEC_ENTRY(0x10de001b, "GPU 1b HDMI/DP", patch_nvhdmi),
4102HDA_CODEC_ENTRY(0x10de001c, "GPU 1c HDMI/DP", patch_nvhdmi),
4103HDA_CODEC_ENTRY(0x10de0020, "Tegra30 HDMI", patch_tegra_hdmi),
4104HDA_CODEC_ENTRY(0x10de0022, "Tegra114 HDMI", patch_tegra_hdmi),
4105HDA_CODEC_ENTRY(0x10de0028, "Tegra124 HDMI", patch_tegra_hdmi),
4106HDA_CODEC_ENTRY(0x10de0029, "Tegra210 HDMI/DP", patch_tegra_hdmi),
4107HDA_CODEC_ENTRY(0x10de002d, "Tegra186 HDMI/DP0", patch_tegra_hdmi),
4108HDA_CODEC_ENTRY(0x10de002e, "Tegra186 HDMI/DP1", patch_tegra_hdmi),
4109HDA_CODEC_ENTRY(0x10de002f, "Tegra194 HDMI/DP2", patch_tegra_hdmi),
4110HDA_CODEC_ENTRY(0x10de0030, "Tegra194 HDMI/DP3", patch_tegra_hdmi),
4111HDA_CODEC_ENTRY(0x10de0040, "GPU 40 HDMI/DP", patch_nvhdmi),
4112HDA_CODEC_ENTRY(0x10de0041, "GPU 41 HDMI/DP", patch_nvhdmi),
4113HDA_CODEC_ENTRY(0x10de0042, "GPU 42 HDMI/DP", patch_nvhdmi),
4114HDA_CODEC_ENTRY(0x10de0043, "GPU 43 HDMI/DP", patch_nvhdmi),
4115HDA_CODEC_ENTRY(0x10de0044, "GPU 44 HDMI/DP", patch_nvhdmi),
4116HDA_CODEC_ENTRY(0x10de0045, "GPU 45 HDMI/DP", patch_nvhdmi),
4117HDA_CODEC_ENTRY(0x10de0050, "GPU 50 HDMI/DP", patch_nvhdmi),
4118HDA_CODEC_ENTRY(0x10de0051, "GPU 51 HDMI/DP", patch_nvhdmi),
4119HDA_CODEC_ENTRY(0x10de0052, "GPU 52 HDMI/DP", patch_nvhdmi),
4120HDA_CODEC_ENTRY(0x10de0060, "GPU 60 HDMI/DP", patch_nvhdmi),
4121HDA_CODEC_ENTRY(0x10de0061, "GPU 61 HDMI/DP", patch_nvhdmi),
4122HDA_CODEC_ENTRY(0x10de0062, "GPU 62 HDMI/DP", patch_nvhdmi),
4123HDA_CODEC_ENTRY(0x10de0067, "MCP67 HDMI", patch_nvhdmi_2ch),
4124HDA_CODEC_ENTRY(0x10de0070, "GPU 70 HDMI/DP", patch_nvhdmi),
4125HDA_CODEC_ENTRY(0x10de0071, "GPU 71 HDMI/DP", patch_nvhdmi),
4126HDA_CODEC_ENTRY(0x10de0072, "GPU 72 HDMI/DP", patch_nvhdmi),
4127HDA_CODEC_ENTRY(0x10de0073, "GPU 73 HDMI/DP", patch_nvhdmi),
4128HDA_CODEC_ENTRY(0x10de0074, "GPU 74 HDMI/DP", patch_nvhdmi),
4129HDA_CODEC_ENTRY(0x10de0076, "GPU 76 HDMI/DP", patch_nvhdmi),
4130HDA_CODEC_ENTRY(0x10de007b, "GPU 7b HDMI/DP", patch_nvhdmi),
4131HDA_CODEC_ENTRY(0x10de007c, "GPU 7c HDMI/DP", patch_nvhdmi),
4132HDA_CODEC_ENTRY(0x10de007d, "GPU 7d HDMI/DP", patch_nvhdmi),
4133HDA_CODEC_ENTRY(0x10de007e, "GPU 7e HDMI/DP", patch_nvhdmi),
4134HDA_CODEC_ENTRY(0x10de0080, "GPU 80 HDMI/DP", patch_nvhdmi),
4135HDA_CODEC_ENTRY(0x10de0081, "GPU 81 HDMI/DP", patch_nvhdmi),
4136HDA_CODEC_ENTRY(0x10de0082, "GPU 82 HDMI/DP", patch_nvhdmi),
4137HDA_CODEC_ENTRY(0x10de0083, "GPU 83 HDMI/DP", patch_nvhdmi),
4138HDA_CODEC_ENTRY(0x10de0084, "GPU 84 HDMI/DP", patch_nvhdmi),
4139HDA_CODEC_ENTRY(0x10de0090, "GPU 90 HDMI/DP", patch_nvhdmi),
4140HDA_CODEC_ENTRY(0x10de0091, "GPU 91 HDMI/DP", patch_nvhdmi),
4141HDA_CODEC_ENTRY(0x10de0092, "GPU 92 HDMI/DP", patch_nvhdmi),
4142HDA_CODEC_ENTRY(0x10de0093, "GPU 93 HDMI/DP", patch_nvhdmi),
4143HDA_CODEC_ENTRY(0x10de0094, "GPU 94 HDMI/DP", patch_nvhdmi),
4144HDA_CODEC_ENTRY(0x10de0095, "GPU 95 HDMI/DP", patch_nvhdmi),
4145HDA_CODEC_ENTRY(0x10de0097, "GPU 97 HDMI/DP", patch_nvhdmi),
4146HDA_CODEC_ENTRY(0x10de0098, "GPU 98 HDMI/DP", patch_nvhdmi),
4147HDA_CODEC_ENTRY(0x10de0099, "GPU 99 HDMI/DP", patch_nvhdmi),
4148HDA_CODEC_ENTRY(0x10de8001, "MCP73 HDMI", patch_nvhdmi_2ch),
4149HDA_CODEC_ENTRY(0x10de8067, "MCP67/68 HDMI", patch_nvhdmi_2ch),
4150HDA_CODEC_ENTRY(0x11069f80, "VX900 HDMI/DP", patch_via_hdmi),
4151HDA_CODEC_ENTRY(0x11069f81, "VX900 HDMI/DP", patch_via_hdmi),
4152HDA_CODEC_ENTRY(0x11069f84, "VX11 HDMI/DP", patch_generic_hdmi),
4153HDA_CODEC_ENTRY(0x11069f85, "VX11 HDMI/DP", patch_generic_hdmi),
4154HDA_CODEC_ENTRY(0x80860054, "IbexPeak HDMI", patch_i915_cpt_hdmi),
4155HDA_CODEC_ENTRY(0x80862800, "Geminilake HDMI", patch_i915_glk_hdmi),
4156HDA_CODEC_ENTRY(0x80862801, "Bearlake HDMI", patch_generic_hdmi),
4157HDA_CODEC_ENTRY(0x80862802, "Cantiga HDMI", patch_generic_hdmi),
4158HDA_CODEC_ENTRY(0x80862803, "Eaglelake HDMI", patch_generic_hdmi),
4159HDA_CODEC_ENTRY(0x80862804, "IbexPeak HDMI", patch_i915_cpt_hdmi),
4160HDA_CODEC_ENTRY(0x80862805, "CougarPoint HDMI", patch_i915_cpt_hdmi),
4161HDA_CODEC_ENTRY(0x80862806, "PantherPoint HDMI", patch_i915_cpt_hdmi),
4162HDA_CODEC_ENTRY(0x80862807, "Haswell HDMI", patch_i915_hsw_hdmi),
4163HDA_CODEC_ENTRY(0x80862808, "Broadwell HDMI", patch_i915_hsw_hdmi),
4164HDA_CODEC_ENTRY(0x80862809, "Skylake HDMI", patch_i915_hsw_hdmi),
4165HDA_CODEC_ENTRY(0x8086280a, "Broxton HDMI", patch_i915_hsw_hdmi),
4166HDA_CODEC_ENTRY(0x8086280b, "Kabylake HDMI", patch_i915_hsw_hdmi),
4167HDA_CODEC_ENTRY(0x8086280c, "Cannonlake HDMI", patch_i915_glk_hdmi),
4168HDA_CODEC_ENTRY(0x8086280d, "Geminilake HDMI", patch_i915_glk_hdmi),
4169HDA_CODEC_ENTRY(0x8086280f, "Icelake HDMI", patch_i915_icl_hdmi),
4170HDA_CODEC_ENTRY(0x80862812, "Tigerlake HDMI", patch_i915_tgl_hdmi),
4171HDA_CODEC_ENTRY(0x80862880, "CedarTrail HDMI", patch_generic_hdmi),
4172HDA_CODEC_ENTRY(0x80862882, "Valleyview2 HDMI", patch_i915_byt_hdmi),
4173HDA_CODEC_ENTRY(0x80862883, "Braswell HDMI", patch_i915_byt_hdmi),
4174HDA_CODEC_ENTRY(0x808629fb, "Crestline HDMI", patch_generic_hdmi),
4175/* special ID for generic HDMI */
4176HDA_CODEC_ENTRY(HDA_CODEC_ID_GENERIC_HDMI, "Generic HDMI", patch_generic_hdmi),
4177{} /* terminator */
4178};
4179MODULE_DEVICE_TABLE(hdaudio, snd_hda_id_hdmi);
4180
4181MODULE_LICENSE("GPL");
4182MODULE_DESCRIPTION("HDMI HD-audio codec");
4183MODULE_ALIAS("snd-hda-codec-intelhdmi");
4184MODULE_ALIAS("snd-hda-codec-nvhdmi");
4185MODULE_ALIAS("snd-hda-codec-atihdmi");
4186
4187static struct hda_codec_driver hdmi_driver = {
4188 .id = snd_hda_id_hdmi,
4189};
4190
4191module_hda_codec_driver(hdmi_driver);