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1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 *
4 * patch_hdmi.c - routines for HDMI/DisplayPort codecs
5 *
6 * Copyright(c) 2008-2010 Intel Corporation. All rights reserved.
7 * Copyright (c) 2006 ATI Technologies Inc.
8 * Copyright (c) 2008 NVIDIA Corp. All rights reserved.
9 * Copyright (c) 2008 Wei Ni <wni@nvidia.com>
10 * Copyright (c) 2013 Anssi Hannula <anssi.hannula@iki.fi>
11 *
12 * Authors:
13 * Wu Fengguang <wfg@linux.intel.com>
14 *
15 * Maintained by:
16 * Wu Fengguang <wfg@linux.intel.com>
17 */
18
19#include <linux/init.h>
20#include <linux/delay.h>
21#include <linux/pci.h>
22#include <linux/slab.h>
23#include <linux/module.h>
24#include <linux/pm_runtime.h>
25#include <sound/core.h>
26#include <sound/jack.h>
27#include <sound/asoundef.h>
28#include <sound/tlv.h>
29#include <sound/hdaudio.h>
30#include <sound/hda_i915.h>
31#include <sound/hda_chmap.h>
32#include <sound/hda_codec.h>
33#include "hda_local.h"
34#include "hda_jack.h"
35#include "hda_controller.h"
36
37static bool static_hdmi_pcm;
38module_param(static_hdmi_pcm, bool, 0644);
39MODULE_PARM_DESC(static_hdmi_pcm, "Don't restrict PCM parameters per ELD info");
40
41static bool enable_acomp = true;
42module_param(enable_acomp, bool, 0444);
43MODULE_PARM_DESC(enable_acomp, "Enable audio component binding (default=yes)");
44
45static bool enable_silent_stream =
46IS_ENABLED(CONFIG_SND_HDA_INTEL_HDMI_SILENT_STREAM);
47module_param(enable_silent_stream, bool, 0644);
48MODULE_PARM_DESC(enable_silent_stream, "Enable Silent Stream for HDMI devices");
49
50struct hdmi_spec_per_cvt {
51 hda_nid_t cvt_nid;
52 int assigned;
53 unsigned int channels_min;
54 unsigned int channels_max;
55 u32 rates;
56 u64 formats;
57 unsigned int maxbps;
58};
59
60/* max. connections to a widget */
61#define HDA_MAX_CONNECTIONS 32
62
63struct hdmi_spec_per_pin {
64 hda_nid_t pin_nid;
65 int dev_id;
66 /* pin idx, different device entries on the same pin use the same idx */
67 int pin_nid_idx;
68 int num_mux_nids;
69 hda_nid_t mux_nids[HDA_MAX_CONNECTIONS];
70 int mux_idx;
71 hda_nid_t cvt_nid;
72
73 struct hda_codec *codec;
74 struct hdmi_eld sink_eld;
75 struct mutex lock;
76 struct delayed_work work;
77 struct hdmi_pcm *pcm; /* pointer to spec->pcm_rec[n] dynamically*/
78 int pcm_idx; /* which pcm is attached. -1 means no pcm is attached */
79 int repoll_count;
80 bool setup; /* the stream has been set up by prepare callback */
81 int channels; /* current number of channels */
82 bool non_pcm;
83 bool chmap_set; /* channel-map override by ALSA API? */
84 unsigned char chmap[8]; /* ALSA API channel-map */
85#ifdef CONFIG_SND_PROC_FS
86 struct snd_info_entry *proc_entry;
87#endif
88};
89
90/* operations used by generic code that can be overridden by patches */
91struct hdmi_ops {
92 int (*pin_get_eld)(struct hda_codec *codec, hda_nid_t pin_nid,
93 int dev_id, unsigned char *buf, int *eld_size);
94
95 void (*pin_setup_infoframe)(struct hda_codec *codec, hda_nid_t pin_nid,
96 int dev_id,
97 int ca, int active_channels, int conn_type);
98
99 /* enable/disable HBR (HD passthrough) */
100 int (*pin_hbr_setup)(struct hda_codec *codec, hda_nid_t pin_nid,
101 int dev_id, bool hbr);
102
103 int (*setup_stream)(struct hda_codec *codec, hda_nid_t cvt_nid,
104 hda_nid_t pin_nid, int dev_id, u32 stream_tag,
105 int format);
106
107 void (*pin_cvt_fixup)(struct hda_codec *codec,
108 struct hdmi_spec_per_pin *per_pin,
109 hda_nid_t cvt_nid);
110};
111
112struct hdmi_pcm {
113 struct hda_pcm *pcm;
114 struct snd_jack *jack;
115 struct snd_kcontrol *eld_ctl;
116};
117
118struct hdmi_spec {
119 struct hda_codec *codec;
120 int num_cvts;
121 struct snd_array cvts; /* struct hdmi_spec_per_cvt */
122 hda_nid_t cvt_nids[4]; /* only for haswell fix */
123
124 /*
125 * num_pins is the number of virtual pins
126 * for example, there are 3 pins, and each pin
127 * has 4 device entries, then the num_pins is 12
128 */
129 int num_pins;
130 /*
131 * num_nids is the number of real pins
132 * In the above example, num_nids is 3
133 */
134 int num_nids;
135 /*
136 * dev_num is the number of device entries
137 * on each pin.
138 * In the above example, dev_num is 4
139 */
140 int dev_num;
141 struct snd_array pins; /* struct hdmi_spec_per_pin */
142 struct hdmi_pcm pcm_rec[16];
143 struct mutex pcm_lock;
144 struct mutex bind_lock; /* for audio component binding */
145 /* pcm_bitmap means which pcms have been assigned to pins*/
146 unsigned long pcm_bitmap;
147 int pcm_used; /* counter of pcm_rec[] */
148 /* bitmap shows whether the pcm is opened in user space
149 * bit 0 means the first playback PCM (PCM3);
150 * bit 1 means the second playback PCM, and so on.
151 */
152 unsigned long pcm_in_use;
153
154 struct hdmi_eld temp_eld;
155 struct hdmi_ops ops;
156
157 bool dyn_pin_out;
158 bool dyn_pcm_assign;
159 bool intel_hsw_fixup; /* apply Intel platform-specific fixups */
160 /*
161 * Non-generic VIA/NVIDIA specific
162 */
163 struct hda_multi_out multiout;
164 struct hda_pcm_stream pcm_playback;
165
166 bool use_acomp_notifier; /* use eld_notify callback for hotplug */
167 bool acomp_registered; /* audio component registered in this driver */
168 bool force_connect; /* force connectivity */
169 struct drm_audio_component_audio_ops drm_audio_ops;
170 int (*port2pin)(struct hda_codec *, int); /* reverse port/pin mapping */
171
172 struct hdac_chmap chmap;
173 hda_nid_t vendor_nid;
174 const int *port_map;
175 int port_num;
176 bool send_silent_stream; /* Flag to enable silent stream feature */
177};
178
179#ifdef CONFIG_SND_HDA_COMPONENT
180static inline bool codec_has_acomp(struct hda_codec *codec)
181{
182 struct hdmi_spec *spec = codec->spec;
183 return spec->use_acomp_notifier;
184}
185#else
186#define codec_has_acomp(codec) false
187#endif
188
189struct hdmi_audio_infoframe {
190 u8 type; /* 0x84 */
191 u8 ver; /* 0x01 */
192 u8 len; /* 0x0a */
193
194 u8 checksum;
195
196 u8 CC02_CT47; /* CC in bits 0:2, CT in 4:7 */
197 u8 SS01_SF24;
198 u8 CXT04;
199 u8 CA;
200 u8 LFEPBL01_LSV36_DM_INH7;
201};
202
203struct dp_audio_infoframe {
204 u8 type; /* 0x84 */
205 u8 len; /* 0x1b */
206 u8 ver; /* 0x11 << 2 */
207
208 u8 CC02_CT47; /* match with HDMI infoframe from this on */
209 u8 SS01_SF24;
210 u8 CXT04;
211 u8 CA;
212 u8 LFEPBL01_LSV36_DM_INH7;
213};
214
215union audio_infoframe {
216 struct hdmi_audio_infoframe hdmi;
217 struct dp_audio_infoframe dp;
218 u8 bytes[0];
219};
220
221/*
222 * HDMI routines
223 */
224
225#define get_pin(spec, idx) \
226 ((struct hdmi_spec_per_pin *)snd_array_elem(&spec->pins, idx))
227#define get_cvt(spec, idx) \
228 ((struct hdmi_spec_per_cvt *)snd_array_elem(&spec->cvts, idx))
229/* obtain hdmi_pcm object assigned to idx */
230#define get_hdmi_pcm(spec, idx) (&(spec)->pcm_rec[idx])
231/* obtain hda_pcm object assigned to idx */
232#define get_pcm_rec(spec, idx) (get_hdmi_pcm(spec, idx)->pcm)
233
234static int pin_id_to_pin_index(struct hda_codec *codec,
235 hda_nid_t pin_nid, int dev_id)
236{
237 struct hdmi_spec *spec = codec->spec;
238 int pin_idx;
239 struct hdmi_spec_per_pin *per_pin;
240
241 /*
242 * (dev_id == -1) means it is NON-MST pin
243 * return the first virtual pin on this port
244 */
245 if (dev_id == -1)
246 dev_id = 0;
247
248 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
249 per_pin = get_pin(spec, pin_idx);
250 if ((per_pin->pin_nid == pin_nid) &&
251 (per_pin->dev_id == dev_id))
252 return pin_idx;
253 }
254
255 codec_warn(codec, "HDMI: pin nid %d not registered\n", pin_nid);
256 return -EINVAL;
257}
258
259static int hinfo_to_pcm_index(struct hda_codec *codec,
260 struct hda_pcm_stream *hinfo)
261{
262 struct hdmi_spec *spec = codec->spec;
263 int pcm_idx;
264
265 for (pcm_idx = 0; pcm_idx < spec->pcm_used; pcm_idx++)
266 if (get_pcm_rec(spec, pcm_idx)->stream == hinfo)
267 return pcm_idx;
268
269 codec_warn(codec, "HDMI: hinfo %p not tied to a PCM\n", hinfo);
270 return -EINVAL;
271}
272
273static int hinfo_to_pin_index(struct hda_codec *codec,
274 struct hda_pcm_stream *hinfo)
275{
276 struct hdmi_spec *spec = codec->spec;
277 struct hdmi_spec_per_pin *per_pin;
278 int pin_idx;
279
280 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
281 per_pin = get_pin(spec, pin_idx);
282 if (per_pin->pcm &&
283 per_pin->pcm->pcm->stream == hinfo)
284 return pin_idx;
285 }
286
287 codec_dbg(codec, "HDMI: hinfo %p (pcm %d) not registered\n", hinfo,
288 hinfo_to_pcm_index(codec, hinfo));
289 return -EINVAL;
290}
291
292static struct hdmi_spec_per_pin *pcm_idx_to_pin(struct hdmi_spec *spec,
293 int pcm_idx)
294{
295 int i;
296 struct hdmi_spec_per_pin *per_pin;
297
298 for (i = 0; i < spec->num_pins; i++) {
299 per_pin = get_pin(spec, i);
300 if (per_pin->pcm_idx == pcm_idx)
301 return per_pin;
302 }
303 return NULL;
304}
305
306static int cvt_nid_to_cvt_index(struct hda_codec *codec, hda_nid_t cvt_nid)
307{
308 struct hdmi_spec *spec = codec->spec;
309 int cvt_idx;
310
311 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++)
312 if (get_cvt(spec, cvt_idx)->cvt_nid == cvt_nid)
313 return cvt_idx;
314
315 codec_warn(codec, "HDMI: cvt nid %d not registered\n", cvt_nid);
316 return -EINVAL;
317}
318
319static int hdmi_eld_ctl_info(struct snd_kcontrol *kcontrol,
320 struct snd_ctl_elem_info *uinfo)
321{
322 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
323 struct hdmi_spec *spec = codec->spec;
324 struct hdmi_spec_per_pin *per_pin;
325 struct hdmi_eld *eld;
326 int pcm_idx;
327
328 uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES;
329
330 pcm_idx = kcontrol->private_value;
331 mutex_lock(&spec->pcm_lock);
332 per_pin = pcm_idx_to_pin(spec, pcm_idx);
333 if (!per_pin) {
334 /* no pin is bound to the pcm */
335 uinfo->count = 0;
336 goto unlock;
337 }
338 eld = &per_pin->sink_eld;
339 uinfo->count = eld->eld_valid ? eld->eld_size : 0;
340
341 unlock:
342 mutex_unlock(&spec->pcm_lock);
343 return 0;
344}
345
346static int hdmi_eld_ctl_get(struct snd_kcontrol *kcontrol,
347 struct snd_ctl_elem_value *ucontrol)
348{
349 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
350 struct hdmi_spec *spec = codec->spec;
351 struct hdmi_spec_per_pin *per_pin;
352 struct hdmi_eld *eld;
353 int pcm_idx;
354 int err = 0;
355
356 pcm_idx = kcontrol->private_value;
357 mutex_lock(&spec->pcm_lock);
358 per_pin = pcm_idx_to_pin(spec, pcm_idx);
359 if (!per_pin) {
360 /* no pin is bound to the pcm */
361 memset(ucontrol->value.bytes.data, 0,
362 ARRAY_SIZE(ucontrol->value.bytes.data));
363 goto unlock;
364 }
365
366 eld = &per_pin->sink_eld;
367 if (eld->eld_size > ARRAY_SIZE(ucontrol->value.bytes.data) ||
368 eld->eld_size > ELD_MAX_SIZE) {
369 snd_BUG();
370 err = -EINVAL;
371 goto unlock;
372 }
373
374 memset(ucontrol->value.bytes.data, 0,
375 ARRAY_SIZE(ucontrol->value.bytes.data));
376 if (eld->eld_valid)
377 memcpy(ucontrol->value.bytes.data, eld->eld_buffer,
378 eld->eld_size);
379
380 unlock:
381 mutex_unlock(&spec->pcm_lock);
382 return err;
383}
384
385static const struct snd_kcontrol_new eld_bytes_ctl = {
386 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE |
387 SNDRV_CTL_ELEM_ACCESS_SKIP_CHECK,
388 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
389 .name = "ELD",
390 .info = hdmi_eld_ctl_info,
391 .get = hdmi_eld_ctl_get,
392};
393
394static int hdmi_create_eld_ctl(struct hda_codec *codec, int pcm_idx,
395 int device)
396{
397 struct snd_kcontrol *kctl;
398 struct hdmi_spec *spec = codec->spec;
399 int err;
400
401 kctl = snd_ctl_new1(&eld_bytes_ctl, codec);
402 if (!kctl)
403 return -ENOMEM;
404 kctl->private_value = pcm_idx;
405 kctl->id.device = device;
406
407 /* no pin nid is associated with the kctl now
408 * tbd: associate pin nid to eld ctl later
409 */
410 err = snd_hda_ctl_add(codec, 0, kctl);
411 if (err < 0)
412 return err;
413
414 get_hdmi_pcm(spec, pcm_idx)->eld_ctl = kctl;
415 return 0;
416}
417
418#ifdef BE_PARANOID
419static void hdmi_get_dip_index(struct hda_codec *codec, hda_nid_t pin_nid,
420 int *packet_index, int *byte_index)
421{
422 int val;
423
424 val = snd_hda_codec_read(codec, pin_nid, 0,
425 AC_VERB_GET_HDMI_DIP_INDEX, 0);
426
427 *packet_index = val >> 5;
428 *byte_index = val & 0x1f;
429}
430#endif
431
432static void hdmi_set_dip_index(struct hda_codec *codec, hda_nid_t pin_nid,
433 int packet_index, int byte_index)
434{
435 int val;
436
437 val = (packet_index << 5) | (byte_index & 0x1f);
438
439 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_INDEX, val);
440}
441
442static void hdmi_write_dip_byte(struct hda_codec *codec, hda_nid_t pin_nid,
443 unsigned char val)
444{
445 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_DATA, val);
446}
447
448static void hdmi_init_pin(struct hda_codec *codec, hda_nid_t pin_nid)
449{
450 struct hdmi_spec *spec = codec->spec;
451 int pin_out;
452
453 /* Unmute */
454 if (get_wcaps(codec, pin_nid) & AC_WCAP_OUT_AMP)
455 snd_hda_codec_write(codec, pin_nid, 0,
456 AC_VERB_SET_AMP_GAIN_MUTE, AMP_OUT_UNMUTE);
457
458 if (spec->dyn_pin_out)
459 /* Disable pin out until stream is active */
460 pin_out = 0;
461 else
462 /* Enable pin out: some machines with GM965 gets broken output
463 * when the pin is disabled or changed while using with HDMI
464 */
465 pin_out = PIN_OUT;
466
467 snd_hda_codec_write(codec, pin_nid, 0,
468 AC_VERB_SET_PIN_WIDGET_CONTROL, pin_out);
469}
470
471/*
472 * ELD proc files
473 */
474
475#ifdef CONFIG_SND_PROC_FS
476static void print_eld_info(struct snd_info_entry *entry,
477 struct snd_info_buffer *buffer)
478{
479 struct hdmi_spec_per_pin *per_pin = entry->private_data;
480
481 mutex_lock(&per_pin->lock);
482 snd_hdmi_print_eld_info(&per_pin->sink_eld, buffer);
483 mutex_unlock(&per_pin->lock);
484}
485
486static void write_eld_info(struct snd_info_entry *entry,
487 struct snd_info_buffer *buffer)
488{
489 struct hdmi_spec_per_pin *per_pin = entry->private_data;
490
491 mutex_lock(&per_pin->lock);
492 snd_hdmi_write_eld_info(&per_pin->sink_eld, buffer);
493 mutex_unlock(&per_pin->lock);
494}
495
496static int eld_proc_new(struct hdmi_spec_per_pin *per_pin, int index)
497{
498 char name[32];
499 struct hda_codec *codec = per_pin->codec;
500 struct snd_info_entry *entry;
501 int err;
502
503 snprintf(name, sizeof(name), "eld#%d.%d", codec->addr, index);
504 err = snd_card_proc_new(codec->card, name, &entry);
505 if (err < 0)
506 return err;
507
508 snd_info_set_text_ops(entry, per_pin, print_eld_info);
509 entry->c.text.write = write_eld_info;
510 entry->mode |= 0200;
511 per_pin->proc_entry = entry;
512
513 return 0;
514}
515
516static void eld_proc_free(struct hdmi_spec_per_pin *per_pin)
517{
518 if (!per_pin->codec->bus->shutdown) {
519 snd_info_free_entry(per_pin->proc_entry);
520 per_pin->proc_entry = NULL;
521 }
522}
523#else
524static inline int eld_proc_new(struct hdmi_spec_per_pin *per_pin,
525 int index)
526{
527 return 0;
528}
529static inline void eld_proc_free(struct hdmi_spec_per_pin *per_pin)
530{
531}
532#endif
533
534/*
535 * Audio InfoFrame routines
536 */
537
538/*
539 * Enable Audio InfoFrame Transmission
540 */
541static void hdmi_start_infoframe_trans(struct hda_codec *codec,
542 hda_nid_t pin_nid)
543{
544 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
545 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_XMIT,
546 AC_DIPXMIT_BEST);
547}
548
549/*
550 * Disable Audio InfoFrame Transmission
551 */
552static void hdmi_stop_infoframe_trans(struct hda_codec *codec,
553 hda_nid_t pin_nid)
554{
555 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
556 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_XMIT,
557 AC_DIPXMIT_DISABLE);
558}
559
560static void hdmi_debug_dip_size(struct hda_codec *codec, hda_nid_t pin_nid)
561{
562#ifdef CONFIG_SND_DEBUG_VERBOSE
563 int i;
564 int size;
565
566 size = snd_hdmi_get_eld_size(codec, pin_nid);
567 codec_dbg(codec, "HDMI: ELD buf size is %d\n", size);
568
569 for (i = 0; i < 8; i++) {
570 size = snd_hda_codec_read(codec, pin_nid, 0,
571 AC_VERB_GET_HDMI_DIP_SIZE, i);
572 codec_dbg(codec, "HDMI: DIP GP[%d] buf size is %d\n", i, size);
573 }
574#endif
575}
576
577static void hdmi_clear_dip_buffers(struct hda_codec *codec, hda_nid_t pin_nid)
578{
579#ifdef BE_PARANOID
580 int i, j;
581 int size;
582 int pi, bi;
583 for (i = 0; i < 8; i++) {
584 size = snd_hda_codec_read(codec, pin_nid, 0,
585 AC_VERB_GET_HDMI_DIP_SIZE, i);
586 if (size == 0)
587 continue;
588
589 hdmi_set_dip_index(codec, pin_nid, i, 0x0);
590 for (j = 1; j < 1000; j++) {
591 hdmi_write_dip_byte(codec, pin_nid, 0x0);
592 hdmi_get_dip_index(codec, pin_nid, &pi, &bi);
593 if (pi != i)
594 codec_dbg(codec, "dip index %d: %d != %d\n",
595 bi, pi, i);
596 if (bi == 0) /* byte index wrapped around */
597 break;
598 }
599 codec_dbg(codec,
600 "HDMI: DIP GP[%d] buf reported size=%d, written=%d\n",
601 i, size, j);
602 }
603#endif
604}
605
606static void hdmi_checksum_audio_infoframe(struct hdmi_audio_infoframe *hdmi_ai)
607{
608 u8 *bytes = (u8 *)hdmi_ai;
609 u8 sum = 0;
610 int i;
611
612 hdmi_ai->checksum = 0;
613
614 for (i = 0; i < sizeof(*hdmi_ai); i++)
615 sum += bytes[i];
616
617 hdmi_ai->checksum = -sum;
618}
619
620static void hdmi_fill_audio_infoframe(struct hda_codec *codec,
621 hda_nid_t pin_nid,
622 u8 *dip, int size)
623{
624 int i;
625
626 hdmi_debug_dip_size(codec, pin_nid);
627 hdmi_clear_dip_buffers(codec, pin_nid); /* be paranoid */
628
629 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
630 for (i = 0; i < size; i++)
631 hdmi_write_dip_byte(codec, pin_nid, dip[i]);
632}
633
634static bool hdmi_infoframe_uptodate(struct hda_codec *codec, hda_nid_t pin_nid,
635 u8 *dip, int size)
636{
637 u8 val;
638 int i;
639
640 if (snd_hda_codec_read(codec, pin_nid, 0, AC_VERB_GET_HDMI_DIP_XMIT, 0)
641 != AC_DIPXMIT_BEST)
642 return false;
643
644 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
645 for (i = 0; i < size; i++) {
646 val = snd_hda_codec_read(codec, pin_nid, 0,
647 AC_VERB_GET_HDMI_DIP_DATA, 0);
648 if (val != dip[i])
649 return false;
650 }
651
652 return true;
653}
654
655static int hdmi_pin_get_eld(struct hda_codec *codec, hda_nid_t nid,
656 int dev_id, unsigned char *buf, int *eld_size)
657{
658 snd_hda_set_dev_select(codec, nid, dev_id);
659
660 return snd_hdmi_get_eld(codec, nid, buf, eld_size);
661}
662
663static void hdmi_pin_setup_infoframe(struct hda_codec *codec,
664 hda_nid_t pin_nid, int dev_id,
665 int ca, int active_channels,
666 int conn_type)
667{
668 union audio_infoframe ai;
669
670 memset(&ai, 0, sizeof(ai));
671 if (conn_type == 0) { /* HDMI */
672 struct hdmi_audio_infoframe *hdmi_ai = &ai.hdmi;
673
674 hdmi_ai->type = 0x84;
675 hdmi_ai->ver = 0x01;
676 hdmi_ai->len = 0x0a;
677 hdmi_ai->CC02_CT47 = active_channels - 1;
678 hdmi_ai->CA = ca;
679 hdmi_checksum_audio_infoframe(hdmi_ai);
680 } else if (conn_type == 1) { /* DisplayPort */
681 struct dp_audio_infoframe *dp_ai = &ai.dp;
682
683 dp_ai->type = 0x84;
684 dp_ai->len = 0x1b;
685 dp_ai->ver = 0x11 << 2;
686 dp_ai->CC02_CT47 = active_channels - 1;
687 dp_ai->CA = ca;
688 } else {
689 codec_dbg(codec, "HDMI: unknown connection type at pin %d\n",
690 pin_nid);
691 return;
692 }
693
694 snd_hda_set_dev_select(codec, pin_nid, dev_id);
695
696 /*
697 * sizeof(ai) is used instead of sizeof(*hdmi_ai) or
698 * sizeof(*dp_ai) to avoid partial match/update problems when
699 * the user switches between HDMI/DP monitors.
700 */
701 if (!hdmi_infoframe_uptodate(codec, pin_nid, ai.bytes,
702 sizeof(ai))) {
703 codec_dbg(codec,
704 "hdmi_pin_setup_infoframe: pin=%d channels=%d ca=0x%02x\n",
705 pin_nid,
706 active_channels, ca);
707 hdmi_stop_infoframe_trans(codec, pin_nid);
708 hdmi_fill_audio_infoframe(codec, pin_nid,
709 ai.bytes, sizeof(ai));
710 hdmi_start_infoframe_trans(codec, pin_nid);
711 }
712}
713
714static void hdmi_setup_audio_infoframe(struct hda_codec *codec,
715 struct hdmi_spec_per_pin *per_pin,
716 bool non_pcm)
717{
718 struct hdmi_spec *spec = codec->spec;
719 struct hdac_chmap *chmap = &spec->chmap;
720 hda_nid_t pin_nid = per_pin->pin_nid;
721 int dev_id = per_pin->dev_id;
722 int channels = per_pin->channels;
723 int active_channels;
724 struct hdmi_eld *eld;
725 int ca;
726
727 if (!channels)
728 return;
729
730 snd_hda_set_dev_select(codec, pin_nid, dev_id);
731
732 /* some HW (e.g. HSW+) needs reprogramming the amp at each time */
733 if (get_wcaps(codec, pin_nid) & AC_WCAP_OUT_AMP)
734 snd_hda_codec_write(codec, pin_nid, 0,
735 AC_VERB_SET_AMP_GAIN_MUTE,
736 AMP_OUT_UNMUTE);
737
738 eld = &per_pin->sink_eld;
739
740 ca = snd_hdac_channel_allocation(&codec->core,
741 eld->info.spk_alloc, channels,
742 per_pin->chmap_set, non_pcm, per_pin->chmap);
743
744 active_channels = snd_hdac_get_active_channels(ca);
745
746 chmap->ops.set_channel_count(&codec->core, per_pin->cvt_nid,
747 active_channels);
748
749 /*
750 * always configure channel mapping, it may have been changed by the
751 * user in the meantime
752 */
753 snd_hdac_setup_channel_mapping(&spec->chmap,
754 pin_nid, non_pcm, ca, channels,
755 per_pin->chmap, per_pin->chmap_set);
756
757 spec->ops.pin_setup_infoframe(codec, pin_nid, dev_id,
758 ca, active_channels, eld->info.conn_type);
759
760 per_pin->non_pcm = non_pcm;
761}
762
763/*
764 * Unsolicited events
765 */
766
767static void hdmi_present_sense(struct hdmi_spec_per_pin *per_pin, int repoll);
768
769static void check_presence_and_report(struct hda_codec *codec, hda_nid_t nid,
770 int dev_id)
771{
772 struct hdmi_spec *spec = codec->spec;
773 int pin_idx = pin_id_to_pin_index(codec, nid, dev_id);
774
775 if (pin_idx < 0)
776 return;
777 mutex_lock(&spec->pcm_lock);
778 hdmi_present_sense(get_pin(spec, pin_idx), 1);
779 mutex_unlock(&spec->pcm_lock);
780}
781
782static void jack_callback(struct hda_codec *codec,
783 struct hda_jack_callback *jack)
784{
785 /* stop polling when notification is enabled */
786 if (codec_has_acomp(codec))
787 return;
788
789 check_presence_and_report(codec, jack->nid, jack->dev_id);
790}
791
792static void hdmi_intrinsic_event(struct hda_codec *codec, unsigned int res,
793 struct hda_jack_tbl *jack)
794{
795 jack->jack_dirty = 1;
796
797 codec_dbg(codec,
798 "HDMI hot plug event: Codec=%d Pin=%d Device=%d Inactive=%d Presence_Detect=%d ELD_Valid=%d\n",
799 codec->addr, jack->nid, jack->dev_id, !!(res & AC_UNSOL_RES_IA),
800 !!(res & AC_UNSOL_RES_PD), !!(res & AC_UNSOL_RES_ELDV));
801
802 check_presence_and_report(codec, jack->nid, jack->dev_id);
803}
804
805static void hdmi_non_intrinsic_event(struct hda_codec *codec, unsigned int res)
806{
807 int tag = res >> AC_UNSOL_RES_TAG_SHIFT;
808 int subtag = (res & AC_UNSOL_RES_SUBTAG) >> AC_UNSOL_RES_SUBTAG_SHIFT;
809 int cp_state = !!(res & AC_UNSOL_RES_CP_STATE);
810 int cp_ready = !!(res & AC_UNSOL_RES_CP_READY);
811
812 codec_info(codec,
813 "HDMI CP event: CODEC=%d TAG=%d SUBTAG=0x%x CP_STATE=%d CP_READY=%d\n",
814 codec->addr,
815 tag,
816 subtag,
817 cp_state,
818 cp_ready);
819
820 /* TODO */
821 if (cp_state) {
822 ;
823 }
824 if (cp_ready) {
825 ;
826 }
827}
828
829
830static void hdmi_unsol_event(struct hda_codec *codec, unsigned int res)
831{
832 int tag = res >> AC_UNSOL_RES_TAG_SHIFT;
833 int subtag = (res & AC_UNSOL_RES_SUBTAG) >> AC_UNSOL_RES_SUBTAG_SHIFT;
834 struct hda_jack_tbl *jack;
835
836 if (codec_has_acomp(codec))
837 return;
838
839 if (codec->dp_mst) {
840 int dev_entry =
841 (res & AC_UNSOL_RES_DE) >> AC_UNSOL_RES_DE_SHIFT;
842
843 jack = snd_hda_jack_tbl_get_from_tag(codec, tag, dev_entry);
844 } else {
845 jack = snd_hda_jack_tbl_get_from_tag(codec, tag, 0);
846 }
847
848 if (!jack) {
849 codec_dbg(codec, "Unexpected HDMI event tag 0x%x\n", tag);
850 return;
851 }
852
853 if (subtag == 0)
854 hdmi_intrinsic_event(codec, res, jack);
855 else
856 hdmi_non_intrinsic_event(codec, res);
857}
858
859static void haswell_verify_D0(struct hda_codec *codec,
860 hda_nid_t cvt_nid, hda_nid_t nid)
861{
862 int pwr;
863
864 /* For Haswell, the converter 1/2 may keep in D3 state after bootup,
865 * thus pins could only choose converter 0 for use. Make sure the
866 * converters are in correct power state */
867 if (!snd_hda_check_power_state(codec, cvt_nid, AC_PWRST_D0))
868 snd_hda_codec_write(codec, cvt_nid, 0, AC_VERB_SET_POWER_STATE, AC_PWRST_D0);
869
870 if (!snd_hda_check_power_state(codec, nid, AC_PWRST_D0)) {
871 snd_hda_codec_write(codec, nid, 0, AC_VERB_SET_POWER_STATE,
872 AC_PWRST_D0);
873 msleep(40);
874 pwr = snd_hda_codec_read(codec, nid, 0, AC_VERB_GET_POWER_STATE, 0);
875 pwr = (pwr & AC_PWRST_ACTUAL) >> AC_PWRST_ACTUAL_SHIFT;
876 codec_dbg(codec, "Haswell HDMI audio: Power for pin 0x%x is now D%d\n", nid, pwr);
877 }
878}
879
880/*
881 * Callbacks
882 */
883
884/* HBR should be Non-PCM, 8 channels */
885#define is_hbr_format(format) \
886 ((format & AC_FMT_TYPE_NON_PCM) && (format & AC_FMT_CHAN_MASK) == 7)
887
888static int hdmi_pin_hbr_setup(struct hda_codec *codec, hda_nid_t pin_nid,
889 int dev_id, bool hbr)
890{
891 int pinctl, new_pinctl;
892
893 if (snd_hda_query_pin_caps(codec, pin_nid) & AC_PINCAP_HBR) {
894 snd_hda_set_dev_select(codec, pin_nid, dev_id);
895 pinctl = snd_hda_codec_read(codec, pin_nid, 0,
896 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
897
898 if (pinctl < 0)
899 return hbr ? -EINVAL : 0;
900
901 new_pinctl = pinctl & ~AC_PINCTL_EPT;
902 if (hbr)
903 new_pinctl |= AC_PINCTL_EPT_HBR;
904 else
905 new_pinctl |= AC_PINCTL_EPT_NATIVE;
906
907 codec_dbg(codec,
908 "hdmi_pin_hbr_setup: NID=0x%x, %spinctl=0x%x\n",
909 pin_nid,
910 pinctl == new_pinctl ? "" : "new-",
911 new_pinctl);
912
913 if (pinctl != new_pinctl)
914 snd_hda_codec_write(codec, pin_nid, 0,
915 AC_VERB_SET_PIN_WIDGET_CONTROL,
916 new_pinctl);
917 } else if (hbr)
918 return -EINVAL;
919
920 return 0;
921}
922
923static int hdmi_setup_stream(struct hda_codec *codec, hda_nid_t cvt_nid,
924 hda_nid_t pin_nid, int dev_id,
925 u32 stream_tag, int format)
926{
927 struct hdmi_spec *spec = codec->spec;
928 unsigned int param;
929 int err;
930
931 err = spec->ops.pin_hbr_setup(codec, pin_nid, dev_id,
932 is_hbr_format(format));
933
934 if (err) {
935 codec_dbg(codec, "hdmi_setup_stream: HBR is not supported\n");
936 return err;
937 }
938
939 if (spec->intel_hsw_fixup) {
940
941 /*
942 * on recent platforms IEC Coding Type is required for HBR
943 * support, read current Digital Converter settings and set
944 * ICT bitfield if needed.
945 */
946 param = snd_hda_codec_read(codec, cvt_nid, 0,
947 AC_VERB_GET_DIGI_CONVERT_1, 0);
948
949 param = (param >> 16) & ~(AC_DIG3_ICT);
950
951 /* on recent platforms ICT mode is required for HBR support */
952 if (is_hbr_format(format))
953 param |= 0x1;
954
955 snd_hda_codec_write(codec, cvt_nid, 0,
956 AC_VERB_SET_DIGI_CONVERT_3, param);
957 }
958
959 snd_hda_codec_setup_stream(codec, cvt_nid, stream_tag, 0, format);
960 return 0;
961}
962
963/* Try to find an available converter
964 * If pin_idx is less then zero, just try to find an available converter.
965 * Otherwise, try to find an available converter and get the cvt mux index
966 * of the pin.
967 */
968static int hdmi_choose_cvt(struct hda_codec *codec,
969 int pin_idx, int *cvt_id)
970{
971 struct hdmi_spec *spec = codec->spec;
972 struct hdmi_spec_per_pin *per_pin;
973 struct hdmi_spec_per_cvt *per_cvt = NULL;
974 int cvt_idx, mux_idx = 0;
975
976 /* pin_idx < 0 means no pin will be bound to the converter */
977 if (pin_idx < 0)
978 per_pin = NULL;
979 else
980 per_pin = get_pin(spec, pin_idx);
981
982 /* Dynamically assign converter to stream */
983 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) {
984 per_cvt = get_cvt(spec, cvt_idx);
985
986 /* Must not already be assigned */
987 if (per_cvt->assigned)
988 continue;
989 if (per_pin == NULL)
990 break;
991 /* Must be in pin's mux's list of converters */
992 for (mux_idx = 0; mux_idx < per_pin->num_mux_nids; mux_idx++)
993 if (per_pin->mux_nids[mux_idx] == per_cvt->cvt_nid)
994 break;
995 /* Not in mux list */
996 if (mux_idx == per_pin->num_mux_nids)
997 continue;
998 break;
999 }
1000
1001 /* No free converters */
1002 if (cvt_idx == spec->num_cvts)
1003 return -EBUSY;
1004
1005 if (per_pin != NULL)
1006 per_pin->mux_idx = mux_idx;
1007
1008 if (cvt_id)
1009 *cvt_id = cvt_idx;
1010
1011 return 0;
1012}
1013
1014/* Assure the pin select the right convetor */
1015static void intel_verify_pin_cvt_connect(struct hda_codec *codec,
1016 struct hdmi_spec_per_pin *per_pin)
1017{
1018 hda_nid_t pin_nid = per_pin->pin_nid;
1019 int mux_idx, curr;
1020
1021 mux_idx = per_pin->mux_idx;
1022 curr = snd_hda_codec_read(codec, pin_nid, 0,
1023 AC_VERB_GET_CONNECT_SEL, 0);
1024 if (curr != mux_idx)
1025 snd_hda_codec_write_cache(codec, pin_nid, 0,
1026 AC_VERB_SET_CONNECT_SEL,
1027 mux_idx);
1028}
1029
1030/* get the mux index for the converter of the pins
1031 * converter's mux index is the same for all pins on Intel platform
1032 */
1033static int intel_cvt_id_to_mux_idx(struct hdmi_spec *spec,
1034 hda_nid_t cvt_nid)
1035{
1036 int i;
1037
1038 for (i = 0; i < spec->num_cvts; i++)
1039 if (spec->cvt_nids[i] == cvt_nid)
1040 return i;
1041 return -EINVAL;
1042}
1043
1044/* Intel HDMI workaround to fix audio routing issue:
1045 * For some Intel display codecs, pins share the same connection list.
1046 * So a conveter can be selected by multiple pins and playback on any of these
1047 * pins will generate sound on the external display, because audio flows from
1048 * the same converter to the display pipeline. Also muting one pin may make
1049 * other pins have no sound output.
1050 * So this function assures that an assigned converter for a pin is not selected
1051 * by any other pins.
1052 */
1053static void intel_not_share_assigned_cvt(struct hda_codec *codec,
1054 hda_nid_t pin_nid,
1055 int dev_id, int mux_idx)
1056{
1057 struct hdmi_spec *spec = codec->spec;
1058 hda_nid_t nid;
1059 int cvt_idx, curr;
1060 struct hdmi_spec_per_cvt *per_cvt;
1061 struct hdmi_spec_per_pin *per_pin;
1062 int pin_idx;
1063
1064 /* configure the pins connections */
1065 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
1066 int dev_id_saved;
1067 int dev_num;
1068
1069 per_pin = get_pin(spec, pin_idx);
1070 /*
1071 * pin not connected to monitor
1072 * no need to operate on it
1073 */
1074 if (!per_pin->pcm)
1075 continue;
1076
1077 if ((per_pin->pin_nid == pin_nid) &&
1078 (per_pin->dev_id == dev_id))
1079 continue;
1080
1081 /*
1082 * if per_pin->dev_id >= dev_num,
1083 * snd_hda_get_dev_select() will fail,
1084 * and the following operation is unpredictable.
1085 * So skip this situation.
1086 */
1087 dev_num = snd_hda_get_num_devices(codec, per_pin->pin_nid) + 1;
1088 if (per_pin->dev_id >= dev_num)
1089 continue;
1090
1091 nid = per_pin->pin_nid;
1092
1093 /*
1094 * Calling this function should not impact
1095 * on the device entry selection
1096 * So let's save the dev id for each pin,
1097 * and restore it when return
1098 */
1099 dev_id_saved = snd_hda_get_dev_select(codec, nid);
1100 snd_hda_set_dev_select(codec, nid, per_pin->dev_id);
1101 curr = snd_hda_codec_read(codec, nid, 0,
1102 AC_VERB_GET_CONNECT_SEL, 0);
1103 if (curr != mux_idx) {
1104 snd_hda_set_dev_select(codec, nid, dev_id_saved);
1105 continue;
1106 }
1107
1108
1109 /* choose an unassigned converter. The conveters in the
1110 * connection list are in the same order as in the codec.
1111 */
1112 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) {
1113 per_cvt = get_cvt(spec, cvt_idx);
1114 if (!per_cvt->assigned) {
1115 codec_dbg(codec,
1116 "choose cvt %d for pin nid %d\n",
1117 cvt_idx, nid);
1118 snd_hda_codec_write_cache(codec, nid, 0,
1119 AC_VERB_SET_CONNECT_SEL,
1120 cvt_idx);
1121 break;
1122 }
1123 }
1124 snd_hda_set_dev_select(codec, nid, dev_id_saved);
1125 }
1126}
1127
1128/* A wrapper of intel_not_share_asigned_cvt() */
1129static void intel_not_share_assigned_cvt_nid(struct hda_codec *codec,
1130 hda_nid_t pin_nid, int dev_id, hda_nid_t cvt_nid)
1131{
1132 int mux_idx;
1133 struct hdmi_spec *spec = codec->spec;
1134
1135 /* On Intel platform, the mapping of converter nid to
1136 * mux index of the pins are always the same.
1137 * The pin nid may be 0, this means all pins will not
1138 * share the converter.
1139 */
1140 mux_idx = intel_cvt_id_to_mux_idx(spec, cvt_nid);
1141 if (mux_idx >= 0)
1142 intel_not_share_assigned_cvt(codec, pin_nid, dev_id, mux_idx);
1143}
1144
1145/* skeleton caller of pin_cvt_fixup ops */
1146static void pin_cvt_fixup(struct hda_codec *codec,
1147 struct hdmi_spec_per_pin *per_pin,
1148 hda_nid_t cvt_nid)
1149{
1150 struct hdmi_spec *spec = codec->spec;
1151
1152 if (spec->ops.pin_cvt_fixup)
1153 spec->ops.pin_cvt_fixup(codec, per_pin, cvt_nid);
1154}
1155
1156/* called in hdmi_pcm_open when no pin is assigned to the PCM
1157 * in dyn_pcm_assign mode.
1158 */
1159static int hdmi_pcm_open_no_pin(struct hda_pcm_stream *hinfo,
1160 struct hda_codec *codec,
1161 struct snd_pcm_substream *substream)
1162{
1163 struct hdmi_spec *spec = codec->spec;
1164 struct snd_pcm_runtime *runtime = substream->runtime;
1165 int cvt_idx, pcm_idx;
1166 struct hdmi_spec_per_cvt *per_cvt = NULL;
1167 int err;
1168
1169 pcm_idx = hinfo_to_pcm_index(codec, hinfo);
1170 if (pcm_idx < 0)
1171 return -EINVAL;
1172
1173 err = hdmi_choose_cvt(codec, -1, &cvt_idx);
1174 if (err)
1175 return err;
1176
1177 per_cvt = get_cvt(spec, cvt_idx);
1178 per_cvt->assigned = 1;
1179 hinfo->nid = per_cvt->cvt_nid;
1180
1181 pin_cvt_fixup(codec, NULL, per_cvt->cvt_nid);
1182
1183 set_bit(pcm_idx, &spec->pcm_in_use);
1184 /* todo: setup spdif ctls assign */
1185
1186 /* Initially set the converter's capabilities */
1187 hinfo->channels_min = per_cvt->channels_min;
1188 hinfo->channels_max = per_cvt->channels_max;
1189 hinfo->rates = per_cvt->rates;
1190 hinfo->formats = per_cvt->formats;
1191 hinfo->maxbps = per_cvt->maxbps;
1192
1193 /* Store the updated parameters */
1194 runtime->hw.channels_min = hinfo->channels_min;
1195 runtime->hw.channels_max = hinfo->channels_max;
1196 runtime->hw.formats = hinfo->formats;
1197 runtime->hw.rates = hinfo->rates;
1198
1199 snd_pcm_hw_constraint_step(substream->runtime, 0,
1200 SNDRV_PCM_HW_PARAM_CHANNELS, 2);
1201 return 0;
1202}
1203
1204/*
1205 * HDA PCM callbacks
1206 */
1207static int hdmi_pcm_open(struct hda_pcm_stream *hinfo,
1208 struct hda_codec *codec,
1209 struct snd_pcm_substream *substream)
1210{
1211 struct hdmi_spec *spec = codec->spec;
1212 struct snd_pcm_runtime *runtime = substream->runtime;
1213 int pin_idx, cvt_idx, pcm_idx;
1214 struct hdmi_spec_per_pin *per_pin;
1215 struct hdmi_eld *eld;
1216 struct hdmi_spec_per_cvt *per_cvt = NULL;
1217 int err;
1218
1219 /* Validate hinfo */
1220 pcm_idx = hinfo_to_pcm_index(codec, hinfo);
1221 if (pcm_idx < 0)
1222 return -EINVAL;
1223
1224 mutex_lock(&spec->pcm_lock);
1225 pin_idx = hinfo_to_pin_index(codec, hinfo);
1226 if (!spec->dyn_pcm_assign) {
1227 if (snd_BUG_ON(pin_idx < 0)) {
1228 err = -EINVAL;
1229 goto unlock;
1230 }
1231 } else {
1232 /* no pin is assigned to the PCM
1233 * PA need pcm open successfully when probe
1234 */
1235 if (pin_idx < 0) {
1236 err = hdmi_pcm_open_no_pin(hinfo, codec, substream);
1237 goto unlock;
1238 }
1239 }
1240
1241 err = hdmi_choose_cvt(codec, pin_idx, &cvt_idx);
1242 if (err < 0)
1243 goto unlock;
1244
1245 per_cvt = get_cvt(spec, cvt_idx);
1246 /* Claim converter */
1247 per_cvt->assigned = 1;
1248
1249 set_bit(pcm_idx, &spec->pcm_in_use);
1250 per_pin = get_pin(spec, pin_idx);
1251 per_pin->cvt_nid = per_cvt->cvt_nid;
1252 hinfo->nid = per_cvt->cvt_nid;
1253
1254 /* flip stripe flag for the assigned stream if supported */
1255 if (get_wcaps(codec, per_cvt->cvt_nid) & AC_WCAP_STRIPE)
1256 azx_stream(get_azx_dev(substream))->stripe = 1;
1257
1258 snd_hda_set_dev_select(codec, per_pin->pin_nid, per_pin->dev_id);
1259 snd_hda_codec_write_cache(codec, per_pin->pin_nid, 0,
1260 AC_VERB_SET_CONNECT_SEL,
1261 per_pin->mux_idx);
1262
1263 /* configure unused pins to choose other converters */
1264 pin_cvt_fixup(codec, per_pin, 0);
1265
1266 snd_hda_spdif_ctls_assign(codec, pcm_idx, per_cvt->cvt_nid);
1267
1268 /* Initially set the converter's capabilities */
1269 hinfo->channels_min = per_cvt->channels_min;
1270 hinfo->channels_max = per_cvt->channels_max;
1271 hinfo->rates = per_cvt->rates;
1272 hinfo->formats = per_cvt->formats;
1273 hinfo->maxbps = per_cvt->maxbps;
1274
1275 eld = &per_pin->sink_eld;
1276 /* Restrict capabilities by ELD if this isn't disabled */
1277 if (!static_hdmi_pcm && eld->eld_valid) {
1278 snd_hdmi_eld_update_pcm_info(&eld->info, hinfo);
1279 if (hinfo->channels_min > hinfo->channels_max ||
1280 !hinfo->rates || !hinfo->formats) {
1281 per_cvt->assigned = 0;
1282 hinfo->nid = 0;
1283 snd_hda_spdif_ctls_unassign(codec, pcm_idx);
1284 err = -ENODEV;
1285 goto unlock;
1286 }
1287 }
1288
1289 /* Store the updated parameters */
1290 runtime->hw.channels_min = hinfo->channels_min;
1291 runtime->hw.channels_max = hinfo->channels_max;
1292 runtime->hw.formats = hinfo->formats;
1293 runtime->hw.rates = hinfo->rates;
1294
1295 snd_pcm_hw_constraint_step(substream->runtime, 0,
1296 SNDRV_PCM_HW_PARAM_CHANNELS, 2);
1297 unlock:
1298 mutex_unlock(&spec->pcm_lock);
1299 return err;
1300}
1301
1302/*
1303 * HDA/HDMI auto parsing
1304 */
1305static int hdmi_read_pin_conn(struct hda_codec *codec, int pin_idx)
1306{
1307 struct hdmi_spec *spec = codec->spec;
1308 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
1309 hda_nid_t pin_nid = per_pin->pin_nid;
1310 int dev_id = per_pin->dev_id;
1311 int conns;
1312
1313 if (!(get_wcaps(codec, pin_nid) & AC_WCAP_CONN_LIST)) {
1314 codec_warn(codec,
1315 "HDMI: pin %d wcaps %#x does not support connection list\n",
1316 pin_nid, get_wcaps(codec, pin_nid));
1317 return -EINVAL;
1318 }
1319
1320 snd_hda_set_dev_select(codec, pin_nid, dev_id);
1321
1322 if (spec->intel_hsw_fixup) {
1323 conns = spec->num_cvts;
1324 memcpy(per_pin->mux_nids, spec->cvt_nids,
1325 sizeof(hda_nid_t) * conns);
1326 } else {
1327 conns = snd_hda_get_raw_connections(codec, pin_nid,
1328 per_pin->mux_nids,
1329 HDA_MAX_CONNECTIONS);
1330 }
1331
1332 /* all the device entries on the same pin have the same conn list */
1333 per_pin->num_mux_nids = conns;
1334
1335 return 0;
1336}
1337
1338static int hdmi_find_pcm_slot(struct hdmi_spec *spec,
1339 struct hdmi_spec_per_pin *per_pin)
1340{
1341 int i;
1342
1343 /*
1344 * generic_hdmi_build_pcms() may allocate extra PCMs on some
1345 * platforms (with maximum of 'num_nids + dev_num - 1')
1346 *
1347 * The per_pin of pin_nid_idx=n and dev_id=m prefers to get pcm-n
1348 * if m==0. This guarantees that dynamic pcm assignments are compatible
1349 * with the legacy static per_pin-pcm assignment that existed in the
1350 * days before DP-MST.
1351 *
1352 * Intel DP-MST prefers this legacy behavior for compatibility, too.
1353 *
1354 * per_pin of m!=0 prefers to get pcm=(num_nids + (m - 1)).
1355 */
1356
1357 if (per_pin->dev_id == 0 || spec->intel_hsw_fixup) {
1358 if (!test_bit(per_pin->pin_nid_idx, &spec->pcm_bitmap))
1359 return per_pin->pin_nid_idx;
1360 } else {
1361 i = spec->num_nids + (per_pin->dev_id - 1);
1362 if (i < spec->pcm_used && !(test_bit(i, &spec->pcm_bitmap)))
1363 return i;
1364 }
1365
1366 /* have a second try; check the area over num_nids */
1367 for (i = spec->num_nids; i < spec->pcm_used; i++) {
1368 if (!test_bit(i, &spec->pcm_bitmap))
1369 return i;
1370 }
1371
1372 /* the last try; check the empty slots in pins */
1373 for (i = 0; i < spec->num_nids; i++) {
1374 if (!test_bit(i, &spec->pcm_bitmap))
1375 return i;
1376 }
1377 return -EBUSY;
1378}
1379
1380static void hdmi_attach_hda_pcm(struct hdmi_spec *spec,
1381 struct hdmi_spec_per_pin *per_pin)
1382{
1383 int idx;
1384
1385 /* pcm already be attached to the pin */
1386 if (per_pin->pcm)
1387 return;
1388 idx = hdmi_find_pcm_slot(spec, per_pin);
1389 if (idx == -EBUSY)
1390 return;
1391 per_pin->pcm_idx = idx;
1392 per_pin->pcm = get_hdmi_pcm(spec, idx);
1393 set_bit(idx, &spec->pcm_bitmap);
1394}
1395
1396static void hdmi_detach_hda_pcm(struct hdmi_spec *spec,
1397 struct hdmi_spec_per_pin *per_pin)
1398{
1399 int idx;
1400
1401 /* pcm already be detached from the pin */
1402 if (!per_pin->pcm)
1403 return;
1404 idx = per_pin->pcm_idx;
1405 per_pin->pcm_idx = -1;
1406 per_pin->pcm = NULL;
1407 if (idx >= 0 && idx < spec->pcm_used)
1408 clear_bit(idx, &spec->pcm_bitmap);
1409}
1410
1411static int hdmi_get_pin_cvt_mux(struct hdmi_spec *spec,
1412 struct hdmi_spec_per_pin *per_pin, hda_nid_t cvt_nid)
1413{
1414 int mux_idx;
1415
1416 for (mux_idx = 0; mux_idx < per_pin->num_mux_nids; mux_idx++)
1417 if (per_pin->mux_nids[mux_idx] == cvt_nid)
1418 break;
1419 return mux_idx;
1420}
1421
1422static bool check_non_pcm_per_cvt(struct hda_codec *codec, hda_nid_t cvt_nid);
1423
1424static void hdmi_pcm_setup_pin(struct hdmi_spec *spec,
1425 struct hdmi_spec_per_pin *per_pin)
1426{
1427 struct hda_codec *codec = per_pin->codec;
1428 struct hda_pcm *pcm;
1429 struct hda_pcm_stream *hinfo;
1430 struct snd_pcm_substream *substream;
1431 int mux_idx;
1432 bool non_pcm;
1433
1434 if (per_pin->pcm_idx >= 0 && per_pin->pcm_idx < spec->pcm_used)
1435 pcm = get_pcm_rec(spec, per_pin->pcm_idx);
1436 else
1437 return;
1438 if (!pcm->pcm)
1439 return;
1440 if (!test_bit(per_pin->pcm_idx, &spec->pcm_in_use))
1441 return;
1442
1443 /* hdmi audio only uses playback and one substream */
1444 hinfo = pcm->stream;
1445 substream = pcm->pcm->streams[0].substream;
1446
1447 per_pin->cvt_nid = hinfo->nid;
1448
1449 mux_idx = hdmi_get_pin_cvt_mux(spec, per_pin, hinfo->nid);
1450 if (mux_idx < per_pin->num_mux_nids) {
1451 snd_hda_set_dev_select(codec, per_pin->pin_nid,
1452 per_pin->dev_id);
1453 snd_hda_codec_write_cache(codec, per_pin->pin_nid, 0,
1454 AC_VERB_SET_CONNECT_SEL,
1455 mux_idx);
1456 }
1457 snd_hda_spdif_ctls_assign(codec, per_pin->pcm_idx, hinfo->nid);
1458
1459 non_pcm = check_non_pcm_per_cvt(codec, hinfo->nid);
1460 if (substream->runtime)
1461 per_pin->channels = substream->runtime->channels;
1462 per_pin->setup = true;
1463 per_pin->mux_idx = mux_idx;
1464
1465 hdmi_setup_audio_infoframe(codec, per_pin, non_pcm);
1466}
1467
1468static void hdmi_pcm_reset_pin(struct hdmi_spec *spec,
1469 struct hdmi_spec_per_pin *per_pin)
1470{
1471 if (per_pin->pcm_idx >= 0 && per_pin->pcm_idx < spec->pcm_used)
1472 snd_hda_spdif_ctls_unassign(per_pin->codec, per_pin->pcm_idx);
1473
1474 per_pin->chmap_set = false;
1475 memset(per_pin->chmap, 0, sizeof(per_pin->chmap));
1476
1477 per_pin->setup = false;
1478 per_pin->channels = 0;
1479}
1480
1481static struct snd_jack *pin_idx_to_pcm_jack(struct hda_codec *codec,
1482 struct hdmi_spec_per_pin *per_pin)
1483{
1484 struct hdmi_spec *spec = codec->spec;
1485
1486 if (per_pin->pcm_idx >= 0)
1487 return spec->pcm_rec[per_pin->pcm_idx].jack;
1488 else
1489 return NULL;
1490}
1491
1492/* update per_pin ELD from the given new ELD;
1493 * setup info frame and notification accordingly
1494 * also notify ELD kctl and report jack status changes
1495 */
1496static void update_eld(struct hda_codec *codec,
1497 struct hdmi_spec_per_pin *per_pin,
1498 struct hdmi_eld *eld,
1499 int repoll)
1500{
1501 struct hdmi_eld *pin_eld = &per_pin->sink_eld;
1502 struct hdmi_spec *spec = codec->spec;
1503 struct snd_jack *pcm_jack;
1504 bool old_eld_valid = pin_eld->eld_valid;
1505 bool eld_changed;
1506 int pcm_idx;
1507
1508 if (eld->eld_valid) {
1509 if (eld->eld_size <= 0 ||
1510 snd_hdmi_parse_eld(codec, &eld->info, eld->eld_buffer,
1511 eld->eld_size) < 0) {
1512 eld->eld_valid = false;
1513 if (repoll) {
1514 schedule_delayed_work(&per_pin->work,
1515 msecs_to_jiffies(300));
1516 return;
1517 }
1518 }
1519 }
1520
1521 if (!eld->eld_valid || eld->eld_size <= 0) {
1522 eld->eld_valid = false;
1523 eld->eld_size = 0;
1524 }
1525
1526 /* for monitor disconnection, save pcm_idx firstly */
1527 pcm_idx = per_pin->pcm_idx;
1528
1529 /*
1530 * pcm_idx >=0 before update_eld() means it is in monitor
1531 * disconnected event. Jack must be fetched before update_eld().
1532 */
1533 pcm_jack = pin_idx_to_pcm_jack(codec, per_pin);
1534
1535 if (spec->dyn_pcm_assign) {
1536 if (eld->eld_valid) {
1537 hdmi_attach_hda_pcm(spec, per_pin);
1538 hdmi_pcm_setup_pin(spec, per_pin);
1539 } else {
1540 hdmi_pcm_reset_pin(spec, per_pin);
1541 hdmi_detach_hda_pcm(spec, per_pin);
1542 }
1543 }
1544 /* if pcm_idx == -1, it means this is in monitor connection event
1545 * we can get the correct pcm_idx now.
1546 */
1547 if (pcm_idx == -1)
1548 pcm_idx = per_pin->pcm_idx;
1549 if (!pcm_jack)
1550 pcm_jack = pin_idx_to_pcm_jack(codec, per_pin);
1551
1552 if (eld->eld_valid)
1553 snd_hdmi_show_eld(codec, &eld->info);
1554
1555 eld_changed = (pin_eld->eld_valid != eld->eld_valid);
1556 eld_changed |= (pin_eld->monitor_present != eld->monitor_present);
1557 if (!eld_changed && eld->eld_valid && pin_eld->eld_valid)
1558 if (pin_eld->eld_size != eld->eld_size ||
1559 memcmp(pin_eld->eld_buffer, eld->eld_buffer,
1560 eld->eld_size) != 0)
1561 eld_changed = true;
1562
1563 if (eld_changed) {
1564 pin_eld->monitor_present = eld->monitor_present;
1565 pin_eld->eld_valid = eld->eld_valid;
1566 pin_eld->eld_size = eld->eld_size;
1567 if (eld->eld_valid)
1568 memcpy(pin_eld->eld_buffer, eld->eld_buffer,
1569 eld->eld_size);
1570 pin_eld->info = eld->info;
1571 }
1572
1573 /*
1574 * Re-setup pin and infoframe. This is needed e.g. when
1575 * - sink is first plugged-in
1576 * - transcoder can change during stream playback on Haswell
1577 * and this can make HW reset converter selection on a pin.
1578 */
1579 if (eld->eld_valid && !old_eld_valid && per_pin->setup) {
1580 pin_cvt_fixup(codec, per_pin, 0);
1581 hdmi_setup_audio_infoframe(codec, per_pin, per_pin->non_pcm);
1582 }
1583
1584 if (eld_changed && pcm_idx >= 0)
1585 snd_ctl_notify(codec->card,
1586 SNDRV_CTL_EVENT_MASK_VALUE |
1587 SNDRV_CTL_EVENT_MASK_INFO,
1588 &get_hdmi_pcm(spec, pcm_idx)->eld_ctl->id);
1589
1590 if (eld_changed && pcm_jack)
1591 snd_jack_report(pcm_jack,
1592 (eld->monitor_present && eld->eld_valid) ?
1593 SND_JACK_AVOUT : 0);
1594}
1595
1596/* update ELD and jack state via HD-audio verbs */
1597static void hdmi_present_sense_via_verbs(struct hdmi_spec_per_pin *per_pin,
1598 int repoll)
1599{
1600 struct hda_codec *codec = per_pin->codec;
1601 struct hdmi_spec *spec = codec->spec;
1602 struct hdmi_eld *eld = &spec->temp_eld;
1603 hda_nid_t pin_nid = per_pin->pin_nid;
1604 int dev_id = per_pin->dev_id;
1605 /*
1606 * Always execute a GetPinSense verb here, even when called from
1607 * hdmi_intrinsic_event; for some NVIDIA HW, the unsolicited
1608 * response's PD bit is not the real PD value, but indicates that
1609 * the real PD value changed. An older version of the HD-audio
1610 * specification worked this way. Hence, we just ignore the data in
1611 * the unsolicited response to avoid custom WARs.
1612 */
1613 int present;
1614 int ret;
1615
1616 ret = snd_hda_power_up_pm(codec);
1617 if (ret < 0 && pm_runtime_suspended(hda_codec_dev(codec)))
1618 goto out;
1619
1620 present = snd_hda_jack_pin_sense(codec, pin_nid, dev_id);
1621
1622 mutex_lock(&per_pin->lock);
1623 eld->monitor_present = !!(present & AC_PINSENSE_PRESENCE);
1624 if (eld->monitor_present)
1625 eld->eld_valid = !!(present & AC_PINSENSE_ELDV);
1626 else
1627 eld->eld_valid = false;
1628
1629 codec_dbg(codec,
1630 "HDMI status: Codec=%d Pin=%d Presence_Detect=%d ELD_Valid=%d\n",
1631 codec->addr, pin_nid, eld->monitor_present, eld->eld_valid);
1632
1633 if (eld->eld_valid) {
1634 if (spec->ops.pin_get_eld(codec, pin_nid, dev_id,
1635 eld->eld_buffer, &eld->eld_size) < 0)
1636 eld->eld_valid = false;
1637 }
1638
1639 update_eld(codec, per_pin, eld, repoll);
1640 mutex_unlock(&per_pin->lock);
1641 out:
1642 snd_hda_power_down_pm(codec);
1643}
1644
1645static void silent_stream_enable(struct hda_codec *codec,
1646 struct hdmi_spec_per_pin *per_pin)
1647{
1648 unsigned int newval, oldval;
1649
1650 codec_dbg(codec, "hdmi: enabling silent stream for NID %d\n",
1651 per_pin->pin_nid);
1652
1653 mutex_lock(&per_pin->lock);
1654
1655 if (!per_pin->channels)
1656 per_pin->channels = 2;
1657
1658 oldval = snd_hda_codec_read(codec, per_pin->pin_nid, 0,
1659 AC_VERB_GET_CONV, 0);
1660 newval = (oldval & 0xF0) | 0xF;
1661 snd_hda_codec_write(codec, per_pin->pin_nid, 0,
1662 AC_VERB_SET_CHANNEL_STREAMID, newval);
1663
1664 hdmi_setup_audio_infoframe(codec, per_pin, per_pin->non_pcm);
1665
1666 mutex_unlock(&per_pin->lock);
1667}
1668
1669/* update ELD and jack state via audio component */
1670static void sync_eld_via_acomp(struct hda_codec *codec,
1671 struct hdmi_spec_per_pin *per_pin)
1672{
1673 struct hdmi_spec *spec = codec->spec;
1674 struct hdmi_eld *eld = &spec->temp_eld;
1675 bool monitor_prev, monitor_next;
1676
1677 mutex_lock(&per_pin->lock);
1678 eld->monitor_present = false;
1679 monitor_prev = per_pin->sink_eld.monitor_present;
1680 eld->eld_size = snd_hdac_acomp_get_eld(&codec->core, per_pin->pin_nid,
1681 per_pin->dev_id, &eld->monitor_present,
1682 eld->eld_buffer, ELD_MAX_SIZE);
1683 eld->eld_valid = (eld->eld_size > 0);
1684 update_eld(codec, per_pin, eld, 0);
1685 monitor_next = per_pin->sink_eld.monitor_present;
1686 mutex_unlock(&per_pin->lock);
1687
1688 /*
1689 * Power-up will call hdmi_present_sense, so the PM calls
1690 * have to be done without mutex held.
1691 */
1692
1693 if (spec->send_silent_stream) {
1694 int pm_ret;
1695
1696 if (!monitor_prev && monitor_next) {
1697 pm_ret = snd_hda_power_up_pm(codec);
1698 if (pm_ret < 0)
1699 codec_err(codec,
1700 "Monitor plugged-in, Failed to power up codec ret=[%d]\n",
1701 pm_ret);
1702 silent_stream_enable(codec, per_pin);
1703 } else if (monitor_prev && !monitor_next) {
1704 pm_ret = snd_hda_power_down_pm(codec);
1705 if (pm_ret < 0)
1706 codec_err(codec,
1707 "Monitor plugged-out, Failed to power down codec ret=[%d]\n",
1708 pm_ret);
1709 }
1710 }
1711}
1712
1713static void hdmi_present_sense(struct hdmi_spec_per_pin *per_pin, int repoll)
1714{
1715 struct hda_codec *codec = per_pin->codec;
1716
1717 if (!codec_has_acomp(codec))
1718 hdmi_present_sense_via_verbs(per_pin, repoll);
1719 else
1720 sync_eld_via_acomp(codec, per_pin);
1721}
1722
1723static void hdmi_repoll_eld(struct work_struct *work)
1724{
1725 struct hdmi_spec_per_pin *per_pin =
1726 container_of(to_delayed_work(work), struct hdmi_spec_per_pin, work);
1727 struct hda_codec *codec = per_pin->codec;
1728 struct hdmi_spec *spec = codec->spec;
1729 struct hda_jack_tbl *jack;
1730
1731 jack = snd_hda_jack_tbl_get_mst(codec, per_pin->pin_nid,
1732 per_pin->dev_id);
1733 if (jack)
1734 jack->jack_dirty = 1;
1735
1736 if (per_pin->repoll_count++ > 6)
1737 per_pin->repoll_count = 0;
1738
1739 mutex_lock(&spec->pcm_lock);
1740 hdmi_present_sense(per_pin, per_pin->repoll_count);
1741 mutex_unlock(&spec->pcm_lock);
1742}
1743
1744static int hdmi_add_pin(struct hda_codec *codec, hda_nid_t pin_nid)
1745{
1746 struct hdmi_spec *spec = codec->spec;
1747 unsigned int caps, config;
1748 int pin_idx;
1749 struct hdmi_spec_per_pin *per_pin;
1750 int err;
1751 int dev_num, i;
1752
1753 caps = snd_hda_query_pin_caps(codec, pin_nid);
1754 if (!(caps & (AC_PINCAP_HDMI | AC_PINCAP_DP)))
1755 return 0;
1756
1757 /*
1758 * For DP MST audio, Configuration Default is the same for
1759 * all device entries on the same pin
1760 */
1761 config = snd_hda_codec_get_pincfg(codec, pin_nid);
1762 if (get_defcfg_connect(config) == AC_JACK_PORT_NONE &&
1763 !spec->force_connect)
1764 return 0;
1765
1766 /*
1767 * To simplify the implementation, malloc all
1768 * the virtual pins in the initialization statically
1769 */
1770 if (spec->intel_hsw_fixup) {
1771 /*
1772 * On Intel platforms, device entries number is
1773 * changed dynamically. If there is a DP MST
1774 * hub connected, the device entries number is 3.
1775 * Otherwise, it is 1.
1776 * Here we manually set dev_num to 3, so that
1777 * we can initialize all the device entries when
1778 * bootup statically.
1779 */
1780 dev_num = 3;
1781 spec->dev_num = 3;
1782 } else if (spec->dyn_pcm_assign && codec->dp_mst) {
1783 dev_num = snd_hda_get_num_devices(codec, pin_nid) + 1;
1784 /*
1785 * spec->dev_num is the maxinum number of device entries
1786 * among all the pins
1787 */
1788 spec->dev_num = (spec->dev_num > dev_num) ?
1789 spec->dev_num : dev_num;
1790 } else {
1791 /*
1792 * If the platform doesn't support DP MST,
1793 * manually set dev_num to 1. This means
1794 * the pin has only one device entry.
1795 */
1796 dev_num = 1;
1797 spec->dev_num = 1;
1798 }
1799
1800 for (i = 0; i < dev_num; i++) {
1801 pin_idx = spec->num_pins;
1802 per_pin = snd_array_new(&spec->pins);
1803
1804 if (!per_pin)
1805 return -ENOMEM;
1806
1807 if (spec->dyn_pcm_assign) {
1808 per_pin->pcm = NULL;
1809 per_pin->pcm_idx = -1;
1810 } else {
1811 per_pin->pcm = get_hdmi_pcm(spec, pin_idx);
1812 per_pin->pcm_idx = pin_idx;
1813 }
1814 per_pin->pin_nid = pin_nid;
1815 per_pin->pin_nid_idx = spec->num_nids;
1816 per_pin->dev_id = i;
1817 per_pin->non_pcm = false;
1818 snd_hda_set_dev_select(codec, pin_nid, i);
1819 err = hdmi_read_pin_conn(codec, pin_idx);
1820 if (err < 0)
1821 return err;
1822 spec->num_pins++;
1823 }
1824 spec->num_nids++;
1825
1826 return 0;
1827}
1828
1829static int hdmi_add_cvt(struct hda_codec *codec, hda_nid_t cvt_nid)
1830{
1831 struct hdmi_spec *spec = codec->spec;
1832 struct hdmi_spec_per_cvt *per_cvt;
1833 unsigned int chans;
1834 int err;
1835
1836 chans = get_wcaps(codec, cvt_nid);
1837 chans = get_wcaps_channels(chans);
1838
1839 per_cvt = snd_array_new(&spec->cvts);
1840 if (!per_cvt)
1841 return -ENOMEM;
1842
1843 per_cvt->cvt_nid = cvt_nid;
1844 per_cvt->channels_min = 2;
1845 if (chans <= 16) {
1846 per_cvt->channels_max = chans;
1847 if (chans > spec->chmap.channels_max)
1848 spec->chmap.channels_max = chans;
1849 }
1850
1851 err = snd_hda_query_supported_pcm(codec, cvt_nid,
1852 &per_cvt->rates,
1853 &per_cvt->formats,
1854 &per_cvt->maxbps);
1855 if (err < 0)
1856 return err;
1857
1858 if (spec->num_cvts < ARRAY_SIZE(spec->cvt_nids))
1859 spec->cvt_nids[spec->num_cvts] = cvt_nid;
1860 spec->num_cvts++;
1861
1862 return 0;
1863}
1864
1865static const struct snd_pci_quirk force_connect_list[] = {
1866 SND_PCI_QUIRK(0x103c, 0x870f, "HP", 1),
1867 SND_PCI_QUIRK(0x103c, 0x871a, "HP", 1),
1868 {}
1869};
1870
1871static int hdmi_parse_codec(struct hda_codec *codec)
1872{
1873 struct hdmi_spec *spec = codec->spec;
1874 hda_nid_t start_nid;
1875 unsigned int caps;
1876 int i, nodes;
1877 const struct snd_pci_quirk *q;
1878
1879 nodes = snd_hda_get_sub_nodes(codec, codec->core.afg, &start_nid);
1880 if (!start_nid || nodes < 0) {
1881 codec_warn(codec, "HDMI: failed to get afg sub nodes\n");
1882 return -EINVAL;
1883 }
1884
1885 q = snd_pci_quirk_lookup(codec->bus->pci, force_connect_list);
1886
1887 if (q && q->value)
1888 spec->force_connect = true;
1889
1890 /*
1891 * hdmi_add_pin() assumes total amount of converters to
1892 * be known, so first discover all converters
1893 */
1894 for (i = 0; i < nodes; i++) {
1895 hda_nid_t nid = start_nid + i;
1896
1897 caps = get_wcaps(codec, nid);
1898
1899 if (!(caps & AC_WCAP_DIGITAL))
1900 continue;
1901
1902 if (get_wcaps_type(caps) == AC_WID_AUD_OUT)
1903 hdmi_add_cvt(codec, nid);
1904 }
1905
1906 /* discover audio pins */
1907 for (i = 0; i < nodes; i++) {
1908 hda_nid_t nid = start_nid + i;
1909
1910 caps = get_wcaps(codec, nid);
1911
1912 if (!(caps & AC_WCAP_DIGITAL))
1913 continue;
1914
1915 if (get_wcaps_type(caps) == AC_WID_PIN)
1916 hdmi_add_pin(codec, nid);
1917 }
1918
1919 return 0;
1920}
1921
1922/*
1923 */
1924static bool check_non_pcm_per_cvt(struct hda_codec *codec, hda_nid_t cvt_nid)
1925{
1926 struct hda_spdif_out *spdif;
1927 bool non_pcm;
1928
1929 mutex_lock(&codec->spdif_mutex);
1930 spdif = snd_hda_spdif_out_of_nid(codec, cvt_nid);
1931 /* Add sanity check to pass klockwork check.
1932 * This should never happen.
1933 */
1934 if (WARN_ON(spdif == NULL)) {
1935 mutex_unlock(&codec->spdif_mutex);
1936 return true;
1937 }
1938 non_pcm = !!(spdif->status & IEC958_AES0_NONAUDIO);
1939 mutex_unlock(&codec->spdif_mutex);
1940 return non_pcm;
1941}
1942
1943/*
1944 * HDMI callbacks
1945 */
1946
1947static int generic_hdmi_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
1948 struct hda_codec *codec,
1949 unsigned int stream_tag,
1950 unsigned int format,
1951 struct snd_pcm_substream *substream)
1952{
1953 hda_nid_t cvt_nid = hinfo->nid;
1954 struct hdmi_spec *spec = codec->spec;
1955 int pin_idx;
1956 struct hdmi_spec_per_pin *per_pin;
1957 struct snd_pcm_runtime *runtime = substream->runtime;
1958 bool non_pcm;
1959 int pinctl, stripe;
1960 int err = 0;
1961
1962 mutex_lock(&spec->pcm_lock);
1963 pin_idx = hinfo_to_pin_index(codec, hinfo);
1964 if (spec->dyn_pcm_assign && pin_idx < 0) {
1965 /* when dyn_pcm_assign and pcm is not bound to a pin
1966 * skip pin setup and return 0 to make audio playback
1967 * be ongoing
1968 */
1969 pin_cvt_fixup(codec, NULL, cvt_nid);
1970 snd_hda_codec_setup_stream(codec, cvt_nid,
1971 stream_tag, 0, format);
1972 goto unlock;
1973 }
1974
1975 if (snd_BUG_ON(pin_idx < 0)) {
1976 err = -EINVAL;
1977 goto unlock;
1978 }
1979 per_pin = get_pin(spec, pin_idx);
1980
1981 /* Verify pin:cvt selections to avoid silent audio after S3.
1982 * After S3, the audio driver restores pin:cvt selections
1983 * but this can happen before gfx is ready and such selection
1984 * is overlooked by HW. Thus multiple pins can share a same
1985 * default convertor and mute control will affect each other,
1986 * which can cause a resumed audio playback become silent
1987 * after S3.
1988 */
1989 pin_cvt_fixup(codec, per_pin, 0);
1990
1991 /* Call sync_audio_rate to set the N/CTS/M manually if necessary */
1992 /* Todo: add DP1.2 MST audio support later */
1993 if (codec_has_acomp(codec))
1994 snd_hdac_sync_audio_rate(&codec->core, per_pin->pin_nid,
1995 per_pin->dev_id, runtime->rate);
1996
1997 non_pcm = check_non_pcm_per_cvt(codec, cvt_nid);
1998 mutex_lock(&per_pin->lock);
1999 per_pin->channels = substream->runtime->channels;
2000 per_pin->setup = true;
2001
2002 if (get_wcaps(codec, cvt_nid) & AC_WCAP_STRIPE) {
2003 stripe = snd_hdac_get_stream_stripe_ctl(&codec->bus->core,
2004 substream);
2005 snd_hda_codec_write(codec, cvt_nid, 0,
2006 AC_VERB_SET_STRIPE_CONTROL,
2007 stripe);
2008 }
2009
2010 hdmi_setup_audio_infoframe(codec, per_pin, non_pcm);
2011 mutex_unlock(&per_pin->lock);
2012 if (spec->dyn_pin_out) {
2013 snd_hda_set_dev_select(codec, per_pin->pin_nid,
2014 per_pin->dev_id);
2015 pinctl = snd_hda_codec_read(codec, per_pin->pin_nid, 0,
2016 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
2017 snd_hda_codec_write(codec, per_pin->pin_nid, 0,
2018 AC_VERB_SET_PIN_WIDGET_CONTROL,
2019 pinctl | PIN_OUT);
2020 }
2021
2022 /* snd_hda_set_dev_select() has been called before */
2023 err = spec->ops.setup_stream(codec, cvt_nid, per_pin->pin_nid,
2024 per_pin->dev_id, stream_tag, format);
2025 unlock:
2026 mutex_unlock(&spec->pcm_lock);
2027 return err;
2028}
2029
2030static int generic_hdmi_playback_pcm_cleanup(struct hda_pcm_stream *hinfo,
2031 struct hda_codec *codec,
2032 struct snd_pcm_substream *substream)
2033{
2034 snd_hda_codec_cleanup_stream(codec, hinfo->nid);
2035 return 0;
2036}
2037
2038static int hdmi_pcm_close(struct hda_pcm_stream *hinfo,
2039 struct hda_codec *codec,
2040 struct snd_pcm_substream *substream)
2041{
2042 struct hdmi_spec *spec = codec->spec;
2043 int cvt_idx, pin_idx, pcm_idx;
2044 struct hdmi_spec_per_cvt *per_cvt;
2045 struct hdmi_spec_per_pin *per_pin;
2046 int pinctl;
2047 int err = 0;
2048
2049 if (hinfo->nid) {
2050 pcm_idx = hinfo_to_pcm_index(codec, hinfo);
2051 if (snd_BUG_ON(pcm_idx < 0))
2052 return -EINVAL;
2053 cvt_idx = cvt_nid_to_cvt_index(codec, hinfo->nid);
2054 if (snd_BUG_ON(cvt_idx < 0))
2055 return -EINVAL;
2056 per_cvt = get_cvt(spec, cvt_idx);
2057
2058 snd_BUG_ON(!per_cvt->assigned);
2059 per_cvt->assigned = 0;
2060 hinfo->nid = 0;
2061
2062 azx_stream(get_azx_dev(substream))->stripe = 0;
2063
2064 mutex_lock(&spec->pcm_lock);
2065 snd_hda_spdif_ctls_unassign(codec, pcm_idx);
2066 clear_bit(pcm_idx, &spec->pcm_in_use);
2067 pin_idx = hinfo_to_pin_index(codec, hinfo);
2068 if (spec->dyn_pcm_assign && pin_idx < 0)
2069 goto unlock;
2070
2071 if (snd_BUG_ON(pin_idx < 0)) {
2072 err = -EINVAL;
2073 goto unlock;
2074 }
2075 per_pin = get_pin(spec, pin_idx);
2076
2077 if (spec->dyn_pin_out) {
2078 snd_hda_set_dev_select(codec, per_pin->pin_nid,
2079 per_pin->dev_id);
2080 pinctl = snd_hda_codec_read(codec, per_pin->pin_nid, 0,
2081 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
2082 snd_hda_codec_write(codec, per_pin->pin_nid, 0,
2083 AC_VERB_SET_PIN_WIDGET_CONTROL,
2084 pinctl & ~PIN_OUT);
2085 }
2086
2087 mutex_lock(&per_pin->lock);
2088 per_pin->chmap_set = false;
2089 memset(per_pin->chmap, 0, sizeof(per_pin->chmap));
2090
2091 per_pin->setup = false;
2092 per_pin->channels = 0;
2093 mutex_unlock(&per_pin->lock);
2094 unlock:
2095 mutex_unlock(&spec->pcm_lock);
2096 }
2097
2098 return err;
2099}
2100
2101static const struct hda_pcm_ops generic_ops = {
2102 .open = hdmi_pcm_open,
2103 .close = hdmi_pcm_close,
2104 .prepare = generic_hdmi_playback_pcm_prepare,
2105 .cleanup = generic_hdmi_playback_pcm_cleanup,
2106};
2107
2108static int hdmi_get_spk_alloc(struct hdac_device *hdac, int pcm_idx)
2109{
2110 struct hda_codec *codec = hdac_to_hda_codec(hdac);
2111 struct hdmi_spec *spec = codec->spec;
2112 struct hdmi_spec_per_pin *per_pin = pcm_idx_to_pin(spec, pcm_idx);
2113
2114 if (!per_pin)
2115 return 0;
2116
2117 return per_pin->sink_eld.info.spk_alloc;
2118}
2119
2120static void hdmi_get_chmap(struct hdac_device *hdac, int pcm_idx,
2121 unsigned char *chmap)
2122{
2123 struct hda_codec *codec = hdac_to_hda_codec(hdac);
2124 struct hdmi_spec *spec = codec->spec;
2125 struct hdmi_spec_per_pin *per_pin = pcm_idx_to_pin(spec, pcm_idx);
2126
2127 /* chmap is already set to 0 in caller */
2128 if (!per_pin)
2129 return;
2130
2131 memcpy(chmap, per_pin->chmap, ARRAY_SIZE(per_pin->chmap));
2132}
2133
2134static void hdmi_set_chmap(struct hdac_device *hdac, int pcm_idx,
2135 unsigned char *chmap, int prepared)
2136{
2137 struct hda_codec *codec = hdac_to_hda_codec(hdac);
2138 struct hdmi_spec *spec = codec->spec;
2139 struct hdmi_spec_per_pin *per_pin = pcm_idx_to_pin(spec, pcm_idx);
2140
2141 if (!per_pin)
2142 return;
2143 mutex_lock(&per_pin->lock);
2144 per_pin->chmap_set = true;
2145 memcpy(per_pin->chmap, chmap, ARRAY_SIZE(per_pin->chmap));
2146 if (prepared)
2147 hdmi_setup_audio_infoframe(codec, per_pin, per_pin->non_pcm);
2148 mutex_unlock(&per_pin->lock);
2149}
2150
2151static bool is_hdmi_pcm_attached(struct hdac_device *hdac, int pcm_idx)
2152{
2153 struct hda_codec *codec = hdac_to_hda_codec(hdac);
2154 struct hdmi_spec *spec = codec->spec;
2155 struct hdmi_spec_per_pin *per_pin = pcm_idx_to_pin(spec, pcm_idx);
2156
2157 return per_pin ? true:false;
2158}
2159
2160static int generic_hdmi_build_pcms(struct hda_codec *codec)
2161{
2162 struct hdmi_spec *spec = codec->spec;
2163 int idx, pcm_num;
2164
2165 /*
2166 * for non-mst mode, pcm number is the same as before
2167 * for DP MST mode without extra PCM, pcm number is same
2168 * for DP MST mode with extra PCMs, pcm number is
2169 * (nid number + dev_num - 1)
2170 * dev_num is the device entry number in a pin
2171 */
2172
2173 if (codec->mst_no_extra_pcms)
2174 pcm_num = spec->num_nids;
2175 else
2176 pcm_num = spec->num_nids + spec->dev_num - 1;
2177
2178 codec_dbg(codec, "hdmi: pcm_num set to %d\n", pcm_num);
2179
2180 for (idx = 0; idx < pcm_num; idx++) {
2181 struct hda_pcm *info;
2182 struct hda_pcm_stream *pstr;
2183
2184 info = snd_hda_codec_pcm_new(codec, "HDMI %d", idx);
2185 if (!info)
2186 return -ENOMEM;
2187
2188 spec->pcm_rec[idx].pcm = info;
2189 spec->pcm_used++;
2190 info->pcm_type = HDA_PCM_TYPE_HDMI;
2191 info->own_chmap = true;
2192
2193 pstr = &info->stream[SNDRV_PCM_STREAM_PLAYBACK];
2194 pstr->substreams = 1;
2195 pstr->ops = generic_ops;
2196 /* pcm number is less than 16 */
2197 if (spec->pcm_used >= 16)
2198 break;
2199 /* other pstr fields are set in open */
2200 }
2201
2202 return 0;
2203}
2204
2205static void free_hdmi_jack_priv(struct snd_jack *jack)
2206{
2207 struct hdmi_pcm *pcm = jack->private_data;
2208
2209 pcm->jack = NULL;
2210}
2211
2212static int generic_hdmi_build_jack(struct hda_codec *codec, int pcm_idx)
2213{
2214 char hdmi_str[32] = "HDMI/DP";
2215 struct hdmi_spec *spec = codec->spec;
2216 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pcm_idx);
2217 struct snd_jack *jack;
2218 int pcmdev = get_pcm_rec(spec, pcm_idx)->device;
2219 int err;
2220
2221 if (pcmdev > 0)
2222 sprintf(hdmi_str + strlen(hdmi_str), ",pcm=%d", pcmdev);
2223 if (!spec->dyn_pcm_assign &&
2224 !is_jack_detectable(codec, per_pin->pin_nid))
2225 strncat(hdmi_str, " Phantom",
2226 sizeof(hdmi_str) - strlen(hdmi_str) - 1);
2227
2228 err = snd_jack_new(codec->card, hdmi_str, SND_JACK_AVOUT, &jack,
2229 true, false);
2230 if (err < 0)
2231 return err;
2232
2233 spec->pcm_rec[pcm_idx].jack = jack;
2234 jack->private_data = &spec->pcm_rec[pcm_idx];
2235 jack->private_free = free_hdmi_jack_priv;
2236 return 0;
2237}
2238
2239static int generic_hdmi_build_controls(struct hda_codec *codec)
2240{
2241 struct hdmi_spec *spec = codec->spec;
2242 int dev, err;
2243 int pin_idx, pcm_idx;
2244
2245 for (pcm_idx = 0; pcm_idx < spec->pcm_used; pcm_idx++) {
2246 if (!get_pcm_rec(spec, pcm_idx)->pcm) {
2247 /* no PCM: mark this for skipping permanently */
2248 set_bit(pcm_idx, &spec->pcm_bitmap);
2249 continue;
2250 }
2251
2252 err = generic_hdmi_build_jack(codec, pcm_idx);
2253 if (err < 0)
2254 return err;
2255
2256 /* create the spdif for each pcm
2257 * pin will be bound when monitor is connected
2258 */
2259 if (spec->dyn_pcm_assign)
2260 err = snd_hda_create_dig_out_ctls(codec,
2261 0, spec->cvt_nids[0],
2262 HDA_PCM_TYPE_HDMI);
2263 else {
2264 struct hdmi_spec_per_pin *per_pin =
2265 get_pin(spec, pcm_idx);
2266 err = snd_hda_create_dig_out_ctls(codec,
2267 per_pin->pin_nid,
2268 per_pin->mux_nids[0],
2269 HDA_PCM_TYPE_HDMI);
2270 }
2271 if (err < 0)
2272 return err;
2273 snd_hda_spdif_ctls_unassign(codec, pcm_idx);
2274
2275 dev = get_pcm_rec(spec, pcm_idx)->device;
2276 if (dev != SNDRV_PCM_INVALID_DEVICE) {
2277 /* add control for ELD Bytes */
2278 err = hdmi_create_eld_ctl(codec, pcm_idx, dev);
2279 if (err < 0)
2280 return err;
2281 }
2282 }
2283
2284 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2285 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2286 struct hdmi_eld *pin_eld = &per_pin->sink_eld;
2287
2288 pin_eld->eld_valid = false;
2289 hdmi_present_sense(per_pin, 0);
2290 }
2291
2292 /* add channel maps */
2293 for (pcm_idx = 0; pcm_idx < spec->pcm_used; pcm_idx++) {
2294 struct hda_pcm *pcm;
2295
2296 pcm = get_pcm_rec(spec, pcm_idx);
2297 if (!pcm || !pcm->pcm)
2298 break;
2299 err = snd_hdac_add_chmap_ctls(pcm->pcm, pcm_idx, &spec->chmap);
2300 if (err < 0)
2301 return err;
2302 }
2303
2304 return 0;
2305}
2306
2307static int generic_hdmi_init_per_pins(struct hda_codec *codec)
2308{
2309 struct hdmi_spec *spec = codec->spec;
2310 int pin_idx;
2311
2312 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2313 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2314
2315 per_pin->codec = codec;
2316 mutex_init(&per_pin->lock);
2317 INIT_DELAYED_WORK(&per_pin->work, hdmi_repoll_eld);
2318 eld_proc_new(per_pin, pin_idx);
2319 }
2320 return 0;
2321}
2322
2323static int generic_hdmi_init(struct hda_codec *codec)
2324{
2325 struct hdmi_spec *spec = codec->spec;
2326 int pin_idx;
2327
2328 mutex_lock(&spec->bind_lock);
2329 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2330 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2331 hda_nid_t pin_nid = per_pin->pin_nid;
2332 int dev_id = per_pin->dev_id;
2333
2334 snd_hda_set_dev_select(codec, pin_nid, dev_id);
2335 hdmi_init_pin(codec, pin_nid);
2336 if (codec_has_acomp(codec))
2337 continue;
2338 snd_hda_jack_detect_enable_callback_mst(codec, pin_nid, dev_id,
2339 jack_callback);
2340 }
2341 mutex_unlock(&spec->bind_lock);
2342 return 0;
2343}
2344
2345static void hdmi_array_init(struct hdmi_spec *spec, int nums)
2346{
2347 snd_array_init(&spec->pins, sizeof(struct hdmi_spec_per_pin), nums);
2348 snd_array_init(&spec->cvts, sizeof(struct hdmi_spec_per_cvt), nums);
2349}
2350
2351static void hdmi_array_free(struct hdmi_spec *spec)
2352{
2353 snd_array_free(&spec->pins);
2354 snd_array_free(&spec->cvts);
2355}
2356
2357static void generic_spec_free(struct hda_codec *codec)
2358{
2359 struct hdmi_spec *spec = codec->spec;
2360
2361 if (spec) {
2362 hdmi_array_free(spec);
2363 kfree(spec);
2364 codec->spec = NULL;
2365 }
2366 codec->dp_mst = false;
2367}
2368
2369static void generic_hdmi_free(struct hda_codec *codec)
2370{
2371 struct hdmi_spec *spec = codec->spec;
2372 int pin_idx, pcm_idx;
2373
2374 if (spec->acomp_registered) {
2375 snd_hdac_acomp_exit(&codec->bus->core);
2376 } else if (codec_has_acomp(codec)) {
2377 snd_hdac_acomp_register_notifier(&codec->bus->core, NULL);
2378 }
2379 codec->relaxed_resume = 0;
2380
2381 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2382 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2383 cancel_delayed_work_sync(&per_pin->work);
2384 eld_proc_free(per_pin);
2385 }
2386
2387 for (pcm_idx = 0; pcm_idx < spec->pcm_used; pcm_idx++) {
2388 if (spec->pcm_rec[pcm_idx].jack == NULL)
2389 continue;
2390 if (spec->dyn_pcm_assign)
2391 snd_device_free(codec->card,
2392 spec->pcm_rec[pcm_idx].jack);
2393 else
2394 spec->pcm_rec[pcm_idx].jack = NULL;
2395 }
2396
2397 generic_spec_free(codec);
2398}
2399
2400#ifdef CONFIG_PM
2401static int generic_hdmi_resume(struct hda_codec *codec)
2402{
2403 struct hdmi_spec *spec = codec->spec;
2404 int pin_idx;
2405
2406 codec->patch_ops.init(codec);
2407 snd_hda_regmap_sync(codec);
2408
2409 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2410 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2411 hdmi_present_sense(per_pin, 1);
2412 }
2413 return 0;
2414}
2415#endif
2416
2417static const struct hda_codec_ops generic_hdmi_patch_ops = {
2418 .init = generic_hdmi_init,
2419 .free = generic_hdmi_free,
2420 .build_pcms = generic_hdmi_build_pcms,
2421 .build_controls = generic_hdmi_build_controls,
2422 .unsol_event = hdmi_unsol_event,
2423#ifdef CONFIG_PM
2424 .resume = generic_hdmi_resume,
2425#endif
2426};
2427
2428static const struct hdmi_ops generic_standard_hdmi_ops = {
2429 .pin_get_eld = hdmi_pin_get_eld,
2430 .pin_setup_infoframe = hdmi_pin_setup_infoframe,
2431 .pin_hbr_setup = hdmi_pin_hbr_setup,
2432 .setup_stream = hdmi_setup_stream,
2433};
2434
2435/* allocate codec->spec and assign/initialize generic parser ops */
2436static int alloc_generic_hdmi(struct hda_codec *codec)
2437{
2438 struct hdmi_spec *spec;
2439
2440 spec = kzalloc(sizeof(*spec), GFP_KERNEL);
2441 if (!spec)
2442 return -ENOMEM;
2443
2444 spec->codec = codec;
2445 spec->ops = generic_standard_hdmi_ops;
2446 spec->dev_num = 1; /* initialize to 1 */
2447 mutex_init(&spec->pcm_lock);
2448 mutex_init(&spec->bind_lock);
2449 snd_hdac_register_chmap_ops(&codec->core, &spec->chmap);
2450
2451 spec->chmap.ops.get_chmap = hdmi_get_chmap;
2452 spec->chmap.ops.set_chmap = hdmi_set_chmap;
2453 spec->chmap.ops.is_pcm_attached = is_hdmi_pcm_attached;
2454 spec->chmap.ops.get_spk_alloc = hdmi_get_spk_alloc,
2455
2456 codec->spec = spec;
2457 hdmi_array_init(spec, 4);
2458
2459 codec->patch_ops = generic_hdmi_patch_ops;
2460
2461 return 0;
2462}
2463
2464/* generic HDMI parser */
2465static int patch_generic_hdmi(struct hda_codec *codec)
2466{
2467 int err;
2468
2469 err = alloc_generic_hdmi(codec);
2470 if (err < 0)
2471 return err;
2472
2473 err = hdmi_parse_codec(codec);
2474 if (err < 0) {
2475 generic_spec_free(codec);
2476 return err;
2477 }
2478
2479 generic_hdmi_init_per_pins(codec);
2480 return 0;
2481}
2482
2483/*
2484 * generic audio component binding
2485 */
2486
2487/* turn on / off the unsol event jack detection dynamically */
2488static void reprogram_jack_detect(struct hda_codec *codec, hda_nid_t nid,
2489 int dev_id, bool use_acomp)
2490{
2491 struct hda_jack_tbl *tbl;
2492
2493 tbl = snd_hda_jack_tbl_get_mst(codec, nid, dev_id);
2494 if (tbl) {
2495 /* clear unsol even if component notifier is used, or re-enable
2496 * if notifier is cleared
2497 */
2498 unsigned int val = use_acomp ? 0 : (AC_USRSP_EN | tbl->tag);
2499 snd_hda_codec_write_cache(codec, nid, 0,
2500 AC_VERB_SET_UNSOLICITED_ENABLE, val);
2501 }
2502}
2503
2504/* set up / clear component notifier dynamically */
2505static void generic_acomp_notifier_set(struct drm_audio_component *acomp,
2506 bool use_acomp)
2507{
2508 struct hdmi_spec *spec;
2509 int i;
2510
2511 spec = container_of(acomp->audio_ops, struct hdmi_spec, drm_audio_ops);
2512 mutex_lock(&spec->bind_lock);
2513 spec->use_acomp_notifier = use_acomp;
2514 spec->codec->relaxed_resume = use_acomp;
2515 spec->codec->bus->keep_power = 0;
2516 /* reprogram each jack detection logic depending on the notifier */
2517 for (i = 0; i < spec->num_pins; i++)
2518 reprogram_jack_detect(spec->codec,
2519 get_pin(spec, i)->pin_nid,
2520 get_pin(spec, i)->dev_id,
2521 use_acomp);
2522 mutex_unlock(&spec->bind_lock);
2523}
2524
2525/* enable / disable the notifier via master bind / unbind */
2526static int generic_acomp_master_bind(struct device *dev,
2527 struct drm_audio_component *acomp)
2528{
2529 generic_acomp_notifier_set(acomp, true);
2530 return 0;
2531}
2532
2533static void generic_acomp_master_unbind(struct device *dev,
2534 struct drm_audio_component *acomp)
2535{
2536 generic_acomp_notifier_set(acomp, false);
2537}
2538
2539/* check whether both HD-audio and DRM PCI devices belong to the same bus */
2540static int match_bound_vga(struct device *dev, int subtype, void *data)
2541{
2542 struct hdac_bus *bus = data;
2543 struct pci_dev *pci, *master;
2544
2545 if (!dev_is_pci(dev) || !dev_is_pci(bus->dev))
2546 return 0;
2547 master = to_pci_dev(bus->dev);
2548 pci = to_pci_dev(dev);
2549 return master->bus == pci->bus;
2550}
2551
2552/* audio component notifier for AMD/Nvidia HDMI codecs */
2553static void generic_acomp_pin_eld_notify(void *audio_ptr, int port, int dev_id)
2554{
2555 struct hda_codec *codec = audio_ptr;
2556 struct hdmi_spec *spec = codec->spec;
2557 hda_nid_t pin_nid = spec->port2pin(codec, port);
2558
2559 if (!pin_nid)
2560 return;
2561 if (get_wcaps_type(get_wcaps(codec, pin_nid)) != AC_WID_PIN)
2562 return;
2563 /* skip notification during system suspend (but not in runtime PM);
2564 * the state will be updated at resume
2565 */
2566 if (snd_power_get_state(codec->card) != SNDRV_CTL_POWER_D0)
2567 return;
2568 /* ditto during suspend/resume process itself */
2569 if (snd_hdac_is_in_pm(&codec->core))
2570 return;
2571
2572 check_presence_and_report(codec, pin_nid, dev_id);
2573}
2574
2575/* set up the private drm_audio_ops from the template */
2576static void setup_drm_audio_ops(struct hda_codec *codec,
2577 const struct drm_audio_component_audio_ops *ops)
2578{
2579 struct hdmi_spec *spec = codec->spec;
2580
2581 spec->drm_audio_ops.audio_ptr = codec;
2582 /* intel_audio_codec_enable() or intel_audio_codec_disable()
2583 * will call pin_eld_notify with using audio_ptr pointer
2584 * We need make sure audio_ptr is really setup
2585 */
2586 wmb();
2587 spec->drm_audio_ops.pin2port = ops->pin2port;
2588 spec->drm_audio_ops.pin_eld_notify = ops->pin_eld_notify;
2589 spec->drm_audio_ops.master_bind = ops->master_bind;
2590 spec->drm_audio_ops.master_unbind = ops->master_unbind;
2591}
2592
2593/* initialize the generic HDMI audio component */
2594static void generic_acomp_init(struct hda_codec *codec,
2595 const struct drm_audio_component_audio_ops *ops,
2596 int (*port2pin)(struct hda_codec *, int))
2597{
2598 struct hdmi_spec *spec = codec->spec;
2599
2600 if (!enable_acomp) {
2601 codec_info(codec, "audio component disabled by module option\n");
2602 return;
2603 }
2604
2605 spec->port2pin = port2pin;
2606 setup_drm_audio_ops(codec, ops);
2607 if (!snd_hdac_acomp_init(&codec->bus->core, &spec->drm_audio_ops,
2608 match_bound_vga, 0)) {
2609 spec->acomp_registered = true;
2610 }
2611}
2612
2613/*
2614 * Intel codec parsers and helpers
2615 */
2616
2617#define INTEL_GET_VENDOR_VERB 0xf81
2618#define INTEL_SET_VENDOR_VERB 0x781
2619#define INTEL_EN_DP12 0x02 /* enable DP 1.2 features */
2620#define INTEL_EN_ALL_PIN_CVTS 0x01 /* enable 2nd & 3rd pins and convertors */
2621
2622static void intel_haswell_enable_all_pins(struct hda_codec *codec,
2623 bool update_tree)
2624{
2625 unsigned int vendor_param;
2626 struct hdmi_spec *spec = codec->spec;
2627
2628 vendor_param = snd_hda_codec_read(codec, spec->vendor_nid, 0,
2629 INTEL_GET_VENDOR_VERB, 0);
2630 if (vendor_param == -1 || vendor_param & INTEL_EN_ALL_PIN_CVTS)
2631 return;
2632
2633 vendor_param |= INTEL_EN_ALL_PIN_CVTS;
2634 vendor_param = snd_hda_codec_read(codec, spec->vendor_nid, 0,
2635 INTEL_SET_VENDOR_VERB, vendor_param);
2636 if (vendor_param == -1)
2637 return;
2638
2639 if (update_tree)
2640 snd_hda_codec_update_widgets(codec);
2641}
2642
2643static void intel_haswell_fixup_enable_dp12(struct hda_codec *codec)
2644{
2645 unsigned int vendor_param;
2646 struct hdmi_spec *spec = codec->spec;
2647
2648 vendor_param = snd_hda_codec_read(codec, spec->vendor_nid, 0,
2649 INTEL_GET_VENDOR_VERB, 0);
2650 if (vendor_param == -1 || vendor_param & INTEL_EN_DP12)
2651 return;
2652
2653 /* enable DP1.2 mode */
2654 vendor_param |= INTEL_EN_DP12;
2655 snd_hdac_regmap_add_vendor_verb(&codec->core, INTEL_SET_VENDOR_VERB);
2656 snd_hda_codec_write_cache(codec, spec->vendor_nid, 0,
2657 INTEL_SET_VENDOR_VERB, vendor_param);
2658}
2659
2660/* Haswell needs to re-issue the vendor-specific verbs before turning to D0.
2661 * Otherwise you may get severe h/w communication errors.
2662 */
2663static void haswell_set_power_state(struct hda_codec *codec, hda_nid_t fg,
2664 unsigned int power_state)
2665{
2666 if (power_state == AC_PWRST_D0) {
2667 intel_haswell_enable_all_pins(codec, false);
2668 intel_haswell_fixup_enable_dp12(codec);
2669 }
2670
2671 snd_hda_codec_read(codec, fg, 0, AC_VERB_SET_POWER_STATE, power_state);
2672 snd_hda_codec_set_power_to_all(codec, fg, power_state);
2673}
2674
2675/* There is a fixed mapping between audio pin node and display port.
2676 * on SNB, IVY, HSW, BSW, SKL, BXT, KBL:
2677 * Pin Widget 5 - PORT B (port = 1 in i915 driver)
2678 * Pin Widget 6 - PORT C (port = 2 in i915 driver)
2679 * Pin Widget 7 - PORT D (port = 3 in i915 driver)
2680 *
2681 * on VLV, ILK:
2682 * Pin Widget 4 - PORT B (port = 1 in i915 driver)
2683 * Pin Widget 5 - PORT C (port = 2 in i915 driver)
2684 * Pin Widget 6 - PORT D (port = 3 in i915 driver)
2685 */
2686static int intel_base_nid(struct hda_codec *codec)
2687{
2688 switch (codec->core.vendor_id) {
2689 case 0x80860054: /* ILK */
2690 case 0x80862804: /* ILK */
2691 case 0x80862882: /* VLV */
2692 return 4;
2693 default:
2694 return 5;
2695 }
2696}
2697
2698static int intel_pin2port(void *audio_ptr, int pin_nid)
2699{
2700 struct hda_codec *codec = audio_ptr;
2701 struct hdmi_spec *spec = codec->spec;
2702 int base_nid, i;
2703
2704 if (!spec->port_num) {
2705 base_nid = intel_base_nid(codec);
2706 if (WARN_ON(pin_nid < base_nid || pin_nid >= base_nid + 3))
2707 return -1;
2708 return pin_nid - base_nid + 1;
2709 }
2710
2711 /*
2712 * looking for the pin number in the mapping table and return
2713 * the index which indicate the port number
2714 */
2715 for (i = 0; i < spec->port_num; i++) {
2716 if (pin_nid == spec->port_map[i])
2717 return i;
2718 }
2719
2720 codec_info(codec, "Can't find the HDMI/DP port for pin %d\n", pin_nid);
2721 return -1;
2722}
2723
2724static int intel_port2pin(struct hda_codec *codec, int port)
2725{
2726 struct hdmi_spec *spec = codec->spec;
2727
2728 if (!spec->port_num) {
2729 /* we assume only from port-B to port-D */
2730 if (port < 1 || port > 3)
2731 return 0;
2732 return port + intel_base_nid(codec) - 1;
2733 }
2734
2735 if (port < 0 || port >= spec->port_num)
2736 return 0;
2737 return spec->port_map[port];
2738}
2739
2740static void intel_pin_eld_notify(void *audio_ptr, int port, int pipe)
2741{
2742 struct hda_codec *codec = audio_ptr;
2743 int pin_nid;
2744 int dev_id = pipe;
2745
2746 pin_nid = intel_port2pin(codec, port);
2747 if (!pin_nid)
2748 return;
2749 /* skip notification during system suspend (but not in runtime PM);
2750 * the state will be updated at resume
2751 */
2752 if (snd_power_get_state(codec->card) != SNDRV_CTL_POWER_D0)
2753 return;
2754 /* ditto during suspend/resume process itself */
2755 if (snd_hdac_is_in_pm(&codec->core))
2756 return;
2757
2758 snd_hdac_i915_set_bclk(&codec->bus->core);
2759 check_presence_and_report(codec, pin_nid, dev_id);
2760}
2761
2762static const struct drm_audio_component_audio_ops intel_audio_ops = {
2763 .pin2port = intel_pin2port,
2764 .pin_eld_notify = intel_pin_eld_notify,
2765};
2766
2767/* register i915 component pin_eld_notify callback */
2768static void register_i915_notifier(struct hda_codec *codec)
2769{
2770 struct hdmi_spec *spec = codec->spec;
2771
2772 spec->use_acomp_notifier = true;
2773 spec->port2pin = intel_port2pin;
2774 setup_drm_audio_ops(codec, &intel_audio_ops);
2775 snd_hdac_acomp_register_notifier(&codec->bus->core,
2776 &spec->drm_audio_ops);
2777 /* no need for forcible resume for jack check thanks to notifier */
2778 codec->relaxed_resume = 1;
2779}
2780
2781/* setup_stream ops override for HSW+ */
2782static int i915_hsw_setup_stream(struct hda_codec *codec, hda_nid_t cvt_nid,
2783 hda_nid_t pin_nid, int dev_id, u32 stream_tag,
2784 int format)
2785{
2786 haswell_verify_D0(codec, cvt_nid, pin_nid);
2787 return hdmi_setup_stream(codec, cvt_nid, pin_nid, dev_id,
2788 stream_tag, format);
2789}
2790
2791/* pin_cvt_fixup ops override for HSW+ and VLV+ */
2792static void i915_pin_cvt_fixup(struct hda_codec *codec,
2793 struct hdmi_spec_per_pin *per_pin,
2794 hda_nid_t cvt_nid)
2795{
2796 if (per_pin) {
2797 haswell_verify_D0(codec, per_pin->cvt_nid, per_pin->pin_nid);
2798 snd_hda_set_dev_select(codec, per_pin->pin_nid,
2799 per_pin->dev_id);
2800 intel_verify_pin_cvt_connect(codec, per_pin);
2801 intel_not_share_assigned_cvt(codec, per_pin->pin_nid,
2802 per_pin->dev_id, per_pin->mux_idx);
2803 } else {
2804 intel_not_share_assigned_cvt_nid(codec, 0, 0, cvt_nid);
2805 }
2806}
2807
2808/* precondition and allocation for Intel codecs */
2809static int alloc_intel_hdmi(struct hda_codec *codec)
2810{
2811 int err;
2812
2813 /* requires i915 binding */
2814 if (!codec->bus->core.audio_component) {
2815 codec_info(codec, "No i915 binding for Intel HDMI/DP codec\n");
2816 /* set probe_id here to prevent generic fallback binding */
2817 codec->probe_id = HDA_CODEC_ID_SKIP_PROBE;
2818 return -ENODEV;
2819 }
2820
2821 err = alloc_generic_hdmi(codec);
2822 if (err < 0)
2823 return err;
2824 /* no need to handle unsol events */
2825 codec->patch_ops.unsol_event = NULL;
2826 return 0;
2827}
2828
2829/* parse and post-process for Intel codecs */
2830static int parse_intel_hdmi(struct hda_codec *codec)
2831{
2832 int err, retries = 3;
2833
2834 do {
2835 err = hdmi_parse_codec(codec);
2836 } while (err < 0 && retries--);
2837
2838 if (err < 0) {
2839 generic_spec_free(codec);
2840 return err;
2841 }
2842
2843 generic_hdmi_init_per_pins(codec);
2844 register_i915_notifier(codec);
2845 return 0;
2846}
2847
2848/* Intel Haswell and onwards; audio component with eld notifier */
2849static int intel_hsw_common_init(struct hda_codec *codec, hda_nid_t vendor_nid,
2850 const int *port_map, int port_num)
2851{
2852 struct hdmi_spec *spec;
2853 int err;
2854
2855 err = alloc_intel_hdmi(codec);
2856 if (err < 0)
2857 return err;
2858 spec = codec->spec;
2859 codec->dp_mst = true;
2860 spec->dyn_pcm_assign = true;
2861 spec->vendor_nid = vendor_nid;
2862 spec->port_map = port_map;
2863 spec->port_num = port_num;
2864 spec->intel_hsw_fixup = true;
2865
2866 intel_haswell_enable_all_pins(codec, true);
2867 intel_haswell_fixup_enable_dp12(codec);
2868
2869 codec->display_power_control = 1;
2870
2871 codec->patch_ops.set_power_state = haswell_set_power_state;
2872 codec->depop_delay = 0;
2873 codec->auto_runtime_pm = 1;
2874
2875 spec->ops.setup_stream = i915_hsw_setup_stream;
2876 spec->ops.pin_cvt_fixup = i915_pin_cvt_fixup;
2877
2878 /*
2879 * Enable silent stream feature, if it is enabled via
2880 * module param or Kconfig option
2881 */
2882 if (enable_silent_stream)
2883 spec->send_silent_stream = true;
2884
2885 return parse_intel_hdmi(codec);
2886}
2887
2888static int patch_i915_hsw_hdmi(struct hda_codec *codec)
2889{
2890 return intel_hsw_common_init(codec, 0x08, NULL, 0);
2891}
2892
2893static int patch_i915_glk_hdmi(struct hda_codec *codec)
2894{
2895 return intel_hsw_common_init(codec, 0x0b, NULL, 0);
2896}
2897
2898static int patch_i915_icl_hdmi(struct hda_codec *codec)
2899{
2900 /*
2901 * pin to port mapping table where the value indicate the pin number and
2902 * the index indicate the port number.
2903 */
2904 static const int map[] = {0x0, 0x4, 0x6, 0x8, 0xa, 0xb};
2905
2906 return intel_hsw_common_init(codec, 0x02, map, ARRAY_SIZE(map));
2907}
2908
2909static int patch_i915_tgl_hdmi(struct hda_codec *codec)
2910{
2911 /*
2912 * pin to port mapping table where the value indicate the pin number and
2913 * the index indicate the port number.
2914 */
2915 static const int map[] = {0x4, 0x6, 0x8, 0xa, 0xb, 0xc, 0xd, 0xe, 0xf};
2916
2917 return intel_hsw_common_init(codec, 0x02, map, ARRAY_SIZE(map));
2918}
2919
2920/* Intel Baytrail and Braswell; with eld notifier */
2921static int patch_i915_byt_hdmi(struct hda_codec *codec)
2922{
2923 struct hdmi_spec *spec;
2924 int err;
2925
2926 err = alloc_intel_hdmi(codec);
2927 if (err < 0)
2928 return err;
2929 spec = codec->spec;
2930
2931 /* For Valleyview/Cherryview, only the display codec is in the display
2932 * power well and can use link_power ops to request/release the power.
2933 */
2934 codec->display_power_control = 1;
2935
2936 codec->depop_delay = 0;
2937 codec->auto_runtime_pm = 1;
2938
2939 spec->ops.pin_cvt_fixup = i915_pin_cvt_fixup;
2940
2941 return parse_intel_hdmi(codec);
2942}
2943
2944/* Intel IronLake, SandyBridge and IvyBridge; with eld notifier */
2945static int patch_i915_cpt_hdmi(struct hda_codec *codec)
2946{
2947 int err;
2948
2949 err = alloc_intel_hdmi(codec);
2950 if (err < 0)
2951 return err;
2952 return parse_intel_hdmi(codec);
2953}
2954
2955/*
2956 * Shared non-generic implementations
2957 */
2958
2959static int simple_playback_build_pcms(struct hda_codec *codec)
2960{
2961 struct hdmi_spec *spec = codec->spec;
2962 struct hda_pcm *info;
2963 unsigned int chans;
2964 struct hda_pcm_stream *pstr;
2965 struct hdmi_spec_per_cvt *per_cvt;
2966
2967 per_cvt = get_cvt(spec, 0);
2968 chans = get_wcaps(codec, per_cvt->cvt_nid);
2969 chans = get_wcaps_channels(chans);
2970
2971 info = snd_hda_codec_pcm_new(codec, "HDMI 0");
2972 if (!info)
2973 return -ENOMEM;
2974 spec->pcm_rec[0].pcm = info;
2975 info->pcm_type = HDA_PCM_TYPE_HDMI;
2976 pstr = &info->stream[SNDRV_PCM_STREAM_PLAYBACK];
2977 *pstr = spec->pcm_playback;
2978 pstr->nid = per_cvt->cvt_nid;
2979 if (pstr->channels_max <= 2 && chans && chans <= 16)
2980 pstr->channels_max = chans;
2981
2982 return 0;
2983}
2984
2985/* unsolicited event for jack sensing */
2986static void simple_hdmi_unsol_event(struct hda_codec *codec,
2987 unsigned int res)
2988{
2989 snd_hda_jack_set_dirty_all(codec);
2990 snd_hda_jack_report_sync(codec);
2991}
2992
2993/* generic_hdmi_build_jack can be used for simple_hdmi, too,
2994 * as long as spec->pins[] is set correctly
2995 */
2996#define simple_hdmi_build_jack generic_hdmi_build_jack
2997
2998static int simple_playback_build_controls(struct hda_codec *codec)
2999{
3000 struct hdmi_spec *spec = codec->spec;
3001 struct hdmi_spec_per_cvt *per_cvt;
3002 int err;
3003
3004 per_cvt = get_cvt(spec, 0);
3005 err = snd_hda_create_dig_out_ctls(codec, per_cvt->cvt_nid,
3006 per_cvt->cvt_nid,
3007 HDA_PCM_TYPE_HDMI);
3008 if (err < 0)
3009 return err;
3010 return simple_hdmi_build_jack(codec, 0);
3011}
3012
3013static int simple_playback_init(struct hda_codec *codec)
3014{
3015 struct hdmi_spec *spec = codec->spec;
3016 struct hdmi_spec_per_pin *per_pin = get_pin(spec, 0);
3017 hda_nid_t pin = per_pin->pin_nid;
3018
3019 snd_hda_codec_write(codec, pin, 0,
3020 AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT);
3021 /* some codecs require to unmute the pin */
3022 if (get_wcaps(codec, pin) & AC_WCAP_OUT_AMP)
3023 snd_hda_codec_write(codec, pin, 0, AC_VERB_SET_AMP_GAIN_MUTE,
3024 AMP_OUT_UNMUTE);
3025 snd_hda_jack_detect_enable(codec, pin, per_pin->dev_id);
3026 return 0;
3027}
3028
3029static void simple_playback_free(struct hda_codec *codec)
3030{
3031 struct hdmi_spec *spec = codec->spec;
3032
3033 hdmi_array_free(spec);
3034 kfree(spec);
3035}
3036
3037/*
3038 * Nvidia specific implementations
3039 */
3040
3041#define Nv_VERB_SET_Channel_Allocation 0xF79
3042#define Nv_VERB_SET_Info_Frame_Checksum 0xF7A
3043#define Nv_VERB_SET_Audio_Protection_On 0xF98
3044#define Nv_VERB_SET_Audio_Protection_Off 0xF99
3045
3046#define nvhdmi_master_con_nid_7x 0x04
3047#define nvhdmi_master_pin_nid_7x 0x05
3048
3049static const hda_nid_t nvhdmi_con_nids_7x[4] = {
3050 /*front, rear, clfe, rear_surr */
3051 0x6, 0x8, 0xa, 0xc,
3052};
3053
3054static const struct hda_verb nvhdmi_basic_init_7x_2ch[] = {
3055 /* set audio protect on */
3056 { 0x1, Nv_VERB_SET_Audio_Protection_On, 0x1},
3057 /* enable digital output on pin widget */
3058 { 0x5, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
3059 {} /* terminator */
3060};
3061
3062static const struct hda_verb nvhdmi_basic_init_7x_8ch[] = {
3063 /* set audio protect on */
3064 { 0x1, Nv_VERB_SET_Audio_Protection_On, 0x1},
3065 /* enable digital output on pin widget */
3066 { 0x5, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
3067 { 0x7, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
3068 { 0x9, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
3069 { 0xb, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
3070 { 0xd, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
3071 {} /* terminator */
3072};
3073
3074#ifdef LIMITED_RATE_FMT_SUPPORT
3075/* support only the safe format and rate */
3076#define SUPPORTED_RATES SNDRV_PCM_RATE_48000
3077#define SUPPORTED_MAXBPS 16
3078#define SUPPORTED_FORMATS SNDRV_PCM_FMTBIT_S16_LE
3079#else
3080/* support all rates and formats */
3081#define SUPPORTED_RATES \
3082 (SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000 |\
3083 SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |\
3084 SNDRV_PCM_RATE_192000)
3085#define SUPPORTED_MAXBPS 24
3086#define SUPPORTED_FORMATS \
3087 (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE)
3088#endif
3089
3090static int nvhdmi_7x_init_2ch(struct hda_codec *codec)
3091{
3092 snd_hda_sequence_write(codec, nvhdmi_basic_init_7x_2ch);
3093 return 0;
3094}
3095
3096static int nvhdmi_7x_init_8ch(struct hda_codec *codec)
3097{
3098 snd_hda_sequence_write(codec, nvhdmi_basic_init_7x_8ch);
3099 return 0;
3100}
3101
3102static const unsigned int channels_2_6_8[] = {
3103 2, 6, 8
3104};
3105
3106static const unsigned int channels_2_8[] = {
3107 2, 8
3108};
3109
3110static const struct snd_pcm_hw_constraint_list hw_constraints_2_6_8_channels = {
3111 .count = ARRAY_SIZE(channels_2_6_8),
3112 .list = channels_2_6_8,
3113 .mask = 0,
3114};
3115
3116static const struct snd_pcm_hw_constraint_list hw_constraints_2_8_channels = {
3117 .count = ARRAY_SIZE(channels_2_8),
3118 .list = channels_2_8,
3119 .mask = 0,
3120};
3121
3122static int simple_playback_pcm_open(struct hda_pcm_stream *hinfo,
3123 struct hda_codec *codec,
3124 struct snd_pcm_substream *substream)
3125{
3126 struct hdmi_spec *spec = codec->spec;
3127 const struct snd_pcm_hw_constraint_list *hw_constraints_channels = NULL;
3128
3129 switch (codec->preset->vendor_id) {
3130 case 0x10de0002:
3131 case 0x10de0003:
3132 case 0x10de0005:
3133 case 0x10de0006:
3134 hw_constraints_channels = &hw_constraints_2_8_channels;
3135 break;
3136 case 0x10de0007:
3137 hw_constraints_channels = &hw_constraints_2_6_8_channels;
3138 break;
3139 default:
3140 break;
3141 }
3142
3143 if (hw_constraints_channels != NULL) {
3144 snd_pcm_hw_constraint_list(substream->runtime, 0,
3145 SNDRV_PCM_HW_PARAM_CHANNELS,
3146 hw_constraints_channels);
3147 } else {
3148 snd_pcm_hw_constraint_step(substream->runtime, 0,
3149 SNDRV_PCM_HW_PARAM_CHANNELS, 2);
3150 }
3151
3152 return snd_hda_multi_out_dig_open(codec, &spec->multiout);
3153}
3154
3155static int simple_playback_pcm_close(struct hda_pcm_stream *hinfo,
3156 struct hda_codec *codec,
3157 struct snd_pcm_substream *substream)
3158{
3159 struct hdmi_spec *spec = codec->spec;
3160 return snd_hda_multi_out_dig_close(codec, &spec->multiout);
3161}
3162
3163static int simple_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
3164 struct hda_codec *codec,
3165 unsigned int stream_tag,
3166 unsigned int format,
3167 struct snd_pcm_substream *substream)
3168{
3169 struct hdmi_spec *spec = codec->spec;
3170 return snd_hda_multi_out_dig_prepare(codec, &spec->multiout,
3171 stream_tag, format, substream);
3172}
3173
3174static const struct hda_pcm_stream simple_pcm_playback = {
3175 .substreams = 1,
3176 .channels_min = 2,
3177 .channels_max = 2,
3178 .ops = {
3179 .open = simple_playback_pcm_open,
3180 .close = simple_playback_pcm_close,
3181 .prepare = simple_playback_pcm_prepare
3182 },
3183};
3184
3185static const struct hda_codec_ops simple_hdmi_patch_ops = {
3186 .build_controls = simple_playback_build_controls,
3187 .build_pcms = simple_playback_build_pcms,
3188 .init = simple_playback_init,
3189 .free = simple_playback_free,
3190 .unsol_event = simple_hdmi_unsol_event,
3191};
3192
3193static int patch_simple_hdmi(struct hda_codec *codec,
3194 hda_nid_t cvt_nid, hda_nid_t pin_nid)
3195{
3196 struct hdmi_spec *spec;
3197 struct hdmi_spec_per_cvt *per_cvt;
3198 struct hdmi_spec_per_pin *per_pin;
3199
3200 spec = kzalloc(sizeof(*spec), GFP_KERNEL);
3201 if (!spec)
3202 return -ENOMEM;
3203
3204 spec->codec = codec;
3205 codec->spec = spec;
3206 hdmi_array_init(spec, 1);
3207
3208 spec->multiout.num_dacs = 0; /* no analog */
3209 spec->multiout.max_channels = 2;
3210 spec->multiout.dig_out_nid = cvt_nid;
3211 spec->num_cvts = 1;
3212 spec->num_pins = 1;
3213 per_pin = snd_array_new(&spec->pins);
3214 per_cvt = snd_array_new(&spec->cvts);
3215 if (!per_pin || !per_cvt) {
3216 simple_playback_free(codec);
3217 return -ENOMEM;
3218 }
3219 per_cvt->cvt_nid = cvt_nid;
3220 per_pin->pin_nid = pin_nid;
3221 spec->pcm_playback = simple_pcm_playback;
3222
3223 codec->patch_ops = simple_hdmi_patch_ops;
3224
3225 return 0;
3226}
3227
3228static void nvhdmi_8ch_7x_set_info_frame_parameters(struct hda_codec *codec,
3229 int channels)
3230{
3231 unsigned int chanmask;
3232 int chan = channels ? (channels - 1) : 1;
3233
3234 switch (channels) {
3235 default:
3236 case 0:
3237 case 2:
3238 chanmask = 0x00;
3239 break;
3240 case 4:
3241 chanmask = 0x08;
3242 break;
3243 case 6:
3244 chanmask = 0x0b;
3245 break;
3246 case 8:
3247 chanmask = 0x13;
3248 break;
3249 }
3250
3251 /* Set the audio infoframe channel allocation and checksum fields. The
3252 * channel count is computed implicitly by the hardware. */
3253 snd_hda_codec_write(codec, 0x1, 0,
3254 Nv_VERB_SET_Channel_Allocation, chanmask);
3255
3256 snd_hda_codec_write(codec, 0x1, 0,
3257 Nv_VERB_SET_Info_Frame_Checksum,
3258 (0x71 - chan - chanmask));
3259}
3260
3261static int nvhdmi_8ch_7x_pcm_close(struct hda_pcm_stream *hinfo,
3262 struct hda_codec *codec,
3263 struct snd_pcm_substream *substream)
3264{
3265 struct hdmi_spec *spec = codec->spec;
3266 int i;
3267
3268 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x,
3269 0, AC_VERB_SET_CHANNEL_STREAMID, 0);
3270 for (i = 0; i < 4; i++) {
3271 /* set the stream id */
3272 snd_hda_codec_write(codec, nvhdmi_con_nids_7x[i], 0,
3273 AC_VERB_SET_CHANNEL_STREAMID, 0);
3274 /* set the stream format */
3275 snd_hda_codec_write(codec, nvhdmi_con_nids_7x[i], 0,
3276 AC_VERB_SET_STREAM_FORMAT, 0);
3277 }
3278
3279 /* The audio hardware sends a channel count of 0x7 (8ch) when all the
3280 * streams are disabled. */
3281 nvhdmi_8ch_7x_set_info_frame_parameters(codec, 8);
3282
3283 return snd_hda_multi_out_dig_close(codec, &spec->multiout);
3284}
3285
3286static int nvhdmi_8ch_7x_pcm_prepare(struct hda_pcm_stream *hinfo,
3287 struct hda_codec *codec,
3288 unsigned int stream_tag,
3289 unsigned int format,
3290 struct snd_pcm_substream *substream)
3291{
3292 int chs;
3293 unsigned int dataDCC2, channel_id;
3294 int i;
3295 struct hdmi_spec *spec = codec->spec;
3296 struct hda_spdif_out *spdif;
3297 struct hdmi_spec_per_cvt *per_cvt;
3298
3299 mutex_lock(&codec->spdif_mutex);
3300 per_cvt = get_cvt(spec, 0);
3301 spdif = snd_hda_spdif_out_of_nid(codec, per_cvt->cvt_nid);
3302
3303 chs = substream->runtime->channels;
3304
3305 dataDCC2 = 0x2;
3306
3307 /* turn off SPDIF once; otherwise the IEC958 bits won't be updated */
3308 if (codec->spdif_status_reset && (spdif->ctls & AC_DIG1_ENABLE))
3309 snd_hda_codec_write(codec,
3310 nvhdmi_master_con_nid_7x,
3311 0,
3312 AC_VERB_SET_DIGI_CONVERT_1,
3313 spdif->ctls & ~AC_DIG1_ENABLE & 0xff);
3314
3315 /* set the stream id */
3316 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, 0,
3317 AC_VERB_SET_CHANNEL_STREAMID, (stream_tag << 4) | 0x0);
3318
3319 /* set the stream format */
3320 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, 0,
3321 AC_VERB_SET_STREAM_FORMAT, format);
3322
3323 /* turn on again (if needed) */
3324 /* enable and set the channel status audio/data flag */
3325 if (codec->spdif_status_reset && (spdif->ctls & AC_DIG1_ENABLE)) {
3326 snd_hda_codec_write(codec,
3327 nvhdmi_master_con_nid_7x,
3328 0,
3329 AC_VERB_SET_DIGI_CONVERT_1,
3330 spdif->ctls & 0xff);
3331 snd_hda_codec_write(codec,
3332 nvhdmi_master_con_nid_7x,
3333 0,
3334 AC_VERB_SET_DIGI_CONVERT_2, dataDCC2);
3335 }
3336
3337 for (i = 0; i < 4; i++) {
3338 if (chs == 2)
3339 channel_id = 0;
3340 else
3341 channel_id = i * 2;
3342
3343 /* turn off SPDIF once;
3344 *otherwise the IEC958 bits won't be updated
3345 */
3346 if (codec->spdif_status_reset &&
3347 (spdif->ctls & AC_DIG1_ENABLE))
3348 snd_hda_codec_write(codec,
3349 nvhdmi_con_nids_7x[i],
3350 0,
3351 AC_VERB_SET_DIGI_CONVERT_1,
3352 spdif->ctls & ~AC_DIG1_ENABLE & 0xff);
3353 /* set the stream id */
3354 snd_hda_codec_write(codec,
3355 nvhdmi_con_nids_7x[i],
3356 0,
3357 AC_VERB_SET_CHANNEL_STREAMID,
3358 (stream_tag << 4) | channel_id);
3359 /* set the stream format */
3360 snd_hda_codec_write(codec,
3361 nvhdmi_con_nids_7x[i],
3362 0,
3363 AC_VERB_SET_STREAM_FORMAT,
3364 format);
3365 /* turn on again (if needed) */
3366 /* enable and set the channel status audio/data flag */
3367 if (codec->spdif_status_reset &&
3368 (spdif->ctls & AC_DIG1_ENABLE)) {
3369 snd_hda_codec_write(codec,
3370 nvhdmi_con_nids_7x[i],
3371 0,
3372 AC_VERB_SET_DIGI_CONVERT_1,
3373 spdif->ctls & 0xff);
3374 snd_hda_codec_write(codec,
3375 nvhdmi_con_nids_7x[i],
3376 0,
3377 AC_VERB_SET_DIGI_CONVERT_2, dataDCC2);
3378 }
3379 }
3380
3381 nvhdmi_8ch_7x_set_info_frame_parameters(codec, chs);
3382
3383 mutex_unlock(&codec->spdif_mutex);
3384 return 0;
3385}
3386
3387static const struct hda_pcm_stream nvhdmi_pcm_playback_8ch_7x = {
3388 .substreams = 1,
3389 .channels_min = 2,
3390 .channels_max = 8,
3391 .nid = nvhdmi_master_con_nid_7x,
3392 .rates = SUPPORTED_RATES,
3393 .maxbps = SUPPORTED_MAXBPS,
3394 .formats = SUPPORTED_FORMATS,
3395 .ops = {
3396 .open = simple_playback_pcm_open,
3397 .close = nvhdmi_8ch_7x_pcm_close,
3398 .prepare = nvhdmi_8ch_7x_pcm_prepare
3399 },
3400};
3401
3402static int patch_nvhdmi_2ch(struct hda_codec *codec)
3403{
3404 struct hdmi_spec *spec;
3405 int err = patch_simple_hdmi(codec, nvhdmi_master_con_nid_7x,
3406 nvhdmi_master_pin_nid_7x);
3407 if (err < 0)
3408 return err;
3409
3410 codec->patch_ops.init = nvhdmi_7x_init_2ch;
3411 /* override the PCM rates, etc, as the codec doesn't give full list */
3412 spec = codec->spec;
3413 spec->pcm_playback.rates = SUPPORTED_RATES;
3414 spec->pcm_playback.maxbps = SUPPORTED_MAXBPS;
3415 spec->pcm_playback.formats = SUPPORTED_FORMATS;
3416 return 0;
3417}
3418
3419static int nvhdmi_7x_8ch_build_pcms(struct hda_codec *codec)
3420{
3421 struct hdmi_spec *spec = codec->spec;
3422 int err = simple_playback_build_pcms(codec);
3423 if (!err) {
3424 struct hda_pcm *info = get_pcm_rec(spec, 0);
3425 info->own_chmap = true;
3426 }
3427 return err;
3428}
3429
3430static int nvhdmi_7x_8ch_build_controls(struct hda_codec *codec)
3431{
3432 struct hdmi_spec *spec = codec->spec;
3433 struct hda_pcm *info;
3434 struct snd_pcm_chmap *chmap;
3435 int err;
3436
3437 err = simple_playback_build_controls(codec);
3438 if (err < 0)
3439 return err;
3440
3441 /* add channel maps */
3442 info = get_pcm_rec(spec, 0);
3443 err = snd_pcm_add_chmap_ctls(info->pcm,
3444 SNDRV_PCM_STREAM_PLAYBACK,
3445 snd_pcm_alt_chmaps, 8, 0, &chmap);
3446 if (err < 0)
3447 return err;
3448 switch (codec->preset->vendor_id) {
3449 case 0x10de0002:
3450 case 0x10de0003:
3451 case 0x10de0005:
3452 case 0x10de0006:
3453 chmap->channel_mask = (1U << 2) | (1U << 8);
3454 break;
3455 case 0x10de0007:
3456 chmap->channel_mask = (1U << 2) | (1U << 6) | (1U << 8);
3457 }
3458 return 0;
3459}
3460
3461static int patch_nvhdmi_8ch_7x(struct hda_codec *codec)
3462{
3463 struct hdmi_spec *spec;
3464 int err = patch_nvhdmi_2ch(codec);
3465 if (err < 0)
3466 return err;
3467 spec = codec->spec;
3468 spec->multiout.max_channels = 8;
3469 spec->pcm_playback = nvhdmi_pcm_playback_8ch_7x;
3470 codec->patch_ops.init = nvhdmi_7x_init_8ch;
3471 codec->patch_ops.build_pcms = nvhdmi_7x_8ch_build_pcms;
3472 codec->patch_ops.build_controls = nvhdmi_7x_8ch_build_controls;
3473
3474 /* Initialize the audio infoframe channel mask and checksum to something
3475 * valid */
3476 nvhdmi_8ch_7x_set_info_frame_parameters(codec, 8);
3477
3478 return 0;
3479}
3480
3481/*
3482 * NVIDIA codecs ignore ASP mapping for 2ch - confirmed on:
3483 * - 0x10de0015
3484 * - 0x10de0040
3485 */
3486static int nvhdmi_chmap_cea_alloc_validate_get_type(struct hdac_chmap *chmap,
3487 struct hdac_cea_channel_speaker_allocation *cap, int channels)
3488{
3489 if (cap->ca_index == 0x00 && channels == 2)
3490 return SNDRV_CTL_TLVT_CHMAP_FIXED;
3491
3492 /* If the speaker allocation matches the channel count, it is OK. */
3493 if (cap->channels != channels)
3494 return -1;
3495
3496 /* all channels are remappable freely */
3497 return SNDRV_CTL_TLVT_CHMAP_VAR;
3498}
3499
3500static int nvhdmi_chmap_validate(struct hdac_chmap *chmap,
3501 int ca, int chs, unsigned char *map)
3502{
3503 if (ca == 0x00 && (map[0] != SNDRV_CHMAP_FL || map[1] != SNDRV_CHMAP_FR))
3504 return -EINVAL;
3505
3506 return 0;
3507}
3508
3509/* map from pin NID to port; port is 0-based */
3510/* for Nvidia: assume widget NID starting from 4, with step 1 (4, 5, 6, ...) */
3511static int nvhdmi_pin2port(void *audio_ptr, int pin_nid)
3512{
3513 return pin_nid - 4;
3514}
3515
3516/* reverse-map from port to pin NID: see above */
3517static int nvhdmi_port2pin(struct hda_codec *codec, int port)
3518{
3519 return port + 4;
3520}
3521
3522static const struct drm_audio_component_audio_ops nvhdmi_audio_ops = {
3523 .pin2port = nvhdmi_pin2port,
3524 .pin_eld_notify = generic_acomp_pin_eld_notify,
3525 .master_bind = generic_acomp_master_bind,
3526 .master_unbind = generic_acomp_master_unbind,
3527};
3528
3529static int patch_nvhdmi(struct hda_codec *codec)
3530{
3531 struct hdmi_spec *spec;
3532 int err;
3533
3534 err = alloc_generic_hdmi(codec);
3535 if (err < 0)
3536 return err;
3537 codec->dp_mst = true;
3538
3539 spec = codec->spec;
3540 spec->dyn_pcm_assign = true;
3541
3542 err = hdmi_parse_codec(codec);
3543 if (err < 0) {
3544 generic_spec_free(codec);
3545 return err;
3546 }
3547
3548 generic_hdmi_init_per_pins(codec);
3549
3550 spec->dyn_pin_out = true;
3551
3552 spec->chmap.ops.chmap_cea_alloc_validate_get_type =
3553 nvhdmi_chmap_cea_alloc_validate_get_type;
3554 spec->chmap.ops.chmap_validate = nvhdmi_chmap_validate;
3555
3556 codec->link_down_at_suspend = 1;
3557
3558 generic_acomp_init(codec, &nvhdmi_audio_ops, nvhdmi_port2pin);
3559
3560 return 0;
3561}
3562
3563static int patch_nvhdmi_legacy(struct hda_codec *codec)
3564{
3565 struct hdmi_spec *spec;
3566 int err;
3567
3568 err = patch_generic_hdmi(codec);
3569 if (err)
3570 return err;
3571
3572 spec = codec->spec;
3573 spec->dyn_pin_out = true;
3574
3575 spec->chmap.ops.chmap_cea_alloc_validate_get_type =
3576 nvhdmi_chmap_cea_alloc_validate_get_type;
3577 spec->chmap.ops.chmap_validate = nvhdmi_chmap_validate;
3578
3579 codec->link_down_at_suspend = 1;
3580
3581 return 0;
3582}
3583
3584/*
3585 * The HDA codec on NVIDIA Tegra contains two scratch registers that are
3586 * accessed using vendor-defined verbs. These registers can be used for
3587 * interoperability between the HDA and HDMI drivers.
3588 */
3589
3590/* Audio Function Group node */
3591#define NVIDIA_AFG_NID 0x01
3592
3593/*
3594 * The SCRATCH0 register is used to notify the HDMI codec of changes in audio
3595 * format. On Tegra, bit 31 is used as a trigger that causes an interrupt to
3596 * be raised in the HDMI codec. The remainder of the bits is arbitrary. This
3597 * implementation stores the HDA format (see AC_FMT_*) in bits [15:0] and an
3598 * additional bit (at position 30) to signal the validity of the format.
3599 *
3600 * | 31 | 30 | 29 16 | 15 0 |
3601 * +---------+-------+--------+--------+
3602 * | TRIGGER | VALID | UNUSED | FORMAT |
3603 * +-----------------------------------|
3604 *
3605 * Note that for the trigger bit to take effect it needs to change value
3606 * (i.e. it needs to be toggled).
3607 */
3608#define NVIDIA_GET_SCRATCH0 0xfa6
3609#define NVIDIA_SET_SCRATCH0_BYTE0 0xfa7
3610#define NVIDIA_SET_SCRATCH0_BYTE1 0xfa8
3611#define NVIDIA_SET_SCRATCH0_BYTE2 0xfa9
3612#define NVIDIA_SET_SCRATCH0_BYTE3 0xfaa
3613#define NVIDIA_SCRATCH_TRIGGER (1 << 7)
3614#define NVIDIA_SCRATCH_VALID (1 << 6)
3615
3616#define NVIDIA_GET_SCRATCH1 0xfab
3617#define NVIDIA_SET_SCRATCH1_BYTE0 0xfac
3618#define NVIDIA_SET_SCRATCH1_BYTE1 0xfad
3619#define NVIDIA_SET_SCRATCH1_BYTE2 0xfae
3620#define NVIDIA_SET_SCRATCH1_BYTE3 0xfaf
3621
3622/*
3623 * The format parameter is the HDA audio format (see AC_FMT_*). If set to 0,
3624 * the format is invalidated so that the HDMI codec can be disabled.
3625 */
3626static void tegra_hdmi_set_format(struct hda_codec *codec, unsigned int format)
3627{
3628 unsigned int value;
3629
3630 /* bits [31:30] contain the trigger and valid bits */
3631 value = snd_hda_codec_read(codec, NVIDIA_AFG_NID, 0,
3632 NVIDIA_GET_SCRATCH0, 0);
3633 value = (value >> 24) & 0xff;
3634
3635 /* bits [15:0] are used to store the HDA format */
3636 snd_hda_codec_write(codec, NVIDIA_AFG_NID, 0,
3637 NVIDIA_SET_SCRATCH0_BYTE0,
3638 (format >> 0) & 0xff);
3639 snd_hda_codec_write(codec, NVIDIA_AFG_NID, 0,
3640 NVIDIA_SET_SCRATCH0_BYTE1,
3641 (format >> 8) & 0xff);
3642
3643 /* bits [16:24] are unused */
3644 snd_hda_codec_write(codec, NVIDIA_AFG_NID, 0,
3645 NVIDIA_SET_SCRATCH0_BYTE2, 0);
3646
3647 /*
3648 * Bit 30 signals that the data is valid and hence that HDMI audio can
3649 * be enabled.
3650 */
3651 if (format == 0)
3652 value &= ~NVIDIA_SCRATCH_VALID;
3653 else
3654 value |= NVIDIA_SCRATCH_VALID;
3655
3656 /*
3657 * Whenever the trigger bit is toggled, an interrupt is raised in the
3658 * HDMI codec. The HDMI driver will use that as trigger to update its
3659 * configuration.
3660 */
3661 value ^= NVIDIA_SCRATCH_TRIGGER;
3662
3663 snd_hda_codec_write(codec, NVIDIA_AFG_NID, 0,
3664 NVIDIA_SET_SCRATCH0_BYTE3, value);
3665}
3666
3667static int tegra_hdmi_pcm_prepare(struct hda_pcm_stream *hinfo,
3668 struct hda_codec *codec,
3669 unsigned int stream_tag,
3670 unsigned int format,
3671 struct snd_pcm_substream *substream)
3672{
3673 int err;
3674
3675 err = generic_hdmi_playback_pcm_prepare(hinfo, codec, stream_tag,
3676 format, substream);
3677 if (err < 0)
3678 return err;
3679
3680 /* notify the HDMI codec of the format change */
3681 tegra_hdmi_set_format(codec, format);
3682
3683 return 0;
3684}
3685
3686static int tegra_hdmi_pcm_cleanup(struct hda_pcm_stream *hinfo,
3687 struct hda_codec *codec,
3688 struct snd_pcm_substream *substream)
3689{
3690 /* invalidate the format in the HDMI codec */
3691 tegra_hdmi_set_format(codec, 0);
3692
3693 return generic_hdmi_playback_pcm_cleanup(hinfo, codec, substream);
3694}
3695
3696static struct hda_pcm *hda_find_pcm_by_type(struct hda_codec *codec, int type)
3697{
3698 struct hdmi_spec *spec = codec->spec;
3699 unsigned int i;
3700
3701 for (i = 0; i < spec->num_pins; i++) {
3702 struct hda_pcm *pcm = get_pcm_rec(spec, i);
3703
3704 if (pcm->pcm_type == type)
3705 return pcm;
3706 }
3707
3708 return NULL;
3709}
3710
3711static int tegra_hdmi_build_pcms(struct hda_codec *codec)
3712{
3713 struct hda_pcm_stream *stream;
3714 struct hda_pcm *pcm;
3715 int err;
3716
3717 err = generic_hdmi_build_pcms(codec);
3718 if (err < 0)
3719 return err;
3720
3721 pcm = hda_find_pcm_by_type(codec, HDA_PCM_TYPE_HDMI);
3722 if (!pcm)
3723 return -ENODEV;
3724
3725 /*
3726 * Override ->prepare() and ->cleanup() operations to notify the HDMI
3727 * codec about format changes.
3728 */
3729 stream = &pcm->stream[SNDRV_PCM_STREAM_PLAYBACK];
3730 stream->ops.prepare = tegra_hdmi_pcm_prepare;
3731 stream->ops.cleanup = tegra_hdmi_pcm_cleanup;
3732
3733 return 0;
3734}
3735
3736static int patch_tegra_hdmi(struct hda_codec *codec)
3737{
3738 struct hdmi_spec *spec;
3739 int err;
3740
3741 err = patch_generic_hdmi(codec);
3742 if (err)
3743 return err;
3744
3745 codec->patch_ops.build_pcms = tegra_hdmi_build_pcms;
3746 spec = codec->spec;
3747 spec->chmap.ops.chmap_cea_alloc_validate_get_type =
3748 nvhdmi_chmap_cea_alloc_validate_get_type;
3749 spec->chmap.ops.chmap_validate = nvhdmi_chmap_validate;
3750
3751 return 0;
3752}
3753
3754/*
3755 * ATI/AMD-specific implementations
3756 */
3757
3758#define is_amdhdmi_rev3_or_later(codec) \
3759 ((codec)->core.vendor_id == 0x1002aa01 && \
3760 ((codec)->core.revision_id & 0xff00) >= 0x0300)
3761#define has_amd_full_remap_support(codec) is_amdhdmi_rev3_or_later(codec)
3762
3763/* ATI/AMD specific HDA pin verbs, see the AMD HDA Verbs specification */
3764#define ATI_VERB_SET_CHANNEL_ALLOCATION 0x771
3765#define ATI_VERB_SET_DOWNMIX_INFO 0x772
3766#define ATI_VERB_SET_MULTICHANNEL_01 0x777
3767#define ATI_VERB_SET_MULTICHANNEL_23 0x778
3768#define ATI_VERB_SET_MULTICHANNEL_45 0x779
3769#define ATI_VERB_SET_MULTICHANNEL_67 0x77a
3770#define ATI_VERB_SET_HBR_CONTROL 0x77c
3771#define ATI_VERB_SET_MULTICHANNEL_1 0x785
3772#define ATI_VERB_SET_MULTICHANNEL_3 0x786
3773#define ATI_VERB_SET_MULTICHANNEL_5 0x787
3774#define ATI_VERB_SET_MULTICHANNEL_7 0x788
3775#define ATI_VERB_SET_MULTICHANNEL_MODE 0x789
3776#define ATI_VERB_GET_CHANNEL_ALLOCATION 0xf71
3777#define ATI_VERB_GET_DOWNMIX_INFO 0xf72
3778#define ATI_VERB_GET_MULTICHANNEL_01 0xf77
3779#define ATI_VERB_GET_MULTICHANNEL_23 0xf78
3780#define ATI_VERB_GET_MULTICHANNEL_45 0xf79
3781#define ATI_VERB_GET_MULTICHANNEL_67 0xf7a
3782#define ATI_VERB_GET_HBR_CONTROL 0xf7c
3783#define ATI_VERB_GET_MULTICHANNEL_1 0xf85
3784#define ATI_VERB_GET_MULTICHANNEL_3 0xf86
3785#define ATI_VERB_GET_MULTICHANNEL_5 0xf87
3786#define ATI_VERB_GET_MULTICHANNEL_7 0xf88
3787#define ATI_VERB_GET_MULTICHANNEL_MODE 0xf89
3788
3789/* AMD specific HDA cvt verbs */
3790#define ATI_VERB_SET_RAMP_RATE 0x770
3791#define ATI_VERB_GET_RAMP_RATE 0xf70
3792
3793#define ATI_OUT_ENABLE 0x1
3794
3795#define ATI_MULTICHANNEL_MODE_PAIRED 0
3796#define ATI_MULTICHANNEL_MODE_SINGLE 1
3797
3798#define ATI_HBR_CAPABLE 0x01
3799#define ATI_HBR_ENABLE 0x10
3800
3801static int atihdmi_pin_get_eld(struct hda_codec *codec, hda_nid_t nid,
3802 int dev_id, unsigned char *buf, int *eld_size)
3803{
3804 WARN_ON(dev_id != 0);
3805 /* call hda_eld.c ATI/AMD-specific function */
3806 return snd_hdmi_get_eld_ati(codec, nid, buf, eld_size,
3807 is_amdhdmi_rev3_or_later(codec));
3808}
3809
3810static void atihdmi_pin_setup_infoframe(struct hda_codec *codec,
3811 hda_nid_t pin_nid, int dev_id, int ca,
3812 int active_channels, int conn_type)
3813{
3814 WARN_ON(dev_id != 0);
3815 snd_hda_codec_write(codec, pin_nid, 0, ATI_VERB_SET_CHANNEL_ALLOCATION, ca);
3816}
3817
3818static int atihdmi_paired_swap_fc_lfe(int pos)
3819{
3820 /*
3821 * ATI/AMD have automatic FC/LFE swap built-in
3822 * when in pairwise mapping mode.
3823 */
3824
3825 switch (pos) {
3826 /* see channel_allocations[].speakers[] */
3827 case 2: return 3;
3828 case 3: return 2;
3829 default: break;
3830 }
3831
3832 return pos;
3833}
3834
3835static int atihdmi_paired_chmap_validate(struct hdac_chmap *chmap,
3836 int ca, int chs, unsigned char *map)
3837{
3838 struct hdac_cea_channel_speaker_allocation *cap;
3839 int i, j;
3840
3841 /* check that only channel pairs need to be remapped on old pre-rev3 ATI/AMD */
3842
3843 cap = snd_hdac_get_ch_alloc_from_ca(ca);
3844 for (i = 0; i < chs; ++i) {
3845 int mask = snd_hdac_chmap_to_spk_mask(map[i]);
3846 bool ok = false;
3847 bool companion_ok = false;
3848
3849 if (!mask)
3850 continue;
3851
3852 for (j = 0 + i % 2; j < 8; j += 2) {
3853 int chan_idx = 7 - atihdmi_paired_swap_fc_lfe(j);
3854 if (cap->speakers[chan_idx] == mask) {
3855 /* channel is in a supported position */
3856 ok = true;
3857
3858 if (i % 2 == 0 && i + 1 < chs) {
3859 /* even channel, check the odd companion */
3860 int comp_chan_idx = 7 - atihdmi_paired_swap_fc_lfe(j + 1);
3861 int comp_mask_req = snd_hdac_chmap_to_spk_mask(map[i+1]);
3862 int comp_mask_act = cap->speakers[comp_chan_idx];
3863
3864 if (comp_mask_req == comp_mask_act)
3865 companion_ok = true;
3866 else
3867 return -EINVAL;
3868 }
3869 break;
3870 }
3871 }
3872
3873 if (!ok)
3874 return -EINVAL;
3875
3876 if (companion_ok)
3877 i++; /* companion channel already checked */
3878 }
3879
3880 return 0;
3881}
3882
3883static int atihdmi_pin_set_slot_channel(struct hdac_device *hdac,
3884 hda_nid_t pin_nid, int hdmi_slot, int stream_channel)
3885{
3886 struct hda_codec *codec = hdac_to_hda_codec(hdac);
3887 int verb;
3888 int ati_channel_setup = 0;
3889
3890 if (hdmi_slot > 7)
3891 return -EINVAL;
3892
3893 if (!has_amd_full_remap_support(codec)) {
3894 hdmi_slot = atihdmi_paired_swap_fc_lfe(hdmi_slot);
3895
3896 /* In case this is an odd slot but without stream channel, do not
3897 * disable the slot since the corresponding even slot could have a
3898 * channel. In case neither have a channel, the slot pair will be
3899 * disabled when this function is called for the even slot. */
3900 if (hdmi_slot % 2 != 0 && stream_channel == 0xf)
3901 return 0;
3902
3903 hdmi_slot -= hdmi_slot % 2;
3904
3905 if (stream_channel != 0xf)
3906 stream_channel -= stream_channel % 2;
3907 }
3908
3909 verb = ATI_VERB_SET_MULTICHANNEL_01 + hdmi_slot/2 + (hdmi_slot % 2) * 0x00e;
3910
3911 /* ati_channel_setup format: [7..4] = stream_channel_id, [1] = mute, [0] = enable */
3912
3913 if (stream_channel != 0xf)
3914 ati_channel_setup = (stream_channel << 4) | ATI_OUT_ENABLE;
3915
3916 return snd_hda_codec_write(codec, pin_nid, 0, verb, ati_channel_setup);
3917}
3918
3919static int atihdmi_pin_get_slot_channel(struct hdac_device *hdac,
3920 hda_nid_t pin_nid, int asp_slot)
3921{
3922 struct hda_codec *codec = hdac_to_hda_codec(hdac);
3923 bool was_odd = false;
3924 int ati_asp_slot = asp_slot;
3925 int verb;
3926 int ati_channel_setup;
3927
3928 if (asp_slot > 7)
3929 return -EINVAL;
3930
3931 if (!has_amd_full_remap_support(codec)) {
3932 ati_asp_slot = atihdmi_paired_swap_fc_lfe(asp_slot);
3933 if (ati_asp_slot % 2 != 0) {
3934 ati_asp_slot -= 1;
3935 was_odd = true;
3936 }
3937 }
3938
3939 verb = ATI_VERB_GET_MULTICHANNEL_01 + ati_asp_slot/2 + (ati_asp_slot % 2) * 0x00e;
3940
3941 ati_channel_setup = snd_hda_codec_read(codec, pin_nid, 0, verb, 0);
3942
3943 if (!(ati_channel_setup & ATI_OUT_ENABLE))
3944 return 0xf;
3945
3946 return ((ati_channel_setup & 0xf0) >> 4) + !!was_odd;
3947}
3948
3949static int atihdmi_paired_chmap_cea_alloc_validate_get_type(
3950 struct hdac_chmap *chmap,
3951 struct hdac_cea_channel_speaker_allocation *cap,
3952 int channels)
3953{
3954 int c;
3955
3956 /*
3957 * Pre-rev3 ATI/AMD codecs operate in a paired channel mode, so
3958 * we need to take that into account (a single channel may take 2
3959 * channel slots if we need to carry a silent channel next to it).
3960 * On Rev3+ AMD codecs this function is not used.
3961 */
3962 int chanpairs = 0;
3963
3964 /* We only produce even-numbered channel count TLVs */
3965 if ((channels % 2) != 0)
3966 return -1;
3967
3968 for (c = 0; c < 7; c += 2) {
3969 if (cap->speakers[c] || cap->speakers[c+1])
3970 chanpairs++;
3971 }
3972
3973 if (chanpairs * 2 != channels)
3974 return -1;
3975
3976 return SNDRV_CTL_TLVT_CHMAP_PAIRED;
3977}
3978
3979static void atihdmi_paired_cea_alloc_to_tlv_chmap(struct hdac_chmap *hchmap,
3980 struct hdac_cea_channel_speaker_allocation *cap,
3981 unsigned int *chmap, int channels)
3982{
3983 /* produce paired maps for pre-rev3 ATI/AMD codecs */
3984 int count = 0;
3985 int c;
3986
3987 for (c = 7; c >= 0; c--) {
3988 int chan = 7 - atihdmi_paired_swap_fc_lfe(7 - c);
3989 int spk = cap->speakers[chan];
3990 if (!spk) {
3991 /* add N/A channel if the companion channel is occupied */
3992 if (cap->speakers[chan + (chan % 2 ? -1 : 1)])
3993 chmap[count++] = SNDRV_CHMAP_NA;
3994
3995 continue;
3996 }
3997
3998 chmap[count++] = snd_hdac_spk_to_chmap(spk);
3999 }
4000
4001 WARN_ON(count != channels);
4002}
4003
4004static int atihdmi_pin_hbr_setup(struct hda_codec *codec, hda_nid_t pin_nid,
4005 int dev_id, bool hbr)
4006{
4007 int hbr_ctl, hbr_ctl_new;
4008
4009 WARN_ON(dev_id != 0);
4010
4011 hbr_ctl = snd_hda_codec_read(codec, pin_nid, 0, ATI_VERB_GET_HBR_CONTROL, 0);
4012 if (hbr_ctl >= 0 && (hbr_ctl & ATI_HBR_CAPABLE)) {
4013 if (hbr)
4014 hbr_ctl_new = hbr_ctl | ATI_HBR_ENABLE;
4015 else
4016 hbr_ctl_new = hbr_ctl & ~ATI_HBR_ENABLE;
4017
4018 codec_dbg(codec,
4019 "atihdmi_pin_hbr_setup: NID=0x%x, %shbr-ctl=0x%x\n",
4020 pin_nid,
4021 hbr_ctl == hbr_ctl_new ? "" : "new-",
4022 hbr_ctl_new);
4023
4024 if (hbr_ctl != hbr_ctl_new)
4025 snd_hda_codec_write(codec, pin_nid, 0,
4026 ATI_VERB_SET_HBR_CONTROL,
4027 hbr_ctl_new);
4028
4029 } else if (hbr)
4030 return -EINVAL;
4031
4032 return 0;
4033}
4034
4035static int atihdmi_setup_stream(struct hda_codec *codec, hda_nid_t cvt_nid,
4036 hda_nid_t pin_nid, int dev_id,
4037 u32 stream_tag, int format)
4038{
4039 if (is_amdhdmi_rev3_or_later(codec)) {
4040 int ramp_rate = 180; /* default as per AMD spec */
4041 /* disable ramp-up/down for non-pcm as per AMD spec */
4042 if (format & AC_FMT_TYPE_NON_PCM)
4043 ramp_rate = 0;
4044
4045 snd_hda_codec_write(codec, cvt_nid, 0, ATI_VERB_SET_RAMP_RATE, ramp_rate);
4046 }
4047
4048 return hdmi_setup_stream(codec, cvt_nid, pin_nid, dev_id,
4049 stream_tag, format);
4050}
4051
4052
4053static int atihdmi_init(struct hda_codec *codec)
4054{
4055 struct hdmi_spec *spec = codec->spec;
4056 int pin_idx, err;
4057
4058 err = generic_hdmi_init(codec);
4059
4060 if (err)
4061 return err;
4062
4063 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
4064 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
4065
4066 /* make sure downmix information in infoframe is zero */
4067 snd_hda_codec_write(codec, per_pin->pin_nid, 0, ATI_VERB_SET_DOWNMIX_INFO, 0);
4068
4069 /* enable channel-wise remap mode if supported */
4070 if (has_amd_full_remap_support(codec))
4071 snd_hda_codec_write(codec, per_pin->pin_nid, 0,
4072 ATI_VERB_SET_MULTICHANNEL_MODE,
4073 ATI_MULTICHANNEL_MODE_SINGLE);
4074 }
4075 codec->auto_runtime_pm = 1;
4076
4077 return 0;
4078}
4079
4080/* map from pin NID to port; port is 0-based */
4081/* for AMD: assume widget NID starting from 3, with step 2 (3, 5, 7, ...) */
4082static int atihdmi_pin2port(void *audio_ptr, int pin_nid)
4083{
4084 return pin_nid / 2 - 1;
4085}
4086
4087/* reverse-map from port to pin NID: see above */
4088static int atihdmi_port2pin(struct hda_codec *codec, int port)
4089{
4090 return port * 2 + 3;
4091}
4092
4093static const struct drm_audio_component_audio_ops atihdmi_audio_ops = {
4094 .pin2port = atihdmi_pin2port,
4095 .pin_eld_notify = generic_acomp_pin_eld_notify,
4096 .master_bind = generic_acomp_master_bind,
4097 .master_unbind = generic_acomp_master_unbind,
4098};
4099
4100static int patch_atihdmi(struct hda_codec *codec)
4101{
4102 struct hdmi_spec *spec;
4103 struct hdmi_spec_per_cvt *per_cvt;
4104 int err, cvt_idx;
4105
4106 err = patch_generic_hdmi(codec);
4107
4108 if (err)
4109 return err;
4110
4111 codec->patch_ops.init = atihdmi_init;
4112
4113 spec = codec->spec;
4114
4115 spec->ops.pin_get_eld = atihdmi_pin_get_eld;
4116 spec->ops.pin_setup_infoframe = atihdmi_pin_setup_infoframe;
4117 spec->ops.pin_hbr_setup = atihdmi_pin_hbr_setup;
4118 spec->ops.setup_stream = atihdmi_setup_stream;
4119
4120 spec->chmap.ops.pin_get_slot_channel = atihdmi_pin_get_slot_channel;
4121 spec->chmap.ops.pin_set_slot_channel = atihdmi_pin_set_slot_channel;
4122
4123 if (!has_amd_full_remap_support(codec)) {
4124 /* override to ATI/AMD-specific versions with pairwise mapping */
4125 spec->chmap.ops.chmap_cea_alloc_validate_get_type =
4126 atihdmi_paired_chmap_cea_alloc_validate_get_type;
4127 spec->chmap.ops.cea_alloc_to_tlv_chmap =
4128 atihdmi_paired_cea_alloc_to_tlv_chmap;
4129 spec->chmap.ops.chmap_validate = atihdmi_paired_chmap_validate;
4130 }
4131
4132 /* ATI/AMD converters do not advertise all of their capabilities */
4133 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) {
4134 per_cvt = get_cvt(spec, cvt_idx);
4135 per_cvt->channels_max = max(per_cvt->channels_max, 8u);
4136 per_cvt->rates |= SUPPORTED_RATES;
4137 per_cvt->formats |= SUPPORTED_FORMATS;
4138 per_cvt->maxbps = max(per_cvt->maxbps, 24u);
4139 }
4140
4141 spec->chmap.channels_max = max(spec->chmap.channels_max, 8u);
4142
4143 /* AMD GPUs have neither EPSS nor CLKSTOP bits, hence preventing
4144 * the link-down as is. Tell the core to allow it.
4145 */
4146 codec->link_down_at_suspend = 1;
4147
4148 generic_acomp_init(codec, &atihdmi_audio_ops, atihdmi_port2pin);
4149
4150 return 0;
4151}
4152
4153/* VIA HDMI Implementation */
4154#define VIAHDMI_CVT_NID 0x02 /* audio converter1 */
4155#define VIAHDMI_PIN_NID 0x03 /* HDMI output pin1 */
4156
4157static int patch_via_hdmi(struct hda_codec *codec)
4158{
4159 return patch_simple_hdmi(codec, VIAHDMI_CVT_NID, VIAHDMI_PIN_NID);
4160}
4161
4162/*
4163 * patch entries
4164 */
4165static const struct hda_device_id snd_hda_id_hdmi[] = {
4166HDA_CODEC_ENTRY(0x1002793c, "RS600 HDMI", patch_atihdmi),
4167HDA_CODEC_ENTRY(0x10027919, "RS600 HDMI", patch_atihdmi),
4168HDA_CODEC_ENTRY(0x1002791a, "RS690/780 HDMI", patch_atihdmi),
4169HDA_CODEC_ENTRY(0x1002aa01, "R6xx HDMI", patch_atihdmi),
4170HDA_CODEC_ENTRY(0x10951390, "SiI1390 HDMI", patch_generic_hdmi),
4171HDA_CODEC_ENTRY(0x10951392, "SiI1392 HDMI", patch_generic_hdmi),
4172HDA_CODEC_ENTRY(0x17e80047, "Chrontel HDMI", patch_generic_hdmi),
4173HDA_CODEC_ENTRY(0x10de0001, "MCP73 HDMI", patch_nvhdmi_2ch),
4174HDA_CODEC_ENTRY(0x10de0002, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x),
4175HDA_CODEC_ENTRY(0x10de0003, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x),
4176HDA_CODEC_ENTRY(0x10de0004, "GPU 04 HDMI", patch_nvhdmi_8ch_7x),
4177HDA_CODEC_ENTRY(0x10de0005, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x),
4178HDA_CODEC_ENTRY(0x10de0006, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x),
4179HDA_CODEC_ENTRY(0x10de0007, "MCP79/7A HDMI", patch_nvhdmi_8ch_7x),
4180HDA_CODEC_ENTRY(0x10de0008, "GPU 08 HDMI/DP", patch_nvhdmi_legacy),
4181HDA_CODEC_ENTRY(0x10de0009, "GPU 09 HDMI/DP", patch_nvhdmi_legacy),
4182HDA_CODEC_ENTRY(0x10de000a, "GPU 0a HDMI/DP", patch_nvhdmi_legacy),
4183HDA_CODEC_ENTRY(0x10de000b, "GPU 0b HDMI/DP", patch_nvhdmi_legacy),
4184HDA_CODEC_ENTRY(0x10de000c, "MCP89 HDMI", patch_nvhdmi_legacy),
4185HDA_CODEC_ENTRY(0x10de000d, "GPU 0d HDMI/DP", patch_nvhdmi_legacy),
4186HDA_CODEC_ENTRY(0x10de0010, "GPU 10 HDMI/DP", patch_nvhdmi_legacy),
4187HDA_CODEC_ENTRY(0x10de0011, "GPU 11 HDMI/DP", patch_nvhdmi_legacy),
4188HDA_CODEC_ENTRY(0x10de0012, "GPU 12 HDMI/DP", patch_nvhdmi_legacy),
4189HDA_CODEC_ENTRY(0x10de0013, "GPU 13 HDMI/DP", patch_nvhdmi_legacy),
4190HDA_CODEC_ENTRY(0x10de0014, "GPU 14 HDMI/DP", patch_nvhdmi_legacy),
4191HDA_CODEC_ENTRY(0x10de0015, "GPU 15 HDMI/DP", patch_nvhdmi_legacy),
4192HDA_CODEC_ENTRY(0x10de0016, "GPU 16 HDMI/DP", patch_nvhdmi_legacy),
4193/* 17 is known to be absent */
4194HDA_CODEC_ENTRY(0x10de0018, "GPU 18 HDMI/DP", patch_nvhdmi_legacy),
4195HDA_CODEC_ENTRY(0x10de0019, "GPU 19 HDMI/DP", patch_nvhdmi_legacy),
4196HDA_CODEC_ENTRY(0x10de001a, "GPU 1a HDMI/DP", patch_nvhdmi_legacy),
4197HDA_CODEC_ENTRY(0x10de001b, "GPU 1b HDMI/DP", patch_nvhdmi_legacy),
4198HDA_CODEC_ENTRY(0x10de001c, "GPU 1c HDMI/DP", patch_nvhdmi_legacy),
4199HDA_CODEC_ENTRY(0x10de0020, "Tegra30 HDMI", patch_tegra_hdmi),
4200HDA_CODEC_ENTRY(0x10de0022, "Tegra114 HDMI", patch_tegra_hdmi),
4201HDA_CODEC_ENTRY(0x10de0028, "Tegra124 HDMI", patch_tegra_hdmi),
4202HDA_CODEC_ENTRY(0x10de0029, "Tegra210 HDMI/DP", patch_tegra_hdmi),
4203HDA_CODEC_ENTRY(0x10de002d, "Tegra186 HDMI/DP0", patch_tegra_hdmi),
4204HDA_CODEC_ENTRY(0x10de002e, "Tegra186 HDMI/DP1", patch_tegra_hdmi),
4205HDA_CODEC_ENTRY(0x10de002f, "Tegra194 HDMI/DP2", patch_tegra_hdmi),
4206HDA_CODEC_ENTRY(0x10de0030, "Tegra194 HDMI/DP3", patch_tegra_hdmi),
4207HDA_CODEC_ENTRY(0x10de0040, "GPU 40 HDMI/DP", patch_nvhdmi),
4208HDA_CODEC_ENTRY(0x10de0041, "GPU 41 HDMI/DP", patch_nvhdmi),
4209HDA_CODEC_ENTRY(0x10de0042, "GPU 42 HDMI/DP", patch_nvhdmi),
4210HDA_CODEC_ENTRY(0x10de0043, "GPU 43 HDMI/DP", patch_nvhdmi),
4211HDA_CODEC_ENTRY(0x10de0044, "GPU 44 HDMI/DP", patch_nvhdmi),
4212HDA_CODEC_ENTRY(0x10de0045, "GPU 45 HDMI/DP", patch_nvhdmi),
4213HDA_CODEC_ENTRY(0x10de0050, "GPU 50 HDMI/DP", patch_nvhdmi),
4214HDA_CODEC_ENTRY(0x10de0051, "GPU 51 HDMI/DP", patch_nvhdmi),
4215HDA_CODEC_ENTRY(0x10de0052, "GPU 52 HDMI/DP", patch_nvhdmi),
4216HDA_CODEC_ENTRY(0x10de0060, "GPU 60 HDMI/DP", patch_nvhdmi),
4217HDA_CODEC_ENTRY(0x10de0061, "GPU 61 HDMI/DP", patch_nvhdmi),
4218HDA_CODEC_ENTRY(0x10de0062, "GPU 62 HDMI/DP", patch_nvhdmi),
4219HDA_CODEC_ENTRY(0x10de0067, "MCP67 HDMI", patch_nvhdmi_2ch),
4220HDA_CODEC_ENTRY(0x10de0070, "GPU 70 HDMI/DP", patch_nvhdmi),
4221HDA_CODEC_ENTRY(0x10de0071, "GPU 71 HDMI/DP", patch_nvhdmi),
4222HDA_CODEC_ENTRY(0x10de0072, "GPU 72 HDMI/DP", patch_nvhdmi),
4223HDA_CODEC_ENTRY(0x10de0073, "GPU 73 HDMI/DP", patch_nvhdmi),
4224HDA_CODEC_ENTRY(0x10de0074, "GPU 74 HDMI/DP", patch_nvhdmi),
4225HDA_CODEC_ENTRY(0x10de0076, "GPU 76 HDMI/DP", patch_nvhdmi),
4226HDA_CODEC_ENTRY(0x10de007b, "GPU 7b HDMI/DP", patch_nvhdmi),
4227HDA_CODEC_ENTRY(0x10de007c, "GPU 7c HDMI/DP", patch_nvhdmi),
4228HDA_CODEC_ENTRY(0x10de007d, "GPU 7d HDMI/DP", patch_nvhdmi),
4229HDA_CODEC_ENTRY(0x10de007e, "GPU 7e HDMI/DP", patch_nvhdmi),
4230HDA_CODEC_ENTRY(0x10de0080, "GPU 80 HDMI/DP", patch_nvhdmi),
4231HDA_CODEC_ENTRY(0x10de0081, "GPU 81 HDMI/DP", patch_nvhdmi),
4232HDA_CODEC_ENTRY(0x10de0082, "GPU 82 HDMI/DP", patch_nvhdmi),
4233HDA_CODEC_ENTRY(0x10de0083, "GPU 83 HDMI/DP", patch_nvhdmi),
4234HDA_CODEC_ENTRY(0x10de0084, "GPU 84 HDMI/DP", patch_nvhdmi),
4235HDA_CODEC_ENTRY(0x10de0090, "GPU 90 HDMI/DP", patch_nvhdmi),
4236HDA_CODEC_ENTRY(0x10de0091, "GPU 91 HDMI/DP", patch_nvhdmi),
4237HDA_CODEC_ENTRY(0x10de0092, "GPU 92 HDMI/DP", patch_nvhdmi),
4238HDA_CODEC_ENTRY(0x10de0093, "GPU 93 HDMI/DP", patch_nvhdmi),
4239HDA_CODEC_ENTRY(0x10de0094, "GPU 94 HDMI/DP", patch_nvhdmi),
4240HDA_CODEC_ENTRY(0x10de0095, "GPU 95 HDMI/DP", patch_nvhdmi),
4241HDA_CODEC_ENTRY(0x10de0097, "GPU 97 HDMI/DP", patch_nvhdmi),
4242HDA_CODEC_ENTRY(0x10de0098, "GPU 98 HDMI/DP", patch_nvhdmi),
4243HDA_CODEC_ENTRY(0x10de0099, "GPU 99 HDMI/DP", patch_nvhdmi),
4244HDA_CODEC_ENTRY(0x10de009a, "GPU 9a HDMI/DP", patch_nvhdmi),
4245HDA_CODEC_ENTRY(0x10de009d, "GPU 9d HDMI/DP", patch_nvhdmi),
4246HDA_CODEC_ENTRY(0x10de009e, "GPU 9e HDMI/DP", patch_nvhdmi),
4247HDA_CODEC_ENTRY(0x10de009f, "GPU 9f HDMI/DP", patch_nvhdmi),
4248HDA_CODEC_ENTRY(0x10de00a0, "GPU a0 HDMI/DP", patch_nvhdmi),
4249HDA_CODEC_ENTRY(0x10de8001, "MCP73 HDMI", patch_nvhdmi_2ch),
4250HDA_CODEC_ENTRY(0x10de8067, "MCP67/68 HDMI", patch_nvhdmi_2ch),
4251HDA_CODEC_ENTRY(0x11069f80, "VX900 HDMI/DP", patch_via_hdmi),
4252HDA_CODEC_ENTRY(0x11069f81, "VX900 HDMI/DP", patch_via_hdmi),
4253HDA_CODEC_ENTRY(0x11069f84, "VX11 HDMI/DP", patch_generic_hdmi),
4254HDA_CODEC_ENTRY(0x11069f85, "VX11 HDMI/DP", patch_generic_hdmi),
4255HDA_CODEC_ENTRY(0x80860054, "IbexPeak HDMI", patch_i915_cpt_hdmi),
4256HDA_CODEC_ENTRY(0x80862800, "Geminilake HDMI", patch_i915_glk_hdmi),
4257HDA_CODEC_ENTRY(0x80862801, "Bearlake HDMI", patch_generic_hdmi),
4258HDA_CODEC_ENTRY(0x80862802, "Cantiga HDMI", patch_generic_hdmi),
4259HDA_CODEC_ENTRY(0x80862803, "Eaglelake HDMI", patch_generic_hdmi),
4260HDA_CODEC_ENTRY(0x80862804, "IbexPeak HDMI", patch_i915_cpt_hdmi),
4261HDA_CODEC_ENTRY(0x80862805, "CougarPoint HDMI", patch_i915_cpt_hdmi),
4262HDA_CODEC_ENTRY(0x80862806, "PantherPoint HDMI", patch_i915_cpt_hdmi),
4263HDA_CODEC_ENTRY(0x80862807, "Haswell HDMI", patch_i915_hsw_hdmi),
4264HDA_CODEC_ENTRY(0x80862808, "Broadwell HDMI", patch_i915_hsw_hdmi),
4265HDA_CODEC_ENTRY(0x80862809, "Skylake HDMI", patch_i915_hsw_hdmi),
4266HDA_CODEC_ENTRY(0x8086280a, "Broxton HDMI", patch_i915_hsw_hdmi),
4267HDA_CODEC_ENTRY(0x8086280b, "Kabylake HDMI", patch_i915_hsw_hdmi),
4268HDA_CODEC_ENTRY(0x8086280c, "Cannonlake HDMI", patch_i915_glk_hdmi),
4269HDA_CODEC_ENTRY(0x8086280d, "Geminilake HDMI", patch_i915_glk_hdmi),
4270HDA_CODEC_ENTRY(0x8086280f, "Icelake HDMI", patch_i915_icl_hdmi),
4271HDA_CODEC_ENTRY(0x80862812, "Tigerlake HDMI", patch_i915_tgl_hdmi),
4272HDA_CODEC_ENTRY(0x80862816, "Rocketlake HDMI", patch_i915_tgl_hdmi),
4273HDA_CODEC_ENTRY(0x8086281a, "Jasperlake HDMI", patch_i915_icl_hdmi),
4274HDA_CODEC_ENTRY(0x8086281b, "Elkhartlake HDMI", patch_i915_icl_hdmi),
4275HDA_CODEC_ENTRY(0x80862880, "CedarTrail HDMI", patch_generic_hdmi),
4276HDA_CODEC_ENTRY(0x80862882, "Valleyview2 HDMI", patch_i915_byt_hdmi),
4277HDA_CODEC_ENTRY(0x80862883, "Braswell HDMI", patch_i915_byt_hdmi),
4278HDA_CODEC_ENTRY(0x808629fb, "Crestline HDMI", patch_generic_hdmi),
4279/* special ID for generic HDMI */
4280HDA_CODEC_ENTRY(HDA_CODEC_ID_GENERIC_HDMI, "Generic HDMI", patch_generic_hdmi),
4281{} /* terminator */
4282};
4283MODULE_DEVICE_TABLE(hdaudio, snd_hda_id_hdmi);
4284
4285MODULE_LICENSE("GPL");
4286MODULE_DESCRIPTION("HDMI HD-audio codec");
4287MODULE_ALIAS("snd-hda-codec-intelhdmi");
4288MODULE_ALIAS("snd-hda-codec-nvhdmi");
4289MODULE_ALIAS("snd-hda-codec-atihdmi");
4290
4291static struct hda_codec_driver hdmi_driver = {
4292 .id = snd_hda_id_hdmi,
4293};
4294
4295module_hda_codec_driver(hdmi_driver);
1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 *
4 * patch_hdmi.c - routines for HDMI/DisplayPort codecs
5 *
6 * Copyright(c) 2008-2010 Intel Corporation. All rights reserved.
7 * Copyright (c) 2006 ATI Technologies Inc.
8 * Copyright (c) 2008 NVIDIA Corp. All rights reserved.
9 * Copyright (c) 2008 Wei Ni <wni@nvidia.com>
10 * Copyright (c) 2013 Anssi Hannula <anssi.hannula@iki.fi>
11 *
12 * Authors:
13 * Wu Fengguang <wfg@linux.intel.com>
14 *
15 * Maintained by:
16 * Wu Fengguang <wfg@linux.intel.com>
17 */
18
19#include <linux/init.h>
20#include <linux/delay.h>
21#include <linux/pci.h>
22#include <linux/slab.h>
23#include <linux/module.h>
24#include <linux/pm_runtime.h>
25#include <sound/core.h>
26#include <sound/jack.h>
27#include <sound/asoundef.h>
28#include <sound/tlv.h>
29#include <sound/hdaudio.h>
30#include <sound/hda_i915.h>
31#include <sound/hda_chmap.h>
32#include <sound/hda_codec.h>
33#include "hda_local.h"
34#include "hda_jack.h"
35#include "hda_controller.h"
36
37static bool static_hdmi_pcm;
38module_param(static_hdmi_pcm, bool, 0644);
39MODULE_PARM_DESC(static_hdmi_pcm, "Don't restrict PCM parameters per ELD info");
40
41static bool enable_acomp = true;
42module_param(enable_acomp, bool, 0444);
43MODULE_PARM_DESC(enable_acomp, "Enable audio component binding (default=yes)");
44
45static bool enable_silent_stream =
46IS_ENABLED(CONFIG_SND_HDA_INTEL_HDMI_SILENT_STREAM);
47module_param(enable_silent_stream, bool, 0644);
48MODULE_PARM_DESC(enable_silent_stream, "Enable Silent Stream for HDMI devices");
49
50static bool enable_all_pins;
51module_param(enable_all_pins, bool, 0444);
52MODULE_PARM_DESC(enable_all_pins, "Forcibly enable all pins");
53
54struct hdmi_spec_per_cvt {
55 hda_nid_t cvt_nid;
56 bool assigned; /* the stream has been assigned */
57 bool silent_stream; /* silent stream activated */
58 unsigned int channels_min;
59 unsigned int channels_max;
60 u32 rates;
61 u64 formats;
62 unsigned int maxbps;
63};
64
65/* max. connections to a widget */
66#define HDA_MAX_CONNECTIONS 32
67
68struct hdmi_spec_per_pin {
69 hda_nid_t pin_nid;
70 int dev_id;
71 /* pin idx, different device entries on the same pin use the same idx */
72 int pin_nid_idx;
73 int num_mux_nids;
74 hda_nid_t mux_nids[HDA_MAX_CONNECTIONS];
75 int mux_idx;
76 hda_nid_t cvt_nid;
77
78 struct hda_codec *codec;
79 struct hdmi_eld sink_eld;
80 struct mutex lock;
81 struct delayed_work work;
82 struct hdmi_pcm *pcm; /* pointer to spec->pcm_rec[n] dynamically*/
83 int pcm_idx; /* which pcm is attached. -1 means no pcm is attached */
84 int repoll_count;
85 bool setup; /* the stream has been set up by prepare callback */
86 bool silent_stream;
87 int channels; /* current number of channels */
88 bool non_pcm;
89 bool chmap_set; /* channel-map override by ALSA API? */
90 unsigned char chmap[8]; /* ALSA API channel-map */
91#ifdef CONFIG_SND_PROC_FS
92 struct snd_info_entry *proc_entry;
93#endif
94};
95
96/* operations used by generic code that can be overridden by patches */
97struct hdmi_ops {
98 int (*pin_get_eld)(struct hda_codec *codec, hda_nid_t pin_nid,
99 int dev_id, unsigned char *buf, int *eld_size);
100
101 void (*pin_setup_infoframe)(struct hda_codec *codec, hda_nid_t pin_nid,
102 int dev_id,
103 int ca, int active_channels, int conn_type);
104
105 /* enable/disable HBR (HD passthrough) */
106 int (*pin_hbr_setup)(struct hda_codec *codec, hda_nid_t pin_nid,
107 int dev_id, bool hbr);
108
109 int (*setup_stream)(struct hda_codec *codec, hda_nid_t cvt_nid,
110 hda_nid_t pin_nid, int dev_id, u32 stream_tag,
111 int format);
112
113 void (*pin_cvt_fixup)(struct hda_codec *codec,
114 struct hdmi_spec_per_pin *per_pin,
115 hda_nid_t cvt_nid);
116};
117
118struct hdmi_pcm {
119 struct hda_pcm *pcm;
120 struct snd_jack *jack;
121 struct snd_kcontrol *eld_ctl;
122};
123
124enum {
125 SILENT_STREAM_OFF = 0,
126 SILENT_STREAM_KAE, /* use standard HDA Keep-Alive */
127 SILENT_STREAM_I915, /* Intel i915 extension */
128};
129
130struct hdmi_spec {
131 struct hda_codec *codec;
132 int num_cvts;
133 struct snd_array cvts; /* struct hdmi_spec_per_cvt */
134 hda_nid_t cvt_nids[4]; /* only for haswell fix */
135
136 /*
137 * num_pins is the number of virtual pins
138 * for example, there are 3 pins, and each pin
139 * has 4 device entries, then the num_pins is 12
140 */
141 int num_pins;
142 /*
143 * num_nids is the number of real pins
144 * In the above example, num_nids is 3
145 */
146 int num_nids;
147 /*
148 * dev_num is the number of device entries
149 * on each pin.
150 * In the above example, dev_num is 4
151 */
152 int dev_num;
153 struct snd_array pins; /* struct hdmi_spec_per_pin */
154 struct hdmi_pcm pcm_rec[8];
155 struct mutex pcm_lock;
156 struct mutex bind_lock; /* for audio component binding */
157 /* pcm_bitmap means which pcms have been assigned to pins*/
158 unsigned long pcm_bitmap;
159 int pcm_used; /* counter of pcm_rec[] */
160 /* bitmap shows whether the pcm is opened in user space
161 * bit 0 means the first playback PCM (PCM3);
162 * bit 1 means the second playback PCM, and so on.
163 */
164 unsigned long pcm_in_use;
165
166 struct hdmi_eld temp_eld;
167 struct hdmi_ops ops;
168
169 bool dyn_pin_out;
170 bool static_pcm_mapping;
171 /* hdmi interrupt trigger control flag for Nvidia codec */
172 bool hdmi_intr_trig_ctrl;
173 bool nv_dp_workaround; /* workaround DP audio infoframe for Nvidia */
174
175 bool intel_hsw_fixup; /* apply Intel platform-specific fixups */
176 /*
177 * Non-generic VIA/NVIDIA specific
178 */
179 struct hda_multi_out multiout;
180 struct hda_pcm_stream pcm_playback;
181
182 bool use_acomp_notifier; /* use eld_notify callback for hotplug */
183 bool acomp_registered; /* audio component registered in this driver */
184 bool force_connect; /* force connectivity */
185 struct drm_audio_component_audio_ops drm_audio_ops;
186 int (*port2pin)(struct hda_codec *, int); /* reverse port/pin mapping */
187
188 struct hdac_chmap chmap;
189 hda_nid_t vendor_nid;
190 const int *port_map;
191 int port_num;
192 int silent_stream_type;
193};
194
195#ifdef CONFIG_SND_HDA_COMPONENT
196static inline bool codec_has_acomp(struct hda_codec *codec)
197{
198 struct hdmi_spec *spec = codec->spec;
199 return spec->use_acomp_notifier;
200}
201#else
202#define codec_has_acomp(codec) false
203#endif
204
205struct hdmi_audio_infoframe {
206 u8 type; /* 0x84 */
207 u8 ver; /* 0x01 */
208 u8 len; /* 0x0a */
209
210 u8 checksum;
211
212 u8 CC02_CT47; /* CC in bits 0:2, CT in 4:7 */
213 u8 SS01_SF24;
214 u8 CXT04;
215 u8 CA;
216 u8 LFEPBL01_LSV36_DM_INH7;
217};
218
219struct dp_audio_infoframe {
220 u8 type; /* 0x84 */
221 u8 len; /* 0x1b */
222 u8 ver; /* 0x11 << 2 */
223
224 u8 CC02_CT47; /* match with HDMI infoframe from this on */
225 u8 SS01_SF24;
226 u8 CXT04;
227 u8 CA;
228 u8 LFEPBL01_LSV36_DM_INH7;
229};
230
231union audio_infoframe {
232 struct hdmi_audio_infoframe hdmi;
233 struct dp_audio_infoframe dp;
234 DECLARE_FLEX_ARRAY(u8, bytes);
235};
236
237/*
238 * HDMI routines
239 */
240
241#define get_pin(spec, idx) \
242 ((struct hdmi_spec_per_pin *)snd_array_elem(&spec->pins, idx))
243#define get_cvt(spec, idx) \
244 ((struct hdmi_spec_per_cvt *)snd_array_elem(&spec->cvts, idx))
245/* obtain hdmi_pcm object assigned to idx */
246#define get_hdmi_pcm(spec, idx) (&(spec)->pcm_rec[idx])
247/* obtain hda_pcm object assigned to idx */
248#define get_pcm_rec(spec, idx) (get_hdmi_pcm(spec, idx)->pcm)
249
250static int pin_id_to_pin_index(struct hda_codec *codec,
251 hda_nid_t pin_nid, int dev_id)
252{
253 struct hdmi_spec *spec = codec->spec;
254 int pin_idx;
255 struct hdmi_spec_per_pin *per_pin;
256
257 /*
258 * (dev_id == -1) means it is NON-MST pin
259 * return the first virtual pin on this port
260 */
261 if (dev_id == -1)
262 dev_id = 0;
263
264 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
265 per_pin = get_pin(spec, pin_idx);
266 if ((per_pin->pin_nid == pin_nid) &&
267 (per_pin->dev_id == dev_id))
268 return pin_idx;
269 }
270
271 codec_warn(codec, "HDMI: pin NID 0x%x not registered\n", pin_nid);
272 return -EINVAL;
273}
274
275static int hinfo_to_pcm_index(struct hda_codec *codec,
276 struct hda_pcm_stream *hinfo)
277{
278 struct hdmi_spec *spec = codec->spec;
279 int pcm_idx;
280
281 for (pcm_idx = 0; pcm_idx < spec->pcm_used; pcm_idx++)
282 if (get_pcm_rec(spec, pcm_idx)->stream == hinfo)
283 return pcm_idx;
284
285 codec_warn(codec, "HDMI: hinfo %p not tied to a PCM\n", hinfo);
286 return -EINVAL;
287}
288
289static int hinfo_to_pin_index(struct hda_codec *codec,
290 struct hda_pcm_stream *hinfo)
291{
292 struct hdmi_spec *spec = codec->spec;
293 struct hdmi_spec_per_pin *per_pin;
294 int pin_idx;
295
296 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
297 per_pin = get_pin(spec, pin_idx);
298 if (per_pin->pcm &&
299 per_pin->pcm->pcm->stream == hinfo)
300 return pin_idx;
301 }
302
303 codec_dbg(codec, "HDMI: hinfo %p (pcm %d) not registered\n", hinfo,
304 hinfo_to_pcm_index(codec, hinfo));
305 return -EINVAL;
306}
307
308static struct hdmi_spec_per_pin *pcm_idx_to_pin(struct hdmi_spec *spec,
309 int pcm_idx)
310{
311 int i;
312 struct hdmi_spec_per_pin *per_pin;
313
314 for (i = 0; i < spec->num_pins; i++) {
315 per_pin = get_pin(spec, i);
316 if (per_pin->pcm_idx == pcm_idx)
317 return per_pin;
318 }
319 return NULL;
320}
321
322static int cvt_nid_to_cvt_index(struct hda_codec *codec, hda_nid_t cvt_nid)
323{
324 struct hdmi_spec *spec = codec->spec;
325 int cvt_idx;
326
327 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++)
328 if (get_cvt(spec, cvt_idx)->cvt_nid == cvt_nid)
329 return cvt_idx;
330
331 codec_warn(codec, "HDMI: cvt NID 0x%x not registered\n", cvt_nid);
332 return -EINVAL;
333}
334
335static int hdmi_eld_ctl_info(struct snd_kcontrol *kcontrol,
336 struct snd_ctl_elem_info *uinfo)
337{
338 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
339 struct hdmi_spec *spec = codec->spec;
340 struct hdmi_spec_per_pin *per_pin;
341 struct hdmi_eld *eld;
342 int pcm_idx;
343
344 uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES;
345
346 pcm_idx = kcontrol->private_value;
347 mutex_lock(&spec->pcm_lock);
348 per_pin = pcm_idx_to_pin(spec, pcm_idx);
349 if (!per_pin) {
350 /* no pin is bound to the pcm */
351 uinfo->count = 0;
352 goto unlock;
353 }
354 eld = &per_pin->sink_eld;
355 uinfo->count = eld->eld_valid ? eld->eld_size : 0;
356
357 unlock:
358 mutex_unlock(&spec->pcm_lock);
359 return 0;
360}
361
362static int hdmi_eld_ctl_get(struct snd_kcontrol *kcontrol,
363 struct snd_ctl_elem_value *ucontrol)
364{
365 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
366 struct hdmi_spec *spec = codec->spec;
367 struct hdmi_spec_per_pin *per_pin;
368 struct hdmi_eld *eld;
369 int pcm_idx;
370 int err = 0;
371
372 pcm_idx = kcontrol->private_value;
373 mutex_lock(&spec->pcm_lock);
374 per_pin = pcm_idx_to_pin(spec, pcm_idx);
375 if (!per_pin) {
376 /* no pin is bound to the pcm */
377 memset(ucontrol->value.bytes.data, 0,
378 ARRAY_SIZE(ucontrol->value.bytes.data));
379 goto unlock;
380 }
381
382 eld = &per_pin->sink_eld;
383 if (eld->eld_size > ARRAY_SIZE(ucontrol->value.bytes.data) ||
384 eld->eld_size > ELD_MAX_SIZE) {
385 snd_BUG();
386 err = -EINVAL;
387 goto unlock;
388 }
389
390 memset(ucontrol->value.bytes.data, 0,
391 ARRAY_SIZE(ucontrol->value.bytes.data));
392 if (eld->eld_valid)
393 memcpy(ucontrol->value.bytes.data, eld->eld_buffer,
394 eld->eld_size);
395
396 unlock:
397 mutex_unlock(&spec->pcm_lock);
398 return err;
399}
400
401static const struct snd_kcontrol_new eld_bytes_ctl = {
402 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE |
403 SNDRV_CTL_ELEM_ACCESS_SKIP_CHECK,
404 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
405 .name = "ELD",
406 .info = hdmi_eld_ctl_info,
407 .get = hdmi_eld_ctl_get,
408};
409
410static int hdmi_create_eld_ctl(struct hda_codec *codec, int pcm_idx,
411 int device)
412{
413 struct snd_kcontrol *kctl;
414 struct hdmi_spec *spec = codec->spec;
415 int err;
416
417 kctl = snd_ctl_new1(&eld_bytes_ctl, codec);
418 if (!kctl)
419 return -ENOMEM;
420 kctl->private_value = pcm_idx;
421 kctl->id.device = device;
422
423 /* no pin nid is associated with the kctl now
424 * tbd: associate pin nid to eld ctl later
425 */
426 err = snd_hda_ctl_add(codec, 0, kctl);
427 if (err < 0)
428 return err;
429
430 get_hdmi_pcm(spec, pcm_idx)->eld_ctl = kctl;
431 return 0;
432}
433
434#ifdef BE_PARANOID
435static void hdmi_get_dip_index(struct hda_codec *codec, hda_nid_t pin_nid,
436 int *packet_index, int *byte_index)
437{
438 int val;
439
440 val = snd_hda_codec_read(codec, pin_nid, 0,
441 AC_VERB_GET_HDMI_DIP_INDEX, 0);
442
443 *packet_index = val >> 5;
444 *byte_index = val & 0x1f;
445}
446#endif
447
448static void hdmi_set_dip_index(struct hda_codec *codec, hda_nid_t pin_nid,
449 int packet_index, int byte_index)
450{
451 int val;
452
453 val = (packet_index << 5) | (byte_index & 0x1f);
454
455 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_INDEX, val);
456}
457
458static void hdmi_write_dip_byte(struct hda_codec *codec, hda_nid_t pin_nid,
459 unsigned char val)
460{
461 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_DATA, val);
462}
463
464static void hdmi_init_pin(struct hda_codec *codec, hda_nid_t pin_nid)
465{
466 struct hdmi_spec *spec = codec->spec;
467 int pin_out;
468
469 /* Unmute */
470 if (get_wcaps(codec, pin_nid) & AC_WCAP_OUT_AMP)
471 snd_hda_codec_write(codec, pin_nid, 0,
472 AC_VERB_SET_AMP_GAIN_MUTE, AMP_OUT_UNMUTE);
473
474 if (spec->dyn_pin_out)
475 /* Disable pin out until stream is active */
476 pin_out = 0;
477 else
478 /* Enable pin out: some machines with GM965 gets broken output
479 * when the pin is disabled or changed while using with HDMI
480 */
481 pin_out = PIN_OUT;
482
483 snd_hda_codec_write(codec, pin_nid, 0,
484 AC_VERB_SET_PIN_WIDGET_CONTROL, pin_out);
485}
486
487/*
488 * ELD proc files
489 */
490
491#ifdef CONFIG_SND_PROC_FS
492static void print_eld_info(struct snd_info_entry *entry,
493 struct snd_info_buffer *buffer)
494{
495 struct hdmi_spec_per_pin *per_pin = entry->private_data;
496
497 mutex_lock(&per_pin->lock);
498 snd_hdmi_print_eld_info(&per_pin->sink_eld, buffer, per_pin->pin_nid,
499 per_pin->dev_id, per_pin->cvt_nid);
500 mutex_unlock(&per_pin->lock);
501}
502
503static void write_eld_info(struct snd_info_entry *entry,
504 struct snd_info_buffer *buffer)
505{
506 struct hdmi_spec_per_pin *per_pin = entry->private_data;
507
508 mutex_lock(&per_pin->lock);
509 snd_hdmi_write_eld_info(&per_pin->sink_eld, buffer);
510 mutex_unlock(&per_pin->lock);
511}
512
513static int eld_proc_new(struct hdmi_spec_per_pin *per_pin, int index)
514{
515 char name[32];
516 struct hda_codec *codec = per_pin->codec;
517 struct snd_info_entry *entry;
518 int err;
519
520 snprintf(name, sizeof(name), "eld#%d.%d", codec->addr, index);
521 err = snd_card_proc_new(codec->card, name, &entry);
522 if (err < 0)
523 return err;
524
525 snd_info_set_text_ops(entry, per_pin, print_eld_info);
526 entry->c.text.write = write_eld_info;
527 entry->mode |= 0200;
528 per_pin->proc_entry = entry;
529
530 return 0;
531}
532
533static void eld_proc_free(struct hdmi_spec_per_pin *per_pin)
534{
535 if (!per_pin->codec->bus->shutdown) {
536 snd_info_free_entry(per_pin->proc_entry);
537 per_pin->proc_entry = NULL;
538 }
539}
540#else
541static inline int eld_proc_new(struct hdmi_spec_per_pin *per_pin,
542 int index)
543{
544 return 0;
545}
546static inline void eld_proc_free(struct hdmi_spec_per_pin *per_pin)
547{
548}
549#endif
550
551/*
552 * Audio InfoFrame routines
553 */
554
555/*
556 * Enable Audio InfoFrame Transmission
557 */
558static void hdmi_start_infoframe_trans(struct hda_codec *codec,
559 hda_nid_t pin_nid)
560{
561 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
562 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_XMIT,
563 AC_DIPXMIT_BEST);
564}
565
566/*
567 * Disable Audio InfoFrame Transmission
568 */
569static void hdmi_stop_infoframe_trans(struct hda_codec *codec,
570 hda_nid_t pin_nid)
571{
572 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
573 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_XMIT,
574 AC_DIPXMIT_DISABLE);
575}
576
577static void hdmi_debug_dip_size(struct hda_codec *codec, hda_nid_t pin_nid)
578{
579#ifdef CONFIG_SND_DEBUG_VERBOSE
580 int i;
581 int size;
582
583 size = snd_hdmi_get_eld_size(codec, pin_nid);
584 codec_dbg(codec, "HDMI: ELD buf size is %d\n", size);
585
586 for (i = 0; i < 8; i++) {
587 size = snd_hda_codec_read(codec, pin_nid, 0,
588 AC_VERB_GET_HDMI_DIP_SIZE, i);
589 codec_dbg(codec, "HDMI: DIP GP[%d] buf size is %d\n", i, size);
590 }
591#endif
592}
593
594static void hdmi_clear_dip_buffers(struct hda_codec *codec, hda_nid_t pin_nid)
595{
596#ifdef BE_PARANOID
597 int i, j;
598 int size;
599 int pi, bi;
600 for (i = 0; i < 8; i++) {
601 size = snd_hda_codec_read(codec, pin_nid, 0,
602 AC_VERB_GET_HDMI_DIP_SIZE, i);
603 if (size == 0)
604 continue;
605
606 hdmi_set_dip_index(codec, pin_nid, i, 0x0);
607 for (j = 1; j < 1000; j++) {
608 hdmi_write_dip_byte(codec, pin_nid, 0x0);
609 hdmi_get_dip_index(codec, pin_nid, &pi, &bi);
610 if (pi != i)
611 codec_dbg(codec, "dip index %d: %d != %d\n",
612 bi, pi, i);
613 if (bi == 0) /* byte index wrapped around */
614 break;
615 }
616 codec_dbg(codec,
617 "HDMI: DIP GP[%d] buf reported size=%d, written=%d\n",
618 i, size, j);
619 }
620#endif
621}
622
623static void hdmi_checksum_audio_infoframe(struct hdmi_audio_infoframe *hdmi_ai)
624{
625 u8 *bytes = (u8 *)hdmi_ai;
626 u8 sum = 0;
627 int i;
628
629 hdmi_ai->checksum = 0;
630
631 for (i = 0; i < sizeof(*hdmi_ai); i++)
632 sum += bytes[i];
633
634 hdmi_ai->checksum = -sum;
635}
636
637static void hdmi_fill_audio_infoframe(struct hda_codec *codec,
638 hda_nid_t pin_nid,
639 u8 *dip, int size)
640{
641 int i;
642
643 hdmi_debug_dip_size(codec, pin_nid);
644 hdmi_clear_dip_buffers(codec, pin_nid); /* be paranoid */
645
646 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
647 for (i = 0; i < size; i++)
648 hdmi_write_dip_byte(codec, pin_nid, dip[i]);
649}
650
651static bool hdmi_infoframe_uptodate(struct hda_codec *codec, hda_nid_t pin_nid,
652 u8 *dip, int size)
653{
654 u8 val;
655 int i;
656
657 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
658 if (snd_hda_codec_read(codec, pin_nid, 0, AC_VERB_GET_HDMI_DIP_XMIT, 0)
659 != AC_DIPXMIT_BEST)
660 return false;
661
662 for (i = 0; i < size; i++) {
663 val = snd_hda_codec_read(codec, pin_nid, 0,
664 AC_VERB_GET_HDMI_DIP_DATA, 0);
665 if (val != dip[i])
666 return false;
667 }
668
669 return true;
670}
671
672static int hdmi_pin_get_eld(struct hda_codec *codec, hda_nid_t nid,
673 int dev_id, unsigned char *buf, int *eld_size)
674{
675 snd_hda_set_dev_select(codec, nid, dev_id);
676
677 return snd_hdmi_get_eld(codec, nid, buf, eld_size);
678}
679
680static void hdmi_pin_setup_infoframe(struct hda_codec *codec,
681 hda_nid_t pin_nid, int dev_id,
682 int ca, int active_channels,
683 int conn_type)
684{
685 struct hdmi_spec *spec = codec->spec;
686 union audio_infoframe ai;
687
688 memset(&ai, 0, sizeof(ai));
689 if ((conn_type == 0) || /* HDMI */
690 /* Nvidia DisplayPort: Nvidia HW expects same layout as HDMI */
691 (conn_type == 1 && spec->nv_dp_workaround)) {
692 struct hdmi_audio_infoframe *hdmi_ai = &ai.hdmi;
693
694 if (conn_type == 0) { /* HDMI */
695 hdmi_ai->type = 0x84;
696 hdmi_ai->ver = 0x01;
697 hdmi_ai->len = 0x0a;
698 } else {/* Nvidia DP */
699 hdmi_ai->type = 0x84;
700 hdmi_ai->ver = 0x1b;
701 hdmi_ai->len = 0x11 << 2;
702 }
703 hdmi_ai->CC02_CT47 = active_channels - 1;
704 hdmi_ai->CA = ca;
705 hdmi_checksum_audio_infoframe(hdmi_ai);
706 } else if (conn_type == 1) { /* DisplayPort */
707 struct dp_audio_infoframe *dp_ai = &ai.dp;
708
709 dp_ai->type = 0x84;
710 dp_ai->len = 0x1b;
711 dp_ai->ver = 0x11 << 2;
712 dp_ai->CC02_CT47 = active_channels - 1;
713 dp_ai->CA = ca;
714 } else {
715 codec_dbg(codec, "HDMI: unknown connection type at pin NID 0x%x\n", pin_nid);
716 return;
717 }
718
719 snd_hda_set_dev_select(codec, pin_nid, dev_id);
720
721 /*
722 * sizeof(ai) is used instead of sizeof(*hdmi_ai) or
723 * sizeof(*dp_ai) to avoid partial match/update problems when
724 * the user switches between HDMI/DP monitors.
725 */
726 if (!hdmi_infoframe_uptodate(codec, pin_nid, ai.bytes,
727 sizeof(ai))) {
728 codec_dbg(codec, "%s: pin NID=0x%x channels=%d ca=0x%02x\n",
729 __func__, pin_nid, active_channels, ca);
730 hdmi_stop_infoframe_trans(codec, pin_nid);
731 hdmi_fill_audio_infoframe(codec, pin_nid,
732 ai.bytes, sizeof(ai));
733 hdmi_start_infoframe_trans(codec, pin_nid);
734 }
735}
736
737static void hdmi_setup_audio_infoframe(struct hda_codec *codec,
738 struct hdmi_spec_per_pin *per_pin,
739 bool non_pcm)
740{
741 struct hdmi_spec *spec = codec->spec;
742 struct hdac_chmap *chmap = &spec->chmap;
743 hda_nid_t pin_nid = per_pin->pin_nid;
744 int dev_id = per_pin->dev_id;
745 int channels = per_pin->channels;
746 int active_channels;
747 struct hdmi_eld *eld;
748 int ca;
749
750 if (!channels)
751 return;
752
753 snd_hda_set_dev_select(codec, pin_nid, dev_id);
754
755 /* some HW (e.g. HSW+) needs reprogramming the amp at each time */
756 if (get_wcaps(codec, pin_nid) & AC_WCAP_OUT_AMP)
757 snd_hda_codec_write(codec, pin_nid, 0,
758 AC_VERB_SET_AMP_GAIN_MUTE,
759 AMP_OUT_UNMUTE);
760
761 eld = &per_pin->sink_eld;
762
763 ca = snd_hdac_channel_allocation(&codec->core,
764 eld->info.spk_alloc, channels,
765 per_pin->chmap_set, non_pcm, per_pin->chmap);
766
767 active_channels = snd_hdac_get_active_channels(ca);
768
769 chmap->ops.set_channel_count(&codec->core, per_pin->cvt_nid,
770 active_channels);
771
772 /*
773 * always configure channel mapping, it may have been changed by the
774 * user in the meantime
775 */
776 snd_hdac_setup_channel_mapping(&spec->chmap,
777 pin_nid, non_pcm, ca, channels,
778 per_pin->chmap, per_pin->chmap_set);
779
780 spec->ops.pin_setup_infoframe(codec, pin_nid, dev_id,
781 ca, active_channels, eld->info.conn_type);
782
783 per_pin->non_pcm = non_pcm;
784}
785
786/*
787 * Unsolicited events
788 */
789
790static void hdmi_present_sense(struct hdmi_spec_per_pin *per_pin, int repoll);
791
792static void check_presence_and_report(struct hda_codec *codec, hda_nid_t nid,
793 int dev_id)
794{
795 struct hdmi_spec *spec = codec->spec;
796 int pin_idx = pin_id_to_pin_index(codec, nid, dev_id);
797
798 if (pin_idx < 0)
799 return;
800 mutex_lock(&spec->pcm_lock);
801 hdmi_present_sense(get_pin(spec, pin_idx), 1);
802 mutex_unlock(&spec->pcm_lock);
803}
804
805static void jack_callback(struct hda_codec *codec,
806 struct hda_jack_callback *jack)
807{
808 /* stop polling when notification is enabled */
809 if (codec_has_acomp(codec))
810 return;
811
812 check_presence_and_report(codec, jack->nid, jack->dev_id);
813}
814
815static void hdmi_intrinsic_event(struct hda_codec *codec, unsigned int res,
816 struct hda_jack_tbl *jack)
817{
818 jack->jack_dirty = 1;
819
820 codec_dbg(codec,
821 "HDMI hot plug event: Codec=%d NID=0x%x Device=%d Inactive=%d Presence_Detect=%d ELD_Valid=%d\n",
822 codec->addr, jack->nid, jack->dev_id, !!(res & AC_UNSOL_RES_IA),
823 !!(res & AC_UNSOL_RES_PD), !!(res & AC_UNSOL_RES_ELDV));
824
825 check_presence_and_report(codec, jack->nid, jack->dev_id);
826}
827
828static void hdmi_non_intrinsic_event(struct hda_codec *codec, unsigned int res)
829{
830 int tag = res >> AC_UNSOL_RES_TAG_SHIFT;
831 int subtag = (res & AC_UNSOL_RES_SUBTAG) >> AC_UNSOL_RES_SUBTAG_SHIFT;
832 int cp_state = !!(res & AC_UNSOL_RES_CP_STATE);
833 int cp_ready = !!(res & AC_UNSOL_RES_CP_READY);
834
835 codec_info(codec,
836 "HDMI CP event: CODEC=%d TAG=%d SUBTAG=0x%x CP_STATE=%d CP_READY=%d\n",
837 codec->addr,
838 tag,
839 subtag,
840 cp_state,
841 cp_ready);
842
843 /* TODO */
844 if (cp_state) {
845 ;
846 }
847 if (cp_ready) {
848 ;
849 }
850}
851
852
853static void hdmi_unsol_event(struct hda_codec *codec, unsigned int res)
854{
855 int tag = res >> AC_UNSOL_RES_TAG_SHIFT;
856 int subtag = (res & AC_UNSOL_RES_SUBTAG) >> AC_UNSOL_RES_SUBTAG_SHIFT;
857 struct hda_jack_tbl *jack;
858
859 if (codec_has_acomp(codec))
860 return;
861
862 if (codec->dp_mst) {
863 int dev_entry =
864 (res & AC_UNSOL_RES_DE) >> AC_UNSOL_RES_DE_SHIFT;
865
866 jack = snd_hda_jack_tbl_get_from_tag(codec, tag, dev_entry);
867 } else {
868 jack = snd_hda_jack_tbl_get_from_tag(codec, tag, 0);
869 }
870
871 if (!jack) {
872 codec_dbg(codec, "Unexpected HDMI event tag 0x%x\n", tag);
873 return;
874 }
875
876 if (subtag == 0)
877 hdmi_intrinsic_event(codec, res, jack);
878 else
879 hdmi_non_intrinsic_event(codec, res);
880}
881
882static void haswell_verify_D0(struct hda_codec *codec,
883 hda_nid_t cvt_nid, hda_nid_t nid)
884{
885 int pwr;
886
887 /* For Haswell, the converter 1/2 may keep in D3 state after bootup,
888 * thus pins could only choose converter 0 for use. Make sure the
889 * converters are in correct power state */
890 if (!snd_hda_check_power_state(codec, cvt_nid, AC_PWRST_D0))
891 snd_hda_codec_write(codec, cvt_nid, 0, AC_VERB_SET_POWER_STATE, AC_PWRST_D0);
892
893 if (!snd_hda_check_power_state(codec, nid, AC_PWRST_D0)) {
894 snd_hda_codec_write(codec, nid, 0, AC_VERB_SET_POWER_STATE,
895 AC_PWRST_D0);
896 msleep(40);
897 pwr = snd_hda_codec_read(codec, nid, 0, AC_VERB_GET_POWER_STATE, 0);
898 pwr = (pwr & AC_PWRST_ACTUAL) >> AC_PWRST_ACTUAL_SHIFT;
899 codec_dbg(codec, "Haswell HDMI audio: Power for NID 0x%x is now D%d\n", nid, pwr);
900 }
901}
902
903/*
904 * Callbacks
905 */
906
907/* HBR should be Non-PCM, 8 channels */
908#define is_hbr_format(format) \
909 ((format & AC_FMT_TYPE_NON_PCM) && (format & AC_FMT_CHAN_MASK) == 7)
910
911static int hdmi_pin_hbr_setup(struct hda_codec *codec, hda_nid_t pin_nid,
912 int dev_id, bool hbr)
913{
914 int pinctl, new_pinctl;
915
916 if (snd_hda_query_pin_caps(codec, pin_nid) & AC_PINCAP_HBR) {
917 snd_hda_set_dev_select(codec, pin_nid, dev_id);
918 pinctl = snd_hda_codec_read(codec, pin_nid, 0,
919 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
920
921 if (pinctl < 0)
922 return hbr ? -EINVAL : 0;
923
924 new_pinctl = pinctl & ~AC_PINCTL_EPT;
925 if (hbr)
926 new_pinctl |= AC_PINCTL_EPT_HBR;
927 else
928 new_pinctl |= AC_PINCTL_EPT_NATIVE;
929
930 codec_dbg(codec,
931 "hdmi_pin_hbr_setup: NID=0x%x, %spinctl=0x%x\n",
932 pin_nid,
933 pinctl == new_pinctl ? "" : "new-",
934 new_pinctl);
935
936 if (pinctl != new_pinctl)
937 snd_hda_codec_write(codec, pin_nid, 0,
938 AC_VERB_SET_PIN_WIDGET_CONTROL,
939 new_pinctl);
940 } else if (hbr)
941 return -EINVAL;
942
943 return 0;
944}
945
946static int hdmi_setup_stream(struct hda_codec *codec, hda_nid_t cvt_nid,
947 hda_nid_t pin_nid, int dev_id,
948 u32 stream_tag, int format)
949{
950 struct hdmi_spec *spec = codec->spec;
951 unsigned int param;
952 int err;
953
954 err = spec->ops.pin_hbr_setup(codec, pin_nid, dev_id,
955 is_hbr_format(format));
956
957 if (err) {
958 codec_dbg(codec, "hdmi_setup_stream: HBR is not supported\n");
959 return err;
960 }
961
962 if (spec->intel_hsw_fixup) {
963
964 /*
965 * on recent platforms IEC Coding Type is required for HBR
966 * support, read current Digital Converter settings and set
967 * ICT bitfield if needed.
968 */
969 param = snd_hda_codec_read(codec, cvt_nid, 0,
970 AC_VERB_GET_DIGI_CONVERT_1, 0);
971
972 param = (param >> 16) & ~(AC_DIG3_ICT);
973
974 /* on recent platforms ICT mode is required for HBR support */
975 if (is_hbr_format(format))
976 param |= 0x1;
977
978 snd_hda_codec_write(codec, cvt_nid, 0,
979 AC_VERB_SET_DIGI_CONVERT_3, param);
980 }
981
982 snd_hda_codec_setup_stream(codec, cvt_nid, stream_tag, 0, format);
983 return 0;
984}
985
986/* Try to find an available converter
987 * If pin_idx is less then zero, just try to find an available converter.
988 * Otherwise, try to find an available converter and get the cvt mux index
989 * of the pin.
990 */
991static int hdmi_choose_cvt(struct hda_codec *codec,
992 int pin_idx, int *cvt_id,
993 bool silent)
994{
995 struct hdmi_spec *spec = codec->spec;
996 struct hdmi_spec_per_pin *per_pin;
997 struct hdmi_spec_per_cvt *per_cvt = NULL;
998 int cvt_idx, mux_idx = 0;
999
1000 /* pin_idx < 0 means no pin will be bound to the converter */
1001 if (pin_idx < 0)
1002 per_pin = NULL;
1003 else
1004 per_pin = get_pin(spec, pin_idx);
1005
1006 if (per_pin && per_pin->silent_stream) {
1007 cvt_idx = cvt_nid_to_cvt_index(codec, per_pin->cvt_nid);
1008 per_cvt = get_cvt(spec, cvt_idx);
1009 if (per_cvt->assigned && !silent)
1010 return -EBUSY;
1011 if (cvt_id)
1012 *cvt_id = cvt_idx;
1013 return 0;
1014 }
1015
1016 /* Dynamically assign converter to stream */
1017 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) {
1018 per_cvt = get_cvt(spec, cvt_idx);
1019
1020 /* Must not already be assigned */
1021 if (per_cvt->assigned || per_cvt->silent_stream)
1022 continue;
1023 if (per_pin == NULL)
1024 break;
1025 /* Must be in pin's mux's list of converters */
1026 for (mux_idx = 0; mux_idx < per_pin->num_mux_nids; mux_idx++)
1027 if (per_pin->mux_nids[mux_idx] == per_cvt->cvt_nid)
1028 break;
1029 /* Not in mux list */
1030 if (mux_idx == per_pin->num_mux_nids)
1031 continue;
1032 break;
1033 }
1034
1035 /* No free converters */
1036 if (cvt_idx == spec->num_cvts)
1037 return -EBUSY;
1038
1039 if (per_pin != NULL)
1040 per_pin->mux_idx = mux_idx;
1041
1042 if (cvt_id)
1043 *cvt_id = cvt_idx;
1044
1045 return 0;
1046}
1047
1048/* Assure the pin select the right convetor */
1049static void intel_verify_pin_cvt_connect(struct hda_codec *codec,
1050 struct hdmi_spec_per_pin *per_pin)
1051{
1052 hda_nid_t pin_nid = per_pin->pin_nid;
1053 int mux_idx, curr;
1054
1055 mux_idx = per_pin->mux_idx;
1056 curr = snd_hda_codec_read(codec, pin_nid, 0,
1057 AC_VERB_GET_CONNECT_SEL, 0);
1058 if (curr != mux_idx)
1059 snd_hda_codec_write_cache(codec, pin_nid, 0,
1060 AC_VERB_SET_CONNECT_SEL,
1061 mux_idx);
1062}
1063
1064/* get the mux index for the converter of the pins
1065 * converter's mux index is the same for all pins on Intel platform
1066 */
1067static int intel_cvt_id_to_mux_idx(struct hdmi_spec *spec,
1068 hda_nid_t cvt_nid)
1069{
1070 int i;
1071
1072 for (i = 0; i < spec->num_cvts; i++)
1073 if (spec->cvt_nids[i] == cvt_nid)
1074 return i;
1075 return -EINVAL;
1076}
1077
1078/* Intel HDMI workaround to fix audio routing issue:
1079 * For some Intel display codecs, pins share the same connection list.
1080 * So a conveter can be selected by multiple pins and playback on any of these
1081 * pins will generate sound on the external display, because audio flows from
1082 * the same converter to the display pipeline. Also muting one pin may make
1083 * other pins have no sound output.
1084 * So this function assures that an assigned converter for a pin is not selected
1085 * by any other pins.
1086 */
1087static void intel_not_share_assigned_cvt(struct hda_codec *codec,
1088 hda_nid_t pin_nid,
1089 int dev_id, int mux_idx)
1090{
1091 struct hdmi_spec *spec = codec->spec;
1092 hda_nid_t nid;
1093 int cvt_idx, curr;
1094 struct hdmi_spec_per_cvt *per_cvt;
1095 struct hdmi_spec_per_pin *per_pin;
1096 int pin_idx;
1097
1098 /* configure the pins connections */
1099 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
1100 int dev_id_saved;
1101 int dev_num;
1102
1103 per_pin = get_pin(spec, pin_idx);
1104 /*
1105 * pin not connected to monitor
1106 * no need to operate on it
1107 */
1108 if (!per_pin->pcm)
1109 continue;
1110
1111 if ((per_pin->pin_nid == pin_nid) &&
1112 (per_pin->dev_id == dev_id))
1113 continue;
1114
1115 /*
1116 * if per_pin->dev_id >= dev_num,
1117 * snd_hda_get_dev_select() will fail,
1118 * and the following operation is unpredictable.
1119 * So skip this situation.
1120 */
1121 dev_num = snd_hda_get_num_devices(codec, per_pin->pin_nid) + 1;
1122 if (per_pin->dev_id >= dev_num)
1123 continue;
1124
1125 nid = per_pin->pin_nid;
1126
1127 /*
1128 * Calling this function should not impact
1129 * on the device entry selection
1130 * So let's save the dev id for each pin,
1131 * and restore it when return
1132 */
1133 dev_id_saved = snd_hda_get_dev_select(codec, nid);
1134 snd_hda_set_dev_select(codec, nid, per_pin->dev_id);
1135 curr = snd_hda_codec_read(codec, nid, 0,
1136 AC_VERB_GET_CONNECT_SEL, 0);
1137 if (curr != mux_idx) {
1138 snd_hda_set_dev_select(codec, nid, dev_id_saved);
1139 continue;
1140 }
1141
1142
1143 /* choose an unassigned converter. The conveters in the
1144 * connection list are in the same order as in the codec.
1145 */
1146 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) {
1147 per_cvt = get_cvt(spec, cvt_idx);
1148 if (!per_cvt->assigned) {
1149 codec_dbg(codec,
1150 "choose cvt %d for pin NID 0x%x\n",
1151 cvt_idx, nid);
1152 snd_hda_codec_write_cache(codec, nid, 0,
1153 AC_VERB_SET_CONNECT_SEL,
1154 cvt_idx);
1155 break;
1156 }
1157 }
1158 snd_hda_set_dev_select(codec, nid, dev_id_saved);
1159 }
1160}
1161
1162/* A wrapper of intel_not_share_asigned_cvt() */
1163static void intel_not_share_assigned_cvt_nid(struct hda_codec *codec,
1164 hda_nid_t pin_nid, int dev_id, hda_nid_t cvt_nid)
1165{
1166 int mux_idx;
1167 struct hdmi_spec *spec = codec->spec;
1168
1169 /* On Intel platform, the mapping of converter nid to
1170 * mux index of the pins are always the same.
1171 * The pin nid may be 0, this means all pins will not
1172 * share the converter.
1173 */
1174 mux_idx = intel_cvt_id_to_mux_idx(spec, cvt_nid);
1175 if (mux_idx >= 0)
1176 intel_not_share_assigned_cvt(codec, pin_nid, dev_id, mux_idx);
1177}
1178
1179/* skeleton caller of pin_cvt_fixup ops */
1180static void pin_cvt_fixup(struct hda_codec *codec,
1181 struct hdmi_spec_per_pin *per_pin,
1182 hda_nid_t cvt_nid)
1183{
1184 struct hdmi_spec *spec = codec->spec;
1185
1186 if (spec->ops.pin_cvt_fixup)
1187 spec->ops.pin_cvt_fixup(codec, per_pin, cvt_nid);
1188}
1189
1190/* called in hdmi_pcm_open when no pin is assigned to the PCM */
1191static int hdmi_pcm_open_no_pin(struct hda_pcm_stream *hinfo,
1192 struct hda_codec *codec,
1193 struct snd_pcm_substream *substream)
1194{
1195 struct hdmi_spec *spec = codec->spec;
1196 struct snd_pcm_runtime *runtime = substream->runtime;
1197 int cvt_idx, pcm_idx;
1198 struct hdmi_spec_per_cvt *per_cvt = NULL;
1199 int err;
1200
1201 pcm_idx = hinfo_to_pcm_index(codec, hinfo);
1202 if (pcm_idx < 0)
1203 return -EINVAL;
1204
1205 err = hdmi_choose_cvt(codec, -1, &cvt_idx, false);
1206 if (err)
1207 return err;
1208
1209 per_cvt = get_cvt(spec, cvt_idx);
1210 per_cvt->assigned = true;
1211 hinfo->nid = per_cvt->cvt_nid;
1212
1213 pin_cvt_fixup(codec, NULL, per_cvt->cvt_nid);
1214
1215 set_bit(pcm_idx, &spec->pcm_in_use);
1216 /* todo: setup spdif ctls assign */
1217
1218 /* Initially set the converter's capabilities */
1219 hinfo->channels_min = per_cvt->channels_min;
1220 hinfo->channels_max = per_cvt->channels_max;
1221 hinfo->rates = per_cvt->rates;
1222 hinfo->formats = per_cvt->formats;
1223 hinfo->maxbps = per_cvt->maxbps;
1224
1225 /* Store the updated parameters */
1226 runtime->hw.channels_min = hinfo->channels_min;
1227 runtime->hw.channels_max = hinfo->channels_max;
1228 runtime->hw.formats = hinfo->formats;
1229 runtime->hw.rates = hinfo->rates;
1230
1231 snd_pcm_hw_constraint_step(substream->runtime, 0,
1232 SNDRV_PCM_HW_PARAM_CHANNELS, 2);
1233 return 0;
1234}
1235
1236/*
1237 * HDA PCM callbacks
1238 */
1239static int hdmi_pcm_open(struct hda_pcm_stream *hinfo,
1240 struct hda_codec *codec,
1241 struct snd_pcm_substream *substream)
1242{
1243 struct hdmi_spec *spec = codec->spec;
1244 struct snd_pcm_runtime *runtime = substream->runtime;
1245 int pin_idx, cvt_idx, pcm_idx;
1246 struct hdmi_spec_per_pin *per_pin;
1247 struct hdmi_eld *eld;
1248 struct hdmi_spec_per_cvt *per_cvt = NULL;
1249 int err;
1250
1251 /* Validate hinfo */
1252 pcm_idx = hinfo_to_pcm_index(codec, hinfo);
1253 if (pcm_idx < 0)
1254 return -EINVAL;
1255
1256 mutex_lock(&spec->pcm_lock);
1257 pin_idx = hinfo_to_pin_index(codec, hinfo);
1258 /* no pin is assigned to the PCM
1259 * PA need pcm open successfully when probe
1260 */
1261 if (pin_idx < 0) {
1262 err = hdmi_pcm_open_no_pin(hinfo, codec, substream);
1263 goto unlock;
1264 }
1265
1266 err = hdmi_choose_cvt(codec, pin_idx, &cvt_idx, false);
1267 if (err < 0)
1268 goto unlock;
1269
1270 per_cvt = get_cvt(spec, cvt_idx);
1271 /* Claim converter */
1272 per_cvt->assigned = true;
1273
1274 set_bit(pcm_idx, &spec->pcm_in_use);
1275 per_pin = get_pin(spec, pin_idx);
1276 per_pin->cvt_nid = per_cvt->cvt_nid;
1277 hinfo->nid = per_cvt->cvt_nid;
1278
1279 /* flip stripe flag for the assigned stream if supported */
1280 if (get_wcaps(codec, per_cvt->cvt_nid) & AC_WCAP_STRIPE)
1281 azx_stream(get_azx_dev(substream))->stripe = 1;
1282
1283 snd_hda_set_dev_select(codec, per_pin->pin_nid, per_pin->dev_id);
1284 snd_hda_codec_write_cache(codec, per_pin->pin_nid, 0,
1285 AC_VERB_SET_CONNECT_SEL,
1286 per_pin->mux_idx);
1287
1288 /* configure unused pins to choose other converters */
1289 pin_cvt_fixup(codec, per_pin, 0);
1290
1291 snd_hda_spdif_ctls_assign(codec, pcm_idx, per_cvt->cvt_nid);
1292
1293 /* Initially set the converter's capabilities */
1294 hinfo->channels_min = per_cvt->channels_min;
1295 hinfo->channels_max = per_cvt->channels_max;
1296 hinfo->rates = per_cvt->rates;
1297 hinfo->formats = per_cvt->formats;
1298 hinfo->maxbps = per_cvt->maxbps;
1299
1300 eld = &per_pin->sink_eld;
1301 /* Restrict capabilities by ELD if this isn't disabled */
1302 if (!static_hdmi_pcm && eld->eld_valid) {
1303 snd_hdmi_eld_update_pcm_info(&eld->info, hinfo);
1304 if (hinfo->channels_min > hinfo->channels_max ||
1305 !hinfo->rates || !hinfo->formats) {
1306 per_cvt->assigned = false;
1307 hinfo->nid = 0;
1308 snd_hda_spdif_ctls_unassign(codec, pcm_idx);
1309 err = -ENODEV;
1310 goto unlock;
1311 }
1312 }
1313
1314 /* Store the updated parameters */
1315 runtime->hw.channels_min = hinfo->channels_min;
1316 runtime->hw.channels_max = hinfo->channels_max;
1317 runtime->hw.formats = hinfo->formats;
1318 runtime->hw.rates = hinfo->rates;
1319
1320 snd_pcm_hw_constraint_step(substream->runtime, 0,
1321 SNDRV_PCM_HW_PARAM_CHANNELS, 2);
1322 unlock:
1323 mutex_unlock(&spec->pcm_lock);
1324 return err;
1325}
1326
1327/*
1328 * HDA/HDMI auto parsing
1329 */
1330static int hdmi_read_pin_conn(struct hda_codec *codec, int pin_idx)
1331{
1332 struct hdmi_spec *spec = codec->spec;
1333 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
1334 hda_nid_t pin_nid = per_pin->pin_nid;
1335 int dev_id = per_pin->dev_id;
1336 int conns;
1337
1338 if (!(get_wcaps(codec, pin_nid) & AC_WCAP_CONN_LIST)) {
1339 codec_warn(codec,
1340 "HDMI: pin NID 0x%x wcaps %#x does not support connection list\n",
1341 pin_nid, get_wcaps(codec, pin_nid));
1342 return -EINVAL;
1343 }
1344
1345 snd_hda_set_dev_select(codec, pin_nid, dev_id);
1346
1347 if (spec->intel_hsw_fixup) {
1348 conns = spec->num_cvts;
1349 memcpy(per_pin->mux_nids, spec->cvt_nids,
1350 sizeof(hda_nid_t) * conns);
1351 } else {
1352 conns = snd_hda_get_raw_connections(codec, pin_nid,
1353 per_pin->mux_nids,
1354 HDA_MAX_CONNECTIONS);
1355 }
1356
1357 /* all the device entries on the same pin have the same conn list */
1358 per_pin->num_mux_nids = conns;
1359
1360 return 0;
1361}
1362
1363static int hdmi_find_pcm_slot(struct hdmi_spec *spec,
1364 struct hdmi_spec_per_pin *per_pin)
1365{
1366 int i;
1367
1368 for (i = 0; i < spec->pcm_used; i++) {
1369 if (!test_bit(i, &spec->pcm_bitmap))
1370 return i;
1371 }
1372 return -EBUSY;
1373}
1374
1375static void hdmi_attach_hda_pcm(struct hdmi_spec *spec,
1376 struct hdmi_spec_per_pin *per_pin)
1377{
1378 int idx;
1379
1380 /* pcm already be attached to the pin */
1381 if (per_pin->pcm)
1382 return;
1383 idx = hdmi_find_pcm_slot(spec, per_pin);
1384 if (idx == -EBUSY)
1385 return;
1386 per_pin->pcm_idx = idx;
1387 per_pin->pcm = get_hdmi_pcm(spec, idx);
1388 set_bit(idx, &spec->pcm_bitmap);
1389}
1390
1391static void hdmi_detach_hda_pcm(struct hdmi_spec *spec,
1392 struct hdmi_spec_per_pin *per_pin)
1393{
1394 int idx;
1395
1396 /* pcm already be detached from the pin */
1397 if (!per_pin->pcm)
1398 return;
1399 idx = per_pin->pcm_idx;
1400 per_pin->pcm_idx = -1;
1401 per_pin->pcm = NULL;
1402 if (idx >= 0 && idx < spec->pcm_used)
1403 clear_bit(idx, &spec->pcm_bitmap);
1404}
1405
1406static int hdmi_get_pin_cvt_mux(struct hdmi_spec *spec,
1407 struct hdmi_spec_per_pin *per_pin, hda_nid_t cvt_nid)
1408{
1409 int mux_idx;
1410
1411 for (mux_idx = 0; mux_idx < per_pin->num_mux_nids; mux_idx++)
1412 if (per_pin->mux_nids[mux_idx] == cvt_nid)
1413 break;
1414 return mux_idx;
1415}
1416
1417static bool check_non_pcm_per_cvt(struct hda_codec *codec, hda_nid_t cvt_nid);
1418
1419static void hdmi_pcm_setup_pin(struct hdmi_spec *spec,
1420 struct hdmi_spec_per_pin *per_pin)
1421{
1422 struct hda_codec *codec = per_pin->codec;
1423 struct hda_pcm *pcm;
1424 struct hda_pcm_stream *hinfo;
1425 struct snd_pcm_substream *substream;
1426 int mux_idx;
1427 bool non_pcm;
1428
1429 if (per_pin->pcm_idx < 0 || per_pin->pcm_idx >= spec->pcm_used)
1430 return;
1431 pcm = get_pcm_rec(spec, per_pin->pcm_idx);
1432 if (!pcm->pcm)
1433 return;
1434 if (!test_bit(per_pin->pcm_idx, &spec->pcm_in_use))
1435 return;
1436
1437 /* hdmi audio only uses playback and one substream */
1438 hinfo = pcm->stream;
1439 substream = pcm->pcm->streams[0].substream;
1440
1441 per_pin->cvt_nid = hinfo->nid;
1442
1443 mux_idx = hdmi_get_pin_cvt_mux(spec, per_pin, hinfo->nid);
1444 if (mux_idx < per_pin->num_mux_nids) {
1445 snd_hda_set_dev_select(codec, per_pin->pin_nid,
1446 per_pin->dev_id);
1447 snd_hda_codec_write_cache(codec, per_pin->pin_nid, 0,
1448 AC_VERB_SET_CONNECT_SEL,
1449 mux_idx);
1450 }
1451 snd_hda_spdif_ctls_assign(codec, per_pin->pcm_idx, hinfo->nid);
1452
1453 non_pcm = check_non_pcm_per_cvt(codec, hinfo->nid);
1454 if (substream->runtime)
1455 per_pin->channels = substream->runtime->channels;
1456 per_pin->setup = true;
1457 per_pin->mux_idx = mux_idx;
1458
1459 hdmi_setup_audio_infoframe(codec, per_pin, non_pcm);
1460}
1461
1462static void hdmi_pcm_reset_pin(struct hdmi_spec *spec,
1463 struct hdmi_spec_per_pin *per_pin)
1464{
1465 if (per_pin->pcm_idx >= 0 && per_pin->pcm_idx < spec->pcm_used)
1466 snd_hda_spdif_ctls_unassign(per_pin->codec, per_pin->pcm_idx);
1467
1468 per_pin->chmap_set = false;
1469 memset(per_pin->chmap, 0, sizeof(per_pin->chmap));
1470
1471 per_pin->setup = false;
1472 per_pin->channels = 0;
1473}
1474
1475static struct snd_jack *pin_idx_to_pcm_jack(struct hda_codec *codec,
1476 struct hdmi_spec_per_pin *per_pin)
1477{
1478 struct hdmi_spec *spec = codec->spec;
1479
1480 if (per_pin->pcm_idx >= 0)
1481 return spec->pcm_rec[per_pin->pcm_idx].jack;
1482 else
1483 return NULL;
1484}
1485
1486/* update per_pin ELD from the given new ELD;
1487 * setup info frame and notification accordingly
1488 * also notify ELD kctl and report jack status changes
1489 */
1490static void update_eld(struct hda_codec *codec,
1491 struct hdmi_spec_per_pin *per_pin,
1492 struct hdmi_eld *eld,
1493 int repoll)
1494{
1495 struct hdmi_eld *pin_eld = &per_pin->sink_eld;
1496 struct hdmi_spec *spec = codec->spec;
1497 struct snd_jack *pcm_jack;
1498 bool old_eld_valid = pin_eld->eld_valid;
1499 bool eld_changed;
1500 int pcm_idx;
1501
1502 if (eld->eld_valid) {
1503 if (eld->eld_size <= 0 ||
1504 snd_hdmi_parse_eld(codec, &eld->info, eld->eld_buffer,
1505 eld->eld_size) < 0) {
1506 eld->eld_valid = false;
1507 if (repoll) {
1508 schedule_delayed_work(&per_pin->work,
1509 msecs_to_jiffies(300));
1510 return;
1511 }
1512 }
1513 }
1514
1515 if (!eld->eld_valid || eld->eld_size <= 0 || eld->info.sad_count <= 0) {
1516 eld->eld_valid = false;
1517 eld->eld_size = 0;
1518 }
1519
1520 /* for monitor disconnection, save pcm_idx firstly */
1521 pcm_idx = per_pin->pcm_idx;
1522
1523 /*
1524 * pcm_idx >=0 before update_eld() means it is in monitor
1525 * disconnected event. Jack must be fetched before update_eld().
1526 */
1527 pcm_jack = pin_idx_to_pcm_jack(codec, per_pin);
1528
1529 if (!spec->static_pcm_mapping) {
1530 if (eld->eld_valid) {
1531 hdmi_attach_hda_pcm(spec, per_pin);
1532 hdmi_pcm_setup_pin(spec, per_pin);
1533 } else {
1534 hdmi_pcm_reset_pin(spec, per_pin);
1535 hdmi_detach_hda_pcm(spec, per_pin);
1536 }
1537 }
1538
1539 /* if pcm_idx == -1, it means this is in monitor connection event
1540 * we can get the correct pcm_idx now.
1541 */
1542 if (pcm_idx == -1)
1543 pcm_idx = per_pin->pcm_idx;
1544 if (!pcm_jack)
1545 pcm_jack = pin_idx_to_pcm_jack(codec, per_pin);
1546
1547 if (eld->eld_valid)
1548 snd_hdmi_show_eld(codec, &eld->info);
1549
1550 eld_changed = (pin_eld->eld_valid != eld->eld_valid);
1551 eld_changed |= (pin_eld->monitor_present != eld->monitor_present);
1552 if (!eld_changed && eld->eld_valid && pin_eld->eld_valid)
1553 if (pin_eld->eld_size != eld->eld_size ||
1554 memcmp(pin_eld->eld_buffer, eld->eld_buffer,
1555 eld->eld_size) != 0)
1556 eld_changed = true;
1557
1558 if (eld_changed) {
1559 pin_eld->monitor_present = eld->monitor_present;
1560 pin_eld->eld_valid = eld->eld_valid;
1561 pin_eld->eld_size = eld->eld_size;
1562 if (eld->eld_valid)
1563 memcpy(pin_eld->eld_buffer, eld->eld_buffer,
1564 eld->eld_size);
1565 pin_eld->info = eld->info;
1566 }
1567
1568 /*
1569 * Re-setup pin and infoframe. This is needed e.g. when
1570 * - sink is first plugged-in
1571 * - transcoder can change during stream playback on Haswell
1572 * and this can make HW reset converter selection on a pin.
1573 */
1574 if (eld->eld_valid && !old_eld_valid && per_pin->setup) {
1575 pin_cvt_fixup(codec, per_pin, 0);
1576 hdmi_setup_audio_infoframe(codec, per_pin, per_pin->non_pcm);
1577 }
1578
1579 if (eld_changed && pcm_idx >= 0)
1580 snd_ctl_notify(codec->card,
1581 SNDRV_CTL_EVENT_MASK_VALUE |
1582 SNDRV_CTL_EVENT_MASK_INFO,
1583 &get_hdmi_pcm(spec, pcm_idx)->eld_ctl->id);
1584
1585 if (eld_changed && pcm_jack)
1586 snd_jack_report(pcm_jack,
1587 (eld->monitor_present && eld->eld_valid) ?
1588 SND_JACK_AVOUT : 0);
1589}
1590
1591/* update ELD and jack state via HD-audio verbs */
1592static void hdmi_present_sense_via_verbs(struct hdmi_spec_per_pin *per_pin,
1593 int repoll)
1594{
1595 struct hda_codec *codec = per_pin->codec;
1596 struct hdmi_spec *spec = codec->spec;
1597 struct hdmi_eld *eld = &spec->temp_eld;
1598 struct device *dev = hda_codec_dev(codec);
1599 hda_nid_t pin_nid = per_pin->pin_nid;
1600 int dev_id = per_pin->dev_id;
1601 /*
1602 * Always execute a GetPinSense verb here, even when called from
1603 * hdmi_intrinsic_event; for some NVIDIA HW, the unsolicited
1604 * response's PD bit is not the real PD value, but indicates that
1605 * the real PD value changed. An older version of the HD-audio
1606 * specification worked this way. Hence, we just ignore the data in
1607 * the unsolicited response to avoid custom WARs.
1608 */
1609 int present;
1610 int ret;
1611
1612#ifdef CONFIG_PM
1613 if (dev->power.runtime_status == RPM_SUSPENDING)
1614 return;
1615#endif
1616
1617 ret = snd_hda_power_up_pm(codec);
1618 if (ret < 0 && pm_runtime_suspended(dev))
1619 goto out;
1620
1621 present = snd_hda_jack_pin_sense(codec, pin_nid, dev_id);
1622
1623 mutex_lock(&per_pin->lock);
1624 eld->monitor_present = !!(present & AC_PINSENSE_PRESENCE);
1625 if (eld->monitor_present)
1626 eld->eld_valid = !!(present & AC_PINSENSE_ELDV);
1627 else
1628 eld->eld_valid = false;
1629
1630 codec_dbg(codec,
1631 "HDMI status: Codec=%d NID=0x%x Presence_Detect=%d ELD_Valid=%d\n",
1632 codec->addr, pin_nid, eld->monitor_present, eld->eld_valid);
1633
1634 if (eld->eld_valid) {
1635 if (spec->ops.pin_get_eld(codec, pin_nid, dev_id,
1636 eld->eld_buffer, &eld->eld_size) < 0)
1637 eld->eld_valid = false;
1638 }
1639
1640 update_eld(codec, per_pin, eld, repoll);
1641 mutex_unlock(&per_pin->lock);
1642 out:
1643 snd_hda_power_down_pm(codec);
1644}
1645
1646#define I915_SILENT_RATE 48000
1647#define I915_SILENT_CHANNELS 2
1648#define I915_SILENT_FORMAT SNDRV_PCM_FORMAT_S16_LE
1649#define I915_SILENT_FORMAT_BITS 16
1650#define I915_SILENT_FMT_MASK 0xf
1651
1652static void silent_stream_enable_i915(struct hda_codec *codec,
1653 struct hdmi_spec_per_pin *per_pin)
1654{
1655 unsigned int format;
1656
1657 snd_hdac_sync_audio_rate(&codec->core, per_pin->pin_nid,
1658 per_pin->dev_id, I915_SILENT_RATE);
1659
1660 /* trigger silent stream generation in hw */
1661 format = snd_hdac_calc_stream_format(I915_SILENT_RATE, I915_SILENT_CHANNELS,
1662 I915_SILENT_FORMAT, I915_SILENT_FORMAT_BITS, 0);
1663 snd_hda_codec_setup_stream(codec, per_pin->cvt_nid,
1664 I915_SILENT_FMT_MASK, I915_SILENT_FMT_MASK, format);
1665 usleep_range(100, 200);
1666 snd_hda_codec_setup_stream(codec, per_pin->cvt_nid, I915_SILENT_FMT_MASK, 0, format);
1667
1668 per_pin->channels = I915_SILENT_CHANNELS;
1669 hdmi_setup_audio_infoframe(codec, per_pin, per_pin->non_pcm);
1670}
1671
1672static void silent_stream_set_kae(struct hda_codec *codec,
1673 struct hdmi_spec_per_pin *per_pin,
1674 bool enable)
1675{
1676 unsigned int param;
1677
1678 codec_dbg(codec, "HDMI: KAE %d cvt-NID=0x%x\n", enable, per_pin->cvt_nid);
1679
1680 param = snd_hda_codec_read(codec, per_pin->cvt_nid, 0, AC_VERB_GET_DIGI_CONVERT_1, 0);
1681 param = (param >> 16) & 0xff;
1682
1683 if (enable)
1684 param |= AC_DIG3_KAE;
1685 else
1686 param &= ~AC_DIG3_KAE;
1687
1688 snd_hda_codec_write(codec, per_pin->cvt_nid, 0, AC_VERB_SET_DIGI_CONVERT_3, param);
1689}
1690
1691static void silent_stream_enable(struct hda_codec *codec,
1692 struct hdmi_spec_per_pin *per_pin)
1693{
1694 struct hdmi_spec *spec = codec->spec;
1695 struct hdmi_spec_per_cvt *per_cvt;
1696 int cvt_idx, pin_idx, err;
1697 int keep_power = 0;
1698
1699 /*
1700 * Power-up will call hdmi_present_sense, so the PM calls
1701 * have to be done without mutex held.
1702 */
1703
1704 err = snd_hda_power_up_pm(codec);
1705 if (err < 0 && err != -EACCES) {
1706 codec_err(codec,
1707 "Failed to power up codec for silent stream enable ret=[%d]\n", err);
1708 snd_hda_power_down_pm(codec);
1709 return;
1710 }
1711
1712 mutex_lock(&per_pin->lock);
1713
1714 if (per_pin->setup) {
1715 codec_dbg(codec, "hdmi: PCM already open, no silent stream\n");
1716 err = -EBUSY;
1717 goto unlock_out;
1718 }
1719
1720 pin_idx = pin_id_to_pin_index(codec, per_pin->pin_nid, per_pin->dev_id);
1721 err = hdmi_choose_cvt(codec, pin_idx, &cvt_idx, true);
1722 if (err) {
1723 codec_err(codec, "hdmi: no free converter to enable silent mode\n");
1724 goto unlock_out;
1725 }
1726
1727 per_cvt = get_cvt(spec, cvt_idx);
1728 per_cvt->silent_stream = true;
1729 per_pin->cvt_nid = per_cvt->cvt_nid;
1730 per_pin->silent_stream = true;
1731
1732 codec_dbg(codec, "hdmi: enabling silent stream pin-NID=0x%x cvt-NID=0x%x\n",
1733 per_pin->pin_nid, per_cvt->cvt_nid);
1734
1735 snd_hda_set_dev_select(codec, per_pin->pin_nid, per_pin->dev_id);
1736 snd_hda_codec_write_cache(codec, per_pin->pin_nid, 0,
1737 AC_VERB_SET_CONNECT_SEL,
1738 per_pin->mux_idx);
1739
1740 /* configure unused pins to choose other converters */
1741 pin_cvt_fixup(codec, per_pin, 0);
1742
1743 switch (spec->silent_stream_type) {
1744 case SILENT_STREAM_KAE:
1745 silent_stream_enable_i915(codec, per_pin);
1746 silent_stream_set_kae(codec, per_pin, true);
1747 break;
1748 case SILENT_STREAM_I915:
1749 silent_stream_enable_i915(codec, per_pin);
1750 keep_power = 1;
1751 break;
1752 default:
1753 break;
1754 }
1755
1756 unlock_out:
1757 mutex_unlock(&per_pin->lock);
1758
1759 if (err || !keep_power)
1760 snd_hda_power_down_pm(codec);
1761}
1762
1763static void silent_stream_disable(struct hda_codec *codec,
1764 struct hdmi_spec_per_pin *per_pin)
1765{
1766 struct hdmi_spec *spec = codec->spec;
1767 struct hdmi_spec_per_cvt *per_cvt;
1768 int cvt_idx, err;
1769
1770 err = snd_hda_power_up_pm(codec);
1771 if (err < 0 && err != -EACCES) {
1772 codec_err(codec,
1773 "Failed to power up codec for silent stream disable ret=[%d]\n",
1774 err);
1775 snd_hda_power_down_pm(codec);
1776 return;
1777 }
1778
1779 mutex_lock(&per_pin->lock);
1780 if (!per_pin->silent_stream)
1781 goto unlock_out;
1782
1783 codec_dbg(codec, "HDMI: disable silent stream on pin-NID=0x%x cvt-NID=0x%x\n",
1784 per_pin->pin_nid, per_pin->cvt_nid);
1785
1786 cvt_idx = cvt_nid_to_cvt_index(codec, per_pin->cvt_nid);
1787 if (cvt_idx >= 0 && cvt_idx < spec->num_cvts) {
1788 per_cvt = get_cvt(spec, cvt_idx);
1789 per_cvt->silent_stream = false;
1790 }
1791
1792 if (spec->silent_stream_type == SILENT_STREAM_I915) {
1793 /* release ref taken in silent_stream_enable() */
1794 snd_hda_power_down_pm(codec);
1795 } else if (spec->silent_stream_type == SILENT_STREAM_KAE) {
1796 silent_stream_set_kae(codec, per_pin, false);
1797 }
1798
1799 per_pin->cvt_nid = 0;
1800 per_pin->silent_stream = false;
1801
1802 unlock_out:
1803 mutex_unlock(&per_pin->lock);
1804
1805 snd_hda_power_down_pm(codec);
1806}
1807
1808/* update ELD and jack state via audio component */
1809static void sync_eld_via_acomp(struct hda_codec *codec,
1810 struct hdmi_spec_per_pin *per_pin)
1811{
1812 struct hdmi_spec *spec = codec->spec;
1813 struct hdmi_eld *eld = &spec->temp_eld;
1814 bool monitor_prev, monitor_next;
1815
1816 mutex_lock(&per_pin->lock);
1817 eld->monitor_present = false;
1818 monitor_prev = per_pin->sink_eld.monitor_present;
1819 eld->eld_size = snd_hdac_acomp_get_eld(&codec->core, per_pin->pin_nid,
1820 per_pin->dev_id, &eld->monitor_present,
1821 eld->eld_buffer, ELD_MAX_SIZE);
1822 eld->eld_valid = (eld->eld_size > 0);
1823 update_eld(codec, per_pin, eld, 0);
1824 monitor_next = per_pin->sink_eld.monitor_present;
1825 mutex_unlock(&per_pin->lock);
1826
1827 if (spec->silent_stream_type) {
1828 if (!monitor_prev && monitor_next)
1829 silent_stream_enable(codec, per_pin);
1830 else if (monitor_prev && !monitor_next)
1831 silent_stream_disable(codec, per_pin);
1832 }
1833}
1834
1835static void hdmi_present_sense(struct hdmi_spec_per_pin *per_pin, int repoll)
1836{
1837 struct hda_codec *codec = per_pin->codec;
1838
1839 if (!codec_has_acomp(codec))
1840 hdmi_present_sense_via_verbs(per_pin, repoll);
1841 else
1842 sync_eld_via_acomp(codec, per_pin);
1843}
1844
1845static void hdmi_repoll_eld(struct work_struct *work)
1846{
1847 struct hdmi_spec_per_pin *per_pin =
1848 container_of(to_delayed_work(work), struct hdmi_spec_per_pin, work);
1849 struct hda_codec *codec = per_pin->codec;
1850 struct hdmi_spec *spec = codec->spec;
1851 struct hda_jack_tbl *jack;
1852
1853 jack = snd_hda_jack_tbl_get_mst(codec, per_pin->pin_nid,
1854 per_pin->dev_id);
1855 if (jack)
1856 jack->jack_dirty = 1;
1857
1858 if (per_pin->repoll_count++ > 6)
1859 per_pin->repoll_count = 0;
1860
1861 mutex_lock(&spec->pcm_lock);
1862 hdmi_present_sense(per_pin, per_pin->repoll_count);
1863 mutex_unlock(&spec->pcm_lock);
1864}
1865
1866static int hdmi_add_pin(struct hda_codec *codec, hda_nid_t pin_nid)
1867{
1868 struct hdmi_spec *spec = codec->spec;
1869 unsigned int caps, config;
1870 int pin_idx;
1871 struct hdmi_spec_per_pin *per_pin;
1872 int err;
1873 int dev_num, i;
1874
1875 caps = snd_hda_query_pin_caps(codec, pin_nid);
1876 if (!(caps & (AC_PINCAP_HDMI | AC_PINCAP_DP)))
1877 return 0;
1878
1879 /*
1880 * For DP MST audio, Configuration Default is the same for
1881 * all device entries on the same pin
1882 */
1883 config = snd_hda_codec_get_pincfg(codec, pin_nid);
1884 if (get_defcfg_connect(config) == AC_JACK_PORT_NONE &&
1885 !spec->force_connect)
1886 return 0;
1887
1888 /*
1889 * To simplify the implementation, malloc all
1890 * the virtual pins in the initialization statically
1891 */
1892 if (spec->intel_hsw_fixup) {
1893 /*
1894 * On Intel platforms, device entries count returned
1895 * by AC_PAR_DEVLIST_LEN is dynamic, and depends on
1896 * the type of receiver that is connected. Allocate pin
1897 * structures based on worst case.
1898 */
1899 dev_num = spec->dev_num;
1900 } else if (codec->dp_mst) {
1901 dev_num = snd_hda_get_num_devices(codec, pin_nid) + 1;
1902 /*
1903 * spec->dev_num is the maxinum number of device entries
1904 * among all the pins
1905 */
1906 spec->dev_num = (spec->dev_num > dev_num) ?
1907 spec->dev_num : dev_num;
1908 } else {
1909 /*
1910 * If the platform doesn't support DP MST,
1911 * manually set dev_num to 1. This means
1912 * the pin has only one device entry.
1913 */
1914 dev_num = 1;
1915 spec->dev_num = 1;
1916 }
1917
1918 for (i = 0; i < dev_num; i++) {
1919 pin_idx = spec->num_pins;
1920 per_pin = snd_array_new(&spec->pins);
1921
1922 if (!per_pin)
1923 return -ENOMEM;
1924
1925 per_pin->pcm = NULL;
1926 per_pin->pcm_idx = -1;
1927 per_pin->pin_nid = pin_nid;
1928 per_pin->pin_nid_idx = spec->num_nids;
1929 per_pin->dev_id = i;
1930 per_pin->non_pcm = false;
1931 snd_hda_set_dev_select(codec, pin_nid, i);
1932 err = hdmi_read_pin_conn(codec, pin_idx);
1933 if (err < 0)
1934 return err;
1935 if (!is_jack_detectable(codec, pin_nid))
1936 codec_warn(codec, "HDMI: pin NID 0x%x - jack not detectable\n", pin_nid);
1937 spec->num_pins++;
1938 }
1939 spec->num_nids++;
1940
1941 return 0;
1942}
1943
1944static int hdmi_add_cvt(struct hda_codec *codec, hda_nid_t cvt_nid)
1945{
1946 struct hdmi_spec *spec = codec->spec;
1947 struct hdmi_spec_per_cvt *per_cvt;
1948 unsigned int chans;
1949 int err;
1950
1951 chans = get_wcaps(codec, cvt_nid);
1952 chans = get_wcaps_channels(chans);
1953
1954 per_cvt = snd_array_new(&spec->cvts);
1955 if (!per_cvt)
1956 return -ENOMEM;
1957
1958 per_cvt->cvt_nid = cvt_nid;
1959 per_cvt->channels_min = 2;
1960 if (chans <= 16) {
1961 per_cvt->channels_max = chans;
1962 if (chans > spec->chmap.channels_max)
1963 spec->chmap.channels_max = chans;
1964 }
1965
1966 err = snd_hda_query_supported_pcm(codec, cvt_nid,
1967 &per_cvt->rates,
1968 &per_cvt->formats,
1969 &per_cvt->maxbps);
1970 if (err < 0)
1971 return err;
1972
1973 if (spec->num_cvts < ARRAY_SIZE(spec->cvt_nids))
1974 spec->cvt_nids[spec->num_cvts] = cvt_nid;
1975 spec->num_cvts++;
1976
1977 return 0;
1978}
1979
1980static const struct snd_pci_quirk force_connect_list[] = {
1981 SND_PCI_QUIRK(0x103c, 0x870f, "HP", 1),
1982 SND_PCI_QUIRK(0x103c, 0x871a, "HP", 1),
1983 SND_PCI_QUIRK(0x103c, 0x8711, "HP", 1),
1984 SND_PCI_QUIRK(0x103c, 0x8715, "HP", 1),
1985 SND_PCI_QUIRK(0x1462, 0xec94, "MS-7C94", 1),
1986 SND_PCI_QUIRK(0x8086, 0x2081, "Intel NUC 10", 1),
1987 {}
1988};
1989
1990static int hdmi_parse_codec(struct hda_codec *codec)
1991{
1992 struct hdmi_spec *spec = codec->spec;
1993 hda_nid_t start_nid;
1994 unsigned int caps;
1995 int i, nodes;
1996 const struct snd_pci_quirk *q;
1997
1998 nodes = snd_hda_get_sub_nodes(codec, codec->core.afg, &start_nid);
1999 if (!start_nid || nodes < 0) {
2000 codec_warn(codec, "HDMI: failed to get afg sub nodes\n");
2001 return -EINVAL;
2002 }
2003
2004 if (enable_all_pins)
2005 spec->force_connect = true;
2006
2007 q = snd_pci_quirk_lookup(codec->bus->pci, force_connect_list);
2008
2009 if (q && q->value)
2010 spec->force_connect = true;
2011
2012 /*
2013 * hdmi_add_pin() assumes total amount of converters to
2014 * be known, so first discover all converters
2015 */
2016 for (i = 0; i < nodes; i++) {
2017 hda_nid_t nid = start_nid + i;
2018
2019 caps = get_wcaps(codec, nid);
2020
2021 if (!(caps & AC_WCAP_DIGITAL))
2022 continue;
2023
2024 if (get_wcaps_type(caps) == AC_WID_AUD_OUT)
2025 hdmi_add_cvt(codec, nid);
2026 }
2027
2028 /* discover audio pins */
2029 for (i = 0; i < nodes; i++) {
2030 hda_nid_t nid = start_nid + i;
2031
2032 caps = get_wcaps(codec, nid);
2033
2034 if (!(caps & AC_WCAP_DIGITAL))
2035 continue;
2036
2037 if (get_wcaps_type(caps) == AC_WID_PIN)
2038 hdmi_add_pin(codec, nid);
2039 }
2040
2041 return 0;
2042}
2043
2044/*
2045 */
2046static bool check_non_pcm_per_cvt(struct hda_codec *codec, hda_nid_t cvt_nid)
2047{
2048 struct hda_spdif_out *spdif;
2049 bool non_pcm;
2050
2051 mutex_lock(&codec->spdif_mutex);
2052 spdif = snd_hda_spdif_out_of_nid(codec, cvt_nid);
2053 /* Add sanity check to pass klockwork check.
2054 * This should never happen.
2055 */
2056 if (WARN_ON(spdif == NULL)) {
2057 mutex_unlock(&codec->spdif_mutex);
2058 return true;
2059 }
2060 non_pcm = !!(spdif->status & IEC958_AES0_NONAUDIO);
2061 mutex_unlock(&codec->spdif_mutex);
2062 return non_pcm;
2063}
2064
2065/*
2066 * HDMI callbacks
2067 */
2068
2069static int generic_hdmi_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
2070 struct hda_codec *codec,
2071 unsigned int stream_tag,
2072 unsigned int format,
2073 struct snd_pcm_substream *substream)
2074{
2075 hda_nid_t cvt_nid = hinfo->nid;
2076 struct hdmi_spec *spec = codec->spec;
2077 int pin_idx;
2078 struct hdmi_spec_per_pin *per_pin;
2079 struct snd_pcm_runtime *runtime = substream->runtime;
2080 bool non_pcm;
2081 int pinctl, stripe;
2082 int err = 0;
2083
2084 mutex_lock(&spec->pcm_lock);
2085 pin_idx = hinfo_to_pin_index(codec, hinfo);
2086 if (pin_idx < 0) {
2087 /* when pcm is not bound to a pin skip pin setup and return 0
2088 * to make audio playback be ongoing
2089 */
2090 pin_cvt_fixup(codec, NULL, cvt_nid);
2091 snd_hda_codec_setup_stream(codec, cvt_nid,
2092 stream_tag, 0, format);
2093 goto unlock;
2094 }
2095
2096 if (snd_BUG_ON(pin_idx < 0)) {
2097 err = -EINVAL;
2098 goto unlock;
2099 }
2100 per_pin = get_pin(spec, pin_idx);
2101
2102 /* Verify pin:cvt selections to avoid silent audio after S3.
2103 * After S3, the audio driver restores pin:cvt selections
2104 * but this can happen before gfx is ready and such selection
2105 * is overlooked by HW. Thus multiple pins can share a same
2106 * default convertor and mute control will affect each other,
2107 * which can cause a resumed audio playback become silent
2108 * after S3.
2109 */
2110 pin_cvt_fixup(codec, per_pin, 0);
2111
2112 /* Call sync_audio_rate to set the N/CTS/M manually if necessary */
2113 /* Todo: add DP1.2 MST audio support later */
2114 if (codec_has_acomp(codec))
2115 snd_hdac_sync_audio_rate(&codec->core, per_pin->pin_nid,
2116 per_pin->dev_id, runtime->rate);
2117
2118 non_pcm = check_non_pcm_per_cvt(codec, cvt_nid);
2119 mutex_lock(&per_pin->lock);
2120 per_pin->channels = substream->runtime->channels;
2121 per_pin->setup = true;
2122
2123 if (get_wcaps(codec, cvt_nid) & AC_WCAP_STRIPE) {
2124 stripe = snd_hdac_get_stream_stripe_ctl(&codec->bus->core,
2125 substream);
2126 snd_hda_codec_write(codec, cvt_nid, 0,
2127 AC_VERB_SET_STRIPE_CONTROL,
2128 stripe);
2129 }
2130
2131 hdmi_setup_audio_infoframe(codec, per_pin, non_pcm);
2132 mutex_unlock(&per_pin->lock);
2133 if (spec->dyn_pin_out) {
2134 snd_hda_set_dev_select(codec, per_pin->pin_nid,
2135 per_pin->dev_id);
2136 pinctl = snd_hda_codec_read(codec, per_pin->pin_nid, 0,
2137 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
2138 snd_hda_codec_write(codec, per_pin->pin_nid, 0,
2139 AC_VERB_SET_PIN_WIDGET_CONTROL,
2140 pinctl | PIN_OUT);
2141 }
2142
2143 /* snd_hda_set_dev_select() has been called before */
2144 err = spec->ops.setup_stream(codec, cvt_nid, per_pin->pin_nid,
2145 per_pin->dev_id, stream_tag, format);
2146 unlock:
2147 mutex_unlock(&spec->pcm_lock);
2148 return err;
2149}
2150
2151static int generic_hdmi_playback_pcm_cleanup(struct hda_pcm_stream *hinfo,
2152 struct hda_codec *codec,
2153 struct snd_pcm_substream *substream)
2154{
2155 snd_hda_codec_cleanup_stream(codec, hinfo->nid);
2156 return 0;
2157}
2158
2159static int hdmi_pcm_close(struct hda_pcm_stream *hinfo,
2160 struct hda_codec *codec,
2161 struct snd_pcm_substream *substream)
2162{
2163 struct hdmi_spec *spec = codec->spec;
2164 int cvt_idx, pin_idx, pcm_idx;
2165 struct hdmi_spec_per_cvt *per_cvt;
2166 struct hdmi_spec_per_pin *per_pin;
2167 int pinctl;
2168 int err = 0;
2169
2170 mutex_lock(&spec->pcm_lock);
2171 if (hinfo->nid) {
2172 pcm_idx = hinfo_to_pcm_index(codec, hinfo);
2173 if (snd_BUG_ON(pcm_idx < 0)) {
2174 err = -EINVAL;
2175 goto unlock;
2176 }
2177 cvt_idx = cvt_nid_to_cvt_index(codec, hinfo->nid);
2178 if (snd_BUG_ON(cvt_idx < 0)) {
2179 err = -EINVAL;
2180 goto unlock;
2181 }
2182 per_cvt = get_cvt(spec, cvt_idx);
2183 per_cvt->assigned = false;
2184 hinfo->nid = 0;
2185
2186 azx_stream(get_azx_dev(substream))->stripe = 0;
2187
2188 snd_hda_spdif_ctls_unassign(codec, pcm_idx);
2189 clear_bit(pcm_idx, &spec->pcm_in_use);
2190 pin_idx = hinfo_to_pin_index(codec, hinfo);
2191 if (pin_idx < 0)
2192 goto unlock;
2193
2194 if (snd_BUG_ON(pin_idx < 0)) {
2195 err = -EINVAL;
2196 goto unlock;
2197 }
2198 per_pin = get_pin(spec, pin_idx);
2199
2200 if (spec->dyn_pin_out) {
2201 snd_hda_set_dev_select(codec, per_pin->pin_nid,
2202 per_pin->dev_id);
2203 pinctl = snd_hda_codec_read(codec, per_pin->pin_nid, 0,
2204 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
2205 snd_hda_codec_write(codec, per_pin->pin_nid, 0,
2206 AC_VERB_SET_PIN_WIDGET_CONTROL,
2207 pinctl & ~PIN_OUT);
2208 }
2209
2210 mutex_lock(&per_pin->lock);
2211 per_pin->chmap_set = false;
2212 memset(per_pin->chmap, 0, sizeof(per_pin->chmap));
2213
2214 per_pin->setup = false;
2215 per_pin->channels = 0;
2216 mutex_unlock(&per_pin->lock);
2217 }
2218
2219unlock:
2220 mutex_unlock(&spec->pcm_lock);
2221
2222 return err;
2223}
2224
2225static const struct hda_pcm_ops generic_ops = {
2226 .open = hdmi_pcm_open,
2227 .close = hdmi_pcm_close,
2228 .prepare = generic_hdmi_playback_pcm_prepare,
2229 .cleanup = generic_hdmi_playback_pcm_cleanup,
2230};
2231
2232static int hdmi_get_spk_alloc(struct hdac_device *hdac, int pcm_idx)
2233{
2234 struct hda_codec *codec = hdac_to_hda_codec(hdac);
2235 struct hdmi_spec *spec = codec->spec;
2236 struct hdmi_spec_per_pin *per_pin = pcm_idx_to_pin(spec, pcm_idx);
2237
2238 if (!per_pin)
2239 return 0;
2240
2241 return per_pin->sink_eld.info.spk_alloc;
2242}
2243
2244static void hdmi_get_chmap(struct hdac_device *hdac, int pcm_idx,
2245 unsigned char *chmap)
2246{
2247 struct hda_codec *codec = hdac_to_hda_codec(hdac);
2248 struct hdmi_spec *spec = codec->spec;
2249 struct hdmi_spec_per_pin *per_pin = pcm_idx_to_pin(spec, pcm_idx);
2250
2251 /* chmap is already set to 0 in caller */
2252 if (!per_pin)
2253 return;
2254
2255 memcpy(chmap, per_pin->chmap, ARRAY_SIZE(per_pin->chmap));
2256}
2257
2258static void hdmi_set_chmap(struct hdac_device *hdac, int pcm_idx,
2259 unsigned char *chmap, int prepared)
2260{
2261 struct hda_codec *codec = hdac_to_hda_codec(hdac);
2262 struct hdmi_spec *spec = codec->spec;
2263 struct hdmi_spec_per_pin *per_pin = pcm_idx_to_pin(spec, pcm_idx);
2264
2265 if (!per_pin)
2266 return;
2267 mutex_lock(&per_pin->lock);
2268 per_pin->chmap_set = true;
2269 memcpy(per_pin->chmap, chmap, ARRAY_SIZE(per_pin->chmap));
2270 if (prepared)
2271 hdmi_setup_audio_infoframe(codec, per_pin, per_pin->non_pcm);
2272 mutex_unlock(&per_pin->lock);
2273}
2274
2275static bool is_hdmi_pcm_attached(struct hdac_device *hdac, int pcm_idx)
2276{
2277 struct hda_codec *codec = hdac_to_hda_codec(hdac);
2278 struct hdmi_spec *spec = codec->spec;
2279 struct hdmi_spec_per_pin *per_pin = pcm_idx_to_pin(spec, pcm_idx);
2280
2281 return per_pin ? true:false;
2282}
2283
2284static int generic_hdmi_build_pcms(struct hda_codec *codec)
2285{
2286 struct hdmi_spec *spec = codec->spec;
2287 int idx, pcm_num;
2288
2289 /* limit the PCM devices to the codec converters or available PINs */
2290 pcm_num = min(spec->num_cvts, spec->num_pins);
2291 codec_dbg(codec, "hdmi: pcm_num set to %d\n", pcm_num);
2292
2293 for (idx = 0; idx < pcm_num; idx++) {
2294 struct hda_pcm *info;
2295 struct hda_pcm_stream *pstr;
2296
2297 info = snd_hda_codec_pcm_new(codec, "HDMI %d", idx);
2298 if (!info)
2299 return -ENOMEM;
2300
2301 spec->pcm_rec[idx].pcm = info;
2302 spec->pcm_used++;
2303 info->pcm_type = HDA_PCM_TYPE_HDMI;
2304 info->own_chmap = true;
2305
2306 pstr = &info->stream[SNDRV_PCM_STREAM_PLAYBACK];
2307 pstr->substreams = 1;
2308 pstr->ops = generic_ops;
2309 /* pcm number is less than pcm_rec array size */
2310 if (spec->pcm_used >= ARRAY_SIZE(spec->pcm_rec))
2311 break;
2312 /* other pstr fields are set in open */
2313 }
2314
2315 return 0;
2316}
2317
2318static void free_hdmi_jack_priv(struct snd_jack *jack)
2319{
2320 struct hdmi_pcm *pcm = jack->private_data;
2321
2322 pcm->jack = NULL;
2323}
2324
2325static int generic_hdmi_build_jack(struct hda_codec *codec, int pcm_idx)
2326{
2327 char hdmi_str[32] = "HDMI/DP";
2328 struct hdmi_spec *spec = codec->spec;
2329 struct snd_jack *jack;
2330 int pcmdev = get_pcm_rec(spec, pcm_idx)->device;
2331 int err;
2332
2333 if (pcmdev > 0)
2334 sprintf(hdmi_str + strlen(hdmi_str), ",pcm=%d", pcmdev);
2335
2336 err = snd_jack_new(codec->card, hdmi_str, SND_JACK_AVOUT, &jack,
2337 true, false);
2338 if (err < 0)
2339 return err;
2340
2341 spec->pcm_rec[pcm_idx].jack = jack;
2342 jack->private_data = &spec->pcm_rec[pcm_idx];
2343 jack->private_free = free_hdmi_jack_priv;
2344 return 0;
2345}
2346
2347static int generic_hdmi_build_controls(struct hda_codec *codec)
2348{
2349 struct hdmi_spec *spec = codec->spec;
2350 int dev, err;
2351 int pin_idx, pcm_idx;
2352
2353 for (pcm_idx = 0; pcm_idx < spec->pcm_used; pcm_idx++) {
2354 if (!get_pcm_rec(spec, pcm_idx)->pcm) {
2355 /* no PCM: mark this for skipping permanently */
2356 set_bit(pcm_idx, &spec->pcm_bitmap);
2357 continue;
2358 }
2359
2360 err = generic_hdmi_build_jack(codec, pcm_idx);
2361 if (err < 0)
2362 return err;
2363
2364 /* create the spdif for each pcm
2365 * pin will be bound when monitor is connected
2366 */
2367 err = snd_hda_create_dig_out_ctls(codec,
2368 0, spec->cvt_nids[0],
2369 HDA_PCM_TYPE_HDMI);
2370 if (err < 0)
2371 return err;
2372 snd_hda_spdif_ctls_unassign(codec, pcm_idx);
2373
2374 dev = get_pcm_rec(spec, pcm_idx)->device;
2375 if (dev != SNDRV_PCM_INVALID_DEVICE) {
2376 /* add control for ELD Bytes */
2377 err = hdmi_create_eld_ctl(codec, pcm_idx, dev);
2378 if (err < 0)
2379 return err;
2380 }
2381 }
2382
2383 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2384 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2385 struct hdmi_eld *pin_eld = &per_pin->sink_eld;
2386
2387 if (spec->static_pcm_mapping) {
2388 hdmi_attach_hda_pcm(spec, per_pin);
2389 hdmi_pcm_setup_pin(spec, per_pin);
2390 }
2391
2392 pin_eld->eld_valid = false;
2393 hdmi_present_sense(per_pin, 0);
2394 }
2395
2396 /* add channel maps */
2397 for (pcm_idx = 0; pcm_idx < spec->pcm_used; pcm_idx++) {
2398 struct hda_pcm *pcm;
2399
2400 pcm = get_pcm_rec(spec, pcm_idx);
2401 if (!pcm || !pcm->pcm)
2402 break;
2403 err = snd_hdac_add_chmap_ctls(pcm->pcm, pcm_idx, &spec->chmap);
2404 if (err < 0)
2405 return err;
2406 }
2407
2408 return 0;
2409}
2410
2411static int generic_hdmi_init_per_pins(struct hda_codec *codec)
2412{
2413 struct hdmi_spec *spec = codec->spec;
2414 int pin_idx;
2415
2416 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2417 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2418
2419 per_pin->codec = codec;
2420 mutex_init(&per_pin->lock);
2421 INIT_DELAYED_WORK(&per_pin->work, hdmi_repoll_eld);
2422 eld_proc_new(per_pin, pin_idx);
2423 }
2424 return 0;
2425}
2426
2427static int generic_hdmi_init(struct hda_codec *codec)
2428{
2429 struct hdmi_spec *spec = codec->spec;
2430 int pin_idx;
2431
2432 mutex_lock(&spec->bind_lock);
2433 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2434 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2435 hda_nid_t pin_nid = per_pin->pin_nid;
2436 int dev_id = per_pin->dev_id;
2437
2438 snd_hda_set_dev_select(codec, pin_nid, dev_id);
2439 hdmi_init_pin(codec, pin_nid);
2440 if (codec_has_acomp(codec))
2441 continue;
2442 snd_hda_jack_detect_enable_callback_mst(codec, pin_nid, dev_id,
2443 jack_callback);
2444 }
2445 mutex_unlock(&spec->bind_lock);
2446 return 0;
2447}
2448
2449static void hdmi_array_init(struct hdmi_spec *spec, int nums)
2450{
2451 snd_array_init(&spec->pins, sizeof(struct hdmi_spec_per_pin), nums);
2452 snd_array_init(&spec->cvts, sizeof(struct hdmi_spec_per_cvt), nums);
2453}
2454
2455static void hdmi_array_free(struct hdmi_spec *spec)
2456{
2457 snd_array_free(&spec->pins);
2458 snd_array_free(&spec->cvts);
2459}
2460
2461static void generic_spec_free(struct hda_codec *codec)
2462{
2463 struct hdmi_spec *spec = codec->spec;
2464
2465 if (spec) {
2466 hdmi_array_free(spec);
2467 kfree(spec);
2468 codec->spec = NULL;
2469 }
2470 codec->dp_mst = false;
2471}
2472
2473static void generic_hdmi_free(struct hda_codec *codec)
2474{
2475 struct hdmi_spec *spec = codec->spec;
2476 int pin_idx, pcm_idx;
2477
2478 if (spec->acomp_registered) {
2479 snd_hdac_acomp_exit(&codec->bus->core);
2480 } else if (codec_has_acomp(codec)) {
2481 snd_hdac_acomp_register_notifier(&codec->bus->core, NULL);
2482 }
2483 codec->relaxed_resume = 0;
2484
2485 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2486 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2487 cancel_delayed_work_sync(&per_pin->work);
2488 eld_proc_free(per_pin);
2489 }
2490
2491 for (pcm_idx = 0; pcm_idx < spec->pcm_used; pcm_idx++) {
2492 if (spec->pcm_rec[pcm_idx].jack == NULL)
2493 continue;
2494 snd_device_free(codec->card, spec->pcm_rec[pcm_idx].jack);
2495 }
2496
2497 generic_spec_free(codec);
2498}
2499
2500#ifdef CONFIG_PM
2501static int generic_hdmi_suspend(struct hda_codec *codec)
2502{
2503 struct hdmi_spec *spec = codec->spec;
2504 int pin_idx;
2505
2506 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2507 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2508 cancel_delayed_work_sync(&per_pin->work);
2509 }
2510 return 0;
2511}
2512
2513static int generic_hdmi_resume(struct hda_codec *codec)
2514{
2515 struct hdmi_spec *spec = codec->spec;
2516 int pin_idx;
2517
2518 codec->patch_ops.init(codec);
2519 snd_hda_regmap_sync(codec);
2520
2521 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2522 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2523 hdmi_present_sense(per_pin, 1);
2524 }
2525 return 0;
2526}
2527#endif
2528
2529static const struct hda_codec_ops generic_hdmi_patch_ops = {
2530 .init = generic_hdmi_init,
2531 .free = generic_hdmi_free,
2532 .build_pcms = generic_hdmi_build_pcms,
2533 .build_controls = generic_hdmi_build_controls,
2534 .unsol_event = hdmi_unsol_event,
2535#ifdef CONFIG_PM
2536 .suspend = generic_hdmi_suspend,
2537 .resume = generic_hdmi_resume,
2538#endif
2539};
2540
2541static const struct hdmi_ops generic_standard_hdmi_ops = {
2542 .pin_get_eld = hdmi_pin_get_eld,
2543 .pin_setup_infoframe = hdmi_pin_setup_infoframe,
2544 .pin_hbr_setup = hdmi_pin_hbr_setup,
2545 .setup_stream = hdmi_setup_stream,
2546};
2547
2548/* allocate codec->spec and assign/initialize generic parser ops */
2549static int alloc_generic_hdmi(struct hda_codec *codec)
2550{
2551 struct hdmi_spec *spec;
2552
2553 spec = kzalloc(sizeof(*spec), GFP_KERNEL);
2554 if (!spec)
2555 return -ENOMEM;
2556
2557 spec->codec = codec;
2558 spec->ops = generic_standard_hdmi_ops;
2559 spec->dev_num = 1; /* initialize to 1 */
2560 mutex_init(&spec->pcm_lock);
2561 mutex_init(&spec->bind_lock);
2562 snd_hdac_register_chmap_ops(&codec->core, &spec->chmap);
2563
2564 spec->chmap.ops.get_chmap = hdmi_get_chmap;
2565 spec->chmap.ops.set_chmap = hdmi_set_chmap;
2566 spec->chmap.ops.is_pcm_attached = is_hdmi_pcm_attached;
2567 spec->chmap.ops.get_spk_alloc = hdmi_get_spk_alloc;
2568
2569 codec->spec = spec;
2570 hdmi_array_init(spec, 4);
2571
2572 codec->patch_ops = generic_hdmi_patch_ops;
2573
2574 return 0;
2575}
2576
2577/* generic HDMI parser */
2578static int patch_generic_hdmi(struct hda_codec *codec)
2579{
2580 int err;
2581
2582 err = alloc_generic_hdmi(codec);
2583 if (err < 0)
2584 return err;
2585
2586 err = hdmi_parse_codec(codec);
2587 if (err < 0) {
2588 generic_spec_free(codec);
2589 return err;
2590 }
2591
2592 generic_hdmi_init_per_pins(codec);
2593 return 0;
2594}
2595
2596/*
2597 * generic audio component binding
2598 */
2599
2600/* turn on / off the unsol event jack detection dynamically */
2601static void reprogram_jack_detect(struct hda_codec *codec, hda_nid_t nid,
2602 int dev_id, bool use_acomp)
2603{
2604 struct hda_jack_tbl *tbl;
2605
2606 tbl = snd_hda_jack_tbl_get_mst(codec, nid, dev_id);
2607 if (tbl) {
2608 /* clear unsol even if component notifier is used, or re-enable
2609 * if notifier is cleared
2610 */
2611 unsigned int val = use_acomp ? 0 : (AC_USRSP_EN | tbl->tag);
2612 snd_hda_codec_write_cache(codec, nid, 0,
2613 AC_VERB_SET_UNSOLICITED_ENABLE, val);
2614 }
2615}
2616
2617/* set up / clear component notifier dynamically */
2618static void generic_acomp_notifier_set(struct drm_audio_component *acomp,
2619 bool use_acomp)
2620{
2621 struct hdmi_spec *spec;
2622 int i;
2623
2624 spec = container_of(acomp->audio_ops, struct hdmi_spec, drm_audio_ops);
2625 mutex_lock(&spec->bind_lock);
2626 spec->use_acomp_notifier = use_acomp;
2627 spec->codec->relaxed_resume = use_acomp;
2628 spec->codec->bus->keep_power = 0;
2629 /* reprogram each jack detection logic depending on the notifier */
2630 for (i = 0; i < spec->num_pins; i++)
2631 reprogram_jack_detect(spec->codec,
2632 get_pin(spec, i)->pin_nid,
2633 get_pin(spec, i)->dev_id,
2634 use_acomp);
2635 mutex_unlock(&spec->bind_lock);
2636}
2637
2638/* enable / disable the notifier via master bind / unbind */
2639static int generic_acomp_master_bind(struct device *dev,
2640 struct drm_audio_component *acomp)
2641{
2642 generic_acomp_notifier_set(acomp, true);
2643 return 0;
2644}
2645
2646static void generic_acomp_master_unbind(struct device *dev,
2647 struct drm_audio_component *acomp)
2648{
2649 generic_acomp_notifier_set(acomp, false);
2650}
2651
2652/* check whether both HD-audio and DRM PCI devices belong to the same bus */
2653static int match_bound_vga(struct device *dev, int subtype, void *data)
2654{
2655 struct hdac_bus *bus = data;
2656 struct pci_dev *pci, *master;
2657
2658 if (!dev_is_pci(dev) || !dev_is_pci(bus->dev))
2659 return 0;
2660 master = to_pci_dev(bus->dev);
2661 pci = to_pci_dev(dev);
2662 return master->bus == pci->bus;
2663}
2664
2665/* audio component notifier for AMD/Nvidia HDMI codecs */
2666static void generic_acomp_pin_eld_notify(void *audio_ptr, int port, int dev_id)
2667{
2668 struct hda_codec *codec = audio_ptr;
2669 struct hdmi_spec *spec = codec->spec;
2670 hda_nid_t pin_nid = spec->port2pin(codec, port);
2671
2672 if (!pin_nid)
2673 return;
2674 if (get_wcaps_type(get_wcaps(codec, pin_nid)) != AC_WID_PIN)
2675 return;
2676 /* skip notification during system suspend (but not in runtime PM);
2677 * the state will be updated at resume
2678 */
2679 if (codec->core.dev.power.power_state.event == PM_EVENT_SUSPEND)
2680 return;
2681
2682 check_presence_and_report(codec, pin_nid, dev_id);
2683}
2684
2685/* set up the private drm_audio_ops from the template */
2686static void setup_drm_audio_ops(struct hda_codec *codec,
2687 const struct drm_audio_component_audio_ops *ops)
2688{
2689 struct hdmi_spec *spec = codec->spec;
2690
2691 spec->drm_audio_ops.audio_ptr = codec;
2692 /* intel_audio_codec_enable() or intel_audio_codec_disable()
2693 * will call pin_eld_notify with using audio_ptr pointer
2694 * We need make sure audio_ptr is really setup
2695 */
2696 wmb();
2697 spec->drm_audio_ops.pin2port = ops->pin2port;
2698 spec->drm_audio_ops.pin_eld_notify = ops->pin_eld_notify;
2699 spec->drm_audio_ops.master_bind = ops->master_bind;
2700 spec->drm_audio_ops.master_unbind = ops->master_unbind;
2701}
2702
2703/* initialize the generic HDMI audio component */
2704static void generic_acomp_init(struct hda_codec *codec,
2705 const struct drm_audio_component_audio_ops *ops,
2706 int (*port2pin)(struct hda_codec *, int))
2707{
2708 struct hdmi_spec *spec = codec->spec;
2709
2710 if (!enable_acomp) {
2711 codec_info(codec, "audio component disabled by module option\n");
2712 return;
2713 }
2714
2715 spec->port2pin = port2pin;
2716 setup_drm_audio_ops(codec, ops);
2717 if (!snd_hdac_acomp_init(&codec->bus->core, &spec->drm_audio_ops,
2718 match_bound_vga, 0)) {
2719 spec->acomp_registered = true;
2720 }
2721}
2722
2723/*
2724 * Intel codec parsers and helpers
2725 */
2726
2727#define INTEL_GET_VENDOR_VERB 0xf81
2728#define INTEL_SET_VENDOR_VERB 0x781
2729#define INTEL_EN_DP12 0x02 /* enable DP 1.2 features */
2730#define INTEL_EN_ALL_PIN_CVTS 0x01 /* enable 2nd & 3rd pins and convertors */
2731
2732static void intel_haswell_enable_all_pins(struct hda_codec *codec,
2733 bool update_tree)
2734{
2735 unsigned int vendor_param;
2736 struct hdmi_spec *spec = codec->spec;
2737
2738 vendor_param = snd_hda_codec_read(codec, spec->vendor_nid, 0,
2739 INTEL_GET_VENDOR_VERB, 0);
2740 if (vendor_param == -1 || vendor_param & INTEL_EN_ALL_PIN_CVTS)
2741 return;
2742
2743 vendor_param |= INTEL_EN_ALL_PIN_CVTS;
2744 vendor_param = snd_hda_codec_read(codec, spec->vendor_nid, 0,
2745 INTEL_SET_VENDOR_VERB, vendor_param);
2746 if (vendor_param == -1)
2747 return;
2748
2749 if (update_tree)
2750 snd_hda_codec_update_widgets(codec);
2751}
2752
2753static void intel_haswell_fixup_enable_dp12(struct hda_codec *codec)
2754{
2755 unsigned int vendor_param;
2756 struct hdmi_spec *spec = codec->spec;
2757
2758 vendor_param = snd_hda_codec_read(codec, spec->vendor_nid, 0,
2759 INTEL_GET_VENDOR_VERB, 0);
2760 if (vendor_param == -1 || vendor_param & INTEL_EN_DP12)
2761 return;
2762
2763 /* enable DP1.2 mode */
2764 vendor_param |= INTEL_EN_DP12;
2765 snd_hdac_regmap_add_vendor_verb(&codec->core, INTEL_SET_VENDOR_VERB);
2766 snd_hda_codec_write_cache(codec, spec->vendor_nid, 0,
2767 INTEL_SET_VENDOR_VERB, vendor_param);
2768}
2769
2770/* Haswell needs to re-issue the vendor-specific verbs before turning to D0.
2771 * Otherwise you may get severe h/w communication errors.
2772 */
2773static void haswell_set_power_state(struct hda_codec *codec, hda_nid_t fg,
2774 unsigned int power_state)
2775{
2776 if (power_state == AC_PWRST_D0) {
2777 intel_haswell_enable_all_pins(codec, false);
2778 intel_haswell_fixup_enable_dp12(codec);
2779 }
2780
2781 snd_hda_codec_read(codec, fg, 0, AC_VERB_SET_POWER_STATE, power_state);
2782 snd_hda_codec_set_power_to_all(codec, fg, power_state);
2783}
2784
2785/* There is a fixed mapping between audio pin node and display port.
2786 * on SNB, IVY, HSW, BSW, SKL, BXT, KBL:
2787 * Pin Widget 5 - PORT B (port = 1 in i915 driver)
2788 * Pin Widget 6 - PORT C (port = 2 in i915 driver)
2789 * Pin Widget 7 - PORT D (port = 3 in i915 driver)
2790 *
2791 * on VLV, ILK:
2792 * Pin Widget 4 - PORT B (port = 1 in i915 driver)
2793 * Pin Widget 5 - PORT C (port = 2 in i915 driver)
2794 * Pin Widget 6 - PORT D (port = 3 in i915 driver)
2795 */
2796static int intel_base_nid(struct hda_codec *codec)
2797{
2798 switch (codec->core.vendor_id) {
2799 case 0x80860054: /* ILK */
2800 case 0x80862804: /* ILK */
2801 case 0x80862882: /* VLV */
2802 return 4;
2803 default:
2804 return 5;
2805 }
2806}
2807
2808static int intel_pin2port(void *audio_ptr, int pin_nid)
2809{
2810 struct hda_codec *codec = audio_ptr;
2811 struct hdmi_spec *spec = codec->spec;
2812 int base_nid, i;
2813
2814 if (!spec->port_num) {
2815 base_nid = intel_base_nid(codec);
2816 if (WARN_ON(pin_nid < base_nid || pin_nid >= base_nid + 3))
2817 return -1;
2818 return pin_nid - base_nid + 1;
2819 }
2820
2821 /*
2822 * looking for the pin number in the mapping table and return
2823 * the index which indicate the port number
2824 */
2825 for (i = 0; i < spec->port_num; i++) {
2826 if (pin_nid == spec->port_map[i])
2827 return i;
2828 }
2829
2830 codec_info(codec, "Can't find the HDMI/DP port for pin NID 0x%x\n", pin_nid);
2831 return -1;
2832}
2833
2834static int intel_port2pin(struct hda_codec *codec, int port)
2835{
2836 struct hdmi_spec *spec = codec->spec;
2837
2838 if (!spec->port_num) {
2839 /* we assume only from port-B to port-D */
2840 if (port < 1 || port > 3)
2841 return 0;
2842 return port + intel_base_nid(codec) - 1;
2843 }
2844
2845 if (port < 0 || port >= spec->port_num)
2846 return 0;
2847 return spec->port_map[port];
2848}
2849
2850static void intel_pin_eld_notify(void *audio_ptr, int port, int pipe)
2851{
2852 struct hda_codec *codec = audio_ptr;
2853 int pin_nid;
2854 int dev_id = pipe;
2855
2856 pin_nid = intel_port2pin(codec, port);
2857 if (!pin_nid)
2858 return;
2859 /* skip notification during system suspend (but not in runtime PM);
2860 * the state will be updated at resume
2861 */
2862 if (codec->core.dev.power.power_state.event == PM_EVENT_SUSPEND)
2863 return;
2864
2865 snd_hdac_i915_set_bclk(&codec->bus->core);
2866 check_presence_and_report(codec, pin_nid, dev_id);
2867}
2868
2869static const struct drm_audio_component_audio_ops intel_audio_ops = {
2870 .pin2port = intel_pin2port,
2871 .pin_eld_notify = intel_pin_eld_notify,
2872};
2873
2874/* register i915 component pin_eld_notify callback */
2875static void register_i915_notifier(struct hda_codec *codec)
2876{
2877 struct hdmi_spec *spec = codec->spec;
2878
2879 spec->use_acomp_notifier = true;
2880 spec->port2pin = intel_port2pin;
2881 setup_drm_audio_ops(codec, &intel_audio_ops);
2882 snd_hdac_acomp_register_notifier(&codec->bus->core,
2883 &spec->drm_audio_ops);
2884 /* no need for forcible resume for jack check thanks to notifier */
2885 codec->relaxed_resume = 1;
2886}
2887
2888/* setup_stream ops override for HSW+ */
2889static int i915_hsw_setup_stream(struct hda_codec *codec, hda_nid_t cvt_nid,
2890 hda_nid_t pin_nid, int dev_id, u32 stream_tag,
2891 int format)
2892{
2893 struct hdmi_spec *spec = codec->spec;
2894 int pin_idx = pin_id_to_pin_index(codec, pin_nid, dev_id);
2895 struct hdmi_spec_per_pin *per_pin;
2896 int res;
2897
2898 if (pin_idx < 0)
2899 per_pin = NULL;
2900 else
2901 per_pin = get_pin(spec, pin_idx);
2902
2903 haswell_verify_D0(codec, cvt_nid, pin_nid);
2904
2905 if (spec->silent_stream_type == SILENT_STREAM_KAE && per_pin && per_pin->silent_stream) {
2906 silent_stream_set_kae(codec, per_pin, false);
2907 /* wait for pending transfers in codec to clear */
2908 usleep_range(100, 200);
2909 }
2910
2911 res = hdmi_setup_stream(codec, cvt_nid, pin_nid, dev_id,
2912 stream_tag, format);
2913
2914 if (spec->silent_stream_type == SILENT_STREAM_KAE && per_pin && per_pin->silent_stream) {
2915 usleep_range(100, 200);
2916 silent_stream_set_kae(codec, per_pin, true);
2917 }
2918
2919 return res;
2920}
2921
2922/* pin_cvt_fixup ops override for HSW+ and VLV+ */
2923static void i915_pin_cvt_fixup(struct hda_codec *codec,
2924 struct hdmi_spec_per_pin *per_pin,
2925 hda_nid_t cvt_nid)
2926{
2927 if (per_pin) {
2928 haswell_verify_D0(codec, per_pin->cvt_nid, per_pin->pin_nid);
2929 snd_hda_set_dev_select(codec, per_pin->pin_nid,
2930 per_pin->dev_id);
2931 intel_verify_pin_cvt_connect(codec, per_pin);
2932 intel_not_share_assigned_cvt(codec, per_pin->pin_nid,
2933 per_pin->dev_id, per_pin->mux_idx);
2934 } else {
2935 intel_not_share_assigned_cvt_nid(codec, 0, 0, cvt_nid);
2936 }
2937}
2938
2939#ifdef CONFIG_PM
2940static int i915_adlp_hdmi_suspend(struct hda_codec *codec)
2941{
2942 struct hdmi_spec *spec = codec->spec;
2943 bool silent_streams = false;
2944 int pin_idx, res;
2945
2946 res = generic_hdmi_suspend(codec);
2947
2948 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2949 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2950
2951 if (per_pin->silent_stream) {
2952 silent_streams = true;
2953 break;
2954 }
2955 }
2956
2957 if (silent_streams && spec->silent_stream_type == SILENT_STREAM_KAE) {
2958 /*
2959 * stream-id should remain programmed when codec goes
2960 * to runtime suspend
2961 */
2962 codec->no_stream_clean_at_suspend = 1;
2963
2964 /*
2965 * the system might go to S3, in which case keep-alive
2966 * must be reprogrammed upon resume
2967 */
2968 codec->forced_resume = 1;
2969
2970 codec_dbg(codec, "HDMI: KAE active at suspend\n");
2971 } else {
2972 codec->no_stream_clean_at_suspend = 0;
2973 codec->forced_resume = 0;
2974 }
2975
2976 return res;
2977}
2978
2979static int i915_adlp_hdmi_resume(struct hda_codec *codec)
2980{
2981 struct hdmi_spec *spec = codec->spec;
2982 int pin_idx, res;
2983
2984 res = generic_hdmi_resume(codec);
2985
2986 /* KAE not programmed at suspend, nothing to do here */
2987 if (!codec->no_stream_clean_at_suspend)
2988 return res;
2989
2990 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2991 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2992
2993 /*
2994 * If system was in suspend with monitor connected,
2995 * the codec setting may have been lost. Re-enable
2996 * keep-alive.
2997 */
2998 if (per_pin->silent_stream) {
2999 unsigned int param;
3000
3001 param = snd_hda_codec_read(codec, per_pin->cvt_nid, 0,
3002 AC_VERB_GET_CONV, 0);
3003 if (!param) {
3004 codec_dbg(codec, "HDMI: KAE: restore stream id\n");
3005 silent_stream_enable_i915(codec, per_pin);
3006 }
3007
3008 param = snd_hda_codec_read(codec, per_pin->cvt_nid, 0,
3009 AC_VERB_GET_DIGI_CONVERT_1, 0);
3010 if (!(param & (AC_DIG3_KAE << 16))) {
3011 codec_dbg(codec, "HDMI: KAE: restore DIG3_KAE\n");
3012 silent_stream_set_kae(codec, per_pin, true);
3013 }
3014 }
3015 }
3016
3017 return res;
3018}
3019#endif
3020
3021/* precondition and allocation for Intel codecs */
3022static int alloc_intel_hdmi(struct hda_codec *codec)
3023{
3024 int err;
3025
3026 /* requires i915 binding */
3027 if (!codec->bus->core.audio_component) {
3028 codec_info(codec, "No i915 binding for Intel HDMI/DP codec\n");
3029 /* set probe_id here to prevent generic fallback binding */
3030 codec->probe_id = HDA_CODEC_ID_SKIP_PROBE;
3031 return -ENODEV;
3032 }
3033
3034 err = alloc_generic_hdmi(codec);
3035 if (err < 0)
3036 return err;
3037 /* no need to handle unsol events */
3038 codec->patch_ops.unsol_event = NULL;
3039 return 0;
3040}
3041
3042/* parse and post-process for Intel codecs */
3043static int parse_intel_hdmi(struct hda_codec *codec)
3044{
3045 int err, retries = 3;
3046
3047 do {
3048 err = hdmi_parse_codec(codec);
3049 } while (err < 0 && retries--);
3050
3051 if (err < 0) {
3052 generic_spec_free(codec);
3053 return err;
3054 }
3055
3056 generic_hdmi_init_per_pins(codec);
3057 register_i915_notifier(codec);
3058 return 0;
3059}
3060
3061/* Intel Haswell and onwards; audio component with eld notifier */
3062static int intel_hsw_common_init(struct hda_codec *codec, hda_nid_t vendor_nid,
3063 const int *port_map, int port_num, int dev_num,
3064 bool send_silent_stream)
3065{
3066 struct hdmi_spec *spec;
3067 int err;
3068
3069 err = alloc_intel_hdmi(codec);
3070 if (err < 0)
3071 return err;
3072 spec = codec->spec;
3073 codec->dp_mst = true;
3074 spec->vendor_nid = vendor_nid;
3075 spec->port_map = port_map;
3076 spec->port_num = port_num;
3077 spec->intel_hsw_fixup = true;
3078 spec->dev_num = dev_num;
3079
3080 intel_haswell_enable_all_pins(codec, true);
3081 intel_haswell_fixup_enable_dp12(codec);
3082
3083 codec->display_power_control = 1;
3084
3085 codec->patch_ops.set_power_state = haswell_set_power_state;
3086 codec->depop_delay = 0;
3087 codec->auto_runtime_pm = 1;
3088
3089 spec->ops.setup_stream = i915_hsw_setup_stream;
3090 spec->ops.pin_cvt_fixup = i915_pin_cvt_fixup;
3091
3092 /*
3093 * Enable silent stream feature, if it is enabled via
3094 * module param or Kconfig option
3095 */
3096 if (send_silent_stream)
3097 spec->silent_stream_type = SILENT_STREAM_I915;
3098
3099 return parse_intel_hdmi(codec);
3100}
3101
3102static int patch_i915_hsw_hdmi(struct hda_codec *codec)
3103{
3104 return intel_hsw_common_init(codec, 0x08, NULL, 0, 3,
3105 enable_silent_stream);
3106}
3107
3108static int patch_i915_glk_hdmi(struct hda_codec *codec)
3109{
3110 /*
3111 * Silent stream calls audio component .get_power() from
3112 * .pin_eld_notify(). On GLK this will deadlock in i915 due
3113 * to the audio vs. CDCLK workaround.
3114 */
3115 return intel_hsw_common_init(codec, 0x0b, NULL, 0, 3, false);
3116}
3117
3118static int patch_i915_icl_hdmi(struct hda_codec *codec)
3119{
3120 /*
3121 * pin to port mapping table where the value indicate the pin number and
3122 * the index indicate the port number.
3123 */
3124 static const int map[] = {0x0, 0x4, 0x6, 0x8, 0xa, 0xb};
3125
3126 return intel_hsw_common_init(codec, 0x02, map, ARRAY_SIZE(map), 3,
3127 enable_silent_stream);
3128}
3129
3130static int patch_i915_tgl_hdmi(struct hda_codec *codec)
3131{
3132 /*
3133 * pin to port mapping table where the value indicate the pin number and
3134 * the index indicate the port number.
3135 */
3136 static const int map[] = {0x4, 0x6, 0x8, 0xa, 0xb, 0xc, 0xd, 0xe, 0xf};
3137
3138 return intel_hsw_common_init(codec, 0x02, map, ARRAY_SIZE(map), 4,
3139 enable_silent_stream);
3140}
3141
3142static int patch_i915_adlp_hdmi(struct hda_codec *codec)
3143{
3144 struct hdmi_spec *spec;
3145 int res;
3146
3147 res = patch_i915_tgl_hdmi(codec);
3148 if (!res) {
3149 spec = codec->spec;
3150
3151 if (spec->silent_stream_type) {
3152 spec->silent_stream_type = SILENT_STREAM_KAE;
3153
3154#ifdef CONFIG_PM
3155 codec->patch_ops.resume = i915_adlp_hdmi_resume;
3156 codec->patch_ops.suspend = i915_adlp_hdmi_suspend;
3157#endif
3158 }
3159 }
3160
3161 return res;
3162}
3163
3164/* Intel Baytrail and Braswell; with eld notifier */
3165static int patch_i915_byt_hdmi(struct hda_codec *codec)
3166{
3167 struct hdmi_spec *spec;
3168 int err;
3169
3170 err = alloc_intel_hdmi(codec);
3171 if (err < 0)
3172 return err;
3173 spec = codec->spec;
3174
3175 /* For Valleyview/Cherryview, only the display codec is in the display
3176 * power well and can use link_power ops to request/release the power.
3177 */
3178 codec->display_power_control = 1;
3179
3180 codec->depop_delay = 0;
3181 codec->auto_runtime_pm = 1;
3182
3183 spec->ops.pin_cvt_fixup = i915_pin_cvt_fixup;
3184
3185 return parse_intel_hdmi(codec);
3186}
3187
3188/* Intel IronLake, SandyBridge and IvyBridge; with eld notifier */
3189static int patch_i915_cpt_hdmi(struct hda_codec *codec)
3190{
3191 int err;
3192
3193 err = alloc_intel_hdmi(codec);
3194 if (err < 0)
3195 return err;
3196 return parse_intel_hdmi(codec);
3197}
3198
3199/*
3200 * Shared non-generic implementations
3201 */
3202
3203static int simple_playback_build_pcms(struct hda_codec *codec)
3204{
3205 struct hdmi_spec *spec = codec->spec;
3206 struct hda_pcm *info;
3207 unsigned int chans;
3208 struct hda_pcm_stream *pstr;
3209 struct hdmi_spec_per_cvt *per_cvt;
3210
3211 per_cvt = get_cvt(spec, 0);
3212 chans = get_wcaps(codec, per_cvt->cvt_nid);
3213 chans = get_wcaps_channels(chans);
3214
3215 info = snd_hda_codec_pcm_new(codec, "HDMI 0");
3216 if (!info)
3217 return -ENOMEM;
3218 spec->pcm_rec[0].pcm = info;
3219 info->pcm_type = HDA_PCM_TYPE_HDMI;
3220 pstr = &info->stream[SNDRV_PCM_STREAM_PLAYBACK];
3221 *pstr = spec->pcm_playback;
3222 pstr->nid = per_cvt->cvt_nid;
3223 if (pstr->channels_max <= 2 && chans && chans <= 16)
3224 pstr->channels_max = chans;
3225
3226 return 0;
3227}
3228
3229/* unsolicited event for jack sensing */
3230static void simple_hdmi_unsol_event(struct hda_codec *codec,
3231 unsigned int res)
3232{
3233 snd_hda_jack_set_dirty_all(codec);
3234 snd_hda_jack_report_sync(codec);
3235}
3236
3237/* generic_hdmi_build_jack can be used for simple_hdmi, too,
3238 * as long as spec->pins[] is set correctly
3239 */
3240#define simple_hdmi_build_jack generic_hdmi_build_jack
3241
3242static int simple_playback_build_controls(struct hda_codec *codec)
3243{
3244 struct hdmi_spec *spec = codec->spec;
3245 struct hdmi_spec_per_cvt *per_cvt;
3246 int err;
3247
3248 per_cvt = get_cvt(spec, 0);
3249 err = snd_hda_create_dig_out_ctls(codec, per_cvt->cvt_nid,
3250 per_cvt->cvt_nid,
3251 HDA_PCM_TYPE_HDMI);
3252 if (err < 0)
3253 return err;
3254 return simple_hdmi_build_jack(codec, 0);
3255}
3256
3257static int simple_playback_init(struct hda_codec *codec)
3258{
3259 struct hdmi_spec *spec = codec->spec;
3260 struct hdmi_spec_per_pin *per_pin = get_pin(spec, 0);
3261 hda_nid_t pin = per_pin->pin_nid;
3262
3263 snd_hda_codec_write(codec, pin, 0,
3264 AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT);
3265 /* some codecs require to unmute the pin */
3266 if (get_wcaps(codec, pin) & AC_WCAP_OUT_AMP)
3267 snd_hda_codec_write(codec, pin, 0, AC_VERB_SET_AMP_GAIN_MUTE,
3268 AMP_OUT_UNMUTE);
3269 snd_hda_jack_detect_enable(codec, pin, per_pin->dev_id);
3270 return 0;
3271}
3272
3273static void simple_playback_free(struct hda_codec *codec)
3274{
3275 struct hdmi_spec *spec = codec->spec;
3276
3277 hdmi_array_free(spec);
3278 kfree(spec);
3279}
3280
3281/*
3282 * Nvidia specific implementations
3283 */
3284
3285#define Nv_VERB_SET_Channel_Allocation 0xF79
3286#define Nv_VERB_SET_Info_Frame_Checksum 0xF7A
3287#define Nv_VERB_SET_Audio_Protection_On 0xF98
3288#define Nv_VERB_SET_Audio_Protection_Off 0xF99
3289
3290#define nvhdmi_master_con_nid_7x 0x04
3291#define nvhdmi_master_pin_nid_7x 0x05
3292
3293static const hda_nid_t nvhdmi_con_nids_7x[4] = {
3294 /*front, rear, clfe, rear_surr */
3295 0x6, 0x8, 0xa, 0xc,
3296};
3297
3298static const struct hda_verb nvhdmi_basic_init_7x_2ch[] = {
3299 /* set audio protect on */
3300 { 0x1, Nv_VERB_SET_Audio_Protection_On, 0x1},
3301 /* enable digital output on pin widget */
3302 { 0x5, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
3303 {} /* terminator */
3304};
3305
3306static const struct hda_verb nvhdmi_basic_init_7x_8ch[] = {
3307 /* set audio protect on */
3308 { 0x1, Nv_VERB_SET_Audio_Protection_On, 0x1},
3309 /* enable digital output on pin widget */
3310 { 0x5, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
3311 { 0x7, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
3312 { 0x9, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
3313 { 0xb, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
3314 { 0xd, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
3315 {} /* terminator */
3316};
3317
3318#ifdef LIMITED_RATE_FMT_SUPPORT
3319/* support only the safe format and rate */
3320#define SUPPORTED_RATES SNDRV_PCM_RATE_48000
3321#define SUPPORTED_MAXBPS 16
3322#define SUPPORTED_FORMATS SNDRV_PCM_FMTBIT_S16_LE
3323#else
3324/* support all rates and formats */
3325#define SUPPORTED_RATES \
3326 (SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000 |\
3327 SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |\
3328 SNDRV_PCM_RATE_192000)
3329#define SUPPORTED_MAXBPS 24
3330#define SUPPORTED_FORMATS \
3331 (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE)
3332#endif
3333
3334static int nvhdmi_7x_init_2ch(struct hda_codec *codec)
3335{
3336 snd_hda_sequence_write(codec, nvhdmi_basic_init_7x_2ch);
3337 return 0;
3338}
3339
3340static int nvhdmi_7x_init_8ch(struct hda_codec *codec)
3341{
3342 snd_hda_sequence_write(codec, nvhdmi_basic_init_7x_8ch);
3343 return 0;
3344}
3345
3346static const unsigned int channels_2_6_8[] = {
3347 2, 6, 8
3348};
3349
3350static const unsigned int channels_2_8[] = {
3351 2, 8
3352};
3353
3354static const struct snd_pcm_hw_constraint_list hw_constraints_2_6_8_channels = {
3355 .count = ARRAY_SIZE(channels_2_6_8),
3356 .list = channels_2_6_8,
3357 .mask = 0,
3358};
3359
3360static const struct snd_pcm_hw_constraint_list hw_constraints_2_8_channels = {
3361 .count = ARRAY_SIZE(channels_2_8),
3362 .list = channels_2_8,
3363 .mask = 0,
3364};
3365
3366static int simple_playback_pcm_open(struct hda_pcm_stream *hinfo,
3367 struct hda_codec *codec,
3368 struct snd_pcm_substream *substream)
3369{
3370 struct hdmi_spec *spec = codec->spec;
3371 const struct snd_pcm_hw_constraint_list *hw_constraints_channels = NULL;
3372
3373 switch (codec->preset->vendor_id) {
3374 case 0x10de0002:
3375 case 0x10de0003:
3376 case 0x10de0005:
3377 case 0x10de0006:
3378 hw_constraints_channels = &hw_constraints_2_8_channels;
3379 break;
3380 case 0x10de0007:
3381 hw_constraints_channels = &hw_constraints_2_6_8_channels;
3382 break;
3383 default:
3384 break;
3385 }
3386
3387 if (hw_constraints_channels != NULL) {
3388 snd_pcm_hw_constraint_list(substream->runtime, 0,
3389 SNDRV_PCM_HW_PARAM_CHANNELS,
3390 hw_constraints_channels);
3391 } else {
3392 snd_pcm_hw_constraint_step(substream->runtime, 0,
3393 SNDRV_PCM_HW_PARAM_CHANNELS, 2);
3394 }
3395
3396 return snd_hda_multi_out_dig_open(codec, &spec->multiout);
3397}
3398
3399static int simple_playback_pcm_close(struct hda_pcm_stream *hinfo,
3400 struct hda_codec *codec,
3401 struct snd_pcm_substream *substream)
3402{
3403 struct hdmi_spec *spec = codec->spec;
3404 return snd_hda_multi_out_dig_close(codec, &spec->multiout);
3405}
3406
3407static int simple_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
3408 struct hda_codec *codec,
3409 unsigned int stream_tag,
3410 unsigned int format,
3411 struct snd_pcm_substream *substream)
3412{
3413 struct hdmi_spec *spec = codec->spec;
3414 return snd_hda_multi_out_dig_prepare(codec, &spec->multiout,
3415 stream_tag, format, substream);
3416}
3417
3418static const struct hda_pcm_stream simple_pcm_playback = {
3419 .substreams = 1,
3420 .channels_min = 2,
3421 .channels_max = 2,
3422 .ops = {
3423 .open = simple_playback_pcm_open,
3424 .close = simple_playback_pcm_close,
3425 .prepare = simple_playback_pcm_prepare
3426 },
3427};
3428
3429static const struct hda_codec_ops simple_hdmi_patch_ops = {
3430 .build_controls = simple_playback_build_controls,
3431 .build_pcms = simple_playback_build_pcms,
3432 .init = simple_playback_init,
3433 .free = simple_playback_free,
3434 .unsol_event = simple_hdmi_unsol_event,
3435};
3436
3437static int patch_simple_hdmi(struct hda_codec *codec,
3438 hda_nid_t cvt_nid, hda_nid_t pin_nid)
3439{
3440 struct hdmi_spec *spec;
3441 struct hdmi_spec_per_cvt *per_cvt;
3442 struct hdmi_spec_per_pin *per_pin;
3443
3444 spec = kzalloc(sizeof(*spec), GFP_KERNEL);
3445 if (!spec)
3446 return -ENOMEM;
3447
3448 spec->codec = codec;
3449 codec->spec = spec;
3450 hdmi_array_init(spec, 1);
3451
3452 spec->multiout.num_dacs = 0; /* no analog */
3453 spec->multiout.max_channels = 2;
3454 spec->multiout.dig_out_nid = cvt_nid;
3455 spec->num_cvts = 1;
3456 spec->num_pins = 1;
3457 per_pin = snd_array_new(&spec->pins);
3458 per_cvt = snd_array_new(&spec->cvts);
3459 if (!per_pin || !per_cvt) {
3460 simple_playback_free(codec);
3461 return -ENOMEM;
3462 }
3463 per_cvt->cvt_nid = cvt_nid;
3464 per_pin->pin_nid = pin_nid;
3465 spec->pcm_playback = simple_pcm_playback;
3466
3467 codec->patch_ops = simple_hdmi_patch_ops;
3468
3469 return 0;
3470}
3471
3472static void nvhdmi_8ch_7x_set_info_frame_parameters(struct hda_codec *codec,
3473 int channels)
3474{
3475 unsigned int chanmask;
3476 int chan = channels ? (channels - 1) : 1;
3477
3478 switch (channels) {
3479 default:
3480 case 0:
3481 case 2:
3482 chanmask = 0x00;
3483 break;
3484 case 4:
3485 chanmask = 0x08;
3486 break;
3487 case 6:
3488 chanmask = 0x0b;
3489 break;
3490 case 8:
3491 chanmask = 0x13;
3492 break;
3493 }
3494
3495 /* Set the audio infoframe channel allocation and checksum fields. The
3496 * channel count is computed implicitly by the hardware. */
3497 snd_hda_codec_write(codec, 0x1, 0,
3498 Nv_VERB_SET_Channel_Allocation, chanmask);
3499
3500 snd_hda_codec_write(codec, 0x1, 0,
3501 Nv_VERB_SET_Info_Frame_Checksum,
3502 (0x71 - chan - chanmask));
3503}
3504
3505static int nvhdmi_8ch_7x_pcm_close(struct hda_pcm_stream *hinfo,
3506 struct hda_codec *codec,
3507 struct snd_pcm_substream *substream)
3508{
3509 struct hdmi_spec *spec = codec->spec;
3510 int i;
3511
3512 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x,
3513 0, AC_VERB_SET_CHANNEL_STREAMID, 0);
3514 for (i = 0; i < 4; i++) {
3515 /* set the stream id */
3516 snd_hda_codec_write(codec, nvhdmi_con_nids_7x[i], 0,
3517 AC_VERB_SET_CHANNEL_STREAMID, 0);
3518 /* set the stream format */
3519 snd_hda_codec_write(codec, nvhdmi_con_nids_7x[i], 0,
3520 AC_VERB_SET_STREAM_FORMAT, 0);
3521 }
3522
3523 /* The audio hardware sends a channel count of 0x7 (8ch) when all the
3524 * streams are disabled. */
3525 nvhdmi_8ch_7x_set_info_frame_parameters(codec, 8);
3526
3527 return snd_hda_multi_out_dig_close(codec, &spec->multiout);
3528}
3529
3530static int nvhdmi_8ch_7x_pcm_prepare(struct hda_pcm_stream *hinfo,
3531 struct hda_codec *codec,
3532 unsigned int stream_tag,
3533 unsigned int format,
3534 struct snd_pcm_substream *substream)
3535{
3536 int chs;
3537 unsigned int dataDCC2, channel_id;
3538 int i;
3539 struct hdmi_spec *spec = codec->spec;
3540 struct hda_spdif_out *spdif;
3541 struct hdmi_spec_per_cvt *per_cvt;
3542
3543 mutex_lock(&codec->spdif_mutex);
3544 per_cvt = get_cvt(spec, 0);
3545 spdif = snd_hda_spdif_out_of_nid(codec, per_cvt->cvt_nid);
3546
3547 chs = substream->runtime->channels;
3548
3549 dataDCC2 = 0x2;
3550
3551 /* turn off SPDIF once; otherwise the IEC958 bits won't be updated */
3552 if (codec->spdif_status_reset && (spdif->ctls & AC_DIG1_ENABLE))
3553 snd_hda_codec_write(codec,
3554 nvhdmi_master_con_nid_7x,
3555 0,
3556 AC_VERB_SET_DIGI_CONVERT_1,
3557 spdif->ctls & ~AC_DIG1_ENABLE & 0xff);
3558
3559 /* set the stream id */
3560 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, 0,
3561 AC_VERB_SET_CHANNEL_STREAMID, (stream_tag << 4) | 0x0);
3562
3563 /* set the stream format */
3564 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, 0,
3565 AC_VERB_SET_STREAM_FORMAT, format);
3566
3567 /* turn on again (if needed) */
3568 /* enable and set the channel status audio/data flag */
3569 if (codec->spdif_status_reset && (spdif->ctls & AC_DIG1_ENABLE)) {
3570 snd_hda_codec_write(codec,
3571 nvhdmi_master_con_nid_7x,
3572 0,
3573 AC_VERB_SET_DIGI_CONVERT_1,
3574 spdif->ctls & 0xff);
3575 snd_hda_codec_write(codec,
3576 nvhdmi_master_con_nid_7x,
3577 0,
3578 AC_VERB_SET_DIGI_CONVERT_2, dataDCC2);
3579 }
3580
3581 for (i = 0; i < 4; i++) {
3582 if (chs == 2)
3583 channel_id = 0;
3584 else
3585 channel_id = i * 2;
3586
3587 /* turn off SPDIF once;
3588 *otherwise the IEC958 bits won't be updated
3589 */
3590 if (codec->spdif_status_reset &&
3591 (spdif->ctls & AC_DIG1_ENABLE))
3592 snd_hda_codec_write(codec,
3593 nvhdmi_con_nids_7x[i],
3594 0,
3595 AC_VERB_SET_DIGI_CONVERT_1,
3596 spdif->ctls & ~AC_DIG1_ENABLE & 0xff);
3597 /* set the stream id */
3598 snd_hda_codec_write(codec,
3599 nvhdmi_con_nids_7x[i],
3600 0,
3601 AC_VERB_SET_CHANNEL_STREAMID,
3602 (stream_tag << 4) | channel_id);
3603 /* set the stream format */
3604 snd_hda_codec_write(codec,
3605 nvhdmi_con_nids_7x[i],
3606 0,
3607 AC_VERB_SET_STREAM_FORMAT,
3608 format);
3609 /* turn on again (if needed) */
3610 /* enable and set the channel status audio/data flag */
3611 if (codec->spdif_status_reset &&
3612 (spdif->ctls & AC_DIG1_ENABLE)) {
3613 snd_hda_codec_write(codec,
3614 nvhdmi_con_nids_7x[i],
3615 0,
3616 AC_VERB_SET_DIGI_CONVERT_1,
3617 spdif->ctls & 0xff);
3618 snd_hda_codec_write(codec,
3619 nvhdmi_con_nids_7x[i],
3620 0,
3621 AC_VERB_SET_DIGI_CONVERT_2, dataDCC2);
3622 }
3623 }
3624
3625 nvhdmi_8ch_7x_set_info_frame_parameters(codec, chs);
3626
3627 mutex_unlock(&codec->spdif_mutex);
3628 return 0;
3629}
3630
3631static const struct hda_pcm_stream nvhdmi_pcm_playback_8ch_7x = {
3632 .substreams = 1,
3633 .channels_min = 2,
3634 .channels_max = 8,
3635 .nid = nvhdmi_master_con_nid_7x,
3636 .rates = SUPPORTED_RATES,
3637 .maxbps = SUPPORTED_MAXBPS,
3638 .formats = SUPPORTED_FORMATS,
3639 .ops = {
3640 .open = simple_playback_pcm_open,
3641 .close = nvhdmi_8ch_7x_pcm_close,
3642 .prepare = nvhdmi_8ch_7x_pcm_prepare
3643 },
3644};
3645
3646static int patch_nvhdmi_2ch(struct hda_codec *codec)
3647{
3648 struct hdmi_spec *spec;
3649 int err = patch_simple_hdmi(codec, nvhdmi_master_con_nid_7x,
3650 nvhdmi_master_pin_nid_7x);
3651 if (err < 0)
3652 return err;
3653
3654 codec->patch_ops.init = nvhdmi_7x_init_2ch;
3655 /* override the PCM rates, etc, as the codec doesn't give full list */
3656 spec = codec->spec;
3657 spec->pcm_playback.rates = SUPPORTED_RATES;
3658 spec->pcm_playback.maxbps = SUPPORTED_MAXBPS;
3659 spec->pcm_playback.formats = SUPPORTED_FORMATS;
3660 spec->nv_dp_workaround = true;
3661 return 0;
3662}
3663
3664static int nvhdmi_7x_8ch_build_pcms(struct hda_codec *codec)
3665{
3666 struct hdmi_spec *spec = codec->spec;
3667 int err = simple_playback_build_pcms(codec);
3668 if (!err) {
3669 struct hda_pcm *info = get_pcm_rec(spec, 0);
3670 info->own_chmap = true;
3671 }
3672 return err;
3673}
3674
3675static int nvhdmi_7x_8ch_build_controls(struct hda_codec *codec)
3676{
3677 struct hdmi_spec *spec = codec->spec;
3678 struct hda_pcm *info;
3679 struct snd_pcm_chmap *chmap;
3680 int err;
3681
3682 err = simple_playback_build_controls(codec);
3683 if (err < 0)
3684 return err;
3685
3686 /* add channel maps */
3687 info = get_pcm_rec(spec, 0);
3688 err = snd_pcm_add_chmap_ctls(info->pcm,
3689 SNDRV_PCM_STREAM_PLAYBACK,
3690 snd_pcm_alt_chmaps, 8, 0, &chmap);
3691 if (err < 0)
3692 return err;
3693 switch (codec->preset->vendor_id) {
3694 case 0x10de0002:
3695 case 0x10de0003:
3696 case 0x10de0005:
3697 case 0x10de0006:
3698 chmap->channel_mask = (1U << 2) | (1U << 8);
3699 break;
3700 case 0x10de0007:
3701 chmap->channel_mask = (1U << 2) | (1U << 6) | (1U << 8);
3702 }
3703 return 0;
3704}
3705
3706static int patch_nvhdmi_8ch_7x(struct hda_codec *codec)
3707{
3708 struct hdmi_spec *spec;
3709 int err = patch_nvhdmi_2ch(codec);
3710 if (err < 0)
3711 return err;
3712 spec = codec->spec;
3713 spec->multiout.max_channels = 8;
3714 spec->pcm_playback = nvhdmi_pcm_playback_8ch_7x;
3715 codec->patch_ops.init = nvhdmi_7x_init_8ch;
3716 codec->patch_ops.build_pcms = nvhdmi_7x_8ch_build_pcms;
3717 codec->patch_ops.build_controls = nvhdmi_7x_8ch_build_controls;
3718
3719 /* Initialize the audio infoframe channel mask and checksum to something
3720 * valid */
3721 nvhdmi_8ch_7x_set_info_frame_parameters(codec, 8);
3722
3723 return 0;
3724}
3725
3726/*
3727 * NVIDIA codecs ignore ASP mapping for 2ch - confirmed on:
3728 * - 0x10de0015
3729 * - 0x10de0040
3730 */
3731static int nvhdmi_chmap_cea_alloc_validate_get_type(struct hdac_chmap *chmap,
3732 struct hdac_cea_channel_speaker_allocation *cap, int channels)
3733{
3734 if (cap->ca_index == 0x00 && channels == 2)
3735 return SNDRV_CTL_TLVT_CHMAP_FIXED;
3736
3737 /* If the speaker allocation matches the channel count, it is OK. */
3738 if (cap->channels != channels)
3739 return -1;
3740
3741 /* all channels are remappable freely */
3742 return SNDRV_CTL_TLVT_CHMAP_VAR;
3743}
3744
3745static int nvhdmi_chmap_validate(struct hdac_chmap *chmap,
3746 int ca, int chs, unsigned char *map)
3747{
3748 if (ca == 0x00 && (map[0] != SNDRV_CHMAP_FL || map[1] != SNDRV_CHMAP_FR))
3749 return -EINVAL;
3750
3751 return 0;
3752}
3753
3754/* map from pin NID to port; port is 0-based */
3755/* for Nvidia: assume widget NID starting from 4, with step 1 (4, 5, 6, ...) */
3756static int nvhdmi_pin2port(void *audio_ptr, int pin_nid)
3757{
3758 return pin_nid - 4;
3759}
3760
3761/* reverse-map from port to pin NID: see above */
3762static int nvhdmi_port2pin(struct hda_codec *codec, int port)
3763{
3764 return port + 4;
3765}
3766
3767static const struct drm_audio_component_audio_ops nvhdmi_audio_ops = {
3768 .pin2port = nvhdmi_pin2port,
3769 .pin_eld_notify = generic_acomp_pin_eld_notify,
3770 .master_bind = generic_acomp_master_bind,
3771 .master_unbind = generic_acomp_master_unbind,
3772};
3773
3774static int patch_nvhdmi(struct hda_codec *codec)
3775{
3776 struct hdmi_spec *spec;
3777 int err;
3778
3779 err = alloc_generic_hdmi(codec);
3780 if (err < 0)
3781 return err;
3782 codec->dp_mst = true;
3783
3784 spec = codec->spec;
3785
3786 err = hdmi_parse_codec(codec);
3787 if (err < 0) {
3788 generic_spec_free(codec);
3789 return err;
3790 }
3791
3792 generic_hdmi_init_per_pins(codec);
3793
3794 spec->dyn_pin_out = true;
3795
3796 spec->chmap.ops.chmap_cea_alloc_validate_get_type =
3797 nvhdmi_chmap_cea_alloc_validate_get_type;
3798 spec->chmap.ops.chmap_validate = nvhdmi_chmap_validate;
3799 spec->nv_dp_workaround = true;
3800
3801 codec->link_down_at_suspend = 1;
3802
3803 generic_acomp_init(codec, &nvhdmi_audio_ops, nvhdmi_port2pin);
3804
3805 return 0;
3806}
3807
3808static int patch_nvhdmi_legacy(struct hda_codec *codec)
3809{
3810 struct hdmi_spec *spec;
3811 int err;
3812
3813 err = patch_generic_hdmi(codec);
3814 if (err)
3815 return err;
3816
3817 spec = codec->spec;
3818 spec->dyn_pin_out = true;
3819
3820 spec->chmap.ops.chmap_cea_alloc_validate_get_type =
3821 nvhdmi_chmap_cea_alloc_validate_get_type;
3822 spec->chmap.ops.chmap_validate = nvhdmi_chmap_validate;
3823 spec->nv_dp_workaround = true;
3824
3825 codec->link_down_at_suspend = 1;
3826
3827 return 0;
3828}
3829
3830/*
3831 * The HDA codec on NVIDIA Tegra contains two scratch registers that are
3832 * accessed using vendor-defined verbs. These registers can be used for
3833 * interoperability between the HDA and HDMI drivers.
3834 */
3835
3836/* Audio Function Group node */
3837#define NVIDIA_AFG_NID 0x01
3838
3839/*
3840 * The SCRATCH0 register is used to notify the HDMI codec of changes in audio
3841 * format. On Tegra, bit 31 is used as a trigger that causes an interrupt to
3842 * be raised in the HDMI codec. The remainder of the bits is arbitrary. This
3843 * implementation stores the HDA format (see AC_FMT_*) in bits [15:0] and an
3844 * additional bit (at position 30) to signal the validity of the format.
3845 *
3846 * | 31 | 30 | 29 16 | 15 0 |
3847 * +---------+-------+--------+--------+
3848 * | TRIGGER | VALID | UNUSED | FORMAT |
3849 * +-----------------------------------|
3850 *
3851 * Note that for the trigger bit to take effect it needs to change value
3852 * (i.e. it needs to be toggled). The trigger bit is not applicable from
3853 * TEGRA234 chip onwards, as new verb id 0xf80 will be used for interrupt
3854 * trigger to hdmi.
3855 */
3856#define NVIDIA_SET_HOST_INTR 0xf80
3857#define NVIDIA_GET_SCRATCH0 0xfa6
3858#define NVIDIA_SET_SCRATCH0_BYTE0 0xfa7
3859#define NVIDIA_SET_SCRATCH0_BYTE1 0xfa8
3860#define NVIDIA_SET_SCRATCH0_BYTE2 0xfa9
3861#define NVIDIA_SET_SCRATCH0_BYTE3 0xfaa
3862#define NVIDIA_SCRATCH_TRIGGER (1 << 7)
3863#define NVIDIA_SCRATCH_VALID (1 << 6)
3864
3865#define NVIDIA_GET_SCRATCH1 0xfab
3866#define NVIDIA_SET_SCRATCH1_BYTE0 0xfac
3867#define NVIDIA_SET_SCRATCH1_BYTE1 0xfad
3868#define NVIDIA_SET_SCRATCH1_BYTE2 0xfae
3869#define NVIDIA_SET_SCRATCH1_BYTE3 0xfaf
3870
3871/*
3872 * The format parameter is the HDA audio format (see AC_FMT_*). If set to 0,
3873 * the format is invalidated so that the HDMI codec can be disabled.
3874 */
3875static void tegra_hdmi_set_format(struct hda_codec *codec,
3876 hda_nid_t cvt_nid,
3877 unsigned int format)
3878{
3879 unsigned int value;
3880 unsigned int nid = NVIDIA_AFG_NID;
3881 struct hdmi_spec *spec = codec->spec;
3882
3883 /*
3884 * Tegra HDA codec design from TEGRA234 chip onwards support DP MST.
3885 * This resulted in moving scratch registers from audio function
3886 * group to converter widget context. So CVT NID should be used for
3887 * scratch register read/write for DP MST supported Tegra HDA codec.
3888 */
3889 if (codec->dp_mst)
3890 nid = cvt_nid;
3891
3892 /* bits [31:30] contain the trigger and valid bits */
3893 value = snd_hda_codec_read(codec, nid, 0,
3894 NVIDIA_GET_SCRATCH0, 0);
3895 value = (value >> 24) & 0xff;
3896
3897 /* bits [15:0] are used to store the HDA format */
3898 snd_hda_codec_write(codec, nid, 0,
3899 NVIDIA_SET_SCRATCH0_BYTE0,
3900 (format >> 0) & 0xff);
3901 snd_hda_codec_write(codec, nid, 0,
3902 NVIDIA_SET_SCRATCH0_BYTE1,
3903 (format >> 8) & 0xff);
3904
3905 /* bits [16:24] are unused */
3906 snd_hda_codec_write(codec, nid, 0,
3907 NVIDIA_SET_SCRATCH0_BYTE2, 0);
3908
3909 /*
3910 * Bit 30 signals that the data is valid and hence that HDMI audio can
3911 * be enabled.
3912 */
3913 if (format == 0)
3914 value &= ~NVIDIA_SCRATCH_VALID;
3915 else
3916 value |= NVIDIA_SCRATCH_VALID;
3917
3918 if (spec->hdmi_intr_trig_ctrl) {
3919 /*
3920 * For Tegra HDA Codec design from TEGRA234 onwards, the
3921 * Interrupt to hdmi driver is triggered by writing
3922 * non-zero values to verb 0xF80 instead of 31st bit of
3923 * scratch register.
3924 */
3925 snd_hda_codec_write(codec, nid, 0,
3926 NVIDIA_SET_SCRATCH0_BYTE3, value);
3927 snd_hda_codec_write(codec, nid, 0,
3928 NVIDIA_SET_HOST_INTR, 0x1);
3929 } else {
3930 /*
3931 * Whenever the 31st trigger bit is toggled, an interrupt is raised
3932 * in the HDMI codec. The HDMI driver will use that as trigger
3933 * to update its configuration.
3934 */
3935 value ^= NVIDIA_SCRATCH_TRIGGER;
3936
3937 snd_hda_codec_write(codec, nid, 0,
3938 NVIDIA_SET_SCRATCH0_BYTE3, value);
3939 }
3940}
3941
3942static int tegra_hdmi_pcm_prepare(struct hda_pcm_stream *hinfo,
3943 struct hda_codec *codec,
3944 unsigned int stream_tag,
3945 unsigned int format,
3946 struct snd_pcm_substream *substream)
3947{
3948 int err;
3949
3950 err = generic_hdmi_playback_pcm_prepare(hinfo, codec, stream_tag,
3951 format, substream);
3952 if (err < 0)
3953 return err;
3954
3955 /* notify the HDMI codec of the format change */
3956 tegra_hdmi_set_format(codec, hinfo->nid, format);
3957
3958 return 0;
3959}
3960
3961static int tegra_hdmi_pcm_cleanup(struct hda_pcm_stream *hinfo,
3962 struct hda_codec *codec,
3963 struct snd_pcm_substream *substream)
3964{
3965 /* invalidate the format in the HDMI codec */
3966 tegra_hdmi_set_format(codec, hinfo->nid, 0);
3967
3968 return generic_hdmi_playback_pcm_cleanup(hinfo, codec, substream);
3969}
3970
3971static struct hda_pcm *hda_find_pcm_by_type(struct hda_codec *codec, int type)
3972{
3973 struct hdmi_spec *spec = codec->spec;
3974 unsigned int i;
3975
3976 for (i = 0; i < spec->num_pins; i++) {
3977 struct hda_pcm *pcm = get_pcm_rec(spec, i);
3978
3979 if (pcm->pcm_type == type)
3980 return pcm;
3981 }
3982
3983 return NULL;
3984}
3985
3986static int tegra_hdmi_build_pcms(struct hda_codec *codec)
3987{
3988 struct hda_pcm_stream *stream;
3989 struct hda_pcm *pcm;
3990 int err;
3991
3992 err = generic_hdmi_build_pcms(codec);
3993 if (err < 0)
3994 return err;
3995
3996 pcm = hda_find_pcm_by_type(codec, HDA_PCM_TYPE_HDMI);
3997 if (!pcm)
3998 return -ENODEV;
3999
4000 /*
4001 * Override ->prepare() and ->cleanup() operations to notify the HDMI
4002 * codec about format changes.
4003 */
4004 stream = &pcm->stream[SNDRV_PCM_STREAM_PLAYBACK];
4005 stream->ops.prepare = tegra_hdmi_pcm_prepare;
4006 stream->ops.cleanup = tegra_hdmi_pcm_cleanup;
4007
4008 return 0;
4009}
4010
4011static int tegra_hdmi_init(struct hda_codec *codec)
4012{
4013 struct hdmi_spec *spec = codec->spec;
4014 int i, err;
4015
4016 err = hdmi_parse_codec(codec);
4017 if (err < 0) {
4018 generic_spec_free(codec);
4019 return err;
4020 }
4021
4022 for (i = 0; i < spec->num_cvts; i++)
4023 snd_hda_codec_write(codec, spec->cvt_nids[i], 0,
4024 AC_VERB_SET_DIGI_CONVERT_1,
4025 AC_DIG1_ENABLE);
4026
4027 generic_hdmi_init_per_pins(codec);
4028
4029 codec->depop_delay = 10;
4030 codec->patch_ops.build_pcms = tegra_hdmi_build_pcms;
4031 spec->chmap.ops.chmap_cea_alloc_validate_get_type =
4032 nvhdmi_chmap_cea_alloc_validate_get_type;
4033 spec->chmap.ops.chmap_validate = nvhdmi_chmap_validate;
4034
4035 spec->chmap.ops.chmap_cea_alloc_validate_get_type =
4036 nvhdmi_chmap_cea_alloc_validate_get_type;
4037 spec->chmap.ops.chmap_validate = nvhdmi_chmap_validate;
4038 spec->nv_dp_workaround = true;
4039
4040 return 0;
4041}
4042
4043static int patch_tegra_hdmi(struct hda_codec *codec)
4044{
4045 int err;
4046
4047 err = alloc_generic_hdmi(codec);
4048 if (err < 0)
4049 return err;
4050
4051 return tegra_hdmi_init(codec);
4052}
4053
4054static int patch_tegra234_hdmi(struct hda_codec *codec)
4055{
4056 struct hdmi_spec *spec;
4057 int err;
4058
4059 err = alloc_generic_hdmi(codec);
4060 if (err < 0)
4061 return err;
4062
4063 codec->dp_mst = true;
4064 spec = codec->spec;
4065 spec->dyn_pin_out = true;
4066 spec->hdmi_intr_trig_ctrl = true;
4067
4068 return tegra_hdmi_init(codec);
4069}
4070
4071/*
4072 * ATI/AMD-specific implementations
4073 */
4074
4075#define is_amdhdmi_rev3_or_later(codec) \
4076 ((codec)->core.vendor_id == 0x1002aa01 && \
4077 ((codec)->core.revision_id & 0xff00) >= 0x0300)
4078#define has_amd_full_remap_support(codec) is_amdhdmi_rev3_or_later(codec)
4079
4080/* ATI/AMD specific HDA pin verbs, see the AMD HDA Verbs specification */
4081#define ATI_VERB_SET_CHANNEL_ALLOCATION 0x771
4082#define ATI_VERB_SET_DOWNMIX_INFO 0x772
4083#define ATI_VERB_SET_MULTICHANNEL_01 0x777
4084#define ATI_VERB_SET_MULTICHANNEL_23 0x778
4085#define ATI_VERB_SET_MULTICHANNEL_45 0x779
4086#define ATI_VERB_SET_MULTICHANNEL_67 0x77a
4087#define ATI_VERB_SET_HBR_CONTROL 0x77c
4088#define ATI_VERB_SET_MULTICHANNEL_1 0x785
4089#define ATI_VERB_SET_MULTICHANNEL_3 0x786
4090#define ATI_VERB_SET_MULTICHANNEL_5 0x787
4091#define ATI_VERB_SET_MULTICHANNEL_7 0x788
4092#define ATI_VERB_SET_MULTICHANNEL_MODE 0x789
4093#define ATI_VERB_GET_CHANNEL_ALLOCATION 0xf71
4094#define ATI_VERB_GET_DOWNMIX_INFO 0xf72
4095#define ATI_VERB_GET_MULTICHANNEL_01 0xf77
4096#define ATI_VERB_GET_MULTICHANNEL_23 0xf78
4097#define ATI_VERB_GET_MULTICHANNEL_45 0xf79
4098#define ATI_VERB_GET_MULTICHANNEL_67 0xf7a
4099#define ATI_VERB_GET_HBR_CONTROL 0xf7c
4100#define ATI_VERB_GET_MULTICHANNEL_1 0xf85
4101#define ATI_VERB_GET_MULTICHANNEL_3 0xf86
4102#define ATI_VERB_GET_MULTICHANNEL_5 0xf87
4103#define ATI_VERB_GET_MULTICHANNEL_7 0xf88
4104#define ATI_VERB_GET_MULTICHANNEL_MODE 0xf89
4105
4106/* AMD specific HDA cvt verbs */
4107#define ATI_VERB_SET_RAMP_RATE 0x770
4108#define ATI_VERB_GET_RAMP_RATE 0xf70
4109
4110#define ATI_OUT_ENABLE 0x1
4111
4112#define ATI_MULTICHANNEL_MODE_PAIRED 0
4113#define ATI_MULTICHANNEL_MODE_SINGLE 1
4114
4115#define ATI_HBR_CAPABLE 0x01
4116#define ATI_HBR_ENABLE 0x10
4117
4118static int atihdmi_pin_get_eld(struct hda_codec *codec, hda_nid_t nid,
4119 int dev_id, unsigned char *buf, int *eld_size)
4120{
4121 WARN_ON(dev_id != 0);
4122 /* call hda_eld.c ATI/AMD-specific function */
4123 return snd_hdmi_get_eld_ati(codec, nid, buf, eld_size,
4124 is_amdhdmi_rev3_or_later(codec));
4125}
4126
4127static void atihdmi_pin_setup_infoframe(struct hda_codec *codec,
4128 hda_nid_t pin_nid, int dev_id, int ca,
4129 int active_channels, int conn_type)
4130{
4131 WARN_ON(dev_id != 0);
4132 snd_hda_codec_write(codec, pin_nid, 0, ATI_VERB_SET_CHANNEL_ALLOCATION, ca);
4133}
4134
4135static int atihdmi_paired_swap_fc_lfe(int pos)
4136{
4137 /*
4138 * ATI/AMD have automatic FC/LFE swap built-in
4139 * when in pairwise mapping mode.
4140 */
4141
4142 switch (pos) {
4143 /* see channel_allocations[].speakers[] */
4144 case 2: return 3;
4145 case 3: return 2;
4146 default: break;
4147 }
4148
4149 return pos;
4150}
4151
4152static int atihdmi_paired_chmap_validate(struct hdac_chmap *chmap,
4153 int ca, int chs, unsigned char *map)
4154{
4155 struct hdac_cea_channel_speaker_allocation *cap;
4156 int i, j;
4157
4158 /* check that only channel pairs need to be remapped on old pre-rev3 ATI/AMD */
4159
4160 cap = snd_hdac_get_ch_alloc_from_ca(ca);
4161 for (i = 0; i < chs; ++i) {
4162 int mask = snd_hdac_chmap_to_spk_mask(map[i]);
4163 bool ok = false;
4164 bool companion_ok = false;
4165
4166 if (!mask)
4167 continue;
4168
4169 for (j = 0 + i % 2; j < 8; j += 2) {
4170 int chan_idx = 7 - atihdmi_paired_swap_fc_lfe(j);
4171 if (cap->speakers[chan_idx] == mask) {
4172 /* channel is in a supported position */
4173 ok = true;
4174
4175 if (i % 2 == 0 && i + 1 < chs) {
4176 /* even channel, check the odd companion */
4177 int comp_chan_idx = 7 - atihdmi_paired_swap_fc_lfe(j + 1);
4178 int comp_mask_req = snd_hdac_chmap_to_spk_mask(map[i+1]);
4179 int comp_mask_act = cap->speakers[comp_chan_idx];
4180
4181 if (comp_mask_req == comp_mask_act)
4182 companion_ok = true;
4183 else
4184 return -EINVAL;
4185 }
4186 break;
4187 }
4188 }
4189
4190 if (!ok)
4191 return -EINVAL;
4192
4193 if (companion_ok)
4194 i++; /* companion channel already checked */
4195 }
4196
4197 return 0;
4198}
4199
4200static int atihdmi_pin_set_slot_channel(struct hdac_device *hdac,
4201 hda_nid_t pin_nid, int hdmi_slot, int stream_channel)
4202{
4203 struct hda_codec *codec = hdac_to_hda_codec(hdac);
4204 int verb;
4205 int ati_channel_setup = 0;
4206
4207 if (hdmi_slot > 7)
4208 return -EINVAL;
4209
4210 if (!has_amd_full_remap_support(codec)) {
4211 hdmi_slot = atihdmi_paired_swap_fc_lfe(hdmi_slot);
4212
4213 /* In case this is an odd slot but without stream channel, do not
4214 * disable the slot since the corresponding even slot could have a
4215 * channel. In case neither have a channel, the slot pair will be
4216 * disabled when this function is called for the even slot. */
4217 if (hdmi_slot % 2 != 0 && stream_channel == 0xf)
4218 return 0;
4219
4220 hdmi_slot -= hdmi_slot % 2;
4221
4222 if (stream_channel != 0xf)
4223 stream_channel -= stream_channel % 2;
4224 }
4225
4226 verb = ATI_VERB_SET_MULTICHANNEL_01 + hdmi_slot/2 + (hdmi_slot % 2) * 0x00e;
4227
4228 /* ati_channel_setup format: [7..4] = stream_channel_id, [1] = mute, [0] = enable */
4229
4230 if (stream_channel != 0xf)
4231 ati_channel_setup = (stream_channel << 4) | ATI_OUT_ENABLE;
4232
4233 return snd_hda_codec_write(codec, pin_nid, 0, verb, ati_channel_setup);
4234}
4235
4236static int atihdmi_pin_get_slot_channel(struct hdac_device *hdac,
4237 hda_nid_t pin_nid, int asp_slot)
4238{
4239 struct hda_codec *codec = hdac_to_hda_codec(hdac);
4240 bool was_odd = false;
4241 int ati_asp_slot = asp_slot;
4242 int verb;
4243 int ati_channel_setup;
4244
4245 if (asp_slot > 7)
4246 return -EINVAL;
4247
4248 if (!has_amd_full_remap_support(codec)) {
4249 ati_asp_slot = atihdmi_paired_swap_fc_lfe(asp_slot);
4250 if (ati_asp_slot % 2 != 0) {
4251 ati_asp_slot -= 1;
4252 was_odd = true;
4253 }
4254 }
4255
4256 verb = ATI_VERB_GET_MULTICHANNEL_01 + ati_asp_slot/2 + (ati_asp_slot % 2) * 0x00e;
4257
4258 ati_channel_setup = snd_hda_codec_read(codec, pin_nid, 0, verb, 0);
4259
4260 if (!(ati_channel_setup & ATI_OUT_ENABLE))
4261 return 0xf;
4262
4263 return ((ati_channel_setup & 0xf0) >> 4) + !!was_odd;
4264}
4265
4266static int atihdmi_paired_chmap_cea_alloc_validate_get_type(
4267 struct hdac_chmap *chmap,
4268 struct hdac_cea_channel_speaker_allocation *cap,
4269 int channels)
4270{
4271 int c;
4272
4273 /*
4274 * Pre-rev3 ATI/AMD codecs operate in a paired channel mode, so
4275 * we need to take that into account (a single channel may take 2
4276 * channel slots if we need to carry a silent channel next to it).
4277 * On Rev3+ AMD codecs this function is not used.
4278 */
4279 int chanpairs = 0;
4280
4281 /* We only produce even-numbered channel count TLVs */
4282 if ((channels % 2) != 0)
4283 return -1;
4284
4285 for (c = 0; c < 7; c += 2) {
4286 if (cap->speakers[c] || cap->speakers[c+1])
4287 chanpairs++;
4288 }
4289
4290 if (chanpairs * 2 != channels)
4291 return -1;
4292
4293 return SNDRV_CTL_TLVT_CHMAP_PAIRED;
4294}
4295
4296static void atihdmi_paired_cea_alloc_to_tlv_chmap(struct hdac_chmap *hchmap,
4297 struct hdac_cea_channel_speaker_allocation *cap,
4298 unsigned int *chmap, int channels)
4299{
4300 /* produce paired maps for pre-rev3 ATI/AMD codecs */
4301 int count = 0;
4302 int c;
4303
4304 for (c = 7; c >= 0; c--) {
4305 int chan = 7 - atihdmi_paired_swap_fc_lfe(7 - c);
4306 int spk = cap->speakers[chan];
4307 if (!spk) {
4308 /* add N/A channel if the companion channel is occupied */
4309 if (cap->speakers[chan + (chan % 2 ? -1 : 1)])
4310 chmap[count++] = SNDRV_CHMAP_NA;
4311
4312 continue;
4313 }
4314
4315 chmap[count++] = snd_hdac_spk_to_chmap(spk);
4316 }
4317
4318 WARN_ON(count != channels);
4319}
4320
4321static int atihdmi_pin_hbr_setup(struct hda_codec *codec, hda_nid_t pin_nid,
4322 int dev_id, bool hbr)
4323{
4324 int hbr_ctl, hbr_ctl_new;
4325
4326 WARN_ON(dev_id != 0);
4327
4328 hbr_ctl = snd_hda_codec_read(codec, pin_nid, 0, ATI_VERB_GET_HBR_CONTROL, 0);
4329 if (hbr_ctl >= 0 && (hbr_ctl & ATI_HBR_CAPABLE)) {
4330 if (hbr)
4331 hbr_ctl_new = hbr_ctl | ATI_HBR_ENABLE;
4332 else
4333 hbr_ctl_new = hbr_ctl & ~ATI_HBR_ENABLE;
4334
4335 codec_dbg(codec,
4336 "atihdmi_pin_hbr_setup: NID=0x%x, %shbr-ctl=0x%x\n",
4337 pin_nid,
4338 hbr_ctl == hbr_ctl_new ? "" : "new-",
4339 hbr_ctl_new);
4340
4341 if (hbr_ctl != hbr_ctl_new)
4342 snd_hda_codec_write(codec, pin_nid, 0,
4343 ATI_VERB_SET_HBR_CONTROL,
4344 hbr_ctl_new);
4345
4346 } else if (hbr)
4347 return -EINVAL;
4348
4349 return 0;
4350}
4351
4352static int atihdmi_setup_stream(struct hda_codec *codec, hda_nid_t cvt_nid,
4353 hda_nid_t pin_nid, int dev_id,
4354 u32 stream_tag, int format)
4355{
4356 if (is_amdhdmi_rev3_or_later(codec)) {
4357 int ramp_rate = 180; /* default as per AMD spec */
4358 /* disable ramp-up/down for non-pcm as per AMD spec */
4359 if (format & AC_FMT_TYPE_NON_PCM)
4360 ramp_rate = 0;
4361
4362 snd_hda_codec_write(codec, cvt_nid, 0, ATI_VERB_SET_RAMP_RATE, ramp_rate);
4363 }
4364
4365 return hdmi_setup_stream(codec, cvt_nid, pin_nid, dev_id,
4366 stream_tag, format);
4367}
4368
4369
4370static int atihdmi_init(struct hda_codec *codec)
4371{
4372 struct hdmi_spec *spec = codec->spec;
4373 int pin_idx, err;
4374
4375 err = generic_hdmi_init(codec);
4376
4377 if (err)
4378 return err;
4379
4380 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
4381 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
4382
4383 /* make sure downmix information in infoframe is zero */
4384 snd_hda_codec_write(codec, per_pin->pin_nid, 0, ATI_VERB_SET_DOWNMIX_INFO, 0);
4385
4386 /* enable channel-wise remap mode if supported */
4387 if (has_amd_full_remap_support(codec))
4388 snd_hda_codec_write(codec, per_pin->pin_nid, 0,
4389 ATI_VERB_SET_MULTICHANNEL_MODE,
4390 ATI_MULTICHANNEL_MODE_SINGLE);
4391 }
4392 codec->auto_runtime_pm = 1;
4393
4394 return 0;
4395}
4396
4397/* map from pin NID to port; port is 0-based */
4398/* for AMD: assume widget NID starting from 3, with step 2 (3, 5, 7, ...) */
4399static int atihdmi_pin2port(void *audio_ptr, int pin_nid)
4400{
4401 return pin_nid / 2 - 1;
4402}
4403
4404/* reverse-map from port to pin NID: see above */
4405static int atihdmi_port2pin(struct hda_codec *codec, int port)
4406{
4407 return port * 2 + 3;
4408}
4409
4410static const struct drm_audio_component_audio_ops atihdmi_audio_ops = {
4411 .pin2port = atihdmi_pin2port,
4412 .pin_eld_notify = generic_acomp_pin_eld_notify,
4413 .master_bind = generic_acomp_master_bind,
4414 .master_unbind = generic_acomp_master_unbind,
4415};
4416
4417static int patch_atihdmi(struct hda_codec *codec)
4418{
4419 struct hdmi_spec *spec;
4420 struct hdmi_spec_per_cvt *per_cvt;
4421 int err, cvt_idx;
4422
4423 err = patch_generic_hdmi(codec);
4424
4425 if (err)
4426 return err;
4427
4428 codec->patch_ops.init = atihdmi_init;
4429
4430 spec = codec->spec;
4431
4432 spec->static_pcm_mapping = true;
4433
4434 spec->ops.pin_get_eld = atihdmi_pin_get_eld;
4435 spec->ops.pin_setup_infoframe = atihdmi_pin_setup_infoframe;
4436 spec->ops.pin_hbr_setup = atihdmi_pin_hbr_setup;
4437 spec->ops.setup_stream = atihdmi_setup_stream;
4438
4439 spec->chmap.ops.pin_get_slot_channel = atihdmi_pin_get_slot_channel;
4440 spec->chmap.ops.pin_set_slot_channel = atihdmi_pin_set_slot_channel;
4441
4442 if (!has_amd_full_remap_support(codec)) {
4443 /* override to ATI/AMD-specific versions with pairwise mapping */
4444 spec->chmap.ops.chmap_cea_alloc_validate_get_type =
4445 atihdmi_paired_chmap_cea_alloc_validate_get_type;
4446 spec->chmap.ops.cea_alloc_to_tlv_chmap =
4447 atihdmi_paired_cea_alloc_to_tlv_chmap;
4448 spec->chmap.ops.chmap_validate = atihdmi_paired_chmap_validate;
4449 }
4450
4451 /* ATI/AMD converters do not advertise all of their capabilities */
4452 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) {
4453 per_cvt = get_cvt(spec, cvt_idx);
4454 per_cvt->channels_max = max(per_cvt->channels_max, 8u);
4455 per_cvt->rates |= SUPPORTED_RATES;
4456 per_cvt->formats |= SUPPORTED_FORMATS;
4457 per_cvt->maxbps = max(per_cvt->maxbps, 24u);
4458 }
4459
4460 spec->chmap.channels_max = max(spec->chmap.channels_max, 8u);
4461
4462 /* AMD GPUs have neither EPSS nor CLKSTOP bits, hence preventing
4463 * the link-down as is. Tell the core to allow it.
4464 */
4465 codec->link_down_at_suspend = 1;
4466
4467 generic_acomp_init(codec, &atihdmi_audio_ops, atihdmi_port2pin);
4468
4469 return 0;
4470}
4471
4472/* VIA HDMI Implementation */
4473#define VIAHDMI_CVT_NID 0x02 /* audio converter1 */
4474#define VIAHDMI_PIN_NID 0x03 /* HDMI output pin1 */
4475
4476static int patch_via_hdmi(struct hda_codec *codec)
4477{
4478 return patch_simple_hdmi(codec, VIAHDMI_CVT_NID, VIAHDMI_PIN_NID);
4479}
4480
4481/*
4482 * patch entries
4483 */
4484static const struct hda_device_id snd_hda_id_hdmi[] = {
4485HDA_CODEC_ENTRY(0x1002793c, "RS600 HDMI", patch_atihdmi),
4486HDA_CODEC_ENTRY(0x10027919, "RS600 HDMI", patch_atihdmi),
4487HDA_CODEC_ENTRY(0x1002791a, "RS690/780 HDMI", patch_atihdmi),
4488HDA_CODEC_ENTRY(0x1002aa01, "R6xx HDMI", patch_atihdmi),
4489HDA_CODEC_ENTRY(0x10951390, "SiI1390 HDMI", patch_generic_hdmi),
4490HDA_CODEC_ENTRY(0x10951392, "SiI1392 HDMI", patch_generic_hdmi),
4491HDA_CODEC_ENTRY(0x17e80047, "Chrontel HDMI", patch_generic_hdmi),
4492HDA_CODEC_ENTRY(0x10de0001, "MCP73 HDMI", patch_nvhdmi_2ch),
4493HDA_CODEC_ENTRY(0x10de0002, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x),
4494HDA_CODEC_ENTRY(0x10de0003, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x),
4495HDA_CODEC_ENTRY(0x10de0004, "GPU 04 HDMI", patch_nvhdmi_8ch_7x),
4496HDA_CODEC_ENTRY(0x10de0005, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x),
4497HDA_CODEC_ENTRY(0x10de0006, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x),
4498HDA_CODEC_ENTRY(0x10de0007, "MCP79/7A HDMI", patch_nvhdmi_8ch_7x),
4499HDA_CODEC_ENTRY(0x10de0008, "GPU 08 HDMI/DP", patch_nvhdmi_legacy),
4500HDA_CODEC_ENTRY(0x10de0009, "GPU 09 HDMI/DP", patch_nvhdmi_legacy),
4501HDA_CODEC_ENTRY(0x10de000a, "GPU 0a HDMI/DP", patch_nvhdmi_legacy),
4502HDA_CODEC_ENTRY(0x10de000b, "GPU 0b HDMI/DP", patch_nvhdmi_legacy),
4503HDA_CODEC_ENTRY(0x10de000c, "MCP89 HDMI", patch_nvhdmi_legacy),
4504HDA_CODEC_ENTRY(0x10de000d, "GPU 0d HDMI/DP", patch_nvhdmi_legacy),
4505HDA_CODEC_ENTRY(0x10de0010, "GPU 10 HDMI/DP", patch_nvhdmi_legacy),
4506HDA_CODEC_ENTRY(0x10de0011, "GPU 11 HDMI/DP", patch_nvhdmi_legacy),
4507HDA_CODEC_ENTRY(0x10de0012, "GPU 12 HDMI/DP", patch_nvhdmi_legacy),
4508HDA_CODEC_ENTRY(0x10de0013, "GPU 13 HDMI/DP", patch_nvhdmi_legacy),
4509HDA_CODEC_ENTRY(0x10de0014, "GPU 14 HDMI/DP", patch_nvhdmi_legacy),
4510HDA_CODEC_ENTRY(0x10de0015, "GPU 15 HDMI/DP", patch_nvhdmi_legacy),
4511HDA_CODEC_ENTRY(0x10de0016, "GPU 16 HDMI/DP", patch_nvhdmi_legacy),
4512/* 17 is known to be absent */
4513HDA_CODEC_ENTRY(0x10de0018, "GPU 18 HDMI/DP", patch_nvhdmi_legacy),
4514HDA_CODEC_ENTRY(0x10de0019, "GPU 19 HDMI/DP", patch_nvhdmi_legacy),
4515HDA_CODEC_ENTRY(0x10de001a, "GPU 1a HDMI/DP", patch_nvhdmi_legacy),
4516HDA_CODEC_ENTRY(0x10de001b, "GPU 1b HDMI/DP", patch_nvhdmi_legacy),
4517HDA_CODEC_ENTRY(0x10de001c, "GPU 1c HDMI/DP", patch_nvhdmi_legacy),
4518HDA_CODEC_ENTRY(0x10de0020, "Tegra30 HDMI", patch_tegra_hdmi),
4519HDA_CODEC_ENTRY(0x10de0022, "Tegra114 HDMI", patch_tegra_hdmi),
4520HDA_CODEC_ENTRY(0x10de0028, "Tegra124 HDMI", patch_tegra_hdmi),
4521HDA_CODEC_ENTRY(0x10de0029, "Tegra210 HDMI/DP", patch_tegra_hdmi),
4522HDA_CODEC_ENTRY(0x10de002d, "Tegra186 HDMI/DP0", patch_tegra_hdmi),
4523HDA_CODEC_ENTRY(0x10de002e, "Tegra186 HDMI/DP1", patch_tegra_hdmi),
4524HDA_CODEC_ENTRY(0x10de002f, "Tegra194 HDMI/DP2", patch_tegra_hdmi),
4525HDA_CODEC_ENTRY(0x10de0030, "Tegra194 HDMI/DP3", patch_tegra_hdmi),
4526HDA_CODEC_ENTRY(0x10de0031, "Tegra234 HDMI/DP", patch_tegra234_hdmi),
4527HDA_CODEC_ENTRY(0x10de0040, "GPU 40 HDMI/DP", patch_nvhdmi),
4528HDA_CODEC_ENTRY(0x10de0041, "GPU 41 HDMI/DP", patch_nvhdmi),
4529HDA_CODEC_ENTRY(0x10de0042, "GPU 42 HDMI/DP", patch_nvhdmi),
4530HDA_CODEC_ENTRY(0x10de0043, "GPU 43 HDMI/DP", patch_nvhdmi),
4531HDA_CODEC_ENTRY(0x10de0044, "GPU 44 HDMI/DP", patch_nvhdmi),
4532HDA_CODEC_ENTRY(0x10de0045, "GPU 45 HDMI/DP", patch_nvhdmi),
4533HDA_CODEC_ENTRY(0x10de0050, "GPU 50 HDMI/DP", patch_nvhdmi),
4534HDA_CODEC_ENTRY(0x10de0051, "GPU 51 HDMI/DP", patch_nvhdmi),
4535HDA_CODEC_ENTRY(0x10de0052, "GPU 52 HDMI/DP", patch_nvhdmi),
4536HDA_CODEC_ENTRY(0x10de0060, "GPU 60 HDMI/DP", patch_nvhdmi),
4537HDA_CODEC_ENTRY(0x10de0061, "GPU 61 HDMI/DP", patch_nvhdmi),
4538HDA_CODEC_ENTRY(0x10de0062, "GPU 62 HDMI/DP", patch_nvhdmi),
4539HDA_CODEC_ENTRY(0x10de0067, "MCP67 HDMI", patch_nvhdmi_2ch),
4540HDA_CODEC_ENTRY(0x10de0070, "GPU 70 HDMI/DP", patch_nvhdmi),
4541HDA_CODEC_ENTRY(0x10de0071, "GPU 71 HDMI/DP", patch_nvhdmi),
4542HDA_CODEC_ENTRY(0x10de0072, "GPU 72 HDMI/DP", patch_nvhdmi),
4543HDA_CODEC_ENTRY(0x10de0073, "GPU 73 HDMI/DP", patch_nvhdmi),
4544HDA_CODEC_ENTRY(0x10de0074, "GPU 74 HDMI/DP", patch_nvhdmi),
4545HDA_CODEC_ENTRY(0x10de0076, "GPU 76 HDMI/DP", patch_nvhdmi),
4546HDA_CODEC_ENTRY(0x10de007b, "GPU 7b HDMI/DP", patch_nvhdmi),
4547HDA_CODEC_ENTRY(0x10de007c, "GPU 7c HDMI/DP", patch_nvhdmi),
4548HDA_CODEC_ENTRY(0x10de007d, "GPU 7d HDMI/DP", patch_nvhdmi),
4549HDA_CODEC_ENTRY(0x10de007e, "GPU 7e HDMI/DP", patch_nvhdmi),
4550HDA_CODEC_ENTRY(0x10de0080, "GPU 80 HDMI/DP", patch_nvhdmi),
4551HDA_CODEC_ENTRY(0x10de0081, "GPU 81 HDMI/DP", patch_nvhdmi),
4552HDA_CODEC_ENTRY(0x10de0082, "GPU 82 HDMI/DP", patch_nvhdmi),
4553HDA_CODEC_ENTRY(0x10de0083, "GPU 83 HDMI/DP", patch_nvhdmi),
4554HDA_CODEC_ENTRY(0x10de0084, "GPU 84 HDMI/DP", patch_nvhdmi),
4555HDA_CODEC_ENTRY(0x10de0090, "GPU 90 HDMI/DP", patch_nvhdmi),
4556HDA_CODEC_ENTRY(0x10de0091, "GPU 91 HDMI/DP", patch_nvhdmi),
4557HDA_CODEC_ENTRY(0x10de0092, "GPU 92 HDMI/DP", patch_nvhdmi),
4558HDA_CODEC_ENTRY(0x10de0093, "GPU 93 HDMI/DP", patch_nvhdmi),
4559HDA_CODEC_ENTRY(0x10de0094, "GPU 94 HDMI/DP", patch_nvhdmi),
4560HDA_CODEC_ENTRY(0x10de0095, "GPU 95 HDMI/DP", patch_nvhdmi),
4561HDA_CODEC_ENTRY(0x10de0097, "GPU 97 HDMI/DP", patch_nvhdmi),
4562HDA_CODEC_ENTRY(0x10de0098, "GPU 98 HDMI/DP", patch_nvhdmi),
4563HDA_CODEC_ENTRY(0x10de0099, "GPU 99 HDMI/DP", patch_nvhdmi),
4564HDA_CODEC_ENTRY(0x10de009a, "GPU 9a HDMI/DP", patch_nvhdmi),
4565HDA_CODEC_ENTRY(0x10de009d, "GPU 9d HDMI/DP", patch_nvhdmi),
4566HDA_CODEC_ENTRY(0x10de009e, "GPU 9e HDMI/DP", patch_nvhdmi),
4567HDA_CODEC_ENTRY(0x10de009f, "GPU 9f HDMI/DP", patch_nvhdmi),
4568HDA_CODEC_ENTRY(0x10de00a0, "GPU a0 HDMI/DP", patch_nvhdmi),
4569HDA_CODEC_ENTRY(0x10de8001, "MCP73 HDMI", patch_nvhdmi_2ch),
4570HDA_CODEC_ENTRY(0x10de8067, "MCP67/68 HDMI", patch_nvhdmi_2ch),
4571HDA_CODEC_ENTRY(0x11069f80, "VX900 HDMI/DP", patch_via_hdmi),
4572HDA_CODEC_ENTRY(0x11069f81, "VX900 HDMI/DP", patch_via_hdmi),
4573HDA_CODEC_ENTRY(0x11069f84, "VX11 HDMI/DP", patch_generic_hdmi),
4574HDA_CODEC_ENTRY(0x11069f85, "VX11 HDMI/DP", patch_generic_hdmi),
4575HDA_CODEC_ENTRY(0x80860054, "IbexPeak HDMI", patch_i915_cpt_hdmi),
4576HDA_CODEC_ENTRY(0x80862800, "Geminilake HDMI", patch_i915_glk_hdmi),
4577HDA_CODEC_ENTRY(0x80862801, "Bearlake HDMI", patch_generic_hdmi),
4578HDA_CODEC_ENTRY(0x80862802, "Cantiga HDMI", patch_generic_hdmi),
4579HDA_CODEC_ENTRY(0x80862803, "Eaglelake HDMI", patch_generic_hdmi),
4580HDA_CODEC_ENTRY(0x80862804, "IbexPeak HDMI", patch_i915_cpt_hdmi),
4581HDA_CODEC_ENTRY(0x80862805, "CougarPoint HDMI", patch_i915_cpt_hdmi),
4582HDA_CODEC_ENTRY(0x80862806, "PantherPoint HDMI", patch_i915_cpt_hdmi),
4583HDA_CODEC_ENTRY(0x80862807, "Haswell HDMI", patch_i915_hsw_hdmi),
4584HDA_CODEC_ENTRY(0x80862808, "Broadwell HDMI", patch_i915_hsw_hdmi),
4585HDA_CODEC_ENTRY(0x80862809, "Skylake HDMI", patch_i915_hsw_hdmi),
4586HDA_CODEC_ENTRY(0x8086280a, "Broxton HDMI", patch_i915_hsw_hdmi),
4587HDA_CODEC_ENTRY(0x8086280b, "Kabylake HDMI", patch_i915_hsw_hdmi),
4588HDA_CODEC_ENTRY(0x8086280c, "Cannonlake HDMI", patch_i915_glk_hdmi),
4589HDA_CODEC_ENTRY(0x8086280d, "Geminilake HDMI", patch_i915_glk_hdmi),
4590HDA_CODEC_ENTRY(0x8086280f, "Icelake HDMI", patch_i915_icl_hdmi),
4591HDA_CODEC_ENTRY(0x80862812, "Tigerlake HDMI", patch_i915_tgl_hdmi),
4592HDA_CODEC_ENTRY(0x80862814, "DG1 HDMI", patch_i915_tgl_hdmi),
4593HDA_CODEC_ENTRY(0x80862815, "Alderlake HDMI", patch_i915_tgl_hdmi),
4594HDA_CODEC_ENTRY(0x80862816, "Rocketlake HDMI", patch_i915_tgl_hdmi),
4595HDA_CODEC_ENTRY(0x80862818, "Raptorlake HDMI", patch_i915_tgl_hdmi),
4596HDA_CODEC_ENTRY(0x80862819, "DG2 HDMI", patch_i915_adlp_hdmi),
4597HDA_CODEC_ENTRY(0x8086281a, "Jasperlake HDMI", patch_i915_icl_hdmi),
4598HDA_CODEC_ENTRY(0x8086281b, "Elkhartlake HDMI", patch_i915_icl_hdmi),
4599HDA_CODEC_ENTRY(0x8086281c, "Alderlake-P HDMI", patch_i915_adlp_hdmi),
4600HDA_CODEC_ENTRY(0x8086281f, "Raptorlake-P HDMI", patch_i915_adlp_hdmi),
4601HDA_CODEC_ENTRY(0x8086281d, "Meteorlake HDMI", patch_i915_adlp_hdmi),
4602HDA_CODEC_ENTRY(0x80862880, "CedarTrail HDMI", patch_generic_hdmi),
4603HDA_CODEC_ENTRY(0x80862882, "Valleyview2 HDMI", patch_i915_byt_hdmi),
4604HDA_CODEC_ENTRY(0x80862883, "Braswell HDMI", patch_i915_byt_hdmi),
4605HDA_CODEC_ENTRY(0x808629fb, "Crestline HDMI", patch_generic_hdmi),
4606/* special ID for generic HDMI */
4607HDA_CODEC_ENTRY(HDA_CODEC_ID_GENERIC_HDMI, "Generic HDMI", patch_generic_hdmi),
4608{} /* terminator */
4609};
4610MODULE_DEVICE_TABLE(hdaudio, snd_hda_id_hdmi);
4611
4612MODULE_LICENSE("GPL");
4613MODULE_DESCRIPTION("HDMI HD-audio codec");
4614MODULE_ALIAS("snd-hda-codec-intelhdmi");
4615MODULE_ALIAS("snd-hda-codec-nvhdmi");
4616MODULE_ALIAS("snd-hda-codec-atihdmi");
4617
4618static struct hda_codec_driver hdmi_driver = {
4619 .id = snd_hda_id_hdmi,
4620};
4621
4622module_hda_codec_driver(hdmi_driver);