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1// SPDX-License-Identifier: GPL-2.0
2
3#define pr_fmt(fmt) "DMAR-IR: " fmt
4
5#include <linux/interrupt.h>
6#include <linux/dmar.h>
7#include <linux/spinlock.h>
8#include <linux/slab.h>
9#include <linux/jiffies.h>
10#include <linux/hpet.h>
11#include <linux/pci.h>
12#include <linux/irq.h>
13#include <linux/intel-iommu.h>
14#include <linux/acpi.h>
15#include <linux/irqdomain.h>
16#include <linux/crash_dump.h>
17#include <asm/io_apic.h>
18#include <asm/apic.h>
19#include <asm/smp.h>
20#include <asm/cpu.h>
21#include <asm/irq_remapping.h>
22#include <asm/pci-direct.h>
23#include <asm/msidef.h>
24
25#include "../irq_remapping.h"
26
27enum irq_mode {
28 IRQ_REMAPPING,
29 IRQ_POSTING,
30};
31
32struct ioapic_scope {
33 struct intel_iommu *iommu;
34 unsigned int id;
35 unsigned int bus; /* PCI bus number */
36 unsigned int devfn; /* PCI devfn number */
37};
38
39struct hpet_scope {
40 struct intel_iommu *iommu;
41 u8 id;
42 unsigned int bus;
43 unsigned int devfn;
44};
45
46struct irq_2_iommu {
47 struct intel_iommu *iommu;
48 u16 irte_index;
49 u16 sub_handle;
50 u8 irte_mask;
51 enum irq_mode mode;
52};
53
54struct intel_ir_data {
55 struct irq_2_iommu irq_2_iommu;
56 struct irte irte_entry;
57 union {
58 struct msi_msg msi_entry;
59 };
60};
61
62#define IR_X2APIC_MODE(mode) (mode ? (1 << 11) : 0)
63#define IRTE_DEST(dest) ((eim_mode) ? dest : dest << 8)
64
65static int __read_mostly eim_mode;
66static struct ioapic_scope ir_ioapic[MAX_IO_APICS];
67static struct hpet_scope ir_hpet[MAX_HPET_TBS];
68
69/*
70 * Lock ordering:
71 * ->dmar_global_lock
72 * ->irq_2_ir_lock
73 * ->qi->q_lock
74 * ->iommu->register_lock
75 * Note:
76 * intel_irq_remap_ops.{supported,prepare,enable,disable,reenable} are called
77 * in single-threaded environment with interrupt disabled, so no need to tabke
78 * the dmar_global_lock.
79 */
80DEFINE_RAW_SPINLOCK(irq_2_ir_lock);
81static const struct irq_domain_ops intel_ir_domain_ops;
82
83static void iommu_disable_irq_remapping(struct intel_iommu *iommu);
84static int __init parse_ioapics_under_ir(void);
85
86static bool ir_pre_enabled(struct intel_iommu *iommu)
87{
88 return (iommu->flags & VTD_FLAG_IRQ_REMAP_PRE_ENABLED);
89}
90
91static void clear_ir_pre_enabled(struct intel_iommu *iommu)
92{
93 iommu->flags &= ~VTD_FLAG_IRQ_REMAP_PRE_ENABLED;
94}
95
96static void init_ir_status(struct intel_iommu *iommu)
97{
98 u32 gsts;
99
100 gsts = readl(iommu->reg + DMAR_GSTS_REG);
101 if (gsts & DMA_GSTS_IRES)
102 iommu->flags |= VTD_FLAG_IRQ_REMAP_PRE_ENABLED;
103}
104
105static int alloc_irte(struct intel_iommu *iommu,
106 struct irq_2_iommu *irq_iommu, u16 count)
107{
108 struct ir_table *table = iommu->ir_table;
109 unsigned int mask = 0;
110 unsigned long flags;
111 int index;
112
113 if (!count || !irq_iommu)
114 return -1;
115
116 if (count > 1) {
117 count = __roundup_pow_of_two(count);
118 mask = ilog2(count);
119 }
120
121 if (mask > ecap_max_handle_mask(iommu->ecap)) {
122 pr_err("Requested mask %x exceeds the max invalidation handle"
123 " mask value %Lx\n", mask,
124 ecap_max_handle_mask(iommu->ecap));
125 return -1;
126 }
127
128 raw_spin_lock_irqsave(&irq_2_ir_lock, flags);
129 index = bitmap_find_free_region(table->bitmap,
130 INTR_REMAP_TABLE_ENTRIES, mask);
131 if (index < 0) {
132 pr_warn("IR%d: can't allocate an IRTE\n", iommu->seq_id);
133 } else {
134 irq_iommu->iommu = iommu;
135 irq_iommu->irte_index = index;
136 irq_iommu->sub_handle = 0;
137 irq_iommu->irte_mask = mask;
138 irq_iommu->mode = IRQ_REMAPPING;
139 }
140 raw_spin_unlock_irqrestore(&irq_2_ir_lock, flags);
141
142 return index;
143}
144
145static int qi_flush_iec(struct intel_iommu *iommu, int index, int mask)
146{
147 struct qi_desc desc;
148
149 desc.qw0 = QI_IEC_IIDEX(index) | QI_IEC_TYPE | QI_IEC_IM(mask)
150 | QI_IEC_SELECTIVE;
151 desc.qw1 = 0;
152 desc.qw2 = 0;
153 desc.qw3 = 0;
154
155 return qi_submit_sync(iommu, &desc, 1, 0);
156}
157
158static int modify_irte(struct irq_2_iommu *irq_iommu,
159 struct irte *irte_modified)
160{
161 struct intel_iommu *iommu;
162 unsigned long flags;
163 struct irte *irte;
164 int rc, index;
165
166 if (!irq_iommu)
167 return -1;
168
169 raw_spin_lock_irqsave(&irq_2_ir_lock, flags);
170
171 iommu = irq_iommu->iommu;
172
173 index = irq_iommu->irte_index + irq_iommu->sub_handle;
174 irte = &iommu->ir_table->base[index];
175
176#if defined(CONFIG_HAVE_CMPXCHG_DOUBLE)
177 if ((irte->pst == 1) || (irte_modified->pst == 1)) {
178 bool ret;
179
180 ret = cmpxchg_double(&irte->low, &irte->high,
181 irte->low, irte->high,
182 irte_modified->low, irte_modified->high);
183 /*
184 * We use cmpxchg16 to atomically update the 128-bit IRTE,
185 * and it cannot be updated by the hardware or other processors
186 * behind us, so the return value of cmpxchg16 should be the
187 * same as the old value.
188 */
189 WARN_ON(!ret);
190 } else
191#endif
192 {
193 set_64bit(&irte->low, irte_modified->low);
194 set_64bit(&irte->high, irte_modified->high);
195 }
196 __iommu_flush_cache(iommu, irte, sizeof(*irte));
197
198 rc = qi_flush_iec(iommu, index, 0);
199
200 /* Update iommu mode according to the IRTE mode */
201 irq_iommu->mode = irte->pst ? IRQ_POSTING : IRQ_REMAPPING;
202 raw_spin_unlock_irqrestore(&irq_2_ir_lock, flags);
203
204 return rc;
205}
206
207static struct intel_iommu *map_hpet_to_ir(u8 hpet_id)
208{
209 int i;
210
211 for (i = 0; i < MAX_HPET_TBS; i++)
212 if (ir_hpet[i].id == hpet_id && ir_hpet[i].iommu)
213 return ir_hpet[i].iommu;
214 return NULL;
215}
216
217static struct intel_iommu *map_ioapic_to_ir(int apic)
218{
219 int i;
220
221 for (i = 0; i < MAX_IO_APICS; i++)
222 if (ir_ioapic[i].id == apic && ir_ioapic[i].iommu)
223 return ir_ioapic[i].iommu;
224 return NULL;
225}
226
227static struct intel_iommu *map_dev_to_ir(struct pci_dev *dev)
228{
229 struct dmar_drhd_unit *drhd;
230
231 drhd = dmar_find_matched_drhd_unit(dev);
232 if (!drhd)
233 return NULL;
234
235 return drhd->iommu;
236}
237
238static int clear_entries(struct irq_2_iommu *irq_iommu)
239{
240 struct irte *start, *entry, *end;
241 struct intel_iommu *iommu;
242 int index;
243
244 if (irq_iommu->sub_handle)
245 return 0;
246
247 iommu = irq_iommu->iommu;
248 index = irq_iommu->irte_index;
249
250 start = iommu->ir_table->base + index;
251 end = start + (1 << irq_iommu->irte_mask);
252
253 for (entry = start; entry < end; entry++) {
254 set_64bit(&entry->low, 0);
255 set_64bit(&entry->high, 0);
256 }
257 bitmap_release_region(iommu->ir_table->bitmap, index,
258 irq_iommu->irte_mask);
259
260 return qi_flush_iec(iommu, index, irq_iommu->irte_mask);
261}
262
263/*
264 * source validation type
265 */
266#define SVT_NO_VERIFY 0x0 /* no verification is required */
267#define SVT_VERIFY_SID_SQ 0x1 /* verify using SID and SQ fields */
268#define SVT_VERIFY_BUS 0x2 /* verify bus of request-id */
269
270/*
271 * source-id qualifier
272 */
273#define SQ_ALL_16 0x0 /* verify all 16 bits of request-id */
274#define SQ_13_IGNORE_1 0x1 /* verify most significant 13 bits, ignore
275 * the third least significant bit
276 */
277#define SQ_13_IGNORE_2 0x2 /* verify most significant 13 bits, ignore
278 * the second and third least significant bits
279 */
280#define SQ_13_IGNORE_3 0x3 /* verify most significant 13 bits, ignore
281 * the least three significant bits
282 */
283
284/*
285 * set SVT, SQ and SID fields of irte to verify
286 * source ids of interrupt requests
287 */
288static void set_irte_sid(struct irte *irte, unsigned int svt,
289 unsigned int sq, unsigned int sid)
290{
291 if (disable_sourceid_checking)
292 svt = SVT_NO_VERIFY;
293 irte->svt = svt;
294 irte->sq = sq;
295 irte->sid = sid;
296}
297
298/*
299 * Set an IRTE to match only the bus number. Interrupt requests that reference
300 * this IRTE must have a requester-id whose bus number is between or equal
301 * to the start_bus and end_bus arguments.
302 */
303static void set_irte_verify_bus(struct irte *irte, unsigned int start_bus,
304 unsigned int end_bus)
305{
306 set_irte_sid(irte, SVT_VERIFY_BUS, SQ_ALL_16,
307 (start_bus << 8) | end_bus);
308}
309
310static int set_ioapic_sid(struct irte *irte, int apic)
311{
312 int i;
313 u16 sid = 0;
314
315 if (!irte)
316 return -1;
317
318 down_read(&dmar_global_lock);
319 for (i = 0; i < MAX_IO_APICS; i++) {
320 if (ir_ioapic[i].iommu && ir_ioapic[i].id == apic) {
321 sid = (ir_ioapic[i].bus << 8) | ir_ioapic[i].devfn;
322 break;
323 }
324 }
325 up_read(&dmar_global_lock);
326
327 if (sid == 0) {
328 pr_warn("Failed to set source-id of IOAPIC (%d)\n", apic);
329 return -1;
330 }
331
332 set_irte_sid(irte, SVT_VERIFY_SID_SQ, SQ_ALL_16, sid);
333
334 return 0;
335}
336
337static int set_hpet_sid(struct irte *irte, u8 id)
338{
339 int i;
340 u16 sid = 0;
341
342 if (!irte)
343 return -1;
344
345 down_read(&dmar_global_lock);
346 for (i = 0; i < MAX_HPET_TBS; i++) {
347 if (ir_hpet[i].iommu && ir_hpet[i].id == id) {
348 sid = (ir_hpet[i].bus << 8) | ir_hpet[i].devfn;
349 break;
350 }
351 }
352 up_read(&dmar_global_lock);
353
354 if (sid == 0) {
355 pr_warn("Failed to set source-id of HPET block (%d)\n", id);
356 return -1;
357 }
358
359 /*
360 * Should really use SQ_ALL_16. Some platforms are broken.
361 * While we figure out the right quirks for these broken platforms, use
362 * SQ_13_IGNORE_3 for now.
363 */
364 set_irte_sid(irte, SVT_VERIFY_SID_SQ, SQ_13_IGNORE_3, sid);
365
366 return 0;
367}
368
369struct set_msi_sid_data {
370 struct pci_dev *pdev;
371 u16 alias;
372 int count;
373 int busmatch_count;
374};
375
376static int set_msi_sid_cb(struct pci_dev *pdev, u16 alias, void *opaque)
377{
378 struct set_msi_sid_data *data = opaque;
379
380 if (data->count == 0 || PCI_BUS_NUM(alias) == PCI_BUS_NUM(data->alias))
381 data->busmatch_count++;
382
383 data->pdev = pdev;
384 data->alias = alias;
385 data->count++;
386
387 return 0;
388}
389
390static int set_msi_sid(struct irte *irte, struct pci_dev *dev)
391{
392 struct set_msi_sid_data data;
393
394 if (!irte || !dev)
395 return -1;
396
397 data.count = 0;
398 data.busmatch_count = 0;
399 pci_for_each_dma_alias(dev, set_msi_sid_cb, &data);
400
401 /*
402 * DMA alias provides us with a PCI device and alias. The only case
403 * where the it will return an alias on a different bus than the
404 * device is the case of a PCIe-to-PCI bridge, where the alias is for
405 * the subordinate bus. In this case we can only verify the bus.
406 *
407 * If there are multiple aliases, all with the same bus number,
408 * then all we can do is verify the bus. This is typical in NTB
409 * hardware which use proxy IDs where the device will generate traffic
410 * from multiple devfn numbers on the same bus.
411 *
412 * If the alias device is on a different bus than our source device
413 * then we have a topology based alias, use it.
414 *
415 * Otherwise, the alias is for a device DMA quirk and we cannot
416 * assume that MSI uses the same requester ID. Therefore use the
417 * original device.
418 */
419 if (PCI_BUS_NUM(data.alias) != data.pdev->bus->number)
420 set_irte_verify_bus(irte, PCI_BUS_NUM(data.alias),
421 dev->bus->number);
422 else if (data.count >= 2 && data.busmatch_count == data.count)
423 set_irte_verify_bus(irte, dev->bus->number, dev->bus->number);
424 else if (data.pdev->bus->number != dev->bus->number)
425 set_irte_sid(irte, SVT_VERIFY_SID_SQ, SQ_ALL_16, data.alias);
426 else
427 set_irte_sid(irte, SVT_VERIFY_SID_SQ, SQ_ALL_16,
428 pci_dev_id(dev));
429
430 return 0;
431}
432
433static int iommu_load_old_irte(struct intel_iommu *iommu)
434{
435 struct irte *old_ir_table;
436 phys_addr_t irt_phys;
437 unsigned int i;
438 size_t size;
439 u64 irta;
440
441 /* Check whether the old ir-table has the same size as ours */
442 irta = dmar_readq(iommu->reg + DMAR_IRTA_REG);
443 if ((irta & INTR_REMAP_TABLE_REG_SIZE_MASK)
444 != INTR_REMAP_TABLE_REG_SIZE)
445 return -EINVAL;
446
447 irt_phys = irta & VTD_PAGE_MASK;
448 size = INTR_REMAP_TABLE_ENTRIES*sizeof(struct irte);
449
450 /* Map the old IR table */
451 old_ir_table = memremap(irt_phys, size, MEMREMAP_WB);
452 if (!old_ir_table)
453 return -ENOMEM;
454
455 /* Copy data over */
456 memcpy(iommu->ir_table->base, old_ir_table, size);
457
458 __iommu_flush_cache(iommu, iommu->ir_table->base, size);
459
460 /*
461 * Now check the table for used entries and mark those as
462 * allocated in the bitmap
463 */
464 for (i = 0; i < INTR_REMAP_TABLE_ENTRIES; i++) {
465 if (iommu->ir_table->base[i].present)
466 bitmap_set(iommu->ir_table->bitmap, i, 1);
467 }
468
469 memunmap(old_ir_table);
470
471 return 0;
472}
473
474
475static void iommu_set_irq_remapping(struct intel_iommu *iommu, int mode)
476{
477 unsigned long flags;
478 u64 addr;
479 u32 sts;
480
481 addr = virt_to_phys((void *)iommu->ir_table->base);
482
483 raw_spin_lock_irqsave(&iommu->register_lock, flags);
484
485 dmar_writeq(iommu->reg + DMAR_IRTA_REG,
486 (addr) | IR_X2APIC_MODE(mode) | INTR_REMAP_TABLE_REG_SIZE);
487
488 /* Set interrupt-remapping table pointer */
489 writel(iommu->gcmd | DMA_GCMD_SIRTP, iommu->reg + DMAR_GCMD_REG);
490
491 IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
492 readl, (sts & DMA_GSTS_IRTPS), sts);
493 raw_spin_unlock_irqrestore(&iommu->register_lock, flags);
494
495 /*
496 * Global invalidation of interrupt entry cache to make sure the
497 * hardware uses the new irq remapping table.
498 */
499 qi_global_iec(iommu);
500}
501
502static void iommu_enable_irq_remapping(struct intel_iommu *iommu)
503{
504 unsigned long flags;
505 u32 sts;
506
507 raw_spin_lock_irqsave(&iommu->register_lock, flags);
508
509 /* Enable interrupt-remapping */
510 iommu->gcmd |= DMA_GCMD_IRE;
511 writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG);
512 IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
513 readl, (sts & DMA_GSTS_IRES), sts);
514
515 /* Block compatibility-format MSIs */
516 if (sts & DMA_GSTS_CFIS) {
517 iommu->gcmd &= ~DMA_GCMD_CFI;
518 writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG);
519 IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
520 readl, !(sts & DMA_GSTS_CFIS), sts);
521 }
522
523 /*
524 * With CFI clear in the Global Command register, we should be
525 * protected from dangerous (i.e. compatibility) interrupts
526 * regardless of x2apic status. Check just to be sure.
527 */
528 if (sts & DMA_GSTS_CFIS)
529 WARN(1, KERN_WARNING
530 "Compatibility-format IRQs enabled despite intr remapping;\n"
531 "you are vulnerable to IRQ injection.\n");
532
533 raw_spin_unlock_irqrestore(&iommu->register_lock, flags);
534}
535
536static int intel_setup_irq_remapping(struct intel_iommu *iommu)
537{
538 struct ir_table *ir_table;
539 struct fwnode_handle *fn;
540 unsigned long *bitmap;
541 struct page *pages;
542
543 if (iommu->ir_table)
544 return 0;
545
546 ir_table = kzalloc(sizeof(struct ir_table), GFP_KERNEL);
547 if (!ir_table)
548 return -ENOMEM;
549
550 pages = alloc_pages_node(iommu->node, GFP_KERNEL | __GFP_ZERO,
551 INTR_REMAP_PAGE_ORDER);
552 if (!pages) {
553 pr_err("IR%d: failed to allocate pages of order %d\n",
554 iommu->seq_id, INTR_REMAP_PAGE_ORDER);
555 goto out_free_table;
556 }
557
558 bitmap = bitmap_zalloc(INTR_REMAP_TABLE_ENTRIES, GFP_ATOMIC);
559 if (bitmap == NULL) {
560 pr_err("IR%d: failed to allocate bitmap\n", iommu->seq_id);
561 goto out_free_pages;
562 }
563
564 fn = irq_domain_alloc_named_id_fwnode("INTEL-IR", iommu->seq_id);
565 if (!fn)
566 goto out_free_bitmap;
567
568 iommu->ir_domain =
569 irq_domain_create_hierarchy(arch_get_ir_parent_domain(),
570 0, INTR_REMAP_TABLE_ENTRIES,
571 fn, &intel_ir_domain_ops,
572 iommu);
573 if (!iommu->ir_domain) {
574 irq_domain_free_fwnode(fn);
575 pr_err("IR%d: failed to allocate irqdomain\n", iommu->seq_id);
576 goto out_free_bitmap;
577 }
578 iommu->ir_msi_domain =
579 arch_create_remap_msi_irq_domain(iommu->ir_domain,
580 "INTEL-IR-MSI",
581 iommu->seq_id);
582
583 ir_table->base = page_address(pages);
584 ir_table->bitmap = bitmap;
585 iommu->ir_table = ir_table;
586
587 /*
588 * If the queued invalidation is already initialized,
589 * shouldn't disable it.
590 */
591 if (!iommu->qi) {
592 /*
593 * Clear previous faults.
594 */
595 dmar_fault(-1, iommu);
596 dmar_disable_qi(iommu);
597
598 if (dmar_enable_qi(iommu)) {
599 pr_err("Failed to enable queued invalidation\n");
600 goto out_free_bitmap;
601 }
602 }
603
604 init_ir_status(iommu);
605
606 if (ir_pre_enabled(iommu)) {
607 if (!is_kdump_kernel()) {
608 pr_warn("IRQ remapping was enabled on %s but we are not in kdump mode\n",
609 iommu->name);
610 clear_ir_pre_enabled(iommu);
611 iommu_disable_irq_remapping(iommu);
612 } else if (iommu_load_old_irte(iommu))
613 pr_err("Failed to copy IR table for %s from previous kernel\n",
614 iommu->name);
615 else
616 pr_info("Copied IR table for %s from previous kernel\n",
617 iommu->name);
618 }
619
620 iommu_set_irq_remapping(iommu, eim_mode);
621
622 return 0;
623
624out_free_bitmap:
625 bitmap_free(bitmap);
626out_free_pages:
627 __free_pages(pages, INTR_REMAP_PAGE_ORDER);
628out_free_table:
629 kfree(ir_table);
630
631 iommu->ir_table = NULL;
632
633 return -ENOMEM;
634}
635
636static void intel_teardown_irq_remapping(struct intel_iommu *iommu)
637{
638 struct fwnode_handle *fn;
639
640 if (iommu && iommu->ir_table) {
641 if (iommu->ir_msi_domain) {
642 fn = iommu->ir_msi_domain->fwnode;
643
644 irq_domain_remove(iommu->ir_msi_domain);
645 irq_domain_free_fwnode(fn);
646 iommu->ir_msi_domain = NULL;
647 }
648 if (iommu->ir_domain) {
649 fn = iommu->ir_domain->fwnode;
650
651 irq_domain_remove(iommu->ir_domain);
652 irq_domain_free_fwnode(fn);
653 iommu->ir_domain = NULL;
654 }
655 free_pages((unsigned long)iommu->ir_table->base,
656 INTR_REMAP_PAGE_ORDER);
657 bitmap_free(iommu->ir_table->bitmap);
658 kfree(iommu->ir_table);
659 iommu->ir_table = NULL;
660 }
661}
662
663/*
664 * Disable Interrupt Remapping.
665 */
666static void iommu_disable_irq_remapping(struct intel_iommu *iommu)
667{
668 unsigned long flags;
669 u32 sts;
670
671 if (!ecap_ir_support(iommu->ecap))
672 return;
673
674 /*
675 * global invalidation of interrupt entry cache before disabling
676 * interrupt-remapping.
677 */
678 qi_global_iec(iommu);
679
680 raw_spin_lock_irqsave(&iommu->register_lock, flags);
681
682 sts = readl(iommu->reg + DMAR_GSTS_REG);
683 if (!(sts & DMA_GSTS_IRES))
684 goto end;
685
686 iommu->gcmd &= ~DMA_GCMD_IRE;
687 writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG);
688
689 IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
690 readl, !(sts & DMA_GSTS_IRES), sts);
691
692end:
693 raw_spin_unlock_irqrestore(&iommu->register_lock, flags);
694}
695
696static int __init dmar_x2apic_optout(void)
697{
698 struct acpi_table_dmar *dmar;
699 dmar = (struct acpi_table_dmar *)dmar_tbl;
700 if (!dmar || no_x2apic_optout)
701 return 0;
702 return dmar->flags & DMAR_X2APIC_OPT_OUT;
703}
704
705static void __init intel_cleanup_irq_remapping(void)
706{
707 struct dmar_drhd_unit *drhd;
708 struct intel_iommu *iommu;
709
710 for_each_iommu(iommu, drhd) {
711 if (ecap_ir_support(iommu->ecap)) {
712 iommu_disable_irq_remapping(iommu);
713 intel_teardown_irq_remapping(iommu);
714 }
715 }
716
717 if (x2apic_supported())
718 pr_warn("Failed to enable irq remapping. You are vulnerable to irq-injection attacks.\n");
719}
720
721static int __init intel_prepare_irq_remapping(void)
722{
723 struct dmar_drhd_unit *drhd;
724 struct intel_iommu *iommu;
725 int eim = 0;
726
727 if (irq_remap_broken) {
728 pr_warn("This system BIOS has enabled interrupt remapping\n"
729 "on a chipset that contains an erratum making that\n"
730 "feature unstable. To maintain system stability\n"
731 "interrupt remapping is being disabled. Please\n"
732 "contact your BIOS vendor for an update\n");
733 add_taint(TAINT_FIRMWARE_WORKAROUND, LOCKDEP_STILL_OK);
734 return -ENODEV;
735 }
736
737 if (dmar_table_init() < 0)
738 return -ENODEV;
739
740 if (!dmar_ir_support())
741 return -ENODEV;
742
743 if (parse_ioapics_under_ir()) {
744 pr_info("Not enabling interrupt remapping\n");
745 goto error;
746 }
747
748 /* First make sure all IOMMUs support IRQ remapping */
749 for_each_iommu(iommu, drhd)
750 if (!ecap_ir_support(iommu->ecap))
751 goto error;
752
753 /* Detect remapping mode: lapic or x2apic */
754 if (x2apic_supported()) {
755 eim = !dmar_x2apic_optout();
756 if (!eim) {
757 pr_info("x2apic is disabled because BIOS sets x2apic opt out bit.");
758 pr_info("Use 'intremap=no_x2apic_optout' to override the BIOS setting.\n");
759 }
760 }
761
762 for_each_iommu(iommu, drhd) {
763 if (eim && !ecap_eim_support(iommu->ecap)) {
764 pr_info("%s does not support EIM\n", iommu->name);
765 eim = 0;
766 }
767 }
768
769 eim_mode = eim;
770 if (eim)
771 pr_info("Queued invalidation will be enabled to support x2apic and Intr-remapping.\n");
772
773 /* Do the initializations early */
774 for_each_iommu(iommu, drhd) {
775 if (intel_setup_irq_remapping(iommu)) {
776 pr_err("Failed to setup irq remapping for %s\n",
777 iommu->name);
778 goto error;
779 }
780 }
781
782 return 0;
783
784error:
785 intel_cleanup_irq_remapping();
786 return -ENODEV;
787}
788
789/*
790 * Set Posted-Interrupts capability.
791 */
792static inline void set_irq_posting_cap(void)
793{
794 struct dmar_drhd_unit *drhd;
795 struct intel_iommu *iommu;
796
797 if (!disable_irq_post) {
798 /*
799 * If IRTE is in posted format, the 'pda' field goes across the
800 * 64-bit boundary, we need use cmpxchg16b to atomically update
801 * it. We only expose posted-interrupt when X86_FEATURE_CX16
802 * is supported. Actually, hardware platforms supporting PI
803 * should have X86_FEATURE_CX16 support, this has been confirmed
804 * with Intel hardware guys.
805 */
806 if (boot_cpu_has(X86_FEATURE_CX16))
807 intel_irq_remap_ops.capability |= 1 << IRQ_POSTING_CAP;
808
809 for_each_iommu(iommu, drhd)
810 if (!cap_pi_support(iommu->cap)) {
811 intel_irq_remap_ops.capability &=
812 ~(1 << IRQ_POSTING_CAP);
813 break;
814 }
815 }
816}
817
818static int __init intel_enable_irq_remapping(void)
819{
820 struct dmar_drhd_unit *drhd;
821 struct intel_iommu *iommu;
822 bool setup = false;
823
824 /*
825 * Setup Interrupt-remapping for all the DRHD's now.
826 */
827 for_each_iommu(iommu, drhd) {
828 if (!ir_pre_enabled(iommu))
829 iommu_enable_irq_remapping(iommu);
830 setup = true;
831 }
832
833 if (!setup)
834 goto error;
835
836 irq_remapping_enabled = 1;
837
838 set_irq_posting_cap();
839
840 pr_info("Enabled IRQ remapping in %s mode\n", eim_mode ? "x2apic" : "xapic");
841
842 return eim_mode ? IRQ_REMAP_X2APIC_MODE : IRQ_REMAP_XAPIC_MODE;
843
844error:
845 intel_cleanup_irq_remapping();
846 return -1;
847}
848
849static int ir_parse_one_hpet_scope(struct acpi_dmar_device_scope *scope,
850 struct intel_iommu *iommu,
851 struct acpi_dmar_hardware_unit *drhd)
852{
853 struct acpi_dmar_pci_path *path;
854 u8 bus;
855 int count, free = -1;
856
857 bus = scope->bus;
858 path = (struct acpi_dmar_pci_path *)(scope + 1);
859 count = (scope->length - sizeof(struct acpi_dmar_device_scope))
860 / sizeof(struct acpi_dmar_pci_path);
861
862 while (--count > 0) {
863 /*
864 * Access PCI directly due to the PCI
865 * subsystem isn't initialized yet.
866 */
867 bus = read_pci_config_byte(bus, path->device, path->function,
868 PCI_SECONDARY_BUS);
869 path++;
870 }
871
872 for (count = 0; count < MAX_HPET_TBS; count++) {
873 if (ir_hpet[count].iommu == iommu &&
874 ir_hpet[count].id == scope->enumeration_id)
875 return 0;
876 else if (ir_hpet[count].iommu == NULL && free == -1)
877 free = count;
878 }
879 if (free == -1) {
880 pr_warn("Exceeded Max HPET blocks\n");
881 return -ENOSPC;
882 }
883
884 ir_hpet[free].iommu = iommu;
885 ir_hpet[free].id = scope->enumeration_id;
886 ir_hpet[free].bus = bus;
887 ir_hpet[free].devfn = PCI_DEVFN(path->device, path->function);
888 pr_info("HPET id %d under DRHD base 0x%Lx\n",
889 scope->enumeration_id, drhd->address);
890
891 return 0;
892}
893
894static int ir_parse_one_ioapic_scope(struct acpi_dmar_device_scope *scope,
895 struct intel_iommu *iommu,
896 struct acpi_dmar_hardware_unit *drhd)
897{
898 struct acpi_dmar_pci_path *path;
899 u8 bus;
900 int count, free = -1;
901
902 bus = scope->bus;
903 path = (struct acpi_dmar_pci_path *)(scope + 1);
904 count = (scope->length - sizeof(struct acpi_dmar_device_scope))
905 / sizeof(struct acpi_dmar_pci_path);
906
907 while (--count > 0) {
908 /*
909 * Access PCI directly due to the PCI
910 * subsystem isn't initialized yet.
911 */
912 bus = read_pci_config_byte(bus, path->device, path->function,
913 PCI_SECONDARY_BUS);
914 path++;
915 }
916
917 for (count = 0; count < MAX_IO_APICS; count++) {
918 if (ir_ioapic[count].iommu == iommu &&
919 ir_ioapic[count].id == scope->enumeration_id)
920 return 0;
921 else if (ir_ioapic[count].iommu == NULL && free == -1)
922 free = count;
923 }
924 if (free == -1) {
925 pr_warn("Exceeded Max IO APICS\n");
926 return -ENOSPC;
927 }
928
929 ir_ioapic[free].bus = bus;
930 ir_ioapic[free].devfn = PCI_DEVFN(path->device, path->function);
931 ir_ioapic[free].iommu = iommu;
932 ir_ioapic[free].id = scope->enumeration_id;
933 pr_info("IOAPIC id %d under DRHD base 0x%Lx IOMMU %d\n",
934 scope->enumeration_id, drhd->address, iommu->seq_id);
935
936 return 0;
937}
938
939static int ir_parse_ioapic_hpet_scope(struct acpi_dmar_header *header,
940 struct intel_iommu *iommu)
941{
942 int ret = 0;
943 struct acpi_dmar_hardware_unit *drhd;
944 struct acpi_dmar_device_scope *scope;
945 void *start, *end;
946
947 drhd = (struct acpi_dmar_hardware_unit *)header;
948 start = (void *)(drhd + 1);
949 end = ((void *)drhd) + header->length;
950
951 while (start < end && ret == 0) {
952 scope = start;
953 if (scope->entry_type == ACPI_DMAR_SCOPE_TYPE_IOAPIC)
954 ret = ir_parse_one_ioapic_scope(scope, iommu, drhd);
955 else if (scope->entry_type == ACPI_DMAR_SCOPE_TYPE_HPET)
956 ret = ir_parse_one_hpet_scope(scope, iommu, drhd);
957 start += scope->length;
958 }
959
960 return ret;
961}
962
963static void ir_remove_ioapic_hpet_scope(struct intel_iommu *iommu)
964{
965 int i;
966
967 for (i = 0; i < MAX_HPET_TBS; i++)
968 if (ir_hpet[i].iommu == iommu)
969 ir_hpet[i].iommu = NULL;
970
971 for (i = 0; i < MAX_IO_APICS; i++)
972 if (ir_ioapic[i].iommu == iommu)
973 ir_ioapic[i].iommu = NULL;
974}
975
976/*
977 * Finds the assocaition between IOAPIC's and its Interrupt-remapping
978 * hardware unit.
979 */
980static int __init parse_ioapics_under_ir(void)
981{
982 struct dmar_drhd_unit *drhd;
983 struct intel_iommu *iommu;
984 bool ir_supported = false;
985 int ioapic_idx;
986
987 for_each_iommu(iommu, drhd) {
988 int ret;
989
990 if (!ecap_ir_support(iommu->ecap))
991 continue;
992
993 ret = ir_parse_ioapic_hpet_scope(drhd->hdr, iommu);
994 if (ret)
995 return ret;
996
997 ir_supported = true;
998 }
999
1000 if (!ir_supported)
1001 return -ENODEV;
1002
1003 for (ioapic_idx = 0; ioapic_idx < nr_ioapics; ioapic_idx++) {
1004 int ioapic_id = mpc_ioapic_id(ioapic_idx);
1005 if (!map_ioapic_to_ir(ioapic_id)) {
1006 pr_err(FW_BUG "ioapic %d has no mapping iommu, "
1007 "interrupt remapping will be disabled\n",
1008 ioapic_id);
1009 return -1;
1010 }
1011 }
1012
1013 return 0;
1014}
1015
1016static int __init ir_dev_scope_init(void)
1017{
1018 int ret;
1019
1020 if (!irq_remapping_enabled)
1021 return 0;
1022
1023 down_write(&dmar_global_lock);
1024 ret = dmar_dev_scope_init();
1025 up_write(&dmar_global_lock);
1026
1027 return ret;
1028}
1029rootfs_initcall(ir_dev_scope_init);
1030
1031static void disable_irq_remapping(void)
1032{
1033 struct dmar_drhd_unit *drhd;
1034 struct intel_iommu *iommu = NULL;
1035
1036 /*
1037 * Disable Interrupt-remapping for all the DRHD's now.
1038 */
1039 for_each_iommu(iommu, drhd) {
1040 if (!ecap_ir_support(iommu->ecap))
1041 continue;
1042
1043 iommu_disable_irq_remapping(iommu);
1044 }
1045
1046 /*
1047 * Clear Posted-Interrupts capability.
1048 */
1049 if (!disable_irq_post)
1050 intel_irq_remap_ops.capability &= ~(1 << IRQ_POSTING_CAP);
1051}
1052
1053static int reenable_irq_remapping(int eim)
1054{
1055 struct dmar_drhd_unit *drhd;
1056 bool setup = false;
1057 struct intel_iommu *iommu = NULL;
1058
1059 for_each_iommu(iommu, drhd)
1060 if (iommu->qi)
1061 dmar_reenable_qi(iommu);
1062
1063 /*
1064 * Setup Interrupt-remapping for all the DRHD's now.
1065 */
1066 for_each_iommu(iommu, drhd) {
1067 if (!ecap_ir_support(iommu->ecap))
1068 continue;
1069
1070 /* Set up interrupt remapping for iommu.*/
1071 iommu_set_irq_remapping(iommu, eim);
1072 iommu_enable_irq_remapping(iommu);
1073 setup = true;
1074 }
1075
1076 if (!setup)
1077 goto error;
1078
1079 set_irq_posting_cap();
1080
1081 return 0;
1082
1083error:
1084 /*
1085 * handle error condition gracefully here!
1086 */
1087 return -1;
1088}
1089
1090static void prepare_irte(struct irte *irte, int vector, unsigned int dest)
1091{
1092 memset(irte, 0, sizeof(*irte));
1093
1094 irte->present = 1;
1095 irte->dst_mode = apic->irq_dest_mode;
1096 /*
1097 * Trigger mode in the IRTE will always be edge, and for IO-APIC, the
1098 * actual level or edge trigger will be setup in the IO-APIC
1099 * RTE. This will help simplify level triggered irq migration.
1100 * For more details, see the comments (in io_apic.c) explainig IO-APIC
1101 * irq migration in the presence of interrupt-remapping.
1102 */
1103 irte->trigger_mode = 0;
1104 irte->dlvry_mode = apic->irq_delivery_mode;
1105 irte->vector = vector;
1106 irte->dest_id = IRTE_DEST(dest);
1107 irte->redir_hint = 1;
1108}
1109
1110static struct irq_domain *intel_get_ir_irq_domain(struct irq_alloc_info *info)
1111{
1112 struct intel_iommu *iommu = NULL;
1113
1114 if (!info)
1115 return NULL;
1116
1117 switch (info->type) {
1118 case X86_IRQ_ALLOC_TYPE_IOAPIC:
1119 iommu = map_ioapic_to_ir(info->ioapic_id);
1120 break;
1121 case X86_IRQ_ALLOC_TYPE_HPET:
1122 iommu = map_hpet_to_ir(info->hpet_id);
1123 break;
1124 case X86_IRQ_ALLOC_TYPE_MSI:
1125 case X86_IRQ_ALLOC_TYPE_MSIX:
1126 iommu = map_dev_to_ir(info->msi_dev);
1127 break;
1128 default:
1129 BUG_ON(1);
1130 break;
1131 }
1132
1133 return iommu ? iommu->ir_domain : NULL;
1134}
1135
1136static struct irq_domain *intel_get_irq_domain(struct irq_alloc_info *info)
1137{
1138 struct intel_iommu *iommu;
1139
1140 if (!info)
1141 return NULL;
1142
1143 switch (info->type) {
1144 case X86_IRQ_ALLOC_TYPE_MSI:
1145 case X86_IRQ_ALLOC_TYPE_MSIX:
1146 iommu = map_dev_to_ir(info->msi_dev);
1147 if (iommu)
1148 return iommu->ir_msi_domain;
1149 break;
1150 default:
1151 break;
1152 }
1153
1154 return NULL;
1155}
1156
1157struct irq_remap_ops intel_irq_remap_ops = {
1158 .prepare = intel_prepare_irq_remapping,
1159 .enable = intel_enable_irq_remapping,
1160 .disable = disable_irq_remapping,
1161 .reenable = reenable_irq_remapping,
1162 .enable_faulting = enable_drhd_fault_handling,
1163 .get_ir_irq_domain = intel_get_ir_irq_domain,
1164 .get_irq_domain = intel_get_irq_domain,
1165};
1166
1167static void intel_ir_reconfigure_irte(struct irq_data *irqd, bool force)
1168{
1169 struct intel_ir_data *ir_data = irqd->chip_data;
1170 struct irte *irte = &ir_data->irte_entry;
1171 struct irq_cfg *cfg = irqd_cfg(irqd);
1172
1173 /*
1174 * Atomically updates the IRTE with the new destination, vector
1175 * and flushes the interrupt entry cache.
1176 */
1177 irte->vector = cfg->vector;
1178 irte->dest_id = IRTE_DEST(cfg->dest_apicid);
1179
1180 /* Update the hardware only if the interrupt is in remapped mode. */
1181 if (force || ir_data->irq_2_iommu.mode == IRQ_REMAPPING)
1182 modify_irte(&ir_data->irq_2_iommu, irte);
1183}
1184
1185/*
1186 * Migrate the IO-APIC irq in the presence of intr-remapping.
1187 *
1188 * For both level and edge triggered, irq migration is a simple atomic
1189 * update(of vector and cpu destination) of IRTE and flush the hardware cache.
1190 *
1191 * For level triggered, we eliminate the io-apic RTE modification (with the
1192 * updated vector information), by using a virtual vector (io-apic pin number).
1193 * Real vector that is used for interrupting cpu will be coming from
1194 * the interrupt-remapping table entry.
1195 *
1196 * As the migration is a simple atomic update of IRTE, the same mechanism
1197 * is used to migrate MSI irq's in the presence of interrupt-remapping.
1198 */
1199static int
1200intel_ir_set_affinity(struct irq_data *data, const struct cpumask *mask,
1201 bool force)
1202{
1203 struct irq_data *parent = data->parent_data;
1204 struct irq_cfg *cfg = irqd_cfg(data);
1205 int ret;
1206
1207 ret = parent->chip->irq_set_affinity(parent, mask, force);
1208 if (ret < 0 || ret == IRQ_SET_MASK_OK_DONE)
1209 return ret;
1210
1211 intel_ir_reconfigure_irte(data, false);
1212 /*
1213 * After this point, all the interrupts will start arriving
1214 * at the new destination. So, time to cleanup the previous
1215 * vector allocation.
1216 */
1217 send_cleanup_vector(cfg);
1218
1219 return IRQ_SET_MASK_OK_DONE;
1220}
1221
1222static void intel_ir_compose_msi_msg(struct irq_data *irq_data,
1223 struct msi_msg *msg)
1224{
1225 struct intel_ir_data *ir_data = irq_data->chip_data;
1226
1227 *msg = ir_data->msi_entry;
1228}
1229
1230static int intel_ir_set_vcpu_affinity(struct irq_data *data, void *info)
1231{
1232 struct intel_ir_data *ir_data = data->chip_data;
1233 struct vcpu_data *vcpu_pi_info = info;
1234
1235 /* stop posting interrupts, back to remapping mode */
1236 if (!vcpu_pi_info) {
1237 modify_irte(&ir_data->irq_2_iommu, &ir_data->irte_entry);
1238 } else {
1239 struct irte irte_pi;
1240
1241 /*
1242 * We are not caching the posted interrupt entry. We
1243 * copy the data from the remapped entry and modify
1244 * the fields which are relevant for posted mode. The
1245 * cached remapped entry is used for switching back to
1246 * remapped mode.
1247 */
1248 memset(&irte_pi, 0, sizeof(irte_pi));
1249 dmar_copy_shared_irte(&irte_pi, &ir_data->irte_entry);
1250
1251 /* Update the posted mode fields */
1252 irte_pi.p_pst = 1;
1253 irte_pi.p_urgent = 0;
1254 irte_pi.p_vector = vcpu_pi_info->vector;
1255 irte_pi.pda_l = (vcpu_pi_info->pi_desc_addr >>
1256 (32 - PDA_LOW_BIT)) & ~(-1UL << PDA_LOW_BIT);
1257 irte_pi.pda_h = (vcpu_pi_info->pi_desc_addr >> 32) &
1258 ~(-1UL << PDA_HIGH_BIT);
1259
1260 modify_irte(&ir_data->irq_2_iommu, &irte_pi);
1261 }
1262
1263 return 0;
1264}
1265
1266static struct irq_chip intel_ir_chip = {
1267 .name = "INTEL-IR",
1268 .irq_ack = apic_ack_irq,
1269 .irq_set_affinity = intel_ir_set_affinity,
1270 .irq_compose_msi_msg = intel_ir_compose_msi_msg,
1271 .irq_set_vcpu_affinity = intel_ir_set_vcpu_affinity,
1272};
1273
1274static void intel_irq_remapping_prepare_irte(struct intel_ir_data *data,
1275 struct irq_cfg *irq_cfg,
1276 struct irq_alloc_info *info,
1277 int index, int sub_handle)
1278{
1279 struct IR_IO_APIC_route_entry *entry;
1280 struct irte *irte = &data->irte_entry;
1281 struct msi_msg *msg = &data->msi_entry;
1282
1283 prepare_irte(irte, irq_cfg->vector, irq_cfg->dest_apicid);
1284 switch (info->type) {
1285 case X86_IRQ_ALLOC_TYPE_IOAPIC:
1286 /* Set source-id of interrupt request */
1287 set_ioapic_sid(irte, info->ioapic_id);
1288 apic_printk(APIC_VERBOSE, KERN_DEBUG "IOAPIC[%d]: Set IRTE entry (P:%d FPD:%d Dst_Mode:%d Redir_hint:%d Trig_Mode:%d Dlvry_Mode:%X Avail:%X Vector:%02X Dest:%08X SID:%04X SQ:%X SVT:%X)\n",
1289 info->ioapic_id, irte->present, irte->fpd,
1290 irte->dst_mode, irte->redir_hint,
1291 irte->trigger_mode, irte->dlvry_mode,
1292 irte->avail, irte->vector, irte->dest_id,
1293 irte->sid, irte->sq, irte->svt);
1294
1295 entry = (struct IR_IO_APIC_route_entry *)info->ioapic_entry;
1296 info->ioapic_entry = NULL;
1297 memset(entry, 0, sizeof(*entry));
1298 entry->index2 = (index >> 15) & 0x1;
1299 entry->zero = 0;
1300 entry->format = 1;
1301 entry->index = (index & 0x7fff);
1302 /*
1303 * IO-APIC RTE will be configured with virtual vector.
1304 * irq handler will do the explicit EOI to the io-apic.
1305 */
1306 entry->vector = info->ioapic_pin;
1307 entry->mask = 0; /* enable IRQ */
1308 entry->trigger = info->ioapic_trigger;
1309 entry->polarity = info->ioapic_polarity;
1310 if (info->ioapic_trigger)
1311 entry->mask = 1; /* Mask level triggered irqs. */
1312 break;
1313
1314 case X86_IRQ_ALLOC_TYPE_HPET:
1315 case X86_IRQ_ALLOC_TYPE_MSI:
1316 case X86_IRQ_ALLOC_TYPE_MSIX:
1317 if (info->type == X86_IRQ_ALLOC_TYPE_HPET)
1318 set_hpet_sid(irte, info->hpet_id);
1319 else
1320 set_msi_sid(irte, info->msi_dev);
1321
1322 msg->address_hi = MSI_ADDR_BASE_HI;
1323 msg->data = sub_handle;
1324 msg->address_lo = MSI_ADDR_BASE_LO | MSI_ADDR_IR_EXT_INT |
1325 MSI_ADDR_IR_SHV |
1326 MSI_ADDR_IR_INDEX1(index) |
1327 MSI_ADDR_IR_INDEX2(index);
1328 break;
1329
1330 default:
1331 BUG_ON(1);
1332 break;
1333 }
1334}
1335
1336static void intel_free_irq_resources(struct irq_domain *domain,
1337 unsigned int virq, unsigned int nr_irqs)
1338{
1339 struct irq_data *irq_data;
1340 struct intel_ir_data *data;
1341 struct irq_2_iommu *irq_iommu;
1342 unsigned long flags;
1343 int i;
1344 for (i = 0; i < nr_irqs; i++) {
1345 irq_data = irq_domain_get_irq_data(domain, virq + i);
1346 if (irq_data && irq_data->chip_data) {
1347 data = irq_data->chip_data;
1348 irq_iommu = &data->irq_2_iommu;
1349 raw_spin_lock_irqsave(&irq_2_ir_lock, flags);
1350 clear_entries(irq_iommu);
1351 raw_spin_unlock_irqrestore(&irq_2_ir_lock, flags);
1352 irq_domain_reset_irq_data(irq_data);
1353 kfree(data);
1354 }
1355 }
1356}
1357
1358static int intel_irq_remapping_alloc(struct irq_domain *domain,
1359 unsigned int virq, unsigned int nr_irqs,
1360 void *arg)
1361{
1362 struct intel_iommu *iommu = domain->host_data;
1363 struct irq_alloc_info *info = arg;
1364 struct intel_ir_data *data, *ird;
1365 struct irq_data *irq_data;
1366 struct irq_cfg *irq_cfg;
1367 int i, ret, index;
1368
1369 if (!info || !iommu)
1370 return -EINVAL;
1371 if (nr_irqs > 1 && info->type != X86_IRQ_ALLOC_TYPE_MSI &&
1372 info->type != X86_IRQ_ALLOC_TYPE_MSIX)
1373 return -EINVAL;
1374
1375 /*
1376 * With IRQ remapping enabled, don't need contiguous CPU vectors
1377 * to support multiple MSI interrupts.
1378 */
1379 if (info->type == X86_IRQ_ALLOC_TYPE_MSI)
1380 info->flags &= ~X86_IRQ_ALLOC_CONTIGUOUS_VECTORS;
1381
1382 ret = irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, arg);
1383 if (ret < 0)
1384 return ret;
1385
1386 ret = -ENOMEM;
1387 data = kzalloc(sizeof(*data), GFP_KERNEL);
1388 if (!data)
1389 goto out_free_parent;
1390
1391 down_read(&dmar_global_lock);
1392 index = alloc_irte(iommu, &data->irq_2_iommu, nr_irqs);
1393 up_read(&dmar_global_lock);
1394 if (index < 0) {
1395 pr_warn("Failed to allocate IRTE\n");
1396 kfree(data);
1397 goto out_free_parent;
1398 }
1399
1400 for (i = 0; i < nr_irqs; i++) {
1401 irq_data = irq_domain_get_irq_data(domain, virq + i);
1402 irq_cfg = irqd_cfg(irq_data);
1403 if (!irq_data || !irq_cfg) {
1404 ret = -EINVAL;
1405 goto out_free_data;
1406 }
1407
1408 if (i > 0) {
1409 ird = kzalloc(sizeof(*ird), GFP_KERNEL);
1410 if (!ird)
1411 goto out_free_data;
1412 /* Initialize the common data */
1413 ird->irq_2_iommu = data->irq_2_iommu;
1414 ird->irq_2_iommu.sub_handle = i;
1415 } else {
1416 ird = data;
1417 }
1418
1419 irq_data->hwirq = (index << 16) + i;
1420 irq_data->chip_data = ird;
1421 irq_data->chip = &intel_ir_chip;
1422 intel_irq_remapping_prepare_irte(ird, irq_cfg, info, index, i);
1423 irq_set_status_flags(virq + i, IRQ_MOVE_PCNTXT);
1424 }
1425 return 0;
1426
1427out_free_data:
1428 intel_free_irq_resources(domain, virq, i);
1429out_free_parent:
1430 irq_domain_free_irqs_common(domain, virq, nr_irqs);
1431 return ret;
1432}
1433
1434static void intel_irq_remapping_free(struct irq_domain *domain,
1435 unsigned int virq, unsigned int nr_irqs)
1436{
1437 intel_free_irq_resources(domain, virq, nr_irqs);
1438 irq_domain_free_irqs_common(domain, virq, nr_irqs);
1439}
1440
1441static int intel_irq_remapping_activate(struct irq_domain *domain,
1442 struct irq_data *irq_data, bool reserve)
1443{
1444 intel_ir_reconfigure_irte(irq_data, true);
1445 return 0;
1446}
1447
1448static void intel_irq_remapping_deactivate(struct irq_domain *domain,
1449 struct irq_data *irq_data)
1450{
1451 struct intel_ir_data *data = irq_data->chip_data;
1452 struct irte entry;
1453
1454 memset(&entry, 0, sizeof(entry));
1455 modify_irte(&data->irq_2_iommu, &entry);
1456}
1457
1458static const struct irq_domain_ops intel_ir_domain_ops = {
1459 .alloc = intel_irq_remapping_alloc,
1460 .free = intel_irq_remapping_free,
1461 .activate = intel_irq_remapping_activate,
1462 .deactivate = intel_irq_remapping_deactivate,
1463};
1464
1465/*
1466 * Support of Interrupt Remapping Unit Hotplug
1467 */
1468static int dmar_ir_add(struct dmar_drhd_unit *dmaru, struct intel_iommu *iommu)
1469{
1470 int ret;
1471 int eim = x2apic_enabled();
1472
1473 if (eim && !ecap_eim_support(iommu->ecap)) {
1474 pr_info("DRHD %Lx: EIM not supported by DRHD, ecap %Lx\n",
1475 iommu->reg_phys, iommu->ecap);
1476 return -ENODEV;
1477 }
1478
1479 if (ir_parse_ioapic_hpet_scope(dmaru->hdr, iommu)) {
1480 pr_warn("DRHD %Lx: failed to parse managed IOAPIC/HPET\n",
1481 iommu->reg_phys);
1482 return -ENODEV;
1483 }
1484
1485 /* TODO: check all IOAPICs are covered by IOMMU */
1486
1487 /* Setup Interrupt-remapping now. */
1488 ret = intel_setup_irq_remapping(iommu);
1489 if (ret) {
1490 pr_err("Failed to setup irq remapping for %s\n",
1491 iommu->name);
1492 intel_teardown_irq_remapping(iommu);
1493 ir_remove_ioapic_hpet_scope(iommu);
1494 } else {
1495 iommu_enable_irq_remapping(iommu);
1496 }
1497
1498 return ret;
1499}
1500
1501int dmar_ir_hotplug(struct dmar_drhd_unit *dmaru, bool insert)
1502{
1503 int ret = 0;
1504 struct intel_iommu *iommu = dmaru->iommu;
1505
1506 if (!irq_remapping_enabled)
1507 return 0;
1508 if (iommu == NULL)
1509 return -EINVAL;
1510 if (!ecap_ir_support(iommu->ecap))
1511 return 0;
1512 if (irq_remapping_cap(IRQ_POSTING_CAP) &&
1513 !cap_pi_support(iommu->cap))
1514 return -EBUSY;
1515
1516 if (insert) {
1517 if (!iommu->ir_table)
1518 ret = dmar_ir_add(dmaru, iommu);
1519 } else {
1520 if (iommu->ir_table) {
1521 if (!bitmap_empty(iommu->ir_table->bitmap,
1522 INTR_REMAP_TABLE_ENTRIES)) {
1523 ret = -EBUSY;
1524 } else {
1525 iommu_disable_irq_remapping(iommu);
1526 intel_teardown_irq_remapping(iommu);
1527 ir_remove_ioapic_hpet_scope(iommu);
1528 }
1529 }
1530 }
1531
1532 return ret;
1533}