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1/*
2 * Copyright 2014 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22
23#include <linux/bsearch.h>
24#include <linux/pci.h>
25#include <linux/slab.h>
26#include "kfd_priv.h"
27#include "kfd_device_queue_manager.h"
28#include "kfd_pm4_headers_vi.h"
29#include "cwsr_trap_handler.h"
30#include "kfd_iommu.h"
31#include "amdgpu_amdkfd.h"
32
33#define MQD_SIZE_ALIGNED 768
34
35/*
36 * kfd_locked is used to lock the kfd driver during suspend or reset
37 * once locked, kfd driver will stop any further GPU execution.
38 * create process (open) will return -EAGAIN.
39 */
40static atomic_t kfd_locked = ATOMIC_INIT(0);
41
42#ifdef CONFIG_DRM_AMDGPU_CIK
43extern const struct kfd2kgd_calls gfx_v7_kfd2kgd;
44#endif
45extern const struct kfd2kgd_calls gfx_v8_kfd2kgd;
46extern const struct kfd2kgd_calls gfx_v9_kfd2kgd;
47extern const struct kfd2kgd_calls arcturus_kfd2kgd;
48extern const struct kfd2kgd_calls gfx_v10_kfd2kgd;
49extern const struct kfd2kgd_calls gfx_v10_3_kfd2kgd;
50
51static const struct kfd2kgd_calls *kfd2kgd_funcs[] = {
52#ifdef KFD_SUPPORT_IOMMU_V2
53#ifdef CONFIG_DRM_AMDGPU_CIK
54 [CHIP_KAVERI] = &gfx_v7_kfd2kgd,
55#endif
56 [CHIP_CARRIZO] = &gfx_v8_kfd2kgd,
57 [CHIP_RAVEN] = &gfx_v9_kfd2kgd,
58#endif
59#ifdef CONFIG_DRM_AMDGPU_CIK
60 [CHIP_HAWAII] = &gfx_v7_kfd2kgd,
61#endif
62 [CHIP_TONGA] = &gfx_v8_kfd2kgd,
63 [CHIP_FIJI] = &gfx_v8_kfd2kgd,
64 [CHIP_POLARIS10] = &gfx_v8_kfd2kgd,
65 [CHIP_POLARIS11] = &gfx_v8_kfd2kgd,
66 [CHIP_POLARIS12] = &gfx_v8_kfd2kgd,
67 [CHIP_VEGAM] = &gfx_v8_kfd2kgd,
68 [CHIP_VEGA10] = &gfx_v9_kfd2kgd,
69 [CHIP_VEGA12] = &gfx_v9_kfd2kgd,
70 [CHIP_VEGA20] = &gfx_v9_kfd2kgd,
71 [CHIP_RENOIR] = &gfx_v9_kfd2kgd,
72 [CHIP_ARCTURUS] = &arcturus_kfd2kgd,
73 [CHIP_NAVI10] = &gfx_v10_kfd2kgd,
74 [CHIP_NAVI12] = &gfx_v10_kfd2kgd,
75 [CHIP_NAVI14] = &gfx_v10_kfd2kgd,
76 [CHIP_SIENNA_CICHLID] = &gfx_v10_3_kfd2kgd,
77 [CHIP_NAVY_FLOUNDER] = &gfx_v10_3_kfd2kgd,
78};
79
80#ifdef KFD_SUPPORT_IOMMU_V2
81static const struct kfd_device_info kaveri_device_info = {
82 .asic_family = CHIP_KAVERI,
83 .asic_name = "kaveri",
84 .max_pasid_bits = 16,
85 /* max num of queues for KV.TODO should be a dynamic value */
86 .max_no_of_hqd = 24,
87 .doorbell_size = 4,
88 .ih_ring_entry_size = 4 * sizeof(uint32_t),
89 .event_interrupt_class = &event_interrupt_class_cik,
90 .num_of_watch_points = 4,
91 .mqd_size_aligned = MQD_SIZE_ALIGNED,
92 .supports_cwsr = false,
93 .needs_iommu_device = true,
94 .needs_pci_atomics = false,
95 .num_sdma_engines = 2,
96 .num_xgmi_sdma_engines = 0,
97 .num_sdma_queues_per_engine = 2,
98};
99
100static const struct kfd_device_info carrizo_device_info = {
101 .asic_family = CHIP_CARRIZO,
102 .asic_name = "carrizo",
103 .max_pasid_bits = 16,
104 /* max num of queues for CZ.TODO should be a dynamic value */
105 .max_no_of_hqd = 24,
106 .doorbell_size = 4,
107 .ih_ring_entry_size = 4 * sizeof(uint32_t),
108 .event_interrupt_class = &event_interrupt_class_cik,
109 .num_of_watch_points = 4,
110 .mqd_size_aligned = MQD_SIZE_ALIGNED,
111 .supports_cwsr = true,
112 .needs_iommu_device = true,
113 .needs_pci_atomics = false,
114 .num_sdma_engines = 2,
115 .num_xgmi_sdma_engines = 0,
116 .num_sdma_queues_per_engine = 2,
117};
118
119static const struct kfd_device_info raven_device_info = {
120 .asic_family = CHIP_RAVEN,
121 .asic_name = "raven",
122 .max_pasid_bits = 16,
123 .max_no_of_hqd = 24,
124 .doorbell_size = 8,
125 .ih_ring_entry_size = 8 * sizeof(uint32_t),
126 .event_interrupt_class = &event_interrupt_class_v9,
127 .num_of_watch_points = 4,
128 .mqd_size_aligned = MQD_SIZE_ALIGNED,
129 .supports_cwsr = true,
130 .needs_iommu_device = true,
131 .needs_pci_atomics = true,
132 .num_sdma_engines = 1,
133 .num_xgmi_sdma_engines = 0,
134 .num_sdma_queues_per_engine = 2,
135};
136#endif
137
138static const struct kfd_device_info hawaii_device_info = {
139 .asic_family = CHIP_HAWAII,
140 .asic_name = "hawaii",
141 .max_pasid_bits = 16,
142 /* max num of queues for KV.TODO should be a dynamic value */
143 .max_no_of_hqd = 24,
144 .doorbell_size = 4,
145 .ih_ring_entry_size = 4 * sizeof(uint32_t),
146 .event_interrupt_class = &event_interrupt_class_cik,
147 .num_of_watch_points = 4,
148 .mqd_size_aligned = MQD_SIZE_ALIGNED,
149 .supports_cwsr = false,
150 .needs_iommu_device = false,
151 .needs_pci_atomics = false,
152 .num_sdma_engines = 2,
153 .num_xgmi_sdma_engines = 0,
154 .num_sdma_queues_per_engine = 2,
155};
156
157static const struct kfd_device_info tonga_device_info = {
158 .asic_family = CHIP_TONGA,
159 .asic_name = "tonga",
160 .max_pasid_bits = 16,
161 .max_no_of_hqd = 24,
162 .doorbell_size = 4,
163 .ih_ring_entry_size = 4 * sizeof(uint32_t),
164 .event_interrupt_class = &event_interrupt_class_cik,
165 .num_of_watch_points = 4,
166 .mqd_size_aligned = MQD_SIZE_ALIGNED,
167 .supports_cwsr = false,
168 .needs_iommu_device = false,
169 .needs_pci_atomics = true,
170 .num_sdma_engines = 2,
171 .num_xgmi_sdma_engines = 0,
172 .num_sdma_queues_per_engine = 2,
173};
174
175static const struct kfd_device_info fiji_device_info = {
176 .asic_family = CHIP_FIJI,
177 .asic_name = "fiji",
178 .max_pasid_bits = 16,
179 .max_no_of_hqd = 24,
180 .doorbell_size = 4,
181 .ih_ring_entry_size = 4 * sizeof(uint32_t),
182 .event_interrupt_class = &event_interrupt_class_cik,
183 .num_of_watch_points = 4,
184 .mqd_size_aligned = MQD_SIZE_ALIGNED,
185 .supports_cwsr = true,
186 .needs_iommu_device = false,
187 .needs_pci_atomics = true,
188 .num_sdma_engines = 2,
189 .num_xgmi_sdma_engines = 0,
190 .num_sdma_queues_per_engine = 2,
191};
192
193static const struct kfd_device_info fiji_vf_device_info = {
194 .asic_family = CHIP_FIJI,
195 .asic_name = "fiji",
196 .max_pasid_bits = 16,
197 .max_no_of_hqd = 24,
198 .doorbell_size = 4,
199 .ih_ring_entry_size = 4 * sizeof(uint32_t),
200 .event_interrupt_class = &event_interrupt_class_cik,
201 .num_of_watch_points = 4,
202 .mqd_size_aligned = MQD_SIZE_ALIGNED,
203 .supports_cwsr = true,
204 .needs_iommu_device = false,
205 .needs_pci_atomics = false,
206 .num_sdma_engines = 2,
207 .num_xgmi_sdma_engines = 0,
208 .num_sdma_queues_per_engine = 2,
209};
210
211
212static const struct kfd_device_info polaris10_device_info = {
213 .asic_family = CHIP_POLARIS10,
214 .asic_name = "polaris10",
215 .max_pasid_bits = 16,
216 .max_no_of_hqd = 24,
217 .doorbell_size = 4,
218 .ih_ring_entry_size = 4 * sizeof(uint32_t),
219 .event_interrupt_class = &event_interrupt_class_cik,
220 .num_of_watch_points = 4,
221 .mqd_size_aligned = MQD_SIZE_ALIGNED,
222 .supports_cwsr = true,
223 .needs_iommu_device = false,
224 .needs_pci_atomics = true,
225 .num_sdma_engines = 2,
226 .num_xgmi_sdma_engines = 0,
227 .num_sdma_queues_per_engine = 2,
228};
229
230static const struct kfd_device_info polaris10_vf_device_info = {
231 .asic_family = CHIP_POLARIS10,
232 .asic_name = "polaris10",
233 .max_pasid_bits = 16,
234 .max_no_of_hqd = 24,
235 .doorbell_size = 4,
236 .ih_ring_entry_size = 4 * sizeof(uint32_t),
237 .event_interrupt_class = &event_interrupt_class_cik,
238 .num_of_watch_points = 4,
239 .mqd_size_aligned = MQD_SIZE_ALIGNED,
240 .supports_cwsr = true,
241 .needs_iommu_device = false,
242 .needs_pci_atomics = false,
243 .num_sdma_engines = 2,
244 .num_xgmi_sdma_engines = 0,
245 .num_sdma_queues_per_engine = 2,
246};
247
248static const struct kfd_device_info polaris11_device_info = {
249 .asic_family = CHIP_POLARIS11,
250 .asic_name = "polaris11",
251 .max_pasid_bits = 16,
252 .max_no_of_hqd = 24,
253 .doorbell_size = 4,
254 .ih_ring_entry_size = 4 * sizeof(uint32_t),
255 .event_interrupt_class = &event_interrupt_class_cik,
256 .num_of_watch_points = 4,
257 .mqd_size_aligned = MQD_SIZE_ALIGNED,
258 .supports_cwsr = true,
259 .needs_iommu_device = false,
260 .needs_pci_atomics = true,
261 .num_sdma_engines = 2,
262 .num_xgmi_sdma_engines = 0,
263 .num_sdma_queues_per_engine = 2,
264};
265
266static const struct kfd_device_info polaris12_device_info = {
267 .asic_family = CHIP_POLARIS12,
268 .asic_name = "polaris12",
269 .max_pasid_bits = 16,
270 .max_no_of_hqd = 24,
271 .doorbell_size = 4,
272 .ih_ring_entry_size = 4 * sizeof(uint32_t),
273 .event_interrupt_class = &event_interrupt_class_cik,
274 .num_of_watch_points = 4,
275 .mqd_size_aligned = MQD_SIZE_ALIGNED,
276 .supports_cwsr = true,
277 .needs_iommu_device = false,
278 .needs_pci_atomics = true,
279 .num_sdma_engines = 2,
280 .num_xgmi_sdma_engines = 0,
281 .num_sdma_queues_per_engine = 2,
282};
283
284static const struct kfd_device_info vegam_device_info = {
285 .asic_family = CHIP_VEGAM,
286 .asic_name = "vegam",
287 .max_pasid_bits = 16,
288 .max_no_of_hqd = 24,
289 .doorbell_size = 4,
290 .ih_ring_entry_size = 4 * sizeof(uint32_t),
291 .event_interrupt_class = &event_interrupt_class_cik,
292 .num_of_watch_points = 4,
293 .mqd_size_aligned = MQD_SIZE_ALIGNED,
294 .supports_cwsr = true,
295 .needs_iommu_device = false,
296 .needs_pci_atomics = true,
297 .num_sdma_engines = 2,
298 .num_xgmi_sdma_engines = 0,
299 .num_sdma_queues_per_engine = 2,
300};
301
302static const struct kfd_device_info vega10_device_info = {
303 .asic_family = CHIP_VEGA10,
304 .asic_name = "vega10",
305 .max_pasid_bits = 16,
306 .max_no_of_hqd = 24,
307 .doorbell_size = 8,
308 .ih_ring_entry_size = 8 * sizeof(uint32_t),
309 .event_interrupt_class = &event_interrupt_class_v9,
310 .num_of_watch_points = 4,
311 .mqd_size_aligned = MQD_SIZE_ALIGNED,
312 .supports_cwsr = true,
313 .needs_iommu_device = false,
314 .needs_pci_atomics = false,
315 .num_sdma_engines = 2,
316 .num_xgmi_sdma_engines = 0,
317 .num_sdma_queues_per_engine = 2,
318};
319
320static const struct kfd_device_info vega10_vf_device_info = {
321 .asic_family = CHIP_VEGA10,
322 .asic_name = "vega10",
323 .max_pasid_bits = 16,
324 .max_no_of_hqd = 24,
325 .doorbell_size = 8,
326 .ih_ring_entry_size = 8 * sizeof(uint32_t),
327 .event_interrupt_class = &event_interrupt_class_v9,
328 .num_of_watch_points = 4,
329 .mqd_size_aligned = MQD_SIZE_ALIGNED,
330 .supports_cwsr = true,
331 .needs_iommu_device = false,
332 .needs_pci_atomics = false,
333 .num_sdma_engines = 2,
334 .num_xgmi_sdma_engines = 0,
335 .num_sdma_queues_per_engine = 2,
336};
337
338static const struct kfd_device_info vega12_device_info = {
339 .asic_family = CHIP_VEGA12,
340 .asic_name = "vega12",
341 .max_pasid_bits = 16,
342 .max_no_of_hqd = 24,
343 .doorbell_size = 8,
344 .ih_ring_entry_size = 8 * sizeof(uint32_t),
345 .event_interrupt_class = &event_interrupt_class_v9,
346 .num_of_watch_points = 4,
347 .mqd_size_aligned = MQD_SIZE_ALIGNED,
348 .supports_cwsr = true,
349 .needs_iommu_device = false,
350 .needs_pci_atomics = false,
351 .num_sdma_engines = 2,
352 .num_xgmi_sdma_engines = 0,
353 .num_sdma_queues_per_engine = 2,
354};
355
356static const struct kfd_device_info vega20_device_info = {
357 .asic_family = CHIP_VEGA20,
358 .asic_name = "vega20",
359 .max_pasid_bits = 16,
360 .max_no_of_hqd = 24,
361 .doorbell_size = 8,
362 .ih_ring_entry_size = 8 * sizeof(uint32_t),
363 .event_interrupt_class = &event_interrupt_class_v9,
364 .num_of_watch_points = 4,
365 .mqd_size_aligned = MQD_SIZE_ALIGNED,
366 .supports_cwsr = true,
367 .needs_iommu_device = false,
368 .needs_pci_atomics = false,
369 .num_sdma_engines = 2,
370 .num_xgmi_sdma_engines = 0,
371 .num_sdma_queues_per_engine = 8,
372};
373
374static const struct kfd_device_info arcturus_device_info = {
375 .asic_family = CHIP_ARCTURUS,
376 .asic_name = "arcturus",
377 .max_pasid_bits = 16,
378 .max_no_of_hqd = 24,
379 .doorbell_size = 8,
380 .ih_ring_entry_size = 8 * sizeof(uint32_t),
381 .event_interrupt_class = &event_interrupt_class_v9,
382 .num_of_watch_points = 4,
383 .mqd_size_aligned = MQD_SIZE_ALIGNED,
384 .supports_cwsr = true,
385 .needs_iommu_device = false,
386 .needs_pci_atomics = false,
387 .num_sdma_engines = 2,
388 .num_xgmi_sdma_engines = 6,
389 .num_sdma_queues_per_engine = 8,
390};
391
392static const struct kfd_device_info renoir_device_info = {
393 .asic_family = CHIP_RENOIR,
394 .asic_name = "renoir",
395 .max_pasid_bits = 16,
396 .max_no_of_hqd = 24,
397 .doorbell_size = 8,
398 .ih_ring_entry_size = 8 * sizeof(uint32_t),
399 .event_interrupt_class = &event_interrupt_class_v9,
400 .num_of_watch_points = 4,
401 .mqd_size_aligned = MQD_SIZE_ALIGNED,
402 .supports_cwsr = true,
403 .needs_iommu_device = false,
404 .needs_pci_atomics = false,
405 .num_sdma_engines = 1,
406 .num_xgmi_sdma_engines = 0,
407 .num_sdma_queues_per_engine = 2,
408};
409
410static const struct kfd_device_info navi10_device_info = {
411 .asic_family = CHIP_NAVI10,
412 .asic_name = "navi10",
413 .max_pasid_bits = 16,
414 .max_no_of_hqd = 24,
415 .doorbell_size = 8,
416 .ih_ring_entry_size = 8 * sizeof(uint32_t),
417 .event_interrupt_class = &event_interrupt_class_v9,
418 .num_of_watch_points = 4,
419 .mqd_size_aligned = MQD_SIZE_ALIGNED,
420 .needs_iommu_device = false,
421 .supports_cwsr = true,
422 .needs_pci_atomics = false,
423 .num_sdma_engines = 2,
424 .num_xgmi_sdma_engines = 0,
425 .num_sdma_queues_per_engine = 8,
426};
427
428static const struct kfd_device_info navi12_device_info = {
429 .asic_family = CHIP_NAVI12,
430 .asic_name = "navi12",
431 .max_pasid_bits = 16,
432 .max_no_of_hqd = 24,
433 .doorbell_size = 8,
434 .ih_ring_entry_size = 8 * sizeof(uint32_t),
435 .event_interrupt_class = &event_interrupt_class_v9,
436 .num_of_watch_points = 4,
437 .mqd_size_aligned = MQD_SIZE_ALIGNED,
438 .needs_iommu_device = false,
439 .supports_cwsr = true,
440 .needs_pci_atomics = false,
441 .num_sdma_engines = 2,
442 .num_xgmi_sdma_engines = 0,
443 .num_sdma_queues_per_engine = 8,
444};
445
446static const struct kfd_device_info navi14_device_info = {
447 .asic_family = CHIP_NAVI14,
448 .asic_name = "navi14",
449 .max_pasid_bits = 16,
450 .max_no_of_hqd = 24,
451 .doorbell_size = 8,
452 .ih_ring_entry_size = 8 * sizeof(uint32_t),
453 .event_interrupt_class = &event_interrupt_class_v9,
454 .num_of_watch_points = 4,
455 .mqd_size_aligned = MQD_SIZE_ALIGNED,
456 .needs_iommu_device = false,
457 .supports_cwsr = true,
458 .needs_pci_atomics = false,
459 .num_sdma_engines = 2,
460 .num_xgmi_sdma_engines = 0,
461 .num_sdma_queues_per_engine = 8,
462};
463
464static const struct kfd_device_info sienna_cichlid_device_info = {
465 .asic_family = CHIP_SIENNA_CICHLID,
466 .asic_name = "sienna_cichlid",
467 .max_pasid_bits = 16,
468 .max_no_of_hqd = 24,
469 .doorbell_size = 8,
470 .ih_ring_entry_size = 8 * sizeof(uint32_t),
471 .event_interrupt_class = &event_interrupt_class_v9,
472 .num_of_watch_points = 4,
473 .mqd_size_aligned = MQD_SIZE_ALIGNED,
474 .needs_iommu_device = false,
475 .supports_cwsr = true,
476 .needs_pci_atomics = false,
477 .num_sdma_engines = 4,
478 .num_xgmi_sdma_engines = 0,
479 .num_sdma_queues_per_engine = 8,
480};
481
482static const struct kfd_device_info navy_flounder_device_info = {
483 .asic_family = CHIP_NAVY_FLOUNDER,
484 .asic_name = "navy_flounder",
485 .max_pasid_bits = 16,
486 .max_no_of_hqd = 24,
487 .doorbell_size = 8,
488 .ih_ring_entry_size = 8 * sizeof(uint32_t),
489 .event_interrupt_class = &event_interrupt_class_v9,
490 .num_of_watch_points = 4,
491 .mqd_size_aligned = MQD_SIZE_ALIGNED,
492 .needs_iommu_device = false,
493 .supports_cwsr = true,
494 .needs_pci_atomics = false,
495 .num_sdma_engines = 2,
496 .num_xgmi_sdma_engines = 0,
497 .num_sdma_queues_per_engine = 8,
498};
499
500/* For each entry, [0] is regular and [1] is virtualisation device. */
501static const struct kfd_device_info *kfd_supported_devices[][2] = {
502#ifdef KFD_SUPPORT_IOMMU_V2
503 [CHIP_KAVERI] = {&kaveri_device_info, NULL},
504 [CHIP_CARRIZO] = {&carrizo_device_info, NULL},
505 [CHIP_RAVEN] = {&raven_device_info, NULL},
506#endif
507 [CHIP_HAWAII] = {&hawaii_device_info, NULL},
508 [CHIP_TONGA] = {&tonga_device_info, NULL},
509 [CHIP_FIJI] = {&fiji_device_info, &fiji_vf_device_info},
510 [CHIP_POLARIS10] = {&polaris10_device_info, &polaris10_vf_device_info},
511 [CHIP_POLARIS11] = {&polaris11_device_info, NULL},
512 [CHIP_POLARIS12] = {&polaris12_device_info, NULL},
513 [CHIP_VEGAM] = {&vegam_device_info, NULL},
514 [CHIP_VEGA10] = {&vega10_device_info, &vega10_vf_device_info},
515 [CHIP_VEGA12] = {&vega12_device_info, NULL},
516 [CHIP_VEGA20] = {&vega20_device_info, NULL},
517 [CHIP_RENOIR] = {&renoir_device_info, NULL},
518 [CHIP_ARCTURUS] = {&arcturus_device_info, &arcturus_device_info},
519 [CHIP_NAVI10] = {&navi10_device_info, NULL},
520 [CHIP_NAVI12] = {&navi12_device_info, &navi12_device_info},
521 [CHIP_NAVI14] = {&navi14_device_info, NULL},
522 [CHIP_SIENNA_CICHLID] = {&sienna_cichlid_device_info, &sienna_cichlid_device_info},
523 [CHIP_NAVY_FLOUNDER] = {&navy_flounder_device_info, &navy_flounder_device_info},
524};
525
526static int kfd_gtt_sa_init(struct kfd_dev *kfd, unsigned int buf_size,
527 unsigned int chunk_size);
528static void kfd_gtt_sa_fini(struct kfd_dev *kfd);
529
530static int kfd_resume(struct kfd_dev *kfd);
531
532struct kfd_dev *kgd2kfd_probe(struct kgd_dev *kgd,
533 struct pci_dev *pdev, unsigned int asic_type, bool vf)
534{
535 struct kfd_dev *kfd;
536 const struct kfd_device_info *device_info;
537 const struct kfd2kgd_calls *f2g;
538
539 if (asic_type >= sizeof(kfd_supported_devices) / (sizeof(void *) * 2)
540 || asic_type >= sizeof(kfd2kgd_funcs) / sizeof(void *)) {
541 dev_err(kfd_device, "asic_type %d out of range\n", asic_type);
542 return NULL; /* asic_type out of range */
543 }
544
545 device_info = kfd_supported_devices[asic_type][vf];
546 f2g = kfd2kgd_funcs[asic_type];
547
548 if (!device_info || !f2g) {
549 dev_err(kfd_device, "%s %s not supported in kfd\n",
550 amdgpu_asic_name[asic_type], vf ? "VF" : "");
551 return NULL;
552 }
553
554 kfd = kzalloc(sizeof(*kfd), GFP_KERNEL);
555 if (!kfd)
556 return NULL;
557
558 /* Allow BIF to recode atomics to PCIe 3.0 AtomicOps.
559 * 32 and 64-bit requests are possible and must be
560 * supported.
561 */
562 kfd->pci_atomic_requested = amdgpu_amdkfd_have_atomics_support(kgd);
563 if (device_info->needs_pci_atomics &&
564 !kfd->pci_atomic_requested) {
565 dev_info(kfd_device,
566 "skipped device %x:%x, PCI rejects atomics\n",
567 pdev->vendor, pdev->device);
568 kfree(kfd);
569 return NULL;
570 }
571
572 kfd->kgd = kgd;
573 kfd->device_info = device_info;
574 kfd->pdev = pdev;
575 kfd->init_complete = false;
576 kfd->kfd2kgd = f2g;
577 atomic_set(&kfd->compute_profile, 0);
578
579 mutex_init(&kfd->doorbell_mutex);
580 memset(&kfd->doorbell_available_index, 0,
581 sizeof(kfd->doorbell_available_index));
582
583 atomic_set(&kfd->sram_ecc_flag, 0);
584
585 return kfd;
586}
587
588static void kfd_cwsr_init(struct kfd_dev *kfd)
589{
590 if (cwsr_enable && kfd->device_info->supports_cwsr) {
591 if (kfd->device_info->asic_family < CHIP_VEGA10) {
592 BUILD_BUG_ON(sizeof(cwsr_trap_gfx8_hex) > PAGE_SIZE);
593 kfd->cwsr_isa = cwsr_trap_gfx8_hex;
594 kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx8_hex);
595 } else if (kfd->device_info->asic_family == CHIP_ARCTURUS) {
596 BUILD_BUG_ON(sizeof(cwsr_trap_arcturus_hex) > PAGE_SIZE);
597 kfd->cwsr_isa = cwsr_trap_arcturus_hex;
598 kfd->cwsr_isa_size = sizeof(cwsr_trap_arcturus_hex);
599 } else if (kfd->device_info->asic_family < CHIP_NAVI10) {
600 BUILD_BUG_ON(sizeof(cwsr_trap_gfx9_hex) > PAGE_SIZE);
601 kfd->cwsr_isa = cwsr_trap_gfx9_hex;
602 kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx9_hex);
603 } else if (kfd->device_info->asic_family < CHIP_SIENNA_CICHLID) {
604 BUILD_BUG_ON(sizeof(cwsr_trap_nv1x_hex) > PAGE_SIZE);
605 kfd->cwsr_isa = cwsr_trap_nv1x_hex;
606 kfd->cwsr_isa_size = sizeof(cwsr_trap_nv1x_hex);
607 } else {
608 BUILD_BUG_ON(sizeof(cwsr_trap_gfx10_hex) > PAGE_SIZE);
609 kfd->cwsr_isa = cwsr_trap_gfx10_hex;
610 kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx10_hex);
611 }
612
613 kfd->cwsr_enabled = true;
614 }
615}
616
617static int kfd_gws_init(struct kfd_dev *kfd)
618{
619 int ret = 0;
620
621 if (kfd->dqm->sched_policy == KFD_SCHED_POLICY_NO_HWS)
622 return 0;
623
624 if (hws_gws_support
625 || (kfd->device_info->asic_family == CHIP_VEGA10
626 && kfd->mec2_fw_version >= 0x81b3)
627 || (kfd->device_info->asic_family >= CHIP_VEGA12
628 && kfd->device_info->asic_family <= CHIP_RAVEN
629 && kfd->mec2_fw_version >= 0x1b3)
630 || (kfd->device_info->asic_family == CHIP_ARCTURUS
631 && kfd->mec2_fw_version >= 0x30))
632 ret = amdgpu_amdkfd_alloc_gws(kfd->kgd,
633 amdgpu_amdkfd_get_num_gws(kfd->kgd), &kfd->gws);
634
635 return ret;
636}
637
638static void kfd_smi_init(struct kfd_dev *dev) {
639 INIT_LIST_HEAD(&dev->smi_clients);
640 spin_lock_init(&dev->smi_lock);
641}
642
643bool kgd2kfd_device_init(struct kfd_dev *kfd,
644 struct drm_device *ddev,
645 const struct kgd2kfd_shared_resources *gpu_resources)
646{
647 unsigned int size;
648
649 kfd->ddev = ddev;
650 kfd->mec_fw_version = amdgpu_amdkfd_get_fw_version(kfd->kgd,
651 KGD_ENGINE_MEC1);
652 kfd->mec2_fw_version = amdgpu_amdkfd_get_fw_version(kfd->kgd,
653 KGD_ENGINE_MEC2);
654 kfd->sdma_fw_version = amdgpu_amdkfd_get_fw_version(kfd->kgd,
655 KGD_ENGINE_SDMA1);
656 kfd->shared_resources = *gpu_resources;
657
658 kfd->vm_info.first_vmid_kfd = ffs(gpu_resources->compute_vmid_bitmap)-1;
659 kfd->vm_info.last_vmid_kfd = fls(gpu_resources->compute_vmid_bitmap)-1;
660 kfd->vm_info.vmid_num_kfd = kfd->vm_info.last_vmid_kfd
661 - kfd->vm_info.first_vmid_kfd + 1;
662
663 /* Verify module parameters regarding mapped process number*/
664 if ((hws_max_conc_proc < 0)
665 || (hws_max_conc_proc > kfd->vm_info.vmid_num_kfd)) {
666 dev_err(kfd_device,
667 "hws_max_conc_proc %d must be between 0 and %d, use %d instead\n",
668 hws_max_conc_proc, kfd->vm_info.vmid_num_kfd,
669 kfd->vm_info.vmid_num_kfd);
670 kfd->max_proc_per_quantum = kfd->vm_info.vmid_num_kfd;
671 } else
672 kfd->max_proc_per_quantum = hws_max_conc_proc;
673
674 /* calculate max size of mqds needed for queues */
675 size = max_num_of_queues_per_device *
676 kfd->device_info->mqd_size_aligned;
677
678 /*
679 * calculate max size of runlist packet.
680 * There can be only 2 packets at once
681 */
682 size += (KFD_MAX_NUM_OF_PROCESSES * sizeof(struct pm4_mes_map_process) +
683 max_num_of_queues_per_device * sizeof(struct pm4_mes_map_queues)
684 + sizeof(struct pm4_mes_runlist)) * 2;
685
686 /* Add size of HIQ & DIQ */
687 size += KFD_KERNEL_QUEUE_SIZE * 2;
688
689 /* add another 512KB for all other allocations on gart (HPD, fences) */
690 size += 512 * 1024;
691
692 if (amdgpu_amdkfd_alloc_gtt_mem(
693 kfd->kgd, size, &kfd->gtt_mem,
694 &kfd->gtt_start_gpu_addr, &kfd->gtt_start_cpu_ptr,
695 false)) {
696 dev_err(kfd_device, "Could not allocate %d bytes\n", size);
697 goto alloc_gtt_mem_failure;
698 }
699
700 dev_info(kfd_device, "Allocated %d bytes on gart\n", size);
701
702 /* Initialize GTT sa with 512 byte chunk size */
703 if (kfd_gtt_sa_init(kfd, size, 512) != 0) {
704 dev_err(kfd_device, "Error initializing gtt sub-allocator\n");
705 goto kfd_gtt_sa_init_error;
706 }
707
708 if (kfd_doorbell_init(kfd)) {
709 dev_err(kfd_device,
710 "Error initializing doorbell aperture\n");
711 goto kfd_doorbell_error;
712 }
713
714 if (kfd->kfd2kgd->get_hive_id)
715 kfd->hive_id = kfd->kfd2kgd->get_hive_id(kfd->kgd);
716
717 if (kfd->kfd2kgd->get_unique_id)
718 kfd->unique_id = kfd->kfd2kgd->get_unique_id(kfd->kgd);
719
720 if (kfd_interrupt_init(kfd)) {
721 dev_err(kfd_device, "Error initializing interrupts\n");
722 goto kfd_interrupt_error;
723 }
724
725 kfd->dqm = device_queue_manager_init(kfd);
726 if (!kfd->dqm) {
727 dev_err(kfd_device, "Error initializing queue manager\n");
728 goto device_queue_manager_error;
729 }
730
731 /* If supported on this device, allocate global GWS that is shared
732 * by all KFD processes
733 */
734 if (kfd_gws_init(kfd)) {
735 dev_err(kfd_device, "Could not allocate %d gws\n",
736 amdgpu_amdkfd_get_num_gws(kfd->kgd));
737 goto gws_error;
738 }
739
740 if (kfd_iommu_device_init(kfd)) {
741 dev_err(kfd_device, "Error initializing iommuv2\n");
742 goto device_iommu_error;
743 }
744
745 kfd_cwsr_init(kfd);
746
747 if (kfd_resume(kfd))
748 goto kfd_resume_error;
749
750 kfd->dbgmgr = NULL;
751
752 if (kfd_topology_add_device(kfd)) {
753 dev_err(kfd_device, "Error adding device to topology\n");
754 goto kfd_topology_add_device_error;
755 }
756
757 kfd_smi_init(kfd);
758
759 kfd->init_complete = true;
760 dev_info(kfd_device, "added device %x:%x\n", kfd->pdev->vendor,
761 kfd->pdev->device);
762
763 pr_debug("Starting kfd with the following scheduling policy %d\n",
764 kfd->dqm->sched_policy);
765
766 goto out;
767
768kfd_topology_add_device_error:
769kfd_resume_error:
770device_iommu_error:
771gws_error:
772 device_queue_manager_uninit(kfd->dqm);
773device_queue_manager_error:
774 kfd_interrupt_exit(kfd);
775kfd_interrupt_error:
776 kfd_doorbell_fini(kfd);
777kfd_doorbell_error:
778 kfd_gtt_sa_fini(kfd);
779kfd_gtt_sa_init_error:
780 amdgpu_amdkfd_free_gtt_mem(kfd->kgd, kfd->gtt_mem);
781alloc_gtt_mem_failure:
782 if (kfd->gws)
783 amdgpu_amdkfd_free_gws(kfd->kgd, kfd->gws);
784 dev_err(kfd_device,
785 "device %x:%x NOT added due to errors\n",
786 kfd->pdev->vendor, kfd->pdev->device);
787out:
788 return kfd->init_complete;
789}
790
791void kgd2kfd_device_exit(struct kfd_dev *kfd)
792{
793 if (kfd->init_complete) {
794 kgd2kfd_suspend(kfd, false);
795 device_queue_manager_uninit(kfd->dqm);
796 kfd_interrupt_exit(kfd);
797 kfd_topology_remove_device(kfd);
798 kfd_doorbell_fini(kfd);
799 kfd_gtt_sa_fini(kfd);
800 amdgpu_amdkfd_free_gtt_mem(kfd->kgd, kfd->gtt_mem);
801 if (kfd->gws)
802 amdgpu_amdkfd_free_gws(kfd->kgd, kfd->gws);
803 }
804
805 kfree(kfd);
806}
807
808int kgd2kfd_pre_reset(struct kfd_dev *kfd)
809{
810 if (!kfd->init_complete)
811 return 0;
812
813 kfd->dqm->ops.pre_reset(kfd->dqm);
814
815 kgd2kfd_suspend(kfd, false);
816
817 kfd_signal_reset_event(kfd);
818 return 0;
819}
820
821/*
822 * Fix me. KFD won't be able to resume existing process for now.
823 * We will keep all existing process in a evicted state and
824 * wait the process to be terminated.
825 */
826
827int kgd2kfd_post_reset(struct kfd_dev *kfd)
828{
829 int ret;
830
831 if (!kfd->init_complete)
832 return 0;
833
834 ret = kfd_resume(kfd);
835 if (ret)
836 return ret;
837 atomic_dec(&kfd_locked);
838
839 atomic_set(&kfd->sram_ecc_flag, 0);
840
841 return 0;
842}
843
844bool kfd_is_locked(void)
845{
846 return (atomic_read(&kfd_locked) > 0);
847}
848
849void kgd2kfd_suspend(struct kfd_dev *kfd, bool run_pm)
850{
851 if (!kfd->init_complete)
852 return;
853
854 /* for runtime suspend, skip locking kfd */
855 if (!run_pm) {
856 /* For first KFD device suspend all the KFD processes */
857 if (atomic_inc_return(&kfd_locked) == 1)
858 kfd_suspend_all_processes();
859 }
860
861 kfd->dqm->ops.stop(kfd->dqm);
862 kfd_iommu_suspend(kfd);
863}
864
865int kgd2kfd_resume(struct kfd_dev *kfd, bool run_pm)
866{
867 int ret, count;
868
869 if (!kfd->init_complete)
870 return 0;
871
872 ret = kfd_resume(kfd);
873 if (ret)
874 return ret;
875
876 /* for runtime resume, skip unlocking kfd */
877 if (!run_pm) {
878 count = atomic_dec_return(&kfd_locked);
879 WARN_ONCE(count < 0, "KFD suspend / resume ref. error");
880 if (count == 0)
881 ret = kfd_resume_all_processes();
882 }
883
884 return ret;
885}
886
887static int kfd_resume(struct kfd_dev *kfd)
888{
889 int err = 0;
890
891 err = kfd_iommu_resume(kfd);
892 if (err) {
893 dev_err(kfd_device,
894 "Failed to resume IOMMU for device %x:%x\n",
895 kfd->pdev->vendor, kfd->pdev->device);
896 return err;
897 }
898
899 err = kfd->dqm->ops.start(kfd->dqm);
900 if (err) {
901 dev_err(kfd_device,
902 "Error starting queue manager for device %x:%x\n",
903 kfd->pdev->vendor, kfd->pdev->device);
904 goto dqm_start_error;
905 }
906
907 return err;
908
909dqm_start_error:
910 kfd_iommu_suspend(kfd);
911 return err;
912}
913
914static inline void kfd_queue_work(struct workqueue_struct *wq,
915 struct work_struct *work)
916{
917 int cpu, new_cpu;
918
919 cpu = new_cpu = smp_processor_id();
920 do {
921 new_cpu = cpumask_next(new_cpu, cpu_online_mask) % nr_cpu_ids;
922 if (cpu_to_node(new_cpu) == numa_node_id())
923 break;
924 } while (cpu != new_cpu);
925
926 queue_work_on(new_cpu, wq, work);
927}
928
929/* This is called directly from KGD at ISR. */
930void kgd2kfd_interrupt(struct kfd_dev *kfd, const void *ih_ring_entry)
931{
932 uint32_t patched_ihre[KFD_MAX_RING_ENTRY_SIZE];
933 bool is_patched = false;
934 unsigned long flags;
935
936 if (!kfd->init_complete)
937 return;
938
939 if (kfd->device_info->ih_ring_entry_size > sizeof(patched_ihre)) {
940 dev_err_once(kfd_device, "Ring entry too small\n");
941 return;
942 }
943
944 spin_lock_irqsave(&kfd->interrupt_lock, flags);
945
946 if (kfd->interrupts_active
947 && interrupt_is_wanted(kfd, ih_ring_entry,
948 patched_ihre, &is_patched)
949 && enqueue_ih_ring_entry(kfd,
950 is_patched ? patched_ihre : ih_ring_entry))
951 kfd_queue_work(kfd->ih_wq, &kfd->interrupt_work);
952
953 spin_unlock_irqrestore(&kfd->interrupt_lock, flags);
954}
955
956int kgd2kfd_quiesce_mm(struct mm_struct *mm)
957{
958 struct kfd_process *p;
959 int r;
960
961 /* Because we are called from arbitrary context (workqueue) as opposed
962 * to process context, kfd_process could attempt to exit while we are
963 * running so the lookup function increments the process ref count.
964 */
965 p = kfd_lookup_process_by_mm(mm);
966 if (!p)
967 return -ESRCH;
968
969 WARN(debug_evictions, "Evicting pid %d", p->lead_thread->pid);
970 r = kfd_process_evict_queues(p);
971
972 kfd_unref_process(p);
973 return r;
974}
975
976int kgd2kfd_resume_mm(struct mm_struct *mm)
977{
978 struct kfd_process *p;
979 int r;
980
981 /* Because we are called from arbitrary context (workqueue) as opposed
982 * to process context, kfd_process could attempt to exit while we are
983 * running so the lookup function increments the process ref count.
984 */
985 p = kfd_lookup_process_by_mm(mm);
986 if (!p)
987 return -ESRCH;
988
989 r = kfd_process_restore_queues(p);
990
991 kfd_unref_process(p);
992 return r;
993}
994
995/** kgd2kfd_schedule_evict_and_restore_process - Schedules work queue that will
996 * prepare for safe eviction of KFD BOs that belong to the specified
997 * process.
998 *
999 * @mm: mm_struct that identifies the specified KFD process
1000 * @fence: eviction fence attached to KFD process BOs
1001 *
1002 */
1003int kgd2kfd_schedule_evict_and_restore_process(struct mm_struct *mm,
1004 struct dma_fence *fence)
1005{
1006 struct kfd_process *p;
1007 unsigned long active_time;
1008 unsigned long delay_jiffies = msecs_to_jiffies(PROCESS_ACTIVE_TIME_MS);
1009
1010 if (!fence)
1011 return -EINVAL;
1012
1013 if (dma_fence_is_signaled(fence))
1014 return 0;
1015
1016 p = kfd_lookup_process_by_mm(mm);
1017 if (!p)
1018 return -ENODEV;
1019
1020 if (fence->seqno == p->last_eviction_seqno)
1021 goto out;
1022
1023 p->last_eviction_seqno = fence->seqno;
1024
1025 /* Avoid KFD process starvation. Wait for at least
1026 * PROCESS_ACTIVE_TIME_MS before evicting the process again
1027 */
1028 active_time = get_jiffies_64() - p->last_restore_timestamp;
1029 if (delay_jiffies > active_time)
1030 delay_jiffies -= active_time;
1031 else
1032 delay_jiffies = 0;
1033
1034 /* During process initialization eviction_work.dwork is initialized
1035 * to kfd_evict_bo_worker
1036 */
1037 WARN(debug_evictions, "Scheduling eviction of pid %d in %ld jiffies",
1038 p->lead_thread->pid, delay_jiffies);
1039 schedule_delayed_work(&p->eviction_work, delay_jiffies);
1040out:
1041 kfd_unref_process(p);
1042 return 0;
1043}
1044
1045static int kfd_gtt_sa_init(struct kfd_dev *kfd, unsigned int buf_size,
1046 unsigned int chunk_size)
1047{
1048 unsigned int num_of_longs;
1049
1050 if (WARN_ON(buf_size < chunk_size))
1051 return -EINVAL;
1052 if (WARN_ON(buf_size == 0))
1053 return -EINVAL;
1054 if (WARN_ON(chunk_size == 0))
1055 return -EINVAL;
1056
1057 kfd->gtt_sa_chunk_size = chunk_size;
1058 kfd->gtt_sa_num_of_chunks = buf_size / chunk_size;
1059
1060 num_of_longs = (kfd->gtt_sa_num_of_chunks + BITS_PER_LONG - 1) /
1061 BITS_PER_LONG;
1062
1063 kfd->gtt_sa_bitmap = kcalloc(num_of_longs, sizeof(long), GFP_KERNEL);
1064
1065 if (!kfd->gtt_sa_bitmap)
1066 return -ENOMEM;
1067
1068 pr_debug("gtt_sa_num_of_chunks = %d, gtt_sa_bitmap = %p\n",
1069 kfd->gtt_sa_num_of_chunks, kfd->gtt_sa_bitmap);
1070
1071 mutex_init(&kfd->gtt_sa_lock);
1072
1073 return 0;
1074
1075}
1076
1077static void kfd_gtt_sa_fini(struct kfd_dev *kfd)
1078{
1079 mutex_destroy(&kfd->gtt_sa_lock);
1080 kfree(kfd->gtt_sa_bitmap);
1081}
1082
1083static inline uint64_t kfd_gtt_sa_calc_gpu_addr(uint64_t start_addr,
1084 unsigned int bit_num,
1085 unsigned int chunk_size)
1086{
1087 return start_addr + bit_num * chunk_size;
1088}
1089
1090static inline uint32_t *kfd_gtt_sa_calc_cpu_addr(void *start_addr,
1091 unsigned int bit_num,
1092 unsigned int chunk_size)
1093{
1094 return (uint32_t *) ((uint64_t) start_addr + bit_num * chunk_size);
1095}
1096
1097int kfd_gtt_sa_allocate(struct kfd_dev *kfd, unsigned int size,
1098 struct kfd_mem_obj **mem_obj)
1099{
1100 unsigned int found, start_search, cur_size;
1101
1102 if (size == 0)
1103 return -EINVAL;
1104
1105 if (size > kfd->gtt_sa_num_of_chunks * kfd->gtt_sa_chunk_size)
1106 return -ENOMEM;
1107
1108 *mem_obj = kzalloc(sizeof(struct kfd_mem_obj), GFP_KERNEL);
1109 if (!(*mem_obj))
1110 return -ENOMEM;
1111
1112 pr_debug("Allocated mem_obj = %p for size = %d\n", *mem_obj, size);
1113
1114 start_search = 0;
1115
1116 mutex_lock(&kfd->gtt_sa_lock);
1117
1118kfd_gtt_restart_search:
1119 /* Find the first chunk that is free */
1120 found = find_next_zero_bit(kfd->gtt_sa_bitmap,
1121 kfd->gtt_sa_num_of_chunks,
1122 start_search);
1123
1124 pr_debug("Found = %d\n", found);
1125
1126 /* If there wasn't any free chunk, bail out */
1127 if (found == kfd->gtt_sa_num_of_chunks)
1128 goto kfd_gtt_no_free_chunk;
1129
1130 /* Update fields of mem_obj */
1131 (*mem_obj)->range_start = found;
1132 (*mem_obj)->range_end = found;
1133 (*mem_obj)->gpu_addr = kfd_gtt_sa_calc_gpu_addr(
1134 kfd->gtt_start_gpu_addr,
1135 found,
1136 kfd->gtt_sa_chunk_size);
1137 (*mem_obj)->cpu_ptr = kfd_gtt_sa_calc_cpu_addr(
1138 kfd->gtt_start_cpu_ptr,
1139 found,
1140 kfd->gtt_sa_chunk_size);
1141
1142 pr_debug("gpu_addr = %p, cpu_addr = %p\n",
1143 (uint64_t *) (*mem_obj)->gpu_addr, (*mem_obj)->cpu_ptr);
1144
1145 /* If we need only one chunk, mark it as allocated and get out */
1146 if (size <= kfd->gtt_sa_chunk_size) {
1147 pr_debug("Single bit\n");
1148 set_bit(found, kfd->gtt_sa_bitmap);
1149 goto kfd_gtt_out;
1150 }
1151
1152 /* Otherwise, try to see if we have enough contiguous chunks */
1153 cur_size = size - kfd->gtt_sa_chunk_size;
1154 do {
1155 (*mem_obj)->range_end =
1156 find_next_zero_bit(kfd->gtt_sa_bitmap,
1157 kfd->gtt_sa_num_of_chunks, ++found);
1158 /*
1159 * If next free chunk is not contiguous than we need to
1160 * restart our search from the last free chunk we found (which
1161 * wasn't contiguous to the previous ones
1162 */
1163 if ((*mem_obj)->range_end != found) {
1164 start_search = found;
1165 goto kfd_gtt_restart_search;
1166 }
1167
1168 /*
1169 * If we reached end of buffer, bail out with error
1170 */
1171 if (found == kfd->gtt_sa_num_of_chunks)
1172 goto kfd_gtt_no_free_chunk;
1173
1174 /* Check if we don't need another chunk */
1175 if (cur_size <= kfd->gtt_sa_chunk_size)
1176 cur_size = 0;
1177 else
1178 cur_size -= kfd->gtt_sa_chunk_size;
1179
1180 } while (cur_size > 0);
1181
1182 pr_debug("range_start = %d, range_end = %d\n",
1183 (*mem_obj)->range_start, (*mem_obj)->range_end);
1184
1185 /* Mark the chunks as allocated */
1186 for (found = (*mem_obj)->range_start;
1187 found <= (*mem_obj)->range_end;
1188 found++)
1189 set_bit(found, kfd->gtt_sa_bitmap);
1190
1191kfd_gtt_out:
1192 mutex_unlock(&kfd->gtt_sa_lock);
1193 return 0;
1194
1195kfd_gtt_no_free_chunk:
1196 pr_debug("Allocation failed with mem_obj = %p\n", *mem_obj);
1197 mutex_unlock(&kfd->gtt_sa_lock);
1198 kfree(*mem_obj);
1199 return -ENOMEM;
1200}
1201
1202int kfd_gtt_sa_free(struct kfd_dev *kfd, struct kfd_mem_obj *mem_obj)
1203{
1204 unsigned int bit;
1205
1206 /* Act like kfree when trying to free a NULL object */
1207 if (!mem_obj)
1208 return 0;
1209
1210 pr_debug("Free mem_obj = %p, range_start = %d, range_end = %d\n",
1211 mem_obj, mem_obj->range_start, mem_obj->range_end);
1212
1213 mutex_lock(&kfd->gtt_sa_lock);
1214
1215 /* Mark the chunks as free */
1216 for (bit = mem_obj->range_start;
1217 bit <= mem_obj->range_end;
1218 bit++)
1219 clear_bit(bit, kfd->gtt_sa_bitmap);
1220
1221 mutex_unlock(&kfd->gtt_sa_lock);
1222
1223 kfree(mem_obj);
1224 return 0;
1225}
1226
1227void kgd2kfd_set_sram_ecc_flag(struct kfd_dev *kfd)
1228{
1229 if (kfd)
1230 atomic_inc(&kfd->sram_ecc_flag);
1231}
1232
1233void kfd_inc_compute_active(struct kfd_dev *kfd)
1234{
1235 if (atomic_inc_return(&kfd->compute_profile) == 1)
1236 amdgpu_amdkfd_set_compute_idle(kfd->kgd, false);
1237}
1238
1239void kfd_dec_compute_active(struct kfd_dev *kfd)
1240{
1241 int count = atomic_dec_return(&kfd->compute_profile);
1242
1243 if (count == 0)
1244 amdgpu_amdkfd_set_compute_idle(kfd->kgd, true);
1245 WARN_ONCE(count < 0, "Compute profile ref. count error");
1246}
1247
1248#if defined(CONFIG_DEBUG_FS)
1249
1250/* This function will send a package to HIQ to hang the HWS
1251 * which will trigger a GPU reset and bring the HWS back to normal state
1252 */
1253int kfd_debugfs_hang_hws(struct kfd_dev *dev)
1254{
1255 int r = 0;
1256
1257 if (dev->dqm->sched_policy != KFD_SCHED_POLICY_HWS) {
1258 pr_err("HWS is not enabled");
1259 return -EINVAL;
1260 }
1261
1262 r = pm_debugfs_hang_hws(&dev->dqm->packets);
1263 if (!r)
1264 r = dqm_debugfs_execute_queues(dev->dqm);
1265
1266 return r;
1267}
1268
1269#endif
1/*
2 * Copyright 2014 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22
23#include <linux/bsearch.h>
24#include <linux/pci.h>
25#include <linux/slab.h>
26#include "kfd_priv.h"
27#include "kfd_device_queue_manager.h"
28#include "kfd_pm4_headers_vi.h"
29#include "cwsr_trap_handler.h"
30#include "kfd_iommu.h"
31#include "amdgpu_amdkfd.h"
32
33#define MQD_SIZE_ALIGNED 768
34
35/*
36 * kfd_locked is used to lock the kfd driver during suspend or reset
37 * once locked, kfd driver will stop any further GPU execution.
38 * create process (open) will return -EAGAIN.
39 */
40static atomic_t kfd_locked = ATOMIC_INIT(0);
41
42#ifdef KFD_SUPPORT_IOMMU_V2
43static const struct kfd_device_info kaveri_device_info = {
44 .asic_family = CHIP_KAVERI,
45 .asic_name = "kaveri",
46 .max_pasid_bits = 16,
47 /* max num of queues for KV.TODO should be a dynamic value */
48 .max_no_of_hqd = 24,
49 .doorbell_size = 4,
50 .ih_ring_entry_size = 4 * sizeof(uint32_t),
51 .event_interrupt_class = &event_interrupt_class_cik,
52 .num_of_watch_points = 4,
53 .mqd_size_aligned = MQD_SIZE_ALIGNED,
54 .supports_cwsr = false,
55 .needs_iommu_device = true,
56 .needs_pci_atomics = false,
57 .num_sdma_engines = 2,
58 .num_xgmi_sdma_engines = 0,
59 .num_sdma_queues_per_engine = 2,
60};
61
62static const struct kfd_device_info carrizo_device_info = {
63 .asic_family = CHIP_CARRIZO,
64 .asic_name = "carrizo",
65 .max_pasid_bits = 16,
66 /* max num of queues for CZ.TODO should be a dynamic value */
67 .max_no_of_hqd = 24,
68 .doorbell_size = 4,
69 .ih_ring_entry_size = 4 * sizeof(uint32_t),
70 .event_interrupt_class = &event_interrupt_class_cik,
71 .num_of_watch_points = 4,
72 .mqd_size_aligned = MQD_SIZE_ALIGNED,
73 .supports_cwsr = true,
74 .needs_iommu_device = true,
75 .needs_pci_atomics = false,
76 .num_sdma_engines = 2,
77 .num_xgmi_sdma_engines = 0,
78 .num_sdma_queues_per_engine = 2,
79};
80
81static const struct kfd_device_info raven_device_info = {
82 .asic_family = CHIP_RAVEN,
83 .asic_name = "raven",
84 .max_pasid_bits = 16,
85 .max_no_of_hqd = 24,
86 .doorbell_size = 8,
87 .ih_ring_entry_size = 8 * sizeof(uint32_t),
88 .event_interrupt_class = &event_interrupt_class_v9,
89 .num_of_watch_points = 4,
90 .mqd_size_aligned = MQD_SIZE_ALIGNED,
91 .supports_cwsr = true,
92 .needs_iommu_device = true,
93 .needs_pci_atomics = true,
94 .num_sdma_engines = 1,
95 .num_xgmi_sdma_engines = 0,
96 .num_sdma_queues_per_engine = 2,
97};
98#endif
99
100static const struct kfd_device_info hawaii_device_info = {
101 .asic_family = CHIP_HAWAII,
102 .asic_name = "hawaii",
103 .max_pasid_bits = 16,
104 /* max num of queues for KV.TODO should be a dynamic value */
105 .max_no_of_hqd = 24,
106 .doorbell_size = 4,
107 .ih_ring_entry_size = 4 * sizeof(uint32_t),
108 .event_interrupt_class = &event_interrupt_class_cik,
109 .num_of_watch_points = 4,
110 .mqd_size_aligned = MQD_SIZE_ALIGNED,
111 .supports_cwsr = false,
112 .needs_iommu_device = false,
113 .needs_pci_atomics = false,
114 .num_sdma_engines = 2,
115 .num_xgmi_sdma_engines = 0,
116 .num_sdma_queues_per_engine = 2,
117};
118
119static const struct kfd_device_info tonga_device_info = {
120 .asic_family = CHIP_TONGA,
121 .asic_name = "tonga",
122 .max_pasid_bits = 16,
123 .max_no_of_hqd = 24,
124 .doorbell_size = 4,
125 .ih_ring_entry_size = 4 * sizeof(uint32_t),
126 .event_interrupt_class = &event_interrupt_class_cik,
127 .num_of_watch_points = 4,
128 .mqd_size_aligned = MQD_SIZE_ALIGNED,
129 .supports_cwsr = false,
130 .needs_iommu_device = false,
131 .needs_pci_atomics = true,
132 .num_sdma_engines = 2,
133 .num_xgmi_sdma_engines = 0,
134 .num_sdma_queues_per_engine = 2,
135};
136
137static const struct kfd_device_info fiji_device_info = {
138 .asic_family = CHIP_FIJI,
139 .asic_name = "fiji",
140 .max_pasid_bits = 16,
141 .max_no_of_hqd = 24,
142 .doorbell_size = 4,
143 .ih_ring_entry_size = 4 * sizeof(uint32_t),
144 .event_interrupt_class = &event_interrupt_class_cik,
145 .num_of_watch_points = 4,
146 .mqd_size_aligned = MQD_SIZE_ALIGNED,
147 .supports_cwsr = true,
148 .needs_iommu_device = false,
149 .needs_pci_atomics = true,
150 .num_sdma_engines = 2,
151 .num_xgmi_sdma_engines = 0,
152 .num_sdma_queues_per_engine = 2,
153};
154
155static const struct kfd_device_info fiji_vf_device_info = {
156 .asic_family = CHIP_FIJI,
157 .asic_name = "fiji",
158 .max_pasid_bits = 16,
159 .max_no_of_hqd = 24,
160 .doorbell_size = 4,
161 .ih_ring_entry_size = 4 * sizeof(uint32_t),
162 .event_interrupt_class = &event_interrupt_class_cik,
163 .num_of_watch_points = 4,
164 .mqd_size_aligned = MQD_SIZE_ALIGNED,
165 .supports_cwsr = true,
166 .needs_iommu_device = false,
167 .needs_pci_atomics = false,
168 .num_sdma_engines = 2,
169 .num_xgmi_sdma_engines = 0,
170 .num_sdma_queues_per_engine = 2,
171};
172
173
174static const struct kfd_device_info polaris10_device_info = {
175 .asic_family = CHIP_POLARIS10,
176 .asic_name = "polaris10",
177 .max_pasid_bits = 16,
178 .max_no_of_hqd = 24,
179 .doorbell_size = 4,
180 .ih_ring_entry_size = 4 * sizeof(uint32_t),
181 .event_interrupt_class = &event_interrupt_class_cik,
182 .num_of_watch_points = 4,
183 .mqd_size_aligned = MQD_SIZE_ALIGNED,
184 .supports_cwsr = true,
185 .needs_iommu_device = false,
186 .needs_pci_atomics = true,
187 .num_sdma_engines = 2,
188 .num_xgmi_sdma_engines = 0,
189 .num_sdma_queues_per_engine = 2,
190};
191
192static const struct kfd_device_info polaris10_vf_device_info = {
193 .asic_family = CHIP_POLARIS10,
194 .asic_name = "polaris10",
195 .max_pasid_bits = 16,
196 .max_no_of_hqd = 24,
197 .doorbell_size = 4,
198 .ih_ring_entry_size = 4 * sizeof(uint32_t),
199 .event_interrupt_class = &event_interrupt_class_cik,
200 .num_of_watch_points = 4,
201 .mqd_size_aligned = MQD_SIZE_ALIGNED,
202 .supports_cwsr = true,
203 .needs_iommu_device = false,
204 .needs_pci_atomics = false,
205 .num_sdma_engines = 2,
206 .num_xgmi_sdma_engines = 0,
207 .num_sdma_queues_per_engine = 2,
208};
209
210static const struct kfd_device_info polaris11_device_info = {
211 .asic_family = CHIP_POLARIS11,
212 .asic_name = "polaris11",
213 .max_pasid_bits = 16,
214 .max_no_of_hqd = 24,
215 .doorbell_size = 4,
216 .ih_ring_entry_size = 4 * sizeof(uint32_t),
217 .event_interrupt_class = &event_interrupt_class_cik,
218 .num_of_watch_points = 4,
219 .mqd_size_aligned = MQD_SIZE_ALIGNED,
220 .supports_cwsr = true,
221 .needs_iommu_device = false,
222 .needs_pci_atomics = true,
223 .num_sdma_engines = 2,
224 .num_xgmi_sdma_engines = 0,
225 .num_sdma_queues_per_engine = 2,
226};
227
228static const struct kfd_device_info polaris12_device_info = {
229 .asic_family = CHIP_POLARIS12,
230 .asic_name = "polaris12",
231 .max_pasid_bits = 16,
232 .max_no_of_hqd = 24,
233 .doorbell_size = 4,
234 .ih_ring_entry_size = 4 * sizeof(uint32_t),
235 .event_interrupt_class = &event_interrupt_class_cik,
236 .num_of_watch_points = 4,
237 .mqd_size_aligned = MQD_SIZE_ALIGNED,
238 .supports_cwsr = true,
239 .needs_iommu_device = false,
240 .needs_pci_atomics = true,
241 .num_sdma_engines = 2,
242 .num_xgmi_sdma_engines = 0,
243 .num_sdma_queues_per_engine = 2,
244};
245
246static const struct kfd_device_info vegam_device_info = {
247 .asic_family = CHIP_VEGAM,
248 .asic_name = "vegam",
249 .max_pasid_bits = 16,
250 .max_no_of_hqd = 24,
251 .doorbell_size = 4,
252 .ih_ring_entry_size = 4 * sizeof(uint32_t),
253 .event_interrupt_class = &event_interrupt_class_cik,
254 .num_of_watch_points = 4,
255 .mqd_size_aligned = MQD_SIZE_ALIGNED,
256 .supports_cwsr = true,
257 .needs_iommu_device = false,
258 .needs_pci_atomics = true,
259 .num_sdma_engines = 2,
260 .num_xgmi_sdma_engines = 0,
261 .num_sdma_queues_per_engine = 2,
262};
263
264static const struct kfd_device_info vega10_device_info = {
265 .asic_family = CHIP_VEGA10,
266 .asic_name = "vega10",
267 .max_pasid_bits = 16,
268 .max_no_of_hqd = 24,
269 .doorbell_size = 8,
270 .ih_ring_entry_size = 8 * sizeof(uint32_t),
271 .event_interrupt_class = &event_interrupt_class_v9,
272 .num_of_watch_points = 4,
273 .mqd_size_aligned = MQD_SIZE_ALIGNED,
274 .supports_cwsr = true,
275 .needs_iommu_device = false,
276 .needs_pci_atomics = false,
277 .num_sdma_engines = 2,
278 .num_xgmi_sdma_engines = 0,
279 .num_sdma_queues_per_engine = 2,
280};
281
282static const struct kfd_device_info vega10_vf_device_info = {
283 .asic_family = CHIP_VEGA10,
284 .asic_name = "vega10",
285 .max_pasid_bits = 16,
286 .max_no_of_hqd = 24,
287 .doorbell_size = 8,
288 .ih_ring_entry_size = 8 * sizeof(uint32_t),
289 .event_interrupt_class = &event_interrupt_class_v9,
290 .num_of_watch_points = 4,
291 .mqd_size_aligned = MQD_SIZE_ALIGNED,
292 .supports_cwsr = true,
293 .needs_iommu_device = false,
294 .needs_pci_atomics = false,
295 .num_sdma_engines = 2,
296 .num_xgmi_sdma_engines = 0,
297 .num_sdma_queues_per_engine = 2,
298};
299
300static const struct kfd_device_info vega12_device_info = {
301 .asic_family = CHIP_VEGA12,
302 .asic_name = "vega12",
303 .max_pasid_bits = 16,
304 .max_no_of_hqd = 24,
305 .doorbell_size = 8,
306 .ih_ring_entry_size = 8 * sizeof(uint32_t),
307 .event_interrupt_class = &event_interrupt_class_v9,
308 .num_of_watch_points = 4,
309 .mqd_size_aligned = MQD_SIZE_ALIGNED,
310 .supports_cwsr = true,
311 .needs_iommu_device = false,
312 .needs_pci_atomics = false,
313 .num_sdma_engines = 2,
314 .num_xgmi_sdma_engines = 0,
315 .num_sdma_queues_per_engine = 2,
316};
317
318static const struct kfd_device_info vega20_device_info = {
319 .asic_family = CHIP_VEGA20,
320 .asic_name = "vega20",
321 .max_pasid_bits = 16,
322 .max_no_of_hqd = 24,
323 .doorbell_size = 8,
324 .ih_ring_entry_size = 8 * sizeof(uint32_t),
325 .event_interrupt_class = &event_interrupt_class_v9,
326 .num_of_watch_points = 4,
327 .mqd_size_aligned = MQD_SIZE_ALIGNED,
328 .supports_cwsr = true,
329 .needs_iommu_device = false,
330 .needs_pci_atomics = false,
331 .num_sdma_engines = 2,
332 .num_xgmi_sdma_engines = 0,
333 .num_sdma_queues_per_engine = 8,
334};
335
336static const struct kfd_device_info arcturus_device_info = {
337 .asic_family = CHIP_ARCTURUS,
338 .asic_name = "arcturus",
339 .max_pasid_bits = 16,
340 .max_no_of_hqd = 24,
341 .doorbell_size = 8,
342 .ih_ring_entry_size = 8 * sizeof(uint32_t),
343 .event_interrupt_class = &event_interrupt_class_v9,
344 .num_of_watch_points = 4,
345 .mqd_size_aligned = MQD_SIZE_ALIGNED,
346 .supports_cwsr = true,
347 .needs_iommu_device = false,
348 .needs_pci_atomics = false,
349 .num_sdma_engines = 2,
350 .num_xgmi_sdma_engines = 6,
351 .num_sdma_queues_per_engine = 8,
352};
353
354static const struct kfd_device_info navi10_device_info = {
355 .asic_family = CHIP_NAVI10,
356 .asic_name = "navi10",
357 .max_pasid_bits = 16,
358 .max_no_of_hqd = 24,
359 .doorbell_size = 8,
360 .ih_ring_entry_size = 8 * sizeof(uint32_t),
361 .event_interrupt_class = &event_interrupt_class_v9,
362 .num_of_watch_points = 4,
363 .mqd_size_aligned = MQD_SIZE_ALIGNED,
364 .needs_iommu_device = false,
365 .supports_cwsr = true,
366 .needs_pci_atomics = false,
367 .num_sdma_engines = 2,
368 .num_xgmi_sdma_engines = 0,
369 .num_sdma_queues_per_engine = 8,
370};
371
372struct kfd_deviceid {
373 unsigned short did;
374 const struct kfd_device_info *device_info;
375};
376
377static const struct kfd_deviceid supported_devices[] = {
378#ifdef KFD_SUPPORT_IOMMU_V2
379 { 0x1304, &kaveri_device_info }, /* Kaveri */
380 { 0x1305, &kaveri_device_info }, /* Kaveri */
381 { 0x1306, &kaveri_device_info }, /* Kaveri */
382 { 0x1307, &kaveri_device_info }, /* Kaveri */
383 { 0x1309, &kaveri_device_info }, /* Kaveri */
384 { 0x130A, &kaveri_device_info }, /* Kaveri */
385 { 0x130B, &kaveri_device_info }, /* Kaveri */
386 { 0x130C, &kaveri_device_info }, /* Kaveri */
387 { 0x130D, &kaveri_device_info }, /* Kaveri */
388 { 0x130E, &kaveri_device_info }, /* Kaveri */
389 { 0x130F, &kaveri_device_info }, /* Kaveri */
390 { 0x1310, &kaveri_device_info }, /* Kaveri */
391 { 0x1311, &kaveri_device_info }, /* Kaveri */
392 { 0x1312, &kaveri_device_info }, /* Kaveri */
393 { 0x1313, &kaveri_device_info }, /* Kaveri */
394 { 0x1315, &kaveri_device_info }, /* Kaveri */
395 { 0x1316, &kaveri_device_info }, /* Kaveri */
396 { 0x1317, &kaveri_device_info }, /* Kaveri */
397 { 0x1318, &kaveri_device_info }, /* Kaveri */
398 { 0x131B, &kaveri_device_info }, /* Kaveri */
399 { 0x131C, &kaveri_device_info }, /* Kaveri */
400 { 0x131D, &kaveri_device_info }, /* Kaveri */
401 { 0x9870, &carrizo_device_info }, /* Carrizo */
402 { 0x9874, &carrizo_device_info }, /* Carrizo */
403 { 0x9875, &carrizo_device_info }, /* Carrizo */
404 { 0x9876, &carrizo_device_info }, /* Carrizo */
405 { 0x9877, &carrizo_device_info }, /* Carrizo */
406 { 0x15DD, &raven_device_info }, /* Raven */
407 { 0x15D8, &raven_device_info }, /* Raven */
408#endif
409 { 0x67A0, &hawaii_device_info }, /* Hawaii */
410 { 0x67A1, &hawaii_device_info }, /* Hawaii */
411 { 0x67A2, &hawaii_device_info }, /* Hawaii */
412 { 0x67A8, &hawaii_device_info }, /* Hawaii */
413 { 0x67A9, &hawaii_device_info }, /* Hawaii */
414 { 0x67AA, &hawaii_device_info }, /* Hawaii */
415 { 0x67B0, &hawaii_device_info }, /* Hawaii */
416 { 0x67B1, &hawaii_device_info }, /* Hawaii */
417 { 0x67B8, &hawaii_device_info }, /* Hawaii */
418 { 0x67B9, &hawaii_device_info }, /* Hawaii */
419 { 0x67BA, &hawaii_device_info }, /* Hawaii */
420 { 0x67BE, &hawaii_device_info }, /* Hawaii */
421 { 0x6920, &tonga_device_info }, /* Tonga */
422 { 0x6921, &tonga_device_info }, /* Tonga */
423 { 0x6928, &tonga_device_info }, /* Tonga */
424 { 0x6929, &tonga_device_info }, /* Tonga */
425 { 0x692B, &tonga_device_info }, /* Tonga */
426 { 0x6938, &tonga_device_info }, /* Tonga */
427 { 0x6939, &tonga_device_info }, /* Tonga */
428 { 0x7300, &fiji_device_info }, /* Fiji */
429 { 0x730F, &fiji_vf_device_info }, /* Fiji vf*/
430 { 0x67C0, &polaris10_device_info }, /* Polaris10 */
431 { 0x67C1, &polaris10_device_info }, /* Polaris10 */
432 { 0x67C2, &polaris10_device_info }, /* Polaris10 */
433 { 0x67C4, &polaris10_device_info }, /* Polaris10 */
434 { 0x67C7, &polaris10_device_info }, /* Polaris10 */
435 { 0x67C8, &polaris10_device_info }, /* Polaris10 */
436 { 0x67C9, &polaris10_device_info }, /* Polaris10 */
437 { 0x67CA, &polaris10_device_info }, /* Polaris10 */
438 { 0x67CC, &polaris10_device_info }, /* Polaris10 */
439 { 0x67CF, &polaris10_device_info }, /* Polaris10 */
440 { 0x67D0, &polaris10_vf_device_info }, /* Polaris10 vf*/
441 { 0x67DF, &polaris10_device_info }, /* Polaris10 */
442 { 0x6FDF, &polaris10_device_info }, /* Polaris10 */
443 { 0x67E0, &polaris11_device_info }, /* Polaris11 */
444 { 0x67E1, &polaris11_device_info }, /* Polaris11 */
445 { 0x67E3, &polaris11_device_info }, /* Polaris11 */
446 { 0x67E7, &polaris11_device_info }, /* Polaris11 */
447 { 0x67E8, &polaris11_device_info }, /* Polaris11 */
448 { 0x67E9, &polaris11_device_info }, /* Polaris11 */
449 { 0x67EB, &polaris11_device_info }, /* Polaris11 */
450 { 0x67EF, &polaris11_device_info }, /* Polaris11 */
451 { 0x67FF, &polaris11_device_info }, /* Polaris11 */
452 { 0x6980, &polaris12_device_info }, /* Polaris12 */
453 { 0x6981, &polaris12_device_info }, /* Polaris12 */
454 { 0x6985, &polaris12_device_info }, /* Polaris12 */
455 { 0x6986, &polaris12_device_info }, /* Polaris12 */
456 { 0x6987, &polaris12_device_info }, /* Polaris12 */
457 { 0x6995, &polaris12_device_info }, /* Polaris12 */
458 { 0x6997, &polaris12_device_info }, /* Polaris12 */
459 { 0x699F, &polaris12_device_info }, /* Polaris12 */
460 { 0x694C, &vegam_device_info }, /* VegaM */
461 { 0x694E, &vegam_device_info }, /* VegaM */
462 { 0x694F, &vegam_device_info }, /* VegaM */
463 { 0x6860, &vega10_device_info }, /* Vega10 */
464 { 0x6861, &vega10_device_info }, /* Vega10 */
465 { 0x6862, &vega10_device_info }, /* Vega10 */
466 { 0x6863, &vega10_device_info }, /* Vega10 */
467 { 0x6864, &vega10_device_info }, /* Vega10 */
468 { 0x6867, &vega10_device_info }, /* Vega10 */
469 { 0x6868, &vega10_device_info }, /* Vega10 */
470 { 0x6869, &vega10_device_info }, /* Vega10 */
471 { 0x686A, &vega10_device_info }, /* Vega10 */
472 { 0x686B, &vega10_device_info }, /* Vega10 */
473 { 0x686C, &vega10_vf_device_info }, /* Vega10 vf*/
474 { 0x686D, &vega10_device_info }, /* Vega10 */
475 { 0x686E, &vega10_device_info }, /* Vega10 */
476 { 0x686F, &vega10_device_info }, /* Vega10 */
477 { 0x687F, &vega10_device_info }, /* Vega10 */
478 { 0x69A0, &vega12_device_info }, /* Vega12 */
479 { 0x69A1, &vega12_device_info }, /* Vega12 */
480 { 0x69A2, &vega12_device_info }, /* Vega12 */
481 { 0x69A3, &vega12_device_info }, /* Vega12 */
482 { 0x69AF, &vega12_device_info }, /* Vega12 */
483 { 0x66a0, &vega20_device_info }, /* Vega20 */
484 { 0x66a1, &vega20_device_info }, /* Vega20 */
485 { 0x66a2, &vega20_device_info }, /* Vega20 */
486 { 0x66a3, &vega20_device_info }, /* Vega20 */
487 { 0x66a4, &vega20_device_info }, /* Vega20 */
488 { 0x66a7, &vega20_device_info }, /* Vega20 */
489 { 0x66af, &vega20_device_info }, /* Vega20 */
490 { 0x738C, &arcturus_device_info }, /* Arcturus */
491 { 0x7388, &arcturus_device_info }, /* Arcturus */
492 { 0x738E, &arcturus_device_info }, /* Arcturus */
493 { 0x7390, &arcturus_device_info }, /* Arcturus vf */
494 { 0x7310, &navi10_device_info }, /* Navi10 */
495 { 0x7312, &navi10_device_info }, /* Navi10 */
496 { 0x7318, &navi10_device_info }, /* Navi10 */
497 { 0x731a, &navi10_device_info }, /* Navi10 */
498 { 0x731f, &navi10_device_info }, /* Navi10 */
499};
500
501static int kfd_gtt_sa_init(struct kfd_dev *kfd, unsigned int buf_size,
502 unsigned int chunk_size);
503static void kfd_gtt_sa_fini(struct kfd_dev *kfd);
504
505static int kfd_resume(struct kfd_dev *kfd);
506
507static const struct kfd_device_info *lookup_device_info(unsigned short did)
508{
509 size_t i;
510
511 for (i = 0; i < ARRAY_SIZE(supported_devices); i++) {
512 if (supported_devices[i].did == did) {
513 WARN_ON(!supported_devices[i].device_info);
514 return supported_devices[i].device_info;
515 }
516 }
517
518 dev_warn(kfd_device, "DID %04x is missing in supported_devices\n",
519 did);
520
521 return NULL;
522}
523
524struct kfd_dev *kgd2kfd_probe(struct kgd_dev *kgd,
525 struct pci_dev *pdev, const struct kfd2kgd_calls *f2g)
526{
527 struct kfd_dev *kfd;
528 const struct kfd_device_info *device_info =
529 lookup_device_info(pdev->device);
530
531 if (!device_info) {
532 dev_err(kfd_device, "kgd2kfd_probe failed\n");
533 return NULL;
534 }
535
536 kfd = kzalloc(sizeof(*kfd), GFP_KERNEL);
537 if (!kfd)
538 return NULL;
539
540 /* Allow BIF to recode atomics to PCIe 3.0 AtomicOps.
541 * 32 and 64-bit requests are possible and must be
542 * supported.
543 */
544 kfd->pci_atomic_requested = amdgpu_amdkfd_have_atomics_support(kgd);
545 if (device_info->needs_pci_atomics &&
546 !kfd->pci_atomic_requested) {
547 dev_info(kfd_device,
548 "skipped device %x:%x, PCI rejects atomics\n",
549 pdev->vendor, pdev->device);
550 kfree(kfd);
551 return NULL;
552 }
553
554 kfd->kgd = kgd;
555 kfd->device_info = device_info;
556 kfd->pdev = pdev;
557 kfd->init_complete = false;
558 kfd->kfd2kgd = f2g;
559 atomic_set(&kfd->compute_profile, 0);
560
561 mutex_init(&kfd->doorbell_mutex);
562 memset(&kfd->doorbell_available_index, 0,
563 sizeof(kfd->doorbell_available_index));
564
565 atomic_set(&kfd->sram_ecc_flag, 0);
566
567 return kfd;
568}
569
570static void kfd_cwsr_init(struct kfd_dev *kfd)
571{
572 if (cwsr_enable && kfd->device_info->supports_cwsr) {
573 if (kfd->device_info->asic_family < CHIP_VEGA10) {
574 BUILD_BUG_ON(sizeof(cwsr_trap_gfx8_hex) > PAGE_SIZE);
575 kfd->cwsr_isa = cwsr_trap_gfx8_hex;
576 kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx8_hex);
577 } else if (kfd->device_info->asic_family == CHIP_ARCTURUS) {
578 BUILD_BUG_ON(sizeof(cwsr_trap_arcturus_hex) > PAGE_SIZE);
579 kfd->cwsr_isa = cwsr_trap_arcturus_hex;
580 kfd->cwsr_isa_size = sizeof(cwsr_trap_arcturus_hex);
581 } else if (kfd->device_info->asic_family < CHIP_NAVI10) {
582 BUILD_BUG_ON(sizeof(cwsr_trap_gfx9_hex) > PAGE_SIZE);
583 kfd->cwsr_isa = cwsr_trap_gfx9_hex;
584 kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx9_hex);
585 } else {
586 BUILD_BUG_ON(sizeof(cwsr_trap_gfx10_hex) > PAGE_SIZE);
587 kfd->cwsr_isa = cwsr_trap_gfx10_hex;
588 kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx10_hex);
589 }
590
591 kfd->cwsr_enabled = true;
592 }
593}
594
595bool kgd2kfd_device_init(struct kfd_dev *kfd,
596 const struct kgd2kfd_shared_resources *gpu_resources)
597{
598 unsigned int size;
599
600 kfd->mec_fw_version = amdgpu_amdkfd_get_fw_version(kfd->kgd,
601 KGD_ENGINE_MEC1);
602 kfd->sdma_fw_version = amdgpu_amdkfd_get_fw_version(kfd->kgd,
603 KGD_ENGINE_SDMA1);
604 kfd->shared_resources = *gpu_resources;
605
606 kfd->vm_info.first_vmid_kfd = ffs(gpu_resources->compute_vmid_bitmap)-1;
607 kfd->vm_info.last_vmid_kfd = fls(gpu_resources->compute_vmid_bitmap)-1;
608 kfd->vm_info.vmid_num_kfd = kfd->vm_info.last_vmid_kfd
609 - kfd->vm_info.first_vmid_kfd + 1;
610
611 /* Verify module parameters regarding mapped process number*/
612 if ((hws_max_conc_proc < 0)
613 || (hws_max_conc_proc > kfd->vm_info.vmid_num_kfd)) {
614 dev_err(kfd_device,
615 "hws_max_conc_proc %d must be between 0 and %d, use %d instead\n",
616 hws_max_conc_proc, kfd->vm_info.vmid_num_kfd,
617 kfd->vm_info.vmid_num_kfd);
618 kfd->max_proc_per_quantum = kfd->vm_info.vmid_num_kfd;
619 } else
620 kfd->max_proc_per_quantum = hws_max_conc_proc;
621
622 /* Allocate global GWS that is shared by all KFD processes */
623 if (hws_gws_support && amdgpu_amdkfd_alloc_gws(kfd->kgd,
624 amdgpu_amdkfd_get_num_gws(kfd->kgd), &kfd->gws)) {
625 dev_err(kfd_device, "Could not allocate %d gws\n",
626 amdgpu_amdkfd_get_num_gws(kfd->kgd));
627 goto out;
628 }
629 /* calculate max size of mqds needed for queues */
630 size = max_num_of_queues_per_device *
631 kfd->device_info->mqd_size_aligned;
632
633 /*
634 * calculate max size of runlist packet.
635 * There can be only 2 packets at once
636 */
637 size += (KFD_MAX_NUM_OF_PROCESSES * sizeof(struct pm4_mes_map_process) +
638 max_num_of_queues_per_device * sizeof(struct pm4_mes_map_queues)
639 + sizeof(struct pm4_mes_runlist)) * 2;
640
641 /* Add size of HIQ & DIQ */
642 size += KFD_KERNEL_QUEUE_SIZE * 2;
643
644 /* add another 512KB for all other allocations on gart (HPD, fences) */
645 size += 512 * 1024;
646
647 if (amdgpu_amdkfd_alloc_gtt_mem(
648 kfd->kgd, size, &kfd->gtt_mem,
649 &kfd->gtt_start_gpu_addr, &kfd->gtt_start_cpu_ptr,
650 false)) {
651 dev_err(kfd_device, "Could not allocate %d bytes\n", size);
652 goto alloc_gtt_mem_failure;
653 }
654
655 dev_info(kfd_device, "Allocated %d bytes on gart\n", size);
656
657 /* Initialize GTT sa with 512 byte chunk size */
658 if (kfd_gtt_sa_init(kfd, size, 512) != 0) {
659 dev_err(kfd_device, "Error initializing gtt sub-allocator\n");
660 goto kfd_gtt_sa_init_error;
661 }
662
663 if (kfd_doorbell_init(kfd)) {
664 dev_err(kfd_device,
665 "Error initializing doorbell aperture\n");
666 goto kfd_doorbell_error;
667 }
668
669 if (kfd->kfd2kgd->get_hive_id)
670 kfd->hive_id = kfd->kfd2kgd->get_hive_id(kfd->kgd);
671
672 if (kfd_interrupt_init(kfd)) {
673 dev_err(kfd_device, "Error initializing interrupts\n");
674 goto kfd_interrupt_error;
675 }
676
677 kfd->dqm = device_queue_manager_init(kfd);
678 if (!kfd->dqm) {
679 dev_err(kfd_device, "Error initializing queue manager\n");
680 goto device_queue_manager_error;
681 }
682
683 if (kfd_iommu_device_init(kfd)) {
684 dev_err(kfd_device, "Error initializing iommuv2\n");
685 goto device_iommu_error;
686 }
687
688 kfd_cwsr_init(kfd);
689
690 if (kfd_resume(kfd))
691 goto kfd_resume_error;
692
693 kfd->dbgmgr = NULL;
694
695 if (kfd_topology_add_device(kfd)) {
696 dev_err(kfd_device, "Error adding device to topology\n");
697 goto kfd_topology_add_device_error;
698 }
699
700 kfd->init_complete = true;
701 dev_info(kfd_device, "added device %x:%x\n", kfd->pdev->vendor,
702 kfd->pdev->device);
703
704 pr_debug("Starting kfd with the following scheduling policy %d\n",
705 kfd->dqm->sched_policy);
706
707 goto out;
708
709kfd_topology_add_device_error:
710kfd_resume_error:
711device_iommu_error:
712 device_queue_manager_uninit(kfd->dqm);
713device_queue_manager_error:
714 kfd_interrupt_exit(kfd);
715kfd_interrupt_error:
716 kfd_doorbell_fini(kfd);
717kfd_doorbell_error:
718 kfd_gtt_sa_fini(kfd);
719kfd_gtt_sa_init_error:
720 amdgpu_amdkfd_free_gtt_mem(kfd->kgd, kfd->gtt_mem);
721alloc_gtt_mem_failure:
722 if (hws_gws_support)
723 amdgpu_amdkfd_free_gws(kfd->kgd, kfd->gws);
724 dev_err(kfd_device,
725 "device %x:%x NOT added due to errors\n",
726 kfd->pdev->vendor, kfd->pdev->device);
727out:
728 return kfd->init_complete;
729}
730
731void kgd2kfd_device_exit(struct kfd_dev *kfd)
732{
733 if (kfd->init_complete) {
734 kgd2kfd_suspend(kfd);
735 device_queue_manager_uninit(kfd->dqm);
736 kfd_interrupt_exit(kfd);
737 kfd_topology_remove_device(kfd);
738 kfd_doorbell_fini(kfd);
739 kfd_gtt_sa_fini(kfd);
740 amdgpu_amdkfd_free_gtt_mem(kfd->kgd, kfd->gtt_mem);
741 if (hws_gws_support)
742 amdgpu_amdkfd_free_gws(kfd->kgd, kfd->gws);
743 }
744
745 kfree(kfd);
746}
747
748int kgd2kfd_pre_reset(struct kfd_dev *kfd)
749{
750 if (!kfd->init_complete)
751 return 0;
752 kgd2kfd_suspend(kfd);
753
754 /* hold dqm->lock to prevent further execution*/
755 dqm_lock(kfd->dqm);
756
757 kfd_signal_reset_event(kfd);
758 return 0;
759}
760
761/*
762 * Fix me. KFD won't be able to resume existing process for now.
763 * We will keep all existing process in a evicted state and
764 * wait the process to be terminated.
765 */
766
767int kgd2kfd_post_reset(struct kfd_dev *kfd)
768{
769 int ret, count;
770
771 if (!kfd->init_complete)
772 return 0;
773
774 dqm_unlock(kfd->dqm);
775
776 ret = kfd_resume(kfd);
777 if (ret)
778 return ret;
779 count = atomic_dec_return(&kfd_locked);
780
781 atomic_set(&kfd->sram_ecc_flag, 0);
782
783 return 0;
784}
785
786bool kfd_is_locked(void)
787{
788 return (atomic_read(&kfd_locked) > 0);
789}
790
791void kgd2kfd_suspend(struct kfd_dev *kfd)
792{
793 if (!kfd->init_complete)
794 return;
795
796 /* For first KFD device suspend all the KFD processes */
797 if (atomic_inc_return(&kfd_locked) == 1)
798 kfd_suspend_all_processes();
799
800 kfd->dqm->ops.stop(kfd->dqm);
801
802 kfd_iommu_suspend(kfd);
803}
804
805int kgd2kfd_resume(struct kfd_dev *kfd)
806{
807 int ret, count;
808
809 if (!kfd->init_complete)
810 return 0;
811
812 ret = kfd_resume(kfd);
813 if (ret)
814 return ret;
815
816 count = atomic_dec_return(&kfd_locked);
817 WARN_ONCE(count < 0, "KFD suspend / resume ref. error");
818 if (count == 0)
819 ret = kfd_resume_all_processes();
820
821 return ret;
822}
823
824static int kfd_resume(struct kfd_dev *kfd)
825{
826 int err = 0;
827
828 err = kfd_iommu_resume(kfd);
829 if (err) {
830 dev_err(kfd_device,
831 "Failed to resume IOMMU for device %x:%x\n",
832 kfd->pdev->vendor, kfd->pdev->device);
833 return err;
834 }
835
836 err = kfd->dqm->ops.start(kfd->dqm);
837 if (err) {
838 dev_err(kfd_device,
839 "Error starting queue manager for device %x:%x\n",
840 kfd->pdev->vendor, kfd->pdev->device);
841 goto dqm_start_error;
842 }
843
844 return err;
845
846dqm_start_error:
847 kfd_iommu_suspend(kfd);
848 return err;
849}
850
851/* This is called directly from KGD at ISR. */
852void kgd2kfd_interrupt(struct kfd_dev *kfd, const void *ih_ring_entry)
853{
854 uint32_t patched_ihre[KFD_MAX_RING_ENTRY_SIZE];
855 bool is_patched = false;
856 unsigned long flags;
857
858 if (!kfd->init_complete)
859 return;
860
861 if (kfd->device_info->ih_ring_entry_size > sizeof(patched_ihre)) {
862 dev_err_once(kfd_device, "Ring entry too small\n");
863 return;
864 }
865
866 spin_lock_irqsave(&kfd->interrupt_lock, flags);
867
868 if (kfd->interrupts_active
869 && interrupt_is_wanted(kfd, ih_ring_entry,
870 patched_ihre, &is_patched)
871 && enqueue_ih_ring_entry(kfd,
872 is_patched ? patched_ihre : ih_ring_entry))
873 queue_work(kfd->ih_wq, &kfd->interrupt_work);
874
875 spin_unlock_irqrestore(&kfd->interrupt_lock, flags);
876}
877
878int kgd2kfd_quiesce_mm(struct mm_struct *mm)
879{
880 struct kfd_process *p;
881 int r;
882
883 /* Because we are called from arbitrary context (workqueue) as opposed
884 * to process context, kfd_process could attempt to exit while we are
885 * running so the lookup function increments the process ref count.
886 */
887 p = kfd_lookup_process_by_mm(mm);
888 if (!p)
889 return -ESRCH;
890
891 r = kfd_process_evict_queues(p);
892
893 kfd_unref_process(p);
894 return r;
895}
896
897int kgd2kfd_resume_mm(struct mm_struct *mm)
898{
899 struct kfd_process *p;
900 int r;
901
902 /* Because we are called from arbitrary context (workqueue) as opposed
903 * to process context, kfd_process could attempt to exit while we are
904 * running so the lookup function increments the process ref count.
905 */
906 p = kfd_lookup_process_by_mm(mm);
907 if (!p)
908 return -ESRCH;
909
910 r = kfd_process_restore_queues(p);
911
912 kfd_unref_process(p);
913 return r;
914}
915
916/** kgd2kfd_schedule_evict_and_restore_process - Schedules work queue that will
917 * prepare for safe eviction of KFD BOs that belong to the specified
918 * process.
919 *
920 * @mm: mm_struct that identifies the specified KFD process
921 * @fence: eviction fence attached to KFD process BOs
922 *
923 */
924int kgd2kfd_schedule_evict_and_restore_process(struct mm_struct *mm,
925 struct dma_fence *fence)
926{
927 struct kfd_process *p;
928 unsigned long active_time;
929 unsigned long delay_jiffies = msecs_to_jiffies(PROCESS_ACTIVE_TIME_MS);
930
931 if (!fence)
932 return -EINVAL;
933
934 if (dma_fence_is_signaled(fence))
935 return 0;
936
937 p = kfd_lookup_process_by_mm(mm);
938 if (!p)
939 return -ENODEV;
940
941 if (fence->seqno == p->last_eviction_seqno)
942 goto out;
943
944 p->last_eviction_seqno = fence->seqno;
945
946 /* Avoid KFD process starvation. Wait for at least
947 * PROCESS_ACTIVE_TIME_MS before evicting the process again
948 */
949 active_time = get_jiffies_64() - p->last_restore_timestamp;
950 if (delay_jiffies > active_time)
951 delay_jiffies -= active_time;
952 else
953 delay_jiffies = 0;
954
955 /* During process initialization eviction_work.dwork is initialized
956 * to kfd_evict_bo_worker
957 */
958 schedule_delayed_work(&p->eviction_work, delay_jiffies);
959out:
960 kfd_unref_process(p);
961 return 0;
962}
963
964static int kfd_gtt_sa_init(struct kfd_dev *kfd, unsigned int buf_size,
965 unsigned int chunk_size)
966{
967 unsigned int num_of_longs;
968
969 if (WARN_ON(buf_size < chunk_size))
970 return -EINVAL;
971 if (WARN_ON(buf_size == 0))
972 return -EINVAL;
973 if (WARN_ON(chunk_size == 0))
974 return -EINVAL;
975
976 kfd->gtt_sa_chunk_size = chunk_size;
977 kfd->gtt_sa_num_of_chunks = buf_size / chunk_size;
978
979 num_of_longs = (kfd->gtt_sa_num_of_chunks + BITS_PER_LONG - 1) /
980 BITS_PER_LONG;
981
982 kfd->gtt_sa_bitmap = kcalloc(num_of_longs, sizeof(long), GFP_KERNEL);
983
984 if (!kfd->gtt_sa_bitmap)
985 return -ENOMEM;
986
987 pr_debug("gtt_sa_num_of_chunks = %d, gtt_sa_bitmap = %p\n",
988 kfd->gtt_sa_num_of_chunks, kfd->gtt_sa_bitmap);
989
990 mutex_init(&kfd->gtt_sa_lock);
991
992 return 0;
993
994}
995
996static void kfd_gtt_sa_fini(struct kfd_dev *kfd)
997{
998 mutex_destroy(&kfd->gtt_sa_lock);
999 kfree(kfd->gtt_sa_bitmap);
1000}
1001
1002static inline uint64_t kfd_gtt_sa_calc_gpu_addr(uint64_t start_addr,
1003 unsigned int bit_num,
1004 unsigned int chunk_size)
1005{
1006 return start_addr + bit_num * chunk_size;
1007}
1008
1009static inline uint32_t *kfd_gtt_sa_calc_cpu_addr(void *start_addr,
1010 unsigned int bit_num,
1011 unsigned int chunk_size)
1012{
1013 return (uint32_t *) ((uint64_t) start_addr + bit_num * chunk_size);
1014}
1015
1016int kfd_gtt_sa_allocate(struct kfd_dev *kfd, unsigned int size,
1017 struct kfd_mem_obj **mem_obj)
1018{
1019 unsigned int found, start_search, cur_size;
1020
1021 if (size == 0)
1022 return -EINVAL;
1023
1024 if (size > kfd->gtt_sa_num_of_chunks * kfd->gtt_sa_chunk_size)
1025 return -ENOMEM;
1026
1027 *mem_obj = kzalloc(sizeof(struct kfd_mem_obj), GFP_KERNEL);
1028 if (!(*mem_obj))
1029 return -ENOMEM;
1030
1031 pr_debug("Allocated mem_obj = %p for size = %d\n", *mem_obj, size);
1032
1033 start_search = 0;
1034
1035 mutex_lock(&kfd->gtt_sa_lock);
1036
1037kfd_gtt_restart_search:
1038 /* Find the first chunk that is free */
1039 found = find_next_zero_bit(kfd->gtt_sa_bitmap,
1040 kfd->gtt_sa_num_of_chunks,
1041 start_search);
1042
1043 pr_debug("Found = %d\n", found);
1044
1045 /* If there wasn't any free chunk, bail out */
1046 if (found == kfd->gtt_sa_num_of_chunks)
1047 goto kfd_gtt_no_free_chunk;
1048
1049 /* Update fields of mem_obj */
1050 (*mem_obj)->range_start = found;
1051 (*mem_obj)->range_end = found;
1052 (*mem_obj)->gpu_addr = kfd_gtt_sa_calc_gpu_addr(
1053 kfd->gtt_start_gpu_addr,
1054 found,
1055 kfd->gtt_sa_chunk_size);
1056 (*mem_obj)->cpu_ptr = kfd_gtt_sa_calc_cpu_addr(
1057 kfd->gtt_start_cpu_ptr,
1058 found,
1059 kfd->gtt_sa_chunk_size);
1060
1061 pr_debug("gpu_addr = %p, cpu_addr = %p\n",
1062 (uint64_t *) (*mem_obj)->gpu_addr, (*mem_obj)->cpu_ptr);
1063
1064 /* If we need only one chunk, mark it as allocated and get out */
1065 if (size <= kfd->gtt_sa_chunk_size) {
1066 pr_debug("Single bit\n");
1067 set_bit(found, kfd->gtt_sa_bitmap);
1068 goto kfd_gtt_out;
1069 }
1070
1071 /* Otherwise, try to see if we have enough contiguous chunks */
1072 cur_size = size - kfd->gtt_sa_chunk_size;
1073 do {
1074 (*mem_obj)->range_end =
1075 find_next_zero_bit(kfd->gtt_sa_bitmap,
1076 kfd->gtt_sa_num_of_chunks, ++found);
1077 /*
1078 * If next free chunk is not contiguous than we need to
1079 * restart our search from the last free chunk we found (which
1080 * wasn't contiguous to the previous ones
1081 */
1082 if ((*mem_obj)->range_end != found) {
1083 start_search = found;
1084 goto kfd_gtt_restart_search;
1085 }
1086
1087 /*
1088 * If we reached end of buffer, bail out with error
1089 */
1090 if (found == kfd->gtt_sa_num_of_chunks)
1091 goto kfd_gtt_no_free_chunk;
1092
1093 /* Check if we don't need another chunk */
1094 if (cur_size <= kfd->gtt_sa_chunk_size)
1095 cur_size = 0;
1096 else
1097 cur_size -= kfd->gtt_sa_chunk_size;
1098
1099 } while (cur_size > 0);
1100
1101 pr_debug("range_start = %d, range_end = %d\n",
1102 (*mem_obj)->range_start, (*mem_obj)->range_end);
1103
1104 /* Mark the chunks as allocated */
1105 for (found = (*mem_obj)->range_start;
1106 found <= (*mem_obj)->range_end;
1107 found++)
1108 set_bit(found, kfd->gtt_sa_bitmap);
1109
1110kfd_gtt_out:
1111 mutex_unlock(&kfd->gtt_sa_lock);
1112 return 0;
1113
1114kfd_gtt_no_free_chunk:
1115 pr_debug("Allocation failed with mem_obj = %p\n", mem_obj);
1116 mutex_unlock(&kfd->gtt_sa_lock);
1117 kfree(mem_obj);
1118 return -ENOMEM;
1119}
1120
1121int kfd_gtt_sa_free(struct kfd_dev *kfd, struct kfd_mem_obj *mem_obj)
1122{
1123 unsigned int bit;
1124
1125 /* Act like kfree when trying to free a NULL object */
1126 if (!mem_obj)
1127 return 0;
1128
1129 pr_debug("Free mem_obj = %p, range_start = %d, range_end = %d\n",
1130 mem_obj, mem_obj->range_start, mem_obj->range_end);
1131
1132 mutex_lock(&kfd->gtt_sa_lock);
1133
1134 /* Mark the chunks as free */
1135 for (bit = mem_obj->range_start;
1136 bit <= mem_obj->range_end;
1137 bit++)
1138 clear_bit(bit, kfd->gtt_sa_bitmap);
1139
1140 mutex_unlock(&kfd->gtt_sa_lock);
1141
1142 kfree(mem_obj);
1143 return 0;
1144}
1145
1146void kgd2kfd_set_sram_ecc_flag(struct kfd_dev *kfd)
1147{
1148 if (kfd)
1149 atomic_inc(&kfd->sram_ecc_flag);
1150}
1151
1152void kfd_inc_compute_active(struct kfd_dev *kfd)
1153{
1154 if (atomic_inc_return(&kfd->compute_profile) == 1)
1155 amdgpu_amdkfd_set_compute_idle(kfd->kgd, false);
1156}
1157
1158void kfd_dec_compute_active(struct kfd_dev *kfd)
1159{
1160 int count = atomic_dec_return(&kfd->compute_profile);
1161
1162 if (count == 0)
1163 amdgpu_amdkfd_set_compute_idle(kfd->kgd, true);
1164 WARN_ONCE(count < 0, "Compute profile ref. count error");
1165}
1166
1167#if defined(CONFIG_DEBUG_FS)
1168
1169/* This function will send a package to HIQ to hang the HWS
1170 * which will trigger a GPU reset and bring the HWS back to normal state
1171 */
1172int kfd_debugfs_hang_hws(struct kfd_dev *dev)
1173{
1174 int r = 0;
1175
1176 if (dev->dqm->sched_policy != KFD_SCHED_POLICY_HWS) {
1177 pr_err("HWS is not enabled");
1178 return -EINVAL;
1179 }
1180
1181 r = pm_debugfs_hang_hws(&dev->dqm->packets);
1182 if (!r)
1183 r = dqm_debugfs_execute_queues(dev->dqm);
1184
1185 return r;
1186}
1187
1188#endif