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1/*
2 * Copyright 2014 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22
23#include <linux/bsearch.h>
24#include <linux/pci.h>
25#include <linux/slab.h>
26#include "kfd_priv.h"
27#include "kfd_device_queue_manager.h"
28#include "kfd_pm4_headers_vi.h"
29#include "cwsr_trap_handler.h"
30#include "kfd_iommu.h"
31#include "amdgpu_amdkfd.h"
32
33#define MQD_SIZE_ALIGNED 768
34
35/*
36 * kfd_locked is used to lock the kfd driver during suspend or reset
37 * once locked, kfd driver will stop any further GPU execution.
38 * create process (open) will return -EAGAIN.
39 */
40static atomic_t kfd_locked = ATOMIC_INIT(0);
41
42#ifdef CONFIG_DRM_AMDGPU_CIK
43extern const struct kfd2kgd_calls gfx_v7_kfd2kgd;
44#endif
45extern const struct kfd2kgd_calls gfx_v8_kfd2kgd;
46extern const struct kfd2kgd_calls gfx_v9_kfd2kgd;
47extern const struct kfd2kgd_calls arcturus_kfd2kgd;
48extern const struct kfd2kgd_calls gfx_v10_kfd2kgd;
49extern const struct kfd2kgd_calls gfx_v10_3_kfd2kgd;
50
51static const struct kfd2kgd_calls *kfd2kgd_funcs[] = {
52#ifdef KFD_SUPPORT_IOMMU_V2
53#ifdef CONFIG_DRM_AMDGPU_CIK
54 [CHIP_KAVERI] = &gfx_v7_kfd2kgd,
55#endif
56 [CHIP_CARRIZO] = &gfx_v8_kfd2kgd,
57 [CHIP_RAVEN] = &gfx_v9_kfd2kgd,
58#endif
59#ifdef CONFIG_DRM_AMDGPU_CIK
60 [CHIP_HAWAII] = &gfx_v7_kfd2kgd,
61#endif
62 [CHIP_TONGA] = &gfx_v8_kfd2kgd,
63 [CHIP_FIJI] = &gfx_v8_kfd2kgd,
64 [CHIP_POLARIS10] = &gfx_v8_kfd2kgd,
65 [CHIP_POLARIS11] = &gfx_v8_kfd2kgd,
66 [CHIP_POLARIS12] = &gfx_v8_kfd2kgd,
67 [CHIP_VEGAM] = &gfx_v8_kfd2kgd,
68 [CHIP_VEGA10] = &gfx_v9_kfd2kgd,
69 [CHIP_VEGA12] = &gfx_v9_kfd2kgd,
70 [CHIP_VEGA20] = &gfx_v9_kfd2kgd,
71 [CHIP_RENOIR] = &gfx_v9_kfd2kgd,
72 [CHIP_ARCTURUS] = &arcturus_kfd2kgd,
73 [CHIP_NAVI10] = &gfx_v10_kfd2kgd,
74 [CHIP_NAVI12] = &gfx_v10_kfd2kgd,
75 [CHIP_NAVI14] = &gfx_v10_kfd2kgd,
76 [CHIP_SIENNA_CICHLID] = &gfx_v10_3_kfd2kgd,
77 [CHIP_NAVY_FLOUNDER] = &gfx_v10_3_kfd2kgd,
78};
79
80#ifdef KFD_SUPPORT_IOMMU_V2
81static const struct kfd_device_info kaveri_device_info = {
82 .asic_family = CHIP_KAVERI,
83 .asic_name = "kaveri",
84 .max_pasid_bits = 16,
85 /* max num of queues for KV.TODO should be a dynamic value */
86 .max_no_of_hqd = 24,
87 .doorbell_size = 4,
88 .ih_ring_entry_size = 4 * sizeof(uint32_t),
89 .event_interrupt_class = &event_interrupt_class_cik,
90 .num_of_watch_points = 4,
91 .mqd_size_aligned = MQD_SIZE_ALIGNED,
92 .supports_cwsr = false,
93 .needs_iommu_device = true,
94 .needs_pci_atomics = false,
95 .num_sdma_engines = 2,
96 .num_xgmi_sdma_engines = 0,
97 .num_sdma_queues_per_engine = 2,
98};
99
100static const struct kfd_device_info carrizo_device_info = {
101 .asic_family = CHIP_CARRIZO,
102 .asic_name = "carrizo",
103 .max_pasid_bits = 16,
104 /* max num of queues for CZ.TODO should be a dynamic value */
105 .max_no_of_hqd = 24,
106 .doorbell_size = 4,
107 .ih_ring_entry_size = 4 * sizeof(uint32_t),
108 .event_interrupt_class = &event_interrupt_class_cik,
109 .num_of_watch_points = 4,
110 .mqd_size_aligned = MQD_SIZE_ALIGNED,
111 .supports_cwsr = true,
112 .needs_iommu_device = true,
113 .needs_pci_atomics = false,
114 .num_sdma_engines = 2,
115 .num_xgmi_sdma_engines = 0,
116 .num_sdma_queues_per_engine = 2,
117};
118
119static const struct kfd_device_info raven_device_info = {
120 .asic_family = CHIP_RAVEN,
121 .asic_name = "raven",
122 .max_pasid_bits = 16,
123 .max_no_of_hqd = 24,
124 .doorbell_size = 8,
125 .ih_ring_entry_size = 8 * sizeof(uint32_t),
126 .event_interrupt_class = &event_interrupt_class_v9,
127 .num_of_watch_points = 4,
128 .mqd_size_aligned = MQD_SIZE_ALIGNED,
129 .supports_cwsr = true,
130 .needs_iommu_device = true,
131 .needs_pci_atomics = true,
132 .num_sdma_engines = 1,
133 .num_xgmi_sdma_engines = 0,
134 .num_sdma_queues_per_engine = 2,
135};
136#endif
137
138static const struct kfd_device_info hawaii_device_info = {
139 .asic_family = CHIP_HAWAII,
140 .asic_name = "hawaii",
141 .max_pasid_bits = 16,
142 /* max num of queues for KV.TODO should be a dynamic value */
143 .max_no_of_hqd = 24,
144 .doorbell_size = 4,
145 .ih_ring_entry_size = 4 * sizeof(uint32_t),
146 .event_interrupt_class = &event_interrupt_class_cik,
147 .num_of_watch_points = 4,
148 .mqd_size_aligned = MQD_SIZE_ALIGNED,
149 .supports_cwsr = false,
150 .needs_iommu_device = false,
151 .needs_pci_atomics = false,
152 .num_sdma_engines = 2,
153 .num_xgmi_sdma_engines = 0,
154 .num_sdma_queues_per_engine = 2,
155};
156
157static const struct kfd_device_info tonga_device_info = {
158 .asic_family = CHIP_TONGA,
159 .asic_name = "tonga",
160 .max_pasid_bits = 16,
161 .max_no_of_hqd = 24,
162 .doorbell_size = 4,
163 .ih_ring_entry_size = 4 * sizeof(uint32_t),
164 .event_interrupt_class = &event_interrupt_class_cik,
165 .num_of_watch_points = 4,
166 .mqd_size_aligned = MQD_SIZE_ALIGNED,
167 .supports_cwsr = false,
168 .needs_iommu_device = false,
169 .needs_pci_atomics = true,
170 .num_sdma_engines = 2,
171 .num_xgmi_sdma_engines = 0,
172 .num_sdma_queues_per_engine = 2,
173};
174
175static const struct kfd_device_info fiji_device_info = {
176 .asic_family = CHIP_FIJI,
177 .asic_name = "fiji",
178 .max_pasid_bits = 16,
179 .max_no_of_hqd = 24,
180 .doorbell_size = 4,
181 .ih_ring_entry_size = 4 * sizeof(uint32_t),
182 .event_interrupt_class = &event_interrupt_class_cik,
183 .num_of_watch_points = 4,
184 .mqd_size_aligned = MQD_SIZE_ALIGNED,
185 .supports_cwsr = true,
186 .needs_iommu_device = false,
187 .needs_pci_atomics = true,
188 .num_sdma_engines = 2,
189 .num_xgmi_sdma_engines = 0,
190 .num_sdma_queues_per_engine = 2,
191};
192
193static const struct kfd_device_info fiji_vf_device_info = {
194 .asic_family = CHIP_FIJI,
195 .asic_name = "fiji",
196 .max_pasid_bits = 16,
197 .max_no_of_hqd = 24,
198 .doorbell_size = 4,
199 .ih_ring_entry_size = 4 * sizeof(uint32_t),
200 .event_interrupt_class = &event_interrupt_class_cik,
201 .num_of_watch_points = 4,
202 .mqd_size_aligned = MQD_SIZE_ALIGNED,
203 .supports_cwsr = true,
204 .needs_iommu_device = false,
205 .needs_pci_atomics = false,
206 .num_sdma_engines = 2,
207 .num_xgmi_sdma_engines = 0,
208 .num_sdma_queues_per_engine = 2,
209};
210
211
212static const struct kfd_device_info polaris10_device_info = {
213 .asic_family = CHIP_POLARIS10,
214 .asic_name = "polaris10",
215 .max_pasid_bits = 16,
216 .max_no_of_hqd = 24,
217 .doorbell_size = 4,
218 .ih_ring_entry_size = 4 * sizeof(uint32_t),
219 .event_interrupt_class = &event_interrupt_class_cik,
220 .num_of_watch_points = 4,
221 .mqd_size_aligned = MQD_SIZE_ALIGNED,
222 .supports_cwsr = true,
223 .needs_iommu_device = false,
224 .needs_pci_atomics = true,
225 .num_sdma_engines = 2,
226 .num_xgmi_sdma_engines = 0,
227 .num_sdma_queues_per_engine = 2,
228};
229
230static const struct kfd_device_info polaris10_vf_device_info = {
231 .asic_family = CHIP_POLARIS10,
232 .asic_name = "polaris10",
233 .max_pasid_bits = 16,
234 .max_no_of_hqd = 24,
235 .doorbell_size = 4,
236 .ih_ring_entry_size = 4 * sizeof(uint32_t),
237 .event_interrupt_class = &event_interrupt_class_cik,
238 .num_of_watch_points = 4,
239 .mqd_size_aligned = MQD_SIZE_ALIGNED,
240 .supports_cwsr = true,
241 .needs_iommu_device = false,
242 .needs_pci_atomics = false,
243 .num_sdma_engines = 2,
244 .num_xgmi_sdma_engines = 0,
245 .num_sdma_queues_per_engine = 2,
246};
247
248static const struct kfd_device_info polaris11_device_info = {
249 .asic_family = CHIP_POLARIS11,
250 .asic_name = "polaris11",
251 .max_pasid_bits = 16,
252 .max_no_of_hqd = 24,
253 .doorbell_size = 4,
254 .ih_ring_entry_size = 4 * sizeof(uint32_t),
255 .event_interrupt_class = &event_interrupt_class_cik,
256 .num_of_watch_points = 4,
257 .mqd_size_aligned = MQD_SIZE_ALIGNED,
258 .supports_cwsr = true,
259 .needs_iommu_device = false,
260 .needs_pci_atomics = true,
261 .num_sdma_engines = 2,
262 .num_xgmi_sdma_engines = 0,
263 .num_sdma_queues_per_engine = 2,
264};
265
266static const struct kfd_device_info polaris12_device_info = {
267 .asic_family = CHIP_POLARIS12,
268 .asic_name = "polaris12",
269 .max_pasid_bits = 16,
270 .max_no_of_hqd = 24,
271 .doorbell_size = 4,
272 .ih_ring_entry_size = 4 * sizeof(uint32_t),
273 .event_interrupt_class = &event_interrupt_class_cik,
274 .num_of_watch_points = 4,
275 .mqd_size_aligned = MQD_SIZE_ALIGNED,
276 .supports_cwsr = true,
277 .needs_iommu_device = false,
278 .needs_pci_atomics = true,
279 .num_sdma_engines = 2,
280 .num_xgmi_sdma_engines = 0,
281 .num_sdma_queues_per_engine = 2,
282};
283
284static const struct kfd_device_info vegam_device_info = {
285 .asic_family = CHIP_VEGAM,
286 .asic_name = "vegam",
287 .max_pasid_bits = 16,
288 .max_no_of_hqd = 24,
289 .doorbell_size = 4,
290 .ih_ring_entry_size = 4 * sizeof(uint32_t),
291 .event_interrupt_class = &event_interrupt_class_cik,
292 .num_of_watch_points = 4,
293 .mqd_size_aligned = MQD_SIZE_ALIGNED,
294 .supports_cwsr = true,
295 .needs_iommu_device = false,
296 .needs_pci_atomics = true,
297 .num_sdma_engines = 2,
298 .num_xgmi_sdma_engines = 0,
299 .num_sdma_queues_per_engine = 2,
300};
301
302static const struct kfd_device_info vega10_device_info = {
303 .asic_family = CHIP_VEGA10,
304 .asic_name = "vega10",
305 .max_pasid_bits = 16,
306 .max_no_of_hqd = 24,
307 .doorbell_size = 8,
308 .ih_ring_entry_size = 8 * sizeof(uint32_t),
309 .event_interrupt_class = &event_interrupt_class_v9,
310 .num_of_watch_points = 4,
311 .mqd_size_aligned = MQD_SIZE_ALIGNED,
312 .supports_cwsr = true,
313 .needs_iommu_device = false,
314 .needs_pci_atomics = false,
315 .num_sdma_engines = 2,
316 .num_xgmi_sdma_engines = 0,
317 .num_sdma_queues_per_engine = 2,
318};
319
320static const struct kfd_device_info vega10_vf_device_info = {
321 .asic_family = CHIP_VEGA10,
322 .asic_name = "vega10",
323 .max_pasid_bits = 16,
324 .max_no_of_hqd = 24,
325 .doorbell_size = 8,
326 .ih_ring_entry_size = 8 * sizeof(uint32_t),
327 .event_interrupt_class = &event_interrupt_class_v9,
328 .num_of_watch_points = 4,
329 .mqd_size_aligned = MQD_SIZE_ALIGNED,
330 .supports_cwsr = true,
331 .needs_iommu_device = false,
332 .needs_pci_atomics = false,
333 .num_sdma_engines = 2,
334 .num_xgmi_sdma_engines = 0,
335 .num_sdma_queues_per_engine = 2,
336};
337
338static const struct kfd_device_info vega12_device_info = {
339 .asic_family = CHIP_VEGA12,
340 .asic_name = "vega12",
341 .max_pasid_bits = 16,
342 .max_no_of_hqd = 24,
343 .doorbell_size = 8,
344 .ih_ring_entry_size = 8 * sizeof(uint32_t),
345 .event_interrupt_class = &event_interrupt_class_v9,
346 .num_of_watch_points = 4,
347 .mqd_size_aligned = MQD_SIZE_ALIGNED,
348 .supports_cwsr = true,
349 .needs_iommu_device = false,
350 .needs_pci_atomics = false,
351 .num_sdma_engines = 2,
352 .num_xgmi_sdma_engines = 0,
353 .num_sdma_queues_per_engine = 2,
354};
355
356static const struct kfd_device_info vega20_device_info = {
357 .asic_family = CHIP_VEGA20,
358 .asic_name = "vega20",
359 .max_pasid_bits = 16,
360 .max_no_of_hqd = 24,
361 .doorbell_size = 8,
362 .ih_ring_entry_size = 8 * sizeof(uint32_t),
363 .event_interrupt_class = &event_interrupt_class_v9,
364 .num_of_watch_points = 4,
365 .mqd_size_aligned = MQD_SIZE_ALIGNED,
366 .supports_cwsr = true,
367 .needs_iommu_device = false,
368 .needs_pci_atomics = false,
369 .num_sdma_engines = 2,
370 .num_xgmi_sdma_engines = 0,
371 .num_sdma_queues_per_engine = 8,
372};
373
374static const struct kfd_device_info arcturus_device_info = {
375 .asic_family = CHIP_ARCTURUS,
376 .asic_name = "arcturus",
377 .max_pasid_bits = 16,
378 .max_no_of_hqd = 24,
379 .doorbell_size = 8,
380 .ih_ring_entry_size = 8 * sizeof(uint32_t),
381 .event_interrupt_class = &event_interrupt_class_v9,
382 .num_of_watch_points = 4,
383 .mqd_size_aligned = MQD_SIZE_ALIGNED,
384 .supports_cwsr = true,
385 .needs_iommu_device = false,
386 .needs_pci_atomics = false,
387 .num_sdma_engines = 2,
388 .num_xgmi_sdma_engines = 6,
389 .num_sdma_queues_per_engine = 8,
390};
391
392static const struct kfd_device_info renoir_device_info = {
393 .asic_family = CHIP_RENOIR,
394 .asic_name = "renoir",
395 .max_pasid_bits = 16,
396 .max_no_of_hqd = 24,
397 .doorbell_size = 8,
398 .ih_ring_entry_size = 8 * sizeof(uint32_t),
399 .event_interrupt_class = &event_interrupt_class_v9,
400 .num_of_watch_points = 4,
401 .mqd_size_aligned = MQD_SIZE_ALIGNED,
402 .supports_cwsr = true,
403 .needs_iommu_device = false,
404 .needs_pci_atomics = false,
405 .num_sdma_engines = 1,
406 .num_xgmi_sdma_engines = 0,
407 .num_sdma_queues_per_engine = 2,
408};
409
410static const struct kfd_device_info navi10_device_info = {
411 .asic_family = CHIP_NAVI10,
412 .asic_name = "navi10",
413 .max_pasid_bits = 16,
414 .max_no_of_hqd = 24,
415 .doorbell_size = 8,
416 .ih_ring_entry_size = 8 * sizeof(uint32_t),
417 .event_interrupt_class = &event_interrupt_class_v9,
418 .num_of_watch_points = 4,
419 .mqd_size_aligned = MQD_SIZE_ALIGNED,
420 .needs_iommu_device = false,
421 .supports_cwsr = true,
422 .needs_pci_atomics = false,
423 .num_sdma_engines = 2,
424 .num_xgmi_sdma_engines = 0,
425 .num_sdma_queues_per_engine = 8,
426};
427
428static const struct kfd_device_info navi12_device_info = {
429 .asic_family = CHIP_NAVI12,
430 .asic_name = "navi12",
431 .max_pasid_bits = 16,
432 .max_no_of_hqd = 24,
433 .doorbell_size = 8,
434 .ih_ring_entry_size = 8 * sizeof(uint32_t),
435 .event_interrupt_class = &event_interrupt_class_v9,
436 .num_of_watch_points = 4,
437 .mqd_size_aligned = MQD_SIZE_ALIGNED,
438 .needs_iommu_device = false,
439 .supports_cwsr = true,
440 .needs_pci_atomics = false,
441 .num_sdma_engines = 2,
442 .num_xgmi_sdma_engines = 0,
443 .num_sdma_queues_per_engine = 8,
444};
445
446static const struct kfd_device_info navi14_device_info = {
447 .asic_family = CHIP_NAVI14,
448 .asic_name = "navi14",
449 .max_pasid_bits = 16,
450 .max_no_of_hqd = 24,
451 .doorbell_size = 8,
452 .ih_ring_entry_size = 8 * sizeof(uint32_t),
453 .event_interrupt_class = &event_interrupt_class_v9,
454 .num_of_watch_points = 4,
455 .mqd_size_aligned = MQD_SIZE_ALIGNED,
456 .needs_iommu_device = false,
457 .supports_cwsr = true,
458 .needs_pci_atomics = false,
459 .num_sdma_engines = 2,
460 .num_xgmi_sdma_engines = 0,
461 .num_sdma_queues_per_engine = 8,
462};
463
464static const struct kfd_device_info sienna_cichlid_device_info = {
465 .asic_family = CHIP_SIENNA_CICHLID,
466 .asic_name = "sienna_cichlid",
467 .max_pasid_bits = 16,
468 .max_no_of_hqd = 24,
469 .doorbell_size = 8,
470 .ih_ring_entry_size = 8 * sizeof(uint32_t),
471 .event_interrupt_class = &event_interrupt_class_v9,
472 .num_of_watch_points = 4,
473 .mqd_size_aligned = MQD_SIZE_ALIGNED,
474 .needs_iommu_device = false,
475 .supports_cwsr = true,
476 .needs_pci_atomics = false,
477 .num_sdma_engines = 4,
478 .num_xgmi_sdma_engines = 0,
479 .num_sdma_queues_per_engine = 8,
480};
481
482static const struct kfd_device_info navy_flounder_device_info = {
483 .asic_family = CHIP_NAVY_FLOUNDER,
484 .asic_name = "navy_flounder",
485 .max_pasid_bits = 16,
486 .max_no_of_hqd = 24,
487 .doorbell_size = 8,
488 .ih_ring_entry_size = 8 * sizeof(uint32_t),
489 .event_interrupt_class = &event_interrupt_class_v9,
490 .num_of_watch_points = 4,
491 .mqd_size_aligned = MQD_SIZE_ALIGNED,
492 .needs_iommu_device = false,
493 .supports_cwsr = true,
494 .needs_pci_atomics = false,
495 .num_sdma_engines = 2,
496 .num_xgmi_sdma_engines = 0,
497 .num_sdma_queues_per_engine = 8,
498};
499
500/* For each entry, [0] is regular and [1] is virtualisation device. */
501static const struct kfd_device_info *kfd_supported_devices[][2] = {
502#ifdef KFD_SUPPORT_IOMMU_V2
503 [CHIP_KAVERI] = {&kaveri_device_info, NULL},
504 [CHIP_CARRIZO] = {&carrizo_device_info, NULL},
505 [CHIP_RAVEN] = {&raven_device_info, NULL},
506#endif
507 [CHIP_HAWAII] = {&hawaii_device_info, NULL},
508 [CHIP_TONGA] = {&tonga_device_info, NULL},
509 [CHIP_FIJI] = {&fiji_device_info, &fiji_vf_device_info},
510 [CHIP_POLARIS10] = {&polaris10_device_info, &polaris10_vf_device_info},
511 [CHIP_POLARIS11] = {&polaris11_device_info, NULL},
512 [CHIP_POLARIS12] = {&polaris12_device_info, NULL},
513 [CHIP_VEGAM] = {&vegam_device_info, NULL},
514 [CHIP_VEGA10] = {&vega10_device_info, &vega10_vf_device_info},
515 [CHIP_VEGA12] = {&vega12_device_info, NULL},
516 [CHIP_VEGA20] = {&vega20_device_info, NULL},
517 [CHIP_RENOIR] = {&renoir_device_info, NULL},
518 [CHIP_ARCTURUS] = {&arcturus_device_info, &arcturus_device_info},
519 [CHIP_NAVI10] = {&navi10_device_info, NULL},
520 [CHIP_NAVI12] = {&navi12_device_info, &navi12_device_info},
521 [CHIP_NAVI14] = {&navi14_device_info, NULL},
522 [CHIP_SIENNA_CICHLID] = {&sienna_cichlid_device_info, &sienna_cichlid_device_info},
523 [CHIP_NAVY_FLOUNDER] = {&navy_flounder_device_info, &navy_flounder_device_info},
524};
525
526static int kfd_gtt_sa_init(struct kfd_dev *kfd, unsigned int buf_size,
527 unsigned int chunk_size);
528static void kfd_gtt_sa_fini(struct kfd_dev *kfd);
529
530static int kfd_resume(struct kfd_dev *kfd);
531
532struct kfd_dev *kgd2kfd_probe(struct kgd_dev *kgd,
533 struct pci_dev *pdev, unsigned int asic_type, bool vf)
534{
535 struct kfd_dev *kfd;
536 const struct kfd_device_info *device_info;
537 const struct kfd2kgd_calls *f2g;
538
539 if (asic_type >= sizeof(kfd_supported_devices) / (sizeof(void *) * 2)
540 || asic_type >= sizeof(kfd2kgd_funcs) / sizeof(void *)) {
541 dev_err(kfd_device, "asic_type %d out of range\n", asic_type);
542 return NULL; /* asic_type out of range */
543 }
544
545 device_info = kfd_supported_devices[asic_type][vf];
546 f2g = kfd2kgd_funcs[asic_type];
547
548 if (!device_info || !f2g) {
549 dev_err(kfd_device, "%s %s not supported in kfd\n",
550 amdgpu_asic_name[asic_type], vf ? "VF" : "");
551 return NULL;
552 }
553
554 kfd = kzalloc(sizeof(*kfd), GFP_KERNEL);
555 if (!kfd)
556 return NULL;
557
558 /* Allow BIF to recode atomics to PCIe 3.0 AtomicOps.
559 * 32 and 64-bit requests are possible and must be
560 * supported.
561 */
562 kfd->pci_atomic_requested = amdgpu_amdkfd_have_atomics_support(kgd);
563 if (device_info->needs_pci_atomics &&
564 !kfd->pci_atomic_requested) {
565 dev_info(kfd_device,
566 "skipped device %x:%x, PCI rejects atomics\n",
567 pdev->vendor, pdev->device);
568 kfree(kfd);
569 return NULL;
570 }
571
572 kfd->kgd = kgd;
573 kfd->device_info = device_info;
574 kfd->pdev = pdev;
575 kfd->init_complete = false;
576 kfd->kfd2kgd = f2g;
577 atomic_set(&kfd->compute_profile, 0);
578
579 mutex_init(&kfd->doorbell_mutex);
580 memset(&kfd->doorbell_available_index, 0,
581 sizeof(kfd->doorbell_available_index));
582
583 atomic_set(&kfd->sram_ecc_flag, 0);
584
585 return kfd;
586}
587
588static void kfd_cwsr_init(struct kfd_dev *kfd)
589{
590 if (cwsr_enable && kfd->device_info->supports_cwsr) {
591 if (kfd->device_info->asic_family < CHIP_VEGA10) {
592 BUILD_BUG_ON(sizeof(cwsr_trap_gfx8_hex) > PAGE_SIZE);
593 kfd->cwsr_isa = cwsr_trap_gfx8_hex;
594 kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx8_hex);
595 } else if (kfd->device_info->asic_family == CHIP_ARCTURUS) {
596 BUILD_BUG_ON(sizeof(cwsr_trap_arcturus_hex) > PAGE_SIZE);
597 kfd->cwsr_isa = cwsr_trap_arcturus_hex;
598 kfd->cwsr_isa_size = sizeof(cwsr_trap_arcturus_hex);
599 } else if (kfd->device_info->asic_family < CHIP_NAVI10) {
600 BUILD_BUG_ON(sizeof(cwsr_trap_gfx9_hex) > PAGE_SIZE);
601 kfd->cwsr_isa = cwsr_trap_gfx9_hex;
602 kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx9_hex);
603 } else if (kfd->device_info->asic_family < CHIP_SIENNA_CICHLID) {
604 BUILD_BUG_ON(sizeof(cwsr_trap_nv1x_hex) > PAGE_SIZE);
605 kfd->cwsr_isa = cwsr_trap_nv1x_hex;
606 kfd->cwsr_isa_size = sizeof(cwsr_trap_nv1x_hex);
607 } else {
608 BUILD_BUG_ON(sizeof(cwsr_trap_gfx10_hex) > PAGE_SIZE);
609 kfd->cwsr_isa = cwsr_trap_gfx10_hex;
610 kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx10_hex);
611 }
612
613 kfd->cwsr_enabled = true;
614 }
615}
616
617static int kfd_gws_init(struct kfd_dev *kfd)
618{
619 int ret = 0;
620
621 if (kfd->dqm->sched_policy == KFD_SCHED_POLICY_NO_HWS)
622 return 0;
623
624 if (hws_gws_support
625 || (kfd->device_info->asic_family == CHIP_VEGA10
626 && kfd->mec2_fw_version >= 0x81b3)
627 || (kfd->device_info->asic_family >= CHIP_VEGA12
628 && kfd->device_info->asic_family <= CHIP_RAVEN
629 && kfd->mec2_fw_version >= 0x1b3)
630 || (kfd->device_info->asic_family == CHIP_ARCTURUS
631 && kfd->mec2_fw_version >= 0x30))
632 ret = amdgpu_amdkfd_alloc_gws(kfd->kgd,
633 amdgpu_amdkfd_get_num_gws(kfd->kgd), &kfd->gws);
634
635 return ret;
636}
637
638static void kfd_smi_init(struct kfd_dev *dev) {
639 INIT_LIST_HEAD(&dev->smi_clients);
640 spin_lock_init(&dev->smi_lock);
641}
642
643bool kgd2kfd_device_init(struct kfd_dev *kfd,
644 struct drm_device *ddev,
645 const struct kgd2kfd_shared_resources *gpu_resources)
646{
647 unsigned int size;
648
649 kfd->ddev = ddev;
650 kfd->mec_fw_version = amdgpu_amdkfd_get_fw_version(kfd->kgd,
651 KGD_ENGINE_MEC1);
652 kfd->mec2_fw_version = amdgpu_amdkfd_get_fw_version(kfd->kgd,
653 KGD_ENGINE_MEC2);
654 kfd->sdma_fw_version = amdgpu_amdkfd_get_fw_version(kfd->kgd,
655 KGD_ENGINE_SDMA1);
656 kfd->shared_resources = *gpu_resources;
657
658 kfd->vm_info.first_vmid_kfd = ffs(gpu_resources->compute_vmid_bitmap)-1;
659 kfd->vm_info.last_vmid_kfd = fls(gpu_resources->compute_vmid_bitmap)-1;
660 kfd->vm_info.vmid_num_kfd = kfd->vm_info.last_vmid_kfd
661 - kfd->vm_info.first_vmid_kfd + 1;
662
663 /* Verify module parameters regarding mapped process number*/
664 if ((hws_max_conc_proc < 0)
665 || (hws_max_conc_proc > kfd->vm_info.vmid_num_kfd)) {
666 dev_err(kfd_device,
667 "hws_max_conc_proc %d must be between 0 and %d, use %d instead\n",
668 hws_max_conc_proc, kfd->vm_info.vmid_num_kfd,
669 kfd->vm_info.vmid_num_kfd);
670 kfd->max_proc_per_quantum = kfd->vm_info.vmid_num_kfd;
671 } else
672 kfd->max_proc_per_quantum = hws_max_conc_proc;
673
674 /* calculate max size of mqds needed for queues */
675 size = max_num_of_queues_per_device *
676 kfd->device_info->mqd_size_aligned;
677
678 /*
679 * calculate max size of runlist packet.
680 * There can be only 2 packets at once
681 */
682 size += (KFD_MAX_NUM_OF_PROCESSES * sizeof(struct pm4_mes_map_process) +
683 max_num_of_queues_per_device * sizeof(struct pm4_mes_map_queues)
684 + sizeof(struct pm4_mes_runlist)) * 2;
685
686 /* Add size of HIQ & DIQ */
687 size += KFD_KERNEL_QUEUE_SIZE * 2;
688
689 /* add another 512KB for all other allocations on gart (HPD, fences) */
690 size += 512 * 1024;
691
692 if (amdgpu_amdkfd_alloc_gtt_mem(
693 kfd->kgd, size, &kfd->gtt_mem,
694 &kfd->gtt_start_gpu_addr, &kfd->gtt_start_cpu_ptr,
695 false)) {
696 dev_err(kfd_device, "Could not allocate %d bytes\n", size);
697 goto alloc_gtt_mem_failure;
698 }
699
700 dev_info(kfd_device, "Allocated %d bytes on gart\n", size);
701
702 /* Initialize GTT sa with 512 byte chunk size */
703 if (kfd_gtt_sa_init(kfd, size, 512) != 0) {
704 dev_err(kfd_device, "Error initializing gtt sub-allocator\n");
705 goto kfd_gtt_sa_init_error;
706 }
707
708 if (kfd_doorbell_init(kfd)) {
709 dev_err(kfd_device,
710 "Error initializing doorbell aperture\n");
711 goto kfd_doorbell_error;
712 }
713
714 if (kfd->kfd2kgd->get_hive_id)
715 kfd->hive_id = kfd->kfd2kgd->get_hive_id(kfd->kgd);
716
717 if (kfd->kfd2kgd->get_unique_id)
718 kfd->unique_id = kfd->kfd2kgd->get_unique_id(kfd->kgd);
719
720 if (kfd_interrupt_init(kfd)) {
721 dev_err(kfd_device, "Error initializing interrupts\n");
722 goto kfd_interrupt_error;
723 }
724
725 kfd->dqm = device_queue_manager_init(kfd);
726 if (!kfd->dqm) {
727 dev_err(kfd_device, "Error initializing queue manager\n");
728 goto device_queue_manager_error;
729 }
730
731 /* If supported on this device, allocate global GWS that is shared
732 * by all KFD processes
733 */
734 if (kfd_gws_init(kfd)) {
735 dev_err(kfd_device, "Could not allocate %d gws\n",
736 amdgpu_amdkfd_get_num_gws(kfd->kgd));
737 goto gws_error;
738 }
739
740 if (kfd_iommu_device_init(kfd)) {
741 dev_err(kfd_device, "Error initializing iommuv2\n");
742 goto device_iommu_error;
743 }
744
745 kfd_cwsr_init(kfd);
746
747 if (kfd_resume(kfd))
748 goto kfd_resume_error;
749
750 kfd->dbgmgr = NULL;
751
752 if (kfd_topology_add_device(kfd)) {
753 dev_err(kfd_device, "Error adding device to topology\n");
754 goto kfd_topology_add_device_error;
755 }
756
757 kfd_smi_init(kfd);
758
759 kfd->init_complete = true;
760 dev_info(kfd_device, "added device %x:%x\n", kfd->pdev->vendor,
761 kfd->pdev->device);
762
763 pr_debug("Starting kfd with the following scheduling policy %d\n",
764 kfd->dqm->sched_policy);
765
766 goto out;
767
768kfd_topology_add_device_error:
769kfd_resume_error:
770device_iommu_error:
771gws_error:
772 device_queue_manager_uninit(kfd->dqm);
773device_queue_manager_error:
774 kfd_interrupt_exit(kfd);
775kfd_interrupt_error:
776 kfd_doorbell_fini(kfd);
777kfd_doorbell_error:
778 kfd_gtt_sa_fini(kfd);
779kfd_gtt_sa_init_error:
780 amdgpu_amdkfd_free_gtt_mem(kfd->kgd, kfd->gtt_mem);
781alloc_gtt_mem_failure:
782 if (kfd->gws)
783 amdgpu_amdkfd_free_gws(kfd->kgd, kfd->gws);
784 dev_err(kfd_device,
785 "device %x:%x NOT added due to errors\n",
786 kfd->pdev->vendor, kfd->pdev->device);
787out:
788 return kfd->init_complete;
789}
790
791void kgd2kfd_device_exit(struct kfd_dev *kfd)
792{
793 if (kfd->init_complete) {
794 kgd2kfd_suspend(kfd, false);
795 device_queue_manager_uninit(kfd->dqm);
796 kfd_interrupt_exit(kfd);
797 kfd_topology_remove_device(kfd);
798 kfd_doorbell_fini(kfd);
799 kfd_gtt_sa_fini(kfd);
800 amdgpu_amdkfd_free_gtt_mem(kfd->kgd, kfd->gtt_mem);
801 if (kfd->gws)
802 amdgpu_amdkfd_free_gws(kfd->kgd, kfd->gws);
803 }
804
805 kfree(kfd);
806}
807
808int kgd2kfd_pre_reset(struct kfd_dev *kfd)
809{
810 if (!kfd->init_complete)
811 return 0;
812
813 kfd->dqm->ops.pre_reset(kfd->dqm);
814
815 kgd2kfd_suspend(kfd, false);
816
817 kfd_signal_reset_event(kfd);
818 return 0;
819}
820
821/*
822 * Fix me. KFD won't be able to resume existing process for now.
823 * We will keep all existing process in a evicted state and
824 * wait the process to be terminated.
825 */
826
827int kgd2kfd_post_reset(struct kfd_dev *kfd)
828{
829 int ret;
830
831 if (!kfd->init_complete)
832 return 0;
833
834 ret = kfd_resume(kfd);
835 if (ret)
836 return ret;
837 atomic_dec(&kfd_locked);
838
839 atomic_set(&kfd->sram_ecc_flag, 0);
840
841 return 0;
842}
843
844bool kfd_is_locked(void)
845{
846 return (atomic_read(&kfd_locked) > 0);
847}
848
849void kgd2kfd_suspend(struct kfd_dev *kfd, bool run_pm)
850{
851 if (!kfd->init_complete)
852 return;
853
854 /* for runtime suspend, skip locking kfd */
855 if (!run_pm) {
856 /* For first KFD device suspend all the KFD processes */
857 if (atomic_inc_return(&kfd_locked) == 1)
858 kfd_suspend_all_processes();
859 }
860
861 kfd->dqm->ops.stop(kfd->dqm);
862 kfd_iommu_suspend(kfd);
863}
864
865int kgd2kfd_resume(struct kfd_dev *kfd, bool run_pm)
866{
867 int ret, count;
868
869 if (!kfd->init_complete)
870 return 0;
871
872 ret = kfd_resume(kfd);
873 if (ret)
874 return ret;
875
876 /* for runtime resume, skip unlocking kfd */
877 if (!run_pm) {
878 count = atomic_dec_return(&kfd_locked);
879 WARN_ONCE(count < 0, "KFD suspend / resume ref. error");
880 if (count == 0)
881 ret = kfd_resume_all_processes();
882 }
883
884 return ret;
885}
886
887static int kfd_resume(struct kfd_dev *kfd)
888{
889 int err = 0;
890
891 err = kfd_iommu_resume(kfd);
892 if (err) {
893 dev_err(kfd_device,
894 "Failed to resume IOMMU for device %x:%x\n",
895 kfd->pdev->vendor, kfd->pdev->device);
896 return err;
897 }
898
899 err = kfd->dqm->ops.start(kfd->dqm);
900 if (err) {
901 dev_err(kfd_device,
902 "Error starting queue manager for device %x:%x\n",
903 kfd->pdev->vendor, kfd->pdev->device);
904 goto dqm_start_error;
905 }
906
907 return err;
908
909dqm_start_error:
910 kfd_iommu_suspend(kfd);
911 return err;
912}
913
914static inline void kfd_queue_work(struct workqueue_struct *wq,
915 struct work_struct *work)
916{
917 int cpu, new_cpu;
918
919 cpu = new_cpu = smp_processor_id();
920 do {
921 new_cpu = cpumask_next(new_cpu, cpu_online_mask) % nr_cpu_ids;
922 if (cpu_to_node(new_cpu) == numa_node_id())
923 break;
924 } while (cpu != new_cpu);
925
926 queue_work_on(new_cpu, wq, work);
927}
928
929/* This is called directly from KGD at ISR. */
930void kgd2kfd_interrupt(struct kfd_dev *kfd, const void *ih_ring_entry)
931{
932 uint32_t patched_ihre[KFD_MAX_RING_ENTRY_SIZE];
933 bool is_patched = false;
934 unsigned long flags;
935
936 if (!kfd->init_complete)
937 return;
938
939 if (kfd->device_info->ih_ring_entry_size > sizeof(patched_ihre)) {
940 dev_err_once(kfd_device, "Ring entry too small\n");
941 return;
942 }
943
944 spin_lock_irqsave(&kfd->interrupt_lock, flags);
945
946 if (kfd->interrupts_active
947 && interrupt_is_wanted(kfd, ih_ring_entry,
948 patched_ihre, &is_patched)
949 && enqueue_ih_ring_entry(kfd,
950 is_patched ? patched_ihre : ih_ring_entry))
951 kfd_queue_work(kfd->ih_wq, &kfd->interrupt_work);
952
953 spin_unlock_irqrestore(&kfd->interrupt_lock, flags);
954}
955
956int kgd2kfd_quiesce_mm(struct mm_struct *mm)
957{
958 struct kfd_process *p;
959 int r;
960
961 /* Because we are called from arbitrary context (workqueue) as opposed
962 * to process context, kfd_process could attempt to exit while we are
963 * running so the lookup function increments the process ref count.
964 */
965 p = kfd_lookup_process_by_mm(mm);
966 if (!p)
967 return -ESRCH;
968
969 WARN(debug_evictions, "Evicting pid %d", p->lead_thread->pid);
970 r = kfd_process_evict_queues(p);
971
972 kfd_unref_process(p);
973 return r;
974}
975
976int kgd2kfd_resume_mm(struct mm_struct *mm)
977{
978 struct kfd_process *p;
979 int r;
980
981 /* Because we are called from arbitrary context (workqueue) as opposed
982 * to process context, kfd_process could attempt to exit while we are
983 * running so the lookup function increments the process ref count.
984 */
985 p = kfd_lookup_process_by_mm(mm);
986 if (!p)
987 return -ESRCH;
988
989 r = kfd_process_restore_queues(p);
990
991 kfd_unref_process(p);
992 return r;
993}
994
995/** kgd2kfd_schedule_evict_and_restore_process - Schedules work queue that will
996 * prepare for safe eviction of KFD BOs that belong to the specified
997 * process.
998 *
999 * @mm: mm_struct that identifies the specified KFD process
1000 * @fence: eviction fence attached to KFD process BOs
1001 *
1002 */
1003int kgd2kfd_schedule_evict_and_restore_process(struct mm_struct *mm,
1004 struct dma_fence *fence)
1005{
1006 struct kfd_process *p;
1007 unsigned long active_time;
1008 unsigned long delay_jiffies = msecs_to_jiffies(PROCESS_ACTIVE_TIME_MS);
1009
1010 if (!fence)
1011 return -EINVAL;
1012
1013 if (dma_fence_is_signaled(fence))
1014 return 0;
1015
1016 p = kfd_lookup_process_by_mm(mm);
1017 if (!p)
1018 return -ENODEV;
1019
1020 if (fence->seqno == p->last_eviction_seqno)
1021 goto out;
1022
1023 p->last_eviction_seqno = fence->seqno;
1024
1025 /* Avoid KFD process starvation. Wait for at least
1026 * PROCESS_ACTIVE_TIME_MS before evicting the process again
1027 */
1028 active_time = get_jiffies_64() - p->last_restore_timestamp;
1029 if (delay_jiffies > active_time)
1030 delay_jiffies -= active_time;
1031 else
1032 delay_jiffies = 0;
1033
1034 /* During process initialization eviction_work.dwork is initialized
1035 * to kfd_evict_bo_worker
1036 */
1037 WARN(debug_evictions, "Scheduling eviction of pid %d in %ld jiffies",
1038 p->lead_thread->pid, delay_jiffies);
1039 schedule_delayed_work(&p->eviction_work, delay_jiffies);
1040out:
1041 kfd_unref_process(p);
1042 return 0;
1043}
1044
1045static int kfd_gtt_sa_init(struct kfd_dev *kfd, unsigned int buf_size,
1046 unsigned int chunk_size)
1047{
1048 unsigned int num_of_longs;
1049
1050 if (WARN_ON(buf_size < chunk_size))
1051 return -EINVAL;
1052 if (WARN_ON(buf_size == 0))
1053 return -EINVAL;
1054 if (WARN_ON(chunk_size == 0))
1055 return -EINVAL;
1056
1057 kfd->gtt_sa_chunk_size = chunk_size;
1058 kfd->gtt_sa_num_of_chunks = buf_size / chunk_size;
1059
1060 num_of_longs = (kfd->gtt_sa_num_of_chunks + BITS_PER_LONG - 1) /
1061 BITS_PER_LONG;
1062
1063 kfd->gtt_sa_bitmap = kcalloc(num_of_longs, sizeof(long), GFP_KERNEL);
1064
1065 if (!kfd->gtt_sa_bitmap)
1066 return -ENOMEM;
1067
1068 pr_debug("gtt_sa_num_of_chunks = %d, gtt_sa_bitmap = %p\n",
1069 kfd->gtt_sa_num_of_chunks, kfd->gtt_sa_bitmap);
1070
1071 mutex_init(&kfd->gtt_sa_lock);
1072
1073 return 0;
1074
1075}
1076
1077static void kfd_gtt_sa_fini(struct kfd_dev *kfd)
1078{
1079 mutex_destroy(&kfd->gtt_sa_lock);
1080 kfree(kfd->gtt_sa_bitmap);
1081}
1082
1083static inline uint64_t kfd_gtt_sa_calc_gpu_addr(uint64_t start_addr,
1084 unsigned int bit_num,
1085 unsigned int chunk_size)
1086{
1087 return start_addr + bit_num * chunk_size;
1088}
1089
1090static inline uint32_t *kfd_gtt_sa_calc_cpu_addr(void *start_addr,
1091 unsigned int bit_num,
1092 unsigned int chunk_size)
1093{
1094 return (uint32_t *) ((uint64_t) start_addr + bit_num * chunk_size);
1095}
1096
1097int kfd_gtt_sa_allocate(struct kfd_dev *kfd, unsigned int size,
1098 struct kfd_mem_obj **mem_obj)
1099{
1100 unsigned int found, start_search, cur_size;
1101
1102 if (size == 0)
1103 return -EINVAL;
1104
1105 if (size > kfd->gtt_sa_num_of_chunks * kfd->gtt_sa_chunk_size)
1106 return -ENOMEM;
1107
1108 *mem_obj = kzalloc(sizeof(struct kfd_mem_obj), GFP_KERNEL);
1109 if (!(*mem_obj))
1110 return -ENOMEM;
1111
1112 pr_debug("Allocated mem_obj = %p for size = %d\n", *mem_obj, size);
1113
1114 start_search = 0;
1115
1116 mutex_lock(&kfd->gtt_sa_lock);
1117
1118kfd_gtt_restart_search:
1119 /* Find the first chunk that is free */
1120 found = find_next_zero_bit(kfd->gtt_sa_bitmap,
1121 kfd->gtt_sa_num_of_chunks,
1122 start_search);
1123
1124 pr_debug("Found = %d\n", found);
1125
1126 /* If there wasn't any free chunk, bail out */
1127 if (found == kfd->gtt_sa_num_of_chunks)
1128 goto kfd_gtt_no_free_chunk;
1129
1130 /* Update fields of mem_obj */
1131 (*mem_obj)->range_start = found;
1132 (*mem_obj)->range_end = found;
1133 (*mem_obj)->gpu_addr = kfd_gtt_sa_calc_gpu_addr(
1134 kfd->gtt_start_gpu_addr,
1135 found,
1136 kfd->gtt_sa_chunk_size);
1137 (*mem_obj)->cpu_ptr = kfd_gtt_sa_calc_cpu_addr(
1138 kfd->gtt_start_cpu_ptr,
1139 found,
1140 kfd->gtt_sa_chunk_size);
1141
1142 pr_debug("gpu_addr = %p, cpu_addr = %p\n",
1143 (uint64_t *) (*mem_obj)->gpu_addr, (*mem_obj)->cpu_ptr);
1144
1145 /* If we need only one chunk, mark it as allocated and get out */
1146 if (size <= kfd->gtt_sa_chunk_size) {
1147 pr_debug("Single bit\n");
1148 set_bit(found, kfd->gtt_sa_bitmap);
1149 goto kfd_gtt_out;
1150 }
1151
1152 /* Otherwise, try to see if we have enough contiguous chunks */
1153 cur_size = size - kfd->gtt_sa_chunk_size;
1154 do {
1155 (*mem_obj)->range_end =
1156 find_next_zero_bit(kfd->gtt_sa_bitmap,
1157 kfd->gtt_sa_num_of_chunks, ++found);
1158 /*
1159 * If next free chunk is not contiguous than we need to
1160 * restart our search from the last free chunk we found (which
1161 * wasn't contiguous to the previous ones
1162 */
1163 if ((*mem_obj)->range_end != found) {
1164 start_search = found;
1165 goto kfd_gtt_restart_search;
1166 }
1167
1168 /*
1169 * If we reached end of buffer, bail out with error
1170 */
1171 if (found == kfd->gtt_sa_num_of_chunks)
1172 goto kfd_gtt_no_free_chunk;
1173
1174 /* Check if we don't need another chunk */
1175 if (cur_size <= kfd->gtt_sa_chunk_size)
1176 cur_size = 0;
1177 else
1178 cur_size -= kfd->gtt_sa_chunk_size;
1179
1180 } while (cur_size > 0);
1181
1182 pr_debug("range_start = %d, range_end = %d\n",
1183 (*mem_obj)->range_start, (*mem_obj)->range_end);
1184
1185 /* Mark the chunks as allocated */
1186 for (found = (*mem_obj)->range_start;
1187 found <= (*mem_obj)->range_end;
1188 found++)
1189 set_bit(found, kfd->gtt_sa_bitmap);
1190
1191kfd_gtt_out:
1192 mutex_unlock(&kfd->gtt_sa_lock);
1193 return 0;
1194
1195kfd_gtt_no_free_chunk:
1196 pr_debug("Allocation failed with mem_obj = %p\n", *mem_obj);
1197 mutex_unlock(&kfd->gtt_sa_lock);
1198 kfree(*mem_obj);
1199 return -ENOMEM;
1200}
1201
1202int kfd_gtt_sa_free(struct kfd_dev *kfd, struct kfd_mem_obj *mem_obj)
1203{
1204 unsigned int bit;
1205
1206 /* Act like kfree when trying to free a NULL object */
1207 if (!mem_obj)
1208 return 0;
1209
1210 pr_debug("Free mem_obj = %p, range_start = %d, range_end = %d\n",
1211 mem_obj, mem_obj->range_start, mem_obj->range_end);
1212
1213 mutex_lock(&kfd->gtt_sa_lock);
1214
1215 /* Mark the chunks as free */
1216 for (bit = mem_obj->range_start;
1217 bit <= mem_obj->range_end;
1218 bit++)
1219 clear_bit(bit, kfd->gtt_sa_bitmap);
1220
1221 mutex_unlock(&kfd->gtt_sa_lock);
1222
1223 kfree(mem_obj);
1224 return 0;
1225}
1226
1227void kgd2kfd_set_sram_ecc_flag(struct kfd_dev *kfd)
1228{
1229 if (kfd)
1230 atomic_inc(&kfd->sram_ecc_flag);
1231}
1232
1233void kfd_inc_compute_active(struct kfd_dev *kfd)
1234{
1235 if (atomic_inc_return(&kfd->compute_profile) == 1)
1236 amdgpu_amdkfd_set_compute_idle(kfd->kgd, false);
1237}
1238
1239void kfd_dec_compute_active(struct kfd_dev *kfd)
1240{
1241 int count = atomic_dec_return(&kfd->compute_profile);
1242
1243 if (count == 0)
1244 amdgpu_amdkfd_set_compute_idle(kfd->kgd, true);
1245 WARN_ONCE(count < 0, "Compute profile ref. count error");
1246}
1247
1248#if defined(CONFIG_DEBUG_FS)
1249
1250/* This function will send a package to HIQ to hang the HWS
1251 * which will trigger a GPU reset and bring the HWS back to normal state
1252 */
1253int kfd_debugfs_hang_hws(struct kfd_dev *dev)
1254{
1255 int r = 0;
1256
1257 if (dev->dqm->sched_policy != KFD_SCHED_POLICY_HWS) {
1258 pr_err("HWS is not enabled");
1259 return -EINVAL;
1260 }
1261
1262 r = pm_debugfs_hang_hws(&dev->dqm->packets);
1263 if (!r)
1264 r = dqm_debugfs_execute_queues(dev->dqm);
1265
1266 return r;
1267}
1268
1269#endif
1// SPDX-License-Identifier: GPL-2.0 OR MIT
2/*
3 * Copyright 2014-2022 Advanced Micro Devices, Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 */
23
24#include <linux/bsearch.h>
25#include <linux/pci.h>
26#include <linux/slab.h>
27#include "kfd_priv.h"
28#include "kfd_device_queue_manager.h"
29#include "kfd_pm4_headers_vi.h"
30#include "kfd_pm4_headers_aldebaran.h"
31#include "cwsr_trap_handler.h"
32#include "amdgpu_amdkfd.h"
33#include "kfd_smi_events.h"
34#include "kfd_svm.h"
35#include "kfd_migrate.h"
36#include "amdgpu.h"
37#include "amdgpu_xcp.h"
38
39#define MQD_SIZE_ALIGNED 768
40
41/*
42 * kfd_locked is used to lock the kfd driver during suspend or reset
43 * once locked, kfd driver will stop any further GPU execution.
44 * create process (open) will return -EAGAIN.
45 */
46static int kfd_locked;
47
48#ifdef CONFIG_DRM_AMDGPU_CIK
49extern const struct kfd2kgd_calls gfx_v7_kfd2kgd;
50#endif
51extern const struct kfd2kgd_calls gfx_v8_kfd2kgd;
52extern const struct kfd2kgd_calls gfx_v9_kfd2kgd;
53extern const struct kfd2kgd_calls arcturus_kfd2kgd;
54extern const struct kfd2kgd_calls aldebaran_kfd2kgd;
55extern const struct kfd2kgd_calls gc_9_4_3_kfd2kgd;
56extern const struct kfd2kgd_calls gfx_v10_kfd2kgd;
57extern const struct kfd2kgd_calls gfx_v10_3_kfd2kgd;
58extern const struct kfd2kgd_calls gfx_v11_kfd2kgd;
59
60static int kfd_gtt_sa_init(struct kfd_dev *kfd, unsigned int buf_size,
61 unsigned int chunk_size);
62static void kfd_gtt_sa_fini(struct kfd_dev *kfd);
63
64static int kfd_resume(struct kfd_node *kfd);
65
66static void kfd_device_info_set_sdma_info(struct kfd_dev *kfd)
67{
68 uint32_t sdma_version = amdgpu_ip_version(kfd->adev, SDMA0_HWIP, 0);
69
70 switch (sdma_version) {
71 case IP_VERSION(4, 0, 0):/* VEGA10 */
72 case IP_VERSION(4, 0, 1):/* VEGA12 */
73 case IP_VERSION(4, 1, 0):/* RAVEN */
74 case IP_VERSION(4, 1, 1):/* RAVEN */
75 case IP_VERSION(4, 1, 2):/* RENOIR */
76 case IP_VERSION(5, 2, 1):/* VANGOGH */
77 case IP_VERSION(5, 2, 3):/* YELLOW_CARP */
78 case IP_VERSION(5, 2, 6):/* GC 10.3.6 */
79 case IP_VERSION(5, 2, 7):/* GC 10.3.7 */
80 kfd->device_info.num_sdma_queues_per_engine = 2;
81 break;
82 case IP_VERSION(4, 2, 0):/* VEGA20 */
83 case IP_VERSION(4, 2, 2):/* ARCTURUS */
84 case IP_VERSION(4, 4, 0):/* ALDEBARAN */
85 case IP_VERSION(4, 4, 2):
86 case IP_VERSION(5, 0, 0):/* NAVI10 */
87 case IP_VERSION(5, 0, 1):/* CYAN_SKILLFISH */
88 case IP_VERSION(5, 0, 2):/* NAVI14 */
89 case IP_VERSION(5, 0, 5):/* NAVI12 */
90 case IP_VERSION(5, 2, 0):/* SIENNA_CICHLID */
91 case IP_VERSION(5, 2, 2):/* NAVY_FLOUNDER */
92 case IP_VERSION(5, 2, 4):/* DIMGREY_CAVEFISH */
93 case IP_VERSION(5, 2, 5):/* BEIGE_GOBY */
94 case IP_VERSION(6, 0, 0):
95 case IP_VERSION(6, 0, 1):
96 case IP_VERSION(6, 0, 2):
97 case IP_VERSION(6, 0, 3):
98 case IP_VERSION(6, 1, 0):
99 kfd->device_info.num_sdma_queues_per_engine = 8;
100 break;
101 default:
102 dev_warn(kfd_device,
103 "Default sdma queue per engine(8) is set due to mismatch of sdma ip block(SDMA_HWIP:0x%x).\n",
104 sdma_version);
105 kfd->device_info.num_sdma_queues_per_engine = 8;
106 }
107
108 bitmap_zero(kfd->device_info.reserved_sdma_queues_bitmap, KFD_MAX_SDMA_QUEUES);
109
110 switch (sdma_version) {
111 case IP_VERSION(6, 0, 0):
112 case IP_VERSION(6, 0, 1):
113 case IP_VERSION(6, 0, 2):
114 case IP_VERSION(6, 0, 3):
115 case IP_VERSION(6, 1, 0):
116 /* Reserve 1 for paging and 1 for gfx */
117 kfd->device_info.num_reserved_sdma_queues_per_engine = 2;
118 /* BIT(0)=engine-0 queue-0; BIT(1)=engine-1 queue-0; BIT(2)=engine-0 queue-1; ... */
119 bitmap_set(kfd->device_info.reserved_sdma_queues_bitmap, 0,
120 kfd->adev->sdma.num_instances *
121 kfd->device_info.num_reserved_sdma_queues_per_engine);
122 break;
123 default:
124 break;
125 }
126}
127
128static void kfd_device_info_set_event_interrupt_class(struct kfd_dev *kfd)
129{
130 uint32_t gc_version = KFD_GC_VERSION(kfd);
131
132 switch (gc_version) {
133 case IP_VERSION(9, 0, 1): /* VEGA10 */
134 case IP_VERSION(9, 1, 0): /* RAVEN */
135 case IP_VERSION(9, 2, 1): /* VEGA12 */
136 case IP_VERSION(9, 2, 2): /* RAVEN */
137 case IP_VERSION(9, 3, 0): /* RENOIR */
138 case IP_VERSION(9, 4, 0): /* VEGA20 */
139 case IP_VERSION(9, 4, 1): /* ARCTURUS */
140 case IP_VERSION(9, 4, 2): /* ALDEBARAN */
141 kfd->device_info.event_interrupt_class = &event_interrupt_class_v9;
142 break;
143 case IP_VERSION(9, 4, 3): /* GC 9.4.3 */
144 kfd->device_info.event_interrupt_class =
145 &event_interrupt_class_v9_4_3;
146 break;
147 case IP_VERSION(10, 3, 1): /* VANGOGH */
148 case IP_VERSION(10, 3, 3): /* YELLOW_CARP */
149 case IP_VERSION(10, 3, 6): /* GC 10.3.6 */
150 case IP_VERSION(10, 3, 7): /* GC 10.3.7 */
151 case IP_VERSION(10, 1, 3): /* CYAN_SKILLFISH */
152 case IP_VERSION(10, 1, 4):
153 case IP_VERSION(10, 1, 10): /* NAVI10 */
154 case IP_VERSION(10, 1, 2): /* NAVI12 */
155 case IP_VERSION(10, 1, 1): /* NAVI14 */
156 case IP_VERSION(10, 3, 0): /* SIENNA_CICHLID */
157 case IP_VERSION(10, 3, 2): /* NAVY_FLOUNDER */
158 case IP_VERSION(10, 3, 4): /* DIMGREY_CAVEFISH */
159 case IP_VERSION(10, 3, 5): /* BEIGE_GOBY */
160 kfd->device_info.event_interrupt_class = &event_interrupt_class_v10;
161 break;
162 case IP_VERSION(11, 0, 0):
163 case IP_VERSION(11, 0, 1):
164 case IP_VERSION(11, 0, 2):
165 case IP_VERSION(11, 0, 3):
166 case IP_VERSION(11, 0, 4):
167 case IP_VERSION(11, 5, 0):
168 kfd->device_info.event_interrupt_class = &event_interrupt_class_v11;
169 break;
170 default:
171 dev_warn(kfd_device, "v9 event interrupt handler is set due to "
172 "mismatch of gc ip block(GC_HWIP:0x%x).\n", gc_version);
173 kfd->device_info.event_interrupt_class = &event_interrupt_class_v9;
174 }
175}
176
177static void kfd_device_info_init(struct kfd_dev *kfd,
178 bool vf, uint32_t gfx_target_version)
179{
180 uint32_t gc_version = KFD_GC_VERSION(kfd);
181 uint32_t asic_type = kfd->adev->asic_type;
182
183 kfd->device_info.max_pasid_bits = 16;
184 kfd->device_info.max_no_of_hqd = 24;
185 kfd->device_info.num_of_watch_points = 4;
186 kfd->device_info.mqd_size_aligned = MQD_SIZE_ALIGNED;
187 kfd->device_info.gfx_target_version = gfx_target_version;
188
189 if (KFD_IS_SOC15(kfd)) {
190 kfd->device_info.doorbell_size = 8;
191 kfd->device_info.ih_ring_entry_size = 8 * sizeof(uint32_t);
192 kfd->device_info.supports_cwsr = true;
193
194 kfd_device_info_set_sdma_info(kfd);
195
196 kfd_device_info_set_event_interrupt_class(kfd);
197
198 if (gc_version < IP_VERSION(11, 0, 0)) {
199 /* Navi2x+, Navi1x+ */
200 if (gc_version == IP_VERSION(10, 3, 6))
201 kfd->device_info.no_atomic_fw_version = 14;
202 else if (gc_version == IP_VERSION(10, 3, 7))
203 kfd->device_info.no_atomic_fw_version = 3;
204 else if (gc_version >= IP_VERSION(10, 3, 0))
205 kfd->device_info.no_atomic_fw_version = 92;
206 else if (gc_version >= IP_VERSION(10, 1, 1))
207 kfd->device_info.no_atomic_fw_version = 145;
208
209 /* Navi1x+ */
210 if (gc_version >= IP_VERSION(10, 1, 1))
211 kfd->device_info.needs_pci_atomics = true;
212 } else if (gc_version < IP_VERSION(12, 0, 0)) {
213 /*
214 * PCIe atomics support acknowledgment in GFX11 RS64 CPFW requires
215 * MEC version >= 509. Prior RS64 CPFW versions (and all F32) require
216 * PCIe atomics support.
217 */
218 kfd->device_info.needs_pci_atomics = true;
219 kfd->device_info.no_atomic_fw_version = kfd->adev->gfx.rs64_enable ? 509 : 0;
220 }
221 } else {
222 kfd->device_info.doorbell_size = 4;
223 kfd->device_info.ih_ring_entry_size = 4 * sizeof(uint32_t);
224 kfd->device_info.event_interrupt_class = &event_interrupt_class_cik;
225 kfd->device_info.num_sdma_queues_per_engine = 2;
226
227 if (asic_type != CHIP_KAVERI &&
228 asic_type != CHIP_HAWAII &&
229 asic_type != CHIP_TONGA)
230 kfd->device_info.supports_cwsr = true;
231
232 if (asic_type != CHIP_HAWAII && !vf)
233 kfd->device_info.needs_pci_atomics = true;
234 }
235}
236
237struct kfd_dev *kgd2kfd_probe(struct amdgpu_device *adev, bool vf)
238{
239 struct kfd_dev *kfd = NULL;
240 const struct kfd2kgd_calls *f2g = NULL;
241 uint32_t gfx_target_version = 0;
242
243 switch (adev->asic_type) {
244#ifdef CONFIG_DRM_AMDGPU_CIK
245 case CHIP_KAVERI:
246 gfx_target_version = 70000;
247 if (!vf)
248 f2g = &gfx_v7_kfd2kgd;
249 break;
250#endif
251 case CHIP_CARRIZO:
252 gfx_target_version = 80001;
253 if (!vf)
254 f2g = &gfx_v8_kfd2kgd;
255 break;
256#ifdef CONFIG_DRM_AMDGPU_CIK
257 case CHIP_HAWAII:
258 gfx_target_version = 70001;
259 if (!amdgpu_exp_hw_support)
260 pr_info(
261 "KFD support on Hawaii is experimental. See modparam exp_hw_support\n"
262 );
263 else if (!vf)
264 f2g = &gfx_v7_kfd2kgd;
265 break;
266#endif
267 case CHIP_TONGA:
268 gfx_target_version = 80002;
269 if (!vf)
270 f2g = &gfx_v8_kfd2kgd;
271 break;
272 case CHIP_FIJI:
273 case CHIP_POLARIS10:
274 gfx_target_version = 80003;
275 f2g = &gfx_v8_kfd2kgd;
276 break;
277 case CHIP_POLARIS11:
278 case CHIP_POLARIS12:
279 case CHIP_VEGAM:
280 gfx_target_version = 80003;
281 if (!vf)
282 f2g = &gfx_v8_kfd2kgd;
283 break;
284 default:
285 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
286 /* Vega 10 */
287 case IP_VERSION(9, 0, 1):
288 gfx_target_version = 90000;
289 f2g = &gfx_v9_kfd2kgd;
290 break;
291 /* Raven */
292 case IP_VERSION(9, 1, 0):
293 case IP_VERSION(9, 2, 2):
294 gfx_target_version = 90002;
295 if (!vf)
296 f2g = &gfx_v9_kfd2kgd;
297 break;
298 /* Vega12 */
299 case IP_VERSION(9, 2, 1):
300 gfx_target_version = 90004;
301 if (!vf)
302 f2g = &gfx_v9_kfd2kgd;
303 break;
304 /* Renoir */
305 case IP_VERSION(9, 3, 0):
306 gfx_target_version = 90012;
307 if (!vf)
308 f2g = &gfx_v9_kfd2kgd;
309 break;
310 /* Vega20 */
311 case IP_VERSION(9, 4, 0):
312 gfx_target_version = 90006;
313 if (!vf)
314 f2g = &gfx_v9_kfd2kgd;
315 break;
316 /* Arcturus */
317 case IP_VERSION(9, 4, 1):
318 gfx_target_version = 90008;
319 f2g = &arcturus_kfd2kgd;
320 break;
321 /* Aldebaran */
322 case IP_VERSION(9, 4, 2):
323 gfx_target_version = 90010;
324 f2g = &aldebaran_kfd2kgd;
325 break;
326 case IP_VERSION(9, 4, 3):
327 gfx_target_version = adev->rev_id >= 1 ? 90402
328 : adev->flags & AMD_IS_APU ? 90400
329 : 90401;
330 f2g = &gc_9_4_3_kfd2kgd;
331 break;
332 /* Navi10 */
333 case IP_VERSION(10, 1, 10):
334 gfx_target_version = 100100;
335 if (!vf)
336 f2g = &gfx_v10_kfd2kgd;
337 break;
338 /* Navi12 */
339 case IP_VERSION(10, 1, 2):
340 gfx_target_version = 100101;
341 f2g = &gfx_v10_kfd2kgd;
342 break;
343 /* Navi14 */
344 case IP_VERSION(10, 1, 1):
345 gfx_target_version = 100102;
346 if (!vf)
347 f2g = &gfx_v10_kfd2kgd;
348 break;
349 /* Cyan Skillfish */
350 case IP_VERSION(10, 1, 3):
351 case IP_VERSION(10, 1, 4):
352 gfx_target_version = 100103;
353 if (!vf)
354 f2g = &gfx_v10_kfd2kgd;
355 break;
356 /* Sienna Cichlid */
357 case IP_VERSION(10, 3, 0):
358 gfx_target_version = 100300;
359 f2g = &gfx_v10_3_kfd2kgd;
360 break;
361 /* Navy Flounder */
362 case IP_VERSION(10, 3, 2):
363 gfx_target_version = 100301;
364 f2g = &gfx_v10_3_kfd2kgd;
365 break;
366 /* Van Gogh */
367 case IP_VERSION(10, 3, 1):
368 gfx_target_version = 100303;
369 if (!vf)
370 f2g = &gfx_v10_3_kfd2kgd;
371 break;
372 /* Dimgrey Cavefish */
373 case IP_VERSION(10, 3, 4):
374 gfx_target_version = 100302;
375 f2g = &gfx_v10_3_kfd2kgd;
376 break;
377 /* Beige Goby */
378 case IP_VERSION(10, 3, 5):
379 gfx_target_version = 100304;
380 f2g = &gfx_v10_3_kfd2kgd;
381 break;
382 /* Yellow Carp */
383 case IP_VERSION(10, 3, 3):
384 gfx_target_version = 100305;
385 if (!vf)
386 f2g = &gfx_v10_3_kfd2kgd;
387 break;
388 case IP_VERSION(10, 3, 6):
389 case IP_VERSION(10, 3, 7):
390 gfx_target_version = 100306;
391 if (!vf)
392 f2g = &gfx_v10_3_kfd2kgd;
393 break;
394 case IP_VERSION(11, 0, 0):
395 gfx_target_version = 110000;
396 f2g = &gfx_v11_kfd2kgd;
397 break;
398 case IP_VERSION(11, 0, 1):
399 case IP_VERSION(11, 0, 4):
400 gfx_target_version = 110003;
401 f2g = &gfx_v11_kfd2kgd;
402 break;
403 case IP_VERSION(11, 0, 2):
404 gfx_target_version = 110002;
405 f2g = &gfx_v11_kfd2kgd;
406 break;
407 case IP_VERSION(11, 0, 3):
408 if ((adev->pdev->device == 0x7460 &&
409 adev->pdev->revision == 0x00) ||
410 (adev->pdev->device == 0x7461 &&
411 adev->pdev->revision == 0x00))
412 /* Note: Compiler version is 11.0.5 while HW version is 11.0.3 */
413 gfx_target_version = 110005;
414 else
415 /* Note: Compiler version is 11.0.1 while HW version is 11.0.3 */
416 gfx_target_version = 110001;
417 f2g = &gfx_v11_kfd2kgd;
418 break;
419 case IP_VERSION(11, 5, 0):
420 gfx_target_version = 110500;
421 f2g = &gfx_v11_kfd2kgd;
422 break;
423 default:
424 break;
425 }
426 break;
427 }
428
429 if (!f2g) {
430 if (amdgpu_ip_version(adev, GC_HWIP, 0))
431 dev_err(kfd_device,
432 "GC IP %06x %s not supported in kfd\n",
433 amdgpu_ip_version(adev, GC_HWIP, 0),
434 vf ? "VF" : "");
435 else
436 dev_err(kfd_device, "%s %s not supported in kfd\n",
437 amdgpu_asic_name[adev->asic_type], vf ? "VF" : "");
438 return NULL;
439 }
440
441 kfd = kzalloc(sizeof(*kfd), GFP_KERNEL);
442 if (!kfd)
443 return NULL;
444
445 kfd->adev = adev;
446 kfd_device_info_init(kfd, vf, gfx_target_version);
447 kfd->init_complete = false;
448 kfd->kfd2kgd = f2g;
449 atomic_set(&kfd->compute_profile, 0);
450
451 mutex_init(&kfd->doorbell_mutex);
452
453 ida_init(&kfd->doorbell_ida);
454
455 return kfd;
456}
457
458static void kfd_cwsr_init(struct kfd_dev *kfd)
459{
460 if (cwsr_enable && kfd->device_info.supports_cwsr) {
461 if (KFD_GC_VERSION(kfd) < IP_VERSION(9, 0, 1)) {
462 BUILD_BUG_ON(sizeof(cwsr_trap_gfx8_hex) > PAGE_SIZE);
463 kfd->cwsr_isa = cwsr_trap_gfx8_hex;
464 kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx8_hex);
465 } else if (KFD_GC_VERSION(kfd) == IP_VERSION(9, 4, 1)) {
466 BUILD_BUG_ON(sizeof(cwsr_trap_arcturus_hex) > PAGE_SIZE);
467 kfd->cwsr_isa = cwsr_trap_arcturus_hex;
468 kfd->cwsr_isa_size = sizeof(cwsr_trap_arcturus_hex);
469 } else if (KFD_GC_VERSION(kfd) == IP_VERSION(9, 4, 2)) {
470 BUILD_BUG_ON(sizeof(cwsr_trap_aldebaran_hex) > PAGE_SIZE);
471 kfd->cwsr_isa = cwsr_trap_aldebaran_hex;
472 kfd->cwsr_isa_size = sizeof(cwsr_trap_aldebaran_hex);
473 } else if (KFD_GC_VERSION(kfd) == IP_VERSION(9, 4, 3)) {
474 BUILD_BUG_ON(sizeof(cwsr_trap_gfx9_4_3_hex) > PAGE_SIZE);
475 kfd->cwsr_isa = cwsr_trap_gfx9_4_3_hex;
476 kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx9_4_3_hex);
477 } else if (KFD_GC_VERSION(kfd) < IP_VERSION(10, 1, 1)) {
478 BUILD_BUG_ON(sizeof(cwsr_trap_gfx9_hex) > PAGE_SIZE);
479 kfd->cwsr_isa = cwsr_trap_gfx9_hex;
480 kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx9_hex);
481 } else if (KFD_GC_VERSION(kfd) < IP_VERSION(10, 3, 0)) {
482 BUILD_BUG_ON(sizeof(cwsr_trap_nv1x_hex) > PAGE_SIZE);
483 kfd->cwsr_isa = cwsr_trap_nv1x_hex;
484 kfd->cwsr_isa_size = sizeof(cwsr_trap_nv1x_hex);
485 } else if (KFD_GC_VERSION(kfd) < IP_VERSION(11, 0, 0)) {
486 BUILD_BUG_ON(sizeof(cwsr_trap_gfx10_hex) > PAGE_SIZE);
487 kfd->cwsr_isa = cwsr_trap_gfx10_hex;
488 kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx10_hex);
489 } else {
490 BUILD_BUG_ON(sizeof(cwsr_trap_gfx11_hex) > PAGE_SIZE);
491 kfd->cwsr_isa = cwsr_trap_gfx11_hex;
492 kfd->cwsr_isa_size = sizeof(cwsr_trap_gfx11_hex);
493 }
494
495 kfd->cwsr_enabled = true;
496 }
497}
498
499static int kfd_gws_init(struct kfd_node *node)
500{
501 int ret = 0;
502 struct kfd_dev *kfd = node->kfd;
503 uint32_t mes_rev = node->adev->mes.sched_version & AMDGPU_MES_VERSION_MASK;
504
505 if (node->dqm->sched_policy == KFD_SCHED_POLICY_NO_HWS)
506 return 0;
507
508 if (hws_gws_support || (KFD_IS_SOC15(node) &&
509 ((KFD_GC_VERSION(node) == IP_VERSION(9, 0, 1)
510 && kfd->mec2_fw_version >= 0x81b3) ||
511 (KFD_GC_VERSION(node) <= IP_VERSION(9, 4, 0)
512 && kfd->mec2_fw_version >= 0x1b3) ||
513 (KFD_GC_VERSION(node) == IP_VERSION(9, 4, 1)
514 && kfd->mec2_fw_version >= 0x30) ||
515 (KFD_GC_VERSION(node) == IP_VERSION(9, 4, 2)
516 && kfd->mec2_fw_version >= 0x28) ||
517 (KFD_GC_VERSION(node) == IP_VERSION(9, 4, 3)) ||
518 (KFD_GC_VERSION(node) >= IP_VERSION(10, 3, 0)
519 && KFD_GC_VERSION(node) < IP_VERSION(11, 0, 0)
520 && kfd->mec2_fw_version >= 0x6b) ||
521 (KFD_GC_VERSION(node) >= IP_VERSION(11, 0, 0)
522 && KFD_GC_VERSION(node) < IP_VERSION(12, 0, 0)
523 && mes_rev >= 68))))
524 ret = amdgpu_amdkfd_alloc_gws(node->adev,
525 node->adev->gds.gws_size, &node->gws);
526
527 return ret;
528}
529
530static void kfd_smi_init(struct kfd_node *dev)
531{
532 INIT_LIST_HEAD(&dev->smi_clients);
533 spin_lock_init(&dev->smi_lock);
534}
535
536static int kfd_init_node(struct kfd_node *node)
537{
538 int err = -1;
539
540 if (kfd_interrupt_init(node)) {
541 dev_err(kfd_device, "Error initializing interrupts\n");
542 goto kfd_interrupt_error;
543 }
544
545 node->dqm = device_queue_manager_init(node);
546 if (!node->dqm) {
547 dev_err(kfd_device, "Error initializing queue manager\n");
548 goto device_queue_manager_error;
549 }
550
551 if (kfd_gws_init(node)) {
552 dev_err(kfd_device, "Could not allocate %d gws\n",
553 node->adev->gds.gws_size);
554 goto gws_error;
555 }
556
557 if (kfd_resume(node))
558 goto kfd_resume_error;
559
560 if (kfd_topology_add_device(node)) {
561 dev_err(kfd_device, "Error adding device to topology\n");
562 goto kfd_topology_add_device_error;
563 }
564
565 kfd_smi_init(node);
566
567 return 0;
568
569kfd_topology_add_device_error:
570kfd_resume_error:
571gws_error:
572 device_queue_manager_uninit(node->dqm);
573device_queue_manager_error:
574 kfd_interrupt_exit(node);
575kfd_interrupt_error:
576 if (node->gws)
577 amdgpu_amdkfd_free_gws(node->adev, node->gws);
578
579 /* Cleanup the node memory here */
580 kfree(node);
581 return err;
582}
583
584static void kfd_cleanup_nodes(struct kfd_dev *kfd, unsigned int num_nodes)
585{
586 struct kfd_node *knode;
587 unsigned int i;
588
589 for (i = 0; i < num_nodes; i++) {
590 knode = kfd->nodes[i];
591 device_queue_manager_uninit(knode->dqm);
592 kfd_interrupt_exit(knode);
593 kfd_topology_remove_device(knode);
594 if (knode->gws)
595 amdgpu_amdkfd_free_gws(knode->adev, knode->gws);
596 kfree(knode);
597 kfd->nodes[i] = NULL;
598 }
599}
600
601static void kfd_setup_interrupt_bitmap(struct kfd_node *node,
602 unsigned int kfd_node_idx)
603{
604 struct amdgpu_device *adev = node->adev;
605 uint32_t xcc_mask = node->xcc_mask;
606 uint32_t xcc, mapped_xcc;
607 /*
608 * Interrupt bitmap is setup for processing interrupts from
609 * different XCDs and AIDs.
610 * Interrupt bitmap is defined as follows:
611 * 1. Bits 0-15 - correspond to the NodeId field.
612 * Each bit corresponds to NodeId number. For example, if
613 * a KFD node has interrupt bitmap set to 0x7, then this
614 * KFD node will process interrupts with NodeId = 0, 1 and 2
615 * in the IH cookie.
616 * 2. Bits 16-31 - unused.
617 *
618 * Please note that the kfd_node_idx argument passed to this
619 * function is not related to NodeId field received in the
620 * IH cookie.
621 *
622 * In CPX mode, a KFD node will process an interrupt if:
623 * - the Node Id matches the corresponding bit set in
624 * Bits 0-15.
625 * - AND VMID reported in the interrupt lies within the
626 * VMID range of the node.
627 */
628 for_each_inst(xcc, xcc_mask) {
629 mapped_xcc = GET_INST(GC, xcc);
630 node->interrupt_bitmap |= (mapped_xcc % 2 ? 5 : 3) << (4 * (mapped_xcc / 2));
631 }
632 dev_info(kfd_device, "Node: %d, interrupt_bitmap: %x\n", kfd_node_idx,
633 node->interrupt_bitmap);
634}
635
636bool kgd2kfd_device_init(struct kfd_dev *kfd,
637 const struct kgd2kfd_shared_resources *gpu_resources)
638{
639 unsigned int size, map_process_packet_size, i;
640 struct kfd_node *node;
641 uint32_t first_vmid_kfd, last_vmid_kfd, vmid_num_kfd;
642 unsigned int max_proc_per_quantum;
643 int partition_mode;
644 int xcp_idx;
645
646 kfd->mec_fw_version = amdgpu_amdkfd_get_fw_version(kfd->adev,
647 KGD_ENGINE_MEC1);
648 kfd->mec2_fw_version = amdgpu_amdkfd_get_fw_version(kfd->adev,
649 KGD_ENGINE_MEC2);
650 kfd->sdma_fw_version = amdgpu_amdkfd_get_fw_version(kfd->adev,
651 KGD_ENGINE_SDMA1);
652 kfd->shared_resources = *gpu_resources;
653
654 kfd->num_nodes = amdgpu_xcp_get_num_xcp(kfd->adev->xcp_mgr);
655
656 if (kfd->num_nodes == 0) {
657 dev_err(kfd_device,
658 "KFD num nodes cannot be 0, num_xcc_in_node: %d\n",
659 kfd->adev->gfx.num_xcc_per_xcp);
660 goto out;
661 }
662
663 /* Allow BIF to recode atomics to PCIe 3.0 AtomicOps.
664 * 32 and 64-bit requests are possible and must be
665 * supported.
666 */
667 kfd->pci_atomic_requested = amdgpu_amdkfd_have_atomics_support(kfd->adev);
668 if (!kfd->pci_atomic_requested &&
669 kfd->device_info.needs_pci_atomics &&
670 (!kfd->device_info.no_atomic_fw_version ||
671 kfd->mec_fw_version < kfd->device_info.no_atomic_fw_version)) {
672 dev_info(kfd_device,
673 "skipped device %x:%x, PCI rejects atomics %d<%d\n",
674 kfd->adev->pdev->vendor, kfd->adev->pdev->device,
675 kfd->mec_fw_version,
676 kfd->device_info.no_atomic_fw_version);
677 return false;
678 }
679
680 first_vmid_kfd = ffs(gpu_resources->compute_vmid_bitmap)-1;
681 last_vmid_kfd = fls(gpu_resources->compute_vmid_bitmap)-1;
682 vmid_num_kfd = last_vmid_kfd - first_vmid_kfd + 1;
683
684 /* For GFX9.4.3, we need special handling for VMIDs depending on
685 * partition mode.
686 * In CPX mode, the VMID range needs to be shared between XCDs.
687 * Additionally, there are 13 VMIDs (3-15) available for KFD. To
688 * divide them equally, we change starting VMID to 4 and not use
689 * VMID 3.
690 * If the VMID range changes for GFX9.4.3, then this code MUST be
691 * revisited.
692 */
693 if (kfd->adev->xcp_mgr) {
694 partition_mode = amdgpu_xcp_query_partition_mode(kfd->adev->xcp_mgr,
695 AMDGPU_XCP_FL_LOCKED);
696 if (partition_mode == AMDGPU_CPX_PARTITION_MODE &&
697 kfd->num_nodes != 1) {
698 vmid_num_kfd /= 2;
699 first_vmid_kfd = last_vmid_kfd + 1 - vmid_num_kfd*2;
700 }
701 }
702
703 /* Verify module parameters regarding mapped process number*/
704 if (hws_max_conc_proc >= 0)
705 max_proc_per_quantum = min((u32)hws_max_conc_proc, vmid_num_kfd);
706 else
707 max_proc_per_quantum = vmid_num_kfd;
708
709 /* calculate max size of mqds needed for queues */
710 size = max_num_of_queues_per_device *
711 kfd->device_info.mqd_size_aligned;
712
713 /*
714 * calculate max size of runlist packet.
715 * There can be only 2 packets at once
716 */
717 map_process_packet_size = KFD_GC_VERSION(kfd) == IP_VERSION(9, 4, 2) ?
718 sizeof(struct pm4_mes_map_process_aldebaran) :
719 sizeof(struct pm4_mes_map_process);
720 size += (KFD_MAX_NUM_OF_PROCESSES * map_process_packet_size +
721 max_num_of_queues_per_device * sizeof(struct pm4_mes_map_queues)
722 + sizeof(struct pm4_mes_runlist)) * 2;
723
724 /* Add size of HIQ & DIQ */
725 size += KFD_KERNEL_QUEUE_SIZE * 2;
726
727 /* add another 512KB for all other allocations on gart (HPD, fences) */
728 size += 512 * 1024;
729
730 if (amdgpu_amdkfd_alloc_gtt_mem(
731 kfd->adev, size, &kfd->gtt_mem,
732 &kfd->gtt_start_gpu_addr, &kfd->gtt_start_cpu_ptr,
733 false)) {
734 dev_err(kfd_device, "Could not allocate %d bytes\n", size);
735 goto alloc_gtt_mem_failure;
736 }
737
738 dev_info(kfd_device, "Allocated %d bytes on gart\n", size);
739
740 /* Initialize GTT sa with 512 byte chunk size */
741 if (kfd_gtt_sa_init(kfd, size, 512) != 0) {
742 dev_err(kfd_device, "Error initializing gtt sub-allocator\n");
743 goto kfd_gtt_sa_init_error;
744 }
745
746 if (kfd_doorbell_init(kfd)) {
747 dev_err(kfd_device,
748 "Error initializing doorbell aperture\n");
749 goto kfd_doorbell_error;
750 }
751
752 if (amdgpu_use_xgmi_p2p)
753 kfd->hive_id = kfd->adev->gmc.xgmi.hive_id;
754
755 /*
756 * For GFX9.4.3, the KFD abstracts all partitions within a socket as
757 * xGMI connected in the topology so assign a unique hive id per
758 * device based on the pci device location if device is in PCIe mode.
759 */
760 if (!kfd->hive_id && (KFD_GC_VERSION(kfd) == IP_VERSION(9, 4, 3)) && kfd->num_nodes > 1)
761 kfd->hive_id = pci_dev_id(kfd->adev->pdev);
762
763 kfd->noretry = kfd->adev->gmc.noretry;
764
765 kfd_cwsr_init(kfd);
766
767 dev_info(kfd_device, "Total number of KFD nodes to be created: %d\n",
768 kfd->num_nodes);
769
770 /* Allocate the KFD nodes */
771 for (i = 0, xcp_idx = 0; i < kfd->num_nodes; i++) {
772 node = kzalloc(sizeof(struct kfd_node), GFP_KERNEL);
773 if (!node)
774 goto node_alloc_error;
775
776 node->node_id = i;
777 node->adev = kfd->adev;
778 node->kfd = kfd;
779 node->kfd2kgd = kfd->kfd2kgd;
780 node->vm_info.vmid_num_kfd = vmid_num_kfd;
781 node->xcp = amdgpu_get_next_xcp(kfd->adev->xcp_mgr, &xcp_idx);
782 /* TODO : Check if error handling is needed */
783 if (node->xcp) {
784 amdgpu_xcp_get_inst_details(node->xcp, AMDGPU_XCP_GFX,
785 &node->xcc_mask);
786 ++xcp_idx;
787 } else {
788 node->xcc_mask =
789 (1U << NUM_XCC(kfd->adev->gfx.xcc_mask)) - 1;
790 }
791
792 if (node->xcp) {
793 dev_info(kfd_device, "KFD node %d partition %d size %lldM\n",
794 node->node_id, node->xcp->mem_id,
795 KFD_XCP_MEMORY_SIZE(node->adev, node->node_id) >> 20);
796 }
797
798 if (KFD_GC_VERSION(kfd) == IP_VERSION(9, 4, 3) &&
799 partition_mode == AMDGPU_CPX_PARTITION_MODE &&
800 kfd->num_nodes != 1) {
801 /* For GFX9.4.3 and CPX mode, first XCD gets VMID range
802 * 4-9 and second XCD gets VMID range 10-15.
803 */
804
805 node->vm_info.first_vmid_kfd = (i%2 == 0) ?
806 first_vmid_kfd :
807 first_vmid_kfd+vmid_num_kfd;
808 node->vm_info.last_vmid_kfd = (i%2 == 0) ?
809 last_vmid_kfd-vmid_num_kfd :
810 last_vmid_kfd;
811 node->compute_vmid_bitmap =
812 ((0x1 << (node->vm_info.last_vmid_kfd + 1)) - 1) -
813 ((0x1 << (node->vm_info.first_vmid_kfd)) - 1);
814 } else {
815 node->vm_info.first_vmid_kfd = first_vmid_kfd;
816 node->vm_info.last_vmid_kfd = last_vmid_kfd;
817 node->compute_vmid_bitmap =
818 gpu_resources->compute_vmid_bitmap;
819 }
820 node->max_proc_per_quantum = max_proc_per_quantum;
821 atomic_set(&node->sram_ecc_flag, 0);
822
823 amdgpu_amdkfd_get_local_mem_info(kfd->adev,
824 &node->local_mem_info, node->xcp);
825
826 if (KFD_GC_VERSION(kfd) == IP_VERSION(9, 4, 3))
827 kfd_setup_interrupt_bitmap(node, i);
828
829 /* Initialize the KFD node */
830 if (kfd_init_node(node)) {
831 dev_err(kfd_device, "Error initializing KFD node\n");
832 goto node_init_error;
833 }
834 kfd->nodes[i] = node;
835 }
836
837 svm_range_set_max_pages(kfd->adev);
838
839 spin_lock_init(&kfd->watch_points_lock);
840
841 kfd->init_complete = true;
842 dev_info(kfd_device, "added device %x:%x\n", kfd->adev->pdev->vendor,
843 kfd->adev->pdev->device);
844
845 pr_debug("Starting kfd with the following scheduling policy %d\n",
846 node->dqm->sched_policy);
847
848 goto out;
849
850node_init_error:
851node_alloc_error:
852 kfd_cleanup_nodes(kfd, i);
853 kfd_doorbell_fini(kfd);
854kfd_doorbell_error:
855 kfd_gtt_sa_fini(kfd);
856kfd_gtt_sa_init_error:
857 amdgpu_amdkfd_free_gtt_mem(kfd->adev, kfd->gtt_mem);
858alloc_gtt_mem_failure:
859 dev_err(kfd_device,
860 "device %x:%x NOT added due to errors\n",
861 kfd->adev->pdev->vendor, kfd->adev->pdev->device);
862out:
863 return kfd->init_complete;
864}
865
866void kgd2kfd_device_exit(struct kfd_dev *kfd)
867{
868 if (kfd->init_complete) {
869 /* Cleanup KFD nodes */
870 kfd_cleanup_nodes(kfd, kfd->num_nodes);
871 /* Cleanup common/shared resources */
872 kfd_doorbell_fini(kfd);
873 ida_destroy(&kfd->doorbell_ida);
874 kfd_gtt_sa_fini(kfd);
875 amdgpu_amdkfd_free_gtt_mem(kfd->adev, kfd->gtt_mem);
876 }
877
878 kfree(kfd);
879}
880
881int kgd2kfd_pre_reset(struct kfd_dev *kfd)
882{
883 struct kfd_node *node;
884 int i;
885
886 if (!kfd->init_complete)
887 return 0;
888
889 for (i = 0; i < kfd->num_nodes; i++) {
890 node = kfd->nodes[i];
891 kfd_smi_event_update_gpu_reset(node, false);
892 node->dqm->ops.pre_reset(node->dqm);
893 }
894
895 kgd2kfd_suspend(kfd, false);
896
897 for (i = 0; i < kfd->num_nodes; i++)
898 kfd_signal_reset_event(kfd->nodes[i]);
899
900 return 0;
901}
902
903/*
904 * Fix me. KFD won't be able to resume existing process for now.
905 * We will keep all existing process in a evicted state and
906 * wait the process to be terminated.
907 */
908
909int kgd2kfd_post_reset(struct kfd_dev *kfd)
910{
911 int ret;
912 struct kfd_node *node;
913 int i;
914
915 if (!kfd->init_complete)
916 return 0;
917
918 for (i = 0; i < kfd->num_nodes; i++) {
919 ret = kfd_resume(kfd->nodes[i]);
920 if (ret)
921 return ret;
922 }
923
924 mutex_lock(&kfd_processes_mutex);
925 --kfd_locked;
926 mutex_unlock(&kfd_processes_mutex);
927
928 for (i = 0; i < kfd->num_nodes; i++) {
929 node = kfd->nodes[i];
930 atomic_set(&node->sram_ecc_flag, 0);
931 kfd_smi_event_update_gpu_reset(node, true);
932 }
933
934 return 0;
935}
936
937bool kfd_is_locked(void)
938{
939 lockdep_assert_held(&kfd_processes_mutex);
940 return (kfd_locked > 0);
941}
942
943void kgd2kfd_suspend(struct kfd_dev *kfd, bool run_pm)
944{
945 struct kfd_node *node;
946 int i;
947 int count;
948
949 if (!kfd->init_complete)
950 return;
951
952 /* for runtime suspend, skip locking kfd */
953 if (!run_pm) {
954 mutex_lock(&kfd_processes_mutex);
955 count = ++kfd_locked;
956 mutex_unlock(&kfd_processes_mutex);
957
958 /* For first KFD device suspend all the KFD processes */
959 if (count == 1)
960 kfd_suspend_all_processes();
961 }
962
963 for (i = 0; i < kfd->num_nodes; i++) {
964 node = kfd->nodes[i];
965 node->dqm->ops.stop(node->dqm);
966 }
967}
968
969int kgd2kfd_resume(struct kfd_dev *kfd, bool run_pm)
970{
971 int ret, count, i;
972
973 if (!kfd->init_complete)
974 return 0;
975
976 for (i = 0; i < kfd->num_nodes; i++) {
977 ret = kfd_resume(kfd->nodes[i]);
978 if (ret)
979 return ret;
980 }
981
982 /* for runtime resume, skip unlocking kfd */
983 if (!run_pm) {
984 mutex_lock(&kfd_processes_mutex);
985 count = --kfd_locked;
986 mutex_unlock(&kfd_processes_mutex);
987
988 WARN_ONCE(count < 0, "KFD suspend / resume ref. error");
989 if (count == 0)
990 ret = kfd_resume_all_processes();
991 }
992
993 return ret;
994}
995
996static int kfd_resume(struct kfd_node *node)
997{
998 int err = 0;
999
1000 err = node->dqm->ops.start(node->dqm);
1001 if (err)
1002 dev_err(kfd_device,
1003 "Error starting queue manager for device %x:%x\n",
1004 node->adev->pdev->vendor, node->adev->pdev->device);
1005
1006 return err;
1007}
1008
1009static inline void kfd_queue_work(struct workqueue_struct *wq,
1010 struct work_struct *work)
1011{
1012 int cpu, new_cpu;
1013
1014 cpu = new_cpu = smp_processor_id();
1015 do {
1016 new_cpu = cpumask_next(new_cpu, cpu_online_mask) % nr_cpu_ids;
1017 if (cpu_to_node(new_cpu) == numa_node_id())
1018 break;
1019 } while (cpu != new_cpu);
1020
1021 queue_work_on(new_cpu, wq, work);
1022}
1023
1024/* This is called directly from KGD at ISR. */
1025void kgd2kfd_interrupt(struct kfd_dev *kfd, const void *ih_ring_entry)
1026{
1027 uint32_t patched_ihre[KFD_MAX_RING_ENTRY_SIZE], i;
1028 bool is_patched = false;
1029 unsigned long flags;
1030 struct kfd_node *node;
1031
1032 if (!kfd->init_complete)
1033 return;
1034
1035 if (kfd->device_info.ih_ring_entry_size > sizeof(patched_ihre)) {
1036 dev_err_once(kfd_device, "Ring entry too small\n");
1037 return;
1038 }
1039
1040 for (i = 0; i < kfd->num_nodes; i++) {
1041 node = kfd->nodes[i];
1042 spin_lock_irqsave(&node->interrupt_lock, flags);
1043
1044 if (node->interrupts_active
1045 && interrupt_is_wanted(node, ih_ring_entry,
1046 patched_ihre, &is_patched)
1047 && enqueue_ih_ring_entry(node,
1048 is_patched ? patched_ihre : ih_ring_entry)) {
1049 kfd_queue_work(node->ih_wq, &node->interrupt_work);
1050 spin_unlock_irqrestore(&node->interrupt_lock, flags);
1051 return;
1052 }
1053 spin_unlock_irqrestore(&node->interrupt_lock, flags);
1054 }
1055
1056}
1057
1058int kgd2kfd_quiesce_mm(struct mm_struct *mm, uint32_t trigger)
1059{
1060 struct kfd_process *p;
1061 int r;
1062
1063 /* Because we are called from arbitrary context (workqueue) as opposed
1064 * to process context, kfd_process could attempt to exit while we are
1065 * running so the lookup function increments the process ref count.
1066 */
1067 p = kfd_lookup_process_by_mm(mm);
1068 if (!p)
1069 return -ESRCH;
1070
1071 WARN(debug_evictions, "Evicting pid %d", p->lead_thread->pid);
1072 r = kfd_process_evict_queues(p, trigger);
1073
1074 kfd_unref_process(p);
1075 return r;
1076}
1077
1078int kgd2kfd_resume_mm(struct mm_struct *mm)
1079{
1080 struct kfd_process *p;
1081 int r;
1082
1083 /* Because we are called from arbitrary context (workqueue) as opposed
1084 * to process context, kfd_process could attempt to exit while we are
1085 * running so the lookup function increments the process ref count.
1086 */
1087 p = kfd_lookup_process_by_mm(mm);
1088 if (!p)
1089 return -ESRCH;
1090
1091 r = kfd_process_restore_queues(p);
1092
1093 kfd_unref_process(p);
1094 return r;
1095}
1096
1097/** kgd2kfd_schedule_evict_and_restore_process - Schedules work queue that will
1098 * prepare for safe eviction of KFD BOs that belong to the specified
1099 * process.
1100 *
1101 * @mm: mm_struct that identifies the specified KFD process
1102 * @fence: eviction fence attached to KFD process BOs
1103 *
1104 */
1105int kgd2kfd_schedule_evict_and_restore_process(struct mm_struct *mm,
1106 struct dma_fence *fence)
1107{
1108 struct kfd_process *p;
1109 unsigned long active_time;
1110 unsigned long delay_jiffies = msecs_to_jiffies(PROCESS_ACTIVE_TIME_MS);
1111
1112 if (!fence)
1113 return -EINVAL;
1114
1115 if (dma_fence_is_signaled(fence))
1116 return 0;
1117
1118 p = kfd_lookup_process_by_mm(mm);
1119 if (!p)
1120 return -ENODEV;
1121
1122 if (fence->seqno == p->last_eviction_seqno)
1123 goto out;
1124
1125 p->last_eviction_seqno = fence->seqno;
1126
1127 /* Avoid KFD process starvation. Wait for at least
1128 * PROCESS_ACTIVE_TIME_MS before evicting the process again
1129 */
1130 active_time = get_jiffies_64() - p->last_restore_timestamp;
1131 if (delay_jiffies > active_time)
1132 delay_jiffies -= active_time;
1133 else
1134 delay_jiffies = 0;
1135
1136 /* During process initialization eviction_work.dwork is initialized
1137 * to kfd_evict_bo_worker
1138 */
1139 WARN(debug_evictions, "Scheduling eviction of pid %d in %ld jiffies",
1140 p->lead_thread->pid, delay_jiffies);
1141 schedule_delayed_work(&p->eviction_work, delay_jiffies);
1142out:
1143 kfd_unref_process(p);
1144 return 0;
1145}
1146
1147static int kfd_gtt_sa_init(struct kfd_dev *kfd, unsigned int buf_size,
1148 unsigned int chunk_size)
1149{
1150 if (WARN_ON(buf_size < chunk_size))
1151 return -EINVAL;
1152 if (WARN_ON(buf_size == 0))
1153 return -EINVAL;
1154 if (WARN_ON(chunk_size == 0))
1155 return -EINVAL;
1156
1157 kfd->gtt_sa_chunk_size = chunk_size;
1158 kfd->gtt_sa_num_of_chunks = buf_size / chunk_size;
1159
1160 kfd->gtt_sa_bitmap = bitmap_zalloc(kfd->gtt_sa_num_of_chunks,
1161 GFP_KERNEL);
1162 if (!kfd->gtt_sa_bitmap)
1163 return -ENOMEM;
1164
1165 pr_debug("gtt_sa_num_of_chunks = %d, gtt_sa_bitmap = %p\n",
1166 kfd->gtt_sa_num_of_chunks, kfd->gtt_sa_bitmap);
1167
1168 mutex_init(&kfd->gtt_sa_lock);
1169
1170 return 0;
1171}
1172
1173static void kfd_gtt_sa_fini(struct kfd_dev *kfd)
1174{
1175 mutex_destroy(&kfd->gtt_sa_lock);
1176 bitmap_free(kfd->gtt_sa_bitmap);
1177}
1178
1179static inline uint64_t kfd_gtt_sa_calc_gpu_addr(uint64_t start_addr,
1180 unsigned int bit_num,
1181 unsigned int chunk_size)
1182{
1183 return start_addr + bit_num * chunk_size;
1184}
1185
1186static inline uint32_t *kfd_gtt_sa_calc_cpu_addr(void *start_addr,
1187 unsigned int bit_num,
1188 unsigned int chunk_size)
1189{
1190 return (uint32_t *) ((uint64_t) start_addr + bit_num * chunk_size);
1191}
1192
1193int kfd_gtt_sa_allocate(struct kfd_node *node, unsigned int size,
1194 struct kfd_mem_obj **mem_obj)
1195{
1196 unsigned int found, start_search, cur_size;
1197 struct kfd_dev *kfd = node->kfd;
1198
1199 if (size == 0)
1200 return -EINVAL;
1201
1202 if (size > kfd->gtt_sa_num_of_chunks * kfd->gtt_sa_chunk_size)
1203 return -ENOMEM;
1204
1205 *mem_obj = kzalloc(sizeof(struct kfd_mem_obj), GFP_KERNEL);
1206 if (!(*mem_obj))
1207 return -ENOMEM;
1208
1209 pr_debug("Allocated mem_obj = %p for size = %d\n", *mem_obj, size);
1210
1211 start_search = 0;
1212
1213 mutex_lock(&kfd->gtt_sa_lock);
1214
1215kfd_gtt_restart_search:
1216 /* Find the first chunk that is free */
1217 found = find_next_zero_bit(kfd->gtt_sa_bitmap,
1218 kfd->gtt_sa_num_of_chunks,
1219 start_search);
1220
1221 pr_debug("Found = %d\n", found);
1222
1223 /* If there wasn't any free chunk, bail out */
1224 if (found == kfd->gtt_sa_num_of_chunks)
1225 goto kfd_gtt_no_free_chunk;
1226
1227 /* Update fields of mem_obj */
1228 (*mem_obj)->range_start = found;
1229 (*mem_obj)->range_end = found;
1230 (*mem_obj)->gpu_addr = kfd_gtt_sa_calc_gpu_addr(
1231 kfd->gtt_start_gpu_addr,
1232 found,
1233 kfd->gtt_sa_chunk_size);
1234 (*mem_obj)->cpu_ptr = kfd_gtt_sa_calc_cpu_addr(
1235 kfd->gtt_start_cpu_ptr,
1236 found,
1237 kfd->gtt_sa_chunk_size);
1238
1239 pr_debug("gpu_addr = %p, cpu_addr = %p\n",
1240 (uint64_t *) (*mem_obj)->gpu_addr, (*mem_obj)->cpu_ptr);
1241
1242 /* If we need only one chunk, mark it as allocated and get out */
1243 if (size <= kfd->gtt_sa_chunk_size) {
1244 pr_debug("Single bit\n");
1245 __set_bit(found, kfd->gtt_sa_bitmap);
1246 goto kfd_gtt_out;
1247 }
1248
1249 /* Otherwise, try to see if we have enough contiguous chunks */
1250 cur_size = size - kfd->gtt_sa_chunk_size;
1251 do {
1252 (*mem_obj)->range_end =
1253 find_next_zero_bit(kfd->gtt_sa_bitmap,
1254 kfd->gtt_sa_num_of_chunks, ++found);
1255 /*
1256 * If next free chunk is not contiguous than we need to
1257 * restart our search from the last free chunk we found (which
1258 * wasn't contiguous to the previous ones
1259 */
1260 if ((*mem_obj)->range_end != found) {
1261 start_search = found;
1262 goto kfd_gtt_restart_search;
1263 }
1264
1265 /*
1266 * If we reached end of buffer, bail out with error
1267 */
1268 if (found == kfd->gtt_sa_num_of_chunks)
1269 goto kfd_gtt_no_free_chunk;
1270
1271 /* Check if we don't need another chunk */
1272 if (cur_size <= kfd->gtt_sa_chunk_size)
1273 cur_size = 0;
1274 else
1275 cur_size -= kfd->gtt_sa_chunk_size;
1276
1277 } while (cur_size > 0);
1278
1279 pr_debug("range_start = %d, range_end = %d\n",
1280 (*mem_obj)->range_start, (*mem_obj)->range_end);
1281
1282 /* Mark the chunks as allocated */
1283 bitmap_set(kfd->gtt_sa_bitmap, (*mem_obj)->range_start,
1284 (*mem_obj)->range_end - (*mem_obj)->range_start + 1);
1285
1286kfd_gtt_out:
1287 mutex_unlock(&kfd->gtt_sa_lock);
1288 return 0;
1289
1290kfd_gtt_no_free_chunk:
1291 pr_debug("Allocation failed with mem_obj = %p\n", *mem_obj);
1292 mutex_unlock(&kfd->gtt_sa_lock);
1293 kfree(*mem_obj);
1294 return -ENOMEM;
1295}
1296
1297int kfd_gtt_sa_free(struct kfd_node *node, struct kfd_mem_obj *mem_obj)
1298{
1299 struct kfd_dev *kfd = node->kfd;
1300
1301 /* Act like kfree when trying to free a NULL object */
1302 if (!mem_obj)
1303 return 0;
1304
1305 pr_debug("Free mem_obj = %p, range_start = %d, range_end = %d\n",
1306 mem_obj, mem_obj->range_start, mem_obj->range_end);
1307
1308 mutex_lock(&kfd->gtt_sa_lock);
1309
1310 /* Mark the chunks as free */
1311 bitmap_clear(kfd->gtt_sa_bitmap, mem_obj->range_start,
1312 mem_obj->range_end - mem_obj->range_start + 1);
1313
1314 mutex_unlock(&kfd->gtt_sa_lock);
1315
1316 kfree(mem_obj);
1317 return 0;
1318}
1319
1320void kgd2kfd_set_sram_ecc_flag(struct kfd_dev *kfd)
1321{
1322 /*
1323 * TODO: Currently update SRAM ECC flag for first node.
1324 * This needs to be updated later when we can
1325 * identify SRAM ECC error on other nodes also.
1326 */
1327 if (kfd)
1328 atomic_inc(&kfd->nodes[0]->sram_ecc_flag);
1329}
1330
1331void kfd_inc_compute_active(struct kfd_node *node)
1332{
1333 if (atomic_inc_return(&node->kfd->compute_profile) == 1)
1334 amdgpu_amdkfd_set_compute_idle(node->adev, false);
1335}
1336
1337void kfd_dec_compute_active(struct kfd_node *node)
1338{
1339 int count = atomic_dec_return(&node->kfd->compute_profile);
1340
1341 if (count == 0)
1342 amdgpu_amdkfd_set_compute_idle(node->adev, true);
1343 WARN_ONCE(count < 0, "Compute profile ref. count error");
1344}
1345
1346void kgd2kfd_smi_event_throttle(struct kfd_dev *kfd, uint64_t throttle_bitmask)
1347{
1348 /*
1349 * TODO: For now, raise the throttling event only on first node.
1350 * This will need to change after we are able to determine
1351 * which node raised the throttling event.
1352 */
1353 if (kfd && kfd->init_complete)
1354 kfd_smi_event_update_thermal_throttling(kfd->nodes[0],
1355 throttle_bitmask);
1356}
1357
1358/* kfd_get_num_sdma_engines returns the number of PCIe optimized SDMA and
1359 * kfd_get_num_xgmi_sdma_engines returns the number of XGMI SDMA.
1360 * When the device has more than two engines, we reserve two for PCIe to enable
1361 * full-duplex and the rest are used as XGMI.
1362 */
1363unsigned int kfd_get_num_sdma_engines(struct kfd_node *node)
1364{
1365 /* If XGMI is not supported, all SDMA engines are PCIe */
1366 if (!node->adev->gmc.xgmi.supported)
1367 return node->adev->sdma.num_instances/(int)node->kfd->num_nodes;
1368
1369 return min(node->adev->sdma.num_instances/(int)node->kfd->num_nodes, 2);
1370}
1371
1372unsigned int kfd_get_num_xgmi_sdma_engines(struct kfd_node *node)
1373{
1374 /* After reserved for PCIe, the rest of engines are XGMI */
1375 return node->adev->sdma.num_instances/(int)node->kfd->num_nodes -
1376 kfd_get_num_sdma_engines(node);
1377}
1378
1379int kgd2kfd_check_and_lock_kfd(void)
1380{
1381 mutex_lock(&kfd_processes_mutex);
1382 if (!hash_empty(kfd_processes_table) || kfd_is_locked()) {
1383 mutex_unlock(&kfd_processes_mutex);
1384 return -EBUSY;
1385 }
1386
1387 ++kfd_locked;
1388 mutex_unlock(&kfd_processes_mutex);
1389
1390 return 0;
1391}
1392
1393void kgd2kfd_unlock_kfd(void)
1394{
1395 mutex_lock(&kfd_processes_mutex);
1396 --kfd_locked;
1397 mutex_unlock(&kfd_processes_mutex);
1398}
1399
1400#if defined(CONFIG_DEBUG_FS)
1401
1402/* This function will send a package to HIQ to hang the HWS
1403 * which will trigger a GPU reset and bring the HWS back to normal state
1404 */
1405int kfd_debugfs_hang_hws(struct kfd_node *dev)
1406{
1407 if (dev->dqm->sched_policy != KFD_SCHED_POLICY_HWS) {
1408 pr_err("HWS is not enabled");
1409 return -EINVAL;
1410 }
1411
1412 return dqm_debugfs_hang_hws(dev->dqm);
1413}
1414
1415#endif