Loading...
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Xilinx Spartan6 and 7 Series Slave Serial SPI Driver
4 *
5 * Copyright (C) 2017 DENX Software Engineering
6 *
7 * Anatolij Gustschin <agust@denx.de>
8 *
9 * Manage Xilinx FPGA firmware that is loaded over SPI using
10 * the slave serial configuration interface.
11 */
12
13#include <linux/delay.h>
14#include <linux/device.h>
15#include <linux/fpga/fpga-mgr.h>
16#include <linux/gpio/consumer.h>
17#include <linux/module.h>
18#include <linux/mod_devicetable.h>
19#include <linux/of.h>
20#include <linux/spi/spi.h>
21#include <linux/sizes.h>
22
23struct xilinx_spi_conf {
24 struct spi_device *spi;
25 struct gpio_desc *prog_b;
26 struct gpio_desc *init_b;
27 struct gpio_desc *done;
28};
29
30static enum fpga_mgr_states xilinx_spi_state(struct fpga_manager *mgr)
31{
32 struct xilinx_spi_conf *conf = mgr->priv;
33
34 if (!gpiod_get_value(conf->done))
35 return FPGA_MGR_STATE_RESET;
36
37 return FPGA_MGR_STATE_UNKNOWN;
38}
39
40/**
41 * wait_for_init_b - wait for the INIT_B pin to have a given state, or wait
42 * a given delay if the pin is unavailable
43 *
44 * @mgr: The FPGA manager object
45 * @value: Value INIT_B to wait for (1 = asserted = low)
46 * @alt_udelay: Delay to wait if the INIT_B GPIO is not available
47 *
48 * Returns 0 when the INIT_B GPIO reached the given state or -ETIMEDOUT if
49 * too much time passed waiting for that. If no INIT_B GPIO is available
50 * then always return 0.
51 */
52static int wait_for_init_b(struct fpga_manager *mgr, int value,
53 unsigned long alt_udelay)
54{
55 struct xilinx_spi_conf *conf = mgr->priv;
56 unsigned long timeout = jiffies + msecs_to_jiffies(1000);
57
58 if (conf->init_b) {
59 while (time_before(jiffies, timeout)) {
60 /* dump_state(conf, "wait for init_d .."); */
61 if (gpiod_get_value(conf->init_b) == value)
62 return 0;
63 usleep_range(100, 400);
64 }
65 return -ETIMEDOUT;
66 }
67
68 udelay(alt_udelay);
69
70 return 0;
71}
72
73static int xilinx_spi_write_init(struct fpga_manager *mgr,
74 struct fpga_image_info *info,
75 const char *buf, size_t count)
76{
77 struct xilinx_spi_conf *conf = mgr->priv;
78 int err;
79
80 if (info->flags & FPGA_MGR_PARTIAL_RECONFIG) {
81 dev_err(&mgr->dev, "Partial reconfiguration not supported.\n");
82 return -EINVAL;
83 }
84
85 gpiod_set_value(conf->prog_b, 1);
86
87 err = wait_for_init_b(mgr, 1, 1); /* min is 500 ns */
88 if (err) {
89 dev_err(&mgr->dev, "INIT_B pin did not go low\n");
90 gpiod_set_value(conf->prog_b, 0);
91 return err;
92 }
93
94 gpiod_set_value(conf->prog_b, 0);
95
96 err = wait_for_init_b(mgr, 0, 0);
97 if (err) {
98 dev_err(&mgr->dev, "INIT_B pin did not go high\n");
99 return err;
100 }
101
102 if (gpiod_get_value(conf->done)) {
103 dev_err(&mgr->dev, "Unexpected DONE pin state...\n");
104 return -EIO;
105 }
106
107 /* program latency */
108 usleep_range(7500, 7600);
109 return 0;
110}
111
112static int xilinx_spi_write(struct fpga_manager *mgr, const char *buf,
113 size_t count)
114{
115 struct xilinx_spi_conf *conf = mgr->priv;
116 const char *fw_data = buf;
117 const char *fw_data_end = fw_data + count;
118
119 while (fw_data < fw_data_end) {
120 size_t remaining, stride;
121 int ret;
122
123 remaining = fw_data_end - fw_data;
124 stride = min_t(size_t, remaining, SZ_4K);
125
126 ret = spi_write(conf->spi, fw_data, stride);
127 if (ret) {
128 dev_err(&mgr->dev, "SPI error in firmware write: %d\n",
129 ret);
130 return ret;
131 }
132 fw_data += stride;
133 }
134
135 return 0;
136}
137
138static int xilinx_spi_apply_cclk_cycles(struct xilinx_spi_conf *conf)
139{
140 struct spi_device *spi = conf->spi;
141 const u8 din_data[1] = { 0xff };
142 int ret;
143
144 ret = spi_write(conf->spi, din_data, sizeof(din_data));
145 if (ret)
146 dev_err(&spi->dev, "applying CCLK cycles failed: %d\n", ret);
147
148 return ret;
149}
150
151static int xilinx_spi_write_complete(struct fpga_manager *mgr,
152 struct fpga_image_info *info)
153{
154 struct xilinx_spi_conf *conf = mgr->priv;
155 unsigned long timeout;
156 int ret;
157
158 if (gpiod_get_value(conf->done))
159 return xilinx_spi_apply_cclk_cycles(conf);
160
161 timeout = jiffies + usecs_to_jiffies(info->config_complete_timeout_us);
162
163 while (time_before(jiffies, timeout)) {
164
165 ret = xilinx_spi_apply_cclk_cycles(conf);
166 if (ret)
167 return ret;
168
169 if (gpiod_get_value(conf->done))
170 return xilinx_spi_apply_cclk_cycles(conf);
171 }
172
173 dev_err(&mgr->dev, "Timeout after config data transfer.\n");
174 return -ETIMEDOUT;
175}
176
177static const struct fpga_manager_ops xilinx_spi_ops = {
178 .state = xilinx_spi_state,
179 .write_init = xilinx_spi_write_init,
180 .write = xilinx_spi_write,
181 .write_complete = xilinx_spi_write_complete,
182};
183
184static int xilinx_spi_probe(struct spi_device *spi)
185{
186 struct xilinx_spi_conf *conf;
187 struct fpga_manager *mgr;
188
189 conf = devm_kzalloc(&spi->dev, sizeof(*conf), GFP_KERNEL);
190 if (!conf)
191 return -ENOMEM;
192
193 conf->spi = spi;
194
195 /* PROGRAM_B is active low */
196 conf->prog_b = devm_gpiod_get(&spi->dev, "prog_b", GPIOD_OUT_LOW);
197 if (IS_ERR(conf->prog_b)) {
198 dev_err(&spi->dev, "Failed to get PROGRAM_B gpio: %ld\n",
199 PTR_ERR(conf->prog_b));
200 return PTR_ERR(conf->prog_b);
201 }
202
203 conf->init_b = devm_gpiod_get_optional(&spi->dev, "init-b", GPIOD_IN);
204 if (IS_ERR(conf->init_b)) {
205 dev_err(&spi->dev, "Failed to get INIT_B gpio: %ld\n",
206 PTR_ERR(conf->init_b));
207 return PTR_ERR(conf->init_b);
208 }
209
210 conf->done = devm_gpiod_get(&spi->dev, "done", GPIOD_IN);
211 if (IS_ERR(conf->done)) {
212 dev_err(&spi->dev, "Failed to get DONE gpio: %ld\n",
213 PTR_ERR(conf->done));
214 return PTR_ERR(conf->done);
215 }
216
217 mgr = devm_fpga_mgr_create(&spi->dev,
218 "Xilinx Slave Serial FPGA Manager",
219 &xilinx_spi_ops, conf);
220 if (!mgr)
221 return -ENOMEM;
222
223 spi_set_drvdata(spi, mgr);
224
225 return fpga_mgr_register(mgr);
226}
227
228static int xilinx_spi_remove(struct spi_device *spi)
229{
230 struct fpga_manager *mgr = spi_get_drvdata(spi);
231
232 fpga_mgr_unregister(mgr);
233
234 return 0;
235}
236
237static const struct of_device_id xlnx_spi_of_match[] = {
238 { .compatible = "xlnx,fpga-slave-serial", },
239 {}
240};
241MODULE_DEVICE_TABLE(of, xlnx_spi_of_match);
242
243static struct spi_driver xilinx_slave_spi_driver = {
244 .driver = {
245 .name = "xlnx-slave-spi",
246 .of_match_table = of_match_ptr(xlnx_spi_of_match),
247 },
248 .probe = xilinx_spi_probe,
249 .remove = xilinx_spi_remove,
250};
251
252module_spi_driver(xilinx_slave_spi_driver)
253
254MODULE_LICENSE("GPL v2");
255MODULE_AUTHOR("Anatolij Gustschin <agust@denx.de>");
256MODULE_DESCRIPTION("Load Xilinx FPGA firmware over SPI");
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Xilinx Spartan6 Slave Serial SPI Driver
4 *
5 * Copyright (C) 2017 DENX Software Engineering
6 *
7 * Anatolij Gustschin <agust@denx.de>
8 *
9 * Manage Xilinx FPGA firmware that is loaded over SPI using
10 * the slave serial configuration interface.
11 */
12
13#include <linux/delay.h>
14#include <linux/device.h>
15#include <linux/fpga/fpga-mgr.h>
16#include <linux/gpio/consumer.h>
17#include <linux/module.h>
18#include <linux/mod_devicetable.h>
19#include <linux/of.h>
20#include <linux/spi/spi.h>
21#include <linux/sizes.h>
22
23struct xilinx_spi_conf {
24 struct spi_device *spi;
25 struct gpio_desc *prog_b;
26 struct gpio_desc *done;
27};
28
29static enum fpga_mgr_states xilinx_spi_state(struct fpga_manager *mgr)
30{
31 struct xilinx_spi_conf *conf = mgr->priv;
32
33 if (!gpiod_get_value(conf->done))
34 return FPGA_MGR_STATE_RESET;
35
36 return FPGA_MGR_STATE_UNKNOWN;
37}
38
39static int xilinx_spi_write_init(struct fpga_manager *mgr,
40 struct fpga_image_info *info,
41 const char *buf, size_t count)
42{
43 struct xilinx_spi_conf *conf = mgr->priv;
44 const size_t prog_latency_7500us = 7500;
45 const size_t prog_pulse_1us = 1;
46
47 if (info->flags & FPGA_MGR_PARTIAL_RECONFIG) {
48 dev_err(&mgr->dev, "Partial reconfiguration not supported.\n");
49 return -EINVAL;
50 }
51
52 gpiod_set_value(conf->prog_b, 1);
53
54 udelay(prog_pulse_1us); /* min is 500 ns */
55
56 gpiod_set_value(conf->prog_b, 0);
57
58 if (gpiod_get_value(conf->done)) {
59 dev_err(&mgr->dev, "Unexpected DONE pin state...\n");
60 return -EIO;
61 }
62
63 /* program latency */
64 usleep_range(prog_latency_7500us, prog_latency_7500us + 100);
65 return 0;
66}
67
68static int xilinx_spi_write(struct fpga_manager *mgr, const char *buf,
69 size_t count)
70{
71 struct xilinx_spi_conf *conf = mgr->priv;
72 const char *fw_data = buf;
73 const char *fw_data_end = fw_data + count;
74
75 while (fw_data < fw_data_end) {
76 size_t remaining, stride;
77 int ret;
78
79 remaining = fw_data_end - fw_data;
80 stride = min_t(size_t, remaining, SZ_4K);
81
82 ret = spi_write(conf->spi, fw_data, stride);
83 if (ret) {
84 dev_err(&mgr->dev, "SPI error in firmware write: %d\n",
85 ret);
86 return ret;
87 }
88 fw_data += stride;
89 }
90
91 return 0;
92}
93
94static int xilinx_spi_apply_cclk_cycles(struct xilinx_spi_conf *conf)
95{
96 struct spi_device *spi = conf->spi;
97 const u8 din_data[1] = { 0xff };
98 int ret;
99
100 ret = spi_write(conf->spi, din_data, sizeof(din_data));
101 if (ret)
102 dev_err(&spi->dev, "applying CCLK cycles failed: %d\n", ret);
103
104 return ret;
105}
106
107static int xilinx_spi_write_complete(struct fpga_manager *mgr,
108 struct fpga_image_info *info)
109{
110 struct xilinx_spi_conf *conf = mgr->priv;
111 unsigned long timeout;
112 int ret;
113
114 if (gpiod_get_value(conf->done))
115 return xilinx_spi_apply_cclk_cycles(conf);
116
117 timeout = jiffies + usecs_to_jiffies(info->config_complete_timeout_us);
118
119 while (time_before(jiffies, timeout)) {
120
121 ret = xilinx_spi_apply_cclk_cycles(conf);
122 if (ret)
123 return ret;
124
125 if (gpiod_get_value(conf->done))
126 return xilinx_spi_apply_cclk_cycles(conf);
127 }
128
129 dev_err(&mgr->dev, "Timeout after config data transfer.\n");
130 return -ETIMEDOUT;
131}
132
133static const struct fpga_manager_ops xilinx_spi_ops = {
134 .state = xilinx_spi_state,
135 .write_init = xilinx_spi_write_init,
136 .write = xilinx_spi_write,
137 .write_complete = xilinx_spi_write_complete,
138};
139
140static int xilinx_spi_probe(struct spi_device *spi)
141{
142 struct xilinx_spi_conf *conf;
143 struct fpga_manager *mgr;
144
145 conf = devm_kzalloc(&spi->dev, sizeof(*conf), GFP_KERNEL);
146 if (!conf)
147 return -ENOMEM;
148
149 conf->spi = spi;
150
151 /* PROGRAM_B is active low */
152 conf->prog_b = devm_gpiod_get(&spi->dev, "prog_b", GPIOD_OUT_LOW);
153 if (IS_ERR(conf->prog_b)) {
154 dev_err(&spi->dev, "Failed to get PROGRAM_B gpio: %ld\n",
155 PTR_ERR(conf->prog_b));
156 return PTR_ERR(conf->prog_b);
157 }
158
159 conf->done = devm_gpiod_get(&spi->dev, "done", GPIOD_IN);
160 if (IS_ERR(conf->done)) {
161 dev_err(&spi->dev, "Failed to get DONE gpio: %ld\n",
162 PTR_ERR(conf->done));
163 return PTR_ERR(conf->done);
164 }
165
166 mgr = devm_fpga_mgr_create(&spi->dev,
167 "Xilinx Slave Serial FPGA Manager",
168 &xilinx_spi_ops, conf);
169 if (!mgr)
170 return -ENOMEM;
171
172 spi_set_drvdata(spi, mgr);
173
174 return fpga_mgr_register(mgr);
175}
176
177static int xilinx_spi_remove(struct spi_device *spi)
178{
179 struct fpga_manager *mgr = spi_get_drvdata(spi);
180
181 fpga_mgr_unregister(mgr);
182
183 return 0;
184}
185
186static const struct of_device_id xlnx_spi_of_match[] = {
187 { .compatible = "xlnx,fpga-slave-serial", },
188 {}
189};
190MODULE_DEVICE_TABLE(of, xlnx_spi_of_match);
191
192static struct spi_driver xilinx_slave_spi_driver = {
193 .driver = {
194 .name = "xlnx-slave-spi",
195 .of_match_table = of_match_ptr(xlnx_spi_of_match),
196 },
197 .probe = xilinx_spi_probe,
198 .remove = xilinx_spi_remove,
199};
200
201module_spi_driver(xilinx_slave_spi_driver)
202
203MODULE_LICENSE("GPL v2");
204MODULE_AUTHOR("Anatolij Gustschin <agust@denx.de>");
205MODULE_DESCRIPTION("Load Xilinx FPGA firmware over SPI");