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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Xilinx Spartan6 and 7 Series Slave Serial SPI Driver
4 *
5 * Copyright (C) 2017 DENX Software Engineering
6 *
7 * Anatolij Gustschin <agust@denx.de>
8 *
9 * Manage Xilinx FPGA firmware that is loaded over SPI using
10 * the slave serial configuration interface.
11 */
12
13#include <linux/delay.h>
14#include <linux/device.h>
15#include <linux/fpga/fpga-mgr.h>
16#include <linux/gpio/consumer.h>
17#include <linux/module.h>
18#include <linux/mod_devicetable.h>
19#include <linux/of.h>
20#include <linux/spi/spi.h>
21#include <linux/sizes.h>
22
23struct xilinx_spi_conf {
24 struct spi_device *spi;
25 struct gpio_desc *prog_b;
26 struct gpio_desc *init_b;
27 struct gpio_desc *done;
28};
29
30static enum fpga_mgr_states xilinx_spi_state(struct fpga_manager *mgr)
31{
32 struct xilinx_spi_conf *conf = mgr->priv;
33
34 if (!gpiod_get_value(conf->done))
35 return FPGA_MGR_STATE_RESET;
36
37 return FPGA_MGR_STATE_UNKNOWN;
38}
39
40/**
41 * wait_for_init_b - wait for the INIT_B pin to have a given state, or wait
42 * a given delay if the pin is unavailable
43 *
44 * @mgr: The FPGA manager object
45 * @value: Value INIT_B to wait for (1 = asserted = low)
46 * @alt_udelay: Delay to wait if the INIT_B GPIO is not available
47 *
48 * Returns 0 when the INIT_B GPIO reached the given state or -ETIMEDOUT if
49 * too much time passed waiting for that. If no INIT_B GPIO is available
50 * then always return 0.
51 */
52static int wait_for_init_b(struct fpga_manager *mgr, int value,
53 unsigned long alt_udelay)
54{
55 struct xilinx_spi_conf *conf = mgr->priv;
56 unsigned long timeout = jiffies + msecs_to_jiffies(1000);
57
58 if (conf->init_b) {
59 while (time_before(jiffies, timeout)) {
60 /* dump_state(conf, "wait for init_d .."); */
61 if (gpiod_get_value(conf->init_b) == value)
62 return 0;
63 usleep_range(100, 400);
64 }
65 return -ETIMEDOUT;
66 }
67
68 udelay(alt_udelay);
69
70 return 0;
71}
72
73static int xilinx_spi_write_init(struct fpga_manager *mgr,
74 struct fpga_image_info *info,
75 const char *buf, size_t count)
76{
77 struct xilinx_spi_conf *conf = mgr->priv;
78 int err;
79
80 if (info->flags & FPGA_MGR_PARTIAL_RECONFIG) {
81 dev_err(&mgr->dev, "Partial reconfiguration not supported.\n");
82 return -EINVAL;
83 }
84
85 gpiod_set_value(conf->prog_b, 1);
86
87 err = wait_for_init_b(mgr, 1, 1); /* min is 500 ns */
88 if (err) {
89 dev_err(&mgr->dev, "INIT_B pin did not go low\n");
90 gpiod_set_value(conf->prog_b, 0);
91 return err;
92 }
93
94 gpiod_set_value(conf->prog_b, 0);
95
96 err = wait_for_init_b(mgr, 0, 0);
97 if (err) {
98 dev_err(&mgr->dev, "INIT_B pin did not go high\n");
99 return err;
100 }
101
102 if (gpiod_get_value(conf->done)) {
103 dev_err(&mgr->dev, "Unexpected DONE pin state...\n");
104 return -EIO;
105 }
106
107 /* program latency */
108 usleep_range(7500, 7600);
109 return 0;
110}
111
112static int xilinx_spi_write(struct fpga_manager *mgr, const char *buf,
113 size_t count)
114{
115 struct xilinx_spi_conf *conf = mgr->priv;
116 const char *fw_data = buf;
117 const char *fw_data_end = fw_data + count;
118
119 while (fw_data < fw_data_end) {
120 size_t remaining, stride;
121 int ret;
122
123 remaining = fw_data_end - fw_data;
124 stride = min_t(size_t, remaining, SZ_4K);
125
126 ret = spi_write(conf->spi, fw_data, stride);
127 if (ret) {
128 dev_err(&mgr->dev, "SPI error in firmware write: %d\n",
129 ret);
130 return ret;
131 }
132 fw_data += stride;
133 }
134
135 return 0;
136}
137
138static int xilinx_spi_apply_cclk_cycles(struct xilinx_spi_conf *conf)
139{
140 struct spi_device *spi = conf->spi;
141 const u8 din_data[1] = { 0xff };
142 int ret;
143
144 ret = spi_write(conf->spi, din_data, sizeof(din_data));
145 if (ret)
146 dev_err(&spi->dev, "applying CCLK cycles failed: %d\n", ret);
147
148 return ret;
149}
150
151static int xilinx_spi_write_complete(struct fpga_manager *mgr,
152 struct fpga_image_info *info)
153{
154 struct xilinx_spi_conf *conf = mgr->priv;
155 unsigned long timeout;
156 int ret;
157
158 if (gpiod_get_value(conf->done))
159 return xilinx_spi_apply_cclk_cycles(conf);
160
161 timeout = jiffies + usecs_to_jiffies(info->config_complete_timeout_us);
162
163 while (time_before(jiffies, timeout)) {
164
165 ret = xilinx_spi_apply_cclk_cycles(conf);
166 if (ret)
167 return ret;
168
169 if (gpiod_get_value(conf->done))
170 return xilinx_spi_apply_cclk_cycles(conf);
171 }
172
173 dev_err(&mgr->dev, "Timeout after config data transfer.\n");
174 return -ETIMEDOUT;
175}
176
177static const struct fpga_manager_ops xilinx_spi_ops = {
178 .state = xilinx_spi_state,
179 .write_init = xilinx_spi_write_init,
180 .write = xilinx_spi_write,
181 .write_complete = xilinx_spi_write_complete,
182};
183
184static int xilinx_spi_probe(struct spi_device *spi)
185{
186 struct xilinx_spi_conf *conf;
187 struct fpga_manager *mgr;
188
189 conf = devm_kzalloc(&spi->dev, sizeof(*conf), GFP_KERNEL);
190 if (!conf)
191 return -ENOMEM;
192
193 conf->spi = spi;
194
195 /* PROGRAM_B is active low */
196 conf->prog_b = devm_gpiod_get(&spi->dev, "prog_b", GPIOD_OUT_LOW);
197 if (IS_ERR(conf->prog_b)) {
198 dev_err(&spi->dev, "Failed to get PROGRAM_B gpio: %ld\n",
199 PTR_ERR(conf->prog_b));
200 return PTR_ERR(conf->prog_b);
201 }
202
203 conf->init_b = devm_gpiod_get_optional(&spi->dev, "init-b", GPIOD_IN);
204 if (IS_ERR(conf->init_b)) {
205 dev_err(&spi->dev, "Failed to get INIT_B gpio: %ld\n",
206 PTR_ERR(conf->init_b));
207 return PTR_ERR(conf->init_b);
208 }
209
210 conf->done = devm_gpiod_get(&spi->dev, "done", GPIOD_IN);
211 if (IS_ERR(conf->done)) {
212 dev_err(&spi->dev, "Failed to get DONE gpio: %ld\n",
213 PTR_ERR(conf->done));
214 return PTR_ERR(conf->done);
215 }
216
217 mgr = devm_fpga_mgr_create(&spi->dev,
218 "Xilinx Slave Serial FPGA Manager",
219 &xilinx_spi_ops, conf);
220 if (!mgr)
221 return -ENOMEM;
222
223 spi_set_drvdata(spi, mgr);
224
225 return fpga_mgr_register(mgr);
226}
227
228static int xilinx_spi_remove(struct spi_device *spi)
229{
230 struct fpga_manager *mgr = spi_get_drvdata(spi);
231
232 fpga_mgr_unregister(mgr);
233
234 return 0;
235}
236
237static const struct of_device_id xlnx_spi_of_match[] = {
238 { .compatible = "xlnx,fpga-slave-serial", },
239 {}
240};
241MODULE_DEVICE_TABLE(of, xlnx_spi_of_match);
242
243static struct spi_driver xilinx_slave_spi_driver = {
244 .driver = {
245 .name = "xlnx-slave-spi",
246 .of_match_table = of_match_ptr(xlnx_spi_of_match),
247 },
248 .probe = xilinx_spi_probe,
249 .remove = xilinx_spi_remove,
250};
251
252module_spi_driver(xilinx_slave_spi_driver)
253
254MODULE_LICENSE("GPL v2");
255MODULE_AUTHOR("Anatolij Gustschin <agust@denx.de>");
256MODULE_DESCRIPTION("Load Xilinx FPGA firmware over SPI");
1/*
2 * Xilinx Spartan6 Slave Serial SPI Driver
3 *
4 * Copyright (C) 2017 DENX Software Engineering
5 *
6 * Anatolij Gustschin <agust@denx.de>
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms and conditions of the GNU General Public License,
10 * version 2, as published by the Free Software Foundation.
11 *
12 * Manage Xilinx FPGA firmware that is loaded over SPI using
13 * the slave serial configuration interface.
14 */
15
16#include <linux/delay.h>
17#include <linux/device.h>
18#include <linux/fpga/fpga-mgr.h>
19#include <linux/gpio/consumer.h>
20#include <linux/module.h>
21#include <linux/mod_devicetable.h>
22#include <linux/of.h>
23#include <linux/spi/spi.h>
24#include <linux/sizes.h>
25
26struct xilinx_spi_conf {
27 struct spi_device *spi;
28 struct gpio_desc *prog_b;
29 struct gpio_desc *done;
30};
31
32static enum fpga_mgr_states xilinx_spi_state(struct fpga_manager *mgr)
33{
34 struct xilinx_spi_conf *conf = mgr->priv;
35
36 if (!gpiod_get_value(conf->done))
37 return FPGA_MGR_STATE_RESET;
38
39 return FPGA_MGR_STATE_UNKNOWN;
40}
41
42static int xilinx_spi_write_init(struct fpga_manager *mgr,
43 struct fpga_image_info *info,
44 const char *buf, size_t count)
45{
46 struct xilinx_spi_conf *conf = mgr->priv;
47 const size_t prog_latency_7500us = 7500;
48 const size_t prog_pulse_1us = 1;
49
50 if (info->flags & FPGA_MGR_PARTIAL_RECONFIG) {
51 dev_err(&mgr->dev, "Partial reconfiguration not supported.\n");
52 return -EINVAL;
53 }
54
55 gpiod_set_value(conf->prog_b, 1);
56
57 udelay(prog_pulse_1us); /* min is 500 ns */
58
59 gpiod_set_value(conf->prog_b, 0);
60
61 if (gpiod_get_value(conf->done)) {
62 dev_err(&mgr->dev, "Unexpected DONE pin state...\n");
63 return -EIO;
64 }
65
66 /* program latency */
67 usleep_range(prog_latency_7500us, prog_latency_7500us + 100);
68 return 0;
69}
70
71static int xilinx_spi_write(struct fpga_manager *mgr, const char *buf,
72 size_t count)
73{
74 struct xilinx_spi_conf *conf = mgr->priv;
75 const char *fw_data = buf;
76 const char *fw_data_end = fw_data + count;
77
78 while (fw_data < fw_data_end) {
79 size_t remaining, stride;
80 int ret;
81
82 remaining = fw_data_end - fw_data;
83 stride = min_t(size_t, remaining, SZ_4K);
84
85 ret = spi_write(conf->spi, fw_data, stride);
86 if (ret) {
87 dev_err(&mgr->dev, "SPI error in firmware write: %d\n",
88 ret);
89 return ret;
90 }
91 fw_data += stride;
92 }
93
94 return 0;
95}
96
97static int xilinx_spi_apply_cclk_cycles(struct xilinx_spi_conf *conf)
98{
99 struct spi_device *spi = conf->spi;
100 const u8 din_data[1] = { 0xff };
101 int ret;
102
103 ret = spi_write(conf->spi, din_data, sizeof(din_data));
104 if (ret)
105 dev_err(&spi->dev, "applying CCLK cycles failed: %d\n", ret);
106
107 return ret;
108}
109
110static int xilinx_spi_write_complete(struct fpga_manager *mgr,
111 struct fpga_image_info *info)
112{
113 struct xilinx_spi_conf *conf = mgr->priv;
114 unsigned long timeout;
115 int ret;
116
117 if (gpiod_get_value(conf->done))
118 return xilinx_spi_apply_cclk_cycles(conf);
119
120 timeout = jiffies + usecs_to_jiffies(info->config_complete_timeout_us);
121
122 while (time_before(jiffies, timeout)) {
123
124 ret = xilinx_spi_apply_cclk_cycles(conf);
125 if (ret)
126 return ret;
127
128 if (gpiod_get_value(conf->done))
129 return xilinx_spi_apply_cclk_cycles(conf);
130 }
131
132 dev_err(&mgr->dev, "Timeout after config data transfer.\n");
133 return -ETIMEDOUT;
134}
135
136static const struct fpga_manager_ops xilinx_spi_ops = {
137 .state = xilinx_spi_state,
138 .write_init = xilinx_spi_write_init,
139 .write = xilinx_spi_write,
140 .write_complete = xilinx_spi_write_complete,
141};
142
143static int xilinx_spi_probe(struct spi_device *spi)
144{
145 struct xilinx_spi_conf *conf;
146
147 conf = devm_kzalloc(&spi->dev, sizeof(*conf), GFP_KERNEL);
148 if (!conf)
149 return -ENOMEM;
150
151 conf->spi = spi;
152
153 /* PROGRAM_B is active low */
154 conf->prog_b = devm_gpiod_get(&spi->dev, "prog_b", GPIOD_OUT_LOW);
155 if (IS_ERR(conf->prog_b)) {
156 dev_err(&spi->dev, "Failed to get PROGRAM_B gpio: %ld\n",
157 PTR_ERR(conf->prog_b));
158 return PTR_ERR(conf->prog_b);
159 }
160
161 conf->done = devm_gpiod_get(&spi->dev, "done", GPIOD_IN);
162 if (IS_ERR(conf->done)) {
163 dev_err(&spi->dev, "Failed to get DONE gpio: %ld\n",
164 PTR_ERR(conf->done));
165 return PTR_ERR(conf->done);
166 }
167
168 return fpga_mgr_register(&spi->dev, "Xilinx Slave Serial FPGA Manager",
169 &xilinx_spi_ops, conf);
170}
171
172static int xilinx_spi_remove(struct spi_device *spi)
173{
174 fpga_mgr_unregister(&spi->dev);
175
176 return 0;
177}
178
179static const struct of_device_id xlnx_spi_of_match[] = {
180 { .compatible = "xlnx,fpga-slave-serial", },
181 {}
182};
183MODULE_DEVICE_TABLE(of, xlnx_spi_of_match);
184
185static struct spi_driver xilinx_slave_spi_driver = {
186 .driver = {
187 .name = "xlnx-slave-spi",
188 .of_match_table = of_match_ptr(xlnx_spi_of_match),
189 },
190 .probe = xilinx_spi_probe,
191 .remove = xilinx_spi_remove,
192};
193
194module_spi_driver(xilinx_slave_spi_driver)
195
196MODULE_LICENSE("GPL v2");
197MODULE_AUTHOR("Anatolij Gustschin <agust@denx.de>");
198MODULE_DESCRIPTION("Load Xilinx FPGA firmware over SPI");