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1// SPDX-License-Identifier: GPL-2.0-only
2#include <linux/init.h>
3
4#include <linux/mm.h>
5#include <linux/spinlock.h>
6#include <linux/smp.h>
7#include <linux/interrupt.h>
8#include <linux/export.h>
9#include <linux/cpu.h>
10#include <linux/debugfs.h>
11
12#include <asm/tlbflush.h>
13#include <asm/mmu_context.h>
14#include <asm/nospec-branch.h>
15#include <asm/cache.h>
16#include <asm/apic.h>
17#include <asm/uv/uv.h>
18
19#include "mm_internal.h"
20
21#ifdef CONFIG_PARAVIRT
22# define STATIC_NOPV
23#else
24# define STATIC_NOPV static
25# define __flush_tlb_local native_flush_tlb_local
26# define __flush_tlb_global native_flush_tlb_global
27# define __flush_tlb_one_user(addr) native_flush_tlb_one_user(addr)
28# define __flush_tlb_others(msk, info) native_flush_tlb_others(msk, info)
29#endif
30
31/*
32 * TLB flushing, formerly SMP-only
33 * c/o Linus Torvalds.
34 *
35 * These mean you can really definitely utterly forget about
36 * writing to user space from interrupts. (Its not allowed anyway).
37 *
38 * Optimizations Manfred Spraul <manfred@colorfullife.com>
39 *
40 * More scalable flush, from Andi Kleen
41 *
42 * Implement flush IPI by CALL_FUNCTION_VECTOR, Alex Shi
43 */
44
45/*
46 * Use bit 0 to mangle the TIF_SPEC_IB state into the mm pointer which is
47 * stored in cpu_tlb_state.last_user_mm_ibpb.
48 */
49#define LAST_USER_MM_IBPB 0x1UL
50
51/*
52 * The x86 feature is called PCID (Process Context IDentifier). It is similar
53 * to what is traditionally called ASID on the RISC processors.
54 *
55 * We don't use the traditional ASID implementation, where each process/mm gets
56 * its own ASID and flush/restart when we run out of ASID space.
57 *
58 * Instead we have a small per-cpu array of ASIDs and cache the last few mm's
59 * that came by on this CPU, allowing cheaper switch_mm between processes on
60 * this CPU.
61 *
62 * We end up with different spaces for different things. To avoid confusion we
63 * use different names for each of them:
64 *
65 * ASID - [0, TLB_NR_DYN_ASIDS-1]
66 * the canonical identifier for an mm
67 *
68 * kPCID - [1, TLB_NR_DYN_ASIDS]
69 * the value we write into the PCID part of CR3; corresponds to the
70 * ASID+1, because PCID 0 is special.
71 *
72 * uPCID - [2048 + 1, 2048 + TLB_NR_DYN_ASIDS]
73 * for KPTI each mm has two address spaces and thus needs two
74 * PCID values, but we can still do with a single ASID denomination
75 * for each mm. Corresponds to kPCID + 2048.
76 *
77 */
78
79/* There are 12 bits of space for ASIDS in CR3 */
80#define CR3_HW_ASID_BITS 12
81
82/*
83 * When enabled, PAGE_TABLE_ISOLATION consumes a single bit for
84 * user/kernel switches
85 */
86#ifdef CONFIG_PAGE_TABLE_ISOLATION
87# define PTI_CONSUMED_PCID_BITS 1
88#else
89# define PTI_CONSUMED_PCID_BITS 0
90#endif
91
92#define CR3_AVAIL_PCID_BITS (X86_CR3_PCID_BITS - PTI_CONSUMED_PCID_BITS)
93
94/*
95 * ASIDs are zero-based: 0->MAX_AVAIL_ASID are valid. -1 below to account
96 * for them being zero-based. Another -1 is because PCID 0 is reserved for
97 * use by non-PCID-aware users.
98 */
99#define MAX_ASID_AVAILABLE ((1 << CR3_AVAIL_PCID_BITS) - 2)
100
101/*
102 * Given @asid, compute kPCID
103 */
104static inline u16 kern_pcid(u16 asid)
105{
106 VM_WARN_ON_ONCE(asid > MAX_ASID_AVAILABLE);
107
108#ifdef CONFIG_PAGE_TABLE_ISOLATION
109 /*
110 * Make sure that the dynamic ASID space does not confict with the
111 * bit we are using to switch between user and kernel ASIDs.
112 */
113 BUILD_BUG_ON(TLB_NR_DYN_ASIDS >= (1 << X86_CR3_PTI_PCID_USER_BIT));
114
115 /*
116 * The ASID being passed in here should have respected the
117 * MAX_ASID_AVAILABLE and thus never have the switch bit set.
118 */
119 VM_WARN_ON_ONCE(asid & (1 << X86_CR3_PTI_PCID_USER_BIT));
120#endif
121 /*
122 * The dynamically-assigned ASIDs that get passed in are small
123 * (<TLB_NR_DYN_ASIDS). They never have the high switch bit set,
124 * so do not bother to clear it.
125 *
126 * If PCID is on, ASID-aware code paths put the ASID+1 into the
127 * PCID bits. This serves two purposes. It prevents a nasty
128 * situation in which PCID-unaware code saves CR3, loads some other
129 * value (with PCID == 0), and then restores CR3, thus corrupting
130 * the TLB for ASID 0 if the saved ASID was nonzero. It also means
131 * that any bugs involving loading a PCID-enabled CR3 with
132 * CR4.PCIDE off will trigger deterministically.
133 */
134 return asid + 1;
135}
136
137/*
138 * Given @asid, compute uPCID
139 */
140static inline u16 user_pcid(u16 asid)
141{
142 u16 ret = kern_pcid(asid);
143#ifdef CONFIG_PAGE_TABLE_ISOLATION
144 ret |= 1 << X86_CR3_PTI_PCID_USER_BIT;
145#endif
146 return ret;
147}
148
149static inline unsigned long build_cr3(pgd_t *pgd, u16 asid)
150{
151 if (static_cpu_has(X86_FEATURE_PCID)) {
152 return __sme_pa(pgd) | kern_pcid(asid);
153 } else {
154 VM_WARN_ON_ONCE(asid != 0);
155 return __sme_pa(pgd);
156 }
157}
158
159static inline unsigned long build_cr3_noflush(pgd_t *pgd, u16 asid)
160{
161 VM_WARN_ON_ONCE(asid > MAX_ASID_AVAILABLE);
162 /*
163 * Use boot_cpu_has() instead of this_cpu_has() as this function
164 * might be called during early boot. This should work even after
165 * boot because all CPU's the have same capabilities:
166 */
167 VM_WARN_ON_ONCE(!boot_cpu_has(X86_FEATURE_PCID));
168 return __sme_pa(pgd) | kern_pcid(asid) | CR3_NOFLUSH;
169}
170
171/*
172 * We get here when we do something requiring a TLB invalidation
173 * but could not go invalidate all of the contexts. We do the
174 * necessary invalidation by clearing out the 'ctx_id' which
175 * forces a TLB flush when the context is loaded.
176 */
177static void clear_asid_other(void)
178{
179 u16 asid;
180
181 /*
182 * This is only expected to be set if we have disabled
183 * kernel _PAGE_GLOBAL pages.
184 */
185 if (!static_cpu_has(X86_FEATURE_PTI)) {
186 WARN_ON_ONCE(1);
187 return;
188 }
189
190 for (asid = 0; asid < TLB_NR_DYN_ASIDS; asid++) {
191 /* Do not need to flush the current asid */
192 if (asid == this_cpu_read(cpu_tlbstate.loaded_mm_asid))
193 continue;
194 /*
195 * Make sure the next time we go to switch to
196 * this asid, we do a flush:
197 */
198 this_cpu_write(cpu_tlbstate.ctxs[asid].ctx_id, 0);
199 }
200 this_cpu_write(cpu_tlbstate.invalidate_other, false);
201}
202
203atomic64_t last_mm_ctx_id = ATOMIC64_INIT(1);
204
205
206static void choose_new_asid(struct mm_struct *next, u64 next_tlb_gen,
207 u16 *new_asid, bool *need_flush)
208{
209 u16 asid;
210
211 if (!static_cpu_has(X86_FEATURE_PCID)) {
212 *new_asid = 0;
213 *need_flush = true;
214 return;
215 }
216
217 if (this_cpu_read(cpu_tlbstate.invalidate_other))
218 clear_asid_other();
219
220 for (asid = 0; asid < TLB_NR_DYN_ASIDS; asid++) {
221 if (this_cpu_read(cpu_tlbstate.ctxs[asid].ctx_id) !=
222 next->context.ctx_id)
223 continue;
224
225 *new_asid = asid;
226 *need_flush = (this_cpu_read(cpu_tlbstate.ctxs[asid].tlb_gen) <
227 next_tlb_gen);
228 return;
229 }
230
231 /*
232 * We don't currently own an ASID slot on this CPU.
233 * Allocate a slot.
234 */
235 *new_asid = this_cpu_add_return(cpu_tlbstate.next_asid, 1) - 1;
236 if (*new_asid >= TLB_NR_DYN_ASIDS) {
237 *new_asid = 0;
238 this_cpu_write(cpu_tlbstate.next_asid, 1);
239 }
240 *need_flush = true;
241}
242
243/*
244 * Given an ASID, flush the corresponding user ASID. We can delay this
245 * until the next time we switch to it.
246 *
247 * See SWITCH_TO_USER_CR3.
248 */
249static inline void invalidate_user_asid(u16 asid)
250{
251 /* There is no user ASID if address space separation is off */
252 if (!IS_ENABLED(CONFIG_PAGE_TABLE_ISOLATION))
253 return;
254
255 /*
256 * We only have a single ASID if PCID is off and the CR3
257 * write will have flushed it.
258 */
259 if (!cpu_feature_enabled(X86_FEATURE_PCID))
260 return;
261
262 if (!static_cpu_has(X86_FEATURE_PTI))
263 return;
264
265 __set_bit(kern_pcid(asid),
266 (unsigned long *)this_cpu_ptr(&cpu_tlbstate.user_pcid_flush_mask));
267}
268
269static void load_new_mm_cr3(pgd_t *pgdir, u16 new_asid, bool need_flush)
270{
271 unsigned long new_mm_cr3;
272
273 if (need_flush) {
274 invalidate_user_asid(new_asid);
275 new_mm_cr3 = build_cr3(pgdir, new_asid);
276 } else {
277 new_mm_cr3 = build_cr3_noflush(pgdir, new_asid);
278 }
279
280 /*
281 * Caution: many callers of this function expect
282 * that load_cr3() is serializing and orders TLB
283 * fills with respect to the mm_cpumask writes.
284 */
285 write_cr3(new_mm_cr3);
286}
287
288void leave_mm(int cpu)
289{
290 struct mm_struct *loaded_mm = this_cpu_read(cpu_tlbstate.loaded_mm);
291
292 /*
293 * It's plausible that we're in lazy TLB mode while our mm is init_mm.
294 * If so, our callers still expect us to flush the TLB, but there
295 * aren't any user TLB entries in init_mm to worry about.
296 *
297 * This needs to happen before any other sanity checks due to
298 * intel_idle's shenanigans.
299 */
300 if (loaded_mm == &init_mm)
301 return;
302
303 /* Warn if we're not lazy. */
304 WARN_ON(!this_cpu_read(cpu_tlbstate.is_lazy));
305
306 switch_mm(NULL, &init_mm, NULL);
307}
308EXPORT_SYMBOL_GPL(leave_mm);
309
310void switch_mm(struct mm_struct *prev, struct mm_struct *next,
311 struct task_struct *tsk)
312{
313 unsigned long flags;
314
315 local_irq_save(flags);
316 switch_mm_irqs_off(prev, next, tsk);
317 local_irq_restore(flags);
318}
319
320static inline unsigned long mm_mangle_tif_spec_ib(struct task_struct *next)
321{
322 unsigned long next_tif = task_thread_info(next)->flags;
323 unsigned long ibpb = (next_tif >> TIF_SPEC_IB) & LAST_USER_MM_IBPB;
324
325 return (unsigned long)next->mm | ibpb;
326}
327
328static void cond_ibpb(struct task_struct *next)
329{
330 if (!next || !next->mm)
331 return;
332
333 /*
334 * Both, the conditional and the always IBPB mode use the mm
335 * pointer to avoid the IBPB when switching between tasks of the
336 * same process. Using the mm pointer instead of mm->context.ctx_id
337 * opens a hypothetical hole vs. mm_struct reuse, which is more or
338 * less impossible to control by an attacker. Aside of that it
339 * would only affect the first schedule so the theoretically
340 * exposed data is not really interesting.
341 */
342 if (static_branch_likely(&switch_mm_cond_ibpb)) {
343 unsigned long prev_mm, next_mm;
344
345 /*
346 * This is a bit more complex than the always mode because
347 * it has to handle two cases:
348 *
349 * 1) Switch from a user space task (potential attacker)
350 * which has TIF_SPEC_IB set to a user space task
351 * (potential victim) which has TIF_SPEC_IB not set.
352 *
353 * 2) Switch from a user space task (potential attacker)
354 * which has TIF_SPEC_IB not set to a user space task
355 * (potential victim) which has TIF_SPEC_IB set.
356 *
357 * This could be done by unconditionally issuing IBPB when
358 * a task which has TIF_SPEC_IB set is either scheduled in
359 * or out. Though that results in two flushes when:
360 *
361 * - the same user space task is scheduled out and later
362 * scheduled in again and only a kernel thread ran in
363 * between.
364 *
365 * - a user space task belonging to the same process is
366 * scheduled in after a kernel thread ran in between
367 *
368 * - a user space task belonging to the same process is
369 * scheduled in immediately.
370 *
371 * Optimize this with reasonably small overhead for the
372 * above cases. Mangle the TIF_SPEC_IB bit into the mm
373 * pointer of the incoming task which is stored in
374 * cpu_tlbstate.last_user_mm_ibpb for comparison.
375 */
376 next_mm = mm_mangle_tif_spec_ib(next);
377 prev_mm = this_cpu_read(cpu_tlbstate.last_user_mm_ibpb);
378
379 /*
380 * Issue IBPB only if the mm's are different and one or
381 * both have the IBPB bit set.
382 */
383 if (next_mm != prev_mm &&
384 (next_mm | prev_mm) & LAST_USER_MM_IBPB)
385 indirect_branch_prediction_barrier();
386
387 this_cpu_write(cpu_tlbstate.last_user_mm_ibpb, next_mm);
388 }
389
390 if (static_branch_unlikely(&switch_mm_always_ibpb)) {
391 /*
392 * Only flush when switching to a user space task with a
393 * different context than the user space task which ran
394 * last on this CPU.
395 */
396 if (this_cpu_read(cpu_tlbstate.last_user_mm) != next->mm) {
397 indirect_branch_prediction_barrier();
398 this_cpu_write(cpu_tlbstate.last_user_mm, next->mm);
399 }
400 }
401}
402
403#ifdef CONFIG_PERF_EVENTS
404static inline void cr4_update_pce_mm(struct mm_struct *mm)
405{
406 if (static_branch_unlikely(&rdpmc_always_available_key) ||
407 (!static_branch_unlikely(&rdpmc_never_available_key) &&
408 atomic_read(&mm->context.perf_rdpmc_allowed)))
409 cr4_set_bits_irqsoff(X86_CR4_PCE);
410 else
411 cr4_clear_bits_irqsoff(X86_CR4_PCE);
412}
413
414void cr4_update_pce(void *ignored)
415{
416 cr4_update_pce_mm(this_cpu_read(cpu_tlbstate.loaded_mm));
417}
418
419#else
420static inline void cr4_update_pce_mm(struct mm_struct *mm) { }
421#endif
422
423void switch_mm_irqs_off(struct mm_struct *prev, struct mm_struct *next,
424 struct task_struct *tsk)
425{
426 struct mm_struct *real_prev = this_cpu_read(cpu_tlbstate.loaded_mm);
427 u16 prev_asid = this_cpu_read(cpu_tlbstate.loaded_mm_asid);
428 bool was_lazy = this_cpu_read(cpu_tlbstate.is_lazy);
429 unsigned cpu = smp_processor_id();
430 u64 next_tlb_gen;
431 bool need_flush;
432 u16 new_asid;
433
434 /*
435 * NB: The scheduler will call us with prev == next when switching
436 * from lazy TLB mode to normal mode if active_mm isn't changing.
437 * When this happens, we don't assume that CR3 (and hence
438 * cpu_tlbstate.loaded_mm) matches next.
439 *
440 * NB: leave_mm() calls us with prev == NULL and tsk == NULL.
441 */
442
443 /* We don't want flush_tlb_func_* to run concurrently with us. */
444 if (IS_ENABLED(CONFIG_PROVE_LOCKING))
445 WARN_ON_ONCE(!irqs_disabled());
446
447 /*
448 * Verify that CR3 is what we think it is. This will catch
449 * hypothetical buggy code that directly switches to swapper_pg_dir
450 * without going through leave_mm() / switch_mm_irqs_off() or that
451 * does something like write_cr3(read_cr3_pa()).
452 *
453 * Only do this check if CONFIG_DEBUG_VM=y because __read_cr3()
454 * isn't free.
455 */
456#ifdef CONFIG_DEBUG_VM
457 if (WARN_ON_ONCE(__read_cr3() != build_cr3(real_prev->pgd, prev_asid))) {
458 /*
459 * If we were to BUG here, we'd be very likely to kill
460 * the system so hard that we don't see the call trace.
461 * Try to recover instead by ignoring the error and doing
462 * a global flush to minimize the chance of corruption.
463 *
464 * (This is far from being a fully correct recovery.
465 * Architecturally, the CPU could prefetch something
466 * back into an incorrect ASID slot and leave it there
467 * to cause trouble down the road. It's better than
468 * nothing, though.)
469 */
470 __flush_tlb_all();
471 }
472#endif
473 this_cpu_write(cpu_tlbstate.is_lazy, false);
474
475 /*
476 * The membarrier system call requires a full memory barrier and
477 * core serialization before returning to user-space, after
478 * storing to rq->curr. Writing to CR3 provides that full
479 * memory barrier and core serializing instruction.
480 */
481 if (real_prev == next) {
482 VM_WARN_ON(this_cpu_read(cpu_tlbstate.ctxs[prev_asid].ctx_id) !=
483 next->context.ctx_id);
484
485 /*
486 * Even in lazy TLB mode, the CPU should stay set in the
487 * mm_cpumask. The TLB shootdown code can figure out from
488 * from cpu_tlbstate.is_lazy whether or not to send an IPI.
489 */
490 if (WARN_ON_ONCE(real_prev != &init_mm &&
491 !cpumask_test_cpu(cpu, mm_cpumask(next))))
492 cpumask_set_cpu(cpu, mm_cpumask(next));
493
494 /*
495 * If the CPU is not in lazy TLB mode, we are just switching
496 * from one thread in a process to another thread in the same
497 * process. No TLB flush required.
498 */
499 if (!was_lazy)
500 return;
501
502 /*
503 * Read the tlb_gen to check whether a flush is needed.
504 * If the TLB is up to date, just use it.
505 * The barrier synchronizes with the tlb_gen increment in
506 * the TLB shootdown code.
507 */
508 smp_mb();
509 next_tlb_gen = atomic64_read(&next->context.tlb_gen);
510 if (this_cpu_read(cpu_tlbstate.ctxs[prev_asid].tlb_gen) ==
511 next_tlb_gen)
512 return;
513
514 /*
515 * TLB contents went out of date while we were in lazy
516 * mode. Fall through to the TLB switching code below.
517 */
518 new_asid = prev_asid;
519 need_flush = true;
520 } else {
521 /*
522 * Avoid user/user BTB poisoning by flushing the branch
523 * predictor when switching between processes. This stops
524 * one process from doing Spectre-v2 attacks on another.
525 */
526 cond_ibpb(tsk);
527
528 /*
529 * Stop remote flushes for the previous mm.
530 * Skip kernel threads; we never send init_mm TLB flushing IPIs,
531 * but the bitmap manipulation can cause cache line contention.
532 */
533 if (real_prev != &init_mm) {
534 VM_WARN_ON_ONCE(!cpumask_test_cpu(cpu,
535 mm_cpumask(real_prev)));
536 cpumask_clear_cpu(cpu, mm_cpumask(real_prev));
537 }
538
539 /*
540 * Start remote flushes and then read tlb_gen.
541 */
542 if (next != &init_mm)
543 cpumask_set_cpu(cpu, mm_cpumask(next));
544 next_tlb_gen = atomic64_read(&next->context.tlb_gen);
545
546 choose_new_asid(next, next_tlb_gen, &new_asid, &need_flush);
547
548 /* Let nmi_uaccess_okay() know that we're changing CR3. */
549 this_cpu_write(cpu_tlbstate.loaded_mm, LOADED_MM_SWITCHING);
550 barrier();
551 }
552
553 if (need_flush) {
554 this_cpu_write(cpu_tlbstate.ctxs[new_asid].ctx_id, next->context.ctx_id);
555 this_cpu_write(cpu_tlbstate.ctxs[new_asid].tlb_gen, next_tlb_gen);
556 load_new_mm_cr3(next->pgd, new_asid, true);
557
558 trace_tlb_flush(TLB_FLUSH_ON_TASK_SWITCH, TLB_FLUSH_ALL);
559 } else {
560 /* The new ASID is already up to date. */
561 load_new_mm_cr3(next->pgd, new_asid, false);
562
563 trace_tlb_flush(TLB_FLUSH_ON_TASK_SWITCH, 0);
564 }
565
566 /* Make sure we write CR3 before loaded_mm. */
567 barrier();
568
569 this_cpu_write(cpu_tlbstate.loaded_mm, next);
570 this_cpu_write(cpu_tlbstate.loaded_mm_asid, new_asid);
571
572 if (next != real_prev) {
573 cr4_update_pce_mm(next);
574 switch_ldt(real_prev, next);
575 }
576}
577
578/*
579 * Please ignore the name of this function. It should be called
580 * switch_to_kernel_thread().
581 *
582 * enter_lazy_tlb() is a hint from the scheduler that we are entering a
583 * kernel thread or other context without an mm. Acceptable implementations
584 * include doing nothing whatsoever, switching to init_mm, or various clever
585 * lazy tricks to try to minimize TLB flushes.
586 *
587 * The scheduler reserves the right to call enter_lazy_tlb() several times
588 * in a row. It will notify us that we're going back to a real mm by
589 * calling switch_mm_irqs_off().
590 */
591void enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk)
592{
593 if (this_cpu_read(cpu_tlbstate.loaded_mm) == &init_mm)
594 return;
595
596 this_cpu_write(cpu_tlbstate.is_lazy, true);
597}
598
599/*
600 * Call this when reinitializing a CPU. It fixes the following potential
601 * problems:
602 *
603 * - The ASID changed from what cpu_tlbstate thinks it is (most likely
604 * because the CPU was taken down and came back up with CR3's PCID
605 * bits clear. CPU hotplug can do this.
606 *
607 * - The TLB contains junk in slots corresponding to inactive ASIDs.
608 *
609 * - The CPU went so far out to lunch that it may have missed a TLB
610 * flush.
611 */
612void initialize_tlbstate_and_flush(void)
613{
614 int i;
615 struct mm_struct *mm = this_cpu_read(cpu_tlbstate.loaded_mm);
616 u64 tlb_gen = atomic64_read(&init_mm.context.tlb_gen);
617 unsigned long cr3 = __read_cr3();
618
619 /* Assert that CR3 already references the right mm. */
620 WARN_ON((cr3 & CR3_ADDR_MASK) != __pa(mm->pgd));
621
622 /*
623 * Assert that CR4.PCIDE is set if needed. (CR4.PCIDE initialization
624 * doesn't work like other CR4 bits because it can only be set from
625 * long mode.)
626 */
627 WARN_ON(boot_cpu_has(X86_FEATURE_PCID) &&
628 !(cr4_read_shadow() & X86_CR4_PCIDE));
629
630 /* Force ASID 0 and force a TLB flush. */
631 write_cr3(build_cr3(mm->pgd, 0));
632
633 /* Reinitialize tlbstate. */
634 this_cpu_write(cpu_tlbstate.last_user_mm_ibpb, LAST_USER_MM_IBPB);
635 this_cpu_write(cpu_tlbstate.loaded_mm_asid, 0);
636 this_cpu_write(cpu_tlbstate.next_asid, 1);
637 this_cpu_write(cpu_tlbstate.ctxs[0].ctx_id, mm->context.ctx_id);
638 this_cpu_write(cpu_tlbstate.ctxs[0].tlb_gen, tlb_gen);
639
640 for (i = 1; i < TLB_NR_DYN_ASIDS; i++)
641 this_cpu_write(cpu_tlbstate.ctxs[i].ctx_id, 0);
642}
643
644/*
645 * flush_tlb_func_common()'s memory ordering requirement is that any
646 * TLB fills that happen after we flush the TLB are ordered after we
647 * read active_mm's tlb_gen. We don't need any explicit barriers
648 * because all x86 flush operations are serializing and the
649 * atomic64_read operation won't be reordered by the compiler.
650 */
651static void flush_tlb_func_common(const struct flush_tlb_info *f,
652 bool local, enum tlb_flush_reason reason)
653{
654 /*
655 * We have three different tlb_gen values in here. They are:
656 *
657 * - mm_tlb_gen: the latest generation.
658 * - local_tlb_gen: the generation that this CPU has already caught
659 * up to.
660 * - f->new_tlb_gen: the generation that the requester of the flush
661 * wants us to catch up to.
662 */
663 struct mm_struct *loaded_mm = this_cpu_read(cpu_tlbstate.loaded_mm);
664 u32 loaded_mm_asid = this_cpu_read(cpu_tlbstate.loaded_mm_asid);
665 u64 mm_tlb_gen = atomic64_read(&loaded_mm->context.tlb_gen);
666 u64 local_tlb_gen = this_cpu_read(cpu_tlbstate.ctxs[loaded_mm_asid].tlb_gen);
667
668 /* This code cannot presently handle being reentered. */
669 VM_WARN_ON(!irqs_disabled());
670
671 if (unlikely(loaded_mm == &init_mm))
672 return;
673
674 VM_WARN_ON(this_cpu_read(cpu_tlbstate.ctxs[loaded_mm_asid].ctx_id) !=
675 loaded_mm->context.ctx_id);
676
677 if (this_cpu_read(cpu_tlbstate.is_lazy)) {
678 /*
679 * We're in lazy mode. We need to at least flush our
680 * paging-structure cache to avoid speculatively reading
681 * garbage into our TLB. Since switching to init_mm is barely
682 * slower than a minimal flush, just switch to init_mm.
683 *
684 * This should be rare, with native_flush_tlb_others skipping
685 * IPIs to lazy TLB mode CPUs.
686 */
687 switch_mm_irqs_off(NULL, &init_mm, NULL);
688 return;
689 }
690
691 if (unlikely(local_tlb_gen == mm_tlb_gen)) {
692 /*
693 * There's nothing to do: we're already up to date. This can
694 * happen if two concurrent flushes happen -- the first flush to
695 * be handled can catch us all the way up, leaving no work for
696 * the second flush.
697 */
698 trace_tlb_flush(reason, 0);
699 return;
700 }
701
702 WARN_ON_ONCE(local_tlb_gen > mm_tlb_gen);
703 WARN_ON_ONCE(f->new_tlb_gen > mm_tlb_gen);
704
705 /*
706 * If we get to this point, we know that our TLB is out of date.
707 * This does not strictly imply that we need to flush (it's
708 * possible that f->new_tlb_gen <= local_tlb_gen), but we're
709 * going to need to flush in the very near future, so we might
710 * as well get it over with.
711 *
712 * The only question is whether to do a full or partial flush.
713 *
714 * We do a partial flush if requested and two extra conditions
715 * are met:
716 *
717 * 1. f->new_tlb_gen == local_tlb_gen + 1. We have an invariant that
718 * we've always done all needed flushes to catch up to
719 * local_tlb_gen. If, for example, local_tlb_gen == 2 and
720 * f->new_tlb_gen == 3, then we know that the flush needed to bring
721 * us up to date for tlb_gen 3 is the partial flush we're
722 * processing.
723 *
724 * As an example of why this check is needed, suppose that there
725 * are two concurrent flushes. The first is a full flush that
726 * changes context.tlb_gen from 1 to 2. The second is a partial
727 * flush that changes context.tlb_gen from 2 to 3. If they get
728 * processed on this CPU in reverse order, we'll see
729 * local_tlb_gen == 1, mm_tlb_gen == 3, and end != TLB_FLUSH_ALL.
730 * If we were to use __flush_tlb_one_user() and set local_tlb_gen to
731 * 3, we'd be break the invariant: we'd update local_tlb_gen above
732 * 1 without the full flush that's needed for tlb_gen 2.
733 *
734 * 2. f->new_tlb_gen == mm_tlb_gen. This is purely an optimiation.
735 * Partial TLB flushes are not all that much cheaper than full TLB
736 * flushes, so it seems unlikely that it would be a performance win
737 * to do a partial flush if that won't bring our TLB fully up to
738 * date. By doing a full flush instead, we can increase
739 * local_tlb_gen all the way to mm_tlb_gen and we can probably
740 * avoid another flush in the very near future.
741 */
742 if (f->end != TLB_FLUSH_ALL &&
743 f->new_tlb_gen == local_tlb_gen + 1 &&
744 f->new_tlb_gen == mm_tlb_gen) {
745 /* Partial flush */
746 unsigned long nr_invalidate = (f->end - f->start) >> f->stride_shift;
747 unsigned long addr = f->start;
748
749 while (addr < f->end) {
750 flush_tlb_one_user(addr);
751 addr += 1UL << f->stride_shift;
752 }
753 if (local)
754 count_vm_tlb_events(NR_TLB_LOCAL_FLUSH_ONE, nr_invalidate);
755 trace_tlb_flush(reason, nr_invalidate);
756 } else {
757 /* Full flush. */
758 flush_tlb_local();
759 if (local)
760 count_vm_tlb_event(NR_TLB_LOCAL_FLUSH_ALL);
761 trace_tlb_flush(reason, TLB_FLUSH_ALL);
762 }
763
764 /* Both paths above update our state to mm_tlb_gen. */
765 this_cpu_write(cpu_tlbstate.ctxs[loaded_mm_asid].tlb_gen, mm_tlb_gen);
766}
767
768static void flush_tlb_func_local(const void *info, enum tlb_flush_reason reason)
769{
770 const struct flush_tlb_info *f = info;
771
772 flush_tlb_func_common(f, true, reason);
773}
774
775static void flush_tlb_func_remote(void *info)
776{
777 const struct flush_tlb_info *f = info;
778
779 inc_irq_stat(irq_tlb_count);
780
781 if (f->mm && f->mm != this_cpu_read(cpu_tlbstate.loaded_mm))
782 return;
783
784 count_vm_tlb_event(NR_TLB_REMOTE_FLUSH_RECEIVED);
785 flush_tlb_func_common(f, false, TLB_REMOTE_SHOOTDOWN);
786}
787
788static bool tlb_is_not_lazy(int cpu, void *data)
789{
790 return !per_cpu(cpu_tlbstate.is_lazy, cpu);
791}
792
793STATIC_NOPV void native_flush_tlb_others(const struct cpumask *cpumask,
794 const struct flush_tlb_info *info)
795{
796 count_vm_tlb_event(NR_TLB_REMOTE_FLUSH);
797 if (info->end == TLB_FLUSH_ALL)
798 trace_tlb_flush(TLB_REMOTE_SEND_IPI, TLB_FLUSH_ALL);
799 else
800 trace_tlb_flush(TLB_REMOTE_SEND_IPI,
801 (info->end - info->start) >> PAGE_SHIFT);
802
803 if (is_uv_system()) {
804 /*
805 * This whole special case is confused. UV has a "Broadcast
806 * Assist Unit", which seems to be a fancy way to send IPIs.
807 * Back when x86 used an explicit TLB flush IPI, UV was
808 * optimized to use its own mechanism. These days, x86 uses
809 * smp_call_function_many(), but UV still uses a manual IPI,
810 * and that IPI's action is out of date -- it does a manual
811 * flush instead of calling flush_tlb_func_remote(). This
812 * means that the percpu tlb_gen variables won't be updated
813 * and we'll do pointless flushes on future context switches.
814 *
815 * Rather than hooking native_flush_tlb_others() here, I think
816 * that UV should be updated so that smp_call_function_many(),
817 * etc, are optimal on UV.
818 */
819 cpumask = uv_flush_tlb_others(cpumask, info);
820 if (cpumask)
821 smp_call_function_many(cpumask, flush_tlb_func_remote,
822 (void *)info, 1);
823 return;
824 }
825
826 /*
827 * If no page tables were freed, we can skip sending IPIs to
828 * CPUs in lazy TLB mode. They will flush the CPU themselves
829 * at the next context switch.
830 *
831 * However, if page tables are getting freed, we need to send the
832 * IPI everywhere, to prevent CPUs in lazy TLB mode from tripping
833 * up on the new contents of what used to be page tables, while
834 * doing a speculative memory access.
835 */
836 if (info->freed_tables)
837 smp_call_function_many(cpumask, flush_tlb_func_remote,
838 (void *)info, 1);
839 else
840 on_each_cpu_cond_mask(tlb_is_not_lazy, flush_tlb_func_remote,
841 (void *)info, 1, cpumask);
842}
843
844void flush_tlb_others(const struct cpumask *cpumask,
845 const struct flush_tlb_info *info)
846{
847 __flush_tlb_others(cpumask, info);
848}
849
850/*
851 * See Documentation/x86/tlb.rst for details. We choose 33
852 * because it is large enough to cover the vast majority (at
853 * least 95%) of allocations, and is small enough that we are
854 * confident it will not cause too much overhead. Each single
855 * flush is about 100 ns, so this caps the maximum overhead at
856 * _about_ 3,000 ns.
857 *
858 * This is in units of pages.
859 */
860unsigned long tlb_single_page_flush_ceiling __read_mostly = 33;
861
862static DEFINE_PER_CPU_SHARED_ALIGNED(struct flush_tlb_info, flush_tlb_info);
863
864#ifdef CONFIG_DEBUG_VM
865static DEFINE_PER_CPU(unsigned int, flush_tlb_info_idx);
866#endif
867
868static inline struct flush_tlb_info *get_flush_tlb_info(struct mm_struct *mm,
869 unsigned long start, unsigned long end,
870 unsigned int stride_shift, bool freed_tables,
871 u64 new_tlb_gen)
872{
873 struct flush_tlb_info *info = this_cpu_ptr(&flush_tlb_info);
874
875#ifdef CONFIG_DEBUG_VM
876 /*
877 * Ensure that the following code is non-reentrant and flush_tlb_info
878 * is not overwritten. This means no TLB flushing is initiated by
879 * interrupt handlers and machine-check exception handlers.
880 */
881 BUG_ON(this_cpu_inc_return(flush_tlb_info_idx) != 1);
882#endif
883
884 info->start = start;
885 info->end = end;
886 info->mm = mm;
887 info->stride_shift = stride_shift;
888 info->freed_tables = freed_tables;
889 info->new_tlb_gen = new_tlb_gen;
890
891 return info;
892}
893
894static inline void put_flush_tlb_info(void)
895{
896#ifdef CONFIG_DEBUG_VM
897 /* Complete reentrency prevention checks */
898 barrier();
899 this_cpu_dec(flush_tlb_info_idx);
900#endif
901}
902
903void flush_tlb_mm_range(struct mm_struct *mm, unsigned long start,
904 unsigned long end, unsigned int stride_shift,
905 bool freed_tables)
906{
907 struct flush_tlb_info *info;
908 u64 new_tlb_gen;
909 int cpu;
910
911 cpu = get_cpu();
912
913 /* Should we flush just the requested range? */
914 if ((end == TLB_FLUSH_ALL) ||
915 ((end - start) >> stride_shift) > tlb_single_page_flush_ceiling) {
916 start = 0;
917 end = TLB_FLUSH_ALL;
918 }
919
920 /* This is also a barrier that synchronizes with switch_mm(). */
921 new_tlb_gen = inc_mm_tlb_gen(mm);
922
923 info = get_flush_tlb_info(mm, start, end, stride_shift, freed_tables,
924 new_tlb_gen);
925
926 if (mm == this_cpu_read(cpu_tlbstate.loaded_mm)) {
927 lockdep_assert_irqs_enabled();
928 local_irq_disable();
929 flush_tlb_func_local(info, TLB_LOCAL_MM_SHOOTDOWN);
930 local_irq_enable();
931 }
932
933 if (cpumask_any_but(mm_cpumask(mm), cpu) < nr_cpu_ids)
934 flush_tlb_others(mm_cpumask(mm), info);
935
936 put_flush_tlb_info();
937 put_cpu();
938}
939
940
941static void do_flush_tlb_all(void *info)
942{
943 count_vm_tlb_event(NR_TLB_REMOTE_FLUSH_RECEIVED);
944 __flush_tlb_all();
945}
946
947void flush_tlb_all(void)
948{
949 count_vm_tlb_event(NR_TLB_REMOTE_FLUSH);
950 on_each_cpu(do_flush_tlb_all, NULL, 1);
951}
952
953static void do_kernel_range_flush(void *info)
954{
955 struct flush_tlb_info *f = info;
956 unsigned long addr;
957
958 /* flush range by one by one 'invlpg' */
959 for (addr = f->start; addr < f->end; addr += PAGE_SIZE)
960 flush_tlb_one_kernel(addr);
961}
962
963void flush_tlb_kernel_range(unsigned long start, unsigned long end)
964{
965 /* Balance as user space task's flush, a bit conservative */
966 if (end == TLB_FLUSH_ALL ||
967 (end - start) > tlb_single_page_flush_ceiling << PAGE_SHIFT) {
968 on_each_cpu(do_flush_tlb_all, NULL, 1);
969 } else {
970 struct flush_tlb_info *info;
971
972 preempt_disable();
973 info = get_flush_tlb_info(NULL, start, end, 0, false, 0);
974
975 on_each_cpu(do_kernel_range_flush, info, 1);
976
977 put_flush_tlb_info();
978 preempt_enable();
979 }
980}
981
982/*
983 * This can be used from process context to figure out what the value of
984 * CR3 is without needing to do a (slow) __read_cr3().
985 *
986 * It's intended to be used for code like KVM that sneakily changes CR3
987 * and needs to restore it. It needs to be used very carefully.
988 */
989unsigned long __get_current_cr3_fast(void)
990{
991 unsigned long cr3 = build_cr3(this_cpu_read(cpu_tlbstate.loaded_mm)->pgd,
992 this_cpu_read(cpu_tlbstate.loaded_mm_asid));
993
994 /* For now, be very restrictive about when this can be called. */
995 VM_WARN_ON(in_nmi() || preemptible());
996
997 VM_BUG_ON(cr3 != __read_cr3());
998 return cr3;
999}
1000EXPORT_SYMBOL_GPL(__get_current_cr3_fast);
1001
1002/*
1003 * Flush one page in the kernel mapping
1004 */
1005void flush_tlb_one_kernel(unsigned long addr)
1006{
1007 count_vm_tlb_event(NR_TLB_LOCAL_FLUSH_ONE);
1008
1009 /*
1010 * If PTI is off, then __flush_tlb_one_user() is just INVLPG or its
1011 * paravirt equivalent. Even with PCID, this is sufficient: we only
1012 * use PCID if we also use global PTEs for the kernel mapping, and
1013 * INVLPG flushes global translations across all address spaces.
1014 *
1015 * If PTI is on, then the kernel is mapped with non-global PTEs, and
1016 * __flush_tlb_one_user() will flush the given address for the current
1017 * kernel address space and for its usermode counterpart, but it does
1018 * not flush it for other address spaces.
1019 */
1020 flush_tlb_one_user(addr);
1021
1022 if (!static_cpu_has(X86_FEATURE_PTI))
1023 return;
1024
1025 /*
1026 * See above. We need to propagate the flush to all other address
1027 * spaces. In principle, we only need to propagate it to kernelmode
1028 * address spaces, but the extra bookkeeping we would need is not
1029 * worth it.
1030 */
1031 this_cpu_write(cpu_tlbstate.invalidate_other, true);
1032}
1033
1034/*
1035 * Flush one page in the user mapping
1036 */
1037STATIC_NOPV void native_flush_tlb_one_user(unsigned long addr)
1038{
1039 u32 loaded_mm_asid = this_cpu_read(cpu_tlbstate.loaded_mm_asid);
1040
1041 asm volatile("invlpg (%0)" ::"r" (addr) : "memory");
1042
1043 if (!static_cpu_has(X86_FEATURE_PTI))
1044 return;
1045
1046 /*
1047 * Some platforms #GP if we call invpcid(type=1/2) before CR4.PCIDE=1.
1048 * Just use invalidate_user_asid() in case we are called early.
1049 */
1050 if (!this_cpu_has(X86_FEATURE_INVPCID_SINGLE))
1051 invalidate_user_asid(loaded_mm_asid);
1052 else
1053 invpcid_flush_one(user_pcid(loaded_mm_asid), addr);
1054}
1055
1056void flush_tlb_one_user(unsigned long addr)
1057{
1058 __flush_tlb_one_user(addr);
1059}
1060
1061/*
1062 * Flush everything
1063 */
1064STATIC_NOPV void native_flush_tlb_global(void)
1065{
1066 unsigned long cr4, flags;
1067
1068 if (static_cpu_has(X86_FEATURE_INVPCID)) {
1069 /*
1070 * Using INVPCID is considerably faster than a pair of writes
1071 * to CR4 sandwiched inside an IRQ flag save/restore.
1072 *
1073 * Note, this works with CR4.PCIDE=0 or 1.
1074 */
1075 invpcid_flush_all();
1076 return;
1077 }
1078
1079 /*
1080 * Read-modify-write to CR4 - protect it from preemption and
1081 * from interrupts. (Use the raw variant because this code can
1082 * be called from deep inside debugging code.)
1083 */
1084 raw_local_irq_save(flags);
1085
1086 cr4 = this_cpu_read(cpu_tlbstate.cr4);
1087 /* toggle PGE */
1088 native_write_cr4(cr4 ^ X86_CR4_PGE);
1089 /* write old PGE again and flush TLBs */
1090 native_write_cr4(cr4);
1091
1092 raw_local_irq_restore(flags);
1093}
1094
1095/*
1096 * Flush the entire current user mapping
1097 */
1098STATIC_NOPV void native_flush_tlb_local(void)
1099{
1100 /*
1101 * Preemption or interrupts must be disabled to protect the access
1102 * to the per CPU variable and to prevent being preempted between
1103 * read_cr3() and write_cr3().
1104 */
1105 WARN_ON_ONCE(preemptible());
1106
1107 invalidate_user_asid(this_cpu_read(cpu_tlbstate.loaded_mm_asid));
1108
1109 /* If current->mm == NULL then the read_cr3() "borrows" an mm */
1110 native_write_cr3(__native_read_cr3());
1111}
1112
1113void flush_tlb_local(void)
1114{
1115 __flush_tlb_local();
1116}
1117
1118/*
1119 * Flush everything
1120 */
1121void __flush_tlb_all(void)
1122{
1123 /*
1124 * This is to catch users with enabled preemption and the PGE feature
1125 * and don't trigger the warning in __native_flush_tlb().
1126 */
1127 VM_WARN_ON_ONCE(preemptible());
1128
1129 if (boot_cpu_has(X86_FEATURE_PGE)) {
1130 __flush_tlb_global();
1131 } else {
1132 /*
1133 * !PGE -> !PCID (setup_pcid()), thus every flush is total.
1134 */
1135 flush_tlb_local();
1136 }
1137}
1138EXPORT_SYMBOL_GPL(__flush_tlb_all);
1139
1140/*
1141 * arch_tlbbatch_flush() performs a full TLB flush regardless of the active mm.
1142 * This means that the 'struct flush_tlb_info' that describes which mappings to
1143 * flush is actually fixed. We therefore set a single fixed struct and use it in
1144 * arch_tlbbatch_flush().
1145 */
1146static const struct flush_tlb_info full_flush_tlb_info = {
1147 .mm = NULL,
1148 .start = 0,
1149 .end = TLB_FLUSH_ALL,
1150};
1151
1152void arch_tlbbatch_flush(struct arch_tlbflush_unmap_batch *batch)
1153{
1154 int cpu = get_cpu();
1155
1156 if (cpumask_test_cpu(cpu, &batch->cpumask)) {
1157 lockdep_assert_irqs_enabled();
1158 local_irq_disable();
1159 flush_tlb_func_local(&full_flush_tlb_info, TLB_LOCAL_SHOOTDOWN);
1160 local_irq_enable();
1161 }
1162
1163 if (cpumask_any_but(&batch->cpumask, cpu) < nr_cpu_ids)
1164 flush_tlb_others(&batch->cpumask, &full_flush_tlb_info);
1165
1166 cpumask_clear(&batch->cpumask);
1167
1168 put_cpu();
1169}
1170
1171/*
1172 * Blindly accessing user memory from NMI context can be dangerous
1173 * if we're in the middle of switching the current user task or
1174 * switching the loaded mm. It can also be dangerous if we
1175 * interrupted some kernel code that was temporarily using a
1176 * different mm.
1177 */
1178bool nmi_uaccess_okay(void)
1179{
1180 struct mm_struct *loaded_mm = this_cpu_read(cpu_tlbstate.loaded_mm);
1181 struct mm_struct *current_mm = current->mm;
1182
1183 VM_WARN_ON_ONCE(!loaded_mm);
1184
1185 /*
1186 * The condition we want to check is
1187 * current_mm->pgd == __va(read_cr3_pa()). This may be slow, though,
1188 * if we're running in a VM with shadow paging, and nmi_uaccess_okay()
1189 * is supposed to be reasonably fast.
1190 *
1191 * Instead, we check the almost equivalent but somewhat conservative
1192 * condition below, and we rely on the fact that switch_mm_irqs_off()
1193 * sets loaded_mm to LOADED_MM_SWITCHING before writing to CR3.
1194 */
1195 if (loaded_mm != current_mm)
1196 return false;
1197
1198 VM_WARN_ON_ONCE(current_mm->pgd != __va(read_cr3_pa()));
1199
1200 return true;
1201}
1202
1203static ssize_t tlbflush_read_file(struct file *file, char __user *user_buf,
1204 size_t count, loff_t *ppos)
1205{
1206 char buf[32];
1207 unsigned int len;
1208
1209 len = sprintf(buf, "%ld\n", tlb_single_page_flush_ceiling);
1210 return simple_read_from_buffer(user_buf, count, ppos, buf, len);
1211}
1212
1213static ssize_t tlbflush_write_file(struct file *file,
1214 const char __user *user_buf, size_t count, loff_t *ppos)
1215{
1216 char buf[32];
1217 ssize_t len;
1218 int ceiling;
1219
1220 len = min(count, sizeof(buf) - 1);
1221 if (copy_from_user(buf, user_buf, len))
1222 return -EFAULT;
1223
1224 buf[len] = '\0';
1225 if (kstrtoint(buf, 0, &ceiling))
1226 return -EINVAL;
1227
1228 if (ceiling < 0)
1229 return -EINVAL;
1230
1231 tlb_single_page_flush_ceiling = ceiling;
1232 return count;
1233}
1234
1235static const struct file_operations fops_tlbflush = {
1236 .read = tlbflush_read_file,
1237 .write = tlbflush_write_file,
1238 .llseek = default_llseek,
1239};
1240
1241static int __init create_tlb_single_page_flush_ceiling(void)
1242{
1243 debugfs_create_file("tlb_single_page_flush_ceiling", S_IRUSR | S_IWUSR,
1244 arch_debugfs_dir, NULL, &fops_tlbflush);
1245 return 0;
1246}
1247late_initcall(create_tlb_single_page_flush_ceiling);
1// SPDX-License-Identifier: GPL-2.0-only
2#include <linux/init.h>
3
4#include <linux/mm.h>
5#include <linux/spinlock.h>
6#include <linux/smp.h>
7#include <linux/interrupt.h>
8#include <linux/export.h>
9#include <linux/cpu.h>
10#include <linux/debugfs.h>
11
12#include <asm/tlbflush.h>
13#include <asm/mmu_context.h>
14#include <asm/nospec-branch.h>
15#include <asm/cache.h>
16#include <asm/apic.h>
17#include <asm/uv/uv.h>
18
19#include "mm_internal.h"
20
21/*
22 * TLB flushing, formerly SMP-only
23 * c/o Linus Torvalds.
24 *
25 * These mean you can really definitely utterly forget about
26 * writing to user space from interrupts. (Its not allowed anyway).
27 *
28 * Optimizations Manfred Spraul <manfred@colorfullife.com>
29 *
30 * More scalable flush, from Andi Kleen
31 *
32 * Implement flush IPI by CALL_FUNCTION_VECTOR, Alex Shi
33 */
34
35/*
36 * Use bit 0 to mangle the TIF_SPEC_IB state into the mm pointer which is
37 * stored in cpu_tlb_state.last_user_mm_ibpb.
38 */
39#define LAST_USER_MM_IBPB 0x1UL
40
41/*
42 * We get here when we do something requiring a TLB invalidation
43 * but could not go invalidate all of the contexts. We do the
44 * necessary invalidation by clearing out the 'ctx_id' which
45 * forces a TLB flush when the context is loaded.
46 */
47static void clear_asid_other(void)
48{
49 u16 asid;
50
51 /*
52 * This is only expected to be set if we have disabled
53 * kernel _PAGE_GLOBAL pages.
54 */
55 if (!static_cpu_has(X86_FEATURE_PTI)) {
56 WARN_ON_ONCE(1);
57 return;
58 }
59
60 for (asid = 0; asid < TLB_NR_DYN_ASIDS; asid++) {
61 /* Do not need to flush the current asid */
62 if (asid == this_cpu_read(cpu_tlbstate.loaded_mm_asid))
63 continue;
64 /*
65 * Make sure the next time we go to switch to
66 * this asid, we do a flush:
67 */
68 this_cpu_write(cpu_tlbstate.ctxs[asid].ctx_id, 0);
69 }
70 this_cpu_write(cpu_tlbstate.invalidate_other, false);
71}
72
73atomic64_t last_mm_ctx_id = ATOMIC64_INIT(1);
74
75
76static void choose_new_asid(struct mm_struct *next, u64 next_tlb_gen,
77 u16 *new_asid, bool *need_flush)
78{
79 u16 asid;
80
81 if (!static_cpu_has(X86_FEATURE_PCID)) {
82 *new_asid = 0;
83 *need_flush = true;
84 return;
85 }
86
87 if (this_cpu_read(cpu_tlbstate.invalidate_other))
88 clear_asid_other();
89
90 for (asid = 0; asid < TLB_NR_DYN_ASIDS; asid++) {
91 if (this_cpu_read(cpu_tlbstate.ctxs[asid].ctx_id) !=
92 next->context.ctx_id)
93 continue;
94
95 *new_asid = asid;
96 *need_flush = (this_cpu_read(cpu_tlbstate.ctxs[asid].tlb_gen) <
97 next_tlb_gen);
98 return;
99 }
100
101 /*
102 * We don't currently own an ASID slot on this CPU.
103 * Allocate a slot.
104 */
105 *new_asid = this_cpu_add_return(cpu_tlbstate.next_asid, 1) - 1;
106 if (*new_asid >= TLB_NR_DYN_ASIDS) {
107 *new_asid = 0;
108 this_cpu_write(cpu_tlbstate.next_asid, 1);
109 }
110 *need_flush = true;
111}
112
113static void load_new_mm_cr3(pgd_t *pgdir, u16 new_asid, bool need_flush)
114{
115 unsigned long new_mm_cr3;
116
117 if (need_flush) {
118 invalidate_user_asid(new_asid);
119 new_mm_cr3 = build_cr3(pgdir, new_asid);
120 } else {
121 new_mm_cr3 = build_cr3_noflush(pgdir, new_asid);
122 }
123
124 /*
125 * Caution: many callers of this function expect
126 * that load_cr3() is serializing and orders TLB
127 * fills with respect to the mm_cpumask writes.
128 */
129 write_cr3(new_mm_cr3);
130}
131
132void leave_mm(int cpu)
133{
134 struct mm_struct *loaded_mm = this_cpu_read(cpu_tlbstate.loaded_mm);
135
136 /*
137 * It's plausible that we're in lazy TLB mode while our mm is init_mm.
138 * If so, our callers still expect us to flush the TLB, but there
139 * aren't any user TLB entries in init_mm to worry about.
140 *
141 * This needs to happen before any other sanity checks due to
142 * intel_idle's shenanigans.
143 */
144 if (loaded_mm == &init_mm)
145 return;
146
147 /* Warn if we're not lazy. */
148 WARN_ON(!this_cpu_read(cpu_tlbstate.is_lazy));
149
150 switch_mm(NULL, &init_mm, NULL);
151}
152EXPORT_SYMBOL_GPL(leave_mm);
153
154void switch_mm(struct mm_struct *prev, struct mm_struct *next,
155 struct task_struct *tsk)
156{
157 unsigned long flags;
158
159 local_irq_save(flags);
160 switch_mm_irqs_off(prev, next, tsk);
161 local_irq_restore(flags);
162}
163
164static void sync_current_stack_to_mm(struct mm_struct *mm)
165{
166 unsigned long sp = current_stack_pointer;
167 pgd_t *pgd = pgd_offset(mm, sp);
168
169 if (pgtable_l5_enabled()) {
170 if (unlikely(pgd_none(*pgd))) {
171 pgd_t *pgd_ref = pgd_offset_k(sp);
172
173 set_pgd(pgd, *pgd_ref);
174 }
175 } else {
176 /*
177 * "pgd" is faked. The top level entries are "p4d"s, so sync
178 * the p4d. This compiles to approximately the same code as
179 * the 5-level case.
180 */
181 p4d_t *p4d = p4d_offset(pgd, sp);
182
183 if (unlikely(p4d_none(*p4d))) {
184 pgd_t *pgd_ref = pgd_offset_k(sp);
185 p4d_t *p4d_ref = p4d_offset(pgd_ref, sp);
186
187 set_p4d(p4d, *p4d_ref);
188 }
189 }
190}
191
192static inline unsigned long mm_mangle_tif_spec_ib(struct task_struct *next)
193{
194 unsigned long next_tif = task_thread_info(next)->flags;
195 unsigned long ibpb = (next_tif >> TIF_SPEC_IB) & LAST_USER_MM_IBPB;
196
197 return (unsigned long)next->mm | ibpb;
198}
199
200static void cond_ibpb(struct task_struct *next)
201{
202 if (!next || !next->mm)
203 return;
204
205 /*
206 * Both, the conditional and the always IBPB mode use the mm
207 * pointer to avoid the IBPB when switching between tasks of the
208 * same process. Using the mm pointer instead of mm->context.ctx_id
209 * opens a hypothetical hole vs. mm_struct reuse, which is more or
210 * less impossible to control by an attacker. Aside of that it
211 * would only affect the first schedule so the theoretically
212 * exposed data is not really interesting.
213 */
214 if (static_branch_likely(&switch_mm_cond_ibpb)) {
215 unsigned long prev_mm, next_mm;
216
217 /*
218 * This is a bit more complex than the always mode because
219 * it has to handle two cases:
220 *
221 * 1) Switch from a user space task (potential attacker)
222 * which has TIF_SPEC_IB set to a user space task
223 * (potential victim) which has TIF_SPEC_IB not set.
224 *
225 * 2) Switch from a user space task (potential attacker)
226 * which has TIF_SPEC_IB not set to a user space task
227 * (potential victim) which has TIF_SPEC_IB set.
228 *
229 * This could be done by unconditionally issuing IBPB when
230 * a task which has TIF_SPEC_IB set is either scheduled in
231 * or out. Though that results in two flushes when:
232 *
233 * - the same user space task is scheduled out and later
234 * scheduled in again and only a kernel thread ran in
235 * between.
236 *
237 * - a user space task belonging to the same process is
238 * scheduled in after a kernel thread ran in between
239 *
240 * - a user space task belonging to the same process is
241 * scheduled in immediately.
242 *
243 * Optimize this with reasonably small overhead for the
244 * above cases. Mangle the TIF_SPEC_IB bit into the mm
245 * pointer of the incoming task which is stored in
246 * cpu_tlbstate.last_user_mm_ibpb for comparison.
247 */
248 next_mm = mm_mangle_tif_spec_ib(next);
249 prev_mm = this_cpu_read(cpu_tlbstate.last_user_mm_ibpb);
250
251 /*
252 * Issue IBPB only if the mm's are different and one or
253 * both have the IBPB bit set.
254 */
255 if (next_mm != prev_mm &&
256 (next_mm | prev_mm) & LAST_USER_MM_IBPB)
257 indirect_branch_prediction_barrier();
258
259 this_cpu_write(cpu_tlbstate.last_user_mm_ibpb, next_mm);
260 }
261
262 if (static_branch_unlikely(&switch_mm_always_ibpb)) {
263 /*
264 * Only flush when switching to a user space task with a
265 * different context than the user space task which ran
266 * last on this CPU.
267 */
268 if (this_cpu_read(cpu_tlbstate.last_user_mm) != next->mm) {
269 indirect_branch_prediction_barrier();
270 this_cpu_write(cpu_tlbstate.last_user_mm, next->mm);
271 }
272 }
273}
274
275void switch_mm_irqs_off(struct mm_struct *prev, struct mm_struct *next,
276 struct task_struct *tsk)
277{
278 struct mm_struct *real_prev = this_cpu_read(cpu_tlbstate.loaded_mm);
279 u16 prev_asid = this_cpu_read(cpu_tlbstate.loaded_mm_asid);
280 bool was_lazy = this_cpu_read(cpu_tlbstate.is_lazy);
281 unsigned cpu = smp_processor_id();
282 u64 next_tlb_gen;
283 bool need_flush;
284 u16 new_asid;
285
286 /*
287 * NB: The scheduler will call us with prev == next when switching
288 * from lazy TLB mode to normal mode if active_mm isn't changing.
289 * When this happens, we don't assume that CR3 (and hence
290 * cpu_tlbstate.loaded_mm) matches next.
291 *
292 * NB: leave_mm() calls us with prev == NULL and tsk == NULL.
293 */
294
295 /* We don't want flush_tlb_func_* to run concurrently with us. */
296 if (IS_ENABLED(CONFIG_PROVE_LOCKING))
297 WARN_ON_ONCE(!irqs_disabled());
298
299 /*
300 * Verify that CR3 is what we think it is. This will catch
301 * hypothetical buggy code that directly switches to swapper_pg_dir
302 * without going through leave_mm() / switch_mm_irqs_off() or that
303 * does something like write_cr3(read_cr3_pa()).
304 *
305 * Only do this check if CONFIG_DEBUG_VM=y because __read_cr3()
306 * isn't free.
307 */
308#ifdef CONFIG_DEBUG_VM
309 if (WARN_ON_ONCE(__read_cr3() != build_cr3(real_prev->pgd, prev_asid))) {
310 /*
311 * If we were to BUG here, we'd be very likely to kill
312 * the system so hard that we don't see the call trace.
313 * Try to recover instead by ignoring the error and doing
314 * a global flush to minimize the chance of corruption.
315 *
316 * (This is far from being a fully correct recovery.
317 * Architecturally, the CPU could prefetch something
318 * back into an incorrect ASID slot and leave it there
319 * to cause trouble down the road. It's better than
320 * nothing, though.)
321 */
322 __flush_tlb_all();
323 }
324#endif
325 this_cpu_write(cpu_tlbstate.is_lazy, false);
326
327 /*
328 * The membarrier system call requires a full memory barrier and
329 * core serialization before returning to user-space, after
330 * storing to rq->curr. Writing to CR3 provides that full
331 * memory barrier and core serializing instruction.
332 */
333 if (real_prev == next) {
334 VM_WARN_ON(this_cpu_read(cpu_tlbstate.ctxs[prev_asid].ctx_id) !=
335 next->context.ctx_id);
336
337 /*
338 * Even in lazy TLB mode, the CPU should stay set in the
339 * mm_cpumask. The TLB shootdown code can figure out from
340 * from cpu_tlbstate.is_lazy whether or not to send an IPI.
341 */
342 if (WARN_ON_ONCE(real_prev != &init_mm &&
343 !cpumask_test_cpu(cpu, mm_cpumask(next))))
344 cpumask_set_cpu(cpu, mm_cpumask(next));
345
346 /*
347 * If the CPU is not in lazy TLB mode, we are just switching
348 * from one thread in a process to another thread in the same
349 * process. No TLB flush required.
350 */
351 if (!was_lazy)
352 return;
353
354 /*
355 * Read the tlb_gen to check whether a flush is needed.
356 * If the TLB is up to date, just use it.
357 * The barrier synchronizes with the tlb_gen increment in
358 * the TLB shootdown code.
359 */
360 smp_mb();
361 next_tlb_gen = atomic64_read(&next->context.tlb_gen);
362 if (this_cpu_read(cpu_tlbstate.ctxs[prev_asid].tlb_gen) ==
363 next_tlb_gen)
364 return;
365
366 /*
367 * TLB contents went out of date while we were in lazy
368 * mode. Fall through to the TLB switching code below.
369 */
370 new_asid = prev_asid;
371 need_flush = true;
372 } else {
373 /*
374 * Avoid user/user BTB poisoning by flushing the branch
375 * predictor when switching between processes. This stops
376 * one process from doing Spectre-v2 attacks on another.
377 */
378 cond_ibpb(tsk);
379
380 if (IS_ENABLED(CONFIG_VMAP_STACK)) {
381 /*
382 * If our current stack is in vmalloc space and isn't
383 * mapped in the new pgd, we'll double-fault. Forcibly
384 * map it.
385 */
386 sync_current_stack_to_mm(next);
387 }
388
389 /*
390 * Stop remote flushes for the previous mm.
391 * Skip kernel threads; we never send init_mm TLB flushing IPIs,
392 * but the bitmap manipulation can cause cache line contention.
393 */
394 if (real_prev != &init_mm) {
395 VM_WARN_ON_ONCE(!cpumask_test_cpu(cpu,
396 mm_cpumask(real_prev)));
397 cpumask_clear_cpu(cpu, mm_cpumask(real_prev));
398 }
399
400 /*
401 * Start remote flushes and then read tlb_gen.
402 */
403 if (next != &init_mm)
404 cpumask_set_cpu(cpu, mm_cpumask(next));
405 next_tlb_gen = atomic64_read(&next->context.tlb_gen);
406
407 choose_new_asid(next, next_tlb_gen, &new_asid, &need_flush);
408
409 /* Let nmi_uaccess_okay() know that we're changing CR3. */
410 this_cpu_write(cpu_tlbstate.loaded_mm, LOADED_MM_SWITCHING);
411 barrier();
412 }
413
414 if (need_flush) {
415 this_cpu_write(cpu_tlbstate.ctxs[new_asid].ctx_id, next->context.ctx_id);
416 this_cpu_write(cpu_tlbstate.ctxs[new_asid].tlb_gen, next_tlb_gen);
417 load_new_mm_cr3(next->pgd, new_asid, true);
418
419 /*
420 * NB: This gets called via leave_mm() in the idle path
421 * where RCU functions differently. Tracing normally
422 * uses RCU, so we need to use the _rcuidle variant.
423 *
424 * (There is no good reason for this. The idle code should
425 * be rearranged to call this before rcu_idle_enter().)
426 */
427 trace_tlb_flush_rcuidle(TLB_FLUSH_ON_TASK_SWITCH, TLB_FLUSH_ALL);
428 } else {
429 /* The new ASID is already up to date. */
430 load_new_mm_cr3(next->pgd, new_asid, false);
431
432 /* See above wrt _rcuidle. */
433 trace_tlb_flush_rcuidle(TLB_FLUSH_ON_TASK_SWITCH, 0);
434 }
435
436 /* Make sure we write CR3 before loaded_mm. */
437 barrier();
438
439 this_cpu_write(cpu_tlbstate.loaded_mm, next);
440 this_cpu_write(cpu_tlbstate.loaded_mm_asid, new_asid);
441
442 if (next != real_prev) {
443 load_mm_cr4_irqsoff(next);
444 switch_ldt(real_prev, next);
445 }
446}
447
448/*
449 * Please ignore the name of this function. It should be called
450 * switch_to_kernel_thread().
451 *
452 * enter_lazy_tlb() is a hint from the scheduler that we are entering a
453 * kernel thread or other context without an mm. Acceptable implementations
454 * include doing nothing whatsoever, switching to init_mm, or various clever
455 * lazy tricks to try to minimize TLB flushes.
456 *
457 * The scheduler reserves the right to call enter_lazy_tlb() several times
458 * in a row. It will notify us that we're going back to a real mm by
459 * calling switch_mm_irqs_off().
460 */
461void enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk)
462{
463 if (this_cpu_read(cpu_tlbstate.loaded_mm) == &init_mm)
464 return;
465
466 this_cpu_write(cpu_tlbstate.is_lazy, true);
467}
468
469/*
470 * Call this when reinitializing a CPU. It fixes the following potential
471 * problems:
472 *
473 * - The ASID changed from what cpu_tlbstate thinks it is (most likely
474 * because the CPU was taken down and came back up with CR3's PCID
475 * bits clear. CPU hotplug can do this.
476 *
477 * - The TLB contains junk in slots corresponding to inactive ASIDs.
478 *
479 * - The CPU went so far out to lunch that it may have missed a TLB
480 * flush.
481 */
482void initialize_tlbstate_and_flush(void)
483{
484 int i;
485 struct mm_struct *mm = this_cpu_read(cpu_tlbstate.loaded_mm);
486 u64 tlb_gen = atomic64_read(&init_mm.context.tlb_gen);
487 unsigned long cr3 = __read_cr3();
488
489 /* Assert that CR3 already references the right mm. */
490 WARN_ON((cr3 & CR3_ADDR_MASK) != __pa(mm->pgd));
491
492 /*
493 * Assert that CR4.PCIDE is set if needed. (CR4.PCIDE initialization
494 * doesn't work like other CR4 bits because it can only be set from
495 * long mode.)
496 */
497 WARN_ON(boot_cpu_has(X86_FEATURE_PCID) &&
498 !(cr4_read_shadow() & X86_CR4_PCIDE));
499
500 /* Force ASID 0 and force a TLB flush. */
501 write_cr3(build_cr3(mm->pgd, 0));
502
503 /* Reinitialize tlbstate. */
504 this_cpu_write(cpu_tlbstate.last_user_mm_ibpb, LAST_USER_MM_IBPB);
505 this_cpu_write(cpu_tlbstate.loaded_mm_asid, 0);
506 this_cpu_write(cpu_tlbstate.next_asid, 1);
507 this_cpu_write(cpu_tlbstate.ctxs[0].ctx_id, mm->context.ctx_id);
508 this_cpu_write(cpu_tlbstate.ctxs[0].tlb_gen, tlb_gen);
509
510 for (i = 1; i < TLB_NR_DYN_ASIDS; i++)
511 this_cpu_write(cpu_tlbstate.ctxs[i].ctx_id, 0);
512}
513
514/*
515 * flush_tlb_func_common()'s memory ordering requirement is that any
516 * TLB fills that happen after we flush the TLB are ordered after we
517 * read active_mm's tlb_gen. We don't need any explicit barriers
518 * because all x86 flush operations are serializing and the
519 * atomic64_read operation won't be reordered by the compiler.
520 */
521static void flush_tlb_func_common(const struct flush_tlb_info *f,
522 bool local, enum tlb_flush_reason reason)
523{
524 /*
525 * We have three different tlb_gen values in here. They are:
526 *
527 * - mm_tlb_gen: the latest generation.
528 * - local_tlb_gen: the generation that this CPU has already caught
529 * up to.
530 * - f->new_tlb_gen: the generation that the requester of the flush
531 * wants us to catch up to.
532 */
533 struct mm_struct *loaded_mm = this_cpu_read(cpu_tlbstate.loaded_mm);
534 u32 loaded_mm_asid = this_cpu_read(cpu_tlbstate.loaded_mm_asid);
535 u64 mm_tlb_gen = atomic64_read(&loaded_mm->context.tlb_gen);
536 u64 local_tlb_gen = this_cpu_read(cpu_tlbstate.ctxs[loaded_mm_asid].tlb_gen);
537
538 /* This code cannot presently handle being reentered. */
539 VM_WARN_ON(!irqs_disabled());
540
541 if (unlikely(loaded_mm == &init_mm))
542 return;
543
544 VM_WARN_ON(this_cpu_read(cpu_tlbstate.ctxs[loaded_mm_asid].ctx_id) !=
545 loaded_mm->context.ctx_id);
546
547 if (this_cpu_read(cpu_tlbstate.is_lazy)) {
548 /*
549 * We're in lazy mode. We need to at least flush our
550 * paging-structure cache to avoid speculatively reading
551 * garbage into our TLB. Since switching to init_mm is barely
552 * slower than a minimal flush, just switch to init_mm.
553 *
554 * This should be rare, with native_flush_tlb_others skipping
555 * IPIs to lazy TLB mode CPUs.
556 */
557 switch_mm_irqs_off(NULL, &init_mm, NULL);
558 return;
559 }
560
561 if (unlikely(local_tlb_gen == mm_tlb_gen)) {
562 /*
563 * There's nothing to do: we're already up to date. This can
564 * happen if two concurrent flushes happen -- the first flush to
565 * be handled can catch us all the way up, leaving no work for
566 * the second flush.
567 */
568 trace_tlb_flush(reason, 0);
569 return;
570 }
571
572 WARN_ON_ONCE(local_tlb_gen > mm_tlb_gen);
573 WARN_ON_ONCE(f->new_tlb_gen > mm_tlb_gen);
574
575 /*
576 * If we get to this point, we know that our TLB is out of date.
577 * This does not strictly imply that we need to flush (it's
578 * possible that f->new_tlb_gen <= local_tlb_gen), but we're
579 * going to need to flush in the very near future, so we might
580 * as well get it over with.
581 *
582 * The only question is whether to do a full or partial flush.
583 *
584 * We do a partial flush if requested and two extra conditions
585 * are met:
586 *
587 * 1. f->new_tlb_gen == local_tlb_gen + 1. We have an invariant that
588 * we've always done all needed flushes to catch up to
589 * local_tlb_gen. If, for example, local_tlb_gen == 2 and
590 * f->new_tlb_gen == 3, then we know that the flush needed to bring
591 * us up to date for tlb_gen 3 is the partial flush we're
592 * processing.
593 *
594 * As an example of why this check is needed, suppose that there
595 * are two concurrent flushes. The first is a full flush that
596 * changes context.tlb_gen from 1 to 2. The second is a partial
597 * flush that changes context.tlb_gen from 2 to 3. If they get
598 * processed on this CPU in reverse order, we'll see
599 * local_tlb_gen == 1, mm_tlb_gen == 3, and end != TLB_FLUSH_ALL.
600 * If we were to use __flush_tlb_one_user() and set local_tlb_gen to
601 * 3, we'd be break the invariant: we'd update local_tlb_gen above
602 * 1 without the full flush that's needed for tlb_gen 2.
603 *
604 * 2. f->new_tlb_gen == mm_tlb_gen. This is purely an optimiation.
605 * Partial TLB flushes are not all that much cheaper than full TLB
606 * flushes, so it seems unlikely that it would be a performance win
607 * to do a partial flush if that won't bring our TLB fully up to
608 * date. By doing a full flush instead, we can increase
609 * local_tlb_gen all the way to mm_tlb_gen and we can probably
610 * avoid another flush in the very near future.
611 */
612 if (f->end != TLB_FLUSH_ALL &&
613 f->new_tlb_gen == local_tlb_gen + 1 &&
614 f->new_tlb_gen == mm_tlb_gen) {
615 /* Partial flush */
616 unsigned long nr_invalidate = (f->end - f->start) >> f->stride_shift;
617 unsigned long addr = f->start;
618
619 while (addr < f->end) {
620 __flush_tlb_one_user(addr);
621 addr += 1UL << f->stride_shift;
622 }
623 if (local)
624 count_vm_tlb_events(NR_TLB_LOCAL_FLUSH_ONE, nr_invalidate);
625 trace_tlb_flush(reason, nr_invalidate);
626 } else {
627 /* Full flush. */
628 local_flush_tlb();
629 if (local)
630 count_vm_tlb_event(NR_TLB_LOCAL_FLUSH_ALL);
631 trace_tlb_flush(reason, TLB_FLUSH_ALL);
632 }
633
634 /* Both paths above update our state to mm_tlb_gen. */
635 this_cpu_write(cpu_tlbstate.ctxs[loaded_mm_asid].tlb_gen, mm_tlb_gen);
636}
637
638static void flush_tlb_func_local(const void *info, enum tlb_flush_reason reason)
639{
640 const struct flush_tlb_info *f = info;
641
642 flush_tlb_func_common(f, true, reason);
643}
644
645static void flush_tlb_func_remote(void *info)
646{
647 const struct flush_tlb_info *f = info;
648
649 inc_irq_stat(irq_tlb_count);
650
651 if (f->mm && f->mm != this_cpu_read(cpu_tlbstate.loaded_mm))
652 return;
653
654 count_vm_tlb_event(NR_TLB_REMOTE_FLUSH_RECEIVED);
655 flush_tlb_func_common(f, false, TLB_REMOTE_SHOOTDOWN);
656}
657
658static bool tlb_is_not_lazy(int cpu, void *data)
659{
660 return !per_cpu(cpu_tlbstate.is_lazy, cpu);
661}
662
663void native_flush_tlb_others(const struct cpumask *cpumask,
664 const struct flush_tlb_info *info)
665{
666 count_vm_tlb_event(NR_TLB_REMOTE_FLUSH);
667 if (info->end == TLB_FLUSH_ALL)
668 trace_tlb_flush(TLB_REMOTE_SEND_IPI, TLB_FLUSH_ALL);
669 else
670 trace_tlb_flush(TLB_REMOTE_SEND_IPI,
671 (info->end - info->start) >> PAGE_SHIFT);
672
673 if (is_uv_system()) {
674 /*
675 * This whole special case is confused. UV has a "Broadcast
676 * Assist Unit", which seems to be a fancy way to send IPIs.
677 * Back when x86 used an explicit TLB flush IPI, UV was
678 * optimized to use its own mechanism. These days, x86 uses
679 * smp_call_function_many(), but UV still uses a manual IPI,
680 * and that IPI's action is out of date -- it does a manual
681 * flush instead of calling flush_tlb_func_remote(). This
682 * means that the percpu tlb_gen variables won't be updated
683 * and we'll do pointless flushes on future context switches.
684 *
685 * Rather than hooking native_flush_tlb_others() here, I think
686 * that UV should be updated so that smp_call_function_many(),
687 * etc, are optimal on UV.
688 */
689 cpumask = uv_flush_tlb_others(cpumask, info);
690 if (cpumask)
691 smp_call_function_many(cpumask, flush_tlb_func_remote,
692 (void *)info, 1);
693 return;
694 }
695
696 /*
697 * If no page tables were freed, we can skip sending IPIs to
698 * CPUs in lazy TLB mode. They will flush the CPU themselves
699 * at the next context switch.
700 *
701 * However, if page tables are getting freed, we need to send the
702 * IPI everywhere, to prevent CPUs in lazy TLB mode from tripping
703 * up on the new contents of what used to be page tables, while
704 * doing a speculative memory access.
705 */
706 if (info->freed_tables)
707 smp_call_function_many(cpumask, flush_tlb_func_remote,
708 (void *)info, 1);
709 else
710 on_each_cpu_cond_mask(tlb_is_not_lazy, flush_tlb_func_remote,
711 (void *)info, 1, GFP_ATOMIC, cpumask);
712}
713
714/*
715 * See Documentation/x86/tlb.rst for details. We choose 33
716 * because it is large enough to cover the vast majority (at
717 * least 95%) of allocations, and is small enough that we are
718 * confident it will not cause too much overhead. Each single
719 * flush is about 100 ns, so this caps the maximum overhead at
720 * _about_ 3,000 ns.
721 *
722 * This is in units of pages.
723 */
724unsigned long tlb_single_page_flush_ceiling __read_mostly = 33;
725
726static DEFINE_PER_CPU_SHARED_ALIGNED(struct flush_tlb_info, flush_tlb_info);
727
728#ifdef CONFIG_DEBUG_VM
729static DEFINE_PER_CPU(unsigned int, flush_tlb_info_idx);
730#endif
731
732static inline struct flush_tlb_info *get_flush_tlb_info(struct mm_struct *mm,
733 unsigned long start, unsigned long end,
734 unsigned int stride_shift, bool freed_tables,
735 u64 new_tlb_gen)
736{
737 struct flush_tlb_info *info = this_cpu_ptr(&flush_tlb_info);
738
739#ifdef CONFIG_DEBUG_VM
740 /*
741 * Ensure that the following code is non-reentrant and flush_tlb_info
742 * is not overwritten. This means no TLB flushing is initiated by
743 * interrupt handlers and machine-check exception handlers.
744 */
745 BUG_ON(this_cpu_inc_return(flush_tlb_info_idx) != 1);
746#endif
747
748 info->start = start;
749 info->end = end;
750 info->mm = mm;
751 info->stride_shift = stride_shift;
752 info->freed_tables = freed_tables;
753 info->new_tlb_gen = new_tlb_gen;
754
755 return info;
756}
757
758static inline void put_flush_tlb_info(void)
759{
760#ifdef CONFIG_DEBUG_VM
761 /* Complete reentrency prevention checks */
762 barrier();
763 this_cpu_dec(flush_tlb_info_idx);
764#endif
765}
766
767void flush_tlb_mm_range(struct mm_struct *mm, unsigned long start,
768 unsigned long end, unsigned int stride_shift,
769 bool freed_tables)
770{
771 struct flush_tlb_info *info;
772 u64 new_tlb_gen;
773 int cpu;
774
775 cpu = get_cpu();
776
777 /* Should we flush just the requested range? */
778 if ((end == TLB_FLUSH_ALL) ||
779 ((end - start) >> stride_shift) > tlb_single_page_flush_ceiling) {
780 start = 0;
781 end = TLB_FLUSH_ALL;
782 }
783
784 /* This is also a barrier that synchronizes with switch_mm(). */
785 new_tlb_gen = inc_mm_tlb_gen(mm);
786
787 info = get_flush_tlb_info(mm, start, end, stride_shift, freed_tables,
788 new_tlb_gen);
789
790 if (mm == this_cpu_read(cpu_tlbstate.loaded_mm)) {
791 lockdep_assert_irqs_enabled();
792 local_irq_disable();
793 flush_tlb_func_local(info, TLB_LOCAL_MM_SHOOTDOWN);
794 local_irq_enable();
795 }
796
797 if (cpumask_any_but(mm_cpumask(mm), cpu) < nr_cpu_ids)
798 flush_tlb_others(mm_cpumask(mm), info);
799
800 put_flush_tlb_info();
801 put_cpu();
802}
803
804
805static void do_flush_tlb_all(void *info)
806{
807 count_vm_tlb_event(NR_TLB_REMOTE_FLUSH_RECEIVED);
808 __flush_tlb_all();
809}
810
811void flush_tlb_all(void)
812{
813 count_vm_tlb_event(NR_TLB_REMOTE_FLUSH);
814 on_each_cpu(do_flush_tlb_all, NULL, 1);
815}
816
817static void do_kernel_range_flush(void *info)
818{
819 struct flush_tlb_info *f = info;
820 unsigned long addr;
821
822 /* flush range by one by one 'invlpg' */
823 for (addr = f->start; addr < f->end; addr += PAGE_SIZE)
824 __flush_tlb_one_kernel(addr);
825}
826
827void flush_tlb_kernel_range(unsigned long start, unsigned long end)
828{
829 /* Balance as user space task's flush, a bit conservative */
830 if (end == TLB_FLUSH_ALL ||
831 (end - start) > tlb_single_page_flush_ceiling << PAGE_SHIFT) {
832 on_each_cpu(do_flush_tlb_all, NULL, 1);
833 } else {
834 struct flush_tlb_info *info;
835
836 preempt_disable();
837 info = get_flush_tlb_info(NULL, start, end, 0, false, 0);
838
839 on_each_cpu(do_kernel_range_flush, info, 1);
840
841 put_flush_tlb_info();
842 preempt_enable();
843 }
844}
845
846/*
847 * arch_tlbbatch_flush() performs a full TLB flush regardless of the active mm.
848 * This means that the 'struct flush_tlb_info' that describes which mappings to
849 * flush is actually fixed. We therefore set a single fixed struct and use it in
850 * arch_tlbbatch_flush().
851 */
852static const struct flush_tlb_info full_flush_tlb_info = {
853 .mm = NULL,
854 .start = 0,
855 .end = TLB_FLUSH_ALL,
856};
857
858void arch_tlbbatch_flush(struct arch_tlbflush_unmap_batch *batch)
859{
860 int cpu = get_cpu();
861
862 if (cpumask_test_cpu(cpu, &batch->cpumask)) {
863 lockdep_assert_irqs_enabled();
864 local_irq_disable();
865 flush_tlb_func_local(&full_flush_tlb_info, TLB_LOCAL_SHOOTDOWN);
866 local_irq_enable();
867 }
868
869 if (cpumask_any_but(&batch->cpumask, cpu) < nr_cpu_ids)
870 flush_tlb_others(&batch->cpumask, &full_flush_tlb_info);
871
872 cpumask_clear(&batch->cpumask);
873
874 put_cpu();
875}
876
877static ssize_t tlbflush_read_file(struct file *file, char __user *user_buf,
878 size_t count, loff_t *ppos)
879{
880 char buf[32];
881 unsigned int len;
882
883 len = sprintf(buf, "%ld\n", tlb_single_page_flush_ceiling);
884 return simple_read_from_buffer(user_buf, count, ppos, buf, len);
885}
886
887static ssize_t tlbflush_write_file(struct file *file,
888 const char __user *user_buf, size_t count, loff_t *ppos)
889{
890 char buf[32];
891 ssize_t len;
892 int ceiling;
893
894 len = min(count, sizeof(buf) - 1);
895 if (copy_from_user(buf, user_buf, len))
896 return -EFAULT;
897
898 buf[len] = '\0';
899 if (kstrtoint(buf, 0, &ceiling))
900 return -EINVAL;
901
902 if (ceiling < 0)
903 return -EINVAL;
904
905 tlb_single_page_flush_ceiling = ceiling;
906 return count;
907}
908
909static const struct file_operations fops_tlbflush = {
910 .read = tlbflush_read_file,
911 .write = tlbflush_write_file,
912 .llseek = default_llseek,
913};
914
915static int __init create_tlb_single_page_flush_ceiling(void)
916{
917 debugfs_create_file("tlb_single_page_flush_ceiling", S_IRUSR | S_IWUSR,
918 arch_debugfs_dir, NULL, &fops_tlbflush);
919 return 0;
920}
921late_initcall(create_tlb_single_page_flush_ceiling);