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1// SPDX-License-Identifier: GPL-2.0+
2// Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
3// Copyright (C) 2008 Juergen Beisert
4
5#include <linux/clk.h>
6#include <linux/completion.h>
7#include <linux/delay.h>
8#include <linux/dmaengine.h>
9#include <linux/dma-mapping.h>
10#include <linux/err.h>
11#include <linux/interrupt.h>
12#include <linux/io.h>
13#include <linux/irq.h>
14#include <linux/kernel.h>
15#include <linux/module.h>
16#include <linux/pinctrl/consumer.h>
17#include <linux/platform_device.h>
18#include <linux/pm_runtime.h>
19#include <linux/slab.h>
20#include <linux/spi/spi.h>
21#include <linux/spi/spi_bitbang.h>
22#include <linux/types.h>
23#include <linux/of.h>
24#include <linux/of_device.h>
25#include <linux/property.h>
26
27#include <linux/platform_data/dma-imx.h>
28
29#define DRIVER_NAME "spi_imx"
30
31static bool use_dma = true;
32module_param(use_dma, bool, 0644);
33MODULE_PARM_DESC(use_dma, "Enable usage of DMA when available (default)");
34
35#define MXC_RPM_TIMEOUT 2000 /* 2000ms */
36
37#define MXC_CSPIRXDATA 0x00
38#define MXC_CSPITXDATA 0x04
39#define MXC_CSPICTRL 0x08
40#define MXC_CSPIINT 0x0c
41#define MXC_RESET 0x1c
42
43/* generic defines to abstract from the different register layouts */
44#define MXC_INT_RR (1 << 0) /* Receive data ready interrupt */
45#define MXC_INT_TE (1 << 1) /* Transmit FIFO empty interrupt */
46#define MXC_INT_RDR BIT(4) /* Receive date threshold interrupt */
47
48/* The maximum bytes that a sdma BD can transfer. */
49#define MAX_SDMA_BD_BYTES (1 << 15)
50#define MX51_ECSPI_CTRL_MAX_BURST 512
51/* The maximum bytes that IMX53_ECSPI can transfer in slave mode.*/
52#define MX53_MAX_TRANSFER_BYTES 512
53
54enum spi_imx_devtype {
55 IMX1_CSPI,
56 IMX21_CSPI,
57 IMX27_CSPI,
58 IMX31_CSPI,
59 IMX35_CSPI, /* CSPI on all i.mx except above */
60 IMX51_ECSPI, /* ECSPI on i.mx51 */
61 IMX53_ECSPI, /* ECSPI on i.mx53 and later */
62};
63
64struct spi_imx_data;
65
66struct spi_imx_devtype_data {
67 void (*intctrl)(struct spi_imx_data *, int);
68 int (*prepare_message)(struct spi_imx_data *, struct spi_message *);
69 int (*prepare_transfer)(struct spi_imx_data *, struct spi_device *,
70 struct spi_transfer *);
71 void (*trigger)(struct spi_imx_data *);
72 int (*rx_available)(struct spi_imx_data *);
73 void (*reset)(struct spi_imx_data *);
74 void (*setup_wml)(struct spi_imx_data *);
75 void (*disable)(struct spi_imx_data *);
76 void (*disable_dma)(struct spi_imx_data *);
77 bool has_dmamode;
78 bool has_slavemode;
79 unsigned int fifo_size;
80 bool dynamic_burst;
81 enum spi_imx_devtype devtype;
82};
83
84struct spi_imx_data {
85 struct spi_bitbang bitbang;
86 struct device *dev;
87
88 struct completion xfer_done;
89 void __iomem *base;
90 unsigned long base_phys;
91
92 struct clk *clk_per;
93 struct clk *clk_ipg;
94 unsigned long spi_clk;
95 unsigned int spi_bus_clk;
96
97 unsigned int bits_per_word;
98 unsigned int spi_drctl;
99
100 unsigned int count, remainder;
101 void (*tx)(struct spi_imx_data *);
102 void (*rx)(struct spi_imx_data *);
103 void *rx_buf;
104 const void *tx_buf;
105 unsigned int txfifo; /* number of words pushed in tx FIFO */
106 unsigned int dynamic_burst;
107
108 /* Slave mode */
109 bool slave_mode;
110 bool slave_aborted;
111 unsigned int slave_burst;
112
113 /* DMA */
114 bool usedma;
115 u32 wml;
116 struct completion dma_rx_completion;
117 struct completion dma_tx_completion;
118
119 const struct spi_imx_devtype_data *devtype_data;
120};
121
122static inline int is_imx27_cspi(struct spi_imx_data *d)
123{
124 return d->devtype_data->devtype == IMX27_CSPI;
125}
126
127static inline int is_imx35_cspi(struct spi_imx_data *d)
128{
129 return d->devtype_data->devtype == IMX35_CSPI;
130}
131
132static inline int is_imx51_ecspi(struct spi_imx_data *d)
133{
134 return d->devtype_data->devtype == IMX51_ECSPI;
135}
136
137static inline int is_imx53_ecspi(struct spi_imx_data *d)
138{
139 return d->devtype_data->devtype == IMX53_ECSPI;
140}
141
142#define MXC_SPI_BUF_RX(type) \
143static void spi_imx_buf_rx_##type(struct spi_imx_data *spi_imx) \
144{ \
145 unsigned int val = readl(spi_imx->base + MXC_CSPIRXDATA); \
146 \
147 if (spi_imx->rx_buf) { \
148 *(type *)spi_imx->rx_buf = val; \
149 spi_imx->rx_buf += sizeof(type); \
150 } \
151 \
152 spi_imx->remainder -= sizeof(type); \
153}
154
155#define MXC_SPI_BUF_TX(type) \
156static void spi_imx_buf_tx_##type(struct spi_imx_data *spi_imx) \
157{ \
158 type val = 0; \
159 \
160 if (spi_imx->tx_buf) { \
161 val = *(type *)spi_imx->tx_buf; \
162 spi_imx->tx_buf += sizeof(type); \
163 } \
164 \
165 spi_imx->count -= sizeof(type); \
166 \
167 writel(val, spi_imx->base + MXC_CSPITXDATA); \
168}
169
170MXC_SPI_BUF_RX(u8)
171MXC_SPI_BUF_TX(u8)
172MXC_SPI_BUF_RX(u16)
173MXC_SPI_BUF_TX(u16)
174MXC_SPI_BUF_RX(u32)
175MXC_SPI_BUF_TX(u32)
176
177/* First entry is reserved, second entry is valid only if SDHC_SPIEN is set
178 * (which is currently not the case in this driver)
179 */
180static int mxc_clkdivs[] = {0, 3, 4, 6, 8, 12, 16, 24, 32, 48, 64, 96, 128, 192,
181 256, 384, 512, 768, 1024};
182
183/* MX21, MX27 */
184static unsigned int spi_imx_clkdiv_1(unsigned int fin,
185 unsigned int fspi, unsigned int max, unsigned int *fres)
186{
187 int i;
188
189 for (i = 2; i < max; i++)
190 if (fspi * mxc_clkdivs[i] >= fin)
191 break;
192
193 *fres = fin / mxc_clkdivs[i];
194 return i;
195}
196
197/* MX1, MX31, MX35, MX51 CSPI */
198static unsigned int spi_imx_clkdiv_2(unsigned int fin,
199 unsigned int fspi, unsigned int *fres)
200{
201 int i, div = 4;
202
203 for (i = 0; i < 7; i++) {
204 if (fspi * div >= fin)
205 goto out;
206 div <<= 1;
207 }
208
209out:
210 *fres = fin / div;
211 return i;
212}
213
214static int spi_imx_bytes_per_word(const int bits_per_word)
215{
216 if (bits_per_word <= 8)
217 return 1;
218 else if (bits_per_word <= 16)
219 return 2;
220 else
221 return 4;
222}
223
224static bool spi_imx_can_dma(struct spi_master *master, struct spi_device *spi,
225 struct spi_transfer *transfer)
226{
227 struct spi_imx_data *spi_imx = spi_master_get_devdata(master);
228
229 if (!use_dma || master->fallback)
230 return false;
231
232 if (!master->dma_rx)
233 return false;
234
235 if (spi_imx->slave_mode)
236 return false;
237
238 if (transfer->len < spi_imx->devtype_data->fifo_size)
239 return false;
240
241 spi_imx->dynamic_burst = 0;
242
243 return true;
244}
245
246#define MX51_ECSPI_CTRL 0x08
247#define MX51_ECSPI_CTRL_ENABLE (1 << 0)
248#define MX51_ECSPI_CTRL_XCH (1 << 2)
249#define MX51_ECSPI_CTRL_SMC (1 << 3)
250#define MX51_ECSPI_CTRL_MODE_MASK (0xf << 4)
251#define MX51_ECSPI_CTRL_DRCTL(drctl) ((drctl) << 16)
252#define MX51_ECSPI_CTRL_POSTDIV_OFFSET 8
253#define MX51_ECSPI_CTRL_PREDIV_OFFSET 12
254#define MX51_ECSPI_CTRL_CS(cs) ((cs) << 18)
255#define MX51_ECSPI_CTRL_BL_OFFSET 20
256#define MX51_ECSPI_CTRL_BL_MASK (0xfff << 20)
257
258#define MX51_ECSPI_CONFIG 0x0c
259#define MX51_ECSPI_CONFIG_SCLKPHA(cs) (1 << ((cs) + 0))
260#define MX51_ECSPI_CONFIG_SCLKPOL(cs) (1 << ((cs) + 4))
261#define MX51_ECSPI_CONFIG_SBBCTRL(cs) (1 << ((cs) + 8))
262#define MX51_ECSPI_CONFIG_SSBPOL(cs) (1 << ((cs) + 12))
263#define MX51_ECSPI_CONFIG_SCLKCTL(cs) (1 << ((cs) + 20))
264
265#define MX51_ECSPI_INT 0x10
266#define MX51_ECSPI_INT_TEEN (1 << 0)
267#define MX51_ECSPI_INT_RREN (1 << 3)
268#define MX51_ECSPI_INT_RDREN (1 << 4)
269
270#define MX51_ECSPI_DMA 0x14
271#define MX51_ECSPI_DMA_TX_WML(wml) ((wml) & 0x3f)
272#define MX51_ECSPI_DMA_RX_WML(wml) (((wml) & 0x3f) << 16)
273#define MX51_ECSPI_DMA_RXT_WML(wml) (((wml) & 0x3f) << 24)
274
275#define MX51_ECSPI_DMA_TEDEN (1 << 7)
276#define MX51_ECSPI_DMA_RXDEN (1 << 23)
277#define MX51_ECSPI_DMA_RXTDEN (1 << 31)
278
279#define MX51_ECSPI_STAT 0x18
280#define MX51_ECSPI_STAT_RR (1 << 3)
281
282#define MX51_ECSPI_TESTREG 0x20
283#define MX51_ECSPI_TESTREG_LBC BIT(31)
284
285static void spi_imx_buf_rx_swap_u32(struct spi_imx_data *spi_imx)
286{
287 unsigned int val = readl(spi_imx->base + MXC_CSPIRXDATA);
288#ifdef __LITTLE_ENDIAN
289 unsigned int bytes_per_word;
290#endif
291
292 if (spi_imx->rx_buf) {
293#ifdef __LITTLE_ENDIAN
294 bytes_per_word = spi_imx_bytes_per_word(spi_imx->bits_per_word);
295 if (bytes_per_word == 1)
296 val = cpu_to_be32(val);
297 else if (bytes_per_word == 2)
298 val = (val << 16) | (val >> 16);
299#endif
300 *(u32 *)spi_imx->rx_buf = val;
301 spi_imx->rx_buf += sizeof(u32);
302 }
303
304 spi_imx->remainder -= sizeof(u32);
305}
306
307static void spi_imx_buf_rx_swap(struct spi_imx_data *spi_imx)
308{
309 int unaligned;
310 u32 val;
311
312 unaligned = spi_imx->remainder % 4;
313
314 if (!unaligned) {
315 spi_imx_buf_rx_swap_u32(spi_imx);
316 return;
317 }
318
319 if (spi_imx_bytes_per_word(spi_imx->bits_per_word) == 2) {
320 spi_imx_buf_rx_u16(spi_imx);
321 return;
322 }
323
324 val = readl(spi_imx->base + MXC_CSPIRXDATA);
325
326 while (unaligned--) {
327 if (spi_imx->rx_buf) {
328 *(u8 *)spi_imx->rx_buf = (val >> (8 * unaligned)) & 0xff;
329 spi_imx->rx_buf++;
330 }
331 spi_imx->remainder--;
332 }
333}
334
335static void spi_imx_buf_tx_swap_u32(struct spi_imx_data *spi_imx)
336{
337 u32 val = 0;
338#ifdef __LITTLE_ENDIAN
339 unsigned int bytes_per_word;
340#endif
341
342 if (spi_imx->tx_buf) {
343 val = *(u32 *)spi_imx->tx_buf;
344 spi_imx->tx_buf += sizeof(u32);
345 }
346
347 spi_imx->count -= sizeof(u32);
348#ifdef __LITTLE_ENDIAN
349 bytes_per_word = spi_imx_bytes_per_word(spi_imx->bits_per_word);
350
351 if (bytes_per_word == 1)
352 val = cpu_to_be32(val);
353 else if (bytes_per_word == 2)
354 val = (val << 16) | (val >> 16);
355#endif
356 writel(val, spi_imx->base + MXC_CSPITXDATA);
357}
358
359static void spi_imx_buf_tx_swap(struct spi_imx_data *spi_imx)
360{
361 int unaligned;
362 u32 val = 0;
363
364 unaligned = spi_imx->count % 4;
365
366 if (!unaligned) {
367 spi_imx_buf_tx_swap_u32(spi_imx);
368 return;
369 }
370
371 if (spi_imx_bytes_per_word(spi_imx->bits_per_word) == 2) {
372 spi_imx_buf_tx_u16(spi_imx);
373 return;
374 }
375
376 while (unaligned--) {
377 if (spi_imx->tx_buf) {
378 val |= *(u8 *)spi_imx->tx_buf << (8 * unaligned);
379 spi_imx->tx_buf++;
380 }
381 spi_imx->count--;
382 }
383
384 writel(val, spi_imx->base + MXC_CSPITXDATA);
385}
386
387static void mx53_ecspi_rx_slave(struct spi_imx_data *spi_imx)
388{
389 u32 val = be32_to_cpu(readl(spi_imx->base + MXC_CSPIRXDATA));
390
391 if (spi_imx->rx_buf) {
392 int n_bytes = spi_imx->slave_burst % sizeof(val);
393
394 if (!n_bytes)
395 n_bytes = sizeof(val);
396
397 memcpy(spi_imx->rx_buf,
398 ((u8 *)&val) + sizeof(val) - n_bytes, n_bytes);
399
400 spi_imx->rx_buf += n_bytes;
401 spi_imx->slave_burst -= n_bytes;
402 }
403
404 spi_imx->remainder -= sizeof(u32);
405}
406
407static void mx53_ecspi_tx_slave(struct spi_imx_data *spi_imx)
408{
409 u32 val = 0;
410 int n_bytes = spi_imx->count % sizeof(val);
411
412 if (!n_bytes)
413 n_bytes = sizeof(val);
414
415 if (spi_imx->tx_buf) {
416 memcpy(((u8 *)&val) + sizeof(val) - n_bytes,
417 spi_imx->tx_buf, n_bytes);
418 val = cpu_to_be32(val);
419 spi_imx->tx_buf += n_bytes;
420 }
421
422 spi_imx->count -= n_bytes;
423
424 writel(val, spi_imx->base + MXC_CSPITXDATA);
425}
426
427/* MX51 eCSPI */
428static unsigned int mx51_ecspi_clkdiv(struct spi_imx_data *spi_imx,
429 unsigned int fspi, unsigned int *fres)
430{
431 /*
432 * there are two 4-bit dividers, the pre-divider divides by
433 * $pre, the post-divider by 2^$post
434 */
435 unsigned int pre, post;
436 unsigned int fin = spi_imx->spi_clk;
437
438 if (unlikely(fspi > fin))
439 return 0;
440
441 post = fls(fin) - fls(fspi);
442 if (fin > fspi << post)
443 post++;
444
445 /* now we have: (fin <= fspi << post) with post being minimal */
446
447 post = max(4U, post) - 4;
448 if (unlikely(post > 0xf)) {
449 dev_err(spi_imx->dev, "cannot set clock freq: %u (base freq: %u)\n",
450 fspi, fin);
451 return 0xff;
452 }
453
454 pre = DIV_ROUND_UP(fin, fspi << post) - 1;
455
456 dev_dbg(spi_imx->dev, "%s: fin: %u, fspi: %u, post: %u, pre: %u\n",
457 __func__, fin, fspi, post, pre);
458
459 /* Resulting frequency for the SCLK line. */
460 *fres = (fin / (pre + 1)) >> post;
461
462 return (pre << MX51_ECSPI_CTRL_PREDIV_OFFSET) |
463 (post << MX51_ECSPI_CTRL_POSTDIV_OFFSET);
464}
465
466static void mx51_ecspi_intctrl(struct spi_imx_data *spi_imx, int enable)
467{
468 unsigned val = 0;
469
470 if (enable & MXC_INT_TE)
471 val |= MX51_ECSPI_INT_TEEN;
472
473 if (enable & MXC_INT_RR)
474 val |= MX51_ECSPI_INT_RREN;
475
476 if (enable & MXC_INT_RDR)
477 val |= MX51_ECSPI_INT_RDREN;
478
479 writel(val, spi_imx->base + MX51_ECSPI_INT);
480}
481
482static void mx51_ecspi_trigger(struct spi_imx_data *spi_imx)
483{
484 u32 reg;
485
486 reg = readl(spi_imx->base + MX51_ECSPI_CTRL);
487 reg |= MX51_ECSPI_CTRL_XCH;
488 writel(reg, spi_imx->base + MX51_ECSPI_CTRL);
489}
490
491static void mx51_disable_dma(struct spi_imx_data *spi_imx)
492{
493 writel(0, spi_imx->base + MX51_ECSPI_DMA);
494}
495
496static void mx51_ecspi_disable(struct spi_imx_data *spi_imx)
497{
498 u32 ctrl;
499
500 ctrl = readl(spi_imx->base + MX51_ECSPI_CTRL);
501 ctrl &= ~MX51_ECSPI_CTRL_ENABLE;
502 writel(ctrl, spi_imx->base + MX51_ECSPI_CTRL);
503}
504
505static int mx51_ecspi_prepare_message(struct spi_imx_data *spi_imx,
506 struct spi_message *msg)
507{
508 struct spi_device *spi = msg->spi;
509 u32 ctrl = MX51_ECSPI_CTRL_ENABLE;
510 u32 testreg;
511 u32 cfg = readl(spi_imx->base + MX51_ECSPI_CONFIG);
512
513 /* set Master or Slave mode */
514 if (spi_imx->slave_mode)
515 ctrl &= ~MX51_ECSPI_CTRL_MODE_MASK;
516 else
517 ctrl |= MX51_ECSPI_CTRL_MODE_MASK;
518
519 /*
520 * Enable SPI_RDY handling (falling edge/level triggered).
521 */
522 if (spi->mode & SPI_READY)
523 ctrl |= MX51_ECSPI_CTRL_DRCTL(spi_imx->spi_drctl);
524
525 /* set chip select to use */
526 ctrl |= MX51_ECSPI_CTRL_CS(spi->chip_select);
527
528 /*
529 * The ctrl register must be written first, with the EN bit set other
530 * registers must not be written to.
531 */
532 writel(ctrl, spi_imx->base + MX51_ECSPI_CTRL);
533
534 testreg = readl(spi_imx->base + MX51_ECSPI_TESTREG);
535 if (spi->mode & SPI_LOOP)
536 testreg |= MX51_ECSPI_TESTREG_LBC;
537 else
538 testreg &= ~MX51_ECSPI_TESTREG_LBC;
539 writel(testreg, spi_imx->base + MX51_ECSPI_TESTREG);
540
541 /*
542 * eCSPI burst completion by Chip Select signal in Slave mode
543 * is not functional for imx53 Soc, config SPI burst completed when
544 * BURST_LENGTH + 1 bits are received
545 */
546 if (spi_imx->slave_mode && is_imx53_ecspi(spi_imx))
547 cfg &= ~MX51_ECSPI_CONFIG_SBBCTRL(spi->chip_select);
548 else
549 cfg |= MX51_ECSPI_CONFIG_SBBCTRL(spi->chip_select);
550
551 if (spi->mode & SPI_CPHA)
552 cfg |= MX51_ECSPI_CONFIG_SCLKPHA(spi->chip_select);
553 else
554 cfg &= ~MX51_ECSPI_CONFIG_SCLKPHA(spi->chip_select);
555
556 if (spi->mode & SPI_CPOL) {
557 cfg |= MX51_ECSPI_CONFIG_SCLKPOL(spi->chip_select);
558 cfg |= MX51_ECSPI_CONFIG_SCLKCTL(spi->chip_select);
559 } else {
560 cfg &= ~MX51_ECSPI_CONFIG_SCLKPOL(spi->chip_select);
561 cfg &= ~MX51_ECSPI_CONFIG_SCLKCTL(spi->chip_select);
562 }
563
564 if (spi->mode & SPI_CS_HIGH)
565 cfg |= MX51_ECSPI_CONFIG_SSBPOL(spi->chip_select);
566 else
567 cfg &= ~MX51_ECSPI_CONFIG_SSBPOL(spi->chip_select);
568
569 writel(cfg, spi_imx->base + MX51_ECSPI_CONFIG);
570
571 return 0;
572}
573
574static int mx51_ecspi_prepare_transfer(struct spi_imx_data *spi_imx,
575 struct spi_device *spi,
576 struct spi_transfer *t)
577{
578 u32 ctrl = readl(spi_imx->base + MX51_ECSPI_CTRL);
579 u32 clk = t->speed_hz, delay;
580
581 /* Clear BL field and set the right value */
582 ctrl &= ~MX51_ECSPI_CTRL_BL_MASK;
583 if (spi_imx->slave_mode && is_imx53_ecspi(spi_imx))
584 ctrl |= (spi_imx->slave_burst * 8 - 1)
585 << MX51_ECSPI_CTRL_BL_OFFSET;
586 else
587 ctrl |= (spi_imx->bits_per_word - 1)
588 << MX51_ECSPI_CTRL_BL_OFFSET;
589
590 /* set clock speed */
591 ctrl &= ~(0xf << MX51_ECSPI_CTRL_POSTDIV_OFFSET |
592 0xf << MX51_ECSPI_CTRL_PREDIV_OFFSET);
593 ctrl |= mx51_ecspi_clkdiv(spi_imx, t->speed_hz, &clk);
594 spi_imx->spi_bus_clk = clk;
595
596 if (spi_imx->usedma)
597 ctrl |= MX51_ECSPI_CTRL_SMC;
598
599 writel(ctrl, spi_imx->base + MX51_ECSPI_CTRL);
600
601 /*
602 * Wait until the changes in the configuration register CONFIGREG
603 * propagate into the hardware. It takes exactly one tick of the
604 * SCLK clock, but we will wait two SCLK clock just to be sure. The
605 * effect of the delay it takes for the hardware to apply changes
606 * is noticable if the SCLK clock run very slow. In such a case, if
607 * the polarity of SCLK should be inverted, the GPIO ChipSelect might
608 * be asserted before the SCLK polarity changes, which would disrupt
609 * the SPI communication as the device on the other end would consider
610 * the change of SCLK polarity as a clock tick already.
611 */
612 delay = (2 * 1000000) / clk;
613 if (likely(delay < 10)) /* SCLK is faster than 100 kHz */
614 udelay(delay);
615 else /* SCLK is _very_ slow */
616 usleep_range(delay, delay + 10);
617
618 return 0;
619}
620
621static void mx51_setup_wml(struct spi_imx_data *spi_imx)
622{
623 /*
624 * Configure the DMA register: setup the watermark
625 * and enable DMA request.
626 */
627 writel(MX51_ECSPI_DMA_RX_WML(spi_imx->wml - 1) |
628 MX51_ECSPI_DMA_TX_WML(spi_imx->wml) |
629 MX51_ECSPI_DMA_RXT_WML(spi_imx->wml) |
630 MX51_ECSPI_DMA_TEDEN | MX51_ECSPI_DMA_RXDEN |
631 MX51_ECSPI_DMA_RXTDEN, spi_imx->base + MX51_ECSPI_DMA);
632}
633
634static int mx51_ecspi_rx_available(struct spi_imx_data *spi_imx)
635{
636 return readl(spi_imx->base + MX51_ECSPI_STAT) & MX51_ECSPI_STAT_RR;
637}
638
639static void mx51_ecspi_reset(struct spi_imx_data *spi_imx)
640{
641 /* drain receive buffer */
642 while (mx51_ecspi_rx_available(spi_imx))
643 readl(spi_imx->base + MXC_CSPIRXDATA);
644}
645
646#define MX31_INTREG_TEEN (1 << 0)
647#define MX31_INTREG_RREN (1 << 3)
648
649#define MX31_CSPICTRL_ENABLE (1 << 0)
650#define MX31_CSPICTRL_MASTER (1 << 1)
651#define MX31_CSPICTRL_XCH (1 << 2)
652#define MX31_CSPICTRL_SMC (1 << 3)
653#define MX31_CSPICTRL_POL (1 << 4)
654#define MX31_CSPICTRL_PHA (1 << 5)
655#define MX31_CSPICTRL_SSCTL (1 << 6)
656#define MX31_CSPICTRL_SSPOL (1 << 7)
657#define MX31_CSPICTRL_BC_SHIFT 8
658#define MX35_CSPICTRL_BL_SHIFT 20
659#define MX31_CSPICTRL_CS_SHIFT 24
660#define MX35_CSPICTRL_CS_SHIFT 12
661#define MX31_CSPICTRL_DR_SHIFT 16
662
663#define MX31_CSPI_DMAREG 0x10
664#define MX31_DMAREG_RH_DEN (1<<4)
665#define MX31_DMAREG_TH_DEN (1<<1)
666
667#define MX31_CSPISTATUS 0x14
668#define MX31_STATUS_RR (1 << 3)
669
670#define MX31_CSPI_TESTREG 0x1C
671#define MX31_TEST_LBC (1 << 14)
672
673/* These functions also work for the i.MX35, but be aware that
674 * the i.MX35 has a slightly different register layout for bits
675 * we do not use here.
676 */
677static void mx31_intctrl(struct spi_imx_data *spi_imx, int enable)
678{
679 unsigned int val = 0;
680
681 if (enable & MXC_INT_TE)
682 val |= MX31_INTREG_TEEN;
683 if (enable & MXC_INT_RR)
684 val |= MX31_INTREG_RREN;
685
686 writel(val, spi_imx->base + MXC_CSPIINT);
687}
688
689static void mx31_trigger(struct spi_imx_data *spi_imx)
690{
691 unsigned int reg;
692
693 reg = readl(spi_imx->base + MXC_CSPICTRL);
694 reg |= MX31_CSPICTRL_XCH;
695 writel(reg, spi_imx->base + MXC_CSPICTRL);
696}
697
698static int mx31_prepare_message(struct spi_imx_data *spi_imx,
699 struct spi_message *msg)
700{
701 return 0;
702}
703
704static int mx31_prepare_transfer(struct spi_imx_data *spi_imx,
705 struct spi_device *spi,
706 struct spi_transfer *t)
707{
708 unsigned int reg = MX31_CSPICTRL_ENABLE | MX31_CSPICTRL_MASTER;
709 unsigned int clk;
710
711 reg |= spi_imx_clkdiv_2(spi_imx->spi_clk, t->speed_hz, &clk) <<
712 MX31_CSPICTRL_DR_SHIFT;
713 spi_imx->spi_bus_clk = clk;
714
715 if (is_imx35_cspi(spi_imx)) {
716 reg |= (spi_imx->bits_per_word - 1) << MX35_CSPICTRL_BL_SHIFT;
717 reg |= MX31_CSPICTRL_SSCTL;
718 } else {
719 reg |= (spi_imx->bits_per_word - 1) << MX31_CSPICTRL_BC_SHIFT;
720 }
721
722 if (spi->mode & SPI_CPHA)
723 reg |= MX31_CSPICTRL_PHA;
724 if (spi->mode & SPI_CPOL)
725 reg |= MX31_CSPICTRL_POL;
726 if (spi->mode & SPI_CS_HIGH)
727 reg |= MX31_CSPICTRL_SSPOL;
728 if (!spi->cs_gpiod)
729 reg |= (spi->chip_select) <<
730 (is_imx35_cspi(spi_imx) ? MX35_CSPICTRL_CS_SHIFT :
731 MX31_CSPICTRL_CS_SHIFT);
732
733 if (spi_imx->usedma)
734 reg |= MX31_CSPICTRL_SMC;
735
736 writel(reg, spi_imx->base + MXC_CSPICTRL);
737
738 reg = readl(spi_imx->base + MX31_CSPI_TESTREG);
739 if (spi->mode & SPI_LOOP)
740 reg |= MX31_TEST_LBC;
741 else
742 reg &= ~MX31_TEST_LBC;
743 writel(reg, spi_imx->base + MX31_CSPI_TESTREG);
744
745 if (spi_imx->usedma) {
746 /*
747 * configure DMA requests when RXFIFO is half full and
748 * when TXFIFO is half empty
749 */
750 writel(MX31_DMAREG_RH_DEN | MX31_DMAREG_TH_DEN,
751 spi_imx->base + MX31_CSPI_DMAREG);
752 }
753
754 return 0;
755}
756
757static int mx31_rx_available(struct spi_imx_data *spi_imx)
758{
759 return readl(spi_imx->base + MX31_CSPISTATUS) & MX31_STATUS_RR;
760}
761
762static void mx31_reset(struct spi_imx_data *spi_imx)
763{
764 /* drain receive buffer */
765 while (readl(spi_imx->base + MX31_CSPISTATUS) & MX31_STATUS_RR)
766 readl(spi_imx->base + MXC_CSPIRXDATA);
767}
768
769#define MX21_INTREG_RR (1 << 4)
770#define MX21_INTREG_TEEN (1 << 9)
771#define MX21_INTREG_RREN (1 << 13)
772
773#define MX21_CSPICTRL_POL (1 << 5)
774#define MX21_CSPICTRL_PHA (1 << 6)
775#define MX21_CSPICTRL_SSPOL (1 << 8)
776#define MX21_CSPICTRL_XCH (1 << 9)
777#define MX21_CSPICTRL_ENABLE (1 << 10)
778#define MX21_CSPICTRL_MASTER (1 << 11)
779#define MX21_CSPICTRL_DR_SHIFT 14
780#define MX21_CSPICTRL_CS_SHIFT 19
781
782static void mx21_intctrl(struct spi_imx_data *spi_imx, int enable)
783{
784 unsigned int val = 0;
785
786 if (enable & MXC_INT_TE)
787 val |= MX21_INTREG_TEEN;
788 if (enable & MXC_INT_RR)
789 val |= MX21_INTREG_RREN;
790
791 writel(val, spi_imx->base + MXC_CSPIINT);
792}
793
794static void mx21_trigger(struct spi_imx_data *spi_imx)
795{
796 unsigned int reg;
797
798 reg = readl(spi_imx->base + MXC_CSPICTRL);
799 reg |= MX21_CSPICTRL_XCH;
800 writel(reg, spi_imx->base + MXC_CSPICTRL);
801}
802
803static int mx21_prepare_message(struct spi_imx_data *spi_imx,
804 struct spi_message *msg)
805{
806 return 0;
807}
808
809static int mx21_prepare_transfer(struct spi_imx_data *spi_imx,
810 struct spi_device *spi,
811 struct spi_transfer *t)
812{
813 unsigned int reg = MX21_CSPICTRL_ENABLE | MX21_CSPICTRL_MASTER;
814 unsigned int max = is_imx27_cspi(spi_imx) ? 16 : 18;
815 unsigned int clk;
816
817 reg |= spi_imx_clkdiv_1(spi_imx->spi_clk, t->speed_hz, max, &clk)
818 << MX21_CSPICTRL_DR_SHIFT;
819 spi_imx->spi_bus_clk = clk;
820
821 reg |= spi_imx->bits_per_word - 1;
822
823 if (spi->mode & SPI_CPHA)
824 reg |= MX21_CSPICTRL_PHA;
825 if (spi->mode & SPI_CPOL)
826 reg |= MX21_CSPICTRL_POL;
827 if (spi->mode & SPI_CS_HIGH)
828 reg |= MX21_CSPICTRL_SSPOL;
829 if (!spi->cs_gpiod)
830 reg |= spi->chip_select << MX21_CSPICTRL_CS_SHIFT;
831
832 writel(reg, spi_imx->base + MXC_CSPICTRL);
833
834 return 0;
835}
836
837static int mx21_rx_available(struct spi_imx_data *spi_imx)
838{
839 return readl(spi_imx->base + MXC_CSPIINT) & MX21_INTREG_RR;
840}
841
842static void mx21_reset(struct spi_imx_data *spi_imx)
843{
844 writel(1, spi_imx->base + MXC_RESET);
845}
846
847#define MX1_INTREG_RR (1 << 3)
848#define MX1_INTREG_TEEN (1 << 8)
849#define MX1_INTREG_RREN (1 << 11)
850
851#define MX1_CSPICTRL_POL (1 << 4)
852#define MX1_CSPICTRL_PHA (1 << 5)
853#define MX1_CSPICTRL_XCH (1 << 8)
854#define MX1_CSPICTRL_ENABLE (1 << 9)
855#define MX1_CSPICTRL_MASTER (1 << 10)
856#define MX1_CSPICTRL_DR_SHIFT 13
857
858static void mx1_intctrl(struct spi_imx_data *spi_imx, int enable)
859{
860 unsigned int val = 0;
861
862 if (enable & MXC_INT_TE)
863 val |= MX1_INTREG_TEEN;
864 if (enable & MXC_INT_RR)
865 val |= MX1_INTREG_RREN;
866
867 writel(val, spi_imx->base + MXC_CSPIINT);
868}
869
870static void mx1_trigger(struct spi_imx_data *spi_imx)
871{
872 unsigned int reg;
873
874 reg = readl(spi_imx->base + MXC_CSPICTRL);
875 reg |= MX1_CSPICTRL_XCH;
876 writel(reg, spi_imx->base + MXC_CSPICTRL);
877}
878
879static int mx1_prepare_message(struct spi_imx_data *spi_imx,
880 struct spi_message *msg)
881{
882 return 0;
883}
884
885static int mx1_prepare_transfer(struct spi_imx_data *spi_imx,
886 struct spi_device *spi,
887 struct spi_transfer *t)
888{
889 unsigned int reg = MX1_CSPICTRL_ENABLE | MX1_CSPICTRL_MASTER;
890 unsigned int clk;
891
892 reg |= spi_imx_clkdiv_2(spi_imx->spi_clk, t->speed_hz, &clk) <<
893 MX1_CSPICTRL_DR_SHIFT;
894 spi_imx->spi_bus_clk = clk;
895
896 reg |= spi_imx->bits_per_word - 1;
897
898 if (spi->mode & SPI_CPHA)
899 reg |= MX1_CSPICTRL_PHA;
900 if (spi->mode & SPI_CPOL)
901 reg |= MX1_CSPICTRL_POL;
902
903 writel(reg, spi_imx->base + MXC_CSPICTRL);
904
905 return 0;
906}
907
908static int mx1_rx_available(struct spi_imx_data *spi_imx)
909{
910 return readl(spi_imx->base + MXC_CSPIINT) & MX1_INTREG_RR;
911}
912
913static void mx1_reset(struct spi_imx_data *spi_imx)
914{
915 writel(1, spi_imx->base + MXC_RESET);
916}
917
918static struct spi_imx_devtype_data imx1_cspi_devtype_data = {
919 .intctrl = mx1_intctrl,
920 .prepare_message = mx1_prepare_message,
921 .prepare_transfer = mx1_prepare_transfer,
922 .trigger = mx1_trigger,
923 .rx_available = mx1_rx_available,
924 .reset = mx1_reset,
925 .fifo_size = 8,
926 .has_dmamode = false,
927 .dynamic_burst = false,
928 .has_slavemode = false,
929 .devtype = IMX1_CSPI,
930};
931
932static struct spi_imx_devtype_data imx21_cspi_devtype_data = {
933 .intctrl = mx21_intctrl,
934 .prepare_message = mx21_prepare_message,
935 .prepare_transfer = mx21_prepare_transfer,
936 .trigger = mx21_trigger,
937 .rx_available = mx21_rx_available,
938 .reset = mx21_reset,
939 .fifo_size = 8,
940 .has_dmamode = false,
941 .dynamic_burst = false,
942 .has_slavemode = false,
943 .devtype = IMX21_CSPI,
944};
945
946static struct spi_imx_devtype_data imx27_cspi_devtype_data = {
947 /* i.mx27 cspi shares the functions with i.mx21 one */
948 .intctrl = mx21_intctrl,
949 .prepare_message = mx21_prepare_message,
950 .prepare_transfer = mx21_prepare_transfer,
951 .trigger = mx21_trigger,
952 .rx_available = mx21_rx_available,
953 .reset = mx21_reset,
954 .fifo_size = 8,
955 .has_dmamode = false,
956 .dynamic_burst = false,
957 .has_slavemode = false,
958 .devtype = IMX27_CSPI,
959};
960
961static struct spi_imx_devtype_data imx31_cspi_devtype_data = {
962 .intctrl = mx31_intctrl,
963 .prepare_message = mx31_prepare_message,
964 .prepare_transfer = mx31_prepare_transfer,
965 .trigger = mx31_trigger,
966 .rx_available = mx31_rx_available,
967 .reset = mx31_reset,
968 .fifo_size = 8,
969 .has_dmamode = false,
970 .dynamic_burst = false,
971 .has_slavemode = false,
972 .devtype = IMX31_CSPI,
973};
974
975static struct spi_imx_devtype_data imx35_cspi_devtype_data = {
976 /* i.mx35 and later cspi shares the functions with i.mx31 one */
977 .intctrl = mx31_intctrl,
978 .prepare_message = mx31_prepare_message,
979 .prepare_transfer = mx31_prepare_transfer,
980 .trigger = mx31_trigger,
981 .rx_available = mx31_rx_available,
982 .reset = mx31_reset,
983 .fifo_size = 8,
984 .has_dmamode = true,
985 .dynamic_burst = false,
986 .has_slavemode = false,
987 .devtype = IMX35_CSPI,
988};
989
990static struct spi_imx_devtype_data imx51_ecspi_devtype_data = {
991 .intctrl = mx51_ecspi_intctrl,
992 .prepare_message = mx51_ecspi_prepare_message,
993 .prepare_transfer = mx51_ecspi_prepare_transfer,
994 .trigger = mx51_ecspi_trigger,
995 .rx_available = mx51_ecspi_rx_available,
996 .reset = mx51_ecspi_reset,
997 .setup_wml = mx51_setup_wml,
998 .disable_dma = mx51_disable_dma,
999 .fifo_size = 64,
1000 .has_dmamode = true,
1001 .dynamic_burst = true,
1002 .has_slavemode = true,
1003 .disable = mx51_ecspi_disable,
1004 .devtype = IMX51_ECSPI,
1005};
1006
1007static struct spi_imx_devtype_data imx53_ecspi_devtype_data = {
1008 .intctrl = mx51_ecspi_intctrl,
1009 .prepare_message = mx51_ecspi_prepare_message,
1010 .prepare_transfer = mx51_ecspi_prepare_transfer,
1011 .trigger = mx51_ecspi_trigger,
1012 .rx_available = mx51_ecspi_rx_available,
1013 .disable_dma = mx51_disable_dma,
1014 .reset = mx51_ecspi_reset,
1015 .fifo_size = 64,
1016 .has_dmamode = true,
1017 .has_slavemode = true,
1018 .disable = mx51_ecspi_disable,
1019 .devtype = IMX53_ECSPI,
1020};
1021
1022static const struct platform_device_id spi_imx_devtype[] = {
1023 {
1024 .name = "imx1-cspi",
1025 .driver_data = (kernel_ulong_t) &imx1_cspi_devtype_data,
1026 }, {
1027 .name = "imx21-cspi",
1028 .driver_data = (kernel_ulong_t) &imx21_cspi_devtype_data,
1029 }, {
1030 .name = "imx27-cspi",
1031 .driver_data = (kernel_ulong_t) &imx27_cspi_devtype_data,
1032 }, {
1033 .name = "imx31-cspi",
1034 .driver_data = (kernel_ulong_t) &imx31_cspi_devtype_data,
1035 }, {
1036 .name = "imx35-cspi",
1037 .driver_data = (kernel_ulong_t) &imx35_cspi_devtype_data,
1038 }, {
1039 .name = "imx51-ecspi",
1040 .driver_data = (kernel_ulong_t) &imx51_ecspi_devtype_data,
1041 }, {
1042 .name = "imx53-ecspi",
1043 .driver_data = (kernel_ulong_t) &imx53_ecspi_devtype_data,
1044 }, {
1045 /* sentinel */
1046 }
1047};
1048
1049static const struct of_device_id spi_imx_dt_ids[] = {
1050 { .compatible = "fsl,imx1-cspi", .data = &imx1_cspi_devtype_data, },
1051 { .compatible = "fsl,imx21-cspi", .data = &imx21_cspi_devtype_data, },
1052 { .compatible = "fsl,imx27-cspi", .data = &imx27_cspi_devtype_data, },
1053 { .compatible = "fsl,imx31-cspi", .data = &imx31_cspi_devtype_data, },
1054 { .compatible = "fsl,imx35-cspi", .data = &imx35_cspi_devtype_data, },
1055 { .compatible = "fsl,imx51-ecspi", .data = &imx51_ecspi_devtype_data, },
1056 { .compatible = "fsl,imx53-ecspi", .data = &imx53_ecspi_devtype_data, },
1057 { /* sentinel */ }
1058};
1059MODULE_DEVICE_TABLE(of, spi_imx_dt_ids);
1060
1061static void spi_imx_set_burst_len(struct spi_imx_data *spi_imx, int n_bits)
1062{
1063 u32 ctrl;
1064
1065 ctrl = readl(spi_imx->base + MX51_ECSPI_CTRL);
1066 ctrl &= ~MX51_ECSPI_CTRL_BL_MASK;
1067 ctrl |= ((n_bits - 1) << MX51_ECSPI_CTRL_BL_OFFSET);
1068 writel(ctrl, spi_imx->base + MX51_ECSPI_CTRL);
1069}
1070
1071static void spi_imx_push(struct spi_imx_data *spi_imx)
1072{
1073 unsigned int burst_len, fifo_words;
1074
1075 if (spi_imx->dynamic_burst)
1076 fifo_words = 4;
1077 else
1078 fifo_words = spi_imx_bytes_per_word(spi_imx->bits_per_word);
1079 /*
1080 * Reload the FIFO when the remaining bytes to be transferred in the
1081 * current burst is 0. This only applies when bits_per_word is a
1082 * multiple of 8.
1083 */
1084 if (!spi_imx->remainder) {
1085 if (spi_imx->dynamic_burst) {
1086
1087 /* We need to deal unaligned data first */
1088 burst_len = spi_imx->count % MX51_ECSPI_CTRL_MAX_BURST;
1089
1090 if (!burst_len)
1091 burst_len = MX51_ECSPI_CTRL_MAX_BURST;
1092
1093 spi_imx_set_burst_len(spi_imx, burst_len * 8);
1094
1095 spi_imx->remainder = burst_len;
1096 } else {
1097 spi_imx->remainder = fifo_words;
1098 }
1099 }
1100
1101 while (spi_imx->txfifo < spi_imx->devtype_data->fifo_size) {
1102 if (!spi_imx->count)
1103 break;
1104 if (spi_imx->dynamic_burst &&
1105 spi_imx->txfifo >= DIV_ROUND_UP(spi_imx->remainder,
1106 fifo_words))
1107 break;
1108 spi_imx->tx(spi_imx);
1109 spi_imx->txfifo++;
1110 }
1111
1112 if (!spi_imx->slave_mode)
1113 spi_imx->devtype_data->trigger(spi_imx);
1114}
1115
1116static irqreturn_t spi_imx_isr(int irq, void *dev_id)
1117{
1118 struct spi_imx_data *spi_imx = dev_id;
1119
1120 while (spi_imx->txfifo &&
1121 spi_imx->devtype_data->rx_available(spi_imx)) {
1122 spi_imx->rx(spi_imx);
1123 spi_imx->txfifo--;
1124 }
1125
1126 if (spi_imx->count) {
1127 spi_imx_push(spi_imx);
1128 return IRQ_HANDLED;
1129 }
1130
1131 if (spi_imx->txfifo) {
1132 /* No data left to push, but still waiting for rx data,
1133 * enable receive data available interrupt.
1134 */
1135 spi_imx->devtype_data->intctrl(
1136 spi_imx, MXC_INT_RR);
1137 return IRQ_HANDLED;
1138 }
1139
1140 spi_imx->devtype_data->intctrl(spi_imx, 0);
1141 complete(&spi_imx->xfer_done);
1142
1143 return IRQ_HANDLED;
1144}
1145
1146static int spi_imx_dma_configure(struct spi_master *master)
1147{
1148 int ret;
1149 enum dma_slave_buswidth buswidth;
1150 struct dma_slave_config rx = {}, tx = {};
1151 struct spi_imx_data *spi_imx = spi_master_get_devdata(master);
1152
1153 switch (spi_imx_bytes_per_word(spi_imx->bits_per_word)) {
1154 case 4:
1155 buswidth = DMA_SLAVE_BUSWIDTH_4_BYTES;
1156 break;
1157 case 2:
1158 buswidth = DMA_SLAVE_BUSWIDTH_2_BYTES;
1159 break;
1160 case 1:
1161 buswidth = DMA_SLAVE_BUSWIDTH_1_BYTE;
1162 break;
1163 default:
1164 return -EINVAL;
1165 }
1166
1167 tx.direction = DMA_MEM_TO_DEV;
1168 tx.dst_addr = spi_imx->base_phys + MXC_CSPITXDATA;
1169 tx.dst_addr_width = buswidth;
1170 tx.dst_maxburst = spi_imx->wml;
1171 ret = dmaengine_slave_config(master->dma_tx, &tx);
1172 if (ret) {
1173 dev_err(spi_imx->dev, "TX dma configuration failed with %d\n", ret);
1174 return ret;
1175 }
1176
1177 rx.direction = DMA_DEV_TO_MEM;
1178 rx.src_addr = spi_imx->base_phys + MXC_CSPIRXDATA;
1179 rx.src_addr_width = buswidth;
1180 rx.src_maxburst = spi_imx->wml;
1181 ret = dmaengine_slave_config(master->dma_rx, &rx);
1182 if (ret) {
1183 dev_err(spi_imx->dev, "RX dma configuration failed with %d\n", ret);
1184 return ret;
1185 }
1186
1187 return 0;
1188}
1189
1190static int spi_imx_setupxfer(struct spi_device *spi,
1191 struct spi_transfer *t)
1192{
1193 struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
1194
1195 if (!t)
1196 return 0;
1197
1198 spi_imx->bits_per_word = t->bits_per_word;
1199
1200 /*
1201 * Initialize the functions for transfer. To transfer non byte-aligned
1202 * words, we have to use multiple word-size bursts, we can't use
1203 * dynamic_burst in that case.
1204 */
1205 if (spi_imx->devtype_data->dynamic_burst && !spi_imx->slave_mode &&
1206 (spi_imx->bits_per_word == 8 ||
1207 spi_imx->bits_per_word == 16 ||
1208 spi_imx->bits_per_word == 32)) {
1209
1210 spi_imx->rx = spi_imx_buf_rx_swap;
1211 spi_imx->tx = spi_imx_buf_tx_swap;
1212 spi_imx->dynamic_burst = 1;
1213
1214 } else {
1215 if (spi_imx->bits_per_word <= 8) {
1216 spi_imx->rx = spi_imx_buf_rx_u8;
1217 spi_imx->tx = spi_imx_buf_tx_u8;
1218 } else if (spi_imx->bits_per_word <= 16) {
1219 spi_imx->rx = spi_imx_buf_rx_u16;
1220 spi_imx->tx = spi_imx_buf_tx_u16;
1221 } else {
1222 spi_imx->rx = spi_imx_buf_rx_u32;
1223 spi_imx->tx = spi_imx_buf_tx_u32;
1224 }
1225 spi_imx->dynamic_burst = 0;
1226 }
1227
1228 if (spi_imx_can_dma(spi_imx->bitbang.master, spi, t))
1229 spi_imx->usedma = true;
1230 else
1231 spi_imx->usedma = false;
1232
1233 if (is_imx53_ecspi(spi_imx) && spi_imx->slave_mode) {
1234 spi_imx->rx = mx53_ecspi_rx_slave;
1235 spi_imx->tx = mx53_ecspi_tx_slave;
1236 spi_imx->slave_burst = t->len;
1237 }
1238
1239 spi_imx->devtype_data->prepare_transfer(spi_imx, spi, t);
1240
1241 return 0;
1242}
1243
1244static void spi_imx_sdma_exit(struct spi_imx_data *spi_imx)
1245{
1246 struct spi_master *master = spi_imx->bitbang.master;
1247
1248 if (master->dma_rx) {
1249 dma_release_channel(master->dma_rx);
1250 master->dma_rx = NULL;
1251 }
1252
1253 if (master->dma_tx) {
1254 dma_release_channel(master->dma_tx);
1255 master->dma_tx = NULL;
1256 }
1257}
1258
1259static int spi_imx_sdma_init(struct device *dev, struct spi_imx_data *spi_imx,
1260 struct spi_master *master)
1261{
1262 int ret;
1263
1264 /* use pio mode for i.mx6dl chip TKT238285 */
1265 if (of_machine_is_compatible("fsl,imx6dl"))
1266 return 0;
1267
1268 spi_imx->wml = spi_imx->devtype_data->fifo_size / 2;
1269
1270 /* Prepare for TX DMA: */
1271 master->dma_tx = dma_request_chan(dev, "tx");
1272 if (IS_ERR(master->dma_tx)) {
1273 ret = PTR_ERR(master->dma_tx);
1274 dev_dbg(dev, "can't get the TX DMA channel, error %d!\n", ret);
1275 master->dma_tx = NULL;
1276 goto err;
1277 }
1278
1279 /* Prepare for RX : */
1280 master->dma_rx = dma_request_chan(dev, "rx");
1281 if (IS_ERR(master->dma_rx)) {
1282 ret = PTR_ERR(master->dma_rx);
1283 dev_dbg(dev, "can't get the RX DMA channel, error %d\n", ret);
1284 master->dma_rx = NULL;
1285 goto err;
1286 }
1287
1288 init_completion(&spi_imx->dma_rx_completion);
1289 init_completion(&spi_imx->dma_tx_completion);
1290 master->can_dma = spi_imx_can_dma;
1291 master->max_dma_len = MAX_SDMA_BD_BYTES;
1292 spi_imx->bitbang.master->flags = SPI_MASTER_MUST_RX |
1293 SPI_MASTER_MUST_TX;
1294
1295 return 0;
1296err:
1297 spi_imx_sdma_exit(spi_imx);
1298 return ret;
1299}
1300
1301static void spi_imx_dma_rx_callback(void *cookie)
1302{
1303 struct spi_imx_data *spi_imx = (struct spi_imx_data *)cookie;
1304
1305 complete(&spi_imx->dma_rx_completion);
1306}
1307
1308static void spi_imx_dma_tx_callback(void *cookie)
1309{
1310 struct spi_imx_data *spi_imx = (struct spi_imx_data *)cookie;
1311
1312 complete(&spi_imx->dma_tx_completion);
1313}
1314
1315static int spi_imx_calculate_timeout(struct spi_imx_data *spi_imx, int size)
1316{
1317 unsigned long timeout = 0;
1318
1319 /* Time with actual data transfer and CS change delay related to HW */
1320 timeout = (8 + 4) * size / spi_imx->spi_bus_clk;
1321
1322 /* Add extra second for scheduler related activities */
1323 timeout += 1;
1324
1325 /* Double calculated timeout */
1326 return msecs_to_jiffies(2 * timeout * MSEC_PER_SEC);
1327}
1328
1329static int spi_imx_dma_transfer(struct spi_imx_data *spi_imx,
1330 struct spi_transfer *transfer)
1331{
1332 struct dma_async_tx_descriptor *desc_tx, *desc_rx;
1333 unsigned long transfer_timeout;
1334 unsigned long timeout;
1335 struct spi_master *master = spi_imx->bitbang.master;
1336 struct sg_table *tx = &transfer->tx_sg, *rx = &transfer->rx_sg;
1337 struct scatterlist *last_sg = sg_last(rx->sgl, rx->nents);
1338 unsigned int bytes_per_word, i;
1339 int ret;
1340
1341 /* Get the right burst length from the last sg to ensure no tail data */
1342 bytes_per_word = spi_imx_bytes_per_word(transfer->bits_per_word);
1343 for (i = spi_imx->devtype_data->fifo_size / 2; i > 0; i--) {
1344 if (!(sg_dma_len(last_sg) % (i * bytes_per_word)))
1345 break;
1346 }
1347 /* Use 1 as wml in case no available burst length got */
1348 if (i == 0)
1349 i = 1;
1350
1351 spi_imx->wml = i;
1352
1353 ret = spi_imx_dma_configure(master);
1354 if (ret)
1355 goto dma_failure_no_start;
1356
1357 if (!spi_imx->devtype_data->setup_wml) {
1358 dev_err(spi_imx->dev, "No setup_wml()?\n");
1359 ret = -EINVAL;
1360 goto dma_failure_no_start;
1361 }
1362 spi_imx->devtype_data->setup_wml(spi_imx);
1363
1364 /*
1365 * The TX DMA setup starts the transfer, so make sure RX is configured
1366 * before TX.
1367 */
1368 desc_rx = dmaengine_prep_slave_sg(master->dma_rx,
1369 rx->sgl, rx->nents, DMA_DEV_TO_MEM,
1370 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1371 if (!desc_rx) {
1372 ret = -EINVAL;
1373 goto dma_failure_no_start;
1374 }
1375
1376 desc_rx->callback = spi_imx_dma_rx_callback;
1377 desc_rx->callback_param = (void *)spi_imx;
1378 dmaengine_submit(desc_rx);
1379 reinit_completion(&spi_imx->dma_rx_completion);
1380 dma_async_issue_pending(master->dma_rx);
1381
1382 desc_tx = dmaengine_prep_slave_sg(master->dma_tx,
1383 tx->sgl, tx->nents, DMA_MEM_TO_DEV,
1384 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1385 if (!desc_tx) {
1386 dmaengine_terminate_all(master->dma_tx);
1387 dmaengine_terminate_all(master->dma_rx);
1388 return -EINVAL;
1389 }
1390
1391 desc_tx->callback = spi_imx_dma_tx_callback;
1392 desc_tx->callback_param = (void *)spi_imx;
1393 dmaengine_submit(desc_tx);
1394 reinit_completion(&spi_imx->dma_tx_completion);
1395 dma_async_issue_pending(master->dma_tx);
1396
1397 transfer_timeout = spi_imx_calculate_timeout(spi_imx, transfer->len);
1398
1399 /* Wait SDMA to finish the data transfer.*/
1400 timeout = wait_for_completion_timeout(&spi_imx->dma_tx_completion,
1401 transfer_timeout);
1402 if (!timeout) {
1403 dev_err(spi_imx->dev, "I/O Error in DMA TX\n");
1404 dmaengine_terminate_all(master->dma_tx);
1405 dmaengine_terminate_all(master->dma_rx);
1406 return -ETIMEDOUT;
1407 }
1408
1409 timeout = wait_for_completion_timeout(&spi_imx->dma_rx_completion,
1410 transfer_timeout);
1411 if (!timeout) {
1412 dev_err(&master->dev, "I/O Error in DMA RX\n");
1413 spi_imx->devtype_data->reset(spi_imx);
1414 dmaengine_terminate_all(master->dma_rx);
1415 return -ETIMEDOUT;
1416 }
1417
1418 return transfer->len;
1419/* fallback to pio */
1420dma_failure_no_start:
1421 transfer->error |= SPI_TRANS_FAIL_NO_START;
1422 return ret;
1423}
1424
1425static int spi_imx_pio_transfer(struct spi_device *spi,
1426 struct spi_transfer *transfer)
1427{
1428 struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
1429 unsigned long transfer_timeout;
1430 unsigned long timeout;
1431
1432 spi_imx->tx_buf = transfer->tx_buf;
1433 spi_imx->rx_buf = transfer->rx_buf;
1434 spi_imx->count = transfer->len;
1435 spi_imx->txfifo = 0;
1436 spi_imx->remainder = 0;
1437
1438 reinit_completion(&spi_imx->xfer_done);
1439
1440 spi_imx_push(spi_imx);
1441
1442 spi_imx->devtype_data->intctrl(spi_imx, MXC_INT_TE);
1443
1444 transfer_timeout = spi_imx_calculate_timeout(spi_imx, transfer->len);
1445
1446 timeout = wait_for_completion_timeout(&spi_imx->xfer_done,
1447 transfer_timeout);
1448 if (!timeout) {
1449 dev_err(&spi->dev, "I/O Error in PIO\n");
1450 spi_imx->devtype_data->reset(spi_imx);
1451 return -ETIMEDOUT;
1452 }
1453
1454 return transfer->len;
1455}
1456
1457static int spi_imx_pio_transfer_slave(struct spi_device *spi,
1458 struct spi_transfer *transfer)
1459{
1460 struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
1461 int ret = transfer->len;
1462
1463 if (is_imx53_ecspi(spi_imx) &&
1464 transfer->len > MX53_MAX_TRANSFER_BYTES) {
1465 dev_err(&spi->dev, "Transaction too big, max size is %d bytes\n",
1466 MX53_MAX_TRANSFER_BYTES);
1467 return -EMSGSIZE;
1468 }
1469
1470 spi_imx->tx_buf = transfer->tx_buf;
1471 spi_imx->rx_buf = transfer->rx_buf;
1472 spi_imx->count = transfer->len;
1473 spi_imx->txfifo = 0;
1474 spi_imx->remainder = 0;
1475
1476 reinit_completion(&spi_imx->xfer_done);
1477 spi_imx->slave_aborted = false;
1478
1479 spi_imx_push(spi_imx);
1480
1481 spi_imx->devtype_data->intctrl(spi_imx, MXC_INT_TE | MXC_INT_RDR);
1482
1483 if (wait_for_completion_interruptible(&spi_imx->xfer_done) ||
1484 spi_imx->slave_aborted) {
1485 dev_dbg(&spi->dev, "interrupted\n");
1486 ret = -EINTR;
1487 }
1488
1489 /* ecspi has a HW issue when works in Slave mode,
1490 * after 64 words writtern to TXFIFO, even TXFIFO becomes empty,
1491 * ECSPI_TXDATA keeps shift out the last word data,
1492 * so we have to disable ECSPI when in slave mode after the
1493 * transfer completes
1494 */
1495 if (spi_imx->devtype_data->disable)
1496 spi_imx->devtype_data->disable(spi_imx);
1497
1498 return ret;
1499}
1500
1501static int spi_imx_transfer(struct spi_device *spi,
1502 struct spi_transfer *transfer)
1503{
1504 struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
1505
1506 /* flush rxfifo before transfer */
1507 while (spi_imx->devtype_data->rx_available(spi_imx))
1508 readl(spi_imx->base + MXC_CSPIRXDATA);
1509
1510 if (spi_imx->slave_mode)
1511 return spi_imx_pio_transfer_slave(spi, transfer);
1512
1513 if (spi_imx->usedma)
1514 return spi_imx_dma_transfer(spi_imx, transfer);
1515
1516 return spi_imx_pio_transfer(spi, transfer);
1517}
1518
1519static int spi_imx_setup(struct spi_device *spi)
1520{
1521 dev_dbg(&spi->dev, "%s: mode %d, %u bpw, %d hz\n", __func__,
1522 spi->mode, spi->bits_per_word, spi->max_speed_hz);
1523
1524 return 0;
1525}
1526
1527static void spi_imx_cleanup(struct spi_device *spi)
1528{
1529}
1530
1531static int
1532spi_imx_prepare_message(struct spi_master *master, struct spi_message *msg)
1533{
1534 struct spi_imx_data *spi_imx = spi_master_get_devdata(master);
1535 int ret;
1536
1537 ret = pm_runtime_get_sync(spi_imx->dev);
1538 if (ret < 0) {
1539 dev_err(spi_imx->dev, "failed to enable clock\n");
1540 return ret;
1541 }
1542
1543 ret = spi_imx->devtype_data->prepare_message(spi_imx, msg);
1544 if (ret) {
1545 pm_runtime_mark_last_busy(spi_imx->dev);
1546 pm_runtime_put_autosuspend(spi_imx->dev);
1547 }
1548
1549 return ret;
1550}
1551
1552static int
1553spi_imx_unprepare_message(struct spi_master *master, struct spi_message *msg)
1554{
1555 struct spi_imx_data *spi_imx = spi_master_get_devdata(master);
1556
1557 pm_runtime_mark_last_busy(spi_imx->dev);
1558 pm_runtime_put_autosuspend(spi_imx->dev);
1559 return 0;
1560}
1561
1562static int spi_imx_slave_abort(struct spi_master *master)
1563{
1564 struct spi_imx_data *spi_imx = spi_master_get_devdata(master);
1565
1566 spi_imx->slave_aborted = true;
1567 complete(&spi_imx->xfer_done);
1568
1569 return 0;
1570}
1571
1572static int spi_imx_probe(struct platform_device *pdev)
1573{
1574 struct device_node *np = pdev->dev.of_node;
1575 const struct of_device_id *of_id =
1576 of_match_device(spi_imx_dt_ids, &pdev->dev);
1577 struct spi_master *master;
1578 struct spi_imx_data *spi_imx;
1579 struct resource *res;
1580 int ret, irq, spi_drctl;
1581 const struct spi_imx_devtype_data *devtype_data = of_id ? of_id->data :
1582 (struct spi_imx_devtype_data *)pdev->id_entry->driver_data;
1583 bool slave_mode;
1584 u32 val;
1585
1586 slave_mode = devtype_data->has_slavemode &&
1587 of_property_read_bool(np, "spi-slave");
1588 if (slave_mode)
1589 master = spi_alloc_slave(&pdev->dev,
1590 sizeof(struct spi_imx_data));
1591 else
1592 master = spi_alloc_master(&pdev->dev,
1593 sizeof(struct spi_imx_data));
1594 if (!master)
1595 return -ENOMEM;
1596
1597 ret = of_property_read_u32(np, "fsl,spi-rdy-drctl", &spi_drctl);
1598 if ((ret < 0) || (spi_drctl >= 0x3)) {
1599 /* '11' is reserved */
1600 spi_drctl = 0;
1601 }
1602
1603 platform_set_drvdata(pdev, master);
1604
1605 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(1, 32);
1606 master->bus_num = np ? -1 : pdev->id;
1607 master->use_gpio_descriptors = true;
1608
1609 spi_imx = spi_master_get_devdata(master);
1610 spi_imx->bitbang.master = master;
1611 spi_imx->dev = &pdev->dev;
1612 spi_imx->slave_mode = slave_mode;
1613
1614 spi_imx->devtype_data = devtype_data;
1615
1616 /*
1617 * Get number of chip selects from device properties. This can be
1618 * coming from device tree or boardfiles, if it is not defined,
1619 * a default value of 3 chip selects will be used, as all the legacy
1620 * board files have <= 3 chip selects.
1621 */
1622 if (!device_property_read_u32(&pdev->dev, "num-cs", &val))
1623 master->num_chipselect = val;
1624 else
1625 master->num_chipselect = 3;
1626
1627 spi_imx->bitbang.setup_transfer = spi_imx_setupxfer;
1628 spi_imx->bitbang.txrx_bufs = spi_imx_transfer;
1629 spi_imx->bitbang.master->setup = spi_imx_setup;
1630 spi_imx->bitbang.master->cleanup = spi_imx_cleanup;
1631 spi_imx->bitbang.master->prepare_message = spi_imx_prepare_message;
1632 spi_imx->bitbang.master->unprepare_message = spi_imx_unprepare_message;
1633 spi_imx->bitbang.master->slave_abort = spi_imx_slave_abort;
1634 spi_imx->bitbang.master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH \
1635 | SPI_NO_CS;
1636 if (is_imx35_cspi(spi_imx) || is_imx51_ecspi(spi_imx) ||
1637 is_imx53_ecspi(spi_imx))
1638 spi_imx->bitbang.master->mode_bits |= SPI_LOOP | SPI_READY;
1639
1640 spi_imx->spi_drctl = spi_drctl;
1641
1642 init_completion(&spi_imx->xfer_done);
1643
1644 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1645 spi_imx->base = devm_ioremap_resource(&pdev->dev, res);
1646 if (IS_ERR(spi_imx->base)) {
1647 ret = PTR_ERR(spi_imx->base);
1648 goto out_master_put;
1649 }
1650 spi_imx->base_phys = res->start;
1651
1652 irq = platform_get_irq(pdev, 0);
1653 if (irq < 0) {
1654 ret = irq;
1655 goto out_master_put;
1656 }
1657
1658 ret = devm_request_irq(&pdev->dev, irq, spi_imx_isr, 0,
1659 dev_name(&pdev->dev), spi_imx);
1660 if (ret) {
1661 dev_err(&pdev->dev, "can't get irq%d: %d\n", irq, ret);
1662 goto out_master_put;
1663 }
1664
1665 spi_imx->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
1666 if (IS_ERR(spi_imx->clk_ipg)) {
1667 ret = PTR_ERR(spi_imx->clk_ipg);
1668 goto out_master_put;
1669 }
1670
1671 spi_imx->clk_per = devm_clk_get(&pdev->dev, "per");
1672 if (IS_ERR(spi_imx->clk_per)) {
1673 ret = PTR_ERR(spi_imx->clk_per);
1674 goto out_master_put;
1675 }
1676
1677 pm_runtime_enable(spi_imx->dev);
1678 pm_runtime_set_autosuspend_delay(spi_imx->dev, MXC_RPM_TIMEOUT);
1679 pm_runtime_use_autosuspend(spi_imx->dev);
1680
1681 ret = pm_runtime_get_sync(spi_imx->dev);
1682 if (ret < 0) {
1683 dev_err(spi_imx->dev, "failed to enable clock\n");
1684 goto out_runtime_pm_put;
1685 }
1686
1687 spi_imx->spi_clk = clk_get_rate(spi_imx->clk_per);
1688 /*
1689 * Only validated on i.mx35 and i.mx6 now, can remove the constraint
1690 * if validated on other chips.
1691 */
1692 if (spi_imx->devtype_data->has_dmamode) {
1693 ret = spi_imx_sdma_init(&pdev->dev, spi_imx, master);
1694 if (ret == -EPROBE_DEFER)
1695 goto out_runtime_pm_put;
1696
1697 if (ret < 0)
1698 dev_err(&pdev->dev, "dma setup error %d, use pio\n",
1699 ret);
1700 }
1701
1702 spi_imx->devtype_data->reset(spi_imx);
1703
1704 spi_imx->devtype_data->intctrl(spi_imx, 0);
1705
1706 master->dev.of_node = pdev->dev.of_node;
1707 ret = spi_bitbang_start(&spi_imx->bitbang);
1708 if (ret) {
1709 dev_err(&pdev->dev, "bitbang start failed with %d\n", ret);
1710 goto out_runtime_pm_put;
1711 }
1712
1713 dev_info(&pdev->dev, "probed\n");
1714
1715 pm_runtime_mark_last_busy(spi_imx->dev);
1716 pm_runtime_put_autosuspend(spi_imx->dev);
1717
1718 return ret;
1719
1720out_runtime_pm_put:
1721 pm_runtime_dont_use_autosuspend(spi_imx->dev);
1722 pm_runtime_put_sync(spi_imx->dev);
1723 pm_runtime_disable(spi_imx->dev);
1724out_master_put:
1725 spi_master_put(master);
1726
1727 return ret;
1728}
1729
1730static int spi_imx_remove(struct platform_device *pdev)
1731{
1732 struct spi_master *master = platform_get_drvdata(pdev);
1733 struct spi_imx_data *spi_imx = spi_master_get_devdata(master);
1734 int ret;
1735
1736 spi_bitbang_stop(&spi_imx->bitbang);
1737
1738 ret = pm_runtime_get_sync(spi_imx->dev);
1739 if (ret < 0) {
1740 dev_err(spi_imx->dev, "failed to enable clock\n");
1741 return ret;
1742 }
1743
1744 writel(0, spi_imx->base + MXC_CSPICTRL);
1745
1746 pm_runtime_dont_use_autosuspend(spi_imx->dev);
1747 pm_runtime_put_sync(spi_imx->dev);
1748 pm_runtime_disable(spi_imx->dev);
1749
1750 spi_imx_sdma_exit(spi_imx);
1751 spi_master_put(master);
1752
1753 return 0;
1754}
1755
1756static int __maybe_unused spi_imx_runtime_resume(struct device *dev)
1757{
1758 struct spi_master *master = dev_get_drvdata(dev);
1759 struct spi_imx_data *spi_imx;
1760 int ret;
1761
1762 spi_imx = spi_master_get_devdata(master);
1763
1764 ret = clk_prepare_enable(spi_imx->clk_per);
1765 if (ret)
1766 return ret;
1767
1768 ret = clk_prepare_enable(spi_imx->clk_ipg);
1769 if (ret) {
1770 clk_disable_unprepare(spi_imx->clk_per);
1771 return ret;
1772 }
1773
1774 return 0;
1775}
1776
1777static int __maybe_unused spi_imx_runtime_suspend(struct device *dev)
1778{
1779 struct spi_master *master = dev_get_drvdata(dev);
1780 struct spi_imx_data *spi_imx;
1781
1782 spi_imx = spi_master_get_devdata(master);
1783
1784 clk_disable_unprepare(spi_imx->clk_per);
1785 clk_disable_unprepare(spi_imx->clk_ipg);
1786
1787 return 0;
1788}
1789
1790static int __maybe_unused spi_imx_suspend(struct device *dev)
1791{
1792 pinctrl_pm_select_sleep_state(dev);
1793 return 0;
1794}
1795
1796static int __maybe_unused spi_imx_resume(struct device *dev)
1797{
1798 pinctrl_pm_select_default_state(dev);
1799 return 0;
1800}
1801
1802static const struct dev_pm_ops imx_spi_pm = {
1803 SET_RUNTIME_PM_OPS(spi_imx_runtime_suspend,
1804 spi_imx_runtime_resume, NULL)
1805 SET_SYSTEM_SLEEP_PM_OPS(spi_imx_suspend, spi_imx_resume)
1806};
1807
1808static struct platform_driver spi_imx_driver = {
1809 .driver = {
1810 .name = DRIVER_NAME,
1811 .of_match_table = spi_imx_dt_ids,
1812 .pm = &imx_spi_pm,
1813 },
1814 .id_table = spi_imx_devtype,
1815 .probe = spi_imx_probe,
1816 .remove = spi_imx_remove,
1817};
1818module_platform_driver(spi_imx_driver);
1819
1820MODULE_DESCRIPTION("SPI Controller driver");
1821MODULE_AUTHOR("Sascha Hauer, Pengutronix");
1822MODULE_LICENSE("GPL");
1823MODULE_ALIAS("platform:" DRIVER_NAME);
1// SPDX-License-Identifier: GPL-2.0+
2// Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
3// Copyright (C) 2008 Juergen Beisert
4
5#include <linux/clk.h>
6#include <linux/completion.h>
7#include <linux/delay.h>
8#include <linux/dmaengine.h>
9#include <linux/dma-mapping.h>
10#include <linux/err.h>
11#include <linux/gpio.h>
12#include <linux/interrupt.h>
13#include <linux/io.h>
14#include <linux/irq.h>
15#include <linux/kernel.h>
16#include <linux/module.h>
17#include <linux/platform_device.h>
18#include <linux/slab.h>
19#include <linux/spi/spi.h>
20#include <linux/spi/spi_bitbang.h>
21#include <linux/types.h>
22#include <linux/of.h>
23#include <linux/of_device.h>
24#include <linux/of_gpio.h>
25
26#include <linux/platform_data/dma-imx.h>
27#include <linux/platform_data/spi-imx.h>
28
29#define DRIVER_NAME "spi_imx"
30
31static bool use_dma = true;
32module_param(use_dma, bool, 0644);
33MODULE_PARM_DESC(use_dma, "Enable usage of DMA when available (default)");
34
35#define MXC_CSPIRXDATA 0x00
36#define MXC_CSPITXDATA 0x04
37#define MXC_CSPICTRL 0x08
38#define MXC_CSPIINT 0x0c
39#define MXC_RESET 0x1c
40
41/* generic defines to abstract from the different register layouts */
42#define MXC_INT_RR (1 << 0) /* Receive data ready interrupt */
43#define MXC_INT_TE (1 << 1) /* Transmit FIFO empty interrupt */
44#define MXC_INT_RDR BIT(4) /* Receive date threshold interrupt */
45
46/* The maximum bytes that a sdma BD can transfer. */
47#define MAX_SDMA_BD_BYTES (1 << 15)
48#define MX51_ECSPI_CTRL_MAX_BURST 512
49/* The maximum bytes that IMX53_ECSPI can transfer in slave mode.*/
50#define MX53_MAX_TRANSFER_BYTES 512
51
52enum spi_imx_devtype {
53 IMX1_CSPI,
54 IMX21_CSPI,
55 IMX27_CSPI,
56 IMX31_CSPI,
57 IMX35_CSPI, /* CSPI on all i.mx except above */
58 IMX51_ECSPI, /* ECSPI on i.mx51 */
59 IMX53_ECSPI, /* ECSPI on i.mx53 and later */
60};
61
62struct spi_imx_data;
63
64struct spi_imx_devtype_data {
65 void (*intctrl)(struct spi_imx_data *, int);
66 int (*prepare_message)(struct spi_imx_data *, struct spi_message *);
67 int (*prepare_transfer)(struct spi_imx_data *, struct spi_device *,
68 struct spi_transfer *);
69 void (*trigger)(struct spi_imx_data *);
70 int (*rx_available)(struct spi_imx_data *);
71 void (*reset)(struct spi_imx_data *);
72 void (*setup_wml)(struct spi_imx_data *);
73 void (*disable)(struct spi_imx_data *);
74 bool has_dmamode;
75 bool has_slavemode;
76 unsigned int fifo_size;
77 bool dynamic_burst;
78 enum spi_imx_devtype devtype;
79};
80
81struct spi_imx_data {
82 struct spi_bitbang bitbang;
83 struct device *dev;
84
85 struct completion xfer_done;
86 void __iomem *base;
87 unsigned long base_phys;
88
89 struct clk *clk_per;
90 struct clk *clk_ipg;
91 unsigned long spi_clk;
92 unsigned int spi_bus_clk;
93
94 unsigned int bits_per_word;
95 unsigned int spi_drctl;
96
97 unsigned int count, remainder;
98 void (*tx)(struct spi_imx_data *);
99 void (*rx)(struct spi_imx_data *);
100 void *rx_buf;
101 const void *tx_buf;
102 unsigned int txfifo; /* number of words pushed in tx FIFO */
103 unsigned int dynamic_burst;
104
105 /* Slave mode */
106 bool slave_mode;
107 bool slave_aborted;
108 unsigned int slave_burst;
109
110 /* DMA */
111 bool usedma;
112 u32 wml;
113 struct completion dma_rx_completion;
114 struct completion dma_tx_completion;
115
116 const struct spi_imx_devtype_data *devtype_data;
117};
118
119static inline int is_imx27_cspi(struct spi_imx_data *d)
120{
121 return d->devtype_data->devtype == IMX27_CSPI;
122}
123
124static inline int is_imx35_cspi(struct spi_imx_data *d)
125{
126 return d->devtype_data->devtype == IMX35_CSPI;
127}
128
129static inline int is_imx51_ecspi(struct spi_imx_data *d)
130{
131 return d->devtype_data->devtype == IMX51_ECSPI;
132}
133
134static inline int is_imx53_ecspi(struct spi_imx_data *d)
135{
136 return d->devtype_data->devtype == IMX53_ECSPI;
137}
138
139#define MXC_SPI_BUF_RX(type) \
140static void spi_imx_buf_rx_##type(struct spi_imx_data *spi_imx) \
141{ \
142 unsigned int val = readl(spi_imx->base + MXC_CSPIRXDATA); \
143 \
144 if (spi_imx->rx_buf) { \
145 *(type *)spi_imx->rx_buf = val; \
146 spi_imx->rx_buf += sizeof(type); \
147 } \
148 \
149 spi_imx->remainder -= sizeof(type); \
150}
151
152#define MXC_SPI_BUF_TX(type) \
153static void spi_imx_buf_tx_##type(struct spi_imx_data *spi_imx) \
154{ \
155 type val = 0; \
156 \
157 if (spi_imx->tx_buf) { \
158 val = *(type *)spi_imx->tx_buf; \
159 spi_imx->tx_buf += sizeof(type); \
160 } \
161 \
162 spi_imx->count -= sizeof(type); \
163 \
164 writel(val, spi_imx->base + MXC_CSPITXDATA); \
165}
166
167MXC_SPI_BUF_RX(u8)
168MXC_SPI_BUF_TX(u8)
169MXC_SPI_BUF_RX(u16)
170MXC_SPI_BUF_TX(u16)
171MXC_SPI_BUF_RX(u32)
172MXC_SPI_BUF_TX(u32)
173
174/* First entry is reserved, second entry is valid only if SDHC_SPIEN is set
175 * (which is currently not the case in this driver)
176 */
177static int mxc_clkdivs[] = {0, 3, 4, 6, 8, 12, 16, 24, 32, 48, 64, 96, 128, 192,
178 256, 384, 512, 768, 1024};
179
180/* MX21, MX27 */
181static unsigned int spi_imx_clkdiv_1(unsigned int fin,
182 unsigned int fspi, unsigned int max, unsigned int *fres)
183{
184 int i;
185
186 for (i = 2; i < max; i++)
187 if (fspi * mxc_clkdivs[i] >= fin)
188 break;
189
190 *fres = fin / mxc_clkdivs[i];
191 return i;
192}
193
194/* MX1, MX31, MX35, MX51 CSPI */
195static unsigned int spi_imx_clkdiv_2(unsigned int fin,
196 unsigned int fspi, unsigned int *fres)
197{
198 int i, div = 4;
199
200 for (i = 0; i < 7; i++) {
201 if (fspi * div >= fin)
202 goto out;
203 div <<= 1;
204 }
205
206out:
207 *fres = fin / div;
208 return i;
209}
210
211static int spi_imx_bytes_per_word(const int bits_per_word)
212{
213 if (bits_per_word <= 8)
214 return 1;
215 else if (bits_per_word <= 16)
216 return 2;
217 else
218 return 4;
219}
220
221static bool spi_imx_can_dma(struct spi_master *master, struct spi_device *spi,
222 struct spi_transfer *transfer)
223{
224 struct spi_imx_data *spi_imx = spi_master_get_devdata(master);
225
226 if (!use_dma)
227 return false;
228
229 if (!master->dma_rx)
230 return false;
231
232 if (spi_imx->slave_mode)
233 return false;
234
235 if (transfer->len < spi_imx->devtype_data->fifo_size)
236 return false;
237
238 spi_imx->dynamic_burst = 0;
239
240 return true;
241}
242
243#define MX51_ECSPI_CTRL 0x08
244#define MX51_ECSPI_CTRL_ENABLE (1 << 0)
245#define MX51_ECSPI_CTRL_XCH (1 << 2)
246#define MX51_ECSPI_CTRL_SMC (1 << 3)
247#define MX51_ECSPI_CTRL_MODE_MASK (0xf << 4)
248#define MX51_ECSPI_CTRL_DRCTL(drctl) ((drctl) << 16)
249#define MX51_ECSPI_CTRL_POSTDIV_OFFSET 8
250#define MX51_ECSPI_CTRL_PREDIV_OFFSET 12
251#define MX51_ECSPI_CTRL_CS(cs) ((cs) << 18)
252#define MX51_ECSPI_CTRL_BL_OFFSET 20
253#define MX51_ECSPI_CTRL_BL_MASK (0xfff << 20)
254
255#define MX51_ECSPI_CONFIG 0x0c
256#define MX51_ECSPI_CONFIG_SCLKPHA(cs) (1 << ((cs) + 0))
257#define MX51_ECSPI_CONFIG_SCLKPOL(cs) (1 << ((cs) + 4))
258#define MX51_ECSPI_CONFIG_SBBCTRL(cs) (1 << ((cs) + 8))
259#define MX51_ECSPI_CONFIG_SSBPOL(cs) (1 << ((cs) + 12))
260#define MX51_ECSPI_CONFIG_SCLKCTL(cs) (1 << ((cs) + 20))
261
262#define MX51_ECSPI_INT 0x10
263#define MX51_ECSPI_INT_TEEN (1 << 0)
264#define MX51_ECSPI_INT_RREN (1 << 3)
265#define MX51_ECSPI_INT_RDREN (1 << 4)
266
267#define MX51_ECSPI_DMA 0x14
268#define MX51_ECSPI_DMA_TX_WML(wml) ((wml) & 0x3f)
269#define MX51_ECSPI_DMA_RX_WML(wml) (((wml) & 0x3f) << 16)
270#define MX51_ECSPI_DMA_RXT_WML(wml) (((wml) & 0x3f) << 24)
271
272#define MX51_ECSPI_DMA_TEDEN (1 << 7)
273#define MX51_ECSPI_DMA_RXDEN (1 << 23)
274#define MX51_ECSPI_DMA_RXTDEN (1 << 31)
275
276#define MX51_ECSPI_STAT 0x18
277#define MX51_ECSPI_STAT_RR (1 << 3)
278
279#define MX51_ECSPI_TESTREG 0x20
280#define MX51_ECSPI_TESTREG_LBC BIT(31)
281
282static void spi_imx_buf_rx_swap_u32(struct spi_imx_data *spi_imx)
283{
284 unsigned int val = readl(spi_imx->base + MXC_CSPIRXDATA);
285#ifdef __LITTLE_ENDIAN
286 unsigned int bytes_per_word;
287#endif
288
289 if (spi_imx->rx_buf) {
290#ifdef __LITTLE_ENDIAN
291 bytes_per_word = spi_imx_bytes_per_word(spi_imx->bits_per_word);
292 if (bytes_per_word == 1)
293 val = cpu_to_be32(val);
294 else if (bytes_per_word == 2)
295 val = (val << 16) | (val >> 16);
296#endif
297 *(u32 *)spi_imx->rx_buf = val;
298 spi_imx->rx_buf += sizeof(u32);
299 }
300
301 spi_imx->remainder -= sizeof(u32);
302}
303
304static void spi_imx_buf_rx_swap(struct spi_imx_data *spi_imx)
305{
306 int unaligned;
307 u32 val;
308
309 unaligned = spi_imx->remainder % 4;
310
311 if (!unaligned) {
312 spi_imx_buf_rx_swap_u32(spi_imx);
313 return;
314 }
315
316 if (spi_imx_bytes_per_word(spi_imx->bits_per_word) == 2) {
317 spi_imx_buf_rx_u16(spi_imx);
318 return;
319 }
320
321 val = readl(spi_imx->base + MXC_CSPIRXDATA);
322
323 while (unaligned--) {
324 if (spi_imx->rx_buf) {
325 *(u8 *)spi_imx->rx_buf = (val >> (8 * unaligned)) & 0xff;
326 spi_imx->rx_buf++;
327 }
328 spi_imx->remainder--;
329 }
330}
331
332static void spi_imx_buf_tx_swap_u32(struct spi_imx_data *spi_imx)
333{
334 u32 val = 0;
335#ifdef __LITTLE_ENDIAN
336 unsigned int bytes_per_word;
337#endif
338
339 if (spi_imx->tx_buf) {
340 val = *(u32 *)spi_imx->tx_buf;
341 spi_imx->tx_buf += sizeof(u32);
342 }
343
344 spi_imx->count -= sizeof(u32);
345#ifdef __LITTLE_ENDIAN
346 bytes_per_word = spi_imx_bytes_per_word(spi_imx->bits_per_word);
347
348 if (bytes_per_word == 1)
349 val = cpu_to_be32(val);
350 else if (bytes_per_word == 2)
351 val = (val << 16) | (val >> 16);
352#endif
353 writel(val, spi_imx->base + MXC_CSPITXDATA);
354}
355
356static void spi_imx_buf_tx_swap(struct spi_imx_data *spi_imx)
357{
358 int unaligned;
359 u32 val = 0;
360
361 unaligned = spi_imx->count % 4;
362
363 if (!unaligned) {
364 spi_imx_buf_tx_swap_u32(spi_imx);
365 return;
366 }
367
368 if (spi_imx_bytes_per_word(spi_imx->bits_per_word) == 2) {
369 spi_imx_buf_tx_u16(spi_imx);
370 return;
371 }
372
373 while (unaligned--) {
374 if (spi_imx->tx_buf) {
375 val |= *(u8 *)spi_imx->tx_buf << (8 * unaligned);
376 spi_imx->tx_buf++;
377 }
378 spi_imx->count--;
379 }
380
381 writel(val, spi_imx->base + MXC_CSPITXDATA);
382}
383
384static void mx53_ecspi_rx_slave(struct spi_imx_data *spi_imx)
385{
386 u32 val = be32_to_cpu(readl(spi_imx->base + MXC_CSPIRXDATA));
387
388 if (spi_imx->rx_buf) {
389 int n_bytes = spi_imx->slave_burst % sizeof(val);
390
391 if (!n_bytes)
392 n_bytes = sizeof(val);
393
394 memcpy(spi_imx->rx_buf,
395 ((u8 *)&val) + sizeof(val) - n_bytes, n_bytes);
396
397 spi_imx->rx_buf += n_bytes;
398 spi_imx->slave_burst -= n_bytes;
399 }
400
401 spi_imx->remainder -= sizeof(u32);
402}
403
404static void mx53_ecspi_tx_slave(struct spi_imx_data *spi_imx)
405{
406 u32 val = 0;
407 int n_bytes = spi_imx->count % sizeof(val);
408
409 if (!n_bytes)
410 n_bytes = sizeof(val);
411
412 if (spi_imx->tx_buf) {
413 memcpy(((u8 *)&val) + sizeof(val) - n_bytes,
414 spi_imx->tx_buf, n_bytes);
415 val = cpu_to_be32(val);
416 spi_imx->tx_buf += n_bytes;
417 }
418
419 spi_imx->count -= n_bytes;
420
421 writel(val, spi_imx->base + MXC_CSPITXDATA);
422}
423
424/* MX51 eCSPI */
425static unsigned int mx51_ecspi_clkdiv(struct spi_imx_data *spi_imx,
426 unsigned int fspi, unsigned int *fres)
427{
428 /*
429 * there are two 4-bit dividers, the pre-divider divides by
430 * $pre, the post-divider by 2^$post
431 */
432 unsigned int pre, post;
433 unsigned int fin = spi_imx->spi_clk;
434
435 if (unlikely(fspi > fin))
436 return 0;
437
438 post = fls(fin) - fls(fspi);
439 if (fin > fspi << post)
440 post++;
441
442 /* now we have: (fin <= fspi << post) with post being minimal */
443
444 post = max(4U, post) - 4;
445 if (unlikely(post > 0xf)) {
446 dev_err(spi_imx->dev, "cannot set clock freq: %u (base freq: %u)\n",
447 fspi, fin);
448 return 0xff;
449 }
450
451 pre = DIV_ROUND_UP(fin, fspi << post) - 1;
452
453 dev_dbg(spi_imx->dev, "%s: fin: %u, fspi: %u, post: %u, pre: %u\n",
454 __func__, fin, fspi, post, pre);
455
456 /* Resulting frequency for the SCLK line. */
457 *fres = (fin / (pre + 1)) >> post;
458
459 return (pre << MX51_ECSPI_CTRL_PREDIV_OFFSET) |
460 (post << MX51_ECSPI_CTRL_POSTDIV_OFFSET);
461}
462
463static void mx51_ecspi_intctrl(struct spi_imx_data *spi_imx, int enable)
464{
465 unsigned val = 0;
466
467 if (enable & MXC_INT_TE)
468 val |= MX51_ECSPI_INT_TEEN;
469
470 if (enable & MXC_INT_RR)
471 val |= MX51_ECSPI_INT_RREN;
472
473 if (enable & MXC_INT_RDR)
474 val |= MX51_ECSPI_INT_RDREN;
475
476 writel(val, spi_imx->base + MX51_ECSPI_INT);
477}
478
479static void mx51_ecspi_trigger(struct spi_imx_data *spi_imx)
480{
481 u32 reg;
482
483 reg = readl(spi_imx->base + MX51_ECSPI_CTRL);
484 reg |= MX51_ECSPI_CTRL_XCH;
485 writel(reg, spi_imx->base + MX51_ECSPI_CTRL);
486}
487
488static void mx51_ecspi_disable(struct spi_imx_data *spi_imx)
489{
490 u32 ctrl;
491
492 ctrl = readl(spi_imx->base + MX51_ECSPI_CTRL);
493 ctrl &= ~MX51_ECSPI_CTRL_ENABLE;
494 writel(ctrl, spi_imx->base + MX51_ECSPI_CTRL);
495}
496
497static int mx51_ecspi_prepare_message(struct spi_imx_data *spi_imx,
498 struct spi_message *msg)
499{
500 struct spi_device *spi = msg->spi;
501 u32 ctrl = MX51_ECSPI_CTRL_ENABLE;
502 u32 testreg;
503 u32 cfg = readl(spi_imx->base + MX51_ECSPI_CONFIG);
504
505 /* set Master or Slave mode */
506 if (spi_imx->slave_mode)
507 ctrl &= ~MX51_ECSPI_CTRL_MODE_MASK;
508 else
509 ctrl |= MX51_ECSPI_CTRL_MODE_MASK;
510
511 /*
512 * Enable SPI_RDY handling (falling edge/level triggered).
513 */
514 if (spi->mode & SPI_READY)
515 ctrl |= MX51_ECSPI_CTRL_DRCTL(spi_imx->spi_drctl);
516
517 /* set chip select to use */
518 ctrl |= MX51_ECSPI_CTRL_CS(spi->chip_select);
519
520 /*
521 * The ctrl register must be written first, with the EN bit set other
522 * registers must not be written to.
523 */
524 writel(ctrl, spi_imx->base + MX51_ECSPI_CTRL);
525
526 testreg = readl(spi_imx->base + MX51_ECSPI_TESTREG);
527 if (spi->mode & SPI_LOOP)
528 testreg |= MX51_ECSPI_TESTREG_LBC;
529 else
530 testreg &= ~MX51_ECSPI_TESTREG_LBC;
531 writel(testreg, spi_imx->base + MX51_ECSPI_TESTREG);
532
533 /*
534 * eCSPI burst completion by Chip Select signal in Slave mode
535 * is not functional for imx53 Soc, config SPI burst completed when
536 * BURST_LENGTH + 1 bits are received
537 */
538 if (spi_imx->slave_mode && is_imx53_ecspi(spi_imx))
539 cfg &= ~MX51_ECSPI_CONFIG_SBBCTRL(spi->chip_select);
540 else
541 cfg |= MX51_ECSPI_CONFIG_SBBCTRL(spi->chip_select);
542
543 if (spi->mode & SPI_CPHA)
544 cfg |= MX51_ECSPI_CONFIG_SCLKPHA(spi->chip_select);
545 else
546 cfg &= ~MX51_ECSPI_CONFIG_SCLKPHA(spi->chip_select);
547
548 if (spi->mode & SPI_CPOL) {
549 cfg |= MX51_ECSPI_CONFIG_SCLKPOL(spi->chip_select);
550 cfg |= MX51_ECSPI_CONFIG_SCLKCTL(spi->chip_select);
551 } else {
552 cfg &= ~MX51_ECSPI_CONFIG_SCLKPOL(spi->chip_select);
553 cfg &= ~MX51_ECSPI_CONFIG_SCLKCTL(spi->chip_select);
554 }
555
556 if (spi->mode & SPI_CS_HIGH)
557 cfg |= MX51_ECSPI_CONFIG_SSBPOL(spi->chip_select);
558 else
559 cfg &= ~MX51_ECSPI_CONFIG_SSBPOL(spi->chip_select);
560
561 writel(cfg, spi_imx->base + MX51_ECSPI_CONFIG);
562
563 return 0;
564}
565
566static int mx51_ecspi_prepare_transfer(struct spi_imx_data *spi_imx,
567 struct spi_device *spi,
568 struct spi_transfer *t)
569{
570 u32 ctrl = readl(spi_imx->base + MX51_ECSPI_CTRL);
571 u32 clk = t->speed_hz, delay;
572
573 /* Clear BL field and set the right value */
574 ctrl &= ~MX51_ECSPI_CTRL_BL_MASK;
575 if (spi_imx->slave_mode && is_imx53_ecspi(spi_imx))
576 ctrl |= (spi_imx->slave_burst * 8 - 1)
577 << MX51_ECSPI_CTRL_BL_OFFSET;
578 else
579 ctrl |= (spi_imx->bits_per_word - 1)
580 << MX51_ECSPI_CTRL_BL_OFFSET;
581
582 /* set clock speed */
583 ctrl &= ~(0xf << MX51_ECSPI_CTRL_POSTDIV_OFFSET |
584 0xf << MX51_ECSPI_CTRL_PREDIV_OFFSET);
585 ctrl |= mx51_ecspi_clkdiv(spi_imx, t->speed_hz, &clk);
586 spi_imx->spi_bus_clk = clk;
587
588 if (spi_imx->usedma)
589 ctrl |= MX51_ECSPI_CTRL_SMC;
590
591 writel(ctrl, spi_imx->base + MX51_ECSPI_CTRL);
592
593 /*
594 * Wait until the changes in the configuration register CONFIGREG
595 * propagate into the hardware. It takes exactly one tick of the
596 * SCLK clock, but we will wait two SCLK clock just to be sure. The
597 * effect of the delay it takes for the hardware to apply changes
598 * is noticable if the SCLK clock run very slow. In such a case, if
599 * the polarity of SCLK should be inverted, the GPIO ChipSelect might
600 * be asserted before the SCLK polarity changes, which would disrupt
601 * the SPI communication as the device on the other end would consider
602 * the change of SCLK polarity as a clock tick already.
603 */
604 delay = (2 * 1000000) / clk;
605 if (likely(delay < 10)) /* SCLK is faster than 100 kHz */
606 udelay(delay);
607 else /* SCLK is _very_ slow */
608 usleep_range(delay, delay + 10);
609
610 return 0;
611}
612
613static void mx51_setup_wml(struct spi_imx_data *spi_imx)
614{
615 /*
616 * Configure the DMA register: setup the watermark
617 * and enable DMA request.
618 */
619 writel(MX51_ECSPI_DMA_RX_WML(spi_imx->wml - 1) |
620 MX51_ECSPI_DMA_TX_WML(spi_imx->wml) |
621 MX51_ECSPI_DMA_RXT_WML(spi_imx->wml) |
622 MX51_ECSPI_DMA_TEDEN | MX51_ECSPI_DMA_RXDEN |
623 MX51_ECSPI_DMA_RXTDEN, spi_imx->base + MX51_ECSPI_DMA);
624}
625
626static int mx51_ecspi_rx_available(struct spi_imx_data *spi_imx)
627{
628 return readl(spi_imx->base + MX51_ECSPI_STAT) & MX51_ECSPI_STAT_RR;
629}
630
631static void mx51_ecspi_reset(struct spi_imx_data *spi_imx)
632{
633 /* drain receive buffer */
634 while (mx51_ecspi_rx_available(spi_imx))
635 readl(spi_imx->base + MXC_CSPIRXDATA);
636}
637
638#define MX31_INTREG_TEEN (1 << 0)
639#define MX31_INTREG_RREN (1 << 3)
640
641#define MX31_CSPICTRL_ENABLE (1 << 0)
642#define MX31_CSPICTRL_MASTER (1 << 1)
643#define MX31_CSPICTRL_XCH (1 << 2)
644#define MX31_CSPICTRL_SMC (1 << 3)
645#define MX31_CSPICTRL_POL (1 << 4)
646#define MX31_CSPICTRL_PHA (1 << 5)
647#define MX31_CSPICTRL_SSCTL (1 << 6)
648#define MX31_CSPICTRL_SSPOL (1 << 7)
649#define MX31_CSPICTRL_BC_SHIFT 8
650#define MX35_CSPICTRL_BL_SHIFT 20
651#define MX31_CSPICTRL_CS_SHIFT 24
652#define MX35_CSPICTRL_CS_SHIFT 12
653#define MX31_CSPICTRL_DR_SHIFT 16
654
655#define MX31_CSPI_DMAREG 0x10
656#define MX31_DMAREG_RH_DEN (1<<4)
657#define MX31_DMAREG_TH_DEN (1<<1)
658
659#define MX31_CSPISTATUS 0x14
660#define MX31_STATUS_RR (1 << 3)
661
662#define MX31_CSPI_TESTREG 0x1C
663#define MX31_TEST_LBC (1 << 14)
664
665/* These functions also work for the i.MX35, but be aware that
666 * the i.MX35 has a slightly different register layout for bits
667 * we do not use here.
668 */
669static void mx31_intctrl(struct spi_imx_data *spi_imx, int enable)
670{
671 unsigned int val = 0;
672
673 if (enable & MXC_INT_TE)
674 val |= MX31_INTREG_TEEN;
675 if (enable & MXC_INT_RR)
676 val |= MX31_INTREG_RREN;
677
678 writel(val, spi_imx->base + MXC_CSPIINT);
679}
680
681static void mx31_trigger(struct spi_imx_data *spi_imx)
682{
683 unsigned int reg;
684
685 reg = readl(spi_imx->base + MXC_CSPICTRL);
686 reg |= MX31_CSPICTRL_XCH;
687 writel(reg, spi_imx->base + MXC_CSPICTRL);
688}
689
690static int mx31_prepare_message(struct spi_imx_data *spi_imx,
691 struct spi_message *msg)
692{
693 return 0;
694}
695
696static int mx31_prepare_transfer(struct spi_imx_data *spi_imx,
697 struct spi_device *spi,
698 struct spi_transfer *t)
699{
700 unsigned int reg = MX31_CSPICTRL_ENABLE | MX31_CSPICTRL_MASTER;
701 unsigned int clk;
702
703 reg |= spi_imx_clkdiv_2(spi_imx->spi_clk, t->speed_hz, &clk) <<
704 MX31_CSPICTRL_DR_SHIFT;
705 spi_imx->spi_bus_clk = clk;
706
707 if (is_imx35_cspi(spi_imx)) {
708 reg |= (spi_imx->bits_per_word - 1) << MX35_CSPICTRL_BL_SHIFT;
709 reg |= MX31_CSPICTRL_SSCTL;
710 } else {
711 reg |= (spi_imx->bits_per_word - 1) << MX31_CSPICTRL_BC_SHIFT;
712 }
713
714 if (spi->mode & SPI_CPHA)
715 reg |= MX31_CSPICTRL_PHA;
716 if (spi->mode & SPI_CPOL)
717 reg |= MX31_CSPICTRL_POL;
718 if (spi->mode & SPI_CS_HIGH)
719 reg |= MX31_CSPICTRL_SSPOL;
720 if (!gpio_is_valid(spi->cs_gpio))
721 reg |= (spi->chip_select) <<
722 (is_imx35_cspi(spi_imx) ? MX35_CSPICTRL_CS_SHIFT :
723 MX31_CSPICTRL_CS_SHIFT);
724
725 if (spi_imx->usedma)
726 reg |= MX31_CSPICTRL_SMC;
727
728 writel(reg, spi_imx->base + MXC_CSPICTRL);
729
730 reg = readl(spi_imx->base + MX31_CSPI_TESTREG);
731 if (spi->mode & SPI_LOOP)
732 reg |= MX31_TEST_LBC;
733 else
734 reg &= ~MX31_TEST_LBC;
735 writel(reg, spi_imx->base + MX31_CSPI_TESTREG);
736
737 if (spi_imx->usedma) {
738 /*
739 * configure DMA requests when RXFIFO is half full and
740 * when TXFIFO is half empty
741 */
742 writel(MX31_DMAREG_RH_DEN | MX31_DMAREG_TH_DEN,
743 spi_imx->base + MX31_CSPI_DMAREG);
744 }
745
746 return 0;
747}
748
749static int mx31_rx_available(struct spi_imx_data *spi_imx)
750{
751 return readl(spi_imx->base + MX31_CSPISTATUS) & MX31_STATUS_RR;
752}
753
754static void mx31_reset(struct spi_imx_data *spi_imx)
755{
756 /* drain receive buffer */
757 while (readl(spi_imx->base + MX31_CSPISTATUS) & MX31_STATUS_RR)
758 readl(spi_imx->base + MXC_CSPIRXDATA);
759}
760
761#define MX21_INTREG_RR (1 << 4)
762#define MX21_INTREG_TEEN (1 << 9)
763#define MX21_INTREG_RREN (1 << 13)
764
765#define MX21_CSPICTRL_POL (1 << 5)
766#define MX21_CSPICTRL_PHA (1 << 6)
767#define MX21_CSPICTRL_SSPOL (1 << 8)
768#define MX21_CSPICTRL_XCH (1 << 9)
769#define MX21_CSPICTRL_ENABLE (1 << 10)
770#define MX21_CSPICTRL_MASTER (1 << 11)
771#define MX21_CSPICTRL_DR_SHIFT 14
772#define MX21_CSPICTRL_CS_SHIFT 19
773
774static void mx21_intctrl(struct spi_imx_data *spi_imx, int enable)
775{
776 unsigned int val = 0;
777
778 if (enable & MXC_INT_TE)
779 val |= MX21_INTREG_TEEN;
780 if (enable & MXC_INT_RR)
781 val |= MX21_INTREG_RREN;
782
783 writel(val, spi_imx->base + MXC_CSPIINT);
784}
785
786static void mx21_trigger(struct spi_imx_data *spi_imx)
787{
788 unsigned int reg;
789
790 reg = readl(spi_imx->base + MXC_CSPICTRL);
791 reg |= MX21_CSPICTRL_XCH;
792 writel(reg, spi_imx->base + MXC_CSPICTRL);
793}
794
795static int mx21_prepare_message(struct spi_imx_data *spi_imx,
796 struct spi_message *msg)
797{
798 return 0;
799}
800
801static int mx21_prepare_transfer(struct spi_imx_data *spi_imx,
802 struct spi_device *spi,
803 struct spi_transfer *t)
804{
805 unsigned int reg = MX21_CSPICTRL_ENABLE | MX21_CSPICTRL_MASTER;
806 unsigned int max = is_imx27_cspi(spi_imx) ? 16 : 18;
807 unsigned int clk;
808
809 reg |= spi_imx_clkdiv_1(spi_imx->spi_clk, t->speed_hz, max, &clk)
810 << MX21_CSPICTRL_DR_SHIFT;
811 spi_imx->spi_bus_clk = clk;
812
813 reg |= spi_imx->bits_per_word - 1;
814
815 if (spi->mode & SPI_CPHA)
816 reg |= MX21_CSPICTRL_PHA;
817 if (spi->mode & SPI_CPOL)
818 reg |= MX21_CSPICTRL_POL;
819 if (spi->mode & SPI_CS_HIGH)
820 reg |= MX21_CSPICTRL_SSPOL;
821 if (!gpio_is_valid(spi->cs_gpio))
822 reg |= spi->chip_select << MX21_CSPICTRL_CS_SHIFT;
823
824 writel(reg, spi_imx->base + MXC_CSPICTRL);
825
826 return 0;
827}
828
829static int mx21_rx_available(struct spi_imx_data *spi_imx)
830{
831 return readl(spi_imx->base + MXC_CSPIINT) & MX21_INTREG_RR;
832}
833
834static void mx21_reset(struct spi_imx_data *spi_imx)
835{
836 writel(1, spi_imx->base + MXC_RESET);
837}
838
839#define MX1_INTREG_RR (1 << 3)
840#define MX1_INTREG_TEEN (1 << 8)
841#define MX1_INTREG_RREN (1 << 11)
842
843#define MX1_CSPICTRL_POL (1 << 4)
844#define MX1_CSPICTRL_PHA (1 << 5)
845#define MX1_CSPICTRL_XCH (1 << 8)
846#define MX1_CSPICTRL_ENABLE (1 << 9)
847#define MX1_CSPICTRL_MASTER (1 << 10)
848#define MX1_CSPICTRL_DR_SHIFT 13
849
850static void mx1_intctrl(struct spi_imx_data *spi_imx, int enable)
851{
852 unsigned int val = 0;
853
854 if (enable & MXC_INT_TE)
855 val |= MX1_INTREG_TEEN;
856 if (enable & MXC_INT_RR)
857 val |= MX1_INTREG_RREN;
858
859 writel(val, spi_imx->base + MXC_CSPIINT);
860}
861
862static void mx1_trigger(struct spi_imx_data *spi_imx)
863{
864 unsigned int reg;
865
866 reg = readl(spi_imx->base + MXC_CSPICTRL);
867 reg |= MX1_CSPICTRL_XCH;
868 writel(reg, spi_imx->base + MXC_CSPICTRL);
869}
870
871static int mx1_prepare_message(struct spi_imx_data *spi_imx,
872 struct spi_message *msg)
873{
874 return 0;
875}
876
877static int mx1_prepare_transfer(struct spi_imx_data *spi_imx,
878 struct spi_device *spi,
879 struct spi_transfer *t)
880{
881 unsigned int reg = MX1_CSPICTRL_ENABLE | MX1_CSPICTRL_MASTER;
882 unsigned int clk;
883
884 reg |= spi_imx_clkdiv_2(spi_imx->spi_clk, t->speed_hz, &clk) <<
885 MX1_CSPICTRL_DR_SHIFT;
886 spi_imx->spi_bus_clk = clk;
887
888 reg |= spi_imx->bits_per_word - 1;
889
890 if (spi->mode & SPI_CPHA)
891 reg |= MX1_CSPICTRL_PHA;
892 if (spi->mode & SPI_CPOL)
893 reg |= MX1_CSPICTRL_POL;
894
895 writel(reg, spi_imx->base + MXC_CSPICTRL);
896
897 return 0;
898}
899
900static int mx1_rx_available(struct spi_imx_data *spi_imx)
901{
902 return readl(spi_imx->base + MXC_CSPIINT) & MX1_INTREG_RR;
903}
904
905static void mx1_reset(struct spi_imx_data *spi_imx)
906{
907 writel(1, spi_imx->base + MXC_RESET);
908}
909
910static struct spi_imx_devtype_data imx1_cspi_devtype_data = {
911 .intctrl = mx1_intctrl,
912 .prepare_message = mx1_prepare_message,
913 .prepare_transfer = mx1_prepare_transfer,
914 .trigger = mx1_trigger,
915 .rx_available = mx1_rx_available,
916 .reset = mx1_reset,
917 .fifo_size = 8,
918 .has_dmamode = false,
919 .dynamic_burst = false,
920 .has_slavemode = false,
921 .devtype = IMX1_CSPI,
922};
923
924static struct spi_imx_devtype_data imx21_cspi_devtype_data = {
925 .intctrl = mx21_intctrl,
926 .prepare_message = mx21_prepare_message,
927 .prepare_transfer = mx21_prepare_transfer,
928 .trigger = mx21_trigger,
929 .rx_available = mx21_rx_available,
930 .reset = mx21_reset,
931 .fifo_size = 8,
932 .has_dmamode = false,
933 .dynamic_burst = false,
934 .has_slavemode = false,
935 .devtype = IMX21_CSPI,
936};
937
938static struct spi_imx_devtype_data imx27_cspi_devtype_data = {
939 /* i.mx27 cspi shares the functions with i.mx21 one */
940 .intctrl = mx21_intctrl,
941 .prepare_message = mx21_prepare_message,
942 .prepare_transfer = mx21_prepare_transfer,
943 .trigger = mx21_trigger,
944 .rx_available = mx21_rx_available,
945 .reset = mx21_reset,
946 .fifo_size = 8,
947 .has_dmamode = false,
948 .dynamic_burst = false,
949 .has_slavemode = false,
950 .devtype = IMX27_CSPI,
951};
952
953static struct spi_imx_devtype_data imx31_cspi_devtype_data = {
954 .intctrl = mx31_intctrl,
955 .prepare_message = mx31_prepare_message,
956 .prepare_transfer = mx31_prepare_transfer,
957 .trigger = mx31_trigger,
958 .rx_available = mx31_rx_available,
959 .reset = mx31_reset,
960 .fifo_size = 8,
961 .has_dmamode = false,
962 .dynamic_burst = false,
963 .has_slavemode = false,
964 .devtype = IMX31_CSPI,
965};
966
967static struct spi_imx_devtype_data imx35_cspi_devtype_data = {
968 /* i.mx35 and later cspi shares the functions with i.mx31 one */
969 .intctrl = mx31_intctrl,
970 .prepare_message = mx31_prepare_message,
971 .prepare_transfer = mx31_prepare_transfer,
972 .trigger = mx31_trigger,
973 .rx_available = mx31_rx_available,
974 .reset = mx31_reset,
975 .fifo_size = 8,
976 .has_dmamode = true,
977 .dynamic_burst = false,
978 .has_slavemode = false,
979 .devtype = IMX35_CSPI,
980};
981
982static struct spi_imx_devtype_data imx51_ecspi_devtype_data = {
983 .intctrl = mx51_ecspi_intctrl,
984 .prepare_message = mx51_ecspi_prepare_message,
985 .prepare_transfer = mx51_ecspi_prepare_transfer,
986 .trigger = mx51_ecspi_trigger,
987 .rx_available = mx51_ecspi_rx_available,
988 .reset = mx51_ecspi_reset,
989 .setup_wml = mx51_setup_wml,
990 .fifo_size = 64,
991 .has_dmamode = true,
992 .dynamic_burst = true,
993 .has_slavemode = true,
994 .disable = mx51_ecspi_disable,
995 .devtype = IMX51_ECSPI,
996};
997
998static struct spi_imx_devtype_data imx53_ecspi_devtype_data = {
999 .intctrl = mx51_ecspi_intctrl,
1000 .prepare_message = mx51_ecspi_prepare_message,
1001 .prepare_transfer = mx51_ecspi_prepare_transfer,
1002 .trigger = mx51_ecspi_trigger,
1003 .rx_available = mx51_ecspi_rx_available,
1004 .reset = mx51_ecspi_reset,
1005 .fifo_size = 64,
1006 .has_dmamode = true,
1007 .has_slavemode = true,
1008 .disable = mx51_ecspi_disable,
1009 .devtype = IMX53_ECSPI,
1010};
1011
1012static const struct platform_device_id spi_imx_devtype[] = {
1013 {
1014 .name = "imx1-cspi",
1015 .driver_data = (kernel_ulong_t) &imx1_cspi_devtype_data,
1016 }, {
1017 .name = "imx21-cspi",
1018 .driver_data = (kernel_ulong_t) &imx21_cspi_devtype_data,
1019 }, {
1020 .name = "imx27-cspi",
1021 .driver_data = (kernel_ulong_t) &imx27_cspi_devtype_data,
1022 }, {
1023 .name = "imx31-cspi",
1024 .driver_data = (kernel_ulong_t) &imx31_cspi_devtype_data,
1025 }, {
1026 .name = "imx35-cspi",
1027 .driver_data = (kernel_ulong_t) &imx35_cspi_devtype_data,
1028 }, {
1029 .name = "imx51-ecspi",
1030 .driver_data = (kernel_ulong_t) &imx51_ecspi_devtype_data,
1031 }, {
1032 .name = "imx53-ecspi",
1033 .driver_data = (kernel_ulong_t) &imx53_ecspi_devtype_data,
1034 }, {
1035 /* sentinel */
1036 }
1037};
1038
1039static const struct of_device_id spi_imx_dt_ids[] = {
1040 { .compatible = "fsl,imx1-cspi", .data = &imx1_cspi_devtype_data, },
1041 { .compatible = "fsl,imx21-cspi", .data = &imx21_cspi_devtype_data, },
1042 { .compatible = "fsl,imx27-cspi", .data = &imx27_cspi_devtype_data, },
1043 { .compatible = "fsl,imx31-cspi", .data = &imx31_cspi_devtype_data, },
1044 { .compatible = "fsl,imx35-cspi", .data = &imx35_cspi_devtype_data, },
1045 { .compatible = "fsl,imx51-ecspi", .data = &imx51_ecspi_devtype_data, },
1046 { .compatible = "fsl,imx53-ecspi", .data = &imx53_ecspi_devtype_data, },
1047 { /* sentinel */ }
1048};
1049MODULE_DEVICE_TABLE(of, spi_imx_dt_ids);
1050
1051static void spi_imx_chipselect(struct spi_device *spi, int is_active)
1052{
1053 int active = is_active != BITBANG_CS_INACTIVE;
1054 int dev_is_lowactive = !(spi->mode & SPI_CS_HIGH);
1055
1056 if (spi->mode & SPI_NO_CS)
1057 return;
1058
1059 if (!gpio_is_valid(spi->cs_gpio))
1060 return;
1061
1062 gpio_set_value(spi->cs_gpio, dev_is_lowactive ^ active);
1063}
1064
1065static void spi_imx_set_burst_len(struct spi_imx_data *spi_imx, int n_bits)
1066{
1067 u32 ctrl;
1068
1069 ctrl = readl(spi_imx->base + MX51_ECSPI_CTRL);
1070 ctrl &= ~MX51_ECSPI_CTRL_BL_MASK;
1071 ctrl |= ((n_bits - 1) << MX51_ECSPI_CTRL_BL_OFFSET);
1072 writel(ctrl, spi_imx->base + MX51_ECSPI_CTRL);
1073}
1074
1075static void spi_imx_push(struct spi_imx_data *spi_imx)
1076{
1077 unsigned int burst_len, fifo_words;
1078
1079 if (spi_imx->dynamic_burst)
1080 fifo_words = 4;
1081 else
1082 fifo_words = spi_imx_bytes_per_word(spi_imx->bits_per_word);
1083 /*
1084 * Reload the FIFO when the remaining bytes to be transferred in the
1085 * current burst is 0. This only applies when bits_per_word is a
1086 * multiple of 8.
1087 */
1088 if (!spi_imx->remainder) {
1089 if (spi_imx->dynamic_burst) {
1090
1091 /* We need to deal unaligned data first */
1092 burst_len = spi_imx->count % MX51_ECSPI_CTRL_MAX_BURST;
1093
1094 if (!burst_len)
1095 burst_len = MX51_ECSPI_CTRL_MAX_BURST;
1096
1097 spi_imx_set_burst_len(spi_imx, burst_len * 8);
1098
1099 spi_imx->remainder = burst_len;
1100 } else {
1101 spi_imx->remainder = fifo_words;
1102 }
1103 }
1104
1105 while (spi_imx->txfifo < spi_imx->devtype_data->fifo_size) {
1106 if (!spi_imx->count)
1107 break;
1108 if (spi_imx->dynamic_burst &&
1109 spi_imx->txfifo >= DIV_ROUND_UP(spi_imx->remainder,
1110 fifo_words))
1111 break;
1112 spi_imx->tx(spi_imx);
1113 spi_imx->txfifo++;
1114 }
1115
1116 if (!spi_imx->slave_mode)
1117 spi_imx->devtype_data->trigger(spi_imx);
1118}
1119
1120static irqreturn_t spi_imx_isr(int irq, void *dev_id)
1121{
1122 struct spi_imx_data *spi_imx = dev_id;
1123
1124 while (spi_imx->txfifo &&
1125 spi_imx->devtype_data->rx_available(spi_imx)) {
1126 spi_imx->rx(spi_imx);
1127 spi_imx->txfifo--;
1128 }
1129
1130 if (spi_imx->count) {
1131 spi_imx_push(spi_imx);
1132 return IRQ_HANDLED;
1133 }
1134
1135 if (spi_imx->txfifo) {
1136 /* No data left to push, but still waiting for rx data,
1137 * enable receive data available interrupt.
1138 */
1139 spi_imx->devtype_data->intctrl(
1140 spi_imx, MXC_INT_RR);
1141 return IRQ_HANDLED;
1142 }
1143
1144 spi_imx->devtype_data->intctrl(spi_imx, 0);
1145 complete(&spi_imx->xfer_done);
1146
1147 return IRQ_HANDLED;
1148}
1149
1150static int spi_imx_dma_configure(struct spi_master *master)
1151{
1152 int ret;
1153 enum dma_slave_buswidth buswidth;
1154 struct dma_slave_config rx = {}, tx = {};
1155 struct spi_imx_data *spi_imx = spi_master_get_devdata(master);
1156
1157 switch (spi_imx_bytes_per_word(spi_imx->bits_per_word)) {
1158 case 4:
1159 buswidth = DMA_SLAVE_BUSWIDTH_4_BYTES;
1160 break;
1161 case 2:
1162 buswidth = DMA_SLAVE_BUSWIDTH_2_BYTES;
1163 break;
1164 case 1:
1165 buswidth = DMA_SLAVE_BUSWIDTH_1_BYTE;
1166 break;
1167 default:
1168 return -EINVAL;
1169 }
1170
1171 tx.direction = DMA_MEM_TO_DEV;
1172 tx.dst_addr = spi_imx->base_phys + MXC_CSPITXDATA;
1173 tx.dst_addr_width = buswidth;
1174 tx.dst_maxburst = spi_imx->wml;
1175 ret = dmaengine_slave_config(master->dma_tx, &tx);
1176 if (ret) {
1177 dev_err(spi_imx->dev, "TX dma configuration failed with %d\n", ret);
1178 return ret;
1179 }
1180
1181 rx.direction = DMA_DEV_TO_MEM;
1182 rx.src_addr = spi_imx->base_phys + MXC_CSPIRXDATA;
1183 rx.src_addr_width = buswidth;
1184 rx.src_maxburst = spi_imx->wml;
1185 ret = dmaengine_slave_config(master->dma_rx, &rx);
1186 if (ret) {
1187 dev_err(spi_imx->dev, "RX dma configuration failed with %d\n", ret);
1188 return ret;
1189 }
1190
1191 return 0;
1192}
1193
1194static int spi_imx_setupxfer(struct spi_device *spi,
1195 struct spi_transfer *t)
1196{
1197 struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
1198
1199 if (!t)
1200 return 0;
1201
1202 spi_imx->bits_per_word = t->bits_per_word;
1203
1204 /*
1205 * Initialize the functions for transfer. To transfer non byte-aligned
1206 * words, we have to use multiple word-size bursts, we can't use
1207 * dynamic_burst in that case.
1208 */
1209 if (spi_imx->devtype_data->dynamic_burst && !spi_imx->slave_mode &&
1210 (spi_imx->bits_per_word == 8 ||
1211 spi_imx->bits_per_word == 16 ||
1212 spi_imx->bits_per_word == 32)) {
1213
1214 spi_imx->rx = spi_imx_buf_rx_swap;
1215 spi_imx->tx = spi_imx_buf_tx_swap;
1216 spi_imx->dynamic_burst = 1;
1217
1218 } else {
1219 if (spi_imx->bits_per_word <= 8) {
1220 spi_imx->rx = spi_imx_buf_rx_u8;
1221 spi_imx->tx = spi_imx_buf_tx_u8;
1222 } else if (spi_imx->bits_per_word <= 16) {
1223 spi_imx->rx = spi_imx_buf_rx_u16;
1224 spi_imx->tx = spi_imx_buf_tx_u16;
1225 } else {
1226 spi_imx->rx = spi_imx_buf_rx_u32;
1227 spi_imx->tx = spi_imx_buf_tx_u32;
1228 }
1229 spi_imx->dynamic_burst = 0;
1230 }
1231
1232 if (spi_imx_can_dma(spi_imx->bitbang.master, spi, t))
1233 spi_imx->usedma = 1;
1234 else
1235 spi_imx->usedma = 0;
1236
1237 if (is_imx53_ecspi(spi_imx) && spi_imx->slave_mode) {
1238 spi_imx->rx = mx53_ecspi_rx_slave;
1239 spi_imx->tx = mx53_ecspi_tx_slave;
1240 spi_imx->slave_burst = t->len;
1241 }
1242
1243 spi_imx->devtype_data->prepare_transfer(spi_imx, spi, t);
1244
1245 return 0;
1246}
1247
1248static void spi_imx_sdma_exit(struct spi_imx_data *spi_imx)
1249{
1250 struct spi_master *master = spi_imx->bitbang.master;
1251
1252 if (master->dma_rx) {
1253 dma_release_channel(master->dma_rx);
1254 master->dma_rx = NULL;
1255 }
1256
1257 if (master->dma_tx) {
1258 dma_release_channel(master->dma_tx);
1259 master->dma_tx = NULL;
1260 }
1261}
1262
1263static int spi_imx_sdma_init(struct device *dev, struct spi_imx_data *spi_imx,
1264 struct spi_master *master)
1265{
1266 int ret;
1267
1268 /* use pio mode for i.mx6dl chip TKT238285 */
1269 if (of_machine_is_compatible("fsl,imx6dl"))
1270 return 0;
1271
1272 spi_imx->wml = spi_imx->devtype_data->fifo_size / 2;
1273
1274 /* Prepare for TX DMA: */
1275 master->dma_tx = dma_request_slave_channel_reason(dev, "tx");
1276 if (IS_ERR(master->dma_tx)) {
1277 ret = PTR_ERR(master->dma_tx);
1278 dev_dbg(dev, "can't get the TX DMA channel, error %d!\n", ret);
1279 master->dma_tx = NULL;
1280 goto err;
1281 }
1282
1283 /* Prepare for RX : */
1284 master->dma_rx = dma_request_slave_channel_reason(dev, "rx");
1285 if (IS_ERR(master->dma_rx)) {
1286 ret = PTR_ERR(master->dma_rx);
1287 dev_dbg(dev, "can't get the RX DMA channel, error %d\n", ret);
1288 master->dma_rx = NULL;
1289 goto err;
1290 }
1291
1292 init_completion(&spi_imx->dma_rx_completion);
1293 init_completion(&spi_imx->dma_tx_completion);
1294 master->can_dma = spi_imx_can_dma;
1295 master->max_dma_len = MAX_SDMA_BD_BYTES;
1296 spi_imx->bitbang.master->flags = SPI_MASTER_MUST_RX |
1297 SPI_MASTER_MUST_TX;
1298
1299 return 0;
1300err:
1301 spi_imx_sdma_exit(spi_imx);
1302 return ret;
1303}
1304
1305static void spi_imx_dma_rx_callback(void *cookie)
1306{
1307 struct spi_imx_data *spi_imx = (struct spi_imx_data *)cookie;
1308
1309 complete(&spi_imx->dma_rx_completion);
1310}
1311
1312static void spi_imx_dma_tx_callback(void *cookie)
1313{
1314 struct spi_imx_data *spi_imx = (struct spi_imx_data *)cookie;
1315
1316 complete(&spi_imx->dma_tx_completion);
1317}
1318
1319static int spi_imx_calculate_timeout(struct spi_imx_data *spi_imx, int size)
1320{
1321 unsigned long timeout = 0;
1322
1323 /* Time with actual data transfer and CS change delay related to HW */
1324 timeout = (8 + 4) * size / spi_imx->spi_bus_clk;
1325
1326 /* Add extra second for scheduler related activities */
1327 timeout += 1;
1328
1329 /* Double calculated timeout */
1330 return msecs_to_jiffies(2 * timeout * MSEC_PER_SEC);
1331}
1332
1333static int spi_imx_dma_transfer(struct spi_imx_data *spi_imx,
1334 struct spi_transfer *transfer)
1335{
1336 struct dma_async_tx_descriptor *desc_tx, *desc_rx;
1337 unsigned long transfer_timeout;
1338 unsigned long timeout;
1339 struct spi_master *master = spi_imx->bitbang.master;
1340 struct sg_table *tx = &transfer->tx_sg, *rx = &transfer->rx_sg;
1341 struct scatterlist *last_sg = sg_last(rx->sgl, rx->nents);
1342 unsigned int bytes_per_word, i;
1343 int ret;
1344
1345 /* Get the right burst length from the last sg to ensure no tail data */
1346 bytes_per_word = spi_imx_bytes_per_word(transfer->bits_per_word);
1347 for (i = spi_imx->devtype_data->fifo_size / 2; i > 0; i--) {
1348 if (!(sg_dma_len(last_sg) % (i * bytes_per_word)))
1349 break;
1350 }
1351 /* Use 1 as wml in case no available burst length got */
1352 if (i == 0)
1353 i = 1;
1354
1355 spi_imx->wml = i;
1356
1357 ret = spi_imx_dma_configure(master);
1358 if (ret)
1359 return ret;
1360
1361 if (!spi_imx->devtype_data->setup_wml) {
1362 dev_err(spi_imx->dev, "No setup_wml()?\n");
1363 return -EINVAL;
1364 }
1365 spi_imx->devtype_data->setup_wml(spi_imx);
1366
1367 /*
1368 * The TX DMA setup starts the transfer, so make sure RX is configured
1369 * before TX.
1370 */
1371 desc_rx = dmaengine_prep_slave_sg(master->dma_rx,
1372 rx->sgl, rx->nents, DMA_DEV_TO_MEM,
1373 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1374 if (!desc_rx)
1375 return -EINVAL;
1376
1377 desc_rx->callback = spi_imx_dma_rx_callback;
1378 desc_rx->callback_param = (void *)spi_imx;
1379 dmaengine_submit(desc_rx);
1380 reinit_completion(&spi_imx->dma_rx_completion);
1381 dma_async_issue_pending(master->dma_rx);
1382
1383 desc_tx = dmaengine_prep_slave_sg(master->dma_tx,
1384 tx->sgl, tx->nents, DMA_MEM_TO_DEV,
1385 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1386 if (!desc_tx) {
1387 dmaengine_terminate_all(master->dma_tx);
1388 return -EINVAL;
1389 }
1390
1391 desc_tx->callback = spi_imx_dma_tx_callback;
1392 desc_tx->callback_param = (void *)spi_imx;
1393 dmaengine_submit(desc_tx);
1394 reinit_completion(&spi_imx->dma_tx_completion);
1395 dma_async_issue_pending(master->dma_tx);
1396
1397 transfer_timeout = spi_imx_calculate_timeout(spi_imx, transfer->len);
1398
1399 /* Wait SDMA to finish the data transfer.*/
1400 timeout = wait_for_completion_timeout(&spi_imx->dma_tx_completion,
1401 transfer_timeout);
1402 if (!timeout) {
1403 dev_err(spi_imx->dev, "I/O Error in DMA TX\n");
1404 dmaengine_terminate_all(master->dma_tx);
1405 dmaengine_terminate_all(master->dma_rx);
1406 return -ETIMEDOUT;
1407 }
1408
1409 timeout = wait_for_completion_timeout(&spi_imx->dma_rx_completion,
1410 transfer_timeout);
1411 if (!timeout) {
1412 dev_err(&master->dev, "I/O Error in DMA RX\n");
1413 spi_imx->devtype_data->reset(spi_imx);
1414 dmaengine_terminate_all(master->dma_rx);
1415 return -ETIMEDOUT;
1416 }
1417
1418 return transfer->len;
1419}
1420
1421static int spi_imx_pio_transfer(struct spi_device *spi,
1422 struct spi_transfer *transfer)
1423{
1424 struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
1425 unsigned long transfer_timeout;
1426 unsigned long timeout;
1427
1428 spi_imx->tx_buf = transfer->tx_buf;
1429 spi_imx->rx_buf = transfer->rx_buf;
1430 spi_imx->count = transfer->len;
1431 spi_imx->txfifo = 0;
1432 spi_imx->remainder = 0;
1433
1434 reinit_completion(&spi_imx->xfer_done);
1435
1436 spi_imx_push(spi_imx);
1437
1438 spi_imx->devtype_data->intctrl(spi_imx, MXC_INT_TE);
1439
1440 transfer_timeout = spi_imx_calculate_timeout(spi_imx, transfer->len);
1441
1442 timeout = wait_for_completion_timeout(&spi_imx->xfer_done,
1443 transfer_timeout);
1444 if (!timeout) {
1445 dev_err(&spi->dev, "I/O Error in PIO\n");
1446 spi_imx->devtype_data->reset(spi_imx);
1447 return -ETIMEDOUT;
1448 }
1449
1450 return transfer->len;
1451}
1452
1453static int spi_imx_pio_transfer_slave(struct spi_device *spi,
1454 struct spi_transfer *transfer)
1455{
1456 struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
1457 int ret = transfer->len;
1458
1459 if (is_imx53_ecspi(spi_imx) &&
1460 transfer->len > MX53_MAX_TRANSFER_BYTES) {
1461 dev_err(&spi->dev, "Transaction too big, max size is %d bytes\n",
1462 MX53_MAX_TRANSFER_BYTES);
1463 return -EMSGSIZE;
1464 }
1465
1466 spi_imx->tx_buf = transfer->tx_buf;
1467 spi_imx->rx_buf = transfer->rx_buf;
1468 spi_imx->count = transfer->len;
1469 spi_imx->txfifo = 0;
1470 spi_imx->remainder = 0;
1471
1472 reinit_completion(&spi_imx->xfer_done);
1473 spi_imx->slave_aborted = false;
1474
1475 spi_imx_push(spi_imx);
1476
1477 spi_imx->devtype_data->intctrl(spi_imx, MXC_INT_TE | MXC_INT_RDR);
1478
1479 if (wait_for_completion_interruptible(&spi_imx->xfer_done) ||
1480 spi_imx->slave_aborted) {
1481 dev_dbg(&spi->dev, "interrupted\n");
1482 ret = -EINTR;
1483 }
1484
1485 /* ecspi has a HW issue when works in Slave mode,
1486 * after 64 words writtern to TXFIFO, even TXFIFO becomes empty,
1487 * ECSPI_TXDATA keeps shift out the last word data,
1488 * so we have to disable ECSPI when in slave mode after the
1489 * transfer completes
1490 */
1491 if (spi_imx->devtype_data->disable)
1492 spi_imx->devtype_data->disable(spi_imx);
1493
1494 return ret;
1495}
1496
1497static int spi_imx_transfer(struct spi_device *spi,
1498 struct spi_transfer *transfer)
1499{
1500 struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
1501
1502 /* flush rxfifo before transfer */
1503 while (spi_imx->devtype_data->rx_available(spi_imx))
1504 readl(spi_imx->base + MXC_CSPIRXDATA);
1505
1506 if (spi_imx->slave_mode)
1507 return spi_imx_pio_transfer_slave(spi, transfer);
1508
1509 if (spi_imx->usedma)
1510 return spi_imx_dma_transfer(spi_imx, transfer);
1511 else
1512 return spi_imx_pio_transfer(spi, transfer);
1513}
1514
1515static int spi_imx_setup(struct spi_device *spi)
1516{
1517 dev_dbg(&spi->dev, "%s: mode %d, %u bpw, %d hz\n", __func__,
1518 spi->mode, spi->bits_per_word, spi->max_speed_hz);
1519
1520 if (spi->mode & SPI_NO_CS)
1521 return 0;
1522
1523 if (gpio_is_valid(spi->cs_gpio))
1524 gpio_direction_output(spi->cs_gpio,
1525 spi->mode & SPI_CS_HIGH ? 0 : 1);
1526
1527 spi_imx_chipselect(spi, BITBANG_CS_INACTIVE);
1528
1529 return 0;
1530}
1531
1532static void spi_imx_cleanup(struct spi_device *spi)
1533{
1534}
1535
1536static int
1537spi_imx_prepare_message(struct spi_master *master, struct spi_message *msg)
1538{
1539 struct spi_imx_data *spi_imx = spi_master_get_devdata(master);
1540 int ret;
1541
1542 ret = clk_enable(spi_imx->clk_per);
1543 if (ret)
1544 return ret;
1545
1546 ret = clk_enable(spi_imx->clk_ipg);
1547 if (ret) {
1548 clk_disable(spi_imx->clk_per);
1549 return ret;
1550 }
1551
1552 ret = spi_imx->devtype_data->prepare_message(spi_imx, msg);
1553 if (ret) {
1554 clk_disable(spi_imx->clk_ipg);
1555 clk_disable(spi_imx->clk_per);
1556 }
1557
1558 return ret;
1559}
1560
1561static int
1562spi_imx_unprepare_message(struct spi_master *master, struct spi_message *msg)
1563{
1564 struct spi_imx_data *spi_imx = spi_master_get_devdata(master);
1565
1566 clk_disable(spi_imx->clk_ipg);
1567 clk_disable(spi_imx->clk_per);
1568 return 0;
1569}
1570
1571static int spi_imx_slave_abort(struct spi_master *master)
1572{
1573 struct spi_imx_data *spi_imx = spi_master_get_devdata(master);
1574
1575 spi_imx->slave_aborted = true;
1576 complete(&spi_imx->xfer_done);
1577
1578 return 0;
1579}
1580
1581static int spi_imx_probe(struct platform_device *pdev)
1582{
1583 struct device_node *np = pdev->dev.of_node;
1584 const struct of_device_id *of_id =
1585 of_match_device(spi_imx_dt_ids, &pdev->dev);
1586 struct spi_imx_master *mxc_platform_info =
1587 dev_get_platdata(&pdev->dev);
1588 struct spi_master *master;
1589 struct spi_imx_data *spi_imx;
1590 struct resource *res;
1591 int i, ret, irq, spi_drctl;
1592 const struct spi_imx_devtype_data *devtype_data = of_id ? of_id->data :
1593 (struct spi_imx_devtype_data *)pdev->id_entry->driver_data;
1594 bool slave_mode;
1595
1596 if (!np && !mxc_platform_info) {
1597 dev_err(&pdev->dev, "can't get the platform data\n");
1598 return -EINVAL;
1599 }
1600
1601 slave_mode = devtype_data->has_slavemode &&
1602 of_property_read_bool(np, "spi-slave");
1603 if (slave_mode)
1604 master = spi_alloc_slave(&pdev->dev,
1605 sizeof(struct spi_imx_data));
1606 else
1607 master = spi_alloc_master(&pdev->dev,
1608 sizeof(struct spi_imx_data));
1609 if (!master)
1610 return -ENOMEM;
1611
1612 ret = of_property_read_u32(np, "fsl,spi-rdy-drctl", &spi_drctl);
1613 if ((ret < 0) || (spi_drctl >= 0x3)) {
1614 /* '11' is reserved */
1615 spi_drctl = 0;
1616 }
1617
1618 platform_set_drvdata(pdev, master);
1619
1620 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(1, 32);
1621 master->bus_num = np ? -1 : pdev->id;
1622
1623 spi_imx = spi_master_get_devdata(master);
1624 spi_imx->bitbang.master = master;
1625 spi_imx->dev = &pdev->dev;
1626 spi_imx->slave_mode = slave_mode;
1627
1628 spi_imx->devtype_data = devtype_data;
1629
1630 /* Get number of chip selects, either platform data or OF */
1631 if (mxc_platform_info) {
1632 master->num_chipselect = mxc_platform_info->num_chipselect;
1633 if (mxc_platform_info->chipselect) {
1634 master->cs_gpios = devm_kcalloc(&master->dev,
1635 master->num_chipselect, sizeof(int),
1636 GFP_KERNEL);
1637 if (!master->cs_gpios)
1638 return -ENOMEM;
1639
1640 for (i = 0; i < master->num_chipselect; i++)
1641 master->cs_gpios[i] = mxc_platform_info->chipselect[i];
1642 }
1643 } else {
1644 u32 num_cs;
1645
1646 if (!of_property_read_u32(np, "num-cs", &num_cs))
1647 master->num_chipselect = num_cs;
1648 /* If not preset, default value of 1 is used */
1649 }
1650
1651 spi_imx->bitbang.chipselect = spi_imx_chipselect;
1652 spi_imx->bitbang.setup_transfer = spi_imx_setupxfer;
1653 spi_imx->bitbang.txrx_bufs = spi_imx_transfer;
1654 spi_imx->bitbang.master->setup = spi_imx_setup;
1655 spi_imx->bitbang.master->cleanup = spi_imx_cleanup;
1656 spi_imx->bitbang.master->prepare_message = spi_imx_prepare_message;
1657 spi_imx->bitbang.master->unprepare_message = spi_imx_unprepare_message;
1658 spi_imx->bitbang.master->slave_abort = spi_imx_slave_abort;
1659 spi_imx->bitbang.master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH \
1660 | SPI_NO_CS;
1661 if (is_imx35_cspi(spi_imx) || is_imx51_ecspi(spi_imx) ||
1662 is_imx53_ecspi(spi_imx))
1663 spi_imx->bitbang.master->mode_bits |= SPI_LOOP | SPI_READY;
1664
1665 spi_imx->spi_drctl = spi_drctl;
1666
1667 init_completion(&spi_imx->xfer_done);
1668
1669 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1670 spi_imx->base = devm_ioremap_resource(&pdev->dev, res);
1671 if (IS_ERR(spi_imx->base)) {
1672 ret = PTR_ERR(spi_imx->base);
1673 goto out_master_put;
1674 }
1675 spi_imx->base_phys = res->start;
1676
1677 irq = platform_get_irq(pdev, 0);
1678 if (irq < 0) {
1679 ret = irq;
1680 goto out_master_put;
1681 }
1682
1683 ret = devm_request_irq(&pdev->dev, irq, spi_imx_isr, 0,
1684 dev_name(&pdev->dev), spi_imx);
1685 if (ret) {
1686 dev_err(&pdev->dev, "can't get irq%d: %d\n", irq, ret);
1687 goto out_master_put;
1688 }
1689
1690 spi_imx->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
1691 if (IS_ERR(spi_imx->clk_ipg)) {
1692 ret = PTR_ERR(spi_imx->clk_ipg);
1693 goto out_master_put;
1694 }
1695
1696 spi_imx->clk_per = devm_clk_get(&pdev->dev, "per");
1697 if (IS_ERR(spi_imx->clk_per)) {
1698 ret = PTR_ERR(spi_imx->clk_per);
1699 goto out_master_put;
1700 }
1701
1702 ret = clk_prepare_enable(spi_imx->clk_per);
1703 if (ret)
1704 goto out_master_put;
1705
1706 ret = clk_prepare_enable(spi_imx->clk_ipg);
1707 if (ret)
1708 goto out_put_per;
1709
1710 spi_imx->spi_clk = clk_get_rate(spi_imx->clk_per);
1711 /*
1712 * Only validated on i.mx35 and i.mx6 now, can remove the constraint
1713 * if validated on other chips.
1714 */
1715 if (spi_imx->devtype_data->has_dmamode) {
1716 ret = spi_imx_sdma_init(&pdev->dev, spi_imx, master);
1717 if (ret == -EPROBE_DEFER)
1718 goto out_clk_put;
1719
1720 if (ret < 0)
1721 dev_err(&pdev->dev, "dma setup error %d, use pio\n",
1722 ret);
1723 }
1724
1725 spi_imx->devtype_data->reset(spi_imx);
1726
1727 spi_imx->devtype_data->intctrl(spi_imx, 0);
1728
1729 master->dev.of_node = pdev->dev.of_node;
1730 ret = spi_bitbang_start(&spi_imx->bitbang);
1731 if (ret) {
1732 dev_err(&pdev->dev, "bitbang start failed with %d\n", ret);
1733 goto out_clk_put;
1734 }
1735
1736 /* Request GPIO CS lines, if any */
1737 if (!spi_imx->slave_mode && master->cs_gpios) {
1738 for (i = 0; i < master->num_chipselect; i++) {
1739 if (!gpio_is_valid(master->cs_gpios[i]))
1740 continue;
1741
1742 ret = devm_gpio_request(&pdev->dev,
1743 master->cs_gpios[i],
1744 DRIVER_NAME);
1745 if (ret) {
1746 dev_err(&pdev->dev, "Can't get CS GPIO %i\n",
1747 master->cs_gpios[i]);
1748 goto out_spi_bitbang;
1749 }
1750 }
1751 }
1752
1753 dev_info(&pdev->dev, "probed\n");
1754
1755 clk_disable(spi_imx->clk_ipg);
1756 clk_disable(spi_imx->clk_per);
1757 return ret;
1758
1759out_spi_bitbang:
1760 spi_bitbang_stop(&spi_imx->bitbang);
1761out_clk_put:
1762 clk_disable_unprepare(spi_imx->clk_ipg);
1763out_put_per:
1764 clk_disable_unprepare(spi_imx->clk_per);
1765out_master_put:
1766 spi_master_put(master);
1767
1768 return ret;
1769}
1770
1771static int spi_imx_remove(struct platform_device *pdev)
1772{
1773 struct spi_master *master = platform_get_drvdata(pdev);
1774 struct spi_imx_data *spi_imx = spi_master_get_devdata(master);
1775 int ret;
1776
1777 spi_bitbang_stop(&spi_imx->bitbang);
1778
1779 ret = clk_enable(spi_imx->clk_per);
1780 if (ret)
1781 return ret;
1782
1783 ret = clk_enable(spi_imx->clk_ipg);
1784 if (ret) {
1785 clk_disable(spi_imx->clk_per);
1786 return ret;
1787 }
1788
1789 writel(0, spi_imx->base + MXC_CSPICTRL);
1790 clk_disable_unprepare(spi_imx->clk_ipg);
1791 clk_disable_unprepare(spi_imx->clk_per);
1792 spi_imx_sdma_exit(spi_imx);
1793 spi_master_put(master);
1794
1795 return 0;
1796}
1797
1798static struct platform_driver spi_imx_driver = {
1799 .driver = {
1800 .name = DRIVER_NAME,
1801 .of_match_table = spi_imx_dt_ids,
1802 },
1803 .id_table = spi_imx_devtype,
1804 .probe = spi_imx_probe,
1805 .remove = spi_imx_remove,
1806};
1807module_platform_driver(spi_imx_driver);
1808
1809MODULE_DESCRIPTION("SPI Controller driver");
1810MODULE_AUTHOR("Sascha Hauer, Pengutronix");
1811MODULE_LICENSE("GPL");
1812MODULE_ALIAS("platform:" DRIVER_NAME);