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1// SPDX-License-Identifier: GPL-2.0+
2// Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
3// Copyright (C) 2008 Juergen Beisert
4
5#include <linux/clk.h>
6#include <linux/completion.h>
7#include <linux/delay.h>
8#include <linux/dmaengine.h>
9#include <linux/dma-mapping.h>
10#include <linux/err.h>
11#include <linux/interrupt.h>
12#include <linux/io.h>
13#include <linux/irq.h>
14#include <linux/kernel.h>
15#include <linux/module.h>
16#include <linux/pinctrl/consumer.h>
17#include <linux/platform_device.h>
18#include <linux/pm_runtime.h>
19#include <linux/slab.h>
20#include <linux/spi/spi.h>
21#include <linux/spi/spi_bitbang.h>
22#include <linux/types.h>
23#include <linux/of.h>
24#include <linux/of_device.h>
25#include <linux/property.h>
26
27#include <linux/platform_data/dma-imx.h>
28
29#define DRIVER_NAME "spi_imx"
30
31static bool use_dma = true;
32module_param(use_dma, bool, 0644);
33MODULE_PARM_DESC(use_dma, "Enable usage of DMA when available (default)");
34
35#define MXC_RPM_TIMEOUT 2000 /* 2000ms */
36
37#define MXC_CSPIRXDATA 0x00
38#define MXC_CSPITXDATA 0x04
39#define MXC_CSPICTRL 0x08
40#define MXC_CSPIINT 0x0c
41#define MXC_RESET 0x1c
42
43/* generic defines to abstract from the different register layouts */
44#define MXC_INT_RR (1 << 0) /* Receive data ready interrupt */
45#define MXC_INT_TE (1 << 1) /* Transmit FIFO empty interrupt */
46#define MXC_INT_RDR BIT(4) /* Receive date threshold interrupt */
47
48/* The maximum bytes that a sdma BD can transfer. */
49#define MAX_SDMA_BD_BYTES (1 << 15)
50#define MX51_ECSPI_CTRL_MAX_BURST 512
51/* The maximum bytes that IMX53_ECSPI can transfer in slave mode.*/
52#define MX53_MAX_TRANSFER_BYTES 512
53
54enum spi_imx_devtype {
55 IMX1_CSPI,
56 IMX21_CSPI,
57 IMX27_CSPI,
58 IMX31_CSPI,
59 IMX35_CSPI, /* CSPI on all i.mx except above */
60 IMX51_ECSPI, /* ECSPI on i.mx51 */
61 IMX53_ECSPI, /* ECSPI on i.mx53 and later */
62};
63
64struct spi_imx_data;
65
66struct spi_imx_devtype_data {
67 void (*intctrl)(struct spi_imx_data *, int);
68 int (*prepare_message)(struct spi_imx_data *, struct spi_message *);
69 int (*prepare_transfer)(struct spi_imx_data *, struct spi_device *,
70 struct spi_transfer *);
71 void (*trigger)(struct spi_imx_data *);
72 int (*rx_available)(struct spi_imx_data *);
73 void (*reset)(struct spi_imx_data *);
74 void (*setup_wml)(struct spi_imx_data *);
75 void (*disable)(struct spi_imx_data *);
76 void (*disable_dma)(struct spi_imx_data *);
77 bool has_dmamode;
78 bool has_slavemode;
79 unsigned int fifo_size;
80 bool dynamic_burst;
81 enum spi_imx_devtype devtype;
82};
83
84struct spi_imx_data {
85 struct spi_bitbang bitbang;
86 struct device *dev;
87
88 struct completion xfer_done;
89 void __iomem *base;
90 unsigned long base_phys;
91
92 struct clk *clk_per;
93 struct clk *clk_ipg;
94 unsigned long spi_clk;
95 unsigned int spi_bus_clk;
96
97 unsigned int bits_per_word;
98 unsigned int spi_drctl;
99
100 unsigned int count, remainder;
101 void (*tx)(struct spi_imx_data *);
102 void (*rx)(struct spi_imx_data *);
103 void *rx_buf;
104 const void *tx_buf;
105 unsigned int txfifo; /* number of words pushed in tx FIFO */
106 unsigned int dynamic_burst;
107
108 /* Slave mode */
109 bool slave_mode;
110 bool slave_aborted;
111 unsigned int slave_burst;
112
113 /* DMA */
114 bool usedma;
115 u32 wml;
116 struct completion dma_rx_completion;
117 struct completion dma_tx_completion;
118
119 const struct spi_imx_devtype_data *devtype_data;
120};
121
122static inline int is_imx27_cspi(struct spi_imx_data *d)
123{
124 return d->devtype_data->devtype == IMX27_CSPI;
125}
126
127static inline int is_imx35_cspi(struct spi_imx_data *d)
128{
129 return d->devtype_data->devtype == IMX35_CSPI;
130}
131
132static inline int is_imx51_ecspi(struct spi_imx_data *d)
133{
134 return d->devtype_data->devtype == IMX51_ECSPI;
135}
136
137static inline int is_imx53_ecspi(struct spi_imx_data *d)
138{
139 return d->devtype_data->devtype == IMX53_ECSPI;
140}
141
142#define MXC_SPI_BUF_RX(type) \
143static void spi_imx_buf_rx_##type(struct spi_imx_data *spi_imx) \
144{ \
145 unsigned int val = readl(spi_imx->base + MXC_CSPIRXDATA); \
146 \
147 if (spi_imx->rx_buf) { \
148 *(type *)spi_imx->rx_buf = val; \
149 spi_imx->rx_buf += sizeof(type); \
150 } \
151 \
152 spi_imx->remainder -= sizeof(type); \
153}
154
155#define MXC_SPI_BUF_TX(type) \
156static void spi_imx_buf_tx_##type(struct spi_imx_data *spi_imx) \
157{ \
158 type val = 0; \
159 \
160 if (spi_imx->tx_buf) { \
161 val = *(type *)spi_imx->tx_buf; \
162 spi_imx->tx_buf += sizeof(type); \
163 } \
164 \
165 spi_imx->count -= sizeof(type); \
166 \
167 writel(val, spi_imx->base + MXC_CSPITXDATA); \
168}
169
170MXC_SPI_BUF_RX(u8)
171MXC_SPI_BUF_TX(u8)
172MXC_SPI_BUF_RX(u16)
173MXC_SPI_BUF_TX(u16)
174MXC_SPI_BUF_RX(u32)
175MXC_SPI_BUF_TX(u32)
176
177/* First entry is reserved, second entry is valid only if SDHC_SPIEN is set
178 * (which is currently not the case in this driver)
179 */
180static int mxc_clkdivs[] = {0, 3, 4, 6, 8, 12, 16, 24, 32, 48, 64, 96, 128, 192,
181 256, 384, 512, 768, 1024};
182
183/* MX21, MX27 */
184static unsigned int spi_imx_clkdiv_1(unsigned int fin,
185 unsigned int fspi, unsigned int max, unsigned int *fres)
186{
187 int i;
188
189 for (i = 2; i < max; i++)
190 if (fspi * mxc_clkdivs[i] >= fin)
191 break;
192
193 *fres = fin / mxc_clkdivs[i];
194 return i;
195}
196
197/* MX1, MX31, MX35, MX51 CSPI */
198static unsigned int spi_imx_clkdiv_2(unsigned int fin,
199 unsigned int fspi, unsigned int *fres)
200{
201 int i, div = 4;
202
203 for (i = 0; i < 7; i++) {
204 if (fspi * div >= fin)
205 goto out;
206 div <<= 1;
207 }
208
209out:
210 *fres = fin / div;
211 return i;
212}
213
214static int spi_imx_bytes_per_word(const int bits_per_word)
215{
216 if (bits_per_word <= 8)
217 return 1;
218 else if (bits_per_word <= 16)
219 return 2;
220 else
221 return 4;
222}
223
224static bool spi_imx_can_dma(struct spi_master *master, struct spi_device *spi,
225 struct spi_transfer *transfer)
226{
227 struct spi_imx_data *spi_imx = spi_master_get_devdata(master);
228
229 if (!use_dma || master->fallback)
230 return false;
231
232 if (!master->dma_rx)
233 return false;
234
235 if (spi_imx->slave_mode)
236 return false;
237
238 if (transfer->len < spi_imx->devtype_data->fifo_size)
239 return false;
240
241 spi_imx->dynamic_burst = 0;
242
243 return true;
244}
245
246#define MX51_ECSPI_CTRL 0x08
247#define MX51_ECSPI_CTRL_ENABLE (1 << 0)
248#define MX51_ECSPI_CTRL_XCH (1 << 2)
249#define MX51_ECSPI_CTRL_SMC (1 << 3)
250#define MX51_ECSPI_CTRL_MODE_MASK (0xf << 4)
251#define MX51_ECSPI_CTRL_DRCTL(drctl) ((drctl) << 16)
252#define MX51_ECSPI_CTRL_POSTDIV_OFFSET 8
253#define MX51_ECSPI_CTRL_PREDIV_OFFSET 12
254#define MX51_ECSPI_CTRL_CS(cs) ((cs) << 18)
255#define MX51_ECSPI_CTRL_BL_OFFSET 20
256#define MX51_ECSPI_CTRL_BL_MASK (0xfff << 20)
257
258#define MX51_ECSPI_CONFIG 0x0c
259#define MX51_ECSPI_CONFIG_SCLKPHA(cs) (1 << ((cs) + 0))
260#define MX51_ECSPI_CONFIG_SCLKPOL(cs) (1 << ((cs) + 4))
261#define MX51_ECSPI_CONFIG_SBBCTRL(cs) (1 << ((cs) + 8))
262#define MX51_ECSPI_CONFIG_SSBPOL(cs) (1 << ((cs) + 12))
263#define MX51_ECSPI_CONFIG_SCLKCTL(cs) (1 << ((cs) + 20))
264
265#define MX51_ECSPI_INT 0x10
266#define MX51_ECSPI_INT_TEEN (1 << 0)
267#define MX51_ECSPI_INT_RREN (1 << 3)
268#define MX51_ECSPI_INT_RDREN (1 << 4)
269
270#define MX51_ECSPI_DMA 0x14
271#define MX51_ECSPI_DMA_TX_WML(wml) ((wml) & 0x3f)
272#define MX51_ECSPI_DMA_RX_WML(wml) (((wml) & 0x3f) << 16)
273#define MX51_ECSPI_DMA_RXT_WML(wml) (((wml) & 0x3f) << 24)
274
275#define MX51_ECSPI_DMA_TEDEN (1 << 7)
276#define MX51_ECSPI_DMA_RXDEN (1 << 23)
277#define MX51_ECSPI_DMA_RXTDEN (1 << 31)
278
279#define MX51_ECSPI_STAT 0x18
280#define MX51_ECSPI_STAT_RR (1 << 3)
281
282#define MX51_ECSPI_TESTREG 0x20
283#define MX51_ECSPI_TESTREG_LBC BIT(31)
284
285static void spi_imx_buf_rx_swap_u32(struct spi_imx_data *spi_imx)
286{
287 unsigned int val = readl(spi_imx->base + MXC_CSPIRXDATA);
288#ifdef __LITTLE_ENDIAN
289 unsigned int bytes_per_word;
290#endif
291
292 if (spi_imx->rx_buf) {
293#ifdef __LITTLE_ENDIAN
294 bytes_per_word = spi_imx_bytes_per_word(spi_imx->bits_per_word);
295 if (bytes_per_word == 1)
296 val = cpu_to_be32(val);
297 else if (bytes_per_word == 2)
298 val = (val << 16) | (val >> 16);
299#endif
300 *(u32 *)spi_imx->rx_buf = val;
301 spi_imx->rx_buf += sizeof(u32);
302 }
303
304 spi_imx->remainder -= sizeof(u32);
305}
306
307static void spi_imx_buf_rx_swap(struct spi_imx_data *spi_imx)
308{
309 int unaligned;
310 u32 val;
311
312 unaligned = spi_imx->remainder % 4;
313
314 if (!unaligned) {
315 spi_imx_buf_rx_swap_u32(spi_imx);
316 return;
317 }
318
319 if (spi_imx_bytes_per_word(spi_imx->bits_per_word) == 2) {
320 spi_imx_buf_rx_u16(spi_imx);
321 return;
322 }
323
324 val = readl(spi_imx->base + MXC_CSPIRXDATA);
325
326 while (unaligned--) {
327 if (spi_imx->rx_buf) {
328 *(u8 *)spi_imx->rx_buf = (val >> (8 * unaligned)) & 0xff;
329 spi_imx->rx_buf++;
330 }
331 spi_imx->remainder--;
332 }
333}
334
335static void spi_imx_buf_tx_swap_u32(struct spi_imx_data *spi_imx)
336{
337 u32 val = 0;
338#ifdef __LITTLE_ENDIAN
339 unsigned int bytes_per_word;
340#endif
341
342 if (spi_imx->tx_buf) {
343 val = *(u32 *)spi_imx->tx_buf;
344 spi_imx->tx_buf += sizeof(u32);
345 }
346
347 spi_imx->count -= sizeof(u32);
348#ifdef __LITTLE_ENDIAN
349 bytes_per_word = spi_imx_bytes_per_word(spi_imx->bits_per_word);
350
351 if (bytes_per_word == 1)
352 val = cpu_to_be32(val);
353 else if (bytes_per_word == 2)
354 val = (val << 16) | (val >> 16);
355#endif
356 writel(val, spi_imx->base + MXC_CSPITXDATA);
357}
358
359static void spi_imx_buf_tx_swap(struct spi_imx_data *spi_imx)
360{
361 int unaligned;
362 u32 val = 0;
363
364 unaligned = spi_imx->count % 4;
365
366 if (!unaligned) {
367 spi_imx_buf_tx_swap_u32(spi_imx);
368 return;
369 }
370
371 if (spi_imx_bytes_per_word(spi_imx->bits_per_word) == 2) {
372 spi_imx_buf_tx_u16(spi_imx);
373 return;
374 }
375
376 while (unaligned--) {
377 if (spi_imx->tx_buf) {
378 val |= *(u8 *)spi_imx->tx_buf << (8 * unaligned);
379 spi_imx->tx_buf++;
380 }
381 spi_imx->count--;
382 }
383
384 writel(val, spi_imx->base + MXC_CSPITXDATA);
385}
386
387static void mx53_ecspi_rx_slave(struct spi_imx_data *spi_imx)
388{
389 u32 val = be32_to_cpu(readl(spi_imx->base + MXC_CSPIRXDATA));
390
391 if (spi_imx->rx_buf) {
392 int n_bytes = spi_imx->slave_burst % sizeof(val);
393
394 if (!n_bytes)
395 n_bytes = sizeof(val);
396
397 memcpy(spi_imx->rx_buf,
398 ((u8 *)&val) + sizeof(val) - n_bytes, n_bytes);
399
400 spi_imx->rx_buf += n_bytes;
401 spi_imx->slave_burst -= n_bytes;
402 }
403
404 spi_imx->remainder -= sizeof(u32);
405}
406
407static void mx53_ecspi_tx_slave(struct spi_imx_data *spi_imx)
408{
409 u32 val = 0;
410 int n_bytes = spi_imx->count % sizeof(val);
411
412 if (!n_bytes)
413 n_bytes = sizeof(val);
414
415 if (spi_imx->tx_buf) {
416 memcpy(((u8 *)&val) + sizeof(val) - n_bytes,
417 spi_imx->tx_buf, n_bytes);
418 val = cpu_to_be32(val);
419 spi_imx->tx_buf += n_bytes;
420 }
421
422 spi_imx->count -= n_bytes;
423
424 writel(val, spi_imx->base + MXC_CSPITXDATA);
425}
426
427/* MX51 eCSPI */
428static unsigned int mx51_ecspi_clkdiv(struct spi_imx_data *spi_imx,
429 unsigned int fspi, unsigned int *fres)
430{
431 /*
432 * there are two 4-bit dividers, the pre-divider divides by
433 * $pre, the post-divider by 2^$post
434 */
435 unsigned int pre, post;
436 unsigned int fin = spi_imx->spi_clk;
437
438 if (unlikely(fspi > fin))
439 return 0;
440
441 post = fls(fin) - fls(fspi);
442 if (fin > fspi << post)
443 post++;
444
445 /* now we have: (fin <= fspi << post) with post being minimal */
446
447 post = max(4U, post) - 4;
448 if (unlikely(post > 0xf)) {
449 dev_err(spi_imx->dev, "cannot set clock freq: %u (base freq: %u)\n",
450 fspi, fin);
451 return 0xff;
452 }
453
454 pre = DIV_ROUND_UP(fin, fspi << post) - 1;
455
456 dev_dbg(spi_imx->dev, "%s: fin: %u, fspi: %u, post: %u, pre: %u\n",
457 __func__, fin, fspi, post, pre);
458
459 /* Resulting frequency for the SCLK line. */
460 *fres = (fin / (pre + 1)) >> post;
461
462 return (pre << MX51_ECSPI_CTRL_PREDIV_OFFSET) |
463 (post << MX51_ECSPI_CTRL_POSTDIV_OFFSET);
464}
465
466static void mx51_ecspi_intctrl(struct spi_imx_data *spi_imx, int enable)
467{
468 unsigned val = 0;
469
470 if (enable & MXC_INT_TE)
471 val |= MX51_ECSPI_INT_TEEN;
472
473 if (enable & MXC_INT_RR)
474 val |= MX51_ECSPI_INT_RREN;
475
476 if (enable & MXC_INT_RDR)
477 val |= MX51_ECSPI_INT_RDREN;
478
479 writel(val, spi_imx->base + MX51_ECSPI_INT);
480}
481
482static void mx51_ecspi_trigger(struct spi_imx_data *spi_imx)
483{
484 u32 reg;
485
486 reg = readl(spi_imx->base + MX51_ECSPI_CTRL);
487 reg |= MX51_ECSPI_CTRL_XCH;
488 writel(reg, spi_imx->base + MX51_ECSPI_CTRL);
489}
490
491static void mx51_disable_dma(struct spi_imx_data *spi_imx)
492{
493 writel(0, spi_imx->base + MX51_ECSPI_DMA);
494}
495
496static void mx51_ecspi_disable(struct spi_imx_data *spi_imx)
497{
498 u32 ctrl;
499
500 ctrl = readl(spi_imx->base + MX51_ECSPI_CTRL);
501 ctrl &= ~MX51_ECSPI_CTRL_ENABLE;
502 writel(ctrl, spi_imx->base + MX51_ECSPI_CTRL);
503}
504
505static int mx51_ecspi_prepare_message(struct spi_imx_data *spi_imx,
506 struct spi_message *msg)
507{
508 struct spi_device *spi = msg->spi;
509 u32 ctrl = MX51_ECSPI_CTRL_ENABLE;
510 u32 testreg;
511 u32 cfg = readl(spi_imx->base + MX51_ECSPI_CONFIG);
512
513 /* set Master or Slave mode */
514 if (spi_imx->slave_mode)
515 ctrl &= ~MX51_ECSPI_CTRL_MODE_MASK;
516 else
517 ctrl |= MX51_ECSPI_CTRL_MODE_MASK;
518
519 /*
520 * Enable SPI_RDY handling (falling edge/level triggered).
521 */
522 if (spi->mode & SPI_READY)
523 ctrl |= MX51_ECSPI_CTRL_DRCTL(spi_imx->spi_drctl);
524
525 /* set chip select to use */
526 ctrl |= MX51_ECSPI_CTRL_CS(spi->chip_select);
527
528 /*
529 * The ctrl register must be written first, with the EN bit set other
530 * registers must not be written to.
531 */
532 writel(ctrl, spi_imx->base + MX51_ECSPI_CTRL);
533
534 testreg = readl(spi_imx->base + MX51_ECSPI_TESTREG);
535 if (spi->mode & SPI_LOOP)
536 testreg |= MX51_ECSPI_TESTREG_LBC;
537 else
538 testreg &= ~MX51_ECSPI_TESTREG_LBC;
539 writel(testreg, spi_imx->base + MX51_ECSPI_TESTREG);
540
541 /*
542 * eCSPI burst completion by Chip Select signal in Slave mode
543 * is not functional for imx53 Soc, config SPI burst completed when
544 * BURST_LENGTH + 1 bits are received
545 */
546 if (spi_imx->slave_mode && is_imx53_ecspi(spi_imx))
547 cfg &= ~MX51_ECSPI_CONFIG_SBBCTRL(spi->chip_select);
548 else
549 cfg |= MX51_ECSPI_CONFIG_SBBCTRL(spi->chip_select);
550
551 if (spi->mode & SPI_CPHA)
552 cfg |= MX51_ECSPI_CONFIG_SCLKPHA(spi->chip_select);
553 else
554 cfg &= ~MX51_ECSPI_CONFIG_SCLKPHA(spi->chip_select);
555
556 if (spi->mode & SPI_CPOL) {
557 cfg |= MX51_ECSPI_CONFIG_SCLKPOL(spi->chip_select);
558 cfg |= MX51_ECSPI_CONFIG_SCLKCTL(spi->chip_select);
559 } else {
560 cfg &= ~MX51_ECSPI_CONFIG_SCLKPOL(spi->chip_select);
561 cfg &= ~MX51_ECSPI_CONFIG_SCLKCTL(spi->chip_select);
562 }
563
564 if (spi->mode & SPI_CS_HIGH)
565 cfg |= MX51_ECSPI_CONFIG_SSBPOL(spi->chip_select);
566 else
567 cfg &= ~MX51_ECSPI_CONFIG_SSBPOL(spi->chip_select);
568
569 writel(cfg, spi_imx->base + MX51_ECSPI_CONFIG);
570
571 return 0;
572}
573
574static int mx51_ecspi_prepare_transfer(struct spi_imx_data *spi_imx,
575 struct spi_device *spi,
576 struct spi_transfer *t)
577{
578 u32 ctrl = readl(spi_imx->base + MX51_ECSPI_CTRL);
579 u32 clk = t->speed_hz, delay;
580
581 /* Clear BL field and set the right value */
582 ctrl &= ~MX51_ECSPI_CTRL_BL_MASK;
583 if (spi_imx->slave_mode && is_imx53_ecspi(spi_imx))
584 ctrl |= (spi_imx->slave_burst * 8 - 1)
585 << MX51_ECSPI_CTRL_BL_OFFSET;
586 else
587 ctrl |= (spi_imx->bits_per_word - 1)
588 << MX51_ECSPI_CTRL_BL_OFFSET;
589
590 /* set clock speed */
591 ctrl &= ~(0xf << MX51_ECSPI_CTRL_POSTDIV_OFFSET |
592 0xf << MX51_ECSPI_CTRL_PREDIV_OFFSET);
593 ctrl |= mx51_ecspi_clkdiv(spi_imx, t->speed_hz, &clk);
594 spi_imx->spi_bus_clk = clk;
595
596 if (spi_imx->usedma)
597 ctrl |= MX51_ECSPI_CTRL_SMC;
598
599 writel(ctrl, spi_imx->base + MX51_ECSPI_CTRL);
600
601 /*
602 * Wait until the changes in the configuration register CONFIGREG
603 * propagate into the hardware. It takes exactly one tick of the
604 * SCLK clock, but we will wait two SCLK clock just to be sure. The
605 * effect of the delay it takes for the hardware to apply changes
606 * is noticable if the SCLK clock run very slow. In such a case, if
607 * the polarity of SCLK should be inverted, the GPIO ChipSelect might
608 * be asserted before the SCLK polarity changes, which would disrupt
609 * the SPI communication as the device on the other end would consider
610 * the change of SCLK polarity as a clock tick already.
611 */
612 delay = (2 * 1000000) / clk;
613 if (likely(delay < 10)) /* SCLK is faster than 100 kHz */
614 udelay(delay);
615 else /* SCLK is _very_ slow */
616 usleep_range(delay, delay + 10);
617
618 return 0;
619}
620
621static void mx51_setup_wml(struct spi_imx_data *spi_imx)
622{
623 /*
624 * Configure the DMA register: setup the watermark
625 * and enable DMA request.
626 */
627 writel(MX51_ECSPI_DMA_RX_WML(spi_imx->wml - 1) |
628 MX51_ECSPI_DMA_TX_WML(spi_imx->wml) |
629 MX51_ECSPI_DMA_RXT_WML(spi_imx->wml) |
630 MX51_ECSPI_DMA_TEDEN | MX51_ECSPI_DMA_RXDEN |
631 MX51_ECSPI_DMA_RXTDEN, spi_imx->base + MX51_ECSPI_DMA);
632}
633
634static int mx51_ecspi_rx_available(struct spi_imx_data *spi_imx)
635{
636 return readl(spi_imx->base + MX51_ECSPI_STAT) & MX51_ECSPI_STAT_RR;
637}
638
639static void mx51_ecspi_reset(struct spi_imx_data *spi_imx)
640{
641 /* drain receive buffer */
642 while (mx51_ecspi_rx_available(spi_imx))
643 readl(spi_imx->base + MXC_CSPIRXDATA);
644}
645
646#define MX31_INTREG_TEEN (1 << 0)
647#define MX31_INTREG_RREN (1 << 3)
648
649#define MX31_CSPICTRL_ENABLE (1 << 0)
650#define MX31_CSPICTRL_MASTER (1 << 1)
651#define MX31_CSPICTRL_XCH (1 << 2)
652#define MX31_CSPICTRL_SMC (1 << 3)
653#define MX31_CSPICTRL_POL (1 << 4)
654#define MX31_CSPICTRL_PHA (1 << 5)
655#define MX31_CSPICTRL_SSCTL (1 << 6)
656#define MX31_CSPICTRL_SSPOL (1 << 7)
657#define MX31_CSPICTRL_BC_SHIFT 8
658#define MX35_CSPICTRL_BL_SHIFT 20
659#define MX31_CSPICTRL_CS_SHIFT 24
660#define MX35_CSPICTRL_CS_SHIFT 12
661#define MX31_CSPICTRL_DR_SHIFT 16
662
663#define MX31_CSPI_DMAREG 0x10
664#define MX31_DMAREG_RH_DEN (1<<4)
665#define MX31_DMAREG_TH_DEN (1<<1)
666
667#define MX31_CSPISTATUS 0x14
668#define MX31_STATUS_RR (1 << 3)
669
670#define MX31_CSPI_TESTREG 0x1C
671#define MX31_TEST_LBC (1 << 14)
672
673/* These functions also work for the i.MX35, but be aware that
674 * the i.MX35 has a slightly different register layout for bits
675 * we do not use here.
676 */
677static void mx31_intctrl(struct spi_imx_data *spi_imx, int enable)
678{
679 unsigned int val = 0;
680
681 if (enable & MXC_INT_TE)
682 val |= MX31_INTREG_TEEN;
683 if (enable & MXC_INT_RR)
684 val |= MX31_INTREG_RREN;
685
686 writel(val, spi_imx->base + MXC_CSPIINT);
687}
688
689static void mx31_trigger(struct spi_imx_data *spi_imx)
690{
691 unsigned int reg;
692
693 reg = readl(spi_imx->base + MXC_CSPICTRL);
694 reg |= MX31_CSPICTRL_XCH;
695 writel(reg, spi_imx->base + MXC_CSPICTRL);
696}
697
698static int mx31_prepare_message(struct spi_imx_data *spi_imx,
699 struct spi_message *msg)
700{
701 return 0;
702}
703
704static int mx31_prepare_transfer(struct spi_imx_data *spi_imx,
705 struct spi_device *spi,
706 struct spi_transfer *t)
707{
708 unsigned int reg = MX31_CSPICTRL_ENABLE | MX31_CSPICTRL_MASTER;
709 unsigned int clk;
710
711 reg |= spi_imx_clkdiv_2(spi_imx->spi_clk, t->speed_hz, &clk) <<
712 MX31_CSPICTRL_DR_SHIFT;
713 spi_imx->spi_bus_clk = clk;
714
715 if (is_imx35_cspi(spi_imx)) {
716 reg |= (spi_imx->bits_per_word - 1) << MX35_CSPICTRL_BL_SHIFT;
717 reg |= MX31_CSPICTRL_SSCTL;
718 } else {
719 reg |= (spi_imx->bits_per_word - 1) << MX31_CSPICTRL_BC_SHIFT;
720 }
721
722 if (spi->mode & SPI_CPHA)
723 reg |= MX31_CSPICTRL_PHA;
724 if (spi->mode & SPI_CPOL)
725 reg |= MX31_CSPICTRL_POL;
726 if (spi->mode & SPI_CS_HIGH)
727 reg |= MX31_CSPICTRL_SSPOL;
728 if (!spi->cs_gpiod)
729 reg |= (spi->chip_select) <<
730 (is_imx35_cspi(spi_imx) ? MX35_CSPICTRL_CS_SHIFT :
731 MX31_CSPICTRL_CS_SHIFT);
732
733 if (spi_imx->usedma)
734 reg |= MX31_CSPICTRL_SMC;
735
736 writel(reg, spi_imx->base + MXC_CSPICTRL);
737
738 reg = readl(spi_imx->base + MX31_CSPI_TESTREG);
739 if (spi->mode & SPI_LOOP)
740 reg |= MX31_TEST_LBC;
741 else
742 reg &= ~MX31_TEST_LBC;
743 writel(reg, spi_imx->base + MX31_CSPI_TESTREG);
744
745 if (spi_imx->usedma) {
746 /*
747 * configure DMA requests when RXFIFO is half full and
748 * when TXFIFO is half empty
749 */
750 writel(MX31_DMAREG_RH_DEN | MX31_DMAREG_TH_DEN,
751 spi_imx->base + MX31_CSPI_DMAREG);
752 }
753
754 return 0;
755}
756
757static int mx31_rx_available(struct spi_imx_data *spi_imx)
758{
759 return readl(spi_imx->base + MX31_CSPISTATUS) & MX31_STATUS_RR;
760}
761
762static void mx31_reset(struct spi_imx_data *spi_imx)
763{
764 /* drain receive buffer */
765 while (readl(spi_imx->base + MX31_CSPISTATUS) & MX31_STATUS_RR)
766 readl(spi_imx->base + MXC_CSPIRXDATA);
767}
768
769#define MX21_INTREG_RR (1 << 4)
770#define MX21_INTREG_TEEN (1 << 9)
771#define MX21_INTREG_RREN (1 << 13)
772
773#define MX21_CSPICTRL_POL (1 << 5)
774#define MX21_CSPICTRL_PHA (1 << 6)
775#define MX21_CSPICTRL_SSPOL (1 << 8)
776#define MX21_CSPICTRL_XCH (1 << 9)
777#define MX21_CSPICTRL_ENABLE (1 << 10)
778#define MX21_CSPICTRL_MASTER (1 << 11)
779#define MX21_CSPICTRL_DR_SHIFT 14
780#define MX21_CSPICTRL_CS_SHIFT 19
781
782static void mx21_intctrl(struct spi_imx_data *spi_imx, int enable)
783{
784 unsigned int val = 0;
785
786 if (enable & MXC_INT_TE)
787 val |= MX21_INTREG_TEEN;
788 if (enable & MXC_INT_RR)
789 val |= MX21_INTREG_RREN;
790
791 writel(val, spi_imx->base + MXC_CSPIINT);
792}
793
794static void mx21_trigger(struct spi_imx_data *spi_imx)
795{
796 unsigned int reg;
797
798 reg = readl(spi_imx->base + MXC_CSPICTRL);
799 reg |= MX21_CSPICTRL_XCH;
800 writel(reg, spi_imx->base + MXC_CSPICTRL);
801}
802
803static int mx21_prepare_message(struct spi_imx_data *spi_imx,
804 struct spi_message *msg)
805{
806 return 0;
807}
808
809static int mx21_prepare_transfer(struct spi_imx_data *spi_imx,
810 struct spi_device *spi,
811 struct spi_transfer *t)
812{
813 unsigned int reg = MX21_CSPICTRL_ENABLE | MX21_CSPICTRL_MASTER;
814 unsigned int max = is_imx27_cspi(spi_imx) ? 16 : 18;
815 unsigned int clk;
816
817 reg |= spi_imx_clkdiv_1(spi_imx->spi_clk, t->speed_hz, max, &clk)
818 << MX21_CSPICTRL_DR_SHIFT;
819 spi_imx->spi_bus_clk = clk;
820
821 reg |= spi_imx->bits_per_word - 1;
822
823 if (spi->mode & SPI_CPHA)
824 reg |= MX21_CSPICTRL_PHA;
825 if (spi->mode & SPI_CPOL)
826 reg |= MX21_CSPICTRL_POL;
827 if (spi->mode & SPI_CS_HIGH)
828 reg |= MX21_CSPICTRL_SSPOL;
829 if (!spi->cs_gpiod)
830 reg |= spi->chip_select << MX21_CSPICTRL_CS_SHIFT;
831
832 writel(reg, spi_imx->base + MXC_CSPICTRL);
833
834 return 0;
835}
836
837static int mx21_rx_available(struct spi_imx_data *spi_imx)
838{
839 return readl(spi_imx->base + MXC_CSPIINT) & MX21_INTREG_RR;
840}
841
842static void mx21_reset(struct spi_imx_data *spi_imx)
843{
844 writel(1, spi_imx->base + MXC_RESET);
845}
846
847#define MX1_INTREG_RR (1 << 3)
848#define MX1_INTREG_TEEN (1 << 8)
849#define MX1_INTREG_RREN (1 << 11)
850
851#define MX1_CSPICTRL_POL (1 << 4)
852#define MX1_CSPICTRL_PHA (1 << 5)
853#define MX1_CSPICTRL_XCH (1 << 8)
854#define MX1_CSPICTRL_ENABLE (1 << 9)
855#define MX1_CSPICTRL_MASTER (1 << 10)
856#define MX1_CSPICTRL_DR_SHIFT 13
857
858static void mx1_intctrl(struct spi_imx_data *spi_imx, int enable)
859{
860 unsigned int val = 0;
861
862 if (enable & MXC_INT_TE)
863 val |= MX1_INTREG_TEEN;
864 if (enable & MXC_INT_RR)
865 val |= MX1_INTREG_RREN;
866
867 writel(val, spi_imx->base + MXC_CSPIINT);
868}
869
870static void mx1_trigger(struct spi_imx_data *spi_imx)
871{
872 unsigned int reg;
873
874 reg = readl(spi_imx->base + MXC_CSPICTRL);
875 reg |= MX1_CSPICTRL_XCH;
876 writel(reg, spi_imx->base + MXC_CSPICTRL);
877}
878
879static int mx1_prepare_message(struct spi_imx_data *spi_imx,
880 struct spi_message *msg)
881{
882 return 0;
883}
884
885static int mx1_prepare_transfer(struct spi_imx_data *spi_imx,
886 struct spi_device *spi,
887 struct spi_transfer *t)
888{
889 unsigned int reg = MX1_CSPICTRL_ENABLE | MX1_CSPICTRL_MASTER;
890 unsigned int clk;
891
892 reg |= spi_imx_clkdiv_2(spi_imx->spi_clk, t->speed_hz, &clk) <<
893 MX1_CSPICTRL_DR_SHIFT;
894 spi_imx->spi_bus_clk = clk;
895
896 reg |= spi_imx->bits_per_word - 1;
897
898 if (spi->mode & SPI_CPHA)
899 reg |= MX1_CSPICTRL_PHA;
900 if (spi->mode & SPI_CPOL)
901 reg |= MX1_CSPICTRL_POL;
902
903 writel(reg, spi_imx->base + MXC_CSPICTRL);
904
905 return 0;
906}
907
908static int mx1_rx_available(struct spi_imx_data *spi_imx)
909{
910 return readl(spi_imx->base + MXC_CSPIINT) & MX1_INTREG_RR;
911}
912
913static void mx1_reset(struct spi_imx_data *spi_imx)
914{
915 writel(1, spi_imx->base + MXC_RESET);
916}
917
918static struct spi_imx_devtype_data imx1_cspi_devtype_data = {
919 .intctrl = mx1_intctrl,
920 .prepare_message = mx1_prepare_message,
921 .prepare_transfer = mx1_prepare_transfer,
922 .trigger = mx1_trigger,
923 .rx_available = mx1_rx_available,
924 .reset = mx1_reset,
925 .fifo_size = 8,
926 .has_dmamode = false,
927 .dynamic_burst = false,
928 .has_slavemode = false,
929 .devtype = IMX1_CSPI,
930};
931
932static struct spi_imx_devtype_data imx21_cspi_devtype_data = {
933 .intctrl = mx21_intctrl,
934 .prepare_message = mx21_prepare_message,
935 .prepare_transfer = mx21_prepare_transfer,
936 .trigger = mx21_trigger,
937 .rx_available = mx21_rx_available,
938 .reset = mx21_reset,
939 .fifo_size = 8,
940 .has_dmamode = false,
941 .dynamic_burst = false,
942 .has_slavemode = false,
943 .devtype = IMX21_CSPI,
944};
945
946static struct spi_imx_devtype_data imx27_cspi_devtype_data = {
947 /* i.mx27 cspi shares the functions with i.mx21 one */
948 .intctrl = mx21_intctrl,
949 .prepare_message = mx21_prepare_message,
950 .prepare_transfer = mx21_prepare_transfer,
951 .trigger = mx21_trigger,
952 .rx_available = mx21_rx_available,
953 .reset = mx21_reset,
954 .fifo_size = 8,
955 .has_dmamode = false,
956 .dynamic_burst = false,
957 .has_slavemode = false,
958 .devtype = IMX27_CSPI,
959};
960
961static struct spi_imx_devtype_data imx31_cspi_devtype_data = {
962 .intctrl = mx31_intctrl,
963 .prepare_message = mx31_prepare_message,
964 .prepare_transfer = mx31_prepare_transfer,
965 .trigger = mx31_trigger,
966 .rx_available = mx31_rx_available,
967 .reset = mx31_reset,
968 .fifo_size = 8,
969 .has_dmamode = false,
970 .dynamic_burst = false,
971 .has_slavemode = false,
972 .devtype = IMX31_CSPI,
973};
974
975static struct spi_imx_devtype_data imx35_cspi_devtype_data = {
976 /* i.mx35 and later cspi shares the functions with i.mx31 one */
977 .intctrl = mx31_intctrl,
978 .prepare_message = mx31_prepare_message,
979 .prepare_transfer = mx31_prepare_transfer,
980 .trigger = mx31_trigger,
981 .rx_available = mx31_rx_available,
982 .reset = mx31_reset,
983 .fifo_size = 8,
984 .has_dmamode = true,
985 .dynamic_burst = false,
986 .has_slavemode = false,
987 .devtype = IMX35_CSPI,
988};
989
990static struct spi_imx_devtype_data imx51_ecspi_devtype_data = {
991 .intctrl = mx51_ecspi_intctrl,
992 .prepare_message = mx51_ecspi_prepare_message,
993 .prepare_transfer = mx51_ecspi_prepare_transfer,
994 .trigger = mx51_ecspi_trigger,
995 .rx_available = mx51_ecspi_rx_available,
996 .reset = mx51_ecspi_reset,
997 .setup_wml = mx51_setup_wml,
998 .disable_dma = mx51_disable_dma,
999 .fifo_size = 64,
1000 .has_dmamode = true,
1001 .dynamic_burst = true,
1002 .has_slavemode = true,
1003 .disable = mx51_ecspi_disable,
1004 .devtype = IMX51_ECSPI,
1005};
1006
1007static struct spi_imx_devtype_data imx53_ecspi_devtype_data = {
1008 .intctrl = mx51_ecspi_intctrl,
1009 .prepare_message = mx51_ecspi_prepare_message,
1010 .prepare_transfer = mx51_ecspi_prepare_transfer,
1011 .trigger = mx51_ecspi_trigger,
1012 .rx_available = mx51_ecspi_rx_available,
1013 .disable_dma = mx51_disable_dma,
1014 .reset = mx51_ecspi_reset,
1015 .fifo_size = 64,
1016 .has_dmamode = true,
1017 .has_slavemode = true,
1018 .disable = mx51_ecspi_disable,
1019 .devtype = IMX53_ECSPI,
1020};
1021
1022static const struct platform_device_id spi_imx_devtype[] = {
1023 {
1024 .name = "imx1-cspi",
1025 .driver_data = (kernel_ulong_t) &imx1_cspi_devtype_data,
1026 }, {
1027 .name = "imx21-cspi",
1028 .driver_data = (kernel_ulong_t) &imx21_cspi_devtype_data,
1029 }, {
1030 .name = "imx27-cspi",
1031 .driver_data = (kernel_ulong_t) &imx27_cspi_devtype_data,
1032 }, {
1033 .name = "imx31-cspi",
1034 .driver_data = (kernel_ulong_t) &imx31_cspi_devtype_data,
1035 }, {
1036 .name = "imx35-cspi",
1037 .driver_data = (kernel_ulong_t) &imx35_cspi_devtype_data,
1038 }, {
1039 .name = "imx51-ecspi",
1040 .driver_data = (kernel_ulong_t) &imx51_ecspi_devtype_data,
1041 }, {
1042 .name = "imx53-ecspi",
1043 .driver_data = (kernel_ulong_t) &imx53_ecspi_devtype_data,
1044 }, {
1045 /* sentinel */
1046 }
1047};
1048
1049static const struct of_device_id spi_imx_dt_ids[] = {
1050 { .compatible = "fsl,imx1-cspi", .data = &imx1_cspi_devtype_data, },
1051 { .compatible = "fsl,imx21-cspi", .data = &imx21_cspi_devtype_data, },
1052 { .compatible = "fsl,imx27-cspi", .data = &imx27_cspi_devtype_data, },
1053 { .compatible = "fsl,imx31-cspi", .data = &imx31_cspi_devtype_data, },
1054 { .compatible = "fsl,imx35-cspi", .data = &imx35_cspi_devtype_data, },
1055 { .compatible = "fsl,imx51-ecspi", .data = &imx51_ecspi_devtype_data, },
1056 { .compatible = "fsl,imx53-ecspi", .data = &imx53_ecspi_devtype_data, },
1057 { /* sentinel */ }
1058};
1059MODULE_DEVICE_TABLE(of, spi_imx_dt_ids);
1060
1061static void spi_imx_set_burst_len(struct spi_imx_data *spi_imx, int n_bits)
1062{
1063 u32 ctrl;
1064
1065 ctrl = readl(spi_imx->base + MX51_ECSPI_CTRL);
1066 ctrl &= ~MX51_ECSPI_CTRL_BL_MASK;
1067 ctrl |= ((n_bits - 1) << MX51_ECSPI_CTRL_BL_OFFSET);
1068 writel(ctrl, spi_imx->base + MX51_ECSPI_CTRL);
1069}
1070
1071static void spi_imx_push(struct spi_imx_data *spi_imx)
1072{
1073 unsigned int burst_len, fifo_words;
1074
1075 if (spi_imx->dynamic_burst)
1076 fifo_words = 4;
1077 else
1078 fifo_words = spi_imx_bytes_per_word(spi_imx->bits_per_word);
1079 /*
1080 * Reload the FIFO when the remaining bytes to be transferred in the
1081 * current burst is 0. This only applies when bits_per_word is a
1082 * multiple of 8.
1083 */
1084 if (!spi_imx->remainder) {
1085 if (spi_imx->dynamic_burst) {
1086
1087 /* We need to deal unaligned data first */
1088 burst_len = spi_imx->count % MX51_ECSPI_CTRL_MAX_BURST;
1089
1090 if (!burst_len)
1091 burst_len = MX51_ECSPI_CTRL_MAX_BURST;
1092
1093 spi_imx_set_burst_len(spi_imx, burst_len * 8);
1094
1095 spi_imx->remainder = burst_len;
1096 } else {
1097 spi_imx->remainder = fifo_words;
1098 }
1099 }
1100
1101 while (spi_imx->txfifo < spi_imx->devtype_data->fifo_size) {
1102 if (!spi_imx->count)
1103 break;
1104 if (spi_imx->dynamic_burst &&
1105 spi_imx->txfifo >= DIV_ROUND_UP(spi_imx->remainder,
1106 fifo_words))
1107 break;
1108 spi_imx->tx(spi_imx);
1109 spi_imx->txfifo++;
1110 }
1111
1112 if (!spi_imx->slave_mode)
1113 spi_imx->devtype_data->trigger(spi_imx);
1114}
1115
1116static irqreturn_t spi_imx_isr(int irq, void *dev_id)
1117{
1118 struct spi_imx_data *spi_imx = dev_id;
1119
1120 while (spi_imx->txfifo &&
1121 spi_imx->devtype_data->rx_available(spi_imx)) {
1122 spi_imx->rx(spi_imx);
1123 spi_imx->txfifo--;
1124 }
1125
1126 if (spi_imx->count) {
1127 spi_imx_push(spi_imx);
1128 return IRQ_HANDLED;
1129 }
1130
1131 if (spi_imx->txfifo) {
1132 /* No data left to push, but still waiting for rx data,
1133 * enable receive data available interrupt.
1134 */
1135 spi_imx->devtype_data->intctrl(
1136 spi_imx, MXC_INT_RR);
1137 return IRQ_HANDLED;
1138 }
1139
1140 spi_imx->devtype_data->intctrl(spi_imx, 0);
1141 complete(&spi_imx->xfer_done);
1142
1143 return IRQ_HANDLED;
1144}
1145
1146static int spi_imx_dma_configure(struct spi_master *master)
1147{
1148 int ret;
1149 enum dma_slave_buswidth buswidth;
1150 struct dma_slave_config rx = {}, tx = {};
1151 struct spi_imx_data *spi_imx = spi_master_get_devdata(master);
1152
1153 switch (spi_imx_bytes_per_word(spi_imx->bits_per_word)) {
1154 case 4:
1155 buswidth = DMA_SLAVE_BUSWIDTH_4_BYTES;
1156 break;
1157 case 2:
1158 buswidth = DMA_SLAVE_BUSWIDTH_2_BYTES;
1159 break;
1160 case 1:
1161 buswidth = DMA_SLAVE_BUSWIDTH_1_BYTE;
1162 break;
1163 default:
1164 return -EINVAL;
1165 }
1166
1167 tx.direction = DMA_MEM_TO_DEV;
1168 tx.dst_addr = spi_imx->base_phys + MXC_CSPITXDATA;
1169 tx.dst_addr_width = buswidth;
1170 tx.dst_maxburst = spi_imx->wml;
1171 ret = dmaengine_slave_config(master->dma_tx, &tx);
1172 if (ret) {
1173 dev_err(spi_imx->dev, "TX dma configuration failed with %d\n", ret);
1174 return ret;
1175 }
1176
1177 rx.direction = DMA_DEV_TO_MEM;
1178 rx.src_addr = spi_imx->base_phys + MXC_CSPIRXDATA;
1179 rx.src_addr_width = buswidth;
1180 rx.src_maxburst = spi_imx->wml;
1181 ret = dmaengine_slave_config(master->dma_rx, &rx);
1182 if (ret) {
1183 dev_err(spi_imx->dev, "RX dma configuration failed with %d\n", ret);
1184 return ret;
1185 }
1186
1187 return 0;
1188}
1189
1190static int spi_imx_setupxfer(struct spi_device *spi,
1191 struct spi_transfer *t)
1192{
1193 struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
1194
1195 if (!t)
1196 return 0;
1197
1198 spi_imx->bits_per_word = t->bits_per_word;
1199
1200 /*
1201 * Initialize the functions for transfer. To transfer non byte-aligned
1202 * words, we have to use multiple word-size bursts, we can't use
1203 * dynamic_burst in that case.
1204 */
1205 if (spi_imx->devtype_data->dynamic_burst && !spi_imx->slave_mode &&
1206 (spi_imx->bits_per_word == 8 ||
1207 spi_imx->bits_per_word == 16 ||
1208 spi_imx->bits_per_word == 32)) {
1209
1210 spi_imx->rx = spi_imx_buf_rx_swap;
1211 spi_imx->tx = spi_imx_buf_tx_swap;
1212 spi_imx->dynamic_burst = 1;
1213
1214 } else {
1215 if (spi_imx->bits_per_word <= 8) {
1216 spi_imx->rx = spi_imx_buf_rx_u8;
1217 spi_imx->tx = spi_imx_buf_tx_u8;
1218 } else if (spi_imx->bits_per_word <= 16) {
1219 spi_imx->rx = spi_imx_buf_rx_u16;
1220 spi_imx->tx = spi_imx_buf_tx_u16;
1221 } else {
1222 spi_imx->rx = spi_imx_buf_rx_u32;
1223 spi_imx->tx = spi_imx_buf_tx_u32;
1224 }
1225 spi_imx->dynamic_burst = 0;
1226 }
1227
1228 if (spi_imx_can_dma(spi_imx->bitbang.master, spi, t))
1229 spi_imx->usedma = true;
1230 else
1231 spi_imx->usedma = false;
1232
1233 if (is_imx53_ecspi(spi_imx) && spi_imx->slave_mode) {
1234 spi_imx->rx = mx53_ecspi_rx_slave;
1235 spi_imx->tx = mx53_ecspi_tx_slave;
1236 spi_imx->slave_burst = t->len;
1237 }
1238
1239 spi_imx->devtype_data->prepare_transfer(spi_imx, spi, t);
1240
1241 return 0;
1242}
1243
1244static void spi_imx_sdma_exit(struct spi_imx_data *spi_imx)
1245{
1246 struct spi_master *master = spi_imx->bitbang.master;
1247
1248 if (master->dma_rx) {
1249 dma_release_channel(master->dma_rx);
1250 master->dma_rx = NULL;
1251 }
1252
1253 if (master->dma_tx) {
1254 dma_release_channel(master->dma_tx);
1255 master->dma_tx = NULL;
1256 }
1257}
1258
1259static int spi_imx_sdma_init(struct device *dev, struct spi_imx_data *spi_imx,
1260 struct spi_master *master)
1261{
1262 int ret;
1263
1264 /* use pio mode for i.mx6dl chip TKT238285 */
1265 if (of_machine_is_compatible("fsl,imx6dl"))
1266 return 0;
1267
1268 spi_imx->wml = spi_imx->devtype_data->fifo_size / 2;
1269
1270 /* Prepare for TX DMA: */
1271 master->dma_tx = dma_request_chan(dev, "tx");
1272 if (IS_ERR(master->dma_tx)) {
1273 ret = PTR_ERR(master->dma_tx);
1274 dev_dbg(dev, "can't get the TX DMA channel, error %d!\n", ret);
1275 master->dma_tx = NULL;
1276 goto err;
1277 }
1278
1279 /* Prepare for RX : */
1280 master->dma_rx = dma_request_chan(dev, "rx");
1281 if (IS_ERR(master->dma_rx)) {
1282 ret = PTR_ERR(master->dma_rx);
1283 dev_dbg(dev, "can't get the RX DMA channel, error %d\n", ret);
1284 master->dma_rx = NULL;
1285 goto err;
1286 }
1287
1288 init_completion(&spi_imx->dma_rx_completion);
1289 init_completion(&spi_imx->dma_tx_completion);
1290 master->can_dma = spi_imx_can_dma;
1291 master->max_dma_len = MAX_SDMA_BD_BYTES;
1292 spi_imx->bitbang.master->flags = SPI_MASTER_MUST_RX |
1293 SPI_MASTER_MUST_TX;
1294
1295 return 0;
1296err:
1297 spi_imx_sdma_exit(spi_imx);
1298 return ret;
1299}
1300
1301static void spi_imx_dma_rx_callback(void *cookie)
1302{
1303 struct spi_imx_data *spi_imx = (struct spi_imx_data *)cookie;
1304
1305 complete(&spi_imx->dma_rx_completion);
1306}
1307
1308static void spi_imx_dma_tx_callback(void *cookie)
1309{
1310 struct spi_imx_data *spi_imx = (struct spi_imx_data *)cookie;
1311
1312 complete(&spi_imx->dma_tx_completion);
1313}
1314
1315static int spi_imx_calculate_timeout(struct spi_imx_data *spi_imx, int size)
1316{
1317 unsigned long timeout = 0;
1318
1319 /* Time with actual data transfer and CS change delay related to HW */
1320 timeout = (8 + 4) * size / spi_imx->spi_bus_clk;
1321
1322 /* Add extra second for scheduler related activities */
1323 timeout += 1;
1324
1325 /* Double calculated timeout */
1326 return msecs_to_jiffies(2 * timeout * MSEC_PER_SEC);
1327}
1328
1329static int spi_imx_dma_transfer(struct spi_imx_data *spi_imx,
1330 struct spi_transfer *transfer)
1331{
1332 struct dma_async_tx_descriptor *desc_tx, *desc_rx;
1333 unsigned long transfer_timeout;
1334 unsigned long timeout;
1335 struct spi_master *master = spi_imx->bitbang.master;
1336 struct sg_table *tx = &transfer->tx_sg, *rx = &transfer->rx_sg;
1337 struct scatterlist *last_sg = sg_last(rx->sgl, rx->nents);
1338 unsigned int bytes_per_word, i;
1339 int ret;
1340
1341 /* Get the right burst length from the last sg to ensure no tail data */
1342 bytes_per_word = spi_imx_bytes_per_word(transfer->bits_per_word);
1343 for (i = spi_imx->devtype_data->fifo_size / 2; i > 0; i--) {
1344 if (!(sg_dma_len(last_sg) % (i * bytes_per_word)))
1345 break;
1346 }
1347 /* Use 1 as wml in case no available burst length got */
1348 if (i == 0)
1349 i = 1;
1350
1351 spi_imx->wml = i;
1352
1353 ret = spi_imx_dma_configure(master);
1354 if (ret)
1355 goto dma_failure_no_start;
1356
1357 if (!spi_imx->devtype_data->setup_wml) {
1358 dev_err(spi_imx->dev, "No setup_wml()?\n");
1359 ret = -EINVAL;
1360 goto dma_failure_no_start;
1361 }
1362 spi_imx->devtype_data->setup_wml(spi_imx);
1363
1364 /*
1365 * The TX DMA setup starts the transfer, so make sure RX is configured
1366 * before TX.
1367 */
1368 desc_rx = dmaengine_prep_slave_sg(master->dma_rx,
1369 rx->sgl, rx->nents, DMA_DEV_TO_MEM,
1370 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1371 if (!desc_rx) {
1372 ret = -EINVAL;
1373 goto dma_failure_no_start;
1374 }
1375
1376 desc_rx->callback = spi_imx_dma_rx_callback;
1377 desc_rx->callback_param = (void *)spi_imx;
1378 dmaengine_submit(desc_rx);
1379 reinit_completion(&spi_imx->dma_rx_completion);
1380 dma_async_issue_pending(master->dma_rx);
1381
1382 desc_tx = dmaengine_prep_slave_sg(master->dma_tx,
1383 tx->sgl, tx->nents, DMA_MEM_TO_DEV,
1384 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1385 if (!desc_tx) {
1386 dmaengine_terminate_all(master->dma_tx);
1387 dmaengine_terminate_all(master->dma_rx);
1388 return -EINVAL;
1389 }
1390
1391 desc_tx->callback = spi_imx_dma_tx_callback;
1392 desc_tx->callback_param = (void *)spi_imx;
1393 dmaengine_submit(desc_tx);
1394 reinit_completion(&spi_imx->dma_tx_completion);
1395 dma_async_issue_pending(master->dma_tx);
1396
1397 transfer_timeout = spi_imx_calculate_timeout(spi_imx, transfer->len);
1398
1399 /* Wait SDMA to finish the data transfer.*/
1400 timeout = wait_for_completion_timeout(&spi_imx->dma_tx_completion,
1401 transfer_timeout);
1402 if (!timeout) {
1403 dev_err(spi_imx->dev, "I/O Error in DMA TX\n");
1404 dmaengine_terminate_all(master->dma_tx);
1405 dmaengine_terminate_all(master->dma_rx);
1406 return -ETIMEDOUT;
1407 }
1408
1409 timeout = wait_for_completion_timeout(&spi_imx->dma_rx_completion,
1410 transfer_timeout);
1411 if (!timeout) {
1412 dev_err(&master->dev, "I/O Error in DMA RX\n");
1413 spi_imx->devtype_data->reset(spi_imx);
1414 dmaengine_terminate_all(master->dma_rx);
1415 return -ETIMEDOUT;
1416 }
1417
1418 return transfer->len;
1419/* fallback to pio */
1420dma_failure_no_start:
1421 transfer->error |= SPI_TRANS_FAIL_NO_START;
1422 return ret;
1423}
1424
1425static int spi_imx_pio_transfer(struct spi_device *spi,
1426 struct spi_transfer *transfer)
1427{
1428 struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
1429 unsigned long transfer_timeout;
1430 unsigned long timeout;
1431
1432 spi_imx->tx_buf = transfer->tx_buf;
1433 spi_imx->rx_buf = transfer->rx_buf;
1434 spi_imx->count = transfer->len;
1435 spi_imx->txfifo = 0;
1436 spi_imx->remainder = 0;
1437
1438 reinit_completion(&spi_imx->xfer_done);
1439
1440 spi_imx_push(spi_imx);
1441
1442 spi_imx->devtype_data->intctrl(spi_imx, MXC_INT_TE);
1443
1444 transfer_timeout = spi_imx_calculate_timeout(spi_imx, transfer->len);
1445
1446 timeout = wait_for_completion_timeout(&spi_imx->xfer_done,
1447 transfer_timeout);
1448 if (!timeout) {
1449 dev_err(&spi->dev, "I/O Error in PIO\n");
1450 spi_imx->devtype_data->reset(spi_imx);
1451 return -ETIMEDOUT;
1452 }
1453
1454 return transfer->len;
1455}
1456
1457static int spi_imx_pio_transfer_slave(struct spi_device *spi,
1458 struct spi_transfer *transfer)
1459{
1460 struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
1461 int ret = transfer->len;
1462
1463 if (is_imx53_ecspi(spi_imx) &&
1464 transfer->len > MX53_MAX_TRANSFER_BYTES) {
1465 dev_err(&spi->dev, "Transaction too big, max size is %d bytes\n",
1466 MX53_MAX_TRANSFER_BYTES);
1467 return -EMSGSIZE;
1468 }
1469
1470 spi_imx->tx_buf = transfer->tx_buf;
1471 spi_imx->rx_buf = transfer->rx_buf;
1472 spi_imx->count = transfer->len;
1473 spi_imx->txfifo = 0;
1474 spi_imx->remainder = 0;
1475
1476 reinit_completion(&spi_imx->xfer_done);
1477 spi_imx->slave_aborted = false;
1478
1479 spi_imx_push(spi_imx);
1480
1481 spi_imx->devtype_data->intctrl(spi_imx, MXC_INT_TE | MXC_INT_RDR);
1482
1483 if (wait_for_completion_interruptible(&spi_imx->xfer_done) ||
1484 spi_imx->slave_aborted) {
1485 dev_dbg(&spi->dev, "interrupted\n");
1486 ret = -EINTR;
1487 }
1488
1489 /* ecspi has a HW issue when works in Slave mode,
1490 * after 64 words writtern to TXFIFO, even TXFIFO becomes empty,
1491 * ECSPI_TXDATA keeps shift out the last word data,
1492 * so we have to disable ECSPI when in slave mode after the
1493 * transfer completes
1494 */
1495 if (spi_imx->devtype_data->disable)
1496 spi_imx->devtype_data->disable(spi_imx);
1497
1498 return ret;
1499}
1500
1501static int spi_imx_transfer(struct spi_device *spi,
1502 struct spi_transfer *transfer)
1503{
1504 struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
1505
1506 /* flush rxfifo before transfer */
1507 while (spi_imx->devtype_data->rx_available(spi_imx))
1508 readl(spi_imx->base + MXC_CSPIRXDATA);
1509
1510 if (spi_imx->slave_mode)
1511 return spi_imx_pio_transfer_slave(spi, transfer);
1512
1513 if (spi_imx->usedma)
1514 return spi_imx_dma_transfer(spi_imx, transfer);
1515
1516 return spi_imx_pio_transfer(spi, transfer);
1517}
1518
1519static int spi_imx_setup(struct spi_device *spi)
1520{
1521 dev_dbg(&spi->dev, "%s: mode %d, %u bpw, %d hz\n", __func__,
1522 spi->mode, spi->bits_per_word, spi->max_speed_hz);
1523
1524 return 0;
1525}
1526
1527static void spi_imx_cleanup(struct spi_device *spi)
1528{
1529}
1530
1531static int
1532spi_imx_prepare_message(struct spi_master *master, struct spi_message *msg)
1533{
1534 struct spi_imx_data *spi_imx = spi_master_get_devdata(master);
1535 int ret;
1536
1537 ret = pm_runtime_get_sync(spi_imx->dev);
1538 if (ret < 0) {
1539 dev_err(spi_imx->dev, "failed to enable clock\n");
1540 return ret;
1541 }
1542
1543 ret = spi_imx->devtype_data->prepare_message(spi_imx, msg);
1544 if (ret) {
1545 pm_runtime_mark_last_busy(spi_imx->dev);
1546 pm_runtime_put_autosuspend(spi_imx->dev);
1547 }
1548
1549 return ret;
1550}
1551
1552static int
1553spi_imx_unprepare_message(struct spi_master *master, struct spi_message *msg)
1554{
1555 struct spi_imx_data *spi_imx = spi_master_get_devdata(master);
1556
1557 pm_runtime_mark_last_busy(spi_imx->dev);
1558 pm_runtime_put_autosuspend(spi_imx->dev);
1559 return 0;
1560}
1561
1562static int spi_imx_slave_abort(struct spi_master *master)
1563{
1564 struct spi_imx_data *spi_imx = spi_master_get_devdata(master);
1565
1566 spi_imx->slave_aborted = true;
1567 complete(&spi_imx->xfer_done);
1568
1569 return 0;
1570}
1571
1572static int spi_imx_probe(struct platform_device *pdev)
1573{
1574 struct device_node *np = pdev->dev.of_node;
1575 const struct of_device_id *of_id =
1576 of_match_device(spi_imx_dt_ids, &pdev->dev);
1577 struct spi_master *master;
1578 struct spi_imx_data *spi_imx;
1579 struct resource *res;
1580 int ret, irq, spi_drctl;
1581 const struct spi_imx_devtype_data *devtype_data = of_id ? of_id->data :
1582 (struct spi_imx_devtype_data *)pdev->id_entry->driver_data;
1583 bool slave_mode;
1584 u32 val;
1585
1586 slave_mode = devtype_data->has_slavemode &&
1587 of_property_read_bool(np, "spi-slave");
1588 if (slave_mode)
1589 master = spi_alloc_slave(&pdev->dev,
1590 sizeof(struct spi_imx_data));
1591 else
1592 master = spi_alloc_master(&pdev->dev,
1593 sizeof(struct spi_imx_data));
1594 if (!master)
1595 return -ENOMEM;
1596
1597 ret = of_property_read_u32(np, "fsl,spi-rdy-drctl", &spi_drctl);
1598 if ((ret < 0) || (spi_drctl >= 0x3)) {
1599 /* '11' is reserved */
1600 spi_drctl = 0;
1601 }
1602
1603 platform_set_drvdata(pdev, master);
1604
1605 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(1, 32);
1606 master->bus_num = np ? -1 : pdev->id;
1607 master->use_gpio_descriptors = true;
1608
1609 spi_imx = spi_master_get_devdata(master);
1610 spi_imx->bitbang.master = master;
1611 spi_imx->dev = &pdev->dev;
1612 spi_imx->slave_mode = slave_mode;
1613
1614 spi_imx->devtype_data = devtype_data;
1615
1616 /*
1617 * Get number of chip selects from device properties. This can be
1618 * coming from device tree or boardfiles, if it is not defined,
1619 * a default value of 3 chip selects will be used, as all the legacy
1620 * board files have <= 3 chip selects.
1621 */
1622 if (!device_property_read_u32(&pdev->dev, "num-cs", &val))
1623 master->num_chipselect = val;
1624 else
1625 master->num_chipselect = 3;
1626
1627 spi_imx->bitbang.setup_transfer = spi_imx_setupxfer;
1628 spi_imx->bitbang.txrx_bufs = spi_imx_transfer;
1629 spi_imx->bitbang.master->setup = spi_imx_setup;
1630 spi_imx->bitbang.master->cleanup = spi_imx_cleanup;
1631 spi_imx->bitbang.master->prepare_message = spi_imx_prepare_message;
1632 spi_imx->bitbang.master->unprepare_message = spi_imx_unprepare_message;
1633 spi_imx->bitbang.master->slave_abort = spi_imx_slave_abort;
1634 spi_imx->bitbang.master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH \
1635 | SPI_NO_CS;
1636 if (is_imx35_cspi(spi_imx) || is_imx51_ecspi(spi_imx) ||
1637 is_imx53_ecspi(spi_imx))
1638 spi_imx->bitbang.master->mode_bits |= SPI_LOOP | SPI_READY;
1639
1640 spi_imx->spi_drctl = spi_drctl;
1641
1642 init_completion(&spi_imx->xfer_done);
1643
1644 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1645 spi_imx->base = devm_ioremap_resource(&pdev->dev, res);
1646 if (IS_ERR(spi_imx->base)) {
1647 ret = PTR_ERR(spi_imx->base);
1648 goto out_master_put;
1649 }
1650 spi_imx->base_phys = res->start;
1651
1652 irq = platform_get_irq(pdev, 0);
1653 if (irq < 0) {
1654 ret = irq;
1655 goto out_master_put;
1656 }
1657
1658 ret = devm_request_irq(&pdev->dev, irq, spi_imx_isr, 0,
1659 dev_name(&pdev->dev), spi_imx);
1660 if (ret) {
1661 dev_err(&pdev->dev, "can't get irq%d: %d\n", irq, ret);
1662 goto out_master_put;
1663 }
1664
1665 spi_imx->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
1666 if (IS_ERR(spi_imx->clk_ipg)) {
1667 ret = PTR_ERR(spi_imx->clk_ipg);
1668 goto out_master_put;
1669 }
1670
1671 spi_imx->clk_per = devm_clk_get(&pdev->dev, "per");
1672 if (IS_ERR(spi_imx->clk_per)) {
1673 ret = PTR_ERR(spi_imx->clk_per);
1674 goto out_master_put;
1675 }
1676
1677 pm_runtime_enable(spi_imx->dev);
1678 pm_runtime_set_autosuspend_delay(spi_imx->dev, MXC_RPM_TIMEOUT);
1679 pm_runtime_use_autosuspend(spi_imx->dev);
1680
1681 ret = pm_runtime_get_sync(spi_imx->dev);
1682 if (ret < 0) {
1683 dev_err(spi_imx->dev, "failed to enable clock\n");
1684 goto out_runtime_pm_put;
1685 }
1686
1687 spi_imx->spi_clk = clk_get_rate(spi_imx->clk_per);
1688 /*
1689 * Only validated on i.mx35 and i.mx6 now, can remove the constraint
1690 * if validated on other chips.
1691 */
1692 if (spi_imx->devtype_data->has_dmamode) {
1693 ret = spi_imx_sdma_init(&pdev->dev, spi_imx, master);
1694 if (ret == -EPROBE_DEFER)
1695 goto out_runtime_pm_put;
1696
1697 if (ret < 0)
1698 dev_err(&pdev->dev, "dma setup error %d, use pio\n",
1699 ret);
1700 }
1701
1702 spi_imx->devtype_data->reset(spi_imx);
1703
1704 spi_imx->devtype_data->intctrl(spi_imx, 0);
1705
1706 master->dev.of_node = pdev->dev.of_node;
1707 ret = spi_bitbang_start(&spi_imx->bitbang);
1708 if (ret) {
1709 dev_err(&pdev->dev, "bitbang start failed with %d\n", ret);
1710 goto out_runtime_pm_put;
1711 }
1712
1713 dev_info(&pdev->dev, "probed\n");
1714
1715 pm_runtime_mark_last_busy(spi_imx->dev);
1716 pm_runtime_put_autosuspend(spi_imx->dev);
1717
1718 return ret;
1719
1720out_runtime_pm_put:
1721 pm_runtime_dont_use_autosuspend(spi_imx->dev);
1722 pm_runtime_put_sync(spi_imx->dev);
1723 pm_runtime_disable(spi_imx->dev);
1724out_master_put:
1725 spi_master_put(master);
1726
1727 return ret;
1728}
1729
1730static int spi_imx_remove(struct platform_device *pdev)
1731{
1732 struct spi_master *master = platform_get_drvdata(pdev);
1733 struct spi_imx_data *spi_imx = spi_master_get_devdata(master);
1734 int ret;
1735
1736 spi_bitbang_stop(&spi_imx->bitbang);
1737
1738 ret = pm_runtime_get_sync(spi_imx->dev);
1739 if (ret < 0) {
1740 dev_err(spi_imx->dev, "failed to enable clock\n");
1741 return ret;
1742 }
1743
1744 writel(0, spi_imx->base + MXC_CSPICTRL);
1745
1746 pm_runtime_dont_use_autosuspend(spi_imx->dev);
1747 pm_runtime_put_sync(spi_imx->dev);
1748 pm_runtime_disable(spi_imx->dev);
1749
1750 spi_imx_sdma_exit(spi_imx);
1751 spi_master_put(master);
1752
1753 return 0;
1754}
1755
1756static int __maybe_unused spi_imx_runtime_resume(struct device *dev)
1757{
1758 struct spi_master *master = dev_get_drvdata(dev);
1759 struct spi_imx_data *spi_imx;
1760 int ret;
1761
1762 spi_imx = spi_master_get_devdata(master);
1763
1764 ret = clk_prepare_enable(spi_imx->clk_per);
1765 if (ret)
1766 return ret;
1767
1768 ret = clk_prepare_enable(spi_imx->clk_ipg);
1769 if (ret) {
1770 clk_disable_unprepare(spi_imx->clk_per);
1771 return ret;
1772 }
1773
1774 return 0;
1775}
1776
1777static int __maybe_unused spi_imx_runtime_suspend(struct device *dev)
1778{
1779 struct spi_master *master = dev_get_drvdata(dev);
1780 struct spi_imx_data *spi_imx;
1781
1782 spi_imx = spi_master_get_devdata(master);
1783
1784 clk_disable_unprepare(spi_imx->clk_per);
1785 clk_disable_unprepare(spi_imx->clk_ipg);
1786
1787 return 0;
1788}
1789
1790static int __maybe_unused spi_imx_suspend(struct device *dev)
1791{
1792 pinctrl_pm_select_sleep_state(dev);
1793 return 0;
1794}
1795
1796static int __maybe_unused spi_imx_resume(struct device *dev)
1797{
1798 pinctrl_pm_select_default_state(dev);
1799 return 0;
1800}
1801
1802static const struct dev_pm_ops imx_spi_pm = {
1803 SET_RUNTIME_PM_OPS(spi_imx_runtime_suspend,
1804 spi_imx_runtime_resume, NULL)
1805 SET_SYSTEM_SLEEP_PM_OPS(spi_imx_suspend, spi_imx_resume)
1806};
1807
1808static struct platform_driver spi_imx_driver = {
1809 .driver = {
1810 .name = DRIVER_NAME,
1811 .of_match_table = spi_imx_dt_ids,
1812 .pm = &imx_spi_pm,
1813 },
1814 .id_table = spi_imx_devtype,
1815 .probe = spi_imx_probe,
1816 .remove = spi_imx_remove,
1817};
1818module_platform_driver(spi_imx_driver);
1819
1820MODULE_DESCRIPTION("SPI Controller driver");
1821MODULE_AUTHOR("Sascha Hauer, Pengutronix");
1822MODULE_LICENSE("GPL");
1823MODULE_ALIAS("platform:" DRIVER_NAME);
1/*
2 * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
3 * Copyright (C) 2008 Juergen Beisert
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the
16 * Free Software Foundation
17 * 51 Franklin Street, Fifth Floor
18 * Boston, MA 02110-1301, USA.
19 */
20
21#include <linux/clk.h>
22#include <linux/completion.h>
23#include <linux/delay.h>
24#include <linux/dmaengine.h>
25#include <linux/dma-mapping.h>
26#include <linux/err.h>
27#include <linux/gpio.h>
28#include <linux/interrupt.h>
29#include <linux/io.h>
30#include <linux/irq.h>
31#include <linux/kernel.h>
32#include <linux/module.h>
33#include <linux/platform_device.h>
34#include <linux/slab.h>
35#include <linux/spi/spi.h>
36#include <linux/spi/spi_bitbang.h>
37#include <linux/types.h>
38#include <linux/of.h>
39#include <linux/of_device.h>
40#include <linux/of_gpio.h>
41
42#include <linux/platform_data/dma-imx.h>
43#include <linux/platform_data/spi-imx.h>
44
45#define DRIVER_NAME "spi_imx"
46
47#define MXC_CSPIRXDATA 0x00
48#define MXC_CSPITXDATA 0x04
49#define MXC_CSPICTRL 0x08
50#define MXC_CSPIINT 0x0c
51#define MXC_RESET 0x1c
52
53/* generic defines to abstract from the different register layouts */
54#define MXC_INT_RR (1 << 0) /* Receive data ready interrupt */
55#define MXC_INT_TE (1 << 1) /* Transmit FIFO empty interrupt */
56
57/* The maximum bytes that a sdma BD can transfer.*/
58#define MAX_SDMA_BD_BYTES (1 << 15)
59struct spi_imx_config {
60 unsigned int speed_hz;
61 unsigned int bpw;
62 unsigned int mode;
63 u8 cs;
64};
65
66enum spi_imx_devtype {
67 IMX1_CSPI,
68 IMX21_CSPI,
69 IMX27_CSPI,
70 IMX31_CSPI,
71 IMX35_CSPI, /* CSPI on all i.mx except above */
72 IMX51_ECSPI, /* ECSPI on i.mx51 and later */
73};
74
75struct spi_imx_data;
76
77struct spi_imx_devtype_data {
78 void (*intctrl)(struct spi_imx_data *, int);
79 int (*config)(struct spi_imx_data *, struct spi_imx_config *);
80 void (*trigger)(struct spi_imx_data *);
81 int (*rx_available)(struct spi_imx_data *);
82 void (*reset)(struct spi_imx_data *);
83 enum spi_imx_devtype devtype;
84};
85
86struct spi_imx_data {
87 struct spi_bitbang bitbang;
88 struct device *dev;
89
90 struct completion xfer_done;
91 void __iomem *base;
92 unsigned long base_phys;
93
94 struct clk *clk_per;
95 struct clk *clk_ipg;
96 unsigned long spi_clk;
97 unsigned int spi_bus_clk;
98
99 unsigned int bytes_per_word;
100
101 unsigned int count;
102 void (*tx)(struct spi_imx_data *);
103 void (*rx)(struct spi_imx_data *);
104 void *rx_buf;
105 const void *tx_buf;
106 unsigned int txfifo; /* number of words pushed in tx FIFO */
107
108 /* DMA */
109 bool usedma;
110 u32 wml;
111 struct completion dma_rx_completion;
112 struct completion dma_tx_completion;
113
114 const struct spi_imx_devtype_data *devtype_data;
115 int chipselect[0];
116};
117
118static inline int is_imx27_cspi(struct spi_imx_data *d)
119{
120 return d->devtype_data->devtype == IMX27_CSPI;
121}
122
123static inline int is_imx35_cspi(struct spi_imx_data *d)
124{
125 return d->devtype_data->devtype == IMX35_CSPI;
126}
127
128static inline int is_imx51_ecspi(struct spi_imx_data *d)
129{
130 return d->devtype_data->devtype == IMX51_ECSPI;
131}
132
133static inline unsigned spi_imx_get_fifosize(struct spi_imx_data *d)
134{
135 return is_imx51_ecspi(d) ? 64 : 8;
136}
137
138#define MXC_SPI_BUF_RX(type) \
139static void spi_imx_buf_rx_##type(struct spi_imx_data *spi_imx) \
140{ \
141 unsigned int val = readl(spi_imx->base + MXC_CSPIRXDATA); \
142 \
143 if (spi_imx->rx_buf) { \
144 *(type *)spi_imx->rx_buf = val; \
145 spi_imx->rx_buf += sizeof(type); \
146 } \
147}
148
149#define MXC_SPI_BUF_TX(type) \
150static void spi_imx_buf_tx_##type(struct spi_imx_data *spi_imx) \
151{ \
152 type val = 0; \
153 \
154 if (spi_imx->tx_buf) { \
155 val = *(type *)spi_imx->tx_buf; \
156 spi_imx->tx_buf += sizeof(type); \
157 } \
158 \
159 spi_imx->count -= sizeof(type); \
160 \
161 writel(val, spi_imx->base + MXC_CSPITXDATA); \
162}
163
164MXC_SPI_BUF_RX(u8)
165MXC_SPI_BUF_TX(u8)
166MXC_SPI_BUF_RX(u16)
167MXC_SPI_BUF_TX(u16)
168MXC_SPI_BUF_RX(u32)
169MXC_SPI_BUF_TX(u32)
170
171/* First entry is reserved, second entry is valid only if SDHC_SPIEN is set
172 * (which is currently not the case in this driver)
173 */
174static int mxc_clkdivs[] = {0, 3, 4, 6, 8, 12, 16, 24, 32, 48, 64, 96, 128, 192,
175 256, 384, 512, 768, 1024};
176
177/* MX21, MX27 */
178static unsigned int spi_imx_clkdiv_1(unsigned int fin,
179 unsigned int fspi, unsigned int max)
180{
181 int i;
182
183 for (i = 2; i < max; i++)
184 if (fspi * mxc_clkdivs[i] >= fin)
185 return i;
186
187 return max;
188}
189
190/* MX1, MX31, MX35, MX51 CSPI */
191static unsigned int spi_imx_clkdiv_2(unsigned int fin,
192 unsigned int fspi)
193{
194 int i, div = 4;
195
196 for (i = 0; i < 7; i++) {
197 if (fspi * div >= fin)
198 return i;
199 div <<= 1;
200 }
201
202 return 7;
203}
204
205static int spi_imx_bytes_per_word(const int bpw)
206{
207 return DIV_ROUND_UP(bpw, BITS_PER_BYTE);
208}
209
210static bool spi_imx_can_dma(struct spi_master *master, struct spi_device *spi,
211 struct spi_transfer *transfer)
212{
213 struct spi_imx_data *spi_imx = spi_master_get_devdata(master);
214 unsigned int bpw;
215
216 if (!master->dma_rx)
217 return false;
218
219 if (!transfer)
220 return false;
221
222 bpw = transfer->bits_per_word;
223 if (!bpw)
224 bpw = spi->bits_per_word;
225
226 bpw = spi_imx_bytes_per_word(bpw);
227
228 if (bpw != 1 && bpw != 2 && bpw != 4)
229 return false;
230
231 if (transfer->len < spi_imx->wml * bpw)
232 return false;
233
234 if (transfer->len % (spi_imx->wml * bpw))
235 return false;
236
237 return true;
238}
239
240#define MX51_ECSPI_CTRL 0x08
241#define MX51_ECSPI_CTRL_ENABLE (1 << 0)
242#define MX51_ECSPI_CTRL_XCH (1 << 2)
243#define MX51_ECSPI_CTRL_SMC (1 << 3)
244#define MX51_ECSPI_CTRL_MODE_MASK (0xf << 4)
245#define MX51_ECSPI_CTRL_POSTDIV_OFFSET 8
246#define MX51_ECSPI_CTRL_PREDIV_OFFSET 12
247#define MX51_ECSPI_CTRL_CS(cs) ((cs) << 18)
248#define MX51_ECSPI_CTRL_BL_OFFSET 20
249
250#define MX51_ECSPI_CONFIG 0x0c
251#define MX51_ECSPI_CONFIG_SCLKPHA(cs) (1 << ((cs) + 0))
252#define MX51_ECSPI_CONFIG_SCLKPOL(cs) (1 << ((cs) + 4))
253#define MX51_ECSPI_CONFIG_SBBCTRL(cs) (1 << ((cs) + 8))
254#define MX51_ECSPI_CONFIG_SSBPOL(cs) (1 << ((cs) + 12))
255#define MX51_ECSPI_CONFIG_SCLKCTL(cs) (1 << ((cs) + 20))
256
257#define MX51_ECSPI_INT 0x10
258#define MX51_ECSPI_INT_TEEN (1 << 0)
259#define MX51_ECSPI_INT_RREN (1 << 3)
260
261#define MX51_ECSPI_DMA 0x14
262#define MX51_ECSPI_DMA_TX_WML(wml) ((wml) & 0x3f)
263#define MX51_ECSPI_DMA_RX_WML(wml) (((wml) & 0x3f) << 16)
264#define MX51_ECSPI_DMA_RXT_WML(wml) (((wml) & 0x3f) << 24)
265
266#define MX51_ECSPI_DMA_TEDEN (1 << 7)
267#define MX51_ECSPI_DMA_RXDEN (1 << 23)
268#define MX51_ECSPI_DMA_RXTDEN (1 << 31)
269
270#define MX51_ECSPI_STAT 0x18
271#define MX51_ECSPI_STAT_RR (1 << 3)
272
273#define MX51_ECSPI_TESTREG 0x20
274#define MX51_ECSPI_TESTREG_LBC BIT(31)
275
276/* MX51 eCSPI */
277static unsigned int mx51_ecspi_clkdiv(struct spi_imx_data *spi_imx,
278 unsigned int fspi, unsigned int *fres)
279{
280 /*
281 * there are two 4-bit dividers, the pre-divider divides by
282 * $pre, the post-divider by 2^$post
283 */
284 unsigned int pre, post;
285 unsigned int fin = spi_imx->spi_clk;
286
287 if (unlikely(fspi > fin))
288 return 0;
289
290 post = fls(fin) - fls(fspi);
291 if (fin > fspi << post)
292 post++;
293
294 /* now we have: (fin <= fspi << post) with post being minimal */
295
296 post = max(4U, post) - 4;
297 if (unlikely(post > 0xf)) {
298 dev_err(spi_imx->dev, "cannot set clock freq: %u (base freq: %u)\n",
299 fspi, fin);
300 return 0xff;
301 }
302
303 pre = DIV_ROUND_UP(fin, fspi << post) - 1;
304
305 dev_dbg(spi_imx->dev, "%s: fin: %u, fspi: %u, post: %u, pre: %u\n",
306 __func__, fin, fspi, post, pre);
307
308 /* Resulting frequency for the SCLK line. */
309 *fres = (fin / (pre + 1)) >> post;
310
311 return (pre << MX51_ECSPI_CTRL_PREDIV_OFFSET) |
312 (post << MX51_ECSPI_CTRL_POSTDIV_OFFSET);
313}
314
315static void __maybe_unused mx51_ecspi_intctrl(struct spi_imx_data *spi_imx, int enable)
316{
317 unsigned val = 0;
318
319 if (enable & MXC_INT_TE)
320 val |= MX51_ECSPI_INT_TEEN;
321
322 if (enable & MXC_INT_RR)
323 val |= MX51_ECSPI_INT_RREN;
324
325 writel(val, spi_imx->base + MX51_ECSPI_INT);
326}
327
328static void __maybe_unused mx51_ecspi_trigger(struct spi_imx_data *spi_imx)
329{
330 u32 reg;
331
332 reg = readl(spi_imx->base + MX51_ECSPI_CTRL);
333 reg |= MX51_ECSPI_CTRL_XCH;
334 writel(reg, spi_imx->base + MX51_ECSPI_CTRL);
335}
336
337static int __maybe_unused mx51_ecspi_config(struct spi_imx_data *spi_imx,
338 struct spi_imx_config *config)
339{
340 u32 ctrl = MX51_ECSPI_CTRL_ENABLE;
341 u32 clk = config->speed_hz, delay, reg;
342 u32 cfg = readl(spi_imx->base + MX51_ECSPI_CONFIG);
343
344 /*
345 * The hardware seems to have a race condition when changing modes. The
346 * current assumption is that the selection of the channel arrives
347 * earlier in the hardware than the mode bits when they are written at
348 * the same time.
349 * So set master mode for all channels as we do not support slave mode.
350 */
351 ctrl |= MX51_ECSPI_CTRL_MODE_MASK;
352
353 /* set clock speed */
354 ctrl |= mx51_ecspi_clkdiv(spi_imx, config->speed_hz, &clk);
355 spi_imx->spi_bus_clk = clk;
356
357 /* set chip select to use */
358 ctrl |= MX51_ECSPI_CTRL_CS(config->cs);
359
360 ctrl |= (config->bpw - 1) << MX51_ECSPI_CTRL_BL_OFFSET;
361
362 cfg |= MX51_ECSPI_CONFIG_SBBCTRL(config->cs);
363
364 if (config->mode & SPI_CPHA)
365 cfg |= MX51_ECSPI_CONFIG_SCLKPHA(config->cs);
366 else
367 cfg &= ~MX51_ECSPI_CONFIG_SCLKPHA(config->cs);
368
369 if (config->mode & SPI_CPOL) {
370 cfg |= MX51_ECSPI_CONFIG_SCLKPOL(config->cs);
371 cfg |= MX51_ECSPI_CONFIG_SCLKCTL(config->cs);
372 } else {
373 cfg &= ~MX51_ECSPI_CONFIG_SCLKPOL(config->cs);
374 cfg &= ~MX51_ECSPI_CONFIG_SCLKCTL(config->cs);
375 }
376 if (config->mode & SPI_CS_HIGH)
377 cfg |= MX51_ECSPI_CONFIG_SSBPOL(config->cs);
378 else
379 cfg &= ~MX51_ECSPI_CONFIG_SSBPOL(config->cs);
380
381 if (spi_imx->usedma)
382 ctrl |= MX51_ECSPI_CTRL_SMC;
383
384 /* CTRL register always go first to bring out controller from reset */
385 writel(ctrl, spi_imx->base + MX51_ECSPI_CTRL);
386
387 reg = readl(spi_imx->base + MX51_ECSPI_TESTREG);
388 if (config->mode & SPI_LOOP)
389 reg |= MX51_ECSPI_TESTREG_LBC;
390 else
391 reg &= ~MX51_ECSPI_TESTREG_LBC;
392 writel(reg, spi_imx->base + MX51_ECSPI_TESTREG);
393
394 writel(cfg, spi_imx->base + MX51_ECSPI_CONFIG);
395
396 /*
397 * Wait until the changes in the configuration register CONFIGREG
398 * propagate into the hardware. It takes exactly one tick of the
399 * SCLK clock, but we will wait two SCLK clock just to be sure. The
400 * effect of the delay it takes for the hardware to apply changes
401 * is noticable if the SCLK clock run very slow. In such a case, if
402 * the polarity of SCLK should be inverted, the GPIO ChipSelect might
403 * be asserted before the SCLK polarity changes, which would disrupt
404 * the SPI communication as the device on the other end would consider
405 * the change of SCLK polarity as a clock tick already.
406 */
407 delay = (2 * 1000000) / clk;
408 if (likely(delay < 10)) /* SCLK is faster than 100 kHz */
409 udelay(delay);
410 else /* SCLK is _very_ slow */
411 usleep_range(delay, delay + 10);
412
413 /*
414 * Configure the DMA register: setup the watermark
415 * and enable DMA request.
416 */
417
418 writel(MX51_ECSPI_DMA_RX_WML(spi_imx->wml) |
419 MX51_ECSPI_DMA_TX_WML(spi_imx->wml) |
420 MX51_ECSPI_DMA_RXT_WML(spi_imx->wml) |
421 MX51_ECSPI_DMA_TEDEN | MX51_ECSPI_DMA_RXDEN |
422 MX51_ECSPI_DMA_RXTDEN, spi_imx->base + MX51_ECSPI_DMA);
423
424 return 0;
425}
426
427static int __maybe_unused mx51_ecspi_rx_available(struct spi_imx_data *spi_imx)
428{
429 return readl(spi_imx->base + MX51_ECSPI_STAT) & MX51_ECSPI_STAT_RR;
430}
431
432static void __maybe_unused mx51_ecspi_reset(struct spi_imx_data *spi_imx)
433{
434 /* drain receive buffer */
435 while (mx51_ecspi_rx_available(spi_imx))
436 readl(spi_imx->base + MXC_CSPIRXDATA);
437}
438
439#define MX31_INTREG_TEEN (1 << 0)
440#define MX31_INTREG_RREN (1 << 3)
441
442#define MX31_CSPICTRL_ENABLE (1 << 0)
443#define MX31_CSPICTRL_MASTER (1 << 1)
444#define MX31_CSPICTRL_XCH (1 << 2)
445#define MX31_CSPICTRL_POL (1 << 4)
446#define MX31_CSPICTRL_PHA (1 << 5)
447#define MX31_CSPICTRL_SSCTL (1 << 6)
448#define MX31_CSPICTRL_SSPOL (1 << 7)
449#define MX31_CSPICTRL_BC_SHIFT 8
450#define MX35_CSPICTRL_BL_SHIFT 20
451#define MX31_CSPICTRL_CS_SHIFT 24
452#define MX35_CSPICTRL_CS_SHIFT 12
453#define MX31_CSPICTRL_DR_SHIFT 16
454
455#define MX31_CSPISTATUS 0x14
456#define MX31_STATUS_RR (1 << 3)
457
458/* These functions also work for the i.MX35, but be aware that
459 * the i.MX35 has a slightly different register layout for bits
460 * we do not use here.
461 */
462static void __maybe_unused mx31_intctrl(struct spi_imx_data *spi_imx, int enable)
463{
464 unsigned int val = 0;
465
466 if (enable & MXC_INT_TE)
467 val |= MX31_INTREG_TEEN;
468 if (enable & MXC_INT_RR)
469 val |= MX31_INTREG_RREN;
470
471 writel(val, spi_imx->base + MXC_CSPIINT);
472}
473
474static void __maybe_unused mx31_trigger(struct spi_imx_data *spi_imx)
475{
476 unsigned int reg;
477
478 reg = readl(spi_imx->base + MXC_CSPICTRL);
479 reg |= MX31_CSPICTRL_XCH;
480 writel(reg, spi_imx->base + MXC_CSPICTRL);
481}
482
483static int __maybe_unused mx31_config(struct spi_imx_data *spi_imx,
484 struct spi_imx_config *config)
485{
486 unsigned int reg = MX31_CSPICTRL_ENABLE | MX31_CSPICTRL_MASTER;
487 int cs = spi_imx->chipselect[config->cs];
488
489 reg |= spi_imx_clkdiv_2(spi_imx->spi_clk, config->speed_hz) <<
490 MX31_CSPICTRL_DR_SHIFT;
491
492 if (is_imx35_cspi(spi_imx)) {
493 reg |= (config->bpw - 1) << MX35_CSPICTRL_BL_SHIFT;
494 reg |= MX31_CSPICTRL_SSCTL;
495 } else {
496 reg |= (config->bpw - 1) << MX31_CSPICTRL_BC_SHIFT;
497 }
498
499 if (config->mode & SPI_CPHA)
500 reg |= MX31_CSPICTRL_PHA;
501 if (config->mode & SPI_CPOL)
502 reg |= MX31_CSPICTRL_POL;
503 if (config->mode & SPI_CS_HIGH)
504 reg |= MX31_CSPICTRL_SSPOL;
505 if (cs < 0)
506 reg |= (cs + 32) <<
507 (is_imx35_cspi(spi_imx) ? MX35_CSPICTRL_CS_SHIFT :
508 MX31_CSPICTRL_CS_SHIFT);
509
510 writel(reg, spi_imx->base + MXC_CSPICTRL);
511
512 return 0;
513}
514
515static int __maybe_unused mx31_rx_available(struct spi_imx_data *spi_imx)
516{
517 return readl(spi_imx->base + MX31_CSPISTATUS) & MX31_STATUS_RR;
518}
519
520static void __maybe_unused mx31_reset(struct spi_imx_data *spi_imx)
521{
522 /* drain receive buffer */
523 while (readl(spi_imx->base + MX31_CSPISTATUS) & MX31_STATUS_RR)
524 readl(spi_imx->base + MXC_CSPIRXDATA);
525}
526
527#define MX21_INTREG_RR (1 << 4)
528#define MX21_INTREG_TEEN (1 << 9)
529#define MX21_INTREG_RREN (1 << 13)
530
531#define MX21_CSPICTRL_POL (1 << 5)
532#define MX21_CSPICTRL_PHA (1 << 6)
533#define MX21_CSPICTRL_SSPOL (1 << 8)
534#define MX21_CSPICTRL_XCH (1 << 9)
535#define MX21_CSPICTRL_ENABLE (1 << 10)
536#define MX21_CSPICTRL_MASTER (1 << 11)
537#define MX21_CSPICTRL_DR_SHIFT 14
538#define MX21_CSPICTRL_CS_SHIFT 19
539
540static void __maybe_unused mx21_intctrl(struct spi_imx_data *spi_imx, int enable)
541{
542 unsigned int val = 0;
543
544 if (enable & MXC_INT_TE)
545 val |= MX21_INTREG_TEEN;
546 if (enable & MXC_INT_RR)
547 val |= MX21_INTREG_RREN;
548
549 writel(val, spi_imx->base + MXC_CSPIINT);
550}
551
552static void __maybe_unused mx21_trigger(struct spi_imx_data *spi_imx)
553{
554 unsigned int reg;
555
556 reg = readl(spi_imx->base + MXC_CSPICTRL);
557 reg |= MX21_CSPICTRL_XCH;
558 writel(reg, spi_imx->base + MXC_CSPICTRL);
559}
560
561static int __maybe_unused mx21_config(struct spi_imx_data *spi_imx,
562 struct spi_imx_config *config)
563{
564 unsigned int reg = MX21_CSPICTRL_ENABLE | MX21_CSPICTRL_MASTER;
565 int cs = spi_imx->chipselect[config->cs];
566 unsigned int max = is_imx27_cspi(spi_imx) ? 16 : 18;
567
568 reg |= spi_imx_clkdiv_1(spi_imx->spi_clk, config->speed_hz, max) <<
569 MX21_CSPICTRL_DR_SHIFT;
570 reg |= config->bpw - 1;
571
572 if (config->mode & SPI_CPHA)
573 reg |= MX21_CSPICTRL_PHA;
574 if (config->mode & SPI_CPOL)
575 reg |= MX21_CSPICTRL_POL;
576 if (config->mode & SPI_CS_HIGH)
577 reg |= MX21_CSPICTRL_SSPOL;
578 if (cs < 0)
579 reg |= (cs + 32) << MX21_CSPICTRL_CS_SHIFT;
580
581 writel(reg, spi_imx->base + MXC_CSPICTRL);
582
583 return 0;
584}
585
586static int __maybe_unused mx21_rx_available(struct spi_imx_data *spi_imx)
587{
588 return readl(spi_imx->base + MXC_CSPIINT) & MX21_INTREG_RR;
589}
590
591static void __maybe_unused mx21_reset(struct spi_imx_data *spi_imx)
592{
593 writel(1, spi_imx->base + MXC_RESET);
594}
595
596#define MX1_INTREG_RR (1 << 3)
597#define MX1_INTREG_TEEN (1 << 8)
598#define MX1_INTREG_RREN (1 << 11)
599
600#define MX1_CSPICTRL_POL (1 << 4)
601#define MX1_CSPICTRL_PHA (1 << 5)
602#define MX1_CSPICTRL_XCH (1 << 8)
603#define MX1_CSPICTRL_ENABLE (1 << 9)
604#define MX1_CSPICTRL_MASTER (1 << 10)
605#define MX1_CSPICTRL_DR_SHIFT 13
606
607static void __maybe_unused mx1_intctrl(struct spi_imx_data *spi_imx, int enable)
608{
609 unsigned int val = 0;
610
611 if (enable & MXC_INT_TE)
612 val |= MX1_INTREG_TEEN;
613 if (enable & MXC_INT_RR)
614 val |= MX1_INTREG_RREN;
615
616 writel(val, spi_imx->base + MXC_CSPIINT);
617}
618
619static void __maybe_unused mx1_trigger(struct spi_imx_data *spi_imx)
620{
621 unsigned int reg;
622
623 reg = readl(spi_imx->base + MXC_CSPICTRL);
624 reg |= MX1_CSPICTRL_XCH;
625 writel(reg, spi_imx->base + MXC_CSPICTRL);
626}
627
628static int __maybe_unused mx1_config(struct spi_imx_data *spi_imx,
629 struct spi_imx_config *config)
630{
631 unsigned int reg = MX1_CSPICTRL_ENABLE | MX1_CSPICTRL_MASTER;
632
633 reg |= spi_imx_clkdiv_2(spi_imx->spi_clk, config->speed_hz) <<
634 MX1_CSPICTRL_DR_SHIFT;
635 reg |= config->bpw - 1;
636
637 if (config->mode & SPI_CPHA)
638 reg |= MX1_CSPICTRL_PHA;
639 if (config->mode & SPI_CPOL)
640 reg |= MX1_CSPICTRL_POL;
641
642 writel(reg, spi_imx->base + MXC_CSPICTRL);
643
644 return 0;
645}
646
647static int __maybe_unused mx1_rx_available(struct spi_imx_data *spi_imx)
648{
649 return readl(spi_imx->base + MXC_CSPIINT) & MX1_INTREG_RR;
650}
651
652static void __maybe_unused mx1_reset(struct spi_imx_data *spi_imx)
653{
654 writel(1, spi_imx->base + MXC_RESET);
655}
656
657static struct spi_imx_devtype_data imx1_cspi_devtype_data = {
658 .intctrl = mx1_intctrl,
659 .config = mx1_config,
660 .trigger = mx1_trigger,
661 .rx_available = mx1_rx_available,
662 .reset = mx1_reset,
663 .devtype = IMX1_CSPI,
664};
665
666static struct spi_imx_devtype_data imx21_cspi_devtype_data = {
667 .intctrl = mx21_intctrl,
668 .config = mx21_config,
669 .trigger = mx21_trigger,
670 .rx_available = mx21_rx_available,
671 .reset = mx21_reset,
672 .devtype = IMX21_CSPI,
673};
674
675static struct spi_imx_devtype_data imx27_cspi_devtype_data = {
676 /* i.mx27 cspi shares the functions with i.mx21 one */
677 .intctrl = mx21_intctrl,
678 .config = mx21_config,
679 .trigger = mx21_trigger,
680 .rx_available = mx21_rx_available,
681 .reset = mx21_reset,
682 .devtype = IMX27_CSPI,
683};
684
685static struct spi_imx_devtype_data imx31_cspi_devtype_data = {
686 .intctrl = mx31_intctrl,
687 .config = mx31_config,
688 .trigger = mx31_trigger,
689 .rx_available = mx31_rx_available,
690 .reset = mx31_reset,
691 .devtype = IMX31_CSPI,
692};
693
694static struct spi_imx_devtype_data imx35_cspi_devtype_data = {
695 /* i.mx35 and later cspi shares the functions with i.mx31 one */
696 .intctrl = mx31_intctrl,
697 .config = mx31_config,
698 .trigger = mx31_trigger,
699 .rx_available = mx31_rx_available,
700 .reset = mx31_reset,
701 .devtype = IMX35_CSPI,
702};
703
704static struct spi_imx_devtype_data imx51_ecspi_devtype_data = {
705 .intctrl = mx51_ecspi_intctrl,
706 .config = mx51_ecspi_config,
707 .trigger = mx51_ecspi_trigger,
708 .rx_available = mx51_ecspi_rx_available,
709 .reset = mx51_ecspi_reset,
710 .devtype = IMX51_ECSPI,
711};
712
713static const struct platform_device_id spi_imx_devtype[] = {
714 {
715 .name = "imx1-cspi",
716 .driver_data = (kernel_ulong_t) &imx1_cspi_devtype_data,
717 }, {
718 .name = "imx21-cspi",
719 .driver_data = (kernel_ulong_t) &imx21_cspi_devtype_data,
720 }, {
721 .name = "imx27-cspi",
722 .driver_data = (kernel_ulong_t) &imx27_cspi_devtype_data,
723 }, {
724 .name = "imx31-cspi",
725 .driver_data = (kernel_ulong_t) &imx31_cspi_devtype_data,
726 }, {
727 .name = "imx35-cspi",
728 .driver_data = (kernel_ulong_t) &imx35_cspi_devtype_data,
729 }, {
730 .name = "imx51-ecspi",
731 .driver_data = (kernel_ulong_t) &imx51_ecspi_devtype_data,
732 }, {
733 /* sentinel */
734 }
735};
736
737static const struct of_device_id spi_imx_dt_ids[] = {
738 { .compatible = "fsl,imx1-cspi", .data = &imx1_cspi_devtype_data, },
739 { .compatible = "fsl,imx21-cspi", .data = &imx21_cspi_devtype_data, },
740 { .compatible = "fsl,imx27-cspi", .data = &imx27_cspi_devtype_data, },
741 { .compatible = "fsl,imx31-cspi", .data = &imx31_cspi_devtype_data, },
742 { .compatible = "fsl,imx35-cspi", .data = &imx35_cspi_devtype_data, },
743 { .compatible = "fsl,imx51-ecspi", .data = &imx51_ecspi_devtype_data, },
744 { /* sentinel */ }
745};
746MODULE_DEVICE_TABLE(of, spi_imx_dt_ids);
747
748static void spi_imx_chipselect(struct spi_device *spi, int is_active)
749{
750 struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
751 int gpio = spi_imx->chipselect[spi->chip_select];
752 int active = is_active != BITBANG_CS_INACTIVE;
753 int dev_is_lowactive = !(spi->mode & SPI_CS_HIGH);
754
755 if (!gpio_is_valid(gpio))
756 return;
757
758 gpio_set_value(gpio, dev_is_lowactive ^ active);
759}
760
761static void spi_imx_push(struct spi_imx_data *spi_imx)
762{
763 while (spi_imx->txfifo < spi_imx_get_fifosize(spi_imx)) {
764 if (!spi_imx->count)
765 break;
766 spi_imx->tx(spi_imx);
767 spi_imx->txfifo++;
768 }
769
770 spi_imx->devtype_data->trigger(spi_imx);
771}
772
773static irqreturn_t spi_imx_isr(int irq, void *dev_id)
774{
775 struct spi_imx_data *spi_imx = dev_id;
776
777 while (spi_imx->devtype_data->rx_available(spi_imx)) {
778 spi_imx->rx(spi_imx);
779 spi_imx->txfifo--;
780 }
781
782 if (spi_imx->count) {
783 spi_imx_push(spi_imx);
784 return IRQ_HANDLED;
785 }
786
787 if (spi_imx->txfifo) {
788 /* No data left to push, but still waiting for rx data,
789 * enable receive data available interrupt.
790 */
791 spi_imx->devtype_data->intctrl(
792 spi_imx, MXC_INT_RR);
793 return IRQ_HANDLED;
794 }
795
796 spi_imx->devtype_data->intctrl(spi_imx, 0);
797 complete(&spi_imx->xfer_done);
798
799 return IRQ_HANDLED;
800}
801
802static int spi_imx_dma_configure(struct spi_master *master,
803 int bytes_per_word)
804{
805 int ret;
806 enum dma_slave_buswidth buswidth;
807 struct dma_slave_config rx = {}, tx = {};
808 struct spi_imx_data *spi_imx = spi_master_get_devdata(master);
809
810 if (bytes_per_word == spi_imx->bytes_per_word)
811 /* Same as last time */
812 return 0;
813
814 switch (bytes_per_word) {
815 case 4:
816 buswidth = DMA_SLAVE_BUSWIDTH_4_BYTES;
817 break;
818 case 2:
819 buswidth = DMA_SLAVE_BUSWIDTH_2_BYTES;
820 break;
821 case 1:
822 buswidth = DMA_SLAVE_BUSWIDTH_1_BYTE;
823 break;
824 default:
825 return -EINVAL;
826 }
827
828 tx.direction = DMA_MEM_TO_DEV;
829 tx.dst_addr = spi_imx->base_phys + MXC_CSPITXDATA;
830 tx.dst_addr_width = buswidth;
831 tx.dst_maxburst = spi_imx->wml;
832 ret = dmaengine_slave_config(master->dma_tx, &tx);
833 if (ret) {
834 dev_err(spi_imx->dev, "TX dma configuration failed with %d\n", ret);
835 return ret;
836 }
837
838 rx.direction = DMA_DEV_TO_MEM;
839 rx.src_addr = spi_imx->base_phys + MXC_CSPIRXDATA;
840 rx.src_addr_width = buswidth;
841 rx.src_maxburst = spi_imx->wml;
842 ret = dmaengine_slave_config(master->dma_rx, &rx);
843 if (ret) {
844 dev_err(spi_imx->dev, "RX dma configuration failed with %d\n", ret);
845 return ret;
846 }
847
848 spi_imx->bytes_per_word = bytes_per_word;
849
850 return 0;
851}
852
853static int spi_imx_setupxfer(struct spi_device *spi,
854 struct spi_transfer *t)
855{
856 struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
857 struct spi_imx_config config;
858 int ret;
859
860 config.bpw = t ? t->bits_per_word : spi->bits_per_word;
861 config.speed_hz = t ? t->speed_hz : spi->max_speed_hz;
862 config.mode = spi->mode;
863 config.cs = spi->chip_select;
864
865 if (!config.speed_hz)
866 config.speed_hz = spi->max_speed_hz;
867 if (!config.bpw)
868 config.bpw = spi->bits_per_word;
869
870 /* Initialize the functions for transfer */
871 if (config.bpw <= 8) {
872 spi_imx->rx = spi_imx_buf_rx_u8;
873 spi_imx->tx = spi_imx_buf_tx_u8;
874 } else if (config.bpw <= 16) {
875 spi_imx->rx = spi_imx_buf_rx_u16;
876 spi_imx->tx = spi_imx_buf_tx_u16;
877 } else {
878 spi_imx->rx = spi_imx_buf_rx_u32;
879 spi_imx->tx = spi_imx_buf_tx_u32;
880 }
881
882 if (spi_imx_can_dma(spi_imx->bitbang.master, spi, t))
883 spi_imx->usedma = 1;
884 else
885 spi_imx->usedma = 0;
886
887 if (spi_imx->usedma) {
888 ret = spi_imx_dma_configure(spi->master,
889 spi_imx_bytes_per_word(config.bpw));
890 if (ret)
891 return ret;
892 }
893
894 spi_imx->devtype_data->config(spi_imx, &config);
895
896 return 0;
897}
898
899static void spi_imx_sdma_exit(struct spi_imx_data *spi_imx)
900{
901 struct spi_master *master = spi_imx->bitbang.master;
902
903 if (master->dma_rx) {
904 dma_release_channel(master->dma_rx);
905 master->dma_rx = NULL;
906 }
907
908 if (master->dma_tx) {
909 dma_release_channel(master->dma_tx);
910 master->dma_tx = NULL;
911 }
912}
913
914static int spi_imx_sdma_init(struct device *dev, struct spi_imx_data *spi_imx,
915 struct spi_master *master)
916{
917 int ret;
918
919 /* use pio mode for i.mx6dl chip TKT238285 */
920 if (of_machine_is_compatible("fsl,imx6dl"))
921 return 0;
922
923 spi_imx->wml = spi_imx_get_fifosize(spi_imx) / 2;
924
925 /* Prepare for TX DMA: */
926 master->dma_tx = dma_request_slave_channel_reason(dev, "tx");
927 if (IS_ERR(master->dma_tx)) {
928 ret = PTR_ERR(master->dma_tx);
929 dev_dbg(dev, "can't get the TX DMA channel, error %d!\n", ret);
930 master->dma_tx = NULL;
931 goto err;
932 }
933
934 /* Prepare for RX : */
935 master->dma_rx = dma_request_slave_channel_reason(dev, "rx");
936 if (IS_ERR(master->dma_rx)) {
937 ret = PTR_ERR(master->dma_rx);
938 dev_dbg(dev, "can't get the RX DMA channel, error %d\n", ret);
939 master->dma_rx = NULL;
940 goto err;
941 }
942
943 spi_imx_dma_configure(master, 1);
944
945 init_completion(&spi_imx->dma_rx_completion);
946 init_completion(&spi_imx->dma_tx_completion);
947 master->can_dma = spi_imx_can_dma;
948 master->max_dma_len = MAX_SDMA_BD_BYTES;
949 spi_imx->bitbang.master->flags = SPI_MASTER_MUST_RX |
950 SPI_MASTER_MUST_TX;
951
952 return 0;
953err:
954 spi_imx_sdma_exit(spi_imx);
955 return ret;
956}
957
958static void spi_imx_dma_rx_callback(void *cookie)
959{
960 struct spi_imx_data *spi_imx = (struct spi_imx_data *)cookie;
961
962 complete(&spi_imx->dma_rx_completion);
963}
964
965static void spi_imx_dma_tx_callback(void *cookie)
966{
967 struct spi_imx_data *spi_imx = (struct spi_imx_data *)cookie;
968
969 complete(&spi_imx->dma_tx_completion);
970}
971
972static int spi_imx_calculate_timeout(struct spi_imx_data *spi_imx, int size)
973{
974 unsigned long timeout = 0;
975
976 /* Time with actual data transfer and CS change delay related to HW */
977 timeout = (8 + 4) * size / spi_imx->spi_bus_clk;
978
979 /* Add extra second for scheduler related activities */
980 timeout += 1;
981
982 /* Double calculated timeout */
983 return msecs_to_jiffies(2 * timeout * MSEC_PER_SEC);
984}
985
986static int spi_imx_dma_transfer(struct spi_imx_data *spi_imx,
987 struct spi_transfer *transfer)
988{
989 struct dma_async_tx_descriptor *desc_tx, *desc_rx;
990 unsigned long transfer_timeout;
991 unsigned long timeout;
992 struct spi_master *master = spi_imx->bitbang.master;
993 struct sg_table *tx = &transfer->tx_sg, *rx = &transfer->rx_sg;
994
995 /*
996 * The TX DMA setup starts the transfer, so make sure RX is configured
997 * before TX.
998 */
999 desc_rx = dmaengine_prep_slave_sg(master->dma_rx,
1000 rx->sgl, rx->nents, DMA_DEV_TO_MEM,
1001 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1002 if (!desc_rx)
1003 return -EINVAL;
1004
1005 desc_rx->callback = spi_imx_dma_rx_callback;
1006 desc_rx->callback_param = (void *)spi_imx;
1007 dmaengine_submit(desc_rx);
1008 reinit_completion(&spi_imx->dma_rx_completion);
1009 dma_async_issue_pending(master->dma_rx);
1010
1011 desc_tx = dmaengine_prep_slave_sg(master->dma_tx,
1012 tx->sgl, tx->nents, DMA_MEM_TO_DEV,
1013 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1014 if (!desc_tx) {
1015 dmaengine_terminate_all(master->dma_tx);
1016 return -EINVAL;
1017 }
1018
1019 desc_tx->callback = spi_imx_dma_tx_callback;
1020 desc_tx->callback_param = (void *)spi_imx;
1021 dmaengine_submit(desc_tx);
1022 reinit_completion(&spi_imx->dma_tx_completion);
1023 dma_async_issue_pending(master->dma_tx);
1024
1025 transfer_timeout = spi_imx_calculate_timeout(spi_imx, transfer->len);
1026
1027 /* Wait SDMA to finish the data transfer.*/
1028 timeout = wait_for_completion_timeout(&spi_imx->dma_tx_completion,
1029 transfer_timeout);
1030 if (!timeout) {
1031 dev_err(spi_imx->dev, "I/O Error in DMA TX\n");
1032 dmaengine_terminate_all(master->dma_tx);
1033 dmaengine_terminate_all(master->dma_rx);
1034 return -ETIMEDOUT;
1035 }
1036
1037 timeout = wait_for_completion_timeout(&spi_imx->dma_rx_completion,
1038 transfer_timeout);
1039 if (!timeout) {
1040 dev_err(&master->dev, "I/O Error in DMA RX\n");
1041 spi_imx->devtype_data->reset(spi_imx);
1042 dmaengine_terminate_all(master->dma_rx);
1043 return -ETIMEDOUT;
1044 }
1045
1046 return transfer->len;
1047}
1048
1049static int spi_imx_pio_transfer(struct spi_device *spi,
1050 struct spi_transfer *transfer)
1051{
1052 struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
1053
1054 spi_imx->tx_buf = transfer->tx_buf;
1055 spi_imx->rx_buf = transfer->rx_buf;
1056 spi_imx->count = transfer->len;
1057 spi_imx->txfifo = 0;
1058
1059 reinit_completion(&spi_imx->xfer_done);
1060
1061 spi_imx_push(spi_imx);
1062
1063 spi_imx->devtype_data->intctrl(spi_imx, MXC_INT_TE);
1064
1065 wait_for_completion(&spi_imx->xfer_done);
1066
1067 return transfer->len;
1068}
1069
1070static int spi_imx_transfer(struct spi_device *spi,
1071 struct spi_transfer *transfer)
1072{
1073 struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
1074
1075 if (spi_imx->usedma)
1076 return spi_imx_dma_transfer(spi_imx, transfer);
1077 else
1078 return spi_imx_pio_transfer(spi, transfer);
1079}
1080
1081static int spi_imx_setup(struct spi_device *spi)
1082{
1083 struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
1084 int gpio = spi_imx->chipselect[spi->chip_select];
1085
1086 dev_dbg(&spi->dev, "%s: mode %d, %u bpw, %d hz\n", __func__,
1087 spi->mode, spi->bits_per_word, spi->max_speed_hz);
1088
1089 if (gpio_is_valid(gpio))
1090 gpio_direction_output(gpio, spi->mode & SPI_CS_HIGH ? 0 : 1);
1091
1092 spi_imx_chipselect(spi, BITBANG_CS_INACTIVE);
1093
1094 return 0;
1095}
1096
1097static void spi_imx_cleanup(struct spi_device *spi)
1098{
1099}
1100
1101static int
1102spi_imx_prepare_message(struct spi_master *master, struct spi_message *msg)
1103{
1104 struct spi_imx_data *spi_imx = spi_master_get_devdata(master);
1105 int ret;
1106
1107 ret = clk_enable(spi_imx->clk_per);
1108 if (ret)
1109 return ret;
1110
1111 ret = clk_enable(spi_imx->clk_ipg);
1112 if (ret) {
1113 clk_disable(spi_imx->clk_per);
1114 return ret;
1115 }
1116
1117 return 0;
1118}
1119
1120static int
1121spi_imx_unprepare_message(struct spi_master *master, struct spi_message *msg)
1122{
1123 struct spi_imx_data *spi_imx = spi_master_get_devdata(master);
1124
1125 clk_disable(spi_imx->clk_ipg);
1126 clk_disable(spi_imx->clk_per);
1127 return 0;
1128}
1129
1130static int spi_imx_probe(struct platform_device *pdev)
1131{
1132 struct device_node *np = pdev->dev.of_node;
1133 const struct of_device_id *of_id =
1134 of_match_device(spi_imx_dt_ids, &pdev->dev);
1135 struct spi_imx_master *mxc_platform_info =
1136 dev_get_platdata(&pdev->dev);
1137 struct spi_master *master;
1138 struct spi_imx_data *spi_imx;
1139 struct resource *res;
1140 int i, ret, num_cs, irq;
1141
1142 if (!np && !mxc_platform_info) {
1143 dev_err(&pdev->dev, "can't get the platform data\n");
1144 return -EINVAL;
1145 }
1146
1147 ret = of_property_read_u32(np, "fsl,spi-num-chipselects", &num_cs);
1148 if (ret < 0) {
1149 if (mxc_platform_info)
1150 num_cs = mxc_platform_info->num_chipselect;
1151 else
1152 return ret;
1153 }
1154
1155 master = spi_alloc_master(&pdev->dev,
1156 sizeof(struct spi_imx_data) + sizeof(int) * num_cs);
1157 if (!master)
1158 return -ENOMEM;
1159
1160 platform_set_drvdata(pdev, master);
1161
1162 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(1, 32);
1163 master->bus_num = pdev->id;
1164 master->num_chipselect = num_cs;
1165
1166 spi_imx = spi_master_get_devdata(master);
1167 spi_imx->bitbang.master = master;
1168 spi_imx->dev = &pdev->dev;
1169
1170 spi_imx->devtype_data = of_id ? of_id->data :
1171 (struct spi_imx_devtype_data *)pdev->id_entry->driver_data;
1172
1173 for (i = 0; i < master->num_chipselect; i++) {
1174 int cs_gpio = of_get_named_gpio(np, "cs-gpios", i);
1175 if (!gpio_is_valid(cs_gpio) && mxc_platform_info)
1176 cs_gpio = mxc_platform_info->chipselect[i];
1177
1178 spi_imx->chipselect[i] = cs_gpio;
1179 if (!gpio_is_valid(cs_gpio))
1180 continue;
1181
1182 ret = devm_gpio_request(&pdev->dev, spi_imx->chipselect[i],
1183 DRIVER_NAME);
1184 if (ret) {
1185 dev_err(&pdev->dev, "can't get cs gpios\n");
1186 goto out_master_put;
1187 }
1188 }
1189
1190 spi_imx->bitbang.chipselect = spi_imx_chipselect;
1191 spi_imx->bitbang.setup_transfer = spi_imx_setupxfer;
1192 spi_imx->bitbang.txrx_bufs = spi_imx_transfer;
1193 spi_imx->bitbang.master->setup = spi_imx_setup;
1194 spi_imx->bitbang.master->cleanup = spi_imx_cleanup;
1195 spi_imx->bitbang.master->prepare_message = spi_imx_prepare_message;
1196 spi_imx->bitbang.master->unprepare_message = spi_imx_unprepare_message;
1197 spi_imx->bitbang.master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
1198 if (is_imx51_ecspi(spi_imx))
1199 spi_imx->bitbang.master->mode_bits |= SPI_LOOP;
1200
1201 init_completion(&spi_imx->xfer_done);
1202
1203 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1204 spi_imx->base = devm_ioremap_resource(&pdev->dev, res);
1205 if (IS_ERR(spi_imx->base)) {
1206 ret = PTR_ERR(spi_imx->base);
1207 goto out_master_put;
1208 }
1209 spi_imx->base_phys = res->start;
1210
1211 irq = platform_get_irq(pdev, 0);
1212 if (irq < 0) {
1213 ret = irq;
1214 goto out_master_put;
1215 }
1216
1217 ret = devm_request_irq(&pdev->dev, irq, spi_imx_isr, 0,
1218 dev_name(&pdev->dev), spi_imx);
1219 if (ret) {
1220 dev_err(&pdev->dev, "can't get irq%d: %d\n", irq, ret);
1221 goto out_master_put;
1222 }
1223
1224 spi_imx->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
1225 if (IS_ERR(spi_imx->clk_ipg)) {
1226 ret = PTR_ERR(spi_imx->clk_ipg);
1227 goto out_master_put;
1228 }
1229
1230 spi_imx->clk_per = devm_clk_get(&pdev->dev, "per");
1231 if (IS_ERR(spi_imx->clk_per)) {
1232 ret = PTR_ERR(spi_imx->clk_per);
1233 goto out_master_put;
1234 }
1235
1236 ret = clk_prepare_enable(spi_imx->clk_per);
1237 if (ret)
1238 goto out_master_put;
1239
1240 ret = clk_prepare_enable(spi_imx->clk_ipg);
1241 if (ret)
1242 goto out_put_per;
1243
1244 spi_imx->spi_clk = clk_get_rate(spi_imx->clk_per);
1245 /*
1246 * Only validated on i.mx6 now, can remove the constrain if validated on
1247 * other chips.
1248 */
1249 if (is_imx51_ecspi(spi_imx)) {
1250 ret = spi_imx_sdma_init(&pdev->dev, spi_imx, master);
1251 if (ret == -EPROBE_DEFER)
1252 goto out_clk_put;
1253
1254 if (ret < 0)
1255 dev_err(&pdev->dev, "dma setup error %d, use pio\n",
1256 ret);
1257 }
1258
1259 spi_imx->devtype_data->reset(spi_imx);
1260
1261 spi_imx->devtype_data->intctrl(spi_imx, 0);
1262
1263 master->dev.of_node = pdev->dev.of_node;
1264 ret = spi_bitbang_start(&spi_imx->bitbang);
1265 if (ret) {
1266 dev_err(&pdev->dev, "bitbang start failed with %d\n", ret);
1267 goto out_clk_put;
1268 }
1269
1270 dev_info(&pdev->dev, "probed\n");
1271
1272 clk_disable(spi_imx->clk_ipg);
1273 clk_disable(spi_imx->clk_per);
1274 return ret;
1275
1276out_clk_put:
1277 clk_disable_unprepare(spi_imx->clk_ipg);
1278out_put_per:
1279 clk_disable_unprepare(spi_imx->clk_per);
1280out_master_put:
1281 spi_master_put(master);
1282
1283 return ret;
1284}
1285
1286static int spi_imx_remove(struct platform_device *pdev)
1287{
1288 struct spi_master *master = platform_get_drvdata(pdev);
1289 struct spi_imx_data *spi_imx = spi_master_get_devdata(master);
1290
1291 spi_bitbang_stop(&spi_imx->bitbang);
1292
1293 writel(0, spi_imx->base + MXC_CSPICTRL);
1294 clk_unprepare(spi_imx->clk_ipg);
1295 clk_unprepare(spi_imx->clk_per);
1296 spi_imx_sdma_exit(spi_imx);
1297 spi_master_put(master);
1298
1299 return 0;
1300}
1301
1302static struct platform_driver spi_imx_driver = {
1303 .driver = {
1304 .name = DRIVER_NAME,
1305 .of_match_table = spi_imx_dt_ids,
1306 },
1307 .id_table = spi_imx_devtype,
1308 .probe = spi_imx_probe,
1309 .remove = spi_imx_remove,
1310};
1311module_platform_driver(spi_imx_driver);
1312
1313MODULE_DESCRIPTION("SPI Master Controller driver");
1314MODULE_AUTHOR("Sascha Hauer, Pengutronix");
1315MODULE_LICENSE("GPL");
1316MODULE_ALIAS("platform:" DRIVER_NAME);