1// SPDX-License-Identifier: GPL-2.0-or-later
   2/*
   3 *  libahci.c - Common AHCI SATA low-level routines
   4 *
   5 *  Maintained by:  Tejun Heo <tj@kernel.org>
   6 *    		    Please ALWAYS copy linux-ide@vger.kernel.org
   7 *		    on emails.
   8 *
   9 *  Copyright 2004-2005 Red Hat, Inc.
  10 *
  11 * libata documentation is available via 'make {ps|pdf}docs',
  12 * as Documentation/driver-api/libata.rst
  13 *
  14 * AHCI hardware documentation:
  15 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
  16 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
  17 */
  18
  19#include <linux/kernel.h>
  20#include <linux/gfp.h>
  21#include <linux/module.h>
  22#include <linux/nospec.h>
  23#include <linux/blkdev.h>
  24#include <linux/delay.h>
  25#include <linux/interrupt.h>
  26#include <linux/dma-mapping.h>
  27#include <linux/device.h>
  28#include <scsi/scsi_host.h>
  29#include <scsi/scsi_cmnd.h>
  30#include <linux/libata.h>
  31#include <linux/pci.h>
  32#include "ahci.h"
  33#include "libata.h"
  34
  35static int ahci_skip_host_reset;
  36int ahci_ignore_sss;
  37EXPORT_SYMBOL_GPL(ahci_ignore_sss);
  38
  39module_param_named(skip_host_reset, ahci_skip_host_reset, int, 0444);
  40MODULE_PARM_DESC(skip_host_reset, "skip global host reset (0=don't skip, 1=skip)");
  41
  42module_param_named(ignore_sss, ahci_ignore_sss, int, 0444);
  43MODULE_PARM_DESC(ignore_sss, "Ignore staggered spinup flag (0=don't ignore, 1=ignore)");
  44
  45static int ahci_set_lpm(struct ata_link *link, enum ata_lpm_policy policy,
  46			unsigned hints);
  47static ssize_t ahci_led_show(struct ata_port *ap, char *buf);
  48static ssize_t ahci_led_store(struct ata_port *ap, const char *buf,
  49			      size_t size);
  50static ssize_t ahci_transmit_led_message(struct ata_port *ap, u32 state,
  51					ssize_t size);
  52
  53
  54
  55static int ahci_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val);
  56static int ahci_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val);
  57static bool ahci_qc_fill_rtf(struct ata_queued_cmd *qc);
  58static int ahci_port_start(struct ata_port *ap);
  59static void ahci_port_stop(struct ata_port *ap);
  60static enum ata_completion_errors ahci_qc_prep(struct ata_queued_cmd *qc);
  61static int ahci_pmp_qc_defer(struct ata_queued_cmd *qc);
  62static void ahci_freeze(struct ata_port *ap);
  63static void ahci_thaw(struct ata_port *ap);
  64static void ahci_set_aggressive_devslp(struct ata_port *ap, bool sleep);
  65static void ahci_enable_fbs(struct ata_port *ap);
  66static void ahci_disable_fbs(struct ata_port *ap);
  67static void ahci_pmp_attach(struct ata_port *ap);
  68static void ahci_pmp_detach(struct ata_port *ap);
  69static int ahci_softreset(struct ata_link *link, unsigned int *class,
  70			  unsigned long deadline);
  71static int ahci_pmp_retry_softreset(struct ata_link *link, unsigned int *class,
  72			  unsigned long deadline);
  73static int ahci_hardreset(struct ata_link *link, unsigned int *class,
  74			  unsigned long deadline);
  75static void ahci_postreset(struct ata_link *link, unsigned int *class);
  76static void ahci_post_internal_cmd(struct ata_queued_cmd *qc);
  77static void ahci_dev_config(struct ata_device *dev);
  78#ifdef CONFIG_PM
  79static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg);
  80#endif
  81static ssize_t ahci_activity_show(struct ata_device *dev, char *buf);
  82static ssize_t ahci_activity_store(struct ata_device *dev,
  83				   enum sw_activity val);
  84static void ahci_init_sw_activity(struct ata_link *link);
  85
  86static ssize_t ahci_show_host_caps(struct device *dev,
  87				   struct device_attribute *attr, char *buf);
  88static ssize_t ahci_show_host_cap2(struct device *dev,
  89				   struct device_attribute *attr, char *buf);
  90static ssize_t ahci_show_host_version(struct device *dev,
  91				      struct device_attribute *attr, char *buf);
  92static ssize_t ahci_show_port_cmd(struct device *dev,
  93				  struct device_attribute *attr, char *buf);
  94static ssize_t ahci_read_em_buffer(struct device *dev,
  95				   struct device_attribute *attr, char *buf);
  96static ssize_t ahci_store_em_buffer(struct device *dev,
  97				    struct device_attribute *attr,
  98				    const char *buf, size_t size);
  99static ssize_t ahci_show_em_supported(struct device *dev,
 100				      struct device_attribute *attr, char *buf);
 101static irqreturn_t ahci_single_level_irq_intr(int irq, void *dev_instance);
 102
 103static DEVICE_ATTR(ahci_host_caps, S_IRUGO, ahci_show_host_caps, NULL);
 104static DEVICE_ATTR(ahci_host_cap2, S_IRUGO, ahci_show_host_cap2, NULL);
 105static DEVICE_ATTR(ahci_host_version, S_IRUGO, ahci_show_host_version, NULL);
 106static DEVICE_ATTR(ahci_port_cmd, S_IRUGO, ahci_show_port_cmd, NULL);
 107static DEVICE_ATTR(em_buffer, S_IWUSR | S_IRUGO,
 108		   ahci_read_em_buffer, ahci_store_em_buffer);
 109static DEVICE_ATTR(em_message_supported, S_IRUGO, ahci_show_em_supported, NULL);
 110
 111struct device_attribute *ahci_shost_attrs[] = {
 112	&dev_attr_link_power_management_policy,
 113	&dev_attr_em_message_type,
 114	&dev_attr_em_message,
 115	&dev_attr_ahci_host_caps,
 116	&dev_attr_ahci_host_cap2,
 117	&dev_attr_ahci_host_version,
 118	&dev_attr_ahci_port_cmd,
 119	&dev_attr_em_buffer,
 120	&dev_attr_em_message_supported,
 121	NULL
 122};
 123EXPORT_SYMBOL_GPL(ahci_shost_attrs);
 124
 125struct device_attribute *ahci_sdev_attrs[] = {
 126	&dev_attr_sw_activity,
 127	&dev_attr_unload_heads,
 128	&dev_attr_ncq_prio_enable,
 129	NULL
 130};
 131EXPORT_SYMBOL_GPL(ahci_sdev_attrs);
 132
 133struct ata_port_operations ahci_ops = {
 134	.inherits		= &sata_pmp_port_ops,
 135
 136	.qc_defer		= ahci_pmp_qc_defer,
 137	.qc_prep		= ahci_qc_prep,
 138	.qc_issue		= ahci_qc_issue,
 139	.qc_fill_rtf		= ahci_qc_fill_rtf,
 140
 141	.freeze			= ahci_freeze,
 142	.thaw			= ahci_thaw,
 143	.softreset		= ahci_softreset,
 144	.hardreset		= ahci_hardreset,
 145	.postreset		= ahci_postreset,
 146	.pmp_softreset		= ahci_softreset,
 147	.error_handler		= ahci_error_handler,
 148	.post_internal_cmd	= ahci_post_internal_cmd,
 149	.dev_config		= ahci_dev_config,
 150
 151	.scr_read		= ahci_scr_read,
 152	.scr_write		= ahci_scr_write,
 153	.pmp_attach		= ahci_pmp_attach,
 154	.pmp_detach		= ahci_pmp_detach,
 155
 156	.set_lpm		= ahci_set_lpm,
 157	.em_show		= ahci_led_show,
 158	.em_store		= ahci_led_store,
 159	.sw_activity_show	= ahci_activity_show,
 160	.sw_activity_store	= ahci_activity_store,
 161	.transmit_led_message	= ahci_transmit_led_message,
 162#ifdef CONFIG_PM
 163	.port_suspend		= ahci_port_suspend,
 164	.port_resume		= ahci_port_resume,
 165#endif
 166	.port_start		= ahci_port_start,
 167	.port_stop		= ahci_port_stop,
 168};
 169EXPORT_SYMBOL_GPL(ahci_ops);
 170
 171struct ata_port_operations ahci_pmp_retry_srst_ops = {
 172	.inherits		= &ahci_ops,
 173	.softreset		= ahci_pmp_retry_softreset,
 174};
 175EXPORT_SYMBOL_GPL(ahci_pmp_retry_srst_ops);
 176
 177static bool ahci_em_messages __read_mostly = true;
 178module_param(ahci_em_messages, bool, 0444);
 179/* add other LED protocol types when they become supported */
 180MODULE_PARM_DESC(ahci_em_messages,
 181	"AHCI Enclosure Management Message control (0 = off, 1 = on)");
 182
 183/* device sleep idle timeout in ms */
 184static int devslp_idle_timeout __read_mostly = 1000;
 185module_param(devslp_idle_timeout, int, 0644);
 186MODULE_PARM_DESC(devslp_idle_timeout, "device sleep idle timeout");
 187
 188static void ahci_enable_ahci(void __iomem *mmio)
 189{
 190	int i;
 191	u32 tmp;
 192
 193	/* turn on AHCI_EN */
 194	tmp = readl(mmio + HOST_CTL);
 195	if (tmp & HOST_AHCI_EN)
 196		return;
 197
 198	/* Some controllers need AHCI_EN to be written multiple times.
 199	 * Try a few times before giving up.
 200	 */
 201	for (i = 0; i < 5; i++) {
 202		tmp |= HOST_AHCI_EN;
 203		writel(tmp, mmio + HOST_CTL);
 204		tmp = readl(mmio + HOST_CTL);	/* flush && sanity check */
 205		if (tmp & HOST_AHCI_EN)
 206			return;
 207		msleep(10);
 208	}
 209
 210	WARN_ON(1);
 211}
 212
 213/**
 214 *	ahci_rpm_get_port - Make sure the port is powered on
 215 *	@ap: Port to power on
 216 *
 217 *	Whenever there is need to access the AHCI host registers outside of
 218 *	normal execution paths, call this function to make sure the host is
 219 *	actually powered on.
 220 */
 221static int ahci_rpm_get_port(struct ata_port *ap)
 222{
 223	return pm_runtime_get_sync(ap->dev);
 224}
 225
 226/**
 227 *	ahci_rpm_put_port - Undoes ahci_rpm_get_port()
 228 *	@ap: Port to power down
 229 *
 230 *	Undoes ahci_rpm_get_port() and possibly powers down the AHCI host
 231 *	if it has no more active users.
 232 */
 233static void ahci_rpm_put_port(struct ata_port *ap)
 234{
 235	pm_runtime_put(ap->dev);
 236}
 237
 238static ssize_t ahci_show_host_caps(struct device *dev,
 239				   struct device_attribute *attr, char *buf)
 240{
 241	struct Scsi_Host *shost = class_to_shost(dev);
 242	struct ata_port *ap = ata_shost_to_port(shost);
 243	struct ahci_host_priv *hpriv = ap->host->private_data;
 244
 245	return sprintf(buf, "%x\n", hpriv->cap);
 246}
 247
 248static ssize_t ahci_show_host_cap2(struct device *dev,
 249				   struct device_attribute *attr, char *buf)
 250{
 251	struct Scsi_Host *shost = class_to_shost(dev);
 252	struct ata_port *ap = ata_shost_to_port(shost);
 253	struct ahci_host_priv *hpriv = ap->host->private_data;
 254
 255	return sprintf(buf, "%x\n", hpriv->cap2);
 256}
 257
 258static ssize_t ahci_show_host_version(struct device *dev,
 259				   struct device_attribute *attr, char *buf)
 260{
 261	struct Scsi_Host *shost = class_to_shost(dev);
 262	struct ata_port *ap = ata_shost_to_port(shost);
 263	struct ahci_host_priv *hpriv = ap->host->private_data;
 264
 265	return sprintf(buf, "%x\n", hpriv->version);
 266}
 267
 268static ssize_t ahci_show_port_cmd(struct device *dev,
 269				  struct device_attribute *attr, char *buf)
 270{
 271	struct Scsi_Host *shost = class_to_shost(dev);
 272	struct ata_port *ap = ata_shost_to_port(shost);
 273	void __iomem *port_mmio = ahci_port_base(ap);
 274	ssize_t ret;
 275
 276	ahci_rpm_get_port(ap);
 277	ret = sprintf(buf, "%x\n", readl(port_mmio + PORT_CMD));
 278	ahci_rpm_put_port(ap);
 279
 280	return ret;
 281}
 282
 283static ssize_t ahci_read_em_buffer(struct device *dev,
 284				   struct device_attribute *attr, char *buf)
 285{
 286	struct Scsi_Host *shost = class_to_shost(dev);
 287	struct ata_port *ap = ata_shost_to_port(shost);
 288	struct ahci_host_priv *hpriv = ap->host->private_data;
 289	void __iomem *mmio = hpriv->mmio;
 290	void __iomem *em_mmio = mmio + hpriv->em_loc;
 291	u32 em_ctl, msg;
 292	unsigned long flags;
 293	size_t count;
 294	int i;
 295
 296	ahci_rpm_get_port(ap);
 297	spin_lock_irqsave(ap->lock, flags);
 298
 299	em_ctl = readl(mmio + HOST_EM_CTL);
 300	if (!(ap->flags & ATA_FLAG_EM) || em_ctl & EM_CTL_XMT ||
 301	    !(hpriv->em_msg_type & EM_MSG_TYPE_SGPIO)) {
 302		spin_unlock_irqrestore(ap->lock, flags);
 303		ahci_rpm_put_port(ap);
 304		return -EINVAL;
 305	}
 306
 307	if (!(em_ctl & EM_CTL_MR)) {
 308		spin_unlock_irqrestore(ap->lock, flags);
 309		ahci_rpm_put_port(ap);
 310		return -EAGAIN;
 311	}
 312
 313	if (!(em_ctl & EM_CTL_SMB))
 314		em_mmio += hpriv->em_buf_sz;
 315
 316	count = hpriv->em_buf_sz;
 317
 318	/* the count should not be larger than PAGE_SIZE */
 319	if (count > PAGE_SIZE) {
 320		if (printk_ratelimit())
 321			ata_port_warn(ap,
 322				      "EM read buffer size too large: "
 323				      "buffer size %u, page size %lu\n",
 324				      hpriv->em_buf_sz, PAGE_SIZE);
 325		count = PAGE_SIZE;
 326	}
 327
 328	for (i = 0; i < count; i += 4) {
 329		msg = readl(em_mmio + i);
 330		buf[i] = msg & 0xff;
 331		buf[i + 1] = (msg >> 8) & 0xff;
 332		buf[i + 2] = (msg >> 16) & 0xff;
 333		buf[i + 3] = (msg >> 24) & 0xff;
 334	}
 335
 336	spin_unlock_irqrestore(ap->lock, flags);
 337	ahci_rpm_put_port(ap);
 338
 339	return i;
 340}
 341
 342static ssize_t ahci_store_em_buffer(struct device *dev,
 343				    struct device_attribute *attr,
 344				    const char *buf, size_t size)
 345{
 346	struct Scsi_Host *shost = class_to_shost(dev);
 347	struct ata_port *ap = ata_shost_to_port(shost);
 348	struct ahci_host_priv *hpriv = ap->host->private_data;
 349	void __iomem *mmio = hpriv->mmio;
 350	void __iomem *em_mmio = mmio + hpriv->em_loc;
 351	const unsigned char *msg_buf = buf;
 352	u32 em_ctl, msg;
 353	unsigned long flags;
 354	int i;
 355
 356	/* check size validity */
 357	if (!(ap->flags & ATA_FLAG_EM) ||
 358	    !(hpriv->em_msg_type & EM_MSG_TYPE_SGPIO) ||
 359	    size % 4 || size > hpriv->em_buf_sz)
 360		return -EINVAL;
 361
 362	ahci_rpm_get_port(ap);
 363	spin_lock_irqsave(ap->lock, flags);
 364
 365	em_ctl = readl(mmio + HOST_EM_CTL);
 366	if (em_ctl & EM_CTL_TM) {
 367		spin_unlock_irqrestore(ap->lock, flags);
 368		ahci_rpm_put_port(ap);
 369		return -EBUSY;
 370	}
 371
 372	for (i = 0; i < size; i += 4) {
 373		msg = msg_buf[i] | msg_buf[i + 1] << 8 |
 374		      msg_buf[i + 2] << 16 | msg_buf[i + 3] << 24;
 375		writel(msg, em_mmio + i);
 376	}
 377
 378	writel(em_ctl | EM_CTL_TM, mmio + HOST_EM_CTL);
 379
 380	spin_unlock_irqrestore(ap->lock, flags);
 381	ahci_rpm_put_port(ap);
 382
 383	return size;
 384}
 385
 386static ssize_t ahci_show_em_supported(struct device *dev,
 387				      struct device_attribute *attr, char *buf)
 388{
 389	struct Scsi_Host *shost = class_to_shost(dev);
 390	struct ata_port *ap = ata_shost_to_port(shost);
 391	struct ahci_host_priv *hpriv = ap->host->private_data;
 392	void __iomem *mmio = hpriv->mmio;
 393	u32 em_ctl;
 394
 395	ahci_rpm_get_port(ap);
 396	em_ctl = readl(mmio + HOST_EM_CTL);
 397	ahci_rpm_put_port(ap);
 398
 399	return sprintf(buf, "%s%s%s%s\n",
 400		       em_ctl & EM_CTL_LED ? "led " : "",
 401		       em_ctl & EM_CTL_SAFTE ? "saf-te " : "",
 402		       em_ctl & EM_CTL_SES ? "ses-2 " : "",
 403		       em_ctl & EM_CTL_SGPIO ? "sgpio " : "");
 404}
 405
 406/**
 407 *	ahci_save_initial_config - Save and fixup initial config values
 408 *	@dev: target AHCI device
 409 *	@hpriv: host private area to store config values
 410 *
 411 *	Some registers containing configuration info might be setup by
 412 *	BIOS and might be cleared on reset.  This function saves the
 413 *	initial values of those registers into @hpriv such that they
 414 *	can be restored after controller reset.
 415 *
 416 *	If inconsistent, config values are fixed up by this function.
 417 *
 418 *	If it is not set already this function sets hpriv->start_engine to
 419 *	ahci_start_engine.
 420 *
 421 *	LOCKING:
 422 *	None.
 423 */
 424void ahci_save_initial_config(struct device *dev, struct ahci_host_priv *hpriv)
 425{
 426	void __iomem *mmio = hpriv->mmio;
 427	u32 cap, cap2, vers, port_map;
 428	int i;
 429
 430	/* make sure AHCI mode is enabled before accessing CAP */
 431	ahci_enable_ahci(mmio);
 432
 433	/* Values prefixed with saved_ are written back to host after
 434	 * reset.  Values without are used for driver operation.
 435	 */
 436	hpriv->saved_cap = cap = readl(mmio + HOST_CAP);
 437	hpriv->saved_port_map = port_map = readl(mmio + HOST_PORTS_IMPL);
 438
 439	/* CAP2 register is only defined for AHCI 1.2 and later */
 440	vers = readl(mmio + HOST_VERSION);
 441	if ((vers >> 16) > 1 ||
 442	   ((vers >> 16) == 1 && (vers & 0xFFFF) >= 0x200))
 443		hpriv->saved_cap2 = cap2 = readl(mmio + HOST_CAP2);
 444	else
 445		hpriv->saved_cap2 = cap2 = 0;
 446
 447	/* some chips have errata preventing 64bit use */
 448	if ((cap & HOST_CAP_64) && (hpriv->flags & AHCI_HFLAG_32BIT_ONLY)) {
 449		dev_info(dev, "controller can't do 64bit DMA, forcing 32bit\n");
 450		cap &= ~HOST_CAP_64;
 451	}
 452
 453	if ((cap & HOST_CAP_NCQ) && (hpriv->flags & AHCI_HFLAG_NO_NCQ)) {
 454		dev_info(dev, "controller can't do NCQ, turning off CAP_NCQ\n");
 455		cap &= ~HOST_CAP_NCQ;
 456	}
 457
 458	if (!(cap & HOST_CAP_NCQ) && (hpriv->flags & AHCI_HFLAG_YES_NCQ)) {
 459		dev_info(dev, "controller can do NCQ, turning on CAP_NCQ\n");
 460		cap |= HOST_CAP_NCQ;
 461	}
 462
 463	if ((cap & HOST_CAP_PMP) && (hpriv->flags & AHCI_HFLAG_NO_PMP)) {
 464		dev_info(dev, "controller can't do PMP, turning off CAP_PMP\n");
 465		cap &= ~HOST_CAP_PMP;
 466	}
 467
 468	if ((cap & HOST_CAP_SNTF) && (hpriv->flags & AHCI_HFLAG_NO_SNTF)) {
 469		dev_info(dev,
 470			 "controller can't do SNTF, turning off CAP_SNTF\n");
 471		cap &= ~HOST_CAP_SNTF;
 472	}
 473
 474	if ((cap2 & HOST_CAP2_SDS) && (hpriv->flags & AHCI_HFLAG_NO_DEVSLP)) {
 475		dev_info(dev,
 476			 "controller can't do DEVSLP, turning off\n");
 477		cap2 &= ~HOST_CAP2_SDS;
 478		cap2 &= ~HOST_CAP2_SADM;
 479	}
 480
 481	if (!(cap & HOST_CAP_FBS) && (hpriv->flags & AHCI_HFLAG_YES_FBS)) {
 482		dev_info(dev, "controller can do FBS, turning on CAP_FBS\n");
 483		cap |= HOST_CAP_FBS;
 484	}
 485
 486	if ((cap & HOST_CAP_FBS) && (hpriv->flags & AHCI_HFLAG_NO_FBS)) {
 487		dev_info(dev, "controller can't do FBS, turning off CAP_FBS\n");
 488		cap &= ~HOST_CAP_FBS;
 489	}
 490
 491	if (!(cap & HOST_CAP_ALPM) && (hpriv->flags & AHCI_HFLAG_YES_ALPM)) {
 492		dev_info(dev, "controller can do ALPM, turning on CAP_ALPM\n");
 493		cap |= HOST_CAP_ALPM;
 494	}
 495
 496	if (hpriv->force_port_map && port_map != hpriv->force_port_map) {
 497		dev_info(dev, "forcing port_map 0x%x -> 0x%x\n",
 498			 port_map, hpriv->force_port_map);
 499		port_map = hpriv->force_port_map;
 500		hpriv->saved_port_map = port_map;
 501	}
 502
 503	if (hpriv->mask_port_map) {
 504		dev_warn(dev, "masking port_map 0x%x -> 0x%x\n",
 505			port_map,
 506			port_map & hpriv->mask_port_map);
 507		port_map &= hpriv->mask_port_map;
 508	}
 509
 510	/* cross check port_map and cap.n_ports */
 511	if (port_map) {
 512		int map_ports = 0;
 513
 514		for (i = 0; i < AHCI_MAX_PORTS; i++)
 515			if (port_map & (1 << i))
 516				map_ports++;
 517
 518		/* If PI has more ports than n_ports, whine, clear
 519		 * port_map and let it be generated from n_ports.
 520		 */
 521		if (map_ports > ahci_nr_ports(cap)) {
 522			dev_warn(dev,
 523				 "implemented port map (0x%x) contains more ports than nr_ports (%u), using nr_ports\n",
 524				 port_map, ahci_nr_ports(cap));
 525			port_map = 0;
 526		}
 527	}
 528
 529	/* fabricate port_map from cap.nr_ports for < AHCI 1.3 */
 530	if (!port_map && vers < 0x10300) {
 531		port_map = (1 << ahci_nr_ports(cap)) - 1;
 532		dev_warn(dev, "forcing PORTS_IMPL to 0x%x\n", port_map);
 533
 534		/* write the fixed up value to the PI register */
 535		hpriv->saved_port_map = port_map;
 536	}
 537
 538	/* record values to use during operation */
 539	hpriv->cap = cap;
 540	hpriv->cap2 = cap2;
 541	hpriv->version = readl(mmio + HOST_VERSION);
 542	hpriv->port_map = port_map;
 543
 544	if (!hpriv->start_engine)
 545		hpriv->start_engine = ahci_start_engine;
 546
 547	if (!hpriv->stop_engine)
 548		hpriv->stop_engine = ahci_stop_engine;
 549
 550	if (!hpriv->irq_handler)
 551		hpriv->irq_handler = ahci_single_level_irq_intr;
 552}
 553EXPORT_SYMBOL_GPL(ahci_save_initial_config);
 554
 555/**
 556 *	ahci_restore_initial_config - Restore initial config
 557 *	@host: target ATA host
 558 *
 559 *	Restore initial config stored by ahci_save_initial_config().
 560 *
 561 *	LOCKING:
 562 *	None.
 563 */
 564static void ahci_restore_initial_config(struct ata_host *host)
 565{
 566	struct ahci_host_priv *hpriv = host->private_data;
 567	void __iomem *mmio = hpriv->mmio;
 568
 569	writel(hpriv->saved_cap, mmio + HOST_CAP);
 570	if (hpriv->saved_cap2)
 571		writel(hpriv->saved_cap2, mmio + HOST_CAP2);
 572	writel(hpriv->saved_port_map, mmio + HOST_PORTS_IMPL);
 573	(void) readl(mmio + HOST_PORTS_IMPL);	/* flush */
 574}
 575
 576static unsigned ahci_scr_offset(struct ata_port *ap, unsigned int sc_reg)
 577{
 578	static const int offset[] = {
 579		[SCR_STATUS]		= PORT_SCR_STAT,
 580		[SCR_CONTROL]		= PORT_SCR_CTL,
 581		[SCR_ERROR]		= PORT_SCR_ERR,
 582		[SCR_ACTIVE]		= PORT_SCR_ACT,
 583		[SCR_NOTIFICATION]	= PORT_SCR_NTF,
 584	};
 585	struct ahci_host_priv *hpriv = ap->host->private_data;
 586
 587	if (sc_reg < ARRAY_SIZE(offset) &&
 588	    (sc_reg != SCR_NOTIFICATION || (hpriv->cap & HOST_CAP_SNTF)))
 589		return offset[sc_reg];
 590	return 0;
 591}
 592
 593static int ahci_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val)
 594{
 595	void __iomem *port_mmio = ahci_port_base(link->ap);
 596	int offset = ahci_scr_offset(link->ap, sc_reg);
 597
 598	if (offset) {
 599		*val = readl(port_mmio + offset);
 600		return 0;
 601	}
 602	return -EINVAL;
 603}
 604
 605static int ahci_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val)
 606{
 607	void __iomem *port_mmio = ahci_port_base(link->ap);
 608	int offset = ahci_scr_offset(link->ap, sc_reg);
 609
 610	if (offset) {
 611		writel(val, port_mmio + offset);
 612		return 0;
 613	}
 614	return -EINVAL;
 615}
 616
 617void ahci_start_engine(struct ata_port *ap)
 618{
 619	void __iomem *port_mmio = ahci_port_base(ap);
 620	u32 tmp;
 621
 622	/* start DMA */
 623	tmp = readl(port_mmio + PORT_CMD);
 624	tmp |= PORT_CMD_START;
 625	writel(tmp, port_mmio + PORT_CMD);
 626	readl(port_mmio + PORT_CMD); /* flush */
 627}
 628EXPORT_SYMBOL_GPL(ahci_start_engine);
 629
 630int ahci_stop_engine(struct ata_port *ap)
 631{
 632	void __iomem *port_mmio = ahci_port_base(ap);
 633	struct ahci_host_priv *hpriv = ap->host->private_data;
 634	u32 tmp;
 635
 636	/*
 637	 * On some controllers, stopping a port's DMA engine while the port
 638	 * is in ALPM state (partial or slumber) results in failures on
 639	 * subsequent DMA engine starts.  For those controllers, put the
 640	 * port back in active state before stopping its DMA engine.
 641	 */
 642	if ((hpriv->flags & AHCI_HFLAG_WAKE_BEFORE_STOP) &&
 643	    (ap->link.lpm_policy > ATA_LPM_MAX_POWER) &&
 644	    ahci_set_lpm(&ap->link, ATA_LPM_MAX_POWER, ATA_LPM_WAKE_ONLY)) {
 645		dev_err(ap->host->dev, "Failed to wake up port before engine stop\n");
 646		return -EIO;
 647	}
 648
 649	tmp = readl(port_mmio + PORT_CMD);
 650
 651	/* check if the HBA is idle */
 652	if ((tmp & (PORT_CMD_START | PORT_CMD_LIST_ON)) == 0)
 653		return 0;
 654
 655	/*
 656	 * Don't try to issue commands but return with ENODEV if the
 657	 * AHCI controller not available anymore (e.g. due to PCIe hot
 658	 * unplugging). Otherwise a 500ms delay for each port is added.
 659	 */
 660	if (tmp == 0xffffffff) {
 661		dev_err(ap->host->dev, "AHCI controller unavailable!\n");
 662		return -ENODEV;
 663	}
 664
 665	/* setting HBA to idle */
 666	tmp &= ~PORT_CMD_START;
 667	writel(tmp, port_mmio + PORT_CMD);
 668
 669	/* wait for engine to stop. This could be as long as 500 msec */
 670	tmp = ata_wait_register(ap, port_mmio + PORT_CMD,
 671				PORT_CMD_LIST_ON, PORT_CMD_LIST_ON, 1, 500);
 672	if (tmp & PORT_CMD_LIST_ON)
 673		return -EIO;
 674
 675	return 0;
 676}
 677EXPORT_SYMBOL_GPL(ahci_stop_engine);
 678
 679void ahci_start_fis_rx(struct ata_port *ap)
 680{
 681	void __iomem *port_mmio = ahci_port_base(ap);
 682	struct ahci_host_priv *hpriv = ap->host->private_data;
 683	struct ahci_port_priv *pp = ap->private_data;
 684	u32 tmp;
 685
 686	/* set FIS registers */
 687	if (hpriv->cap & HOST_CAP_64)
 688		writel((pp->cmd_slot_dma >> 16) >> 16,
 689		       port_mmio + PORT_LST_ADDR_HI);
 690	writel(pp->cmd_slot_dma & 0xffffffff, port_mmio + PORT_LST_ADDR);
 691
 692	if (hpriv->cap & HOST_CAP_64)
 693		writel((pp->rx_fis_dma >> 16) >> 16,
 694		       port_mmio + PORT_FIS_ADDR_HI);
 695	writel(pp->rx_fis_dma & 0xffffffff, port_mmio + PORT_FIS_ADDR);
 696
 697	/* enable FIS reception */
 698	tmp = readl(port_mmio + PORT_CMD);
 699	tmp |= PORT_CMD_FIS_RX;
 700	writel(tmp, port_mmio + PORT_CMD);
 701
 702	/* flush */
 703	readl(port_mmio + PORT_CMD);
 704}
 705EXPORT_SYMBOL_GPL(ahci_start_fis_rx);
 706
 707static int ahci_stop_fis_rx(struct ata_port *ap)
 708{
 709	void __iomem *port_mmio = ahci_port_base(ap);
 710	u32 tmp;
 711
 712	/* disable FIS reception */
 713	tmp = readl(port_mmio + PORT_CMD);
 714	tmp &= ~PORT_CMD_FIS_RX;
 715	writel(tmp, port_mmio + PORT_CMD);
 716
 717	/* wait for completion, spec says 500ms, give it 1000 */
 718	tmp = ata_wait_register(ap, port_mmio + PORT_CMD, PORT_CMD_FIS_ON,
 719				PORT_CMD_FIS_ON, 10, 1000);
 720	if (tmp & PORT_CMD_FIS_ON)
 721		return -EBUSY;
 722
 723	return 0;
 724}
 725
 726static void ahci_power_up(struct ata_port *ap)
 727{
 728	struct ahci_host_priv *hpriv = ap->host->private_data;
 729	void __iomem *port_mmio = ahci_port_base(ap);
 730	u32 cmd;
 731
 732	cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
 733
 734	/* spin up device */
 735	if (hpriv->cap & HOST_CAP_SSS) {
 736		cmd |= PORT_CMD_SPIN_UP;
 737		writel(cmd, port_mmio + PORT_CMD);
 738	}
 739
 740	/* wake up link */
 741	writel(cmd | PORT_CMD_ICC_ACTIVE, port_mmio + PORT_CMD);
 742}
 743
 744static int ahci_set_lpm(struct ata_link *link, enum ata_lpm_policy policy,
 745			unsigned int hints)
 746{
 747	struct ata_port *ap = link->ap;
 748	struct ahci_host_priv *hpriv = ap->host->private_data;
 749	struct ahci_port_priv *pp = ap->private_data;
 750	void __iomem *port_mmio = ahci_port_base(ap);
 751
 752	if (policy != ATA_LPM_MAX_POWER) {
 753		/* wakeup flag only applies to the max power policy */
 754		hints &= ~ATA_LPM_WAKE_ONLY;
 755
 756		/*
 757		 * Disable interrupts on Phy Ready. This keeps us from
 758		 * getting woken up due to spurious phy ready
 759		 * interrupts.
 760		 */
 761		pp->intr_mask &= ~PORT_IRQ_PHYRDY;
 762		writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
 763
 764		sata_link_scr_lpm(link, policy, false);
 765	}
 766
 767	if (hpriv->cap & HOST_CAP_ALPM) {
 768		u32 cmd = readl(port_mmio + PORT_CMD);
 769
 770		if (policy == ATA_LPM_MAX_POWER || !(hints & ATA_LPM_HIPM)) {
 771			if (!(hints & ATA_LPM_WAKE_ONLY))
 772				cmd &= ~(PORT_CMD_ASP | PORT_CMD_ALPE);
 773			cmd |= PORT_CMD_ICC_ACTIVE;
 774
 775			writel(cmd, port_mmio + PORT_CMD);
 776			readl(port_mmio + PORT_CMD);
 777
 778			/* wait 10ms to be sure we've come out of LPM state */
 779			ata_msleep(ap, 10);
 780
 781			if (hints & ATA_LPM_WAKE_ONLY)
 782				return 0;
 783		} else {
 784			cmd |= PORT_CMD_ALPE;
 785			if (policy == ATA_LPM_MIN_POWER)
 786				cmd |= PORT_CMD_ASP;
 787			else if (policy == ATA_LPM_MIN_POWER_WITH_PARTIAL)
 788				cmd &= ~PORT_CMD_ASP;
 789
 790			/* write out new cmd value */
 791			writel(cmd, port_mmio + PORT_CMD);
 792		}
 793	}
 794
 795	/* set aggressive device sleep */
 796	if ((hpriv->cap2 & HOST_CAP2_SDS) &&
 797	    (hpriv->cap2 & HOST_CAP2_SADM) &&
 798	    (link->device->flags & ATA_DFLAG_DEVSLP)) {
 799		if (policy == ATA_LPM_MIN_POWER ||
 800		    policy == ATA_LPM_MIN_POWER_WITH_PARTIAL)
 801			ahci_set_aggressive_devslp(ap, true);
 802		else
 803			ahci_set_aggressive_devslp(ap, false);
 804	}
 805
 806	if (policy == ATA_LPM_MAX_POWER) {
 807		sata_link_scr_lpm(link, policy, false);
 808
 809		/* turn PHYRDY IRQ back on */
 810		pp->intr_mask |= PORT_IRQ_PHYRDY;
 811		writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
 812	}
 813
 814	return 0;
 815}
 816
 817#ifdef CONFIG_PM
 818static void ahci_power_down(struct ata_port *ap)
 819{
 820	struct ahci_host_priv *hpriv = ap->host->private_data;
 821	void __iomem *port_mmio = ahci_port_base(ap);
 822	u32 cmd, scontrol;
 823
 824	if (!(hpriv->cap & HOST_CAP_SSS))
 825		return;
 826
 827	/* put device into listen mode, first set PxSCTL.DET to 0 */
 828	scontrol = readl(port_mmio + PORT_SCR_CTL);
 829	scontrol &= ~0xf;
 830	writel(scontrol, port_mmio + PORT_SCR_CTL);
 831
 832	/* then set PxCMD.SUD to 0 */
 833	cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
 834	cmd &= ~PORT_CMD_SPIN_UP;
 835	writel(cmd, port_mmio + PORT_CMD);
 836}
 837#endif
 838
 839static void ahci_start_port(struct ata_port *ap)
 840{
 841	struct ahci_host_priv *hpriv = ap->host->private_data;
 842	struct ahci_port_priv *pp = ap->private_data;
 843	struct ata_link *link;
 844	struct ahci_em_priv *emp;
 845	ssize_t rc;
 846	int i;
 847
 848	/* enable FIS reception */
 849	ahci_start_fis_rx(ap);
 850
 851	/* enable DMA */
 852	if (!(hpriv->flags & AHCI_HFLAG_DELAY_ENGINE))
 853		hpriv->start_engine(ap);
 854
 855	/* turn on LEDs */
 856	if (ap->flags & ATA_FLAG_EM) {
 857		ata_for_each_link(link, ap, EDGE) {
 858			emp = &pp->em_priv[link->pmp];
 859
 860			/* EM Transmit bit maybe busy during init */
 861			for (i = 0; i < EM_MAX_RETRY; i++) {
 862				rc = ap->ops->transmit_led_message(ap,
 863							       emp->led_state,
 864							       4);
 865				/*
 866				 * If busy, give a breather but do not
 867				 * release EH ownership by using msleep()
 868				 * instead of ata_msleep().  EM Transmit
 869				 * bit is busy for the whole host and
 870				 * releasing ownership will cause other
 871				 * ports to fail the same way.
 872				 */
 873				if (rc == -EBUSY)
 874					msleep(1);
 875				else
 876					break;
 877			}
 878		}
 879	}
 880
 881	if (ap->flags & ATA_FLAG_SW_ACTIVITY)
 882		ata_for_each_link(link, ap, EDGE)
 883			ahci_init_sw_activity(link);
 884
 885}
 886
 887static int ahci_deinit_port(struct ata_port *ap, const char **emsg)
 888{
 889	int rc;
 890	struct ahci_host_priv *hpriv = ap->host->private_data;
 891
 892	/* disable DMA */
 893	rc = hpriv->stop_engine(ap);
 894	if (rc) {
 895		*emsg = "failed to stop engine";
 896		return rc;
 897	}
 898
 899	/* disable FIS reception */
 900	rc = ahci_stop_fis_rx(ap);
 901	if (rc) {
 902		*emsg = "failed stop FIS RX";
 903		return rc;
 904	}
 905
 906	return 0;
 907}
 908
 909int ahci_reset_controller(struct ata_host *host)
 910{
 911	struct ahci_host_priv *hpriv = host->private_data;
 912	void __iomem *mmio = hpriv->mmio;
 913	u32 tmp;
 914
 915	/* we must be in AHCI mode, before using anything
 916	 * AHCI-specific, such as HOST_RESET.
 917	 */
 918	ahci_enable_ahci(mmio);
 919
 920	/* global controller reset */
 921	if (!ahci_skip_host_reset) {
 922		tmp = readl(mmio + HOST_CTL);
 923		if ((tmp & HOST_RESET) == 0) {
 924			writel(tmp | HOST_RESET, mmio + HOST_CTL);
 925			readl(mmio + HOST_CTL); /* flush */
 926		}
 927
 928		/*
 929		 * to perform host reset, OS should set HOST_RESET
 930		 * and poll until this bit is read to be "0".
 931		 * reset must complete within 1 second, or
 932		 * the hardware should be considered fried.
 933		 */
 934		tmp = ata_wait_register(NULL, mmio + HOST_CTL, HOST_RESET,
 935					HOST_RESET, 10, 1000);
 936
 937		if (tmp & HOST_RESET) {
 938			dev_err(host->dev, "controller reset failed (0x%x)\n",
 939				tmp);
 940			return -EIO;
 941		}
 942
 943		/* turn on AHCI mode */
 944		ahci_enable_ahci(mmio);
 945
 946		/* Some registers might be cleared on reset.  Restore
 947		 * initial values.
 948		 */
 949		if (!(hpriv->flags & AHCI_HFLAG_NO_WRITE_TO_RO))
 950			ahci_restore_initial_config(host);
 951	} else
 952		dev_info(host->dev, "skipping global host reset\n");
 953
 954	return 0;
 955}
 956EXPORT_SYMBOL_GPL(ahci_reset_controller);
 957
 958static void ahci_sw_activity(struct ata_link *link)
 959{
 960	struct ata_port *ap = link->ap;
 961	struct ahci_port_priv *pp = ap->private_data;
 962	struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
 963
 964	if (!(link->flags & ATA_LFLAG_SW_ACTIVITY))
 965		return;
 966
 967	emp->activity++;
 968	if (!timer_pending(&emp->timer))
 969		mod_timer(&emp->timer, jiffies + msecs_to_jiffies(10));
 970}
 971
 972static void ahci_sw_activity_blink(struct timer_list *t)
 973{
 974	struct ahci_em_priv *emp = from_timer(emp, t, timer);
 975	struct ata_link *link = emp->link;
 976	struct ata_port *ap = link->ap;
 977
 978	unsigned long led_message = emp->led_state;
 979	u32 activity_led_state;
 980	unsigned long flags;
 981
 982	led_message &= EM_MSG_LED_VALUE;
 983	led_message |= ap->port_no | (link->pmp << 8);
 984
 985	/* check to see if we've had activity.  If so,
 986	 * toggle state of LED and reset timer.  If not,
 987	 * turn LED to desired idle state.
 988	 */
 989	spin_lock_irqsave(ap->lock, flags);
 990	if (emp->saved_activity != emp->activity) {
 991		emp->saved_activity = emp->activity;
 992		/* get the current LED state */
 993		activity_led_state = led_message & EM_MSG_LED_VALUE_ON;
 994
 995		if (activity_led_state)
 996			activity_led_state = 0;
 997		else
 998			activity_led_state = 1;
 999
1000		/* clear old state */
1001		led_message &= ~EM_MSG_LED_VALUE_ACTIVITY;
1002
1003		/* toggle state */
1004		led_message |= (activity_led_state << 16);
1005		mod_timer(&emp->timer, jiffies + msecs_to_jiffies(100));
1006	} else {
1007		/* switch to idle */
1008		led_message &= ~EM_MSG_LED_VALUE_ACTIVITY;
1009		if (emp->blink_policy == BLINK_OFF)
1010			led_message |= (1 << 16);
1011	}
1012	spin_unlock_irqrestore(ap->lock, flags);
1013	ap->ops->transmit_led_message(ap, led_message, 4);
1014}
1015
1016static void ahci_init_sw_activity(struct ata_link *link)
1017{
1018	struct ata_port *ap = link->ap;
1019	struct ahci_port_priv *pp = ap->private_data;
1020	struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
1021
1022	/* init activity stats, setup timer */
1023	emp->saved_activity = emp->activity = 0;
1024	emp->link = link;
1025	timer_setup(&emp->timer, ahci_sw_activity_blink, 0);
1026
1027	/* check our blink policy and set flag for link if it's enabled */
1028	if (emp->blink_policy)
1029		link->flags |= ATA_LFLAG_SW_ACTIVITY;
1030}
1031
1032int ahci_reset_em(struct ata_host *host)
1033{
1034	struct ahci_host_priv *hpriv = host->private_data;
1035	void __iomem *mmio = hpriv->mmio;
1036	u32 em_ctl;
1037
1038	em_ctl = readl(mmio + HOST_EM_CTL);
1039	if ((em_ctl & EM_CTL_TM) || (em_ctl & EM_CTL_RST))
1040		return -EINVAL;
1041
1042	writel(em_ctl | EM_CTL_RST, mmio + HOST_EM_CTL);
1043	return 0;
1044}
1045EXPORT_SYMBOL_GPL(ahci_reset_em);
1046
1047static ssize_t ahci_transmit_led_message(struct ata_port *ap, u32 state,
1048					ssize_t size)
1049{
1050	struct ahci_host_priv *hpriv = ap->host->private_data;
1051	struct ahci_port_priv *pp = ap->private_data;
1052	void __iomem *mmio = hpriv->mmio;
1053	u32 em_ctl;
1054	u32 message[] = {0, 0};
1055	unsigned long flags;
1056	int pmp;
1057	struct ahci_em_priv *emp;
1058
1059	/* get the slot number from the message */
1060	pmp = (state & EM_MSG_LED_PMP_SLOT) >> 8;
1061	if (pmp < EM_MAX_SLOTS)
1062		emp = &pp->em_priv[pmp];
1063	else
1064		return -EINVAL;
1065
1066	ahci_rpm_get_port(ap);
1067	spin_lock_irqsave(ap->lock, flags);
1068
1069	/*
1070	 * if we are still busy transmitting a previous message,
1071	 * do not allow
1072	 */
1073	em_ctl = readl(mmio + HOST_EM_CTL);
1074	if (em_ctl & EM_CTL_TM) {
1075		spin_unlock_irqrestore(ap->lock, flags);
1076		ahci_rpm_put_port(ap);
1077		return -EBUSY;
1078	}
1079
1080	if (hpriv->em_msg_type & EM_MSG_TYPE_LED) {
1081		/*
1082		 * create message header - this is all zero except for
1083		 * the message size, which is 4 bytes.
1084		 */
1085		message[0] |= (4 << 8);
1086
1087		/* ignore 0:4 of byte zero, fill in port info yourself */
1088		message[1] = ((state & ~EM_MSG_LED_HBA_PORT) | ap->port_no);
1089
1090		/* write message to EM_LOC */
1091		writel(message[0], mmio + hpriv->em_loc);
1092		writel(message[1], mmio + hpriv->em_loc+4);
1093
1094		/*
1095		 * tell hardware to transmit the message
1096		 */
1097		writel(em_ctl | EM_CTL_TM, mmio + HOST_EM_CTL);
1098	}
1099
1100	/* save off new led state for port/slot */
1101	emp->led_state = state;
1102
1103	spin_unlock_irqrestore(ap->lock, flags);
1104	ahci_rpm_put_port(ap);
1105
1106	return size;
1107}
1108
1109static ssize_t ahci_led_show(struct ata_port *ap, char *buf)
1110{
1111	struct ahci_port_priv *pp = ap->private_data;
1112	struct ata_link *link;
1113	struct ahci_em_priv *emp;
1114	int rc = 0;
1115
1116	ata_for_each_link(link, ap, EDGE) {
1117		emp = &pp->em_priv[link->pmp];
1118		rc += sprintf(buf, "%lx\n", emp->led_state);
1119	}
1120	return rc;
1121}
1122
1123static ssize_t ahci_led_store(struct ata_port *ap, const char *buf,
1124				size_t size)
1125{
1126	unsigned int state;
1127	int pmp;
1128	struct ahci_port_priv *pp = ap->private_data;
1129	struct ahci_em_priv *emp;
1130
1131	if (kstrtouint(buf, 0, &state) < 0)
1132		return -EINVAL;
1133
1134	/* get the slot number from the message */
1135	pmp = (state & EM_MSG_LED_PMP_SLOT) >> 8;
1136	if (pmp < EM_MAX_SLOTS) {
1137		pmp = array_index_nospec(pmp, EM_MAX_SLOTS);
1138		emp = &pp->em_priv[pmp];
1139	} else {
1140		return -EINVAL;
1141	}
1142
1143	/* mask off the activity bits if we are in sw_activity
1144	 * mode, user should turn off sw_activity before setting
1145	 * activity led through em_message
1146	 */
1147	if (emp->blink_policy)
1148		state &= ~EM_MSG_LED_VALUE_ACTIVITY;
1149
1150	return ap->ops->transmit_led_message(ap, state, size);
1151}
1152
1153static ssize_t ahci_activity_store(struct ata_device *dev, enum sw_activity val)
1154{
1155	struct ata_link *link = dev->link;
1156	struct ata_port *ap = link->ap;
1157	struct ahci_port_priv *pp = ap->private_data;
1158	struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
1159	u32 port_led_state = emp->led_state;
1160
1161	/* save the desired Activity LED behavior */
1162	if (val == OFF) {
1163		/* clear LFLAG */
1164		link->flags &= ~(ATA_LFLAG_SW_ACTIVITY);
1165
1166		/* set the LED to OFF */
1167		port_led_state &= EM_MSG_LED_VALUE_OFF;
1168		port_led_state |= (ap->port_no | (link->pmp << 8));
1169		ap->ops->transmit_led_message(ap, port_led_state, 4);
1170	} else {
1171		link->flags |= ATA_LFLAG_SW_ACTIVITY;
1172		if (val == BLINK_OFF) {
1173			/* set LED to ON for idle */
1174			port_led_state &= EM_MSG_LED_VALUE_OFF;
1175			port_led_state |= (ap->port_no | (link->pmp << 8));
1176			port_led_state |= EM_MSG_LED_VALUE_ON; /* check this */
1177			ap->ops->transmit_led_message(ap, port_led_state, 4);
1178		}
1179	}
1180	emp->blink_policy = val;
1181	return 0;
1182}
1183
1184static ssize_t ahci_activity_show(struct ata_device *dev, char *buf)
1185{
1186	struct ata_link *link = dev->link;
1187	struct ata_port *ap = link->ap;
1188	struct ahci_port_priv *pp = ap->private_data;
1189	struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
1190
1191	/* display the saved value of activity behavior for this
1192	 * disk.
1193	 */
1194	return sprintf(buf, "%d\n", emp->blink_policy);
1195}
1196
1197static void ahci_port_init(struct device *dev, struct ata_port *ap,
1198			   int port_no, void __iomem *mmio,
1199			   void __iomem *port_mmio)
1200{
1201	struct ahci_host_priv *hpriv = ap->host->private_data;
1202	const char *emsg = NULL;
1203	int rc;
1204	u32 tmp;
1205
1206	/* make sure port is not active */
1207	rc = ahci_deinit_port(ap, &emsg);
1208	if (rc)
1209		dev_warn(dev, "%s (%d)\n", emsg, rc);
1210
1211	/* clear SError */
1212	tmp = readl(port_mmio + PORT_SCR_ERR);
1213	VPRINTK("PORT_SCR_ERR 0x%x\n", tmp);
1214	writel(tmp, port_mmio + PORT_SCR_ERR);
1215
1216	/* clear port IRQ */
1217	tmp = readl(port_mmio + PORT_IRQ_STAT);
1218	VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
1219	if (tmp)
1220		writel(tmp, port_mmio + PORT_IRQ_STAT);
1221
1222	writel(1 << port_no, mmio + HOST_IRQ_STAT);
1223
1224	/* mark esata ports */
1225	tmp = readl(port_mmio + PORT_CMD);
1226	if ((tmp & PORT_CMD_ESP) && (hpriv->cap & HOST_CAP_SXS))
1227		ap->pflags |= ATA_PFLAG_EXTERNAL;
1228}
1229
1230void ahci_init_controller(struct ata_host *host)
1231{
1232	struct ahci_host_priv *hpriv = host->private_data;
1233	void __iomem *mmio = hpriv->mmio;
1234	int i;
1235	void __iomem *port_mmio;
1236	u32 tmp;
1237
1238	for (i = 0; i < host->n_ports; i++) {
1239		struct ata_port *ap = host->ports[i];
1240
1241		port_mmio = ahci_port_base(ap);
1242		if (ata_port_is_dummy(ap))
1243			continue;
1244
1245		ahci_port_init(host->dev, ap, i, mmio, port_mmio);
1246	}
1247
1248	tmp = readl(mmio + HOST_CTL);
1249	VPRINTK("HOST_CTL 0x%x\n", tmp);
1250	writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL);
1251	tmp = readl(mmio + HOST_CTL);
1252	VPRINTK("HOST_CTL 0x%x\n", tmp);
1253}
1254EXPORT_SYMBOL_GPL(ahci_init_controller);
1255
1256static void ahci_dev_config(struct ata_device *dev)
1257{
1258	struct ahci_host_priv *hpriv = dev->link->ap->host->private_data;
1259
1260	if (hpriv->flags & AHCI_HFLAG_SECT255) {
1261		dev->max_sectors = 255;
1262		ata_dev_info(dev,
1263			     "SB600 AHCI: limiting to 255 sectors per cmd\n");
1264	}
1265}
1266
1267unsigned int ahci_dev_classify(struct ata_port *ap)
1268{
1269	void __iomem *port_mmio = ahci_port_base(ap);
1270	struct ata_taskfile tf;
1271	u32 tmp;
1272
1273	tmp = readl(port_mmio + PORT_SIG);
1274	tf.lbah		= (tmp >> 24)	& 0xff;
1275	tf.lbam		= (tmp >> 16)	& 0xff;
1276	tf.lbal		= (tmp >> 8)	& 0xff;
1277	tf.nsect	= (tmp)		& 0xff;
1278
1279	return ata_dev_classify(&tf);
1280}
1281EXPORT_SYMBOL_GPL(ahci_dev_classify);
1282
1283void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag,
1284			u32 opts)
1285{
1286	dma_addr_t cmd_tbl_dma;
1287
1288	cmd_tbl_dma = pp->cmd_tbl_dma + tag * AHCI_CMD_TBL_SZ;
1289
1290	pp->cmd_slot[tag].opts = cpu_to_le32(opts);
1291	pp->cmd_slot[tag].status = 0;
1292	pp->cmd_slot[tag].tbl_addr = cpu_to_le32(cmd_tbl_dma & 0xffffffff);
1293	pp->cmd_slot[tag].tbl_addr_hi = cpu_to_le32((cmd_tbl_dma >> 16) >> 16);
1294}
1295EXPORT_SYMBOL_GPL(ahci_fill_cmd_slot);
1296
1297int ahci_kick_engine(struct ata_port *ap)
1298{
1299	void __iomem *port_mmio = ahci_port_base(ap);
1300	struct ahci_host_priv *hpriv = ap->host->private_data;
1301	u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF;
1302	u32 tmp;
1303	int busy, rc;
1304
1305	/* stop engine */
1306	rc = hpriv->stop_engine(ap);
1307	if (rc)
1308		goto out_restart;
1309
1310	/* need to do CLO?
1311	 * always do CLO if PMP is attached (AHCI-1.3 9.2)
1312	 */
1313	busy = status & (ATA_BUSY | ATA_DRQ);
1314	if (!busy && !sata_pmp_attached(ap)) {
1315		rc = 0;
1316		goto out_restart;
1317	}
1318
1319	if (!(hpriv->cap & HOST_CAP_CLO)) {
1320		rc = -EOPNOTSUPP;
1321		goto out_restart;
1322	}
1323
1324	/* perform CLO */
1325	tmp = readl(port_mmio + PORT_CMD);
1326	tmp |= PORT_CMD_CLO;
1327	writel(tmp, port_mmio + PORT_CMD);
1328
1329	rc = 0;
1330	tmp = ata_wait_register(ap, port_mmio + PORT_CMD,
1331				PORT_CMD_CLO, PORT_CMD_CLO, 1, 500);
1332	if (tmp & PORT_CMD_CLO)
1333		rc = -EIO;
1334
1335	/* restart engine */
1336 out_restart:
1337	hpriv->start_engine(ap);
1338	return rc;
1339}
1340EXPORT_SYMBOL_GPL(ahci_kick_engine);
1341
1342static int ahci_exec_polled_cmd(struct ata_port *ap, int pmp,
1343				struct ata_taskfile *tf, int is_cmd, u16 flags,
1344				unsigned long timeout_msec)
1345{
1346	const u32 cmd_fis_len = 5; /* five dwords */
1347	struct ahci_port_priv *pp = ap->private_data;
1348	void __iomem *port_mmio = ahci_port_base(ap);
1349	u8 *fis = pp->cmd_tbl;
1350	u32 tmp;
1351
1352	/* prep the command */
1353	ata_tf_to_fis(tf, pmp, is_cmd, fis);
1354	ahci_fill_cmd_slot(pp, 0, cmd_fis_len | flags | (pmp << 12));
1355
1356	/* set port value for softreset of Port Multiplier */
1357	if (pp->fbs_enabled && pp->fbs_last_dev != pmp) {
1358		tmp = readl(port_mmio + PORT_FBS);
1359		tmp &= ~(PORT_FBS_DEV_MASK | PORT_FBS_DEC);
1360		tmp |= pmp << PORT_FBS_DEV_OFFSET;
1361		writel(tmp, port_mmio + PORT_FBS);
1362		pp->fbs_last_dev = pmp;
1363	}
1364
1365	/* issue & wait */
1366	writel(1, port_mmio + PORT_CMD_ISSUE);
1367
1368	if (timeout_msec) {
1369		tmp = ata_wait_register(ap, port_mmio + PORT_CMD_ISSUE,
1370					0x1, 0x1, 1, timeout_msec);
1371		if (tmp & 0x1) {
1372			ahci_kick_engine(ap);
1373			return -EBUSY;
1374		}
1375	} else
1376		readl(port_mmio + PORT_CMD_ISSUE);	/* flush */
1377
1378	return 0;
1379}
1380
1381int ahci_do_softreset(struct ata_link *link, unsigned int *class,
1382		      int pmp, unsigned long deadline,
1383		      int (*check_ready)(struct ata_link *link))
1384{
1385	struct ata_port *ap = link->ap;
1386	struct ahci_host_priv *hpriv = ap->host->private_data;
1387	struct ahci_port_priv *pp = ap->private_data;
1388	const char *reason = NULL;
1389	unsigned long now, msecs;
1390	struct ata_taskfile tf;
1391	bool fbs_disabled = false;
1392	int rc;
1393
1394	DPRINTK("ENTER\n");
1395
1396	/* prepare for SRST (AHCI-1.1 10.4.1) */
1397	rc = ahci_kick_engine(ap);
1398	if (rc && rc != -EOPNOTSUPP)
1399		ata_link_warn(link, "failed to reset engine (errno=%d)\n", rc);
1400
1401	/*
1402	 * According to AHCI-1.2 9.3.9: if FBS is enable, software shall
1403	 * clear PxFBS.EN to '0' prior to issuing software reset to devices
1404	 * that is attached to port multiplier.
1405	 */
1406	if (!ata_is_host_link(link) && pp->fbs_enabled) {
1407		ahci_disable_fbs(ap);
1408		fbs_disabled = true;
1409	}
1410
1411	ata_tf_init(link->device, &tf);
1412
1413	/* issue the first H2D Register FIS */
1414	msecs = 0;
1415	now = jiffies;
1416	if (time_after(deadline, now))
1417		msecs = jiffies_to_msecs(deadline - now);
1418
1419	tf.ctl |= ATA_SRST;
1420	if (ahci_exec_polled_cmd(ap, pmp, &tf, 0,
1421				 AHCI_CMD_RESET | AHCI_CMD_CLR_BUSY, msecs)) {
1422		rc = -EIO;
1423		reason = "1st FIS failed";
1424		goto fail;
1425	}
1426
1427	/* spec says at least 5us, but be generous and sleep for 1ms */
1428	ata_msleep(ap, 1);
1429
1430	/* issue the second H2D Register FIS */
1431	tf.ctl &= ~ATA_SRST;
1432	ahci_exec_polled_cmd(ap, pmp, &tf, 0, 0, 0);
1433
1434	/* wait for link to become ready */
1435	rc = ata_wait_after_reset(link, deadline, check_ready);
1436	if (rc == -EBUSY && hpriv->flags & AHCI_HFLAG_SRST_TOUT_IS_OFFLINE) {
1437		/*
1438		 * Workaround for cases where link online status can't
1439		 * be trusted.  Treat device readiness timeout as link
1440		 * offline.
1441		 */
1442		ata_link_info(link, "device not ready, treating as offline\n");
1443		*class = ATA_DEV_NONE;
1444	} else if (rc) {
1445		/* link occupied, -ENODEV too is an error */
1446		reason = "device not ready";
1447		goto fail;
1448	} else
1449		*class = ahci_dev_classify(ap);
1450
1451	/* re-enable FBS if disabled before */
1452	if (fbs_disabled)
1453		ahci_enable_fbs(ap);
1454
1455	DPRINTK("EXIT, class=%u\n", *class);
1456	return 0;
1457
1458 fail:
1459	ata_link_err(link, "softreset failed (%s)\n", reason);
1460	return rc;
1461}
1462
1463int ahci_check_ready(struct ata_link *link)
1464{
1465	void __iomem *port_mmio = ahci_port_base(link->ap);
1466	u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF;
1467
1468	return ata_check_ready(status);
1469}
1470EXPORT_SYMBOL_GPL(ahci_check_ready);
1471
1472static int ahci_softreset(struct ata_link *link, unsigned int *class,
1473			  unsigned long deadline)
1474{
1475	int pmp = sata_srst_pmp(link);
1476
1477	DPRINTK("ENTER\n");
1478
1479	return ahci_do_softreset(link, class, pmp, deadline, ahci_check_ready);
1480}
1481EXPORT_SYMBOL_GPL(ahci_do_softreset);
1482
1483static int ahci_bad_pmp_check_ready(struct ata_link *link)
1484{
1485	void __iomem *port_mmio = ahci_port_base(link->ap);
1486	u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF;
1487	u32 irq_status = readl(port_mmio + PORT_IRQ_STAT);
1488
1489	/*
1490	 * There is no need to check TFDATA if BAD PMP is found due to HW bug,
1491	 * which can save timeout delay.
1492	 */
1493	if (irq_status & PORT_IRQ_BAD_PMP)
1494		return -EIO;
1495
1496	return ata_check_ready(status);
1497}
1498
1499static int ahci_pmp_retry_softreset(struct ata_link *link, unsigned int *class,
1500				    unsigned long deadline)
1501{
1502	struct ata_port *ap = link->ap;
1503	void __iomem *port_mmio = ahci_port_base(ap);
1504	int pmp = sata_srst_pmp(link);
1505	int rc;
1506	u32 irq_sts;
1507
1508	DPRINTK("ENTER\n");
1509
1510	rc = ahci_do_softreset(link, class, pmp, deadline,
1511			       ahci_bad_pmp_check_ready);
1512
1513	/*
1514	 * Soft reset fails with IPMS set when PMP is enabled but
1515	 * SATA HDD/ODD is connected to SATA port, do soft reset
1516	 * again to port 0.
1517	 */
1518	if (rc == -EIO) {
1519		irq_sts = readl(port_mmio + PORT_IRQ_STAT);
1520		if (irq_sts & PORT_IRQ_BAD_PMP) {
1521			ata_link_warn(link,
1522					"applying PMP SRST workaround "
1523					"and retrying\n");
1524			rc = ahci_do_softreset(link, class, 0, deadline,
1525					       ahci_check_ready);
1526		}
1527	}
1528
1529	return rc;
1530}
1531
1532int ahci_do_hardreset(struct ata_link *link, unsigned int *class,
1533		      unsigned long deadline, bool *online)
1534{
1535	const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context);
1536	struct ata_port *ap = link->ap;
1537	struct ahci_port_priv *pp = ap->private_data;
1538	struct ahci_host_priv *hpriv = ap->host->private_data;
1539	u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
1540	struct ata_taskfile tf;
1541	int rc;
1542
1543	DPRINTK("ENTER\n");
1544
1545	hpriv->stop_engine(ap);
1546
1547	/* clear D2H reception area to properly wait for D2H FIS */
1548	ata_tf_init(link->device, &tf);
1549	tf.command = ATA_BUSY;
1550	ata_tf_to_fis(&tf, 0, 0, d2h_fis);
1551
1552	rc = sata_link_hardreset(link, timing, deadline, online,
1553				 ahci_check_ready);
1554
1555	hpriv->start_engine(ap);
1556
1557	if (*online)
1558		*class = ahci_dev_classify(ap);
1559
1560	DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
1561	return rc;
1562}
1563EXPORT_SYMBOL_GPL(ahci_do_hardreset);
1564
1565static int ahci_hardreset(struct ata_link *link, unsigned int *class,
1566			  unsigned long deadline)
1567{
1568	bool online;
1569
1570	return ahci_do_hardreset(link, class, deadline, &online);
1571}
1572
1573static void ahci_postreset(struct ata_link *link, unsigned int *class)
1574{
1575	struct ata_port *ap = link->ap;
1576	void __iomem *port_mmio = ahci_port_base(ap);
1577	u32 new_tmp, tmp;
1578
1579	ata_std_postreset(link, class);
1580
1581	/* Make sure port's ATAPI bit is set appropriately */
1582	new_tmp = tmp = readl(port_mmio + PORT_CMD);
1583	if (*class == ATA_DEV_ATAPI)
1584		new_tmp |= PORT_CMD_ATAPI;
1585	else
1586		new_tmp &= ~PORT_CMD_ATAPI;
1587	if (new_tmp != tmp) {
1588		writel(new_tmp, port_mmio + PORT_CMD);
1589		readl(port_mmio + PORT_CMD); /* flush */
1590	}
1591}
1592
1593static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc, void *cmd_tbl)
1594{
1595	struct scatterlist *sg;
1596	struct ahci_sg *ahci_sg = cmd_tbl + AHCI_CMD_TBL_HDR_SZ;
1597	unsigned int si;
1598
1599	VPRINTK("ENTER\n");
1600
1601	/*
1602	 * Next, the S/G list.
1603	 */
1604	for_each_sg(qc->sg, sg, qc->n_elem, si) {
1605		dma_addr_t addr = sg_dma_address(sg);
1606		u32 sg_len = sg_dma_len(sg);
1607
1608		ahci_sg[si].addr = cpu_to_le32(addr & 0xffffffff);
1609		ahci_sg[si].addr_hi = cpu_to_le32((addr >> 16) >> 16);
1610		ahci_sg[si].flags_size = cpu_to_le32(sg_len - 1);
1611	}
1612
1613	return si;
1614}
1615
1616static int ahci_pmp_qc_defer(struct ata_queued_cmd *qc)
1617{
1618	struct ata_port *ap = qc->ap;
1619	struct ahci_port_priv *pp = ap->private_data;
1620
1621	if (!sata_pmp_attached(ap) || pp->fbs_enabled)
1622		return ata_std_qc_defer(qc);
1623	else
1624		return sata_pmp_qc_defer_cmd_switch(qc);
1625}
1626
1627static enum ata_completion_errors ahci_qc_prep(struct ata_queued_cmd *qc)
1628{
1629	struct ata_port *ap = qc->ap;
1630	struct ahci_port_priv *pp = ap->private_data;
1631	int is_atapi = ata_is_atapi(qc->tf.protocol);
1632	void *cmd_tbl;
1633	u32 opts;
1634	const u32 cmd_fis_len = 5; /* five dwords */
1635	unsigned int n_elem;
1636
1637	/*
1638	 * Fill in command table information.  First, the header,
1639	 * a SATA Register - Host to Device command FIS.
1640	 */
1641	cmd_tbl = pp->cmd_tbl + qc->hw_tag * AHCI_CMD_TBL_SZ;
1642
1643	ata_tf_to_fis(&qc->tf, qc->dev->link->pmp, 1, cmd_tbl);
1644	if (is_atapi) {
1645		memset(cmd_tbl + AHCI_CMD_TBL_CDB, 0, 32);
1646		memcpy(cmd_tbl + AHCI_CMD_TBL_CDB, qc->cdb, qc->dev->cdb_len);
1647	}
1648
1649	n_elem = 0;
1650	if (qc->flags & ATA_QCFLAG_DMAMAP)
1651		n_elem = ahci_fill_sg(qc, cmd_tbl);
1652
1653	/*
1654	 * Fill in command slot information.
1655	 */
1656	opts = cmd_fis_len | n_elem << 16 | (qc->dev->link->pmp << 12);
1657	if (qc->tf.flags & ATA_TFLAG_WRITE)
1658		opts |= AHCI_CMD_WRITE;
1659	if (is_atapi)
1660		opts |= AHCI_CMD_ATAPI | AHCI_CMD_PREFETCH;
1661
1662	ahci_fill_cmd_slot(pp, qc->hw_tag, opts);
1663
1664	return AC_ERR_OK;
1665}
1666
1667static void ahci_fbs_dec_intr(struct ata_port *ap)
1668{
1669	struct ahci_port_priv *pp = ap->private_data;
1670	void __iomem *port_mmio = ahci_port_base(ap);
1671	u32 fbs = readl(port_mmio + PORT_FBS);
1672	int retries = 3;
1673
1674	DPRINTK("ENTER\n");
1675	BUG_ON(!pp->fbs_enabled);
1676
1677	/* time to wait for DEC is not specified by AHCI spec,
1678	 * add a retry loop for safety.
1679	 */
1680	writel(fbs | PORT_FBS_DEC, port_mmio + PORT_FBS);
1681	fbs = readl(port_mmio + PORT_FBS);
1682	while ((fbs & PORT_FBS_DEC) && retries--) {
1683		udelay(1);
1684		fbs = readl(port_mmio + PORT_FBS);
1685	}
1686
1687	if (fbs & PORT_FBS_DEC)
1688		dev_err(ap->host->dev, "failed to clear device error\n");
1689}
1690
1691static void ahci_error_intr(struct ata_port *ap, u32 irq_stat)
1692{
1693	struct ahci_host_priv *hpriv = ap->host->private_data;
1694	struct ahci_port_priv *pp = ap->private_data;
1695	struct ata_eh_info *host_ehi = &ap->link.eh_info;
1696	struct ata_link *link = NULL;
1697	struct ata_queued_cmd *active_qc;
1698	struct ata_eh_info *active_ehi;
1699	bool fbs_need_dec = false;
1700	u32 serror;
1701
1702	/* determine active link with error */
1703	if (pp->fbs_enabled) {
1704		void __iomem *port_mmio = ahci_port_base(ap);
1705		u32 fbs = readl(port_mmio + PORT_FBS);
1706		int pmp = fbs >> PORT_FBS_DWE_OFFSET;
1707
1708		if ((fbs & PORT_FBS_SDE) && (pmp < ap->nr_pmp_links)) {
1709			link = &ap->pmp_link[pmp];
1710			fbs_need_dec = true;
1711		}
1712
1713	} else
1714		ata_for_each_link(link, ap, EDGE)
1715			if (ata_link_active(link))
1716				break;
1717
1718	if (!link)
1719		link = &ap->link;
1720
1721	active_qc = ata_qc_from_tag(ap, link->active_tag);
1722	active_ehi = &link->eh_info;
1723
1724	/* record irq stat */
1725	ata_ehi_clear_desc(host_ehi);
1726	ata_ehi_push_desc(host_ehi, "irq_stat 0x%08x", irq_stat);
1727
1728	/* AHCI needs SError cleared; otherwise, it might lock up */
1729	ahci_scr_read(&ap->link, SCR_ERROR, &serror);
1730	ahci_scr_write(&ap->link, SCR_ERROR, serror);
1731	host_ehi->serror |= serror;
1732
1733	/* some controllers set IRQ_IF_ERR on device errors, ignore it */
1734	if (hpriv->flags & AHCI_HFLAG_IGN_IRQ_IF_ERR)
1735		irq_stat &= ~PORT_IRQ_IF_ERR;
1736
1737	if (irq_stat & PORT_IRQ_TF_ERR) {
1738		/* If qc is active, charge it; otherwise, the active
1739		 * link.  There's no active qc on NCQ errors.  It will
1740		 * be determined by EH by reading log page 10h.
1741		 */
1742		if (active_qc)
1743			active_qc->err_mask |= AC_ERR_DEV;
1744		else
1745			active_ehi->err_mask |= AC_ERR_DEV;
1746
1747		if (hpriv->flags & AHCI_HFLAG_IGN_SERR_INTERNAL)
1748			host_ehi->serror &= ~SERR_INTERNAL;
1749	}
1750
1751	if (irq_stat & PORT_IRQ_UNK_FIS) {
1752		u32 *unk = pp->rx_fis + RX_FIS_UNK;
1753
1754		active_ehi->err_mask |= AC_ERR_HSM;
1755		active_ehi->action |= ATA_EH_RESET;
1756		ata_ehi_push_desc(active_ehi,
1757				  "unknown FIS %08x %08x %08x %08x" ,
1758				  unk[0], unk[1], unk[2], unk[3]);
1759	}
1760
1761	if (sata_pmp_attached(ap) && (irq_stat & PORT_IRQ_BAD_PMP)) {
1762		active_ehi->err_mask |= AC_ERR_HSM;
1763		active_ehi->action |= ATA_EH_RESET;
1764		ata_ehi_push_desc(active_ehi, "incorrect PMP");
1765	}
1766
1767	if (irq_stat & (PORT_IRQ_HBUS_ERR | PORT_IRQ_HBUS_DATA_ERR)) {
1768		host_ehi->err_mask |= AC_ERR_HOST_BUS;
1769		host_ehi->action |= ATA_EH_RESET;
1770		ata_ehi_push_desc(host_ehi, "host bus error");
1771	}
1772
1773	if (irq_stat & PORT_IRQ_IF_ERR) {
1774		if (fbs_need_dec)
1775			active_ehi->err_mask |= AC_ERR_DEV;
1776		else {
1777			host_ehi->err_mask |= AC_ERR_ATA_BUS;
1778			host_ehi->action |= ATA_EH_RESET;
1779		}
1780
1781		ata_ehi_push_desc(host_ehi, "interface fatal error");
1782	}
1783
1784	if (irq_stat & (PORT_IRQ_CONNECT | PORT_IRQ_PHYRDY)) {
1785		ata_ehi_hotplugged(host_ehi);
1786		ata_ehi_push_desc(host_ehi, "%s",
1787			irq_stat & PORT_IRQ_CONNECT ?
1788			"connection status changed" : "PHY RDY changed");
1789	}
1790
1791	/* okay, let's hand over to EH */
1792
1793	if (irq_stat & PORT_IRQ_FREEZE)
1794		ata_port_freeze(ap);
1795	else if (fbs_need_dec) {
1796		ata_link_abort(link);
1797		ahci_fbs_dec_intr(ap);
1798	} else
1799		ata_port_abort(ap);
1800}
1801
1802static void ahci_handle_port_interrupt(struct ata_port *ap,
1803				       void __iomem *port_mmio, u32 status)
1804{
1805	struct ata_eh_info *ehi = &ap->link.eh_info;
1806	struct ahci_port_priv *pp = ap->private_data;
1807	struct ahci_host_priv *hpriv = ap->host->private_data;
1808	int resetting = !!(ap->pflags & ATA_PFLAG_RESETTING);
1809	u32 qc_active = 0;
1810	int rc;
1811
1812	/* ignore BAD_PMP while resetting */
1813	if (unlikely(resetting))
1814		status &= ~PORT_IRQ_BAD_PMP;
1815
1816	if (sata_lpm_ignore_phy_events(&ap->link)) {
1817		status &= ~PORT_IRQ_PHYRDY;
1818		ahci_scr_write(&ap->link, SCR_ERROR, SERR_PHYRDY_CHG);
1819	}
1820
1821	if (unlikely(status & PORT_IRQ_ERROR)) {
1822		ahci_error_intr(ap, status);
1823		return;
1824	}
1825
1826	if (status & PORT_IRQ_SDB_FIS) {
1827		/* If SNotification is available, leave notification
1828		 * handling to sata_async_notification().  If not,
1829		 * emulate it by snooping SDB FIS RX area.
1830		 *
1831		 * Snooping FIS RX area is probably cheaper than
1832		 * poking SNotification but some constrollers which
1833		 * implement SNotification, ICH9 for example, don't
1834		 * store AN SDB FIS into receive area.
1835		 */
1836		if (hpriv->cap & HOST_CAP_SNTF)
1837			sata_async_notification(ap);
1838		else {
1839			/* If the 'N' bit in word 0 of the FIS is set,
1840			 * we just received asynchronous notification.
1841			 * Tell libata about it.
1842			 *
1843			 * Lack of SNotification should not appear in
1844			 * ahci 1.2, so the workaround is unnecessary
1845			 * when FBS is enabled.
1846			 */
1847			if (pp->fbs_enabled)
1848				WARN_ON_ONCE(1);
1849			else {
1850				const __le32 *f = pp->rx_fis + RX_FIS_SDB;
1851				u32 f0 = le32_to_cpu(f[0]);
1852				if (f0 & (1 << 15))
1853					sata_async_notification(ap);
1854			}
1855		}
1856	}
1857
1858	/* pp->active_link is not reliable once FBS is enabled, both
1859	 * PORT_SCR_ACT and PORT_CMD_ISSUE should be checked because
1860	 * NCQ and non-NCQ commands may be in flight at the same time.
1861	 */
1862	if (pp->fbs_enabled) {
1863		if (ap->qc_active) {
1864			qc_active = readl(port_mmio + PORT_SCR_ACT);
1865			qc_active |= readl(port_mmio + PORT_CMD_ISSUE);
1866		}
1867	} else {
1868		/* pp->active_link is valid iff any command is in flight */
1869		if (ap->qc_active && pp->active_link->sactive)
1870			qc_active = readl(port_mmio + PORT_SCR_ACT);
1871		else
1872			qc_active = readl(port_mmio + PORT_CMD_ISSUE);
1873	}
1874
1875
1876	rc = ata_qc_complete_multiple(ap, qc_active);
1877
1878	/* while resetting, invalid completions are expected */
1879	if (unlikely(rc < 0 && !resetting)) {
1880		ehi->err_mask |= AC_ERR_HSM;
1881		ehi->action |= ATA_EH_RESET;
1882		ata_port_freeze(ap);
1883	}
1884}
1885
1886static void ahci_port_intr(struct ata_port *ap)
1887{
1888	void __iomem *port_mmio = ahci_port_base(ap);
1889	u32 status;
1890
1891	status = readl(port_mmio + PORT_IRQ_STAT);
1892	writel(status, port_mmio + PORT_IRQ_STAT);
1893
1894	ahci_handle_port_interrupt(ap, port_mmio, status);
1895}
1896
1897static irqreturn_t ahci_multi_irqs_intr_hard(int irq, void *dev_instance)
1898{
1899	struct ata_port *ap = dev_instance;
1900	void __iomem *port_mmio = ahci_port_base(ap);
1901	u32 status;
1902
1903	VPRINTK("ENTER\n");
1904
1905	status = readl(port_mmio + PORT_IRQ_STAT);
1906	writel(status, port_mmio + PORT_IRQ_STAT);
1907
1908	spin_lock(ap->lock);
1909	ahci_handle_port_interrupt(ap, port_mmio, status);
1910	spin_unlock(ap->lock);
1911
1912	VPRINTK("EXIT\n");
1913
1914	return IRQ_HANDLED;
1915}
1916
1917u32 ahci_handle_port_intr(struct ata_host *host, u32 irq_masked)
1918{
1919	unsigned int i, handled = 0;
1920
1921	for (i = 0; i < host->n_ports; i++) {
1922		struct ata_port *ap;
1923
1924		if (!(irq_masked & (1 << i)))
1925			continue;
1926
1927		ap = host->ports[i];
1928		if (ap) {
1929			ahci_port_intr(ap);
1930			VPRINTK("port %u\n", i);
1931		} else {
1932			VPRINTK("port %u (no irq)\n", i);
1933			if (ata_ratelimit())
1934				dev_warn(host->dev,
1935					 "interrupt on disabled port %u\n", i);
1936		}
1937
1938		handled = 1;
1939	}
1940
1941	return handled;
1942}
1943EXPORT_SYMBOL_GPL(ahci_handle_port_intr);
1944
1945static irqreturn_t ahci_single_level_irq_intr(int irq, void *dev_instance)
1946{
1947	struct ata_host *host = dev_instance;
1948	struct ahci_host_priv *hpriv;
1949	unsigned int rc = 0;
1950	void __iomem *mmio;
1951	u32 irq_stat, irq_masked;
1952
1953	VPRINTK("ENTER\n");
1954
1955	hpriv = host->private_data;
1956	mmio = hpriv->mmio;
1957
1958	/* sigh.  0xffffffff is a valid return from h/w */
1959	irq_stat = readl(mmio + HOST_IRQ_STAT);
1960	if (!irq_stat)
1961		return IRQ_NONE;
1962
1963	irq_masked = irq_stat & hpriv->port_map;
1964
1965	spin_lock(&host->lock);
1966
1967	rc = ahci_handle_port_intr(host, irq_masked);
1968
1969	/* HOST_IRQ_STAT behaves as level triggered latch meaning that
1970	 * it should be cleared after all the port events are cleared;
1971	 * otherwise, it will raise a spurious interrupt after each
1972	 * valid one.  Please read section 10.6.2 of ahci 1.1 for more
1973	 * information.
1974	 *
1975	 * Also, use the unmasked value to clear interrupt as spurious
1976	 * pending event on a dummy port might cause screaming IRQ.
1977	 */
1978	writel(irq_stat, mmio + HOST_IRQ_STAT);
1979
1980	spin_unlock(&host->lock);
1981
1982	VPRINTK("EXIT\n");
1983
1984	return IRQ_RETVAL(rc);
1985}
1986
1987unsigned int ahci_qc_issue(struct ata_queued_cmd *qc)
1988{
1989	struct ata_port *ap = qc->ap;
1990	void __iomem *port_mmio = ahci_port_base(ap);
1991	struct ahci_port_priv *pp = ap->private_data;
1992
1993	/* Keep track of the currently active link.  It will be used
1994	 * in completion path to determine whether NCQ phase is in
1995	 * progress.
1996	 */
1997	pp->active_link = qc->dev->link;
1998
1999	if (ata_is_ncq(qc->tf.protocol))
2000		writel(1 << qc->hw_tag, port_mmio + PORT_SCR_ACT);
2001
2002	if (pp->fbs_enabled && pp->fbs_last_dev != qc->dev->link->pmp) {
2003		u32 fbs = readl(port_mmio + PORT_FBS);
2004		fbs &= ~(PORT_FBS_DEV_MASK | PORT_FBS_DEC);
2005		fbs |= qc->dev->link->pmp << PORT_FBS_DEV_OFFSET;
2006		writel(fbs, port_mmio + PORT_FBS);
2007		pp->fbs_last_dev = qc->dev->link->pmp;
2008	}
2009
2010	writel(1 << qc->hw_tag, port_mmio + PORT_CMD_ISSUE);
2011
2012	ahci_sw_activity(qc->dev->link);
2013
2014	return 0;
2015}
2016EXPORT_SYMBOL_GPL(ahci_qc_issue);
2017
2018static bool ahci_qc_fill_rtf(struct ata_queued_cmd *qc)
2019{
2020	struct ahci_port_priv *pp = qc->ap->private_data;
2021	u8 *rx_fis = pp->rx_fis;
2022
2023	if (pp->fbs_enabled)
2024		rx_fis += qc->dev->link->pmp * AHCI_RX_FIS_SZ;
2025
2026	/*
2027	 * After a successful execution of an ATA PIO data-in command,
2028	 * the device doesn't send D2H Reg FIS to update the TF and
2029	 * the host should take TF and E_Status from the preceding PIO
2030	 * Setup FIS.
2031	 */
2032	if (qc->tf.protocol == ATA_PROT_PIO && qc->dma_dir == DMA_FROM_DEVICE &&
2033	    !(qc->flags & ATA_QCFLAG_FAILED)) {
2034		ata_tf_from_fis(rx_fis + RX_FIS_PIO_SETUP, &qc->result_tf);
2035		qc->result_tf.command = (rx_fis + RX_FIS_PIO_SETUP)[15];
2036	} else
2037		ata_tf_from_fis(rx_fis + RX_FIS_D2H_REG, &qc->result_tf);
2038
2039	return true;
2040}
2041
2042static void ahci_freeze(struct ata_port *ap)
2043{
2044	void __iomem *port_mmio = ahci_port_base(ap);
2045
2046	/* turn IRQ off */
2047	writel(0, port_mmio + PORT_IRQ_MASK);
2048}
2049
2050static void ahci_thaw(struct ata_port *ap)
2051{
2052	struct ahci_host_priv *hpriv = ap->host->private_data;
2053	void __iomem *mmio = hpriv->mmio;
2054	void __iomem *port_mmio = ahci_port_base(ap);
2055	u32 tmp;
2056	struct ahci_port_priv *pp = ap->private_data;
2057
2058	/* clear IRQ */
2059	tmp = readl(port_mmio + PORT_IRQ_STAT);
2060	writel(tmp, port_mmio + PORT_IRQ_STAT);
2061	writel(1 << ap->port_no, mmio + HOST_IRQ_STAT);
2062
2063	/* turn IRQ back on */
2064	writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
2065}
2066
2067void ahci_error_handler(struct ata_port *ap)
2068{
2069	struct ahci_host_priv *hpriv = ap->host->private_data;
2070
2071	if (!(ap->pflags & ATA_PFLAG_FROZEN)) {
2072		/* restart engine */
2073		hpriv->stop_engine(ap);
2074		hpriv->start_engine(ap);
2075	}
2076
2077	sata_pmp_error_handler(ap);
2078
2079	if (!ata_dev_enabled(ap->link.device))
2080		hpriv->stop_engine(ap);
2081}
2082EXPORT_SYMBOL_GPL(ahci_error_handler);
2083
2084static void ahci_post_internal_cmd(struct ata_queued_cmd *qc)
2085{
2086	struct ata_port *ap = qc->ap;
2087
2088	/* make DMA engine forget about the failed command */
2089	if (qc->flags & ATA_QCFLAG_FAILED)
2090		ahci_kick_engine(ap);
2091}
2092
2093static void ahci_set_aggressive_devslp(struct ata_port *ap, bool sleep)
2094{
2095	struct ahci_host_priv *hpriv = ap->host->private_data;
2096	void __iomem *port_mmio = ahci_port_base(ap);
2097	struct ata_device *dev = ap->link.device;
2098	u32 devslp, dm, dito, mdat, deto, dito_conf;
2099	int rc;
2100	unsigned int err_mask;
2101
2102	devslp = readl(port_mmio + PORT_DEVSLP);
2103	if (!(devslp & PORT_DEVSLP_DSP)) {
2104		dev_info(ap->host->dev, "port does not support device sleep\n");
2105		return;
2106	}
2107
2108	/* disable device sleep */
2109	if (!sleep) {
2110		if (devslp & PORT_DEVSLP_ADSE) {
2111			writel(devslp & ~PORT_DEVSLP_ADSE,
2112			       port_mmio + PORT_DEVSLP);
2113			err_mask = ata_dev_set_feature(dev,
2114						       SETFEATURES_SATA_DISABLE,
2115						       SATA_DEVSLP);
2116			if (err_mask && err_mask != AC_ERR_DEV)
2117				ata_dev_warn(dev, "failed to disable DEVSLP\n");
2118		}
2119		return;
2120	}
2121
2122	dm = (devslp & PORT_DEVSLP_DM_MASK) >> PORT_DEVSLP_DM_OFFSET;
2123	dito = devslp_idle_timeout / (dm + 1);
2124	if (dito > 0x3ff)
2125		dito = 0x3ff;
2126
2127	dito_conf = (devslp >> PORT_DEVSLP_DITO_OFFSET) & 0x3FF;
2128
2129	/* device sleep was already enabled and same dito */
2130	if ((devslp & PORT_DEVSLP_ADSE) && (dito_conf == dito))
2131		return;
2132
2133	/* set DITO, MDAT, DETO and enable DevSlp, need to stop engine first */
2134	rc = hpriv->stop_engine(ap);
2135	if (rc)
2136		return;
2137
2138	/* Use the nominal value 10 ms if the read MDAT is zero,
2139	 * the nominal value of DETO is 20 ms.
2140	 */
2141	if (dev->devslp_timing[ATA_LOG_DEVSLP_VALID] &
2142	    ATA_LOG_DEVSLP_VALID_MASK) {
2143		mdat = dev->devslp_timing[ATA_LOG_DEVSLP_MDAT] &
2144		       ATA_LOG_DEVSLP_MDAT_MASK;
2145		if (!mdat)
2146			mdat = 10;
2147		deto = dev->devslp_timing[ATA_LOG_DEVSLP_DETO];
2148		if (!deto)
2149			deto = 20;
2150	} else {
2151		mdat = 10;
2152		deto = 20;
2153	}
2154
2155	/* Make dito, mdat, deto bits to 0s */
2156	devslp &= ~GENMASK_ULL(24, 2);
2157	devslp |= ((dito << PORT_DEVSLP_DITO_OFFSET) |
2158		   (mdat << PORT_DEVSLP_MDAT_OFFSET) |
2159		   (deto << PORT_DEVSLP_DETO_OFFSET) |
2160		   PORT_DEVSLP_ADSE);
2161	writel(devslp, port_mmio + PORT_DEVSLP);
2162
2163	hpriv->start_engine(ap);
2164
2165	/* enable device sleep feature for the drive */
2166	err_mask = ata_dev_set_feature(dev,
2167				       SETFEATURES_SATA_ENABLE,
2168				       SATA_DEVSLP);
2169	if (err_mask && err_mask != AC_ERR_DEV)
2170		ata_dev_warn(dev, "failed to enable DEVSLP\n");
2171}
2172
2173static void ahci_enable_fbs(struct ata_port *ap)
2174{
2175	struct ahci_host_priv *hpriv = ap->host->private_data;
2176	struct ahci_port_priv *pp = ap->private_data;
2177	void __iomem *port_mmio = ahci_port_base(ap);
2178	u32 fbs;
2179	int rc;
2180
2181	if (!pp->fbs_supported)
2182		return;
2183
2184	fbs = readl(port_mmio + PORT_FBS);
2185	if (fbs & PORT_FBS_EN) {
2186		pp->fbs_enabled = true;
2187		pp->fbs_last_dev = -1; /* initialization */
2188		return;
2189	}
2190
2191	rc = hpriv->stop_engine(ap);
2192	if (rc)
2193		return;
2194
2195	writel(fbs | PORT_FBS_EN, port_mmio + PORT_FBS);
2196	fbs = readl(port_mmio + PORT_FBS);
2197	if (fbs & PORT_FBS_EN) {
2198		dev_info(ap->host->dev, "FBS is enabled\n");
2199		pp->fbs_enabled = true;
2200		pp->fbs_last_dev = -1; /* initialization */
2201	} else
2202		dev_err(ap->host->dev, "Failed to enable FBS\n");
2203
2204	hpriv->start_engine(ap);
2205}
2206
2207static void ahci_disable_fbs(struct ata_port *ap)
2208{
2209	struct ahci_host_priv *hpriv = ap->host->private_data;
2210	struct ahci_port_priv *pp = ap->private_data;
2211	void __iomem *port_mmio = ahci_port_base(ap);
2212	u32 fbs;
2213	int rc;
2214
2215	if (!pp->fbs_supported)
2216		return;
2217
2218	fbs = readl(port_mmio + PORT_FBS);
2219	if ((fbs & PORT_FBS_EN) == 0) {
2220		pp->fbs_enabled = false;
2221		return;
2222	}
2223
2224	rc = hpriv->stop_engine(ap);
2225	if (rc)
2226		return;
2227
2228	writel(fbs & ~PORT_FBS_EN, port_mmio + PORT_FBS);
2229	fbs = readl(port_mmio + PORT_FBS);
2230	if (fbs & PORT_FBS_EN)
2231		dev_err(ap->host->dev, "Failed to disable FBS\n");
2232	else {
2233		dev_info(ap->host->dev, "FBS is disabled\n");
2234		pp->fbs_enabled = false;
2235	}
2236
2237	hpriv->start_engine(ap);
2238}
2239
2240static void ahci_pmp_attach(struct ata_port *ap)
2241{
2242	void __iomem *port_mmio = ahci_port_base(ap);
2243	struct ahci_port_priv *pp = ap->private_data;
2244	u32 cmd;
2245
2246	cmd = readl(port_mmio + PORT_CMD);
2247	cmd |= PORT_CMD_PMP;
2248	writel(cmd, port_mmio + PORT_CMD);
2249
2250	ahci_enable_fbs(ap);
2251
2252	pp->intr_mask |= PORT_IRQ_BAD_PMP;
2253
2254	/*
2255	 * We must not change the port interrupt mask register if the
2256	 * port is marked frozen, the value in pp->intr_mask will be
2257	 * restored later when the port is thawed.
2258	 *
2259	 * Note that during initialization, the port is marked as
2260	 * frozen since the irq handler is not yet registered.
2261	 */
2262	if (!(ap->pflags & ATA_PFLAG_FROZEN))
2263		writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
2264}
2265
2266static void ahci_pmp_detach(struct ata_port *ap)
2267{
2268	void __iomem *port_mmio = ahci_port_base(ap);
2269	struct ahci_port_priv *pp = ap->private_data;
2270	u32 cmd;
2271
2272	ahci_disable_fbs(ap);
2273
2274	cmd = readl(port_mmio + PORT_CMD);
2275	cmd &= ~PORT_CMD_PMP;
2276	writel(cmd, port_mmio + PORT_CMD);
2277
2278	pp->intr_mask &= ~PORT_IRQ_BAD_PMP;
2279
2280	/* see comment above in ahci_pmp_attach() */
2281	if (!(ap->pflags & ATA_PFLAG_FROZEN))
2282		writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
2283}
2284
2285int ahci_port_resume(struct ata_port *ap)
2286{
2287	ahci_rpm_get_port(ap);
2288
2289	ahci_power_up(ap);
2290	ahci_start_port(ap);
2291
2292	if (sata_pmp_attached(ap))
2293		ahci_pmp_attach(ap);
2294	else
2295		ahci_pmp_detach(ap);
2296
2297	return 0;
2298}
2299EXPORT_SYMBOL_GPL(ahci_port_resume);
2300
2301#ifdef CONFIG_PM
2302static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg)
2303{
2304	const char *emsg = NULL;
2305	int rc;
2306
2307	rc = ahci_deinit_port(ap, &emsg);
2308	if (rc == 0)
2309		ahci_power_down(ap);
2310	else {
2311		ata_port_err(ap, "%s (%d)\n", emsg, rc);
2312		ata_port_freeze(ap);
2313	}
2314
2315	ahci_rpm_put_port(ap);
2316	return rc;
2317}
2318#endif
2319
2320static int ahci_port_start(struct ata_port *ap)
2321{
2322	struct ahci_host_priv *hpriv = ap->host->private_data;
2323	struct device *dev = ap->host->dev;
2324	struct ahci_port_priv *pp;
2325	void *mem;
2326	dma_addr_t mem_dma;
2327	size_t dma_sz, rx_fis_sz;
2328
2329	pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
2330	if (!pp)
2331		return -ENOMEM;
2332
2333	if (ap->host->n_ports > 1) {
2334		pp->irq_desc = devm_kzalloc(dev, 8, GFP_KERNEL);
2335		if (!pp->irq_desc) {
2336			devm_kfree(dev, pp);
2337			return -ENOMEM;
2338		}
2339		snprintf(pp->irq_desc, 8,
2340			 "%s%d", dev_driver_string(dev), ap->port_no);
2341	}
2342
2343	/* check FBS capability */
2344	if ((hpriv->cap & HOST_CAP_FBS) && sata_pmp_supported(ap)) {
2345		void __iomem *port_mmio = ahci_port_base(ap);
2346		u32 cmd = readl(port_mmio + PORT_CMD);
2347		if (cmd & PORT_CMD_FBSCP)
2348			pp->fbs_supported = true;
2349		else if (hpriv->flags & AHCI_HFLAG_YES_FBS) {
2350			dev_info(dev, "port %d can do FBS, forcing FBSCP\n",
2351				 ap->port_no);
2352			pp->fbs_supported = true;
2353		} else
2354			dev_warn(dev, "port %d is not capable of FBS\n",
2355				 ap->port_no);
2356	}
2357
2358	if (pp->fbs_supported) {
2359		dma_sz = AHCI_PORT_PRIV_FBS_DMA_SZ;
2360		rx_fis_sz = AHCI_RX_FIS_SZ * 16;
2361	} else {
2362		dma_sz = AHCI_PORT_PRIV_DMA_SZ;
2363		rx_fis_sz = AHCI_RX_FIS_SZ;
2364	}
2365
2366	mem = dmam_alloc_coherent(dev, dma_sz, &mem_dma, GFP_KERNEL);
2367	if (!mem)
2368		return -ENOMEM;
2369
2370	/*
2371	 * First item in chunk of DMA memory: 32-slot command table,
2372	 * 32 bytes each in size
2373	 */
2374	pp->cmd_slot = mem;
2375	pp->cmd_slot_dma = mem_dma;
2376
2377	mem += AHCI_CMD_SLOT_SZ;
2378	mem_dma += AHCI_CMD_SLOT_SZ;
2379
2380	/*
2381	 * Second item: Received-FIS area
2382	 */
2383	pp->rx_fis = mem;
2384	pp->rx_fis_dma = mem_dma;
2385
2386	mem += rx_fis_sz;
2387	mem_dma += rx_fis_sz;
2388
2389	/*
2390	 * Third item: data area for storing a single command
2391	 * and its scatter-gather table
2392	 */
2393	pp->cmd_tbl = mem;
2394	pp->cmd_tbl_dma = mem_dma;
2395
2396	/*
2397	 * Save off initial list of interrupts to be enabled.
2398	 * This could be changed later
2399	 */
2400	pp->intr_mask = DEF_PORT_IRQ;
2401
2402	/*
2403	 * Switch to per-port locking in case each port has its own MSI vector.
2404	 */
2405	if (hpriv->flags & AHCI_HFLAG_MULTI_MSI) {
2406		spin_lock_init(&pp->lock);
2407		ap->lock = &pp->lock;
2408	}
2409
2410	ap->private_data = pp;
2411
2412	/* engage engines, captain */
2413	return ahci_port_resume(ap);
2414}
2415
2416static void ahci_port_stop(struct ata_port *ap)
2417{
2418	const char *emsg = NULL;
2419	struct ahci_host_priv *hpriv = ap->host->private_data;
2420	void __iomem *host_mmio = hpriv->mmio;
2421	int rc;
2422
2423	/* de-initialize port */
2424	rc = ahci_deinit_port(ap, &emsg);
2425	if (rc)
2426		ata_port_warn(ap, "%s (%d)\n", emsg, rc);
2427
2428	/*
2429	 * Clear GHC.IS to prevent stuck INTx after disabling MSI and
2430	 * re-enabling INTx.
2431	 */
2432	writel(1 << ap->port_no, host_mmio + HOST_IRQ_STAT);
2433
2434	ahci_rpm_put_port(ap);
2435}
2436
2437void ahci_print_info(struct ata_host *host, const char *scc_s)
2438{
2439	struct ahci_host_priv *hpriv = host->private_data;
2440	u32 vers, cap, cap2, impl, speed;
2441	const char *speed_s;
2442
2443	vers = hpriv->version;
2444	cap = hpriv->cap;
2445	cap2 = hpriv->cap2;
2446	impl = hpriv->port_map;
2447
2448	speed = (cap >> 20) & 0xf;
2449	if (speed == 1)
2450		speed_s = "1.5";
2451	else if (speed == 2)
2452		speed_s = "3";
2453	else if (speed == 3)
2454		speed_s = "6";
2455	else
2456		speed_s = "?";
2457
2458	dev_info(host->dev,
2459		"AHCI %02x%02x.%02x%02x "
2460		"%u slots %u ports %s Gbps 0x%x impl %s mode\n"
2461		,
2462
2463		(vers >> 24) & 0xff,
2464		(vers >> 16) & 0xff,
2465		(vers >> 8) & 0xff,
2466		vers & 0xff,
2467
2468		((cap >> 8) & 0x1f) + 1,
2469		(cap & 0x1f) + 1,
2470		speed_s,
2471		impl,
2472		scc_s);
2473
2474	dev_info(host->dev,
2475		"flags: "
2476		"%s%s%s%s%s%s%s"
2477		"%s%s%s%s%s%s%s"
2478		"%s%s%s%s%s%s%s"
2479		"%s%s\n"
2480		,
2481
2482		cap & HOST_CAP_64 ? "64bit " : "",
2483		cap & HOST_CAP_NCQ ? "ncq " : "",
2484		cap & HOST_CAP_SNTF ? "sntf " : "",
2485		cap & HOST_CAP_MPS ? "ilck " : "",
2486		cap & HOST_CAP_SSS ? "stag " : "",
2487		cap & HOST_CAP_ALPM ? "pm " : "",
2488		cap & HOST_CAP_LED ? "led " : "",
2489		cap & HOST_CAP_CLO ? "clo " : "",
2490		cap & HOST_CAP_ONLY ? "only " : "",
2491		cap & HOST_CAP_PMP ? "pmp " : "",
2492		cap & HOST_CAP_FBS ? "fbs " : "",
2493		cap & HOST_CAP_PIO_MULTI ? "pio " : "",
2494		cap & HOST_CAP_SSC ? "slum " : "",
2495		cap & HOST_CAP_PART ? "part " : "",
2496		cap & HOST_CAP_CCC ? "ccc " : "",
2497		cap & HOST_CAP_EMS ? "ems " : "",
2498		cap & HOST_CAP_SXS ? "sxs " : "",
2499		cap2 & HOST_CAP2_DESO ? "deso " : "",
2500		cap2 & HOST_CAP2_SADM ? "sadm " : "",
2501		cap2 & HOST_CAP2_SDS ? "sds " : "",
2502		cap2 & HOST_CAP2_APST ? "apst " : "",
2503		cap2 & HOST_CAP2_NVMHCI ? "nvmp " : "",
2504		cap2 & HOST_CAP2_BOH ? "boh " : ""
2505		);
2506}
2507EXPORT_SYMBOL_GPL(ahci_print_info);
2508
2509void ahci_set_em_messages(struct ahci_host_priv *hpriv,
2510			  struct ata_port_info *pi)
2511{
2512	u8 messages;
2513	void __iomem *mmio = hpriv->mmio;
2514	u32 em_loc = readl(mmio + HOST_EM_LOC);
2515	u32 em_ctl = readl(mmio + HOST_EM_CTL);
2516
2517	if (!ahci_em_messages || !(hpriv->cap & HOST_CAP_EMS))
2518		return;
2519
2520	messages = (em_ctl & EM_CTRL_MSG_TYPE) >> 16;
2521
2522	if (messages) {
2523		/* store em_loc */
2524		hpriv->em_loc = ((em_loc >> 16) * 4);
2525		hpriv->em_buf_sz = ((em_loc & 0xff) * 4);
2526		hpriv->em_msg_type = messages;
2527		pi->flags |= ATA_FLAG_EM;
2528		if (!(em_ctl & EM_CTL_ALHD))
2529			pi->flags |= ATA_FLAG_SW_ACTIVITY;
2530	}
2531}
2532EXPORT_SYMBOL_GPL(ahci_set_em_messages);
2533
2534static int ahci_host_activate_multi_irqs(struct ata_host *host,
2535					 struct scsi_host_template *sht)
2536{
2537	struct ahci_host_priv *hpriv = host->private_data;
2538	int i, rc;
2539
2540	rc = ata_host_start(host);
2541	if (rc)
2542		return rc;
2543	/*
2544	 * Requests IRQs according to AHCI-1.1 when multiple MSIs were
2545	 * allocated. That is one MSI per port, starting from @irq.
2546	 */
2547	for (i = 0; i < host->n_ports; i++) {
2548		struct ahci_port_priv *pp = host->ports[i]->private_data;
2549		int irq = hpriv->get_irq_vector(host, i);
2550
2551		/* Do not receive interrupts sent by dummy ports */
2552		if (!pp) {
2553			disable_irq(irq);
2554			continue;
2555		}
2556
2557		rc = devm_request_irq(host->dev, irq, ahci_multi_irqs_intr_hard,
2558				0, pp->irq_desc, host->ports[i]);
2559
2560		if (rc)
2561			return rc;
2562		ata_port_desc(host->ports[i], "irq %d", irq);
2563	}
2564
2565	return ata_host_register(host, sht);
2566}
2567
2568/**
2569 *	ahci_host_activate - start AHCI host, request IRQs and register it
2570 *	@host: target ATA host
2571 *	@sht: scsi_host_template to use when registering the host
2572 *
2573 *	LOCKING:
2574 *	Inherited from calling layer (may sleep).
2575 *
2576 *	RETURNS:
2577 *	0 on success, -errno otherwise.
2578 */
2579int ahci_host_activate(struct ata_host *host, struct scsi_host_template *sht)
2580{
2581	struct ahci_host_priv *hpriv = host->private_data;
2582	int irq = hpriv->irq;
2583	int rc;
2584
2585	if (hpriv->flags & AHCI_HFLAG_MULTI_MSI) {
2586		if (hpriv->irq_handler &&
2587		    hpriv->irq_handler != ahci_single_level_irq_intr)
2588			dev_warn(host->dev,
2589			         "both AHCI_HFLAG_MULTI_MSI flag set and custom irq handler implemented\n");
2590		if (!hpriv->get_irq_vector) {
2591			dev_err(host->dev,
2592				"AHCI_HFLAG_MULTI_MSI requires ->get_irq_vector!\n");
2593			return -EIO;
2594		}
2595
2596		rc = ahci_host_activate_multi_irqs(host, sht);
2597	} else {
2598		rc = ata_host_activate(host, irq, hpriv->irq_handler,
2599				       IRQF_SHARED, sht);
2600	}
2601
2602
2603	return rc;
2604}
2605EXPORT_SYMBOL_GPL(ahci_host_activate);
2606
2607MODULE_AUTHOR("Jeff Garzik");
2608MODULE_DESCRIPTION("Common AHCI SATA low-level routines");
2609MODULE_LICENSE("GPL");