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1/*
2 * Copyright 2014 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22
23/* amdgpu_amdkfd.h defines the private interface between amdgpu and amdkfd. */
24
25#ifndef AMDGPU_AMDKFD_H_INCLUDED
26#define AMDGPU_AMDKFD_H_INCLUDED
27
28#include <linux/types.h>
29#include <linux/mm.h>
30#include <linux/kthread.h>
31#include <linux/workqueue.h>
32#include <kgd_kfd_interface.h>
33#include <drm/ttm/ttm_execbuf_util.h>
34#include "amdgpu_sync.h"
35#include "amdgpu_vm.h"
36
37extern uint64_t amdgpu_amdkfd_total_mem_size;
38
39struct amdgpu_device;
40
41struct kfd_bo_va_list {
42 struct list_head bo_list;
43 struct amdgpu_bo_va *bo_va;
44 void *kgd_dev;
45 bool is_mapped;
46 uint64_t va;
47 uint64_t pte_flags;
48};
49
50struct kgd_mem {
51 struct mutex lock;
52 struct amdgpu_bo *bo;
53 struct list_head bo_va_list;
54 /* protected by amdkfd_process_info.lock */
55 struct ttm_validate_buffer validate_list;
56 struct ttm_validate_buffer resv_list;
57 uint32_t domain;
58 unsigned int mapped_to_gpu_memory;
59 uint64_t va;
60
61 uint32_t alloc_flags;
62
63 atomic_t invalid;
64 struct amdkfd_process_info *process_info;
65
66 struct amdgpu_sync sync;
67
68 bool aql_queue;
69 bool is_imported;
70};
71
72/* KFD Memory Eviction */
73struct amdgpu_amdkfd_fence {
74 struct dma_fence base;
75 struct mm_struct *mm;
76 spinlock_t lock;
77 char timeline_name[TASK_COMM_LEN];
78};
79
80struct amdgpu_kfd_dev {
81 struct kfd_dev *dev;
82 uint64_t vram_used;
83};
84
85enum kgd_engine_type {
86 KGD_ENGINE_PFP = 1,
87 KGD_ENGINE_ME,
88 KGD_ENGINE_CE,
89 KGD_ENGINE_MEC1,
90 KGD_ENGINE_MEC2,
91 KGD_ENGINE_RLC,
92 KGD_ENGINE_SDMA1,
93 KGD_ENGINE_SDMA2,
94 KGD_ENGINE_MAX
95};
96
97struct amdgpu_amdkfd_fence *amdgpu_amdkfd_fence_create(u64 context,
98 struct mm_struct *mm);
99bool amdkfd_fence_check_mm(struct dma_fence *f, struct mm_struct *mm);
100struct amdgpu_amdkfd_fence *to_amdgpu_amdkfd_fence(struct dma_fence *f);
101int amdgpu_amdkfd_remove_fence_on_pt_pd_bos(struct amdgpu_bo *bo);
102
103struct amdkfd_process_info {
104 /* List head of all VMs that belong to a KFD process */
105 struct list_head vm_list_head;
106 /* List head for all KFD BOs that belong to a KFD process. */
107 struct list_head kfd_bo_list;
108 /* List of userptr BOs that are valid or invalid */
109 struct list_head userptr_valid_list;
110 struct list_head userptr_inval_list;
111 /* Lock to protect kfd_bo_list */
112 struct mutex lock;
113
114 /* Number of VMs */
115 unsigned int n_vms;
116 /* Eviction Fence */
117 struct amdgpu_amdkfd_fence *eviction_fence;
118
119 /* MMU-notifier related fields */
120 atomic_t evicted_bos;
121 struct delayed_work restore_userptr_work;
122 struct pid *pid;
123};
124
125int amdgpu_amdkfd_init(void);
126void amdgpu_amdkfd_fini(void);
127
128void amdgpu_amdkfd_suspend(struct amdgpu_device *adev, bool run_pm);
129int amdgpu_amdkfd_resume(struct amdgpu_device *adev, bool run_pm);
130void amdgpu_amdkfd_interrupt(struct amdgpu_device *adev,
131 const void *ih_ring_entry);
132void amdgpu_amdkfd_device_probe(struct amdgpu_device *adev);
133void amdgpu_amdkfd_device_init(struct amdgpu_device *adev);
134void amdgpu_amdkfd_device_fini(struct amdgpu_device *adev);
135
136int amdgpu_amdkfd_evict_userptr(struct kgd_mem *mem, struct mm_struct *mm);
137int amdgpu_amdkfd_submit_ib(struct kgd_dev *kgd, enum kgd_engine_type engine,
138 uint32_t vmid, uint64_t gpu_addr,
139 uint32_t *ib_cmd, uint32_t ib_len);
140void amdgpu_amdkfd_set_compute_idle(struct kgd_dev *kgd, bool idle);
141bool amdgpu_amdkfd_have_atomics_support(struct kgd_dev *kgd);
142int amdgpu_amdkfd_flush_gpu_tlb_vmid(struct kgd_dev *kgd, uint16_t vmid);
143int amdgpu_amdkfd_flush_gpu_tlb_pasid(struct kgd_dev *kgd, uint16_t pasid);
144
145bool amdgpu_amdkfd_is_kfd_vmid(struct amdgpu_device *adev, u32 vmid);
146
147int amdgpu_amdkfd_pre_reset(struct amdgpu_device *adev);
148
149int amdgpu_amdkfd_post_reset(struct amdgpu_device *adev);
150
151void amdgpu_amdkfd_gpu_reset(struct kgd_dev *kgd);
152
153int amdgpu_queue_mask_bit_to_set_resource_bit(struct amdgpu_device *adev,
154 int queue_bit);
155
156/* Shared API */
157int amdgpu_amdkfd_alloc_gtt_mem(struct kgd_dev *kgd, size_t size,
158 void **mem_obj, uint64_t *gpu_addr,
159 void **cpu_ptr, bool mqd_gfx9);
160void amdgpu_amdkfd_free_gtt_mem(struct kgd_dev *kgd, void *mem_obj);
161int amdgpu_amdkfd_alloc_gws(struct kgd_dev *kgd, size_t size, void **mem_obj);
162void amdgpu_amdkfd_free_gws(struct kgd_dev *kgd, void *mem_obj);
163int amdgpu_amdkfd_add_gws_to_process(void *info, void *gws, struct kgd_mem **mem);
164int amdgpu_amdkfd_remove_gws_from_process(void *info, void *mem);
165uint32_t amdgpu_amdkfd_get_fw_version(struct kgd_dev *kgd,
166 enum kgd_engine_type type);
167void amdgpu_amdkfd_get_local_mem_info(struct kgd_dev *kgd,
168 struct kfd_local_mem_info *mem_info);
169uint64_t amdgpu_amdkfd_get_gpu_clock_counter(struct kgd_dev *kgd);
170
171uint32_t amdgpu_amdkfd_get_max_engine_clock_in_mhz(struct kgd_dev *kgd);
172void amdgpu_amdkfd_get_cu_info(struct kgd_dev *kgd, struct kfd_cu_info *cu_info);
173int amdgpu_amdkfd_get_dmabuf_info(struct kgd_dev *kgd, int dma_buf_fd,
174 struct kgd_dev **dmabuf_kgd,
175 uint64_t *bo_size, void *metadata_buffer,
176 size_t buffer_size, uint32_t *metadata_size,
177 uint32_t *flags);
178uint64_t amdgpu_amdkfd_get_vram_usage(struct kgd_dev *kgd);
179uint64_t amdgpu_amdkfd_get_hive_id(struct kgd_dev *kgd);
180uint64_t amdgpu_amdkfd_get_unique_id(struct kgd_dev *kgd);
181uint64_t amdgpu_amdkfd_get_mmio_remap_phys_addr(struct kgd_dev *kgd);
182uint32_t amdgpu_amdkfd_get_num_gws(struct kgd_dev *kgd);
183uint32_t amdgpu_amdkfd_get_asic_rev_id(struct kgd_dev *kgd);
184uint8_t amdgpu_amdkfd_get_xgmi_hops_count(struct kgd_dev *dst, struct kgd_dev *src);
185
186/* Read user wptr from a specified user address space with page fault
187 * disabled. The memory must be pinned and mapped to the hardware when
188 * this is called in hqd_load functions, so it should never fault in
189 * the first place. This resolves a circular lock dependency involving
190 * four locks, including the DQM lock and mmap_lock.
191 */
192#define read_user_wptr(mmptr, wptr, dst) \
193 ({ \
194 bool valid = false; \
195 if ((mmptr) && (wptr)) { \
196 pagefault_disable(); \
197 if ((mmptr) == current->mm) { \
198 valid = !get_user((dst), (wptr)); \
199 } else if (current->flags & PF_KTHREAD) { \
200 kthread_use_mm(mmptr); \
201 valid = !get_user((dst), (wptr)); \
202 kthread_unuse_mm(mmptr); \
203 } \
204 pagefault_enable(); \
205 } \
206 valid; \
207 })
208
209/* GPUVM API */
210int amdgpu_amdkfd_gpuvm_create_process_vm(struct kgd_dev *kgd, unsigned int pasid,
211 void **vm, void **process_info,
212 struct dma_fence **ef);
213int amdgpu_amdkfd_gpuvm_acquire_process_vm(struct kgd_dev *kgd,
214 struct file *filp, unsigned int pasid,
215 void **vm, void **process_info,
216 struct dma_fence **ef);
217void amdgpu_amdkfd_gpuvm_destroy_cb(struct amdgpu_device *adev,
218 struct amdgpu_vm *vm);
219void amdgpu_amdkfd_gpuvm_destroy_process_vm(struct kgd_dev *kgd, void *vm);
220void amdgpu_amdkfd_gpuvm_release_process_vm(struct kgd_dev *kgd, void *vm);
221uint64_t amdgpu_amdkfd_gpuvm_get_process_page_dir(void *vm);
222int amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu(
223 struct kgd_dev *kgd, uint64_t va, uint64_t size,
224 void *vm, struct kgd_mem **mem,
225 uint64_t *offset, uint32_t flags);
226int amdgpu_amdkfd_gpuvm_free_memory_of_gpu(
227 struct kgd_dev *kgd, struct kgd_mem *mem, uint64_t *size);
228int amdgpu_amdkfd_gpuvm_map_memory_to_gpu(
229 struct kgd_dev *kgd, struct kgd_mem *mem, void *vm);
230int amdgpu_amdkfd_gpuvm_unmap_memory_from_gpu(
231 struct kgd_dev *kgd, struct kgd_mem *mem, void *vm);
232int amdgpu_amdkfd_gpuvm_sync_memory(
233 struct kgd_dev *kgd, struct kgd_mem *mem, bool intr);
234int amdgpu_amdkfd_gpuvm_map_gtt_bo_to_kernel(struct kgd_dev *kgd,
235 struct kgd_mem *mem, void **kptr, uint64_t *size);
236int amdgpu_amdkfd_gpuvm_restore_process_bos(void *process_info,
237 struct dma_fence **ef);
238
239int amdgpu_amdkfd_gpuvm_get_vm_fault_info(struct kgd_dev *kgd,
240 struct kfd_vm_fault_info *info);
241
242int amdgpu_amdkfd_gpuvm_import_dmabuf(struct kgd_dev *kgd,
243 struct dma_buf *dmabuf,
244 uint64_t va, void *vm,
245 struct kgd_mem **mem, uint64_t *size,
246 uint64_t *mmap_offset);
247
248void amdgpu_amdkfd_gpuvm_init_mem_limits(void);
249void amdgpu_amdkfd_unreserve_memory_limit(struct amdgpu_bo *bo);
250
251int amdgpu_amdkfd_get_tile_config(struct kgd_dev *kgd,
252 struct tile_config *config);
253
254/* KGD2KFD callbacks */
255int kgd2kfd_init(void);
256void kgd2kfd_exit(void);
257struct kfd_dev *kgd2kfd_probe(struct kgd_dev *kgd, struct pci_dev *pdev,
258 unsigned int asic_type, bool vf);
259bool kgd2kfd_device_init(struct kfd_dev *kfd,
260 struct drm_device *ddev,
261 const struct kgd2kfd_shared_resources *gpu_resources);
262void kgd2kfd_device_exit(struct kfd_dev *kfd);
263void kgd2kfd_suspend(struct kfd_dev *kfd, bool run_pm);
264int kgd2kfd_resume(struct kfd_dev *kfd, bool run_pm);
265int kgd2kfd_pre_reset(struct kfd_dev *kfd);
266int kgd2kfd_post_reset(struct kfd_dev *kfd);
267void kgd2kfd_interrupt(struct kfd_dev *kfd, const void *ih_ring_entry);
268int kgd2kfd_quiesce_mm(struct mm_struct *mm);
269int kgd2kfd_resume_mm(struct mm_struct *mm);
270int kgd2kfd_schedule_evict_and_restore_process(struct mm_struct *mm,
271 struct dma_fence *fence);
272void kgd2kfd_set_sram_ecc_flag(struct kfd_dev *kfd);
273
274#endif /* AMDGPU_AMDKFD_H_INCLUDED */
1/*
2 * Copyright 2014 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22
23/* amdgpu_amdkfd.h defines the private interface between amdgpu and amdkfd. */
24
25#ifndef AMDGPU_AMDKFD_H_INCLUDED
26#define AMDGPU_AMDKFD_H_INCLUDED
27
28#include <linux/types.h>
29#include <linux/mm.h>
30#include <linux/kthread.h>
31#include <linux/workqueue.h>
32#include <kgd_kfd_interface.h>
33#include <drm/ttm/ttm_execbuf_util.h>
34#include "amdgpu_sync.h"
35#include "amdgpu_vm.h"
36
37extern uint64_t amdgpu_amdkfd_total_mem_size;
38
39enum TLB_FLUSH_TYPE {
40 TLB_FLUSH_LEGACY = 0,
41 TLB_FLUSH_LIGHTWEIGHT,
42 TLB_FLUSH_HEAVYWEIGHT
43};
44
45struct amdgpu_device;
46
47enum kfd_mem_attachment_type {
48 KFD_MEM_ATT_SHARED, /* Share kgd_mem->bo or another attachment's */
49 KFD_MEM_ATT_USERPTR, /* SG bo to DMA map pages from a userptr bo */
50 KFD_MEM_ATT_DMABUF, /* DMAbuf to DMA map TTM BOs */
51};
52
53struct kfd_mem_attachment {
54 struct list_head list;
55 enum kfd_mem_attachment_type type;
56 bool is_mapped;
57 struct amdgpu_bo_va *bo_va;
58 struct amdgpu_device *adev;
59 uint64_t va;
60 uint64_t pte_flags;
61};
62
63struct kgd_mem {
64 struct mutex lock;
65 struct amdgpu_bo *bo;
66 struct dma_buf *dmabuf;
67 struct list_head attachments;
68 /* protected by amdkfd_process_info.lock */
69 struct ttm_validate_buffer validate_list;
70 struct ttm_validate_buffer resv_list;
71 uint32_t domain;
72 unsigned int mapped_to_gpu_memory;
73 uint64_t va;
74
75 uint32_t alloc_flags;
76
77 atomic_t invalid;
78 struct amdkfd_process_info *process_info;
79
80 struct amdgpu_sync sync;
81
82 bool aql_queue;
83 bool is_imported;
84};
85
86/* KFD Memory Eviction */
87struct amdgpu_amdkfd_fence {
88 struct dma_fence base;
89 struct mm_struct *mm;
90 spinlock_t lock;
91 char timeline_name[TASK_COMM_LEN];
92 struct svm_range_bo *svm_bo;
93};
94
95struct amdgpu_kfd_dev {
96 struct kfd_dev *dev;
97 uint64_t vram_used;
98 bool init_complete;
99};
100
101enum kgd_engine_type {
102 KGD_ENGINE_PFP = 1,
103 KGD_ENGINE_ME,
104 KGD_ENGINE_CE,
105 KGD_ENGINE_MEC1,
106 KGD_ENGINE_MEC2,
107 KGD_ENGINE_RLC,
108 KGD_ENGINE_SDMA1,
109 KGD_ENGINE_SDMA2,
110 KGD_ENGINE_MAX
111};
112
113
114struct amdkfd_process_info {
115 /* List head of all VMs that belong to a KFD process */
116 struct list_head vm_list_head;
117 /* List head for all KFD BOs that belong to a KFD process. */
118 struct list_head kfd_bo_list;
119 /* List of userptr BOs that are valid or invalid */
120 struct list_head userptr_valid_list;
121 struct list_head userptr_inval_list;
122 /* Lock to protect kfd_bo_list */
123 struct mutex lock;
124
125 /* Number of VMs */
126 unsigned int n_vms;
127 /* Eviction Fence */
128 struct amdgpu_amdkfd_fence *eviction_fence;
129
130 /* MMU-notifier related fields */
131 atomic_t evicted_bos;
132 struct delayed_work restore_userptr_work;
133 struct pid *pid;
134};
135
136int amdgpu_amdkfd_init(void);
137void amdgpu_amdkfd_fini(void);
138
139void amdgpu_amdkfd_suspend(struct amdgpu_device *adev, bool run_pm);
140int amdgpu_amdkfd_resume_iommu(struct amdgpu_device *adev);
141int amdgpu_amdkfd_resume(struct amdgpu_device *adev, bool run_pm);
142void amdgpu_amdkfd_interrupt(struct amdgpu_device *adev,
143 const void *ih_ring_entry);
144void amdgpu_amdkfd_device_probe(struct amdgpu_device *adev);
145void amdgpu_amdkfd_device_init(struct amdgpu_device *adev);
146void amdgpu_amdkfd_device_fini_sw(struct amdgpu_device *adev);
147int amdgpu_amdkfd_submit_ib(struct kgd_dev *kgd, enum kgd_engine_type engine,
148 uint32_t vmid, uint64_t gpu_addr,
149 uint32_t *ib_cmd, uint32_t ib_len);
150void amdgpu_amdkfd_set_compute_idle(struct kgd_dev *kgd, bool idle);
151bool amdgpu_amdkfd_have_atomics_support(struct kgd_dev *kgd);
152int amdgpu_amdkfd_flush_gpu_tlb_vmid(struct kgd_dev *kgd, uint16_t vmid);
153int amdgpu_amdkfd_flush_gpu_tlb_pasid(struct kgd_dev *kgd, uint16_t pasid,
154 enum TLB_FLUSH_TYPE flush_type);
155
156bool amdgpu_amdkfd_is_kfd_vmid(struct amdgpu_device *adev, u32 vmid);
157
158int amdgpu_amdkfd_pre_reset(struct amdgpu_device *adev);
159
160int amdgpu_amdkfd_post_reset(struct amdgpu_device *adev);
161
162void amdgpu_amdkfd_gpu_reset(struct kgd_dev *kgd);
163
164int amdgpu_queue_mask_bit_to_set_resource_bit(struct amdgpu_device *adev,
165 int queue_bit);
166
167struct amdgpu_amdkfd_fence *amdgpu_amdkfd_fence_create(u64 context,
168 struct mm_struct *mm,
169 struct svm_range_bo *svm_bo);
170#if IS_ENABLED(CONFIG_HSA_AMD)
171bool amdkfd_fence_check_mm(struct dma_fence *f, struct mm_struct *mm);
172struct amdgpu_amdkfd_fence *to_amdgpu_amdkfd_fence(struct dma_fence *f);
173int amdgpu_amdkfd_remove_fence_on_pt_pd_bos(struct amdgpu_bo *bo);
174int amdgpu_amdkfd_evict_userptr(struct kgd_mem *mem, struct mm_struct *mm);
175#else
176static inline
177bool amdkfd_fence_check_mm(struct dma_fence *f, struct mm_struct *mm)
178{
179 return false;
180}
181
182static inline
183struct amdgpu_amdkfd_fence *to_amdgpu_amdkfd_fence(struct dma_fence *f)
184{
185 return NULL;
186}
187
188static inline
189int amdgpu_amdkfd_remove_fence_on_pt_pd_bos(struct amdgpu_bo *bo)
190{
191 return 0;
192}
193
194static inline
195int amdgpu_amdkfd_evict_userptr(struct kgd_mem *mem, struct mm_struct *mm)
196{
197 return 0;
198}
199#endif
200/* Shared API */
201int amdgpu_amdkfd_alloc_gtt_mem(struct kgd_dev *kgd, size_t size,
202 void **mem_obj, uint64_t *gpu_addr,
203 void **cpu_ptr, bool mqd_gfx9);
204void amdgpu_amdkfd_free_gtt_mem(struct kgd_dev *kgd, void *mem_obj);
205int amdgpu_amdkfd_alloc_gws(struct kgd_dev *kgd, size_t size, void **mem_obj);
206void amdgpu_amdkfd_free_gws(struct kgd_dev *kgd, void *mem_obj);
207int amdgpu_amdkfd_add_gws_to_process(void *info, void *gws, struct kgd_mem **mem);
208int amdgpu_amdkfd_remove_gws_from_process(void *info, void *mem);
209uint32_t amdgpu_amdkfd_get_fw_version(struct kgd_dev *kgd,
210 enum kgd_engine_type type);
211void amdgpu_amdkfd_get_local_mem_info(struct kgd_dev *kgd,
212 struct kfd_local_mem_info *mem_info);
213uint64_t amdgpu_amdkfd_get_gpu_clock_counter(struct kgd_dev *kgd);
214
215uint32_t amdgpu_amdkfd_get_max_engine_clock_in_mhz(struct kgd_dev *kgd);
216void amdgpu_amdkfd_get_cu_info(struct kgd_dev *kgd, struct kfd_cu_info *cu_info);
217int amdgpu_amdkfd_get_dmabuf_info(struct kgd_dev *kgd, int dma_buf_fd,
218 struct kgd_dev **dmabuf_kgd,
219 uint64_t *bo_size, void *metadata_buffer,
220 size_t buffer_size, uint32_t *metadata_size,
221 uint32_t *flags);
222uint64_t amdgpu_amdkfd_get_vram_usage(struct kgd_dev *kgd);
223uint64_t amdgpu_amdkfd_get_hive_id(struct kgd_dev *kgd);
224uint64_t amdgpu_amdkfd_get_unique_id(struct kgd_dev *kgd);
225uint64_t amdgpu_amdkfd_get_mmio_remap_phys_addr(struct kgd_dev *kgd);
226uint32_t amdgpu_amdkfd_get_num_gws(struct kgd_dev *kgd);
227uint32_t amdgpu_amdkfd_get_asic_rev_id(struct kgd_dev *kgd);
228int amdgpu_amdkfd_get_noretry(struct kgd_dev *kgd);
229uint8_t amdgpu_amdkfd_get_xgmi_hops_count(struct kgd_dev *dst, struct kgd_dev *src);
230
231/* Read user wptr from a specified user address space with page fault
232 * disabled. The memory must be pinned and mapped to the hardware when
233 * this is called in hqd_load functions, so it should never fault in
234 * the first place. This resolves a circular lock dependency involving
235 * four locks, including the DQM lock and mmap_lock.
236 */
237#define read_user_wptr(mmptr, wptr, dst) \
238 ({ \
239 bool valid = false; \
240 if ((mmptr) && (wptr)) { \
241 pagefault_disable(); \
242 if ((mmptr) == current->mm) { \
243 valid = !get_user((dst), (wptr)); \
244 } else if (current->flags & PF_KTHREAD) { \
245 kthread_use_mm(mmptr); \
246 valid = !get_user((dst), (wptr)); \
247 kthread_unuse_mm(mmptr); \
248 } \
249 pagefault_enable(); \
250 } \
251 valid; \
252 })
253
254/* GPUVM API */
255#define drm_priv_to_vm(drm_priv) \
256 (&((struct amdgpu_fpriv *) \
257 ((struct drm_file *)(drm_priv))->driver_priv)->vm)
258
259int amdgpu_amdkfd_gpuvm_acquire_process_vm(struct kgd_dev *kgd,
260 struct file *filp, u32 pasid,
261 void **process_info,
262 struct dma_fence **ef);
263void amdgpu_amdkfd_gpuvm_release_process_vm(struct kgd_dev *kgd, void *drm_priv);
264uint64_t amdgpu_amdkfd_gpuvm_get_process_page_dir(void *drm_priv);
265int amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu(
266 struct kgd_dev *kgd, uint64_t va, uint64_t size,
267 void *drm_priv, struct kgd_mem **mem,
268 uint64_t *offset, uint32_t flags);
269int amdgpu_amdkfd_gpuvm_free_memory_of_gpu(
270 struct kgd_dev *kgd, struct kgd_mem *mem, void *drm_priv,
271 uint64_t *size);
272int amdgpu_amdkfd_gpuvm_map_memory_to_gpu(
273 struct kgd_dev *kgd, struct kgd_mem *mem, void *drm_priv);
274int amdgpu_amdkfd_gpuvm_unmap_memory_from_gpu(
275 struct kgd_dev *kgd, struct kgd_mem *mem, void *drm_priv);
276int amdgpu_amdkfd_gpuvm_sync_memory(
277 struct kgd_dev *kgd, struct kgd_mem *mem, bool intr);
278int amdgpu_amdkfd_gpuvm_map_gtt_bo_to_kernel(struct kgd_dev *kgd,
279 struct kgd_mem *mem, void **kptr, uint64_t *size);
280int amdgpu_amdkfd_gpuvm_restore_process_bos(void *process_info,
281 struct dma_fence **ef);
282int amdgpu_amdkfd_gpuvm_get_vm_fault_info(struct kgd_dev *kgd,
283 struct kfd_vm_fault_info *info);
284int amdgpu_amdkfd_gpuvm_import_dmabuf(struct kgd_dev *kgd,
285 struct dma_buf *dmabuf,
286 uint64_t va, void *drm_priv,
287 struct kgd_mem **mem, uint64_t *size,
288 uint64_t *mmap_offset);
289int amdgpu_amdkfd_get_tile_config(struct kgd_dev *kgd,
290 struct tile_config *config);
291#if IS_ENABLED(CONFIG_HSA_AMD)
292void amdgpu_amdkfd_gpuvm_init_mem_limits(void);
293void amdgpu_amdkfd_gpuvm_destroy_cb(struct amdgpu_device *adev,
294 struct amdgpu_vm *vm);
295void amdgpu_amdkfd_unreserve_memory_limit(struct amdgpu_bo *bo);
296void amdgpu_amdkfd_reserve_system_mem(uint64_t size);
297#else
298static inline
299void amdgpu_amdkfd_gpuvm_init_mem_limits(void)
300{
301}
302
303static inline
304void amdgpu_amdkfd_gpuvm_destroy_cb(struct amdgpu_device *adev,
305 struct amdgpu_vm *vm)
306{
307}
308
309static inline
310void amdgpu_amdkfd_unreserve_memory_limit(struct amdgpu_bo *bo)
311{
312}
313#endif
314/* KGD2KFD callbacks */
315int kgd2kfd_quiesce_mm(struct mm_struct *mm);
316int kgd2kfd_resume_mm(struct mm_struct *mm);
317int kgd2kfd_schedule_evict_and_restore_process(struct mm_struct *mm,
318 struct dma_fence *fence);
319#if IS_ENABLED(CONFIG_HSA_AMD)
320int kgd2kfd_init(void);
321void kgd2kfd_exit(void);
322struct kfd_dev *kgd2kfd_probe(struct kgd_dev *kgd, struct pci_dev *pdev,
323 unsigned int asic_type, bool vf);
324bool kgd2kfd_device_init(struct kfd_dev *kfd,
325 struct drm_device *ddev,
326 const struct kgd2kfd_shared_resources *gpu_resources);
327void kgd2kfd_device_exit(struct kfd_dev *kfd);
328void kgd2kfd_suspend(struct kfd_dev *kfd, bool run_pm);
329int kgd2kfd_resume_iommu(struct kfd_dev *kfd);
330int kgd2kfd_resume(struct kfd_dev *kfd, bool run_pm);
331int kgd2kfd_pre_reset(struct kfd_dev *kfd);
332int kgd2kfd_post_reset(struct kfd_dev *kfd);
333void kgd2kfd_interrupt(struct kfd_dev *kfd, const void *ih_ring_entry);
334void kgd2kfd_set_sram_ecc_flag(struct kfd_dev *kfd);
335void kgd2kfd_smi_event_throttle(struct kfd_dev *kfd, uint32_t throttle_bitmask);
336#else
337static inline int kgd2kfd_init(void)
338{
339 return -ENOENT;
340}
341
342static inline void kgd2kfd_exit(void)
343{
344}
345
346static inline
347struct kfd_dev *kgd2kfd_probe(struct kgd_dev *kgd, struct pci_dev *pdev,
348 unsigned int asic_type, bool vf)
349{
350 return NULL;
351}
352
353static inline
354bool kgd2kfd_device_init(struct kfd_dev *kfd, struct drm_device *ddev,
355 const struct kgd2kfd_shared_resources *gpu_resources)
356{
357 return false;
358}
359
360static inline void kgd2kfd_device_exit(struct kfd_dev *kfd)
361{
362}
363
364static inline void kgd2kfd_suspend(struct kfd_dev *kfd, bool run_pm)
365{
366}
367
368static int __maybe_unused kgd2kfd_resume_iommu(struct kfd_dev *kfd)
369{
370 return 0;
371}
372
373static inline int kgd2kfd_resume(struct kfd_dev *kfd, bool run_pm)
374{
375 return 0;
376}
377
378static inline int kgd2kfd_pre_reset(struct kfd_dev *kfd)
379{
380 return 0;
381}
382
383static inline int kgd2kfd_post_reset(struct kfd_dev *kfd)
384{
385 return 0;
386}
387
388static inline
389void kgd2kfd_interrupt(struct kfd_dev *kfd, const void *ih_ring_entry)
390{
391}
392
393static inline
394void kgd2kfd_set_sram_ecc_flag(struct kfd_dev *kfd)
395{
396}
397
398static inline
399void kgd2kfd_smi_event_throttle(struct kfd_dev *kfd, uint32_t throttle_bitmask)
400{
401}
402#endif
403#endif /* AMDGPU_AMDKFD_H_INCLUDED */