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1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * Copyright (c) 2012 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * Copyright (C) 2010 Samsung Electronics Co. Ltd.
7 * Jaswinder Singh <jassi.brar@samsung.com>
8 */
9
10#include <linux/debugfs.h>
11#include <linux/kernel.h>
12#include <linux/io.h>
13#include <linux/init.h>
14#include <linux/slab.h>
15#include <linux/module.h>
16#include <linux/string.h>
17#include <linux/delay.h>
18#include <linux/interrupt.h>
19#include <linux/dma-mapping.h>
20#include <linux/dmaengine.h>
21#include <linux/amba/bus.h>
22#include <linux/scatterlist.h>
23#include <linux/of.h>
24#include <linux/of_dma.h>
25#include <linux/err.h>
26#include <linux/pm_runtime.h>
27#include <linux/bug.h>
28#include <linux/reset.h>
29
30#include "dmaengine.h"
31#define PL330_MAX_CHAN 8
32#define PL330_MAX_IRQS 32
33#define PL330_MAX_PERI 32
34#define PL330_MAX_BURST 16
35
36#define PL330_QUIRK_BROKEN_NO_FLUSHP BIT(0)
37#define PL330_QUIRK_PERIPH_BURST BIT(1)
38
39enum pl330_cachectrl {
40 CCTRL0, /* Noncacheable and nonbufferable */
41 CCTRL1, /* Bufferable only */
42 CCTRL2, /* Cacheable, but do not allocate */
43 CCTRL3, /* Cacheable and bufferable, but do not allocate */
44 INVALID1, /* AWCACHE = 0x1000 */
45 INVALID2,
46 CCTRL6, /* Cacheable write-through, allocate on writes only */
47 CCTRL7, /* Cacheable write-back, allocate on writes only */
48};
49
50enum pl330_byteswap {
51 SWAP_NO,
52 SWAP_2,
53 SWAP_4,
54 SWAP_8,
55 SWAP_16,
56};
57
58/* Register and Bit field Definitions */
59#define DS 0x0
60#define DS_ST_STOP 0x0
61#define DS_ST_EXEC 0x1
62#define DS_ST_CMISS 0x2
63#define DS_ST_UPDTPC 0x3
64#define DS_ST_WFE 0x4
65#define DS_ST_ATBRR 0x5
66#define DS_ST_QBUSY 0x6
67#define DS_ST_WFP 0x7
68#define DS_ST_KILL 0x8
69#define DS_ST_CMPLT 0x9
70#define DS_ST_FLTCMP 0xe
71#define DS_ST_FAULT 0xf
72
73#define DPC 0x4
74#define INTEN 0x20
75#define ES 0x24
76#define INTSTATUS 0x28
77#define INTCLR 0x2c
78#define FSM 0x30
79#define FSC 0x34
80#define FTM 0x38
81
82#define _FTC 0x40
83#define FTC(n) (_FTC + (n)*0x4)
84
85#define _CS 0x100
86#define CS(n) (_CS + (n)*0x8)
87#define CS_CNS (1 << 21)
88
89#define _CPC 0x104
90#define CPC(n) (_CPC + (n)*0x8)
91
92#define _SA 0x400
93#define SA(n) (_SA + (n)*0x20)
94
95#define _DA 0x404
96#define DA(n) (_DA + (n)*0x20)
97
98#define _CC 0x408
99#define CC(n) (_CC + (n)*0x20)
100
101#define CC_SRCINC (1 << 0)
102#define CC_DSTINC (1 << 14)
103#define CC_SRCPRI (1 << 8)
104#define CC_DSTPRI (1 << 22)
105#define CC_SRCNS (1 << 9)
106#define CC_DSTNS (1 << 23)
107#define CC_SRCIA (1 << 10)
108#define CC_DSTIA (1 << 24)
109#define CC_SRCBRSTLEN_SHFT 4
110#define CC_DSTBRSTLEN_SHFT 18
111#define CC_SRCBRSTSIZE_SHFT 1
112#define CC_DSTBRSTSIZE_SHFT 15
113#define CC_SRCCCTRL_SHFT 11
114#define CC_SRCCCTRL_MASK 0x7
115#define CC_DSTCCTRL_SHFT 25
116#define CC_DRCCCTRL_MASK 0x7
117#define CC_SWAP_SHFT 28
118
119#define _LC0 0x40c
120#define LC0(n) (_LC0 + (n)*0x20)
121
122#define _LC1 0x410
123#define LC1(n) (_LC1 + (n)*0x20)
124
125#define DBGSTATUS 0xd00
126#define DBG_BUSY (1 << 0)
127
128#define DBGCMD 0xd04
129#define DBGINST0 0xd08
130#define DBGINST1 0xd0c
131
132#define CR0 0xe00
133#define CR1 0xe04
134#define CR2 0xe08
135#define CR3 0xe0c
136#define CR4 0xe10
137#define CRD 0xe14
138
139#define PERIPH_ID 0xfe0
140#define PERIPH_REV_SHIFT 20
141#define PERIPH_REV_MASK 0xf
142#define PERIPH_REV_R0P0 0
143#define PERIPH_REV_R1P0 1
144#define PERIPH_REV_R1P1 2
145
146#define CR0_PERIPH_REQ_SET (1 << 0)
147#define CR0_BOOT_EN_SET (1 << 1)
148#define CR0_BOOT_MAN_NS (1 << 2)
149#define CR0_NUM_CHANS_SHIFT 4
150#define CR0_NUM_CHANS_MASK 0x7
151#define CR0_NUM_PERIPH_SHIFT 12
152#define CR0_NUM_PERIPH_MASK 0x1f
153#define CR0_NUM_EVENTS_SHIFT 17
154#define CR0_NUM_EVENTS_MASK 0x1f
155
156#define CR1_ICACHE_LEN_SHIFT 0
157#define CR1_ICACHE_LEN_MASK 0x7
158#define CR1_NUM_ICACHELINES_SHIFT 4
159#define CR1_NUM_ICACHELINES_MASK 0xf
160
161#define CRD_DATA_WIDTH_SHIFT 0
162#define CRD_DATA_WIDTH_MASK 0x7
163#define CRD_WR_CAP_SHIFT 4
164#define CRD_WR_CAP_MASK 0x7
165#define CRD_WR_Q_DEP_SHIFT 8
166#define CRD_WR_Q_DEP_MASK 0xf
167#define CRD_RD_CAP_SHIFT 12
168#define CRD_RD_CAP_MASK 0x7
169#define CRD_RD_Q_DEP_SHIFT 16
170#define CRD_RD_Q_DEP_MASK 0xf
171#define CRD_DATA_BUFF_SHIFT 20
172#define CRD_DATA_BUFF_MASK 0x3ff
173
174#define PART 0x330
175#define DESIGNER 0x41
176#define REVISION 0x0
177#define INTEG_CFG 0x0
178#define PERIPH_ID_VAL ((PART << 0) | (DESIGNER << 12))
179
180#define PL330_STATE_STOPPED (1 << 0)
181#define PL330_STATE_EXECUTING (1 << 1)
182#define PL330_STATE_WFE (1 << 2)
183#define PL330_STATE_FAULTING (1 << 3)
184#define PL330_STATE_COMPLETING (1 << 4)
185#define PL330_STATE_WFP (1 << 5)
186#define PL330_STATE_KILLING (1 << 6)
187#define PL330_STATE_FAULT_COMPLETING (1 << 7)
188#define PL330_STATE_CACHEMISS (1 << 8)
189#define PL330_STATE_UPDTPC (1 << 9)
190#define PL330_STATE_ATBARRIER (1 << 10)
191#define PL330_STATE_QUEUEBUSY (1 << 11)
192#define PL330_STATE_INVALID (1 << 15)
193
194#define PL330_STABLE_STATES (PL330_STATE_STOPPED | PL330_STATE_EXECUTING \
195 | PL330_STATE_WFE | PL330_STATE_FAULTING)
196
197#define CMD_DMAADDH 0x54
198#define CMD_DMAEND 0x00
199#define CMD_DMAFLUSHP 0x35
200#define CMD_DMAGO 0xa0
201#define CMD_DMALD 0x04
202#define CMD_DMALDP 0x25
203#define CMD_DMALP 0x20
204#define CMD_DMALPEND 0x28
205#define CMD_DMAKILL 0x01
206#define CMD_DMAMOV 0xbc
207#define CMD_DMANOP 0x18
208#define CMD_DMARMB 0x12
209#define CMD_DMASEV 0x34
210#define CMD_DMAST 0x08
211#define CMD_DMASTP 0x29
212#define CMD_DMASTZ 0x0c
213#define CMD_DMAWFE 0x36
214#define CMD_DMAWFP 0x30
215#define CMD_DMAWMB 0x13
216
217#define SZ_DMAADDH 3
218#define SZ_DMAEND 1
219#define SZ_DMAFLUSHP 2
220#define SZ_DMALD 1
221#define SZ_DMALDP 2
222#define SZ_DMALP 2
223#define SZ_DMALPEND 2
224#define SZ_DMAKILL 1
225#define SZ_DMAMOV 6
226#define SZ_DMANOP 1
227#define SZ_DMARMB 1
228#define SZ_DMASEV 2
229#define SZ_DMAST 1
230#define SZ_DMASTP 2
231#define SZ_DMASTZ 1
232#define SZ_DMAWFE 2
233#define SZ_DMAWFP 2
234#define SZ_DMAWMB 1
235#define SZ_DMAGO 6
236
237#define BRST_LEN(ccr) ((((ccr) >> CC_SRCBRSTLEN_SHFT) & 0xf) + 1)
238#define BRST_SIZE(ccr) (1 << (((ccr) >> CC_SRCBRSTSIZE_SHFT) & 0x7))
239
240#define BYTE_TO_BURST(b, ccr) ((b) / BRST_SIZE(ccr) / BRST_LEN(ccr))
241#define BURST_TO_BYTE(c, ccr) ((c) * BRST_SIZE(ccr) * BRST_LEN(ccr))
242
243/*
244 * With 256 bytes, we can do more than 2.5MB and 5MB xfers per req
245 * at 1byte/burst for P<->M and M<->M respectively.
246 * For typical scenario, at 1word/burst, 10MB and 20MB xfers per req
247 * should be enough for P<->M and M<->M respectively.
248 */
249#define MCODE_BUFF_PER_REQ 256
250
251/* Use this _only_ to wait on transient states */
252#define UNTIL(t, s) while (!(_state(t) & (s))) cpu_relax();
253
254#ifdef PL330_DEBUG_MCGEN
255static unsigned cmd_line;
256#define PL330_DBGCMD_DUMP(off, x...) do { \
257 printk("%x:", cmd_line); \
258 printk(x); \
259 cmd_line += off; \
260 } while (0)
261#define PL330_DBGMC_START(addr) (cmd_line = addr)
262#else
263#define PL330_DBGCMD_DUMP(off, x...) do {} while (0)
264#define PL330_DBGMC_START(addr) do {} while (0)
265#endif
266
267/* The number of default descriptors */
268
269#define NR_DEFAULT_DESC 16
270
271/* Delay for runtime PM autosuspend, ms */
272#define PL330_AUTOSUSPEND_DELAY 20
273
274/* Populated by the PL330 core driver for DMA API driver's info */
275struct pl330_config {
276 u32 periph_id;
277#define DMAC_MODE_NS (1 << 0)
278 unsigned int mode;
279 unsigned int data_bus_width:10; /* In number of bits */
280 unsigned int data_buf_dep:11;
281 unsigned int num_chan:4;
282 unsigned int num_peri:6;
283 u32 peri_ns;
284 unsigned int num_events:6;
285 u32 irq_ns;
286};
287
288/*
289 * Request Configuration.
290 * The PL330 core does not modify this and uses the last
291 * working configuration if the request doesn't provide any.
292 *
293 * The Client may want to provide this info only for the
294 * first request and a request with new settings.
295 */
296struct pl330_reqcfg {
297 /* Address Incrementing */
298 unsigned dst_inc:1;
299 unsigned src_inc:1;
300
301 /*
302 * For now, the SRC & DST protection levels
303 * and burst size/length are assumed same.
304 */
305 bool nonsecure;
306 bool privileged;
307 bool insnaccess;
308 unsigned brst_len:5;
309 unsigned brst_size:3; /* in power of 2 */
310
311 enum pl330_cachectrl dcctl;
312 enum pl330_cachectrl scctl;
313 enum pl330_byteswap swap;
314 struct pl330_config *pcfg;
315};
316
317/*
318 * One cycle of DMAC operation.
319 * There may be more than one xfer in a request.
320 */
321struct pl330_xfer {
322 u32 src_addr;
323 u32 dst_addr;
324 /* Size to xfer */
325 u32 bytes;
326};
327
328/* The xfer callbacks are made with one of these arguments. */
329enum pl330_op_err {
330 /* The all xfers in the request were success. */
331 PL330_ERR_NONE,
332 /* If req aborted due to global error. */
333 PL330_ERR_ABORT,
334 /* If req failed due to problem with Channel. */
335 PL330_ERR_FAIL,
336};
337
338enum dmamov_dst {
339 SAR = 0,
340 CCR,
341 DAR,
342};
343
344enum pl330_dst {
345 SRC = 0,
346 DST,
347};
348
349enum pl330_cond {
350 SINGLE,
351 BURST,
352 ALWAYS,
353};
354
355struct dma_pl330_desc;
356
357struct _pl330_req {
358 u32 mc_bus;
359 void *mc_cpu;
360 struct dma_pl330_desc *desc;
361};
362
363/* ToBeDone for tasklet */
364struct _pl330_tbd {
365 bool reset_dmac;
366 bool reset_mngr;
367 u8 reset_chan;
368};
369
370/* A DMAC Thread */
371struct pl330_thread {
372 u8 id;
373 int ev;
374 /* If the channel is not yet acquired by any client */
375 bool free;
376 /* Parent DMAC */
377 struct pl330_dmac *dmac;
378 /* Only two at a time */
379 struct _pl330_req req[2];
380 /* Index of the last enqueued request */
381 unsigned lstenq;
382 /* Index of the last submitted request or -1 if the DMA is stopped */
383 int req_running;
384};
385
386enum pl330_dmac_state {
387 UNINIT,
388 INIT,
389 DYING,
390};
391
392enum desc_status {
393 /* In the DMAC pool */
394 FREE,
395 /*
396 * Allocated to some channel during prep_xxx
397 * Also may be sitting on the work_list.
398 */
399 PREP,
400 /*
401 * Sitting on the work_list and already submitted
402 * to the PL330 core. Not more than two descriptors
403 * of a channel can be BUSY at any time.
404 */
405 BUSY,
406 /*
407 * Sitting on the channel work_list but xfer done
408 * by PL330 core
409 */
410 DONE,
411};
412
413struct dma_pl330_chan {
414 /* Schedule desc completion */
415 struct tasklet_struct task;
416
417 /* DMA-Engine Channel */
418 struct dma_chan chan;
419
420 /* List of submitted descriptors */
421 struct list_head submitted_list;
422 /* List of issued descriptors */
423 struct list_head work_list;
424 /* List of completed descriptors */
425 struct list_head completed_list;
426
427 /* Pointer to the DMAC that manages this channel,
428 * NULL if the channel is available to be acquired.
429 * As the parent, this DMAC also provides descriptors
430 * to the channel.
431 */
432 struct pl330_dmac *dmac;
433
434 /* To protect channel manipulation */
435 spinlock_t lock;
436
437 /*
438 * Hardware channel thread of PL330 DMAC. NULL if the channel is
439 * available.
440 */
441 struct pl330_thread *thread;
442
443 /* For D-to-M and M-to-D channels */
444 int burst_sz; /* the peripheral fifo width */
445 int burst_len; /* the number of burst */
446 phys_addr_t fifo_addr;
447 /* DMA-mapped view of the FIFO; may differ if an IOMMU is present */
448 dma_addr_t fifo_dma;
449 enum dma_data_direction dir;
450 struct dma_slave_config slave_config;
451
452 /* for cyclic capability */
453 bool cyclic;
454
455 /* for runtime pm tracking */
456 bool active;
457};
458
459struct pl330_dmac {
460 /* DMA-Engine Device */
461 struct dma_device ddma;
462
463 /* Holds info about sg limitations */
464 struct device_dma_parameters dma_parms;
465
466 /* Pool of descriptors available for the DMAC's channels */
467 struct list_head desc_pool;
468 /* To protect desc_pool manipulation */
469 spinlock_t pool_lock;
470
471 /* Size of MicroCode buffers for each channel. */
472 unsigned mcbufsz;
473 /* ioremap'ed address of PL330 registers. */
474 void __iomem *base;
475 /* Populated by the PL330 core driver during pl330_add */
476 struct pl330_config pcfg;
477
478 spinlock_t lock;
479 /* Maximum possible events/irqs */
480 int events[32];
481 /* BUS address of MicroCode buffer */
482 dma_addr_t mcode_bus;
483 /* CPU address of MicroCode buffer */
484 void *mcode_cpu;
485 /* List of all Channel threads */
486 struct pl330_thread *channels;
487 /* Pointer to the MANAGER thread */
488 struct pl330_thread *manager;
489 /* To handle bad news in interrupt */
490 struct tasklet_struct tasks;
491 struct _pl330_tbd dmac_tbd;
492 /* State of DMAC operation */
493 enum pl330_dmac_state state;
494 /* Holds list of reqs with due callbacks */
495 struct list_head req_done;
496
497 /* Peripheral channels connected to this DMAC */
498 unsigned int num_peripherals;
499 struct dma_pl330_chan *peripherals; /* keep at end */
500 int quirks;
501
502 struct reset_control *rstc;
503 struct reset_control *rstc_ocp;
504};
505
506static struct pl330_of_quirks {
507 char *quirk;
508 int id;
509} of_quirks[] = {
510 {
511 .quirk = "arm,pl330-broken-no-flushp",
512 .id = PL330_QUIRK_BROKEN_NO_FLUSHP,
513 },
514 {
515 .quirk = "arm,pl330-periph-burst",
516 .id = PL330_QUIRK_PERIPH_BURST,
517 }
518};
519
520struct dma_pl330_desc {
521 /* To attach to a queue as child */
522 struct list_head node;
523
524 /* Descriptor for the DMA Engine API */
525 struct dma_async_tx_descriptor txd;
526
527 /* Xfer for PL330 core */
528 struct pl330_xfer px;
529
530 struct pl330_reqcfg rqcfg;
531
532 enum desc_status status;
533
534 int bytes_requested;
535 bool last;
536
537 /* The channel which currently holds this desc */
538 struct dma_pl330_chan *pchan;
539
540 enum dma_transfer_direction rqtype;
541 /* Index of peripheral for the xfer. */
542 unsigned peri:5;
543 /* Hook to attach to DMAC's list of reqs with due callback */
544 struct list_head rqd;
545};
546
547struct _xfer_spec {
548 u32 ccr;
549 struct dma_pl330_desc *desc;
550};
551
552static int pl330_config_write(struct dma_chan *chan,
553 struct dma_slave_config *slave_config,
554 enum dma_transfer_direction direction);
555
556static inline bool _queue_full(struct pl330_thread *thrd)
557{
558 return thrd->req[0].desc != NULL && thrd->req[1].desc != NULL;
559}
560
561static inline bool is_manager(struct pl330_thread *thrd)
562{
563 return thrd->dmac->manager == thrd;
564}
565
566/* If manager of the thread is in Non-Secure mode */
567static inline bool _manager_ns(struct pl330_thread *thrd)
568{
569 return (thrd->dmac->pcfg.mode & DMAC_MODE_NS) ? true : false;
570}
571
572static inline u32 get_revision(u32 periph_id)
573{
574 return (periph_id >> PERIPH_REV_SHIFT) & PERIPH_REV_MASK;
575}
576
577static inline u32 _emit_END(unsigned dry_run, u8 buf[])
578{
579 if (dry_run)
580 return SZ_DMAEND;
581
582 buf[0] = CMD_DMAEND;
583
584 PL330_DBGCMD_DUMP(SZ_DMAEND, "\tDMAEND\n");
585
586 return SZ_DMAEND;
587}
588
589static inline u32 _emit_FLUSHP(unsigned dry_run, u8 buf[], u8 peri)
590{
591 if (dry_run)
592 return SZ_DMAFLUSHP;
593
594 buf[0] = CMD_DMAFLUSHP;
595
596 peri &= 0x1f;
597 peri <<= 3;
598 buf[1] = peri;
599
600 PL330_DBGCMD_DUMP(SZ_DMAFLUSHP, "\tDMAFLUSHP %u\n", peri >> 3);
601
602 return SZ_DMAFLUSHP;
603}
604
605static inline u32 _emit_LD(unsigned dry_run, u8 buf[], enum pl330_cond cond)
606{
607 if (dry_run)
608 return SZ_DMALD;
609
610 buf[0] = CMD_DMALD;
611
612 if (cond == SINGLE)
613 buf[0] |= (0 << 1) | (1 << 0);
614 else if (cond == BURST)
615 buf[0] |= (1 << 1) | (1 << 0);
616
617 PL330_DBGCMD_DUMP(SZ_DMALD, "\tDMALD%c\n",
618 cond == SINGLE ? 'S' : (cond == BURST ? 'B' : 'A'));
619
620 return SZ_DMALD;
621}
622
623static inline u32 _emit_LDP(unsigned dry_run, u8 buf[],
624 enum pl330_cond cond, u8 peri)
625{
626 if (dry_run)
627 return SZ_DMALDP;
628
629 buf[0] = CMD_DMALDP;
630
631 if (cond == BURST)
632 buf[0] |= (1 << 1);
633
634 peri &= 0x1f;
635 peri <<= 3;
636 buf[1] = peri;
637
638 PL330_DBGCMD_DUMP(SZ_DMALDP, "\tDMALDP%c %u\n",
639 cond == SINGLE ? 'S' : 'B', peri >> 3);
640
641 return SZ_DMALDP;
642}
643
644static inline u32 _emit_LP(unsigned dry_run, u8 buf[],
645 unsigned loop, u8 cnt)
646{
647 if (dry_run)
648 return SZ_DMALP;
649
650 buf[0] = CMD_DMALP;
651
652 if (loop)
653 buf[0] |= (1 << 1);
654
655 cnt--; /* DMAC increments by 1 internally */
656 buf[1] = cnt;
657
658 PL330_DBGCMD_DUMP(SZ_DMALP, "\tDMALP_%c %u\n", loop ? '1' : '0', cnt);
659
660 return SZ_DMALP;
661}
662
663struct _arg_LPEND {
664 enum pl330_cond cond;
665 bool forever;
666 unsigned loop;
667 u8 bjump;
668};
669
670static inline u32 _emit_LPEND(unsigned dry_run, u8 buf[],
671 const struct _arg_LPEND *arg)
672{
673 enum pl330_cond cond = arg->cond;
674 bool forever = arg->forever;
675 unsigned loop = arg->loop;
676 u8 bjump = arg->bjump;
677
678 if (dry_run)
679 return SZ_DMALPEND;
680
681 buf[0] = CMD_DMALPEND;
682
683 if (loop)
684 buf[0] |= (1 << 2);
685
686 if (!forever)
687 buf[0] |= (1 << 4);
688
689 if (cond == SINGLE)
690 buf[0] |= (0 << 1) | (1 << 0);
691 else if (cond == BURST)
692 buf[0] |= (1 << 1) | (1 << 0);
693
694 buf[1] = bjump;
695
696 PL330_DBGCMD_DUMP(SZ_DMALPEND, "\tDMALP%s%c_%c bjmpto_%x\n",
697 forever ? "FE" : "END",
698 cond == SINGLE ? 'S' : (cond == BURST ? 'B' : 'A'),
699 loop ? '1' : '0',
700 bjump);
701
702 return SZ_DMALPEND;
703}
704
705static inline u32 _emit_KILL(unsigned dry_run, u8 buf[])
706{
707 if (dry_run)
708 return SZ_DMAKILL;
709
710 buf[0] = CMD_DMAKILL;
711
712 return SZ_DMAKILL;
713}
714
715static inline u32 _emit_MOV(unsigned dry_run, u8 buf[],
716 enum dmamov_dst dst, u32 val)
717{
718 if (dry_run)
719 return SZ_DMAMOV;
720
721 buf[0] = CMD_DMAMOV;
722 buf[1] = dst;
723 buf[2] = val;
724 buf[3] = val >> 8;
725 buf[4] = val >> 16;
726 buf[5] = val >> 24;
727
728 PL330_DBGCMD_DUMP(SZ_DMAMOV, "\tDMAMOV %s 0x%x\n",
729 dst == SAR ? "SAR" : (dst == DAR ? "DAR" : "CCR"), val);
730
731 return SZ_DMAMOV;
732}
733
734static inline u32 _emit_RMB(unsigned dry_run, u8 buf[])
735{
736 if (dry_run)
737 return SZ_DMARMB;
738
739 buf[0] = CMD_DMARMB;
740
741 PL330_DBGCMD_DUMP(SZ_DMARMB, "\tDMARMB\n");
742
743 return SZ_DMARMB;
744}
745
746static inline u32 _emit_SEV(unsigned dry_run, u8 buf[], u8 ev)
747{
748 if (dry_run)
749 return SZ_DMASEV;
750
751 buf[0] = CMD_DMASEV;
752
753 ev &= 0x1f;
754 ev <<= 3;
755 buf[1] = ev;
756
757 PL330_DBGCMD_DUMP(SZ_DMASEV, "\tDMASEV %u\n", ev >> 3);
758
759 return SZ_DMASEV;
760}
761
762static inline u32 _emit_ST(unsigned dry_run, u8 buf[], enum pl330_cond cond)
763{
764 if (dry_run)
765 return SZ_DMAST;
766
767 buf[0] = CMD_DMAST;
768
769 if (cond == SINGLE)
770 buf[0] |= (0 << 1) | (1 << 0);
771 else if (cond == BURST)
772 buf[0] |= (1 << 1) | (1 << 0);
773
774 PL330_DBGCMD_DUMP(SZ_DMAST, "\tDMAST%c\n",
775 cond == SINGLE ? 'S' : (cond == BURST ? 'B' : 'A'));
776
777 return SZ_DMAST;
778}
779
780static inline u32 _emit_STP(unsigned dry_run, u8 buf[],
781 enum pl330_cond cond, u8 peri)
782{
783 if (dry_run)
784 return SZ_DMASTP;
785
786 buf[0] = CMD_DMASTP;
787
788 if (cond == BURST)
789 buf[0] |= (1 << 1);
790
791 peri &= 0x1f;
792 peri <<= 3;
793 buf[1] = peri;
794
795 PL330_DBGCMD_DUMP(SZ_DMASTP, "\tDMASTP%c %u\n",
796 cond == SINGLE ? 'S' : 'B', peri >> 3);
797
798 return SZ_DMASTP;
799}
800
801static inline u32 _emit_WFP(unsigned dry_run, u8 buf[],
802 enum pl330_cond cond, u8 peri)
803{
804 if (dry_run)
805 return SZ_DMAWFP;
806
807 buf[0] = CMD_DMAWFP;
808
809 if (cond == SINGLE)
810 buf[0] |= (0 << 1) | (0 << 0);
811 else if (cond == BURST)
812 buf[0] |= (1 << 1) | (0 << 0);
813 else
814 buf[0] |= (0 << 1) | (1 << 0);
815
816 peri &= 0x1f;
817 peri <<= 3;
818 buf[1] = peri;
819
820 PL330_DBGCMD_DUMP(SZ_DMAWFP, "\tDMAWFP%c %u\n",
821 cond == SINGLE ? 'S' : (cond == BURST ? 'B' : 'P'), peri >> 3);
822
823 return SZ_DMAWFP;
824}
825
826static inline u32 _emit_WMB(unsigned dry_run, u8 buf[])
827{
828 if (dry_run)
829 return SZ_DMAWMB;
830
831 buf[0] = CMD_DMAWMB;
832
833 PL330_DBGCMD_DUMP(SZ_DMAWMB, "\tDMAWMB\n");
834
835 return SZ_DMAWMB;
836}
837
838struct _arg_GO {
839 u8 chan;
840 u32 addr;
841 unsigned ns;
842};
843
844static inline u32 _emit_GO(unsigned dry_run, u8 buf[],
845 const struct _arg_GO *arg)
846{
847 u8 chan = arg->chan;
848 u32 addr = arg->addr;
849 unsigned ns = arg->ns;
850
851 if (dry_run)
852 return SZ_DMAGO;
853
854 buf[0] = CMD_DMAGO;
855 buf[0] |= (ns << 1);
856 buf[1] = chan & 0x7;
857 buf[2] = addr;
858 buf[3] = addr >> 8;
859 buf[4] = addr >> 16;
860 buf[5] = addr >> 24;
861
862 return SZ_DMAGO;
863}
864
865#define msecs_to_loops(t) (loops_per_jiffy / 1000 * HZ * t)
866
867/* Returns Time-Out */
868static bool _until_dmac_idle(struct pl330_thread *thrd)
869{
870 void __iomem *regs = thrd->dmac->base;
871 unsigned long loops = msecs_to_loops(5);
872
873 do {
874 /* Until Manager is Idle */
875 if (!(readl(regs + DBGSTATUS) & DBG_BUSY))
876 break;
877
878 cpu_relax();
879 } while (--loops);
880
881 if (!loops)
882 return true;
883
884 return false;
885}
886
887static inline void _execute_DBGINSN(struct pl330_thread *thrd,
888 u8 insn[], bool as_manager)
889{
890 void __iomem *regs = thrd->dmac->base;
891 u32 val;
892
893 /* If timed out due to halted state-machine */
894 if (_until_dmac_idle(thrd)) {
895 dev_err(thrd->dmac->ddma.dev, "DMAC halted!\n");
896 return;
897 }
898
899 val = (insn[0] << 16) | (insn[1] << 24);
900 if (!as_manager) {
901 val |= (1 << 0);
902 val |= (thrd->id << 8); /* Channel Number */
903 }
904 writel(val, regs + DBGINST0);
905
906 val = le32_to_cpu(*((__le32 *)&insn[2]));
907 writel(val, regs + DBGINST1);
908
909 /* Get going */
910 writel(0, regs + DBGCMD);
911}
912
913static inline u32 _state(struct pl330_thread *thrd)
914{
915 void __iomem *regs = thrd->dmac->base;
916 u32 val;
917
918 if (is_manager(thrd))
919 val = readl(regs + DS) & 0xf;
920 else
921 val = readl(regs + CS(thrd->id)) & 0xf;
922
923 switch (val) {
924 case DS_ST_STOP:
925 return PL330_STATE_STOPPED;
926 case DS_ST_EXEC:
927 return PL330_STATE_EXECUTING;
928 case DS_ST_CMISS:
929 return PL330_STATE_CACHEMISS;
930 case DS_ST_UPDTPC:
931 return PL330_STATE_UPDTPC;
932 case DS_ST_WFE:
933 return PL330_STATE_WFE;
934 case DS_ST_FAULT:
935 return PL330_STATE_FAULTING;
936 case DS_ST_ATBRR:
937 if (is_manager(thrd))
938 return PL330_STATE_INVALID;
939 else
940 return PL330_STATE_ATBARRIER;
941 case DS_ST_QBUSY:
942 if (is_manager(thrd))
943 return PL330_STATE_INVALID;
944 else
945 return PL330_STATE_QUEUEBUSY;
946 case DS_ST_WFP:
947 if (is_manager(thrd))
948 return PL330_STATE_INVALID;
949 else
950 return PL330_STATE_WFP;
951 case DS_ST_KILL:
952 if (is_manager(thrd))
953 return PL330_STATE_INVALID;
954 else
955 return PL330_STATE_KILLING;
956 case DS_ST_CMPLT:
957 if (is_manager(thrd))
958 return PL330_STATE_INVALID;
959 else
960 return PL330_STATE_COMPLETING;
961 case DS_ST_FLTCMP:
962 if (is_manager(thrd))
963 return PL330_STATE_INVALID;
964 else
965 return PL330_STATE_FAULT_COMPLETING;
966 default:
967 return PL330_STATE_INVALID;
968 }
969}
970
971static void _stop(struct pl330_thread *thrd)
972{
973 void __iomem *regs = thrd->dmac->base;
974 u8 insn[6] = {0, 0, 0, 0, 0, 0};
975 u32 inten = readl(regs + INTEN);
976
977 if (_state(thrd) == PL330_STATE_FAULT_COMPLETING)
978 UNTIL(thrd, PL330_STATE_FAULTING | PL330_STATE_KILLING);
979
980 /* Return if nothing needs to be done */
981 if (_state(thrd) == PL330_STATE_COMPLETING
982 || _state(thrd) == PL330_STATE_KILLING
983 || _state(thrd) == PL330_STATE_STOPPED)
984 return;
985
986 _emit_KILL(0, insn);
987
988 _execute_DBGINSN(thrd, insn, is_manager(thrd));
989
990 /* clear the event */
991 if (inten & (1 << thrd->ev))
992 writel(1 << thrd->ev, regs + INTCLR);
993 /* Stop generating interrupts for SEV */
994 writel(inten & ~(1 << thrd->ev), regs + INTEN);
995}
996
997/* Start doing req 'idx' of thread 'thrd' */
998static bool _trigger(struct pl330_thread *thrd)
999{
1000 void __iomem *regs = thrd->dmac->base;
1001 struct _pl330_req *req;
1002 struct dma_pl330_desc *desc;
1003 struct _arg_GO go;
1004 unsigned ns;
1005 u8 insn[6] = {0, 0, 0, 0, 0, 0};
1006 int idx;
1007
1008 /* Return if already ACTIVE */
1009 if (_state(thrd) != PL330_STATE_STOPPED)
1010 return true;
1011
1012 idx = 1 - thrd->lstenq;
1013 if (thrd->req[idx].desc != NULL) {
1014 req = &thrd->req[idx];
1015 } else {
1016 idx = thrd->lstenq;
1017 if (thrd->req[idx].desc != NULL)
1018 req = &thrd->req[idx];
1019 else
1020 req = NULL;
1021 }
1022
1023 /* Return if no request */
1024 if (!req)
1025 return true;
1026
1027 /* Return if req is running */
1028 if (idx == thrd->req_running)
1029 return true;
1030
1031 desc = req->desc;
1032
1033 ns = desc->rqcfg.nonsecure ? 1 : 0;
1034
1035 /* See 'Abort Sources' point-4 at Page 2-25 */
1036 if (_manager_ns(thrd) && !ns)
1037 dev_info(thrd->dmac->ddma.dev, "%s:%d Recipe for ABORT!\n",
1038 __func__, __LINE__);
1039
1040 go.chan = thrd->id;
1041 go.addr = req->mc_bus;
1042 go.ns = ns;
1043 _emit_GO(0, insn, &go);
1044
1045 /* Set to generate interrupts for SEV */
1046 writel(readl(regs + INTEN) | (1 << thrd->ev), regs + INTEN);
1047
1048 /* Only manager can execute GO */
1049 _execute_DBGINSN(thrd, insn, true);
1050
1051 thrd->req_running = idx;
1052
1053 return true;
1054}
1055
1056static bool _start(struct pl330_thread *thrd)
1057{
1058 switch (_state(thrd)) {
1059 case PL330_STATE_FAULT_COMPLETING:
1060 UNTIL(thrd, PL330_STATE_FAULTING | PL330_STATE_KILLING);
1061
1062 if (_state(thrd) == PL330_STATE_KILLING)
1063 UNTIL(thrd, PL330_STATE_STOPPED)
1064 fallthrough;
1065
1066 case PL330_STATE_FAULTING:
1067 _stop(thrd);
1068 fallthrough;
1069
1070 case PL330_STATE_KILLING:
1071 case PL330_STATE_COMPLETING:
1072 UNTIL(thrd, PL330_STATE_STOPPED)
1073 fallthrough;
1074
1075 case PL330_STATE_STOPPED:
1076 return _trigger(thrd);
1077
1078 case PL330_STATE_WFP:
1079 case PL330_STATE_QUEUEBUSY:
1080 case PL330_STATE_ATBARRIER:
1081 case PL330_STATE_UPDTPC:
1082 case PL330_STATE_CACHEMISS:
1083 case PL330_STATE_EXECUTING:
1084 return true;
1085
1086 case PL330_STATE_WFE: /* For RESUME, nothing yet */
1087 default:
1088 return false;
1089 }
1090}
1091
1092static inline int _ldst_memtomem(unsigned dry_run, u8 buf[],
1093 const struct _xfer_spec *pxs, int cyc)
1094{
1095 int off = 0;
1096 struct pl330_config *pcfg = pxs->desc->rqcfg.pcfg;
1097
1098 /* check lock-up free version */
1099 if (get_revision(pcfg->periph_id) >= PERIPH_REV_R1P0) {
1100 while (cyc--) {
1101 off += _emit_LD(dry_run, &buf[off], ALWAYS);
1102 off += _emit_ST(dry_run, &buf[off], ALWAYS);
1103 }
1104 } else {
1105 while (cyc--) {
1106 off += _emit_LD(dry_run, &buf[off], ALWAYS);
1107 off += _emit_RMB(dry_run, &buf[off]);
1108 off += _emit_ST(dry_run, &buf[off], ALWAYS);
1109 off += _emit_WMB(dry_run, &buf[off]);
1110 }
1111 }
1112
1113 return off;
1114}
1115
1116static u32 _emit_load(unsigned int dry_run, u8 buf[],
1117 enum pl330_cond cond, enum dma_transfer_direction direction,
1118 u8 peri)
1119{
1120 int off = 0;
1121
1122 switch (direction) {
1123 case DMA_MEM_TO_MEM:
1124 case DMA_MEM_TO_DEV:
1125 off += _emit_LD(dry_run, &buf[off], cond);
1126 break;
1127
1128 case DMA_DEV_TO_MEM:
1129 if (cond == ALWAYS) {
1130 off += _emit_LDP(dry_run, &buf[off], SINGLE,
1131 peri);
1132 off += _emit_LDP(dry_run, &buf[off], BURST,
1133 peri);
1134 } else {
1135 off += _emit_LDP(dry_run, &buf[off], cond,
1136 peri);
1137 }
1138 break;
1139
1140 default:
1141 /* this code should be unreachable */
1142 WARN_ON(1);
1143 break;
1144 }
1145
1146 return off;
1147}
1148
1149static inline u32 _emit_store(unsigned int dry_run, u8 buf[],
1150 enum pl330_cond cond, enum dma_transfer_direction direction,
1151 u8 peri)
1152{
1153 int off = 0;
1154
1155 switch (direction) {
1156 case DMA_MEM_TO_MEM:
1157 case DMA_DEV_TO_MEM:
1158 off += _emit_ST(dry_run, &buf[off], cond);
1159 break;
1160
1161 case DMA_MEM_TO_DEV:
1162 if (cond == ALWAYS) {
1163 off += _emit_STP(dry_run, &buf[off], SINGLE,
1164 peri);
1165 off += _emit_STP(dry_run, &buf[off], BURST,
1166 peri);
1167 } else {
1168 off += _emit_STP(dry_run, &buf[off], cond,
1169 peri);
1170 }
1171 break;
1172
1173 default:
1174 /* this code should be unreachable */
1175 WARN_ON(1);
1176 break;
1177 }
1178
1179 return off;
1180}
1181
1182static inline int _ldst_peripheral(struct pl330_dmac *pl330,
1183 unsigned dry_run, u8 buf[],
1184 const struct _xfer_spec *pxs, int cyc,
1185 enum pl330_cond cond)
1186{
1187 int off = 0;
1188
1189 /*
1190 * do FLUSHP at beginning to clear any stale dma requests before the
1191 * first WFP.
1192 */
1193 if (!(pl330->quirks & PL330_QUIRK_BROKEN_NO_FLUSHP))
1194 off += _emit_FLUSHP(dry_run, &buf[off], pxs->desc->peri);
1195 while (cyc--) {
1196 off += _emit_WFP(dry_run, &buf[off], cond, pxs->desc->peri);
1197 off += _emit_load(dry_run, &buf[off], cond, pxs->desc->rqtype,
1198 pxs->desc->peri);
1199 off += _emit_store(dry_run, &buf[off], cond, pxs->desc->rqtype,
1200 pxs->desc->peri);
1201 }
1202
1203 return off;
1204}
1205
1206static int _bursts(struct pl330_dmac *pl330, unsigned dry_run, u8 buf[],
1207 const struct _xfer_spec *pxs, int cyc)
1208{
1209 int off = 0;
1210 enum pl330_cond cond = BRST_LEN(pxs->ccr) > 1 ? BURST : SINGLE;
1211
1212 if (pl330->quirks & PL330_QUIRK_PERIPH_BURST)
1213 cond = BURST;
1214
1215 switch (pxs->desc->rqtype) {
1216 case DMA_MEM_TO_DEV:
1217 case DMA_DEV_TO_MEM:
1218 off += _ldst_peripheral(pl330, dry_run, &buf[off], pxs, cyc,
1219 cond);
1220 break;
1221
1222 case DMA_MEM_TO_MEM:
1223 off += _ldst_memtomem(dry_run, &buf[off], pxs, cyc);
1224 break;
1225
1226 default:
1227 /* this code should be unreachable */
1228 WARN_ON(1);
1229 break;
1230 }
1231
1232 return off;
1233}
1234
1235/*
1236 * only the unaligned burst transfers have the dregs.
1237 * so, still transfer dregs with a reduced size burst
1238 * for mem-to-mem, mem-to-dev or dev-to-mem.
1239 */
1240static int _dregs(struct pl330_dmac *pl330, unsigned int dry_run, u8 buf[],
1241 const struct _xfer_spec *pxs, int transfer_length)
1242{
1243 int off = 0;
1244 int dregs_ccr;
1245
1246 if (transfer_length == 0)
1247 return off;
1248
1249 /*
1250 * dregs_len = (total bytes - BURST_TO_BYTE(bursts, ccr)) /
1251 * BRST_SIZE(ccr)
1252 * the dregs len must be smaller than burst len,
1253 * so, for higher efficiency, we can modify CCR
1254 * to use a reduced size burst len for the dregs.
1255 */
1256 dregs_ccr = pxs->ccr;
1257 dregs_ccr &= ~((0xf << CC_SRCBRSTLEN_SHFT) |
1258 (0xf << CC_DSTBRSTLEN_SHFT));
1259 dregs_ccr |= (((transfer_length - 1) & 0xf) <<
1260 CC_SRCBRSTLEN_SHFT);
1261 dregs_ccr |= (((transfer_length - 1) & 0xf) <<
1262 CC_DSTBRSTLEN_SHFT);
1263
1264 switch (pxs->desc->rqtype) {
1265 case DMA_MEM_TO_DEV:
1266 case DMA_DEV_TO_MEM:
1267 off += _emit_MOV(dry_run, &buf[off], CCR, dregs_ccr);
1268 off += _ldst_peripheral(pl330, dry_run, &buf[off], pxs, 1,
1269 BURST);
1270 break;
1271
1272 case DMA_MEM_TO_MEM:
1273 off += _emit_MOV(dry_run, &buf[off], CCR, dregs_ccr);
1274 off += _ldst_memtomem(dry_run, &buf[off], pxs, 1);
1275 break;
1276
1277 default:
1278 /* this code should be unreachable */
1279 WARN_ON(1);
1280 break;
1281 }
1282
1283 return off;
1284}
1285
1286/* Returns bytes consumed and updates bursts */
1287static inline int _loop(struct pl330_dmac *pl330, unsigned dry_run, u8 buf[],
1288 unsigned long *bursts, const struct _xfer_spec *pxs)
1289{
1290 int cyc, cycmax, szlp, szlpend, szbrst, off;
1291 unsigned lcnt0, lcnt1, ljmp0, ljmp1;
1292 struct _arg_LPEND lpend;
1293
1294 if (*bursts == 1)
1295 return _bursts(pl330, dry_run, buf, pxs, 1);
1296
1297 /* Max iterations possible in DMALP is 256 */
1298 if (*bursts >= 256*256) {
1299 lcnt1 = 256;
1300 lcnt0 = 256;
1301 cyc = *bursts / lcnt1 / lcnt0;
1302 } else if (*bursts > 256) {
1303 lcnt1 = 256;
1304 lcnt0 = *bursts / lcnt1;
1305 cyc = 1;
1306 } else {
1307 lcnt1 = *bursts;
1308 lcnt0 = 0;
1309 cyc = 1;
1310 }
1311
1312 szlp = _emit_LP(1, buf, 0, 0);
1313 szbrst = _bursts(pl330, 1, buf, pxs, 1);
1314
1315 lpend.cond = ALWAYS;
1316 lpend.forever = false;
1317 lpend.loop = 0;
1318 lpend.bjump = 0;
1319 szlpend = _emit_LPEND(1, buf, &lpend);
1320
1321 if (lcnt0) {
1322 szlp *= 2;
1323 szlpend *= 2;
1324 }
1325
1326 /*
1327 * Max bursts that we can unroll due to limit on the
1328 * size of backward jump that can be encoded in DMALPEND
1329 * which is 8-bits and hence 255
1330 */
1331 cycmax = (255 - (szlp + szlpend)) / szbrst;
1332
1333 cyc = (cycmax < cyc) ? cycmax : cyc;
1334
1335 off = 0;
1336
1337 if (lcnt0) {
1338 off += _emit_LP(dry_run, &buf[off], 0, lcnt0);
1339 ljmp0 = off;
1340 }
1341
1342 off += _emit_LP(dry_run, &buf[off], 1, lcnt1);
1343 ljmp1 = off;
1344
1345 off += _bursts(pl330, dry_run, &buf[off], pxs, cyc);
1346
1347 lpend.cond = ALWAYS;
1348 lpend.forever = false;
1349 lpend.loop = 1;
1350 lpend.bjump = off - ljmp1;
1351 off += _emit_LPEND(dry_run, &buf[off], &lpend);
1352
1353 if (lcnt0) {
1354 lpend.cond = ALWAYS;
1355 lpend.forever = false;
1356 lpend.loop = 0;
1357 lpend.bjump = off - ljmp0;
1358 off += _emit_LPEND(dry_run, &buf[off], &lpend);
1359 }
1360
1361 *bursts = lcnt1 * cyc;
1362 if (lcnt0)
1363 *bursts *= lcnt0;
1364
1365 return off;
1366}
1367
1368static inline int _setup_loops(struct pl330_dmac *pl330,
1369 unsigned dry_run, u8 buf[],
1370 const struct _xfer_spec *pxs)
1371{
1372 struct pl330_xfer *x = &pxs->desc->px;
1373 u32 ccr = pxs->ccr;
1374 unsigned long c, bursts = BYTE_TO_BURST(x->bytes, ccr);
1375 int num_dregs = (x->bytes - BURST_TO_BYTE(bursts, ccr)) /
1376 BRST_SIZE(ccr);
1377 int off = 0;
1378
1379 while (bursts) {
1380 c = bursts;
1381 off += _loop(pl330, dry_run, &buf[off], &c, pxs);
1382 bursts -= c;
1383 }
1384 off += _dregs(pl330, dry_run, &buf[off], pxs, num_dregs);
1385
1386 return off;
1387}
1388
1389static inline int _setup_xfer(struct pl330_dmac *pl330,
1390 unsigned dry_run, u8 buf[],
1391 const struct _xfer_spec *pxs)
1392{
1393 struct pl330_xfer *x = &pxs->desc->px;
1394 int off = 0;
1395
1396 /* DMAMOV SAR, x->src_addr */
1397 off += _emit_MOV(dry_run, &buf[off], SAR, x->src_addr);
1398 /* DMAMOV DAR, x->dst_addr */
1399 off += _emit_MOV(dry_run, &buf[off], DAR, x->dst_addr);
1400
1401 /* Setup Loop(s) */
1402 off += _setup_loops(pl330, dry_run, &buf[off], pxs);
1403
1404 return off;
1405}
1406
1407/*
1408 * A req is a sequence of one or more xfer units.
1409 * Returns the number of bytes taken to setup the MC for the req.
1410 */
1411static int _setup_req(struct pl330_dmac *pl330, unsigned dry_run,
1412 struct pl330_thread *thrd, unsigned index,
1413 struct _xfer_spec *pxs)
1414{
1415 struct _pl330_req *req = &thrd->req[index];
1416 u8 *buf = req->mc_cpu;
1417 int off = 0;
1418
1419 PL330_DBGMC_START(req->mc_bus);
1420
1421 /* DMAMOV CCR, ccr */
1422 off += _emit_MOV(dry_run, &buf[off], CCR, pxs->ccr);
1423
1424 off += _setup_xfer(pl330, dry_run, &buf[off], pxs);
1425
1426 /* DMASEV peripheral/event */
1427 off += _emit_SEV(dry_run, &buf[off], thrd->ev);
1428 /* DMAEND */
1429 off += _emit_END(dry_run, &buf[off]);
1430
1431 return off;
1432}
1433
1434static inline u32 _prepare_ccr(const struct pl330_reqcfg *rqc)
1435{
1436 u32 ccr = 0;
1437
1438 if (rqc->src_inc)
1439 ccr |= CC_SRCINC;
1440
1441 if (rqc->dst_inc)
1442 ccr |= CC_DSTINC;
1443
1444 /* We set same protection levels for Src and DST for now */
1445 if (rqc->privileged)
1446 ccr |= CC_SRCPRI | CC_DSTPRI;
1447 if (rqc->nonsecure)
1448 ccr |= CC_SRCNS | CC_DSTNS;
1449 if (rqc->insnaccess)
1450 ccr |= CC_SRCIA | CC_DSTIA;
1451
1452 ccr |= (((rqc->brst_len - 1) & 0xf) << CC_SRCBRSTLEN_SHFT);
1453 ccr |= (((rqc->brst_len - 1) & 0xf) << CC_DSTBRSTLEN_SHFT);
1454
1455 ccr |= (rqc->brst_size << CC_SRCBRSTSIZE_SHFT);
1456 ccr |= (rqc->brst_size << CC_DSTBRSTSIZE_SHFT);
1457
1458 ccr |= (rqc->scctl << CC_SRCCCTRL_SHFT);
1459 ccr |= (rqc->dcctl << CC_DSTCCTRL_SHFT);
1460
1461 ccr |= (rqc->swap << CC_SWAP_SHFT);
1462
1463 return ccr;
1464}
1465
1466/*
1467 * Submit a list of xfers after which the client wants notification.
1468 * Client is not notified after each xfer unit, just once after all
1469 * xfer units are done or some error occurs.
1470 */
1471static int pl330_submit_req(struct pl330_thread *thrd,
1472 struct dma_pl330_desc *desc)
1473{
1474 struct pl330_dmac *pl330 = thrd->dmac;
1475 struct _xfer_spec xs;
1476 unsigned long flags;
1477 unsigned idx;
1478 u32 ccr;
1479 int ret = 0;
1480
1481 switch (desc->rqtype) {
1482 case DMA_MEM_TO_DEV:
1483 break;
1484
1485 case DMA_DEV_TO_MEM:
1486 break;
1487
1488 case DMA_MEM_TO_MEM:
1489 break;
1490
1491 default:
1492 return -ENOTSUPP;
1493 }
1494
1495 if (pl330->state == DYING
1496 || pl330->dmac_tbd.reset_chan & (1 << thrd->id)) {
1497 dev_info(thrd->dmac->ddma.dev, "%s:%d\n",
1498 __func__, __LINE__);
1499 return -EAGAIN;
1500 }
1501
1502 /* If request for non-existing peripheral */
1503 if (desc->rqtype != DMA_MEM_TO_MEM &&
1504 desc->peri >= pl330->pcfg.num_peri) {
1505 dev_info(thrd->dmac->ddma.dev,
1506 "%s:%d Invalid peripheral(%u)!\n",
1507 __func__, __LINE__, desc->peri);
1508 return -EINVAL;
1509 }
1510
1511 spin_lock_irqsave(&pl330->lock, flags);
1512
1513 if (_queue_full(thrd)) {
1514 ret = -EAGAIN;
1515 goto xfer_exit;
1516 }
1517
1518 /* Prefer Secure Channel */
1519 if (!_manager_ns(thrd))
1520 desc->rqcfg.nonsecure = 0;
1521 else
1522 desc->rqcfg.nonsecure = 1;
1523
1524 ccr = _prepare_ccr(&desc->rqcfg);
1525
1526 idx = thrd->req[0].desc == NULL ? 0 : 1;
1527
1528 xs.ccr = ccr;
1529 xs.desc = desc;
1530
1531 /* First dry run to check if req is acceptable */
1532 ret = _setup_req(pl330, 1, thrd, idx, &xs);
1533 if (ret < 0)
1534 goto xfer_exit;
1535
1536 if (ret > pl330->mcbufsz / 2) {
1537 dev_info(pl330->ddma.dev, "%s:%d Try increasing mcbufsz (%i/%i)\n",
1538 __func__, __LINE__, ret, pl330->mcbufsz / 2);
1539 ret = -ENOMEM;
1540 goto xfer_exit;
1541 }
1542
1543 /* Hook the request */
1544 thrd->lstenq = idx;
1545 thrd->req[idx].desc = desc;
1546 _setup_req(pl330, 0, thrd, idx, &xs);
1547
1548 ret = 0;
1549
1550xfer_exit:
1551 spin_unlock_irqrestore(&pl330->lock, flags);
1552
1553 return ret;
1554}
1555
1556static void dma_pl330_rqcb(struct dma_pl330_desc *desc, enum pl330_op_err err)
1557{
1558 struct dma_pl330_chan *pch;
1559 unsigned long flags;
1560
1561 if (!desc)
1562 return;
1563
1564 pch = desc->pchan;
1565
1566 /* If desc aborted */
1567 if (!pch)
1568 return;
1569
1570 spin_lock_irqsave(&pch->lock, flags);
1571
1572 desc->status = DONE;
1573
1574 spin_unlock_irqrestore(&pch->lock, flags);
1575
1576 tasklet_schedule(&pch->task);
1577}
1578
1579static void pl330_dotask(unsigned long data)
1580{
1581 struct pl330_dmac *pl330 = (struct pl330_dmac *) data;
1582 unsigned long flags;
1583 int i;
1584
1585 spin_lock_irqsave(&pl330->lock, flags);
1586
1587 /* The DMAC itself gone nuts */
1588 if (pl330->dmac_tbd.reset_dmac) {
1589 pl330->state = DYING;
1590 /* Reset the manager too */
1591 pl330->dmac_tbd.reset_mngr = true;
1592 /* Clear the reset flag */
1593 pl330->dmac_tbd.reset_dmac = false;
1594 }
1595
1596 if (pl330->dmac_tbd.reset_mngr) {
1597 _stop(pl330->manager);
1598 /* Reset all channels */
1599 pl330->dmac_tbd.reset_chan = (1 << pl330->pcfg.num_chan) - 1;
1600 /* Clear the reset flag */
1601 pl330->dmac_tbd.reset_mngr = false;
1602 }
1603
1604 for (i = 0; i < pl330->pcfg.num_chan; i++) {
1605
1606 if (pl330->dmac_tbd.reset_chan & (1 << i)) {
1607 struct pl330_thread *thrd = &pl330->channels[i];
1608 void __iomem *regs = pl330->base;
1609 enum pl330_op_err err;
1610
1611 _stop(thrd);
1612
1613 if (readl(regs + FSC) & (1 << thrd->id))
1614 err = PL330_ERR_FAIL;
1615 else
1616 err = PL330_ERR_ABORT;
1617
1618 spin_unlock_irqrestore(&pl330->lock, flags);
1619 dma_pl330_rqcb(thrd->req[1 - thrd->lstenq].desc, err);
1620 dma_pl330_rqcb(thrd->req[thrd->lstenq].desc, err);
1621 spin_lock_irqsave(&pl330->lock, flags);
1622
1623 thrd->req[0].desc = NULL;
1624 thrd->req[1].desc = NULL;
1625 thrd->req_running = -1;
1626
1627 /* Clear the reset flag */
1628 pl330->dmac_tbd.reset_chan &= ~(1 << i);
1629 }
1630 }
1631
1632 spin_unlock_irqrestore(&pl330->lock, flags);
1633
1634 return;
1635}
1636
1637/* Returns 1 if state was updated, 0 otherwise */
1638static int pl330_update(struct pl330_dmac *pl330)
1639{
1640 struct dma_pl330_desc *descdone;
1641 unsigned long flags;
1642 void __iomem *regs;
1643 u32 val;
1644 int id, ev, ret = 0;
1645
1646 regs = pl330->base;
1647
1648 spin_lock_irqsave(&pl330->lock, flags);
1649
1650 val = readl(regs + FSM) & 0x1;
1651 if (val)
1652 pl330->dmac_tbd.reset_mngr = true;
1653 else
1654 pl330->dmac_tbd.reset_mngr = false;
1655
1656 val = readl(regs + FSC) & ((1 << pl330->pcfg.num_chan) - 1);
1657 pl330->dmac_tbd.reset_chan |= val;
1658 if (val) {
1659 int i = 0;
1660 while (i < pl330->pcfg.num_chan) {
1661 if (val & (1 << i)) {
1662 dev_info(pl330->ddma.dev,
1663 "Reset Channel-%d\t CS-%x FTC-%x\n",
1664 i, readl(regs + CS(i)),
1665 readl(regs + FTC(i)));
1666 _stop(&pl330->channels[i]);
1667 }
1668 i++;
1669 }
1670 }
1671
1672 /* Check which event happened i.e, thread notified */
1673 val = readl(regs + ES);
1674 if (pl330->pcfg.num_events < 32
1675 && val & ~((1 << pl330->pcfg.num_events) - 1)) {
1676 pl330->dmac_tbd.reset_dmac = true;
1677 dev_err(pl330->ddma.dev, "%s:%d Unexpected!\n", __func__,
1678 __LINE__);
1679 ret = 1;
1680 goto updt_exit;
1681 }
1682
1683 for (ev = 0; ev < pl330->pcfg.num_events; ev++) {
1684 if (val & (1 << ev)) { /* Event occurred */
1685 struct pl330_thread *thrd;
1686 u32 inten = readl(regs + INTEN);
1687 int active;
1688
1689 /* Clear the event */
1690 if (inten & (1 << ev))
1691 writel(1 << ev, regs + INTCLR);
1692
1693 ret = 1;
1694
1695 id = pl330->events[ev];
1696
1697 thrd = &pl330->channels[id];
1698
1699 active = thrd->req_running;
1700 if (active == -1) /* Aborted */
1701 continue;
1702
1703 /* Detach the req */
1704 descdone = thrd->req[active].desc;
1705 thrd->req[active].desc = NULL;
1706
1707 thrd->req_running = -1;
1708
1709 /* Get going again ASAP */
1710 _start(thrd);
1711
1712 /* For now, just make a list of callbacks to be done */
1713 list_add_tail(&descdone->rqd, &pl330->req_done);
1714 }
1715 }
1716
1717 /* Now that we are in no hurry, do the callbacks */
1718 while (!list_empty(&pl330->req_done)) {
1719 descdone = list_first_entry(&pl330->req_done,
1720 struct dma_pl330_desc, rqd);
1721 list_del(&descdone->rqd);
1722 spin_unlock_irqrestore(&pl330->lock, flags);
1723 dma_pl330_rqcb(descdone, PL330_ERR_NONE);
1724 spin_lock_irqsave(&pl330->lock, flags);
1725 }
1726
1727updt_exit:
1728 spin_unlock_irqrestore(&pl330->lock, flags);
1729
1730 if (pl330->dmac_tbd.reset_dmac
1731 || pl330->dmac_tbd.reset_mngr
1732 || pl330->dmac_tbd.reset_chan) {
1733 ret = 1;
1734 tasklet_schedule(&pl330->tasks);
1735 }
1736
1737 return ret;
1738}
1739
1740/* Reserve an event */
1741static inline int _alloc_event(struct pl330_thread *thrd)
1742{
1743 struct pl330_dmac *pl330 = thrd->dmac;
1744 int ev;
1745
1746 for (ev = 0; ev < pl330->pcfg.num_events; ev++)
1747 if (pl330->events[ev] == -1) {
1748 pl330->events[ev] = thrd->id;
1749 return ev;
1750 }
1751
1752 return -1;
1753}
1754
1755static bool _chan_ns(const struct pl330_dmac *pl330, int i)
1756{
1757 return pl330->pcfg.irq_ns & (1 << i);
1758}
1759
1760/* Upon success, returns IdentityToken for the
1761 * allocated channel, NULL otherwise.
1762 */
1763static struct pl330_thread *pl330_request_channel(struct pl330_dmac *pl330)
1764{
1765 struct pl330_thread *thrd = NULL;
1766 int chans, i;
1767
1768 if (pl330->state == DYING)
1769 return NULL;
1770
1771 chans = pl330->pcfg.num_chan;
1772
1773 for (i = 0; i < chans; i++) {
1774 thrd = &pl330->channels[i];
1775 if ((thrd->free) && (!_manager_ns(thrd) ||
1776 _chan_ns(pl330, i))) {
1777 thrd->ev = _alloc_event(thrd);
1778 if (thrd->ev >= 0) {
1779 thrd->free = false;
1780 thrd->lstenq = 1;
1781 thrd->req[0].desc = NULL;
1782 thrd->req[1].desc = NULL;
1783 thrd->req_running = -1;
1784 break;
1785 }
1786 }
1787 thrd = NULL;
1788 }
1789
1790 return thrd;
1791}
1792
1793/* Release an event */
1794static inline void _free_event(struct pl330_thread *thrd, int ev)
1795{
1796 struct pl330_dmac *pl330 = thrd->dmac;
1797
1798 /* If the event is valid and was held by the thread */
1799 if (ev >= 0 && ev < pl330->pcfg.num_events
1800 && pl330->events[ev] == thrd->id)
1801 pl330->events[ev] = -1;
1802}
1803
1804static void pl330_release_channel(struct pl330_thread *thrd)
1805{
1806 if (!thrd || thrd->free)
1807 return;
1808
1809 _stop(thrd);
1810
1811 dma_pl330_rqcb(thrd->req[1 - thrd->lstenq].desc, PL330_ERR_ABORT);
1812 dma_pl330_rqcb(thrd->req[thrd->lstenq].desc, PL330_ERR_ABORT);
1813
1814 _free_event(thrd, thrd->ev);
1815 thrd->free = true;
1816}
1817
1818/* Initialize the structure for PL330 configuration, that can be used
1819 * by the client driver the make best use of the DMAC
1820 */
1821static void read_dmac_config(struct pl330_dmac *pl330)
1822{
1823 void __iomem *regs = pl330->base;
1824 u32 val;
1825
1826 val = readl(regs + CRD) >> CRD_DATA_WIDTH_SHIFT;
1827 val &= CRD_DATA_WIDTH_MASK;
1828 pl330->pcfg.data_bus_width = 8 * (1 << val);
1829
1830 val = readl(regs + CRD) >> CRD_DATA_BUFF_SHIFT;
1831 val &= CRD_DATA_BUFF_MASK;
1832 pl330->pcfg.data_buf_dep = val + 1;
1833
1834 val = readl(regs + CR0) >> CR0_NUM_CHANS_SHIFT;
1835 val &= CR0_NUM_CHANS_MASK;
1836 val += 1;
1837 pl330->pcfg.num_chan = val;
1838
1839 val = readl(regs + CR0);
1840 if (val & CR0_PERIPH_REQ_SET) {
1841 val = (val >> CR0_NUM_PERIPH_SHIFT) & CR0_NUM_PERIPH_MASK;
1842 val += 1;
1843 pl330->pcfg.num_peri = val;
1844 pl330->pcfg.peri_ns = readl(regs + CR4);
1845 } else {
1846 pl330->pcfg.num_peri = 0;
1847 }
1848
1849 val = readl(regs + CR0);
1850 if (val & CR0_BOOT_MAN_NS)
1851 pl330->pcfg.mode |= DMAC_MODE_NS;
1852 else
1853 pl330->pcfg.mode &= ~DMAC_MODE_NS;
1854
1855 val = readl(regs + CR0) >> CR0_NUM_EVENTS_SHIFT;
1856 val &= CR0_NUM_EVENTS_MASK;
1857 val += 1;
1858 pl330->pcfg.num_events = val;
1859
1860 pl330->pcfg.irq_ns = readl(regs + CR3);
1861}
1862
1863static inline void _reset_thread(struct pl330_thread *thrd)
1864{
1865 struct pl330_dmac *pl330 = thrd->dmac;
1866
1867 thrd->req[0].mc_cpu = pl330->mcode_cpu
1868 + (thrd->id * pl330->mcbufsz);
1869 thrd->req[0].mc_bus = pl330->mcode_bus
1870 + (thrd->id * pl330->mcbufsz);
1871 thrd->req[0].desc = NULL;
1872
1873 thrd->req[1].mc_cpu = thrd->req[0].mc_cpu
1874 + pl330->mcbufsz / 2;
1875 thrd->req[1].mc_bus = thrd->req[0].mc_bus
1876 + pl330->mcbufsz / 2;
1877 thrd->req[1].desc = NULL;
1878
1879 thrd->req_running = -1;
1880}
1881
1882static int dmac_alloc_threads(struct pl330_dmac *pl330)
1883{
1884 int chans = pl330->pcfg.num_chan;
1885 struct pl330_thread *thrd;
1886 int i;
1887
1888 /* Allocate 1 Manager and 'chans' Channel threads */
1889 pl330->channels = kcalloc(1 + chans, sizeof(*thrd),
1890 GFP_KERNEL);
1891 if (!pl330->channels)
1892 return -ENOMEM;
1893
1894 /* Init Channel threads */
1895 for (i = 0; i < chans; i++) {
1896 thrd = &pl330->channels[i];
1897 thrd->id = i;
1898 thrd->dmac = pl330;
1899 _reset_thread(thrd);
1900 thrd->free = true;
1901 }
1902
1903 /* MANAGER is indexed at the end */
1904 thrd = &pl330->channels[chans];
1905 thrd->id = chans;
1906 thrd->dmac = pl330;
1907 thrd->free = false;
1908 pl330->manager = thrd;
1909
1910 return 0;
1911}
1912
1913static int dmac_alloc_resources(struct pl330_dmac *pl330)
1914{
1915 int chans = pl330->pcfg.num_chan;
1916 int ret;
1917
1918 /*
1919 * Alloc MicroCode buffer for 'chans' Channel threads.
1920 * A channel's buffer offset is (Channel_Id * MCODE_BUFF_PERCHAN)
1921 */
1922 pl330->mcode_cpu = dma_alloc_attrs(pl330->ddma.dev,
1923 chans * pl330->mcbufsz,
1924 &pl330->mcode_bus, GFP_KERNEL,
1925 DMA_ATTR_PRIVILEGED);
1926 if (!pl330->mcode_cpu) {
1927 dev_err(pl330->ddma.dev, "%s:%d Can't allocate memory!\n",
1928 __func__, __LINE__);
1929 return -ENOMEM;
1930 }
1931
1932 ret = dmac_alloc_threads(pl330);
1933 if (ret) {
1934 dev_err(pl330->ddma.dev, "%s:%d Can't to create channels for DMAC!\n",
1935 __func__, __LINE__);
1936 dma_free_attrs(pl330->ddma.dev,
1937 chans * pl330->mcbufsz,
1938 pl330->mcode_cpu, pl330->mcode_bus,
1939 DMA_ATTR_PRIVILEGED);
1940 return ret;
1941 }
1942
1943 return 0;
1944}
1945
1946static int pl330_add(struct pl330_dmac *pl330)
1947{
1948 int i, ret;
1949
1950 /* Check if we can handle this DMAC */
1951 if ((pl330->pcfg.periph_id & 0xfffff) != PERIPH_ID_VAL) {
1952 dev_err(pl330->ddma.dev, "PERIPH_ID 0x%x !\n",
1953 pl330->pcfg.periph_id);
1954 return -EINVAL;
1955 }
1956
1957 /* Read the configuration of the DMAC */
1958 read_dmac_config(pl330);
1959
1960 if (pl330->pcfg.num_events == 0) {
1961 dev_err(pl330->ddma.dev, "%s:%d Can't work without events!\n",
1962 __func__, __LINE__);
1963 return -EINVAL;
1964 }
1965
1966 spin_lock_init(&pl330->lock);
1967
1968 INIT_LIST_HEAD(&pl330->req_done);
1969
1970 /* Use default MC buffer size if not provided */
1971 if (!pl330->mcbufsz)
1972 pl330->mcbufsz = MCODE_BUFF_PER_REQ * 2;
1973
1974 /* Mark all events as free */
1975 for (i = 0; i < pl330->pcfg.num_events; i++)
1976 pl330->events[i] = -1;
1977
1978 /* Allocate resources needed by the DMAC */
1979 ret = dmac_alloc_resources(pl330);
1980 if (ret) {
1981 dev_err(pl330->ddma.dev, "Unable to create channels for DMAC\n");
1982 return ret;
1983 }
1984
1985 tasklet_init(&pl330->tasks, pl330_dotask, (unsigned long) pl330);
1986
1987 pl330->state = INIT;
1988
1989 return 0;
1990}
1991
1992static int dmac_free_threads(struct pl330_dmac *pl330)
1993{
1994 struct pl330_thread *thrd;
1995 int i;
1996
1997 /* Release Channel threads */
1998 for (i = 0; i < pl330->pcfg.num_chan; i++) {
1999 thrd = &pl330->channels[i];
2000 pl330_release_channel(thrd);
2001 }
2002
2003 /* Free memory */
2004 kfree(pl330->channels);
2005
2006 return 0;
2007}
2008
2009static void pl330_del(struct pl330_dmac *pl330)
2010{
2011 pl330->state = UNINIT;
2012
2013 tasklet_kill(&pl330->tasks);
2014
2015 /* Free DMAC resources */
2016 dmac_free_threads(pl330);
2017
2018 dma_free_attrs(pl330->ddma.dev,
2019 pl330->pcfg.num_chan * pl330->mcbufsz, pl330->mcode_cpu,
2020 pl330->mcode_bus, DMA_ATTR_PRIVILEGED);
2021}
2022
2023/* forward declaration */
2024static struct amba_driver pl330_driver;
2025
2026static inline struct dma_pl330_chan *
2027to_pchan(struct dma_chan *ch)
2028{
2029 if (!ch)
2030 return NULL;
2031
2032 return container_of(ch, struct dma_pl330_chan, chan);
2033}
2034
2035static inline struct dma_pl330_desc *
2036to_desc(struct dma_async_tx_descriptor *tx)
2037{
2038 return container_of(tx, struct dma_pl330_desc, txd);
2039}
2040
2041static inline void fill_queue(struct dma_pl330_chan *pch)
2042{
2043 struct dma_pl330_desc *desc;
2044 int ret;
2045
2046 list_for_each_entry(desc, &pch->work_list, node) {
2047
2048 /* If already submitted */
2049 if (desc->status == BUSY)
2050 continue;
2051
2052 ret = pl330_submit_req(pch->thread, desc);
2053 if (!ret) {
2054 desc->status = BUSY;
2055 } else if (ret == -EAGAIN) {
2056 /* QFull or DMAC Dying */
2057 break;
2058 } else {
2059 /* Unacceptable request */
2060 desc->status = DONE;
2061 dev_err(pch->dmac->ddma.dev, "%s:%d Bad Desc(%d)\n",
2062 __func__, __LINE__, desc->txd.cookie);
2063 tasklet_schedule(&pch->task);
2064 }
2065 }
2066}
2067
2068static void pl330_tasklet(unsigned long data)
2069{
2070 struct dma_pl330_chan *pch = (struct dma_pl330_chan *)data;
2071 struct dma_pl330_desc *desc, *_dt;
2072 unsigned long flags;
2073 bool power_down = false;
2074
2075 spin_lock_irqsave(&pch->lock, flags);
2076
2077 /* Pick up ripe tomatoes */
2078 list_for_each_entry_safe(desc, _dt, &pch->work_list, node)
2079 if (desc->status == DONE) {
2080 if (!pch->cyclic)
2081 dma_cookie_complete(&desc->txd);
2082 list_move_tail(&desc->node, &pch->completed_list);
2083 }
2084
2085 /* Try to submit a req imm. next to the last completed cookie */
2086 fill_queue(pch);
2087
2088 if (list_empty(&pch->work_list)) {
2089 spin_lock(&pch->thread->dmac->lock);
2090 _stop(pch->thread);
2091 spin_unlock(&pch->thread->dmac->lock);
2092 power_down = true;
2093 pch->active = false;
2094 } else {
2095 /* Make sure the PL330 Channel thread is active */
2096 spin_lock(&pch->thread->dmac->lock);
2097 _start(pch->thread);
2098 spin_unlock(&pch->thread->dmac->lock);
2099 }
2100
2101 while (!list_empty(&pch->completed_list)) {
2102 struct dmaengine_desc_callback cb;
2103
2104 desc = list_first_entry(&pch->completed_list,
2105 struct dma_pl330_desc, node);
2106
2107 dmaengine_desc_get_callback(&desc->txd, &cb);
2108
2109 if (pch->cyclic) {
2110 desc->status = PREP;
2111 list_move_tail(&desc->node, &pch->work_list);
2112 if (power_down) {
2113 pch->active = true;
2114 spin_lock(&pch->thread->dmac->lock);
2115 _start(pch->thread);
2116 spin_unlock(&pch->thread->dmac->lock);
2117 power_down = false;
2118 }
2119 } else {
2120 desc->status = FREE;
2121 list_move_tail(&desc->node, &pch->dmac->desc_pool);
2122 }
2123
2124 dma_descriptor_unmap(&desc->txd);
2125
2126 if (dmaengine_desc_callback_valid(&cb)) {
2127 spin_unlock_irqrestore(&pch->lock, flags);
2128 dmaengine_desc_callback_invoke(&cb, NULL);
2129 spin_lock_irqsave(&pch->lock, flags);
2130 }
2131 }
2132 spin_unlock_irqrestore(&pch->lock, flags);
2133
2134 /* If work list empty, power down */
2135 if (power_down) {
2136 pm_runtime_mark_last_busy(pch->dmac->ddma.dev);
2137 pm_runtime_put_autosuspend(pch->dmac->ddma.dev);
2138 }
2139}
2140
2141static struct dma_chan *of_dma_pl330_xlate(struct of_phandle_args *dma_spec,
2142 struct of_dma *ofdma)
2143{
2144 int count = dma_spec->args_count;
2145 struct pl330_dmac *pl330 = ofdma->of_dma_data;
2146 unsigned int chan_id;
2147
2148 if (!pl330)
2149 return NULL;
2150
2151 if (count != 1)
2152 return NULL;
2153
2154 chan_id = dma_spec->args[0];
2155 if (chan_id >= pl330->num_peripherals)
2156 return NULL;
2157
2158 return dma_get_slave_channel(&pl330->peripherals[chan_id].chan);
2159}
2160
2161static int pl330_alloc_chan_resources(struct dma_chan *chan)
2162{
2163 struct dma_pl330_chan *pch = to_pchan(chan);
2164 struct pl330_dmac *pl330 = pch->dmac;
2165 unsigned long flags;
2166
2167 spin_lock_irqsave(&pl330->lock, flags);
2168
2169 dma_cookie_init(chan);
2170 pch->cyclic = false;
2171
2172 pch->thread = pl330_request_channel(pl330);
2173 if (!pch->thread) {
2174 spin_unlock_irqrestore(&pl330->lock, flags);
2175 return -ENOMEM;
2176 }
2177
2178 tasklet_init(&pch->task, pl330_tasklet, (unsigned long) pch);
2179
2180 spin_unlock_irqrestore(&pl330->lock, flags);
2181
2182 return 1;
2183}
2184
2185/*
2186 * We need the data direction between the DMAC (the dma-mapping "device") and
2187 * the FIFO (the dmaengine "dev"), from the FIFO's point of view. Confusing!
2188 */
2189static enum dma_data_direction
2190pl330_dma_slave_map_dir(enum dma_transfer_direction dir)
2191{
2192 switch (dir) {
2193 case DMA_MEM_TO_DEV:
2194 return DMA_FROM_DEVICE;
2195 case DMA_DEV_TO_MEM:
2196 return DMA_TO_DEVICE;
2197 case DMA_DEV_TO_DEV:
2198 return DMA_BIDIRECTIONAL;
2199 default:
2200 return DMA_NONE;
2201 }
2202}
2203
2204static void pl330_unprep_slave_fifo(struct dma_pl330_chan *pch)
2205{
2206 if (pch->dir != DMA_NONE)
2207 dma_unmap_resource(pch->chan.device->dev, pch->fifo_dma,
2208 1 << pch->burst_sz, pch->dir, 0);
2209 pch->dir = DMA_NONE;
2210}
2211
2212
2213static bool pl330_prep_slave_fifo(struct dma_pl330_chan *pch,
2214 enum dma_transfer_direction dir)
2215{
2216 struct device *dev = pch->chan.device->dev;
2217 enum dma_data_direction dma_dir = pl330_dma_slave_map_dir(dir);
2218
2219 /* Already mapped for this config? */
2220 if (pch->dir == dma_dir)
2221 return true;
2222
2223 pl330_unprep_slave_fifo(pch);
2224 pch->fifo_dma = dma_map_resource(dev, pch->fifo_addr,
2225 1 << pch->burst_sz, dma_dir, 0);
2226 if (dma_mapping_error(dev, pch->fifo_dma))
2227 return false;
2228
2229 pch->dir = dma_dir;
2230 return true;
2231}
2232
2233static int fixup_burst_len(int max_burst_len, int quirks)
2234{
2235 if (max_burst_len > PL330_MAX_BURST)
2236 return PL330_MAX_BURST;
2237 else if (max_burst_len < 1)
2238 return 1;
2239 else
2240 return max_burst_len;
2241}
2242
2243static int pl330_config_write(struct dma_chan *chan,
2244 struct dma_slave_config *slave_config,
2245 enum dma_transfer_direction direction)
2246{
2247 struct dma_pl330_chan *pch = to_pchan(chan);
2248
2249 pl330_unprep_slave_fifo(pch);
2250 if (direction == DMA_MEM_TO_DEV) {
2251 if (slave_config->dst_addr)
2252 pch->fifo_addr = slave_config->dst_addr;
2253 if (slave_config->dst_addr_width)
2254 pch->burst_sz = __ffs(slave_config->dst_addr_width);
2255 pch->burst_len = fixup_burst_len(slave_config->dst_maxburst,
2256 pch->dmac->quirks);
2257 } else if (direction == DMA_DEV_TO_MEM) {
2258 if (slave_config->src_addr)
2259 pch->fifo_addr = slave_config->src_addr;
2260 if (slave_config->src_addr_width)
2261 pch->burst_sz = __ffs(slave_config->src_addr_width);
2262 pch->burst_len = fixup_burst_len(slave_config->src_maxburst,
2263 pch->dmac->quirks);
2264 }
2265
2266 return 0;
2267}
2268
2269static int pl330_config(struct dma_chan *chan,
2270 struct dma_slave_config *slave_config)
2271{
2272 struct dma_pl330_chan *pch = to_pchan(chan);
2273
2274 memcpy(&pch->slave_config, slave_config, sizeof(*slave_config));
2275
2276 return 0;
2277}
2278
2279static int pl330_terminate_all(struct dma_chan *chan)
2280{
2281 struct dma_pl330_chan *pch = to_pchan(chan);
2282 struct dma_pl330_desc *desc;
2283 unsigned long flags;
2284 struct pl330_dmac *pl330 = pch->dmac;
2285 bool power_down = false;
2286
2287 pm_runtime_get_sync(pl330->ddma.dev);
2288 spin_lock_irqsave(&pch->lock, flags);
2289
2290 spin_lock(&pl330->lock);
2291 _stop(pch->thread);
2292 pch->thread->req[0].desc = NULL;
2293 pch->thread->req[1].desc = NULL;
2294 pch->thread->req_running = -1;
2295 spin_unlock(&pl330->lock);
2296
2297 power_down = pch->active;
2298 pch->active = false;
2299
2300 /* Mark all desc done */
2301 list_for_each_entry(desc, &pch->submitted_list, node) {
2302 desc->status = FREE;
2303 dma_cookie_complete(&desc->txd);
2304 }
2305
2306 list_for_each_entry(desc, &pch->work_list , node) {
2307 desc->status = FREE;
2308 dma_cookie_complete(&desc->txd);
2309 }
2310
2311 list_splice_tail_init(&pch->submitted_list, &pl330->desc_pool);
2312 list_splice_tail_init(&pch->work_list, &pl330->desc_pool);
2313 list_splice_tail_init(&pch->completed_list, &pl330->desc_pool);
2314 spin_unlock_irqrestore(&pch->lock, flags);
2315 pm_runtime_mark_last_busy(pl330->ddma.dev);
2316 if (power_down)
2317 pm_runtime_put_autosuspend(pl330->ddma.dev);
2318 pm_runtime_put_autosuspend(pl330->ddma.dev);
2319
2320 return 0;
2321}
2322
2323/*
2324 * We don't support DMA_RESUME command because of hardware
2325 * limitations, so after pausing the channel we cannot restore
2326 * it to active state. We have to terminate channel and setup
2327 * DMA transfer again. This pause feature was implemented to
2328 * allow safely read residue before channel termination.
2329 */
2330static int pl330_pause(struct dma_chan *chan)
2331{
2332 struct dma_pl330_chan *pch = to_pchan(chan);
2333 struct pl330_dmac *pl330 = pch->dmac;
2334 unsigned long flags;
2335
2336 pm_runtime_get_sync(pl330->ddma.dev);
2337 spin_lock_irqsave(&pch->lock, flags);
2338
2339 spin_lock(&pl330->lock);
2340 _stop(pch->thread);
2341 spin_unlock(&pl330->lock);
2342
2343 spin_unlock_irqrestore(&pch->lock, flags);
2344 pm_runtime_mark_last_busy(pl330->ddma.dev);
2345 pm_runtime_put_autosuspend(pl330->ddma.dev);
2346
2347 return 0;
2348}
2349
2350static void pl330_free_chan_resources(struct dma_chan *chan)
2351{
2352 struct dma_pl330_chan *pch = to_pchan(chan);
2353 struct pl330_dmac *pl330 = pch->dmac;
2354 unsigned long flags;
2355
2356 tasklet_kill(&pch->task);
2357
2358 pm_runtime_get_sync(pch->dmac->ddma.dev);
2359 spin_lock_irqsave(&pl330->lock, flags);
2360
2361 pl330_release_channel(pch->thread);
2362 pch->thread = NULL;
2363
2364 if (pch->cyclic)
2365 list_splice_tail_init(&pch->work_list, &pch->dmac->desc_pool);
2366
2367 spin_unlock_irqrestore(&pl330->lock, flags);
2368 pm_runtime_mark_last_busy(pch->dmac->ddma.dev);
2369 pm_runtime_put_autosuspend(pch->dmac->ddma.dev);
2370 pl330_unprep_slave_fifo(pch);
2371}
2372
2373static int pl330_get_current_xferred_count(struct dma_pl330_chan *pch,
2374 struct dma_pl330_desc *desc)
2375{
2376 struct pl330_thread *thrd = pch->thread;
2377 struct pl330_dmac *pl330 = pch->dmac;
2378 void __iomem *regs = thrd->dmac->base;
2379 u32 val, addr;
2380
2381 pm_runtime_get_sync(pl330->ddma.dev);
2382 val = addr = 0;
2383 if (desc->rqcfg.src_inc) {
2384 val = readl(regs + SA(thrd->id));
2385 addr = desc->px.src_addr;
2386 } else {
2387 val = readl(regs + DA(thrd->id));
2388 addr = desc->px.dst_addr;
2389 }
2390 pm_runtime_mark_last_busy(pch->dmac->ddma.dev);
2391 pm_runtime_put_autosuspend(pl330->ddma.dev);
2392
2393 /* If DMAMOV hasn't finished yet, SAR/DAR can be zero */
2394 if (!val)
2395 return 0;
2396
2397 return val - addr;
2398}
2399
2400static enum dma_status
2401pl330_tx_status(struct dma_chan *chan, dma_cookie_t cookie,
2402 struct dma_tx_state *txstate)
2403{
2404 enum dma_status ret;
2405 unsigned long flags;
2406 struct dma_pl330_desc *desc, *running = NULL, *last_enq = NULL;
2407 struct dma_pl330_chan *pch = to_pchan(chan);
2408 unsigned int transferred, residual = 0;
2409
2410 ret = dma_cookie_status(chan, cookie, txstate);
2411
2412 if (!txstate)
2413 return ret;
2414
2415 if (ret == DMA_COMPLETE)
2416 goto out;
2417
2418 spin_lock_irqsave(&pch->lock, flags);
2419 spin_lock(&pch->thread->dmac->lock);
2420
2421 if (pch->thread->req_running != -1)
2422 running = pch->thread->req[pch->thread->req_running].desc;
2423
2424 last_enq = pch->thread->req[pch->thread->lstenq].desc;
2425
2426 /* Check in pending list */
2427 list_for_each_entry(desc, &pch->work_list, node) {
2428 if (desc->status == DONE)
2429 transferred = desc->bytes_requested;
2430 else if (running && desc == running)
2431 transferred =
2432 pl330_get_current_xferred_count(pch, desc);
2433 else if (desc->status == BUSY)
2434 /*
2435 * Busy but not running means either just enqueued,
2436 * or finished and not yet marked done
2437 */
2438 if (desc == last_enq)
2439 transferred = 0;
2440 else
2441 transferred = desc->bytes_requested;
2442 else
2443 transferred = 0;
2444 residual += desc->bytes_requested - transferred;
2445 if (desc->txd.cookie == cookie) {
2446 switch (desc->status) {
2447 case DONE:
2448 ret = DMA_COMPLETE;
2449 break;
2450 case PREP:
2451 case BUSY:
2452 ret = DMA_IN_PROGRESS;
2453 break;
2454 default:
2455 WARN_ON(1);
2456 }
2457 break;
2458 }
2459 if (desc->last)
2460 residual = 0;
2461 }
2462 spin_unlock(&pch->thread->dmac->lock);
2463 spin_unlock_irqrestore(&pch->lock, flags);
2464
2465out:
2466 dma_set_residue(txstate, residual);
2467
2468 return ret;
2469}
2470
2471static void pl330_issue_pending(struct dma_chan *chan)
2472{
2473 struct dma_pl330_chan *pch = to_pchan(chan);
2474 unsigned long flags;
2475
2476 spin_lock_irqsave(&pch->lock, flags);
2477 if (list_empty(&pch->work_list)) {
2478 /*
2479 * Warn on nothing pending. Empty submitted_list may
2480 * break our pm_runtime usage counter as it is
2481 * updated on work_list emptiness status.
2482 */
2483 WARN_ON(list_empty(&pch->submitted_list));
2484 pch->active = true;
2485 pm_runtime_get_sync(pch->dmac->ddma.dev);
2486 }
2487 list_splice_tail_init(&pch->submitted_list, &pch->work_list);
2488 spin_unlock_irqrestore(&pch->lock, flags);
2489
2490 pl330_tasklet((unsigned long)pch);
2491}
2492
2493/*
2494 * We returned the last one of the circular list of descriptor(s)
2495 * from prep_xxx, so the argument to submit corresponds to the last
2496 * descriptor of the list.
2497 */
2498static dma_cookie_t pl330_tx_submit(struct dma_async_tx_descriptor *tx)
2499{
2500 struct dma_pl330_desc *desc, *last = to_desc(tx);
2501 struct dma_pl330_chan *pch = to_pchan(tx->chan);
2502 dma_cookie_t cookie;
2503 unsigned long flags;
2504
2505 spin_lock_irqsave(&pch->lock, flags);
2506
2507 /* Assign cookies to all nodes */
2508 while (!list_empty(&last->node)) {
2509 desc = list_entry(last->node.next, struct dma_pl330_desc, node);
2510 if (pch->cyclic) {
2511 desc->txd.callback = last->txd.callback;
2512 desc->txd.callback_param = last->txd.callback_param;
2513 }
2514 desc->last = false;
2515
2516 dma_cookie_assign(&desc->txd);
2517
2518 list_move_tail(&desc->node, &pch->submitted_list);
2519 }
2520
2521 last->last = true;
2522 cookie = dma_cookie_assign(&last->txd);
2523 list_add_tail(&last->node, &pch->submitted_list);
2524 spin_unlock_irqrestore(&pch->lock, flags);
2525
2526 return cookie;
2527}
2528
2529static inline void _init_desc(struct dma_pl330_desc *desc)
2530{
2531 desc->rqcfg.swap = SWAP_NO;
2532 desc->rqcfg.scctl = CCTRL0;
2533 desc->rqcfg.dcctl = CCTRL0;
2534 desc->txd.tx_submit = pl330_tx_submit;
2535
2536 INIT_LIST_HEAD(&desc->node);
2537}
2538
2539/* Returns the number of descriptors added to the DMAC pool */
2540static int add_desc(struct list_head *pool, spinlock_t *lock,
2541 gfp_t flg, int count)
2542{
2543 struct dma_pl330_desc *desc;
2544 unsigned long flags;
2545 int i;
2546
2547 desc = kcalloc(count, sizeof(*desc), flg);
2548 if (!desc)
2549 return 0;
2550
2551 spin_lock_irqsave(lock, flags);
2552
2553 for (i = 0; i < count; i++) {
2554 _init_desc(&desc[i]);
2555 list_add_tail(&desc[i].node, pool);
2556 }
2557
2558 spin_unlock_irqrestore(lock, flags);
2559
2560 return count;
2561}
2562
2563static struct dma_pl330_desc *pluck_desc(struct list_head *pool,
2564 spinlock_t *lock)
2565{
2566 struct dma_pl330_desc *desc = NULL;
2567 unsigned long flags;
2568
2569 spin_lock_irqsave(lock, flags);
2570
2571 if (!list_empty(pool)) {
2572 desc = list_entry(pool->next,
2573 struct dma_pl330_desc, node);
2574
2575 list_del_init(&desc->node);
2576
2577 desc->status = PREP;
2578 desc->txd.callback = NULL;
2579 }
2580
2581 spin_unlock_irqrestore(lock, flags);
2582
2583 return desc;
2584}
2585
2586static struct dma_pl330_desc *pl330_get_desc(struct dma_pl330_chan *pch)
2587{
2588 struct pl330_dmac *pl330 = pch->dmac;
2589 u8 *peri_id = pch->chan.private;
2590 struct dma_pl330_desc *desc;
2591
2592 /* Pluck one desc from the pool of DMAC */
2593 desc = pluck_desc(&pl330->desc_pool, &pl330->pool_lock);
2594
2595 /* If the DMAC pool is empty, alloc new */
2596 if (!desc) {
2597 DEFINE_SPINLOCK(lock);
2598 LIST_HEAD(pool);
2599
2600 if (!add_desc(&pool, &lock, GFP_ATOMIC, 1))
2601 return NULL;
2602
2603 desc = pluck_desc(&pool, &lock);
2604 WARN_ON(!desc || !list_empty(&pool));
2605 }
2606
2607 /* Initialize the descriptor */
2608 desc->pchan = pch;
2609 desc->txd.cookie = 0;
2610 async_tx_ack(&desc->txd);
2611
2612 desc->peri = peri_id ? pch->chan.chan_id : 0;
2613 desc->rqcfg.pcfg = &pch->dmac->pcfg;
2614
2615 dma_async_tx_descriptor_init(&desc->txd, &pch->chan);
2616
2617 return desc;
2618}
2619
2620static inline void fill_px(struct pl330_xfer *px,
2621 dma_addr_t dst, dma_addr_t src, size_t len)
2622{
2623 px->bytes = len;
2624 px->dst_addr = dst;
2625 px->src_addr = src;
2626}
2627
2628static struct dma_pl330_desc *
2629__pl330_prep_dma_memcpy(struct dma_pl330_chan *pch, dma_addr_t dst,
2630 dma_addr_t src, size_t len)
2631{
2632 struct dma_pl330_desc *desc = pl330_get_desc(pch);
2633
2634 if (!desc) {
2635 dev_err(pch->dmac->ddma.dev, "%s:%d Unable to fetch desc\n",
2636 __func__, __LINE__);
2637 return NULL;
2638 }
2639
2640 /*
2641 * Ideally we should lookout for reqs bigger than
2642 * those that can be programmed with 256 bytes of
2643 * MC buffer, but considering a req size is seldom
2644 * going to be word-unaligned and more than 200MB,
2645 * we take it easy.
2646 * Also, should the limit is reached we'd rather
2647 * have the platform increase MC buffer size than
2648 * complicating this API driver.
2649 */
2650 fill_px(&desc->px, dst, src, len);
2651
2652 return desc;
2653}
2654
2655/* Call after fixing burst size */
2656static inline int get_burst_len(struct dma_pl330_desc *desc, size_t len)
2657{
2658 struct dma_pl330_chan *pch = desc->pchan;
2659 struct pl330_dmac *pl330 = pch->dmac;
2660 int burst_len;
2661
2662 burst_len = pl330->pcfg.data_bus_width / 8;
2663 burst_len *= pl330->pcfg.data_buf_dep / pl330->pcfg.num_chan;
2664 burst_len >>= desc->rqcfg.brst_size;
2665
2666 /* src/dst_burst_len can't be more than 16 */
2667 if (burst_len > PL330_MAX_BURST)
2668 burst_len = PL330_MAX_BURST;
2669
2670 return burst_len;
2671}
2672
2673static struct dma_async_tx_descriptor *pl330_prep_dma_cyclic(
2674 struct dma_chan *chan, dma_addr_t dma_addr, size_t len,
2675 size_t period_len, enum dma_transfer_direction direction,
2676 unsigned long flags)
2677{
2678 struct dma_pl330_desc *desc = NULL, *first = NULL;
2679 struct dma_pl330_chan *pch = to_pchan(chan);
2680 struct pl330_dmac *pl330 = pch->dmac;
2681 unsigned int i;
2682 dma_addr_t dst;
2683 dma_addr_t src;
2684
2685 if (len % period_len != 0)
2686 return NULL;
2687
2688 if (!is_slave_direction(direction)) {
2689 dev_err(pch->dmac->ddma.dev, "%s:%d Invalid dma direction\n",
2690 __func__, __LINE__);
2691 return NULL;
2692 }
2693
2694 pl330_config_write(chan, &pch->slave_config, direction);
2695
2696 if (!pl330_prep_slave_fifo(pch, direction))
2697 return NULL;
2698
2699 for (i = 0; i < len / period_len; i++) {
2700 desc = pl330_get_desc(pch);
2701 if (!desc) {
2702 dev_err(pch->dmac->ddma.dev, "%s:%d Unable to fetch desc\n",
2703 __func__, __LINE__);
2704
2705 if (!first)
2706 return NULL;
2707
2708 spin_lock_irqsave(&pl330->pool_lock, flags);
2709
2710 while (!list_empty(&first->node)) {
2711 desc = list_entry(first->node.next,
2712 struct dma_pl330_desc, node);
2713 list_move_tail(&desc->node, &pl330->desc_pool);
2714 }
2715
2716 list_move_tail(&first->node, &pl330->desc_pool);
2717
2718 spin_unlock_irqrestore(&pl330->pool_lock, flags);
2719
2720 return NULL;
2721 }
2722
2723 switch (direction) {
2724 case DMA_MEM_TO_DEV:
2725 desc->rqcfg.src_inc = 1;
2726 desc->rqcfg.dst_inc = 0;
2727 src = dma_addr;
2728 dst = pch->fifo_dma;
2729 break;
2730 case DMA_DEV_TO_MEM:
2731 desc->rqcfg.src_inc = 0;
2732 desc->rqcfg.dst_inc = 1;
2733 src = pch->fifo_dma;
2734 dst = dma_addr;
2735 break;
2736 default:
2737 break;
2738 }
2739
2740 desc->rqtype = direction;
2741 desc->rqcfg.brst_size = pch->burst_sz;
2742 desc->rqcfg.brst_len = pch->burst_len;
2743 desc->bytes_requested = period_len;
2744 fill_px(&desc->px, dst, src, period_len);
2745
2746 if (!first)
2747 first = desc;
2748 else
2749 list_add_tail(&desc->node, &first->node);
2750
2751 dma_addr += period_len;
2752 }
2753
2754 if (!desc)
2755 return NULL;
2756
2757 pch->cyclic = true;
2758 desc->txd.flags = flags;
2759
2760 return &desc->txd;
2761}
2762
2763static struct dma_async_tx_descriptor *
2764pl330_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dst,
2765 dma_addr_t src, size_t len, unsigned long flags)
2766{
2767 struct dma_pl330_desc *desc;
2768 struct dma_pl330_chan *pch = to_pchan(chan);
2769 struct pl330_dmac *pl330;
2770 int burst;
2771
2772 if (unlikely(!pch || !len))
2773 return NULL;
2774
2775 pl330 = pch->dmac;
2776
2777 desc = __pl330_prep_dma_memcpy(pch, dst, src, len);
2778 if (!desc)
2779 return NULL;
2780
2781 desc->rqcfg.src_inc = 1;
2782 desc->rqcfg.dst_inc = 1;
2783 desc->rqtype = DMA_MEM_TO_MEM;
2784
2785 /* Select max possible burst size */
2786 burst = pl330->pcfg.data_bus_width / 8;
2787
2788 /*
2789 * Make sure we use a burst size that aligns with all the memcpy
2790 * parameters because our DMA programming algorithm doesn't cope with
2791 * transfers which straddle an entry in the DMA device's MFIFO.
2792 */
2793 while ((src | dst | len) & (burst - 1))
2794 burst /= 2;
2795
2796 desc->rqcfg.brst_size = 0;
2797 while (burst != (1 << desc->rqcfg.brst_size))
2798 desc->rqcfg.brst_size++;
2799
2800 desc->rqcfg.brst_len = get_burst_len(desc, len);
2801 /*
2802 * If burst size is smaller than bus width then make sure we only
2803 * transfer one at a time to avoid a burst stradling an MFIFO entry.
2804 */
2805 if (desc->rqcfg.brst_size * 8 < pl330->pcfg.data_bus_width)
2806 desc->rqcfg.brst_len = 1;
2807
2808 desc->bytes_requested = len;
2809
2810 desc->txd.flags = flags;
2811
2812 return &desc->txd;
2813}
2814
2815static void __pl330_giveback_desc(struct pl330_dmac *pl330,
2816 struct dma_pl330_desc *first)
2817{
2818 unsigned long flags;
2819 struct dma_pl330_desc *desc;
2820
2821 if (!first)
2822 return;
2823
2824 spin_lock_irqsave(&pl330->pool_lock, flags);
2825
2826 while (!list_empty(&first->node)) {
2827 desc = list_entry(first->node.next,
2828 struct dma_pl330_desc, node);
2829 list_move_tail(&desc->node, &pl330->desc_pool);
2830 }
2831
2832 list_move_tail(&first->node, &pl330->desc_pool);
2833
2834 spin_unlock_irqrestore(&pl330->pool_lock, flags);
2835}
2836
2837static struct dma_async_tx_descriptor *
2838pl330_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
2839 unsigned int sg_len, enum dma_transfer_direction direction,
2840 unsigned long flg, void *context)
2841{
2842 struct dma_pl330_desc *first, *desc = NULL;
2843 struct dma_pl330_chan *pch = to_pchan(chan);
2844 struct scatterlist *sg;
2845 int i;
2846
2847 if (unlikely(!pch || !sgl || !sg_len))
2848 return NULL;
2849
2850 pl330_config_write(chan, &pch->slave_config, direction);
2851
2852 if (!pl330_prep_slave_fifo(pch, direction))
2853 return NULL;
2854
2855 first = NULL;
2856
2857 for_each_sg(sgl, sg, sg_len, i) {
2858
2859 desc = pl330_get_desc(pch);
2860 if (!desc) {
2861 struct pl330_dmac *pl330 = pch->dmac;
2862
2863 dev_err(pch->dmac->ddma.dev,
2864 "%s:%d Unable to fetch desc\n",
2865 __func__, __LINE__);
2866 __pl330_giveback_desc(pl330, first);
2867
2868 return NULL;
2869 }
2870
2871 if (!first)
2872 first = desc;
2873 else
2874 list_add_tail(&desc->node, &first->node);
2875
2876 if (direction == DMA_MEM_TO_DEV) {
2877 desc->rqcfg.src_inc = 1;
2878 desc->rqcfg.dst_inc = 0;
2879 fill_px(&desc->px, pch->fifo_dma, sg_dma_address(sg),
2880 sg_dma_len(sg));
2881 } else {
2882 desc->rqcfg.src_inc = 0;
2883 desc->rqcfg.dst_inc = 1;
2884 fill_px(&desc->px, sg_dma_address(sg), pch->fifo_dma,
2885 sg_dma_len(sg));
2886 }
2887
2888 desc->rqcfg.brst_size = pch->burst_sz;
2889 desc->rqcfg.brst_len = pch->burst_len;
2890 desc->rqtype = direction;
2891 desc->bytes_requested = sg_dma_len(sg);
2892 }
2893
2894 /* Return the last desc in the chain */
2895 desc->txd.flags = flg;
2896 return &desc->txd;
2897}
2898
2899static irqreturn_t pl330_irq_handler(int irq, void *data)
2900{
2901 if (pl330_update(data))
2902 return IRQ_HANDLED;
2903 else
2904 return IRQ_NONE;
2905}
2906
2907#define PL330_DMA_BUSWIDTHS \
2908 BIT(DMA_SLAVE_BUSWIDTH_UNDEFINED) | \
2909 BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | \
2910 BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | \
2911 BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) | \
2912 BIT(DMA_SLAVE_BUSWIDTH_8_BYTES)
2913
2914#ifdef CONFIG_DEBUG_FS
2915static int pl330_debugfs_show(struct seq_file *s, void *data)
2916{
2917 struct pl330_dmac *pl330 = s->private;
2918 int chans, pchs, ch, pr;
2919
2920 chans = pl330->pcfg.num_chan;
2921 pchs = pl330->num_peripherals;
2922
2923 seq_puts(s, "PL330 physical channels:\n");
2924 seq_puts(s, "THREAD:\t\tCHANNEL:\n");
2925 seq_puts(s, "--------\t-----\n");
2926 for (ch = 0; ch < chans; ch++) {
2927 struct pl330_thread *thrd = &pl330->channels[ch];
2928 int found = -1;
2929
2930 for (pr = 0; pr < pchs; pr++) {
2931 struct dma_pl330_chan *pch = &pl330->peripherals[pr];
2932
2933 if (!pch->thread || thrd->id != pch->thread->id)
2934 continue;
2935
2936 found = pr;
2937 }
2938
2939 seq_printf(s, "%d\t\t", thrd->id);
2940 if (found == -1)
2941 seq_puts(s, "--\n");
2942 else
2943 seq_printf(s, "%d\n", found);
2944 }
2945
2946 return 0;
2947}
2948
2949DEFINE_SHOW_ATTRIBUTE(pl330_debugfs);
2950
2951static inline void init_pl330_debugfs(struct pl330_dmac *pl330)
2952{
2953 debugfs_create_file(dev_name(pl330->ddma.dev),
2954 S_IFREG | 0444, NULL, pl330,
2955 &pl330_debugfs_fops);
2956}
2957#else
2958static inline void init_pl330_debugfs(struct pl330_dmac *pl330)
2959{
2960}
2961#endif
2962
2963/*
2964 * Runtime PM callbacks are provided by amba/bus.c driver.
2965 *
2966 * It is assumed here that IRQ safe runtime PM is chosen in probe and amba
2967 * bus driver will only disable/enable the clock in runtime PM callbacks.
2968 */
2969static int __maybe_unused pl330_suspend(struct device *dev)
2970{
2971 struct amba_device *pcdev = to_amba_device(dev);
2972
2973 pm_runtime_force_suspend(dev);
2974 amba_pclk_unprepare(pcdev);
2975
2976 return 0;
2977}
2978
2979static int __maybe_unused pl330_resume(struct device *dev)
2980{
2981 struct amba_device *pcdev = to_amba_device(dev);
2982 int ret;
2983
2984 ret = amba_pclk_prepare(pcdev);
2985 if (ret)
2986 return ret;
2987
2988 pm_runtime_force_resume(dev);
2989
2990 return ret;
2991}
2992
2993static const struct dev_pm_ops pl330_pm = {
2994 SET_LATE_SYSTEM_SLEEP_PM_OPS(pl330_suspend, pl330_resume)
2995};
2996
2997static int
2998pl330_probe(struct amba_device *adev, const struct amba_id *id)
2999{
3000 struct pl330_config *pcfg;
3001 struct pl330_dmac *pl330;
3002 struct dma_pl330_chan *pch, *_p;
3003 struct dma_device *pd;
3004 struct resource *res;
3005 int i, ret, irq;
3006 int num_chan;
3007 struct device_node *np = adev->dev.of_node;
3008
3009 ret = dma_set_mask_and_coherent(&adev->dev, DMA_BIT_MASK(32));
3010 if (ret)
3011 return ret;
3012
3013 /* Allocate a new DMAC and its Channels */
3014 pl330 = devm_kzalloc(&adev->dev, sizeof(*pl330), GFP_KERNEL);
3015 if (!pl330)
3016 return -ENOMEM;
3017
3018 pd = &pl330->ddma;
3019 pd->dev = &adev->dev;
3020
3021 pl330->mcbufsz = 0;
3022
3023 /* get quirk */
3024 for (i = 0; i < ARRAY_SIZE(of_quirks); i++)
3025 if (of_property_read_bool(np, of_quirks[i].quirk))
3026 pl330->quirks |= of_quirks[i].id;
3027
3028 res = &adev->res;
3029 pl330->base = devm_ioremap_resource(&adev->dev, res);
3030 if (IS_ERR(pl330->base))
3031 return PTR_ERR(pl330->base);
3032
3033 amba_set_drvdata(adev, pl330);
3034
3035 pl330->rstc = devm_reset_control_get_optional(&adev->dev, "dma");
3036 if (IS_ERR(pl330->rstc)) {
3037 if (PTR_ERR(pl330->rstc) != -EPROBE_DEFER)
3038 dev_err(&adev->dev, "Failed to get reset!\n");
3039 return PTR_ERR(pl330->rstc);
3040 } else {
3041 ret = reset_control_deassert(pl330->rstc);
3042 if (ret) {
3043 dev_err(&adev->dev, "Couldn't deassert the device from reset!\n");
3044 return ret;
3045 }
3046 }
3047
3048 pl330->rstc_ocp = devm_reset_control_get_optional(&adev->dev, "dma-ocp");
3049 if (IS_ERR(pl330->rstc_ocp)) {
3050 if (PTR_ERR(pl330->rstc_ocp) != -EPROBE_DEFER)
3051 dev_err(&adev->dev, "Failed to get OCP reset!\n");
3052 return PTR_ERR(pl330->rstc_ocp);
3053 } else {
3054 ret = reset_control_deassert(pl330->rstc_ocp);
3055 if (ret) {
3056 dev_err(&adev->dev, "Couldn't deassert the device from OCP reset!\n");
3057 return ret;
3058 }
3059 }
3060
3061 for (i = 0; i < AMBA_NR_IRQS; i++) {
3062 irq = adev->irq[i];
3063 if (irq) {
3064 ret = devm_request_irq(&adev->dev, irq,
3065 pl330_irq_handler, 0,
3066 dev_name(&adev->dev), pl330);
3067 if (ret)
3068 return ret;
3069 } else {
3070 break;
3071 }
3072 }
3073
3074 pcfg = &pl330->pcfg;
3075
3076 pcfg->periph_id = adev->periphid;
3077 ret = pl330_add(pl330);
3078 if (ret)
3079 return ret;
3080
3081 INIT_LIST_HEAD(&pl330->desc_pool);
3082 spin_lock_init(&pl330->pool_lock);
3083
3084 /* Create a descriptor pool of default size */
3085 if (!add_desc(&pl330->desc_pool, &pl330->pool_lock,
3086 GFP_KERNEL, NR_DEFAULT_DESC))
3087 dev_warn(&adev->dev, "unable to allocate desc\n");
3088
3089 INIT_LIST_HEAD(&pd->channels);
3090
3091 /* Initialize channel parameters */
3092 num_chan = max_t(int, pcfg->num_peri, pcfg->num_chan);
3093
3094 pl330->num_peripherals = num_chan;
3095
3096 pl330->peripherals = kcalloc(num_chan, sizeof(*pch), GFP_KERNEL);
3097 if (!pl330->peripherals) {
3098 ret = -ENOMEM;
3099 goto probe_err2;
3100 }
3101
3102 for (i = 0; i < num_chan; i++) {
3103 pch = &pl330->peripherals[i];
3104
3105 pch->chan.private = adev->dev.of_node;
3106 INIT_LIST_HEAD(&pch->submitted_list);
3107 INIT_LIST_HEAD(&pch->work_list);
3108 INIT_LIST_HEAD(&pch->completed_list);
3109 spin_lock_init(&pch->lock);
3110 pch->thread = NULL;
3111 pch->chan.device = pd;
3112 pch->dmac = pl330;
3113 pch->dir = DMA_NONE;
3114
3115 /* Add the channel to the DMAC list */
3116 list_add_tail(&pch->chan.device_node, &pd->channels);
3117 }
3118
3119 dma_cap_set(DMA_MEMCPY, pd->cap_mask);
3120 if (pcfg->num_peri) {
3121 dma_cap_set(DMA_SLAVE, pd->cap_mask);
3122 dma_cap_set(DMA_CYCLIC, pd->cap_mask);
3123 dma_cap_set(DMA_PRIVATE, pd->cap_mask);
3124 }
3125
3126 pd->device_alloc_chan_resources = pl330_alloc_chan_resources;
3127 pd->device_free_chan_resources = pl330_free_chan_resources;
3128 pd->device_prep_dma_memcpy = pl330_prep_dma_memcpy;
3129 pd->device_prep_dma_cyclic = pl330_prep_dma_cyclic;
3130 pd->device_tx_status = pl330_tx_status;
3131 pd->device_prep_slave_sg = pl330_prep_slave_sg;
3132 pd->device_config = pl330_config;
3133 pd->device_pause = pl330_pause;
3134 pd->device_terminate_all = pl330_terminate_all;
3135 pd->device_issue_pending = pl330_issue_pending;
3136 pd->src_addr_widths = PL330_DMA_BUSWIDTHS;
3137 pd->dst_addr_widths = PL330_DMA_BUSWIDTHS;
3138 pd->directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV);
3139 pd->residue_granularity = DMA_RESIDUE_GRANULARITY_BURST;
3140 pd->max_burst = PL330_MAX_BURST;
3141
3142 ret = dma_async_device_register(pd);
3143 if (ret) {
3144 dev_err(&adev->dev, "unable to register DMAC\n");
3145 goto probe_err3;
3146 }
3147
3148 if (adev->dev.of_node) {
3149 ret = of_dma_controller_register(adev->dev.of_node,
3150 of_dma_pl330_xlate, pl330);
3151 if (ret) {
3152 dev_err(&adev->dev,
3153 "unable to register DMA to the generic DT DMA helpers\n");
3154 }
3155 }
3156
3157 adev->dev.dma_parms = &pl330->dma_parms;
3158
3159 /*
3160 * This is the limit for transfers with a buswidth of 1, larger
3161 * buswidths will have larger limits.
3162 */
3163 ret = dma_set_max_seg_size(&adev->dev, 1900800);
3164 if (ret)
3165 dev_err(&adev->dev, "unable to set the seg size\n");
3166
3167
3168 init_pl330_debugfs(pl330);
3169 dev_info(&adev->dev,
3170 "Loaded driver for PL330 DMAC-%x\n", adev->periphid);
3171 dev_info(&adev->dev,
3172 "\tDBUFF-%ux%ubytes Num_Chans-%u Num_Peri-%u Num_Events-%u\n",
3173 pcfg->data_buf_dep, pcfg->data_bus_width / 8, pcfg->num_chan,
3174 pcfg->num_peri, pcfg->num_events);
3175
3176 pm_runtime_irq_safe(&adev->dev);
3177 pm_runtime_use_autosuspend(&adev->dev);
3178 pm_runtime_set_autosuspend_delay(&adev->dev, PL330_AUTOSUSPEND_DELAY);
3179 pm_runtime_mark_last_busy(&adev->dev);
3180 pm_runtime_put_autosuspend(&adev->dev);
3181
3182 return 0;
3183probe_err3:
3184 /* Idle the DMAC */
3185 list_for_each_entry_safe(pch, _p, &pl330->ddma.channels,
3186 chan.device_node) {
3187
3188 /* Remove the channel */
3189 list_del(&pch->chan.device_node);
3190
3191 /* Flush the channel */
3192 if (pch->thread) {
3193 pl330_terminate_all(&pch->chan);
3194 pl330_free_chan_resources(&pch->chan);
3195 }
3196 }
3197probe_err2:
3198 pl330_del(pl330);
3199
3200 if (pl330->rstc_ocp)
3201 reset_control_assert(pl330->rstc_ocp);
3202
3203 if (pl330->rstc)
3204 reset_control_assert(pl330->rstc);
3205 return ret;
3206}
3207
3208static int pl330_remove(struct amba_device *adev)
3209{
3210 struct pl330_dmac *pl330 = amba_get_drvdata(adev);
3211 struct dma_pl330_chan *pch, *_p;
3212 int i, irq;
3213
3214 pm_runtime_get_noresume(pl330->ddma.dev);
3215
3216 if (adev->dev.of_node)
3217 of_dma_controller_free(adev->dev.of_node);
3218
3219 for (i = 0; i < AMBA_NR_IRQS; i++) {
3220 irq = adev->irq[i];
3221 if (irq)
3222 devm_free_irq(&adev->dev, irq, pl330);
3223 }
3224
3225 dma_async_device_unregister(&pl330->ddma);
3226
3227 /* Idle the DMAC */
3228 list_for_each_entry_safe(pch, _p, &pl330->ddma.channels,
3229 chan.device_node) {
3230
3231 /* Remove the channel */
3232 list_del(&pch->chan.device_node);
3233
3234 /* Flush the channel */
3235 if (pch->thread) {
3236 pl330_terminate_all(&pch->chan);
3237 pl330_free_chan_resources(&pch->chan);
3238 }
3239 }
3240
3241 pl330_del(pl330);
3242
3243 if (pl330->rstc_ocp)
3244 reset_control_assert(pl330->rstc_ocp);
3245
3246 if (pl330->rstc)
3247 reset_control_assert(pl330->rstc);
3248 return 0;
3249}
3250
3251static const struct amba_id pl330_ids[] = {
3252 {
3253 .id = 0x00041330,
3254 .mask = 0x000fffff,
3255 },
3256 { 0, 0 },
3257};
3258
3259MODULE_DEVICE_TABLE(amba, pl330_ids);
3260
3261static struct amba_driver pl330_driver = {
3262 .drv = {
3263 .owner = THIS_MODULE,
3264 .name = "dma-pl330",
3265 .pm = &pl330_pm,
3266 },
3267 .id_table = pl330_ids,
3268 .probe = pl330_probe,
3269 .remove = pl330_remove,
3270};
3271
3272module_amba_driver(pl330_driver);
3273
3274MODULE_AUTHOR("Jaswinder Singh <jassisinghbrar@gmail.com>");
3275MODULE_DESCRIPTION("API Driver for PL330 DMAC");
3276MODULE_LICENSE("GPL");
1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * Copyright (c) 2012 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * Copyright (C) 2010 Samsung Electronics Co. Ltd.
7 * Jaswinder Singh <jassi.brar@samsung.com>
8 */
9
10#include <linux/debugfs.h>
11#include <linux/kernel.h>
12#include <linux/io.h>
13#include <linux/init.h>
14#include <linux/slab.h>
15#include <linux/module.h>
16#include <linux/string.h>
17#include <linux/delay.h>
18#include <linux/interrupt.h>
19#include <linux/dma-mapping.h>
20#include <linux/dmaengine.h>
21#include <linux/amba/bus.h>
22#include <linux/scatterlist.h>
23#include <linux/of.h>
24#include <linux/of_dma.h>
25#include <linux/err.h>
26#include <linux/pm_runtime.h>
27#include <linux/bug.h>
28#include <linux/reset.h>
29
30#include "dmaengine.h"
31#define PL330_MAX_CHAN 8
32#define PL330_MAX_IRQS 32
33#define PL330_MAX_PERI 32
34#define PL330_MAX_BURST 16
35
36#define PL330_QUIRK_BROKEN_NO_FLUSHP BIT(0)
37#define PL330_QUIRK_PERIPH_BURST BIT(1)
38
39enum pl330_cachectrl {
40 CCTRL0, /* Noncacheable and nonbufferable */
41 CCTRL1, /* Bufferable only */
42 CCTRL2, /* Cacheable, but do not allocate */
43 CCTRL3, /* Cacheable and bufferable, but do not allocate */
44 INVALID1, /* AWCACHE = 0x1000 */
45 INVALID2,
46 CCTRL6, /* Cacheable write-through, allocate on writes only */
47 CCTRL7, /* Cacheable write-back, allocate on writes only */
48};
49
50enum pl330_byteswap {
51 SWAP_NO,
52 SWAP_2,
53 SWAP_4,
54 SWAP_8,
55 SWAP_16,
56};
57
58/* Register and Bit field Definitions */
59#define DS 0x0
60#define DS_ST_STOP 0x0
61#define DS_ST_EXEC 0x1
62#define DS_ST_CMISS 0x2
63#define DS_ST_UPDTPC 0x3
64#define DS_ST_WFE 0x4
65#define DS_ST_ATBRR 0x5
66#define DS_ST_QBUSY 0x6
67#define DS_ST_WFP 0x7
68#define DS_ST_KILL 0x8
69#define DS_ST_CMPLT 0x9
70#define DS_ST_FLTCMP 0xe
71#define DS_ST_FAULT 0xf
72
73#define DPC 0x4
74#define INTEN 0x20
75#define ES 0x24
76#define INTSTATUS 0x28
77#define INTCLR 0x2c
78#define FSM 0x30
79#define FSC 0x34
80#define FTM 0x38
81
82#define _FTC 0x40
83#define FTC(n) (_FTC + (n)*0x4)
84
85#define _CS 0x100
86#define CS(n) (_CS + (n)*0x8)
87#define CS_CNS (1 << 21)
88
89#define _CPC 0x104
90#define CPC(n) (_CPC + (n)*0x8)
91
92#define _SA 0x400
93#define SA(n) (_SA + (n)*0x20)
94
95#define _DA 0x404
96#define DA(n) (_DA + (n)*0x20)
97
98#define _CC 0x408
99#define CC(n) (_CC + (n)*0x20)
100
101#define CC_SRCINC (1 << 0)
102#define CC_DSTINC (1 << 14)
103#define CC_SRCPRI (1 << 8)
104#define CC_DSTPRI (1 << 22)
105#define CC_SRCNS (1 << 9)
106#define CC_DSTNS (1 << 23)
107#define CC_SRCIA (1 << 10)
108#define CC_DSTIA (1 << 24)
109#define CC_SRCBRSTLEN_SHFT 4
110#define CC_DSTBRSTLEN_SHFT 18
111#define CC_SRCBRSTSIZE_SHFT 1
112#define CC_DSTBRSTSIZE_SHFT 15
113#define CC_SRCCCTRL_SHFT 11
114#define CC_SRCCCTRL_MASK 0x7
115#define CC_DSTCCTRL_SHFT 25
116#define CC_DRCCCTRL_MASK 0x7
117#define CC_SWAP_SHFT 28
118
119#define _LC0 0x40c
120#define LC0(n) (_LC0 + (n)*0x20)
121
122#define _LC1 0x410
123#define LC1(n) (_LC1 + (n)*0x20)
124
125#define DBGSTATUS 0xd00
126#define DBG_BUSY (1 << 0)
127
128#define DBGCMD 0xd04
129#define DBGINST0 0xd08
130#define DBGINST1 0xd0c
131
132#define CR0 0xe00
133#define CR1 0xe04
134#define CR2 0xe08
135#define CR3 0xe0c
136#define CR4 0xe10
137#define CRD 0xe14
138
139#define PERIPH_ID 0xfe0
140#define PERIPH_REV_SHIFT 20
141#define PERIPH_REV_MASK 0xf
142#define PERIPH_REV_R0P0 0
143#define PERIPH_REV_R1P0 1
144#define PERIPH_REV_R1P1 2
145
146#define CR0_PERIPH_REQ_SET (1 << 0)
147#define CR0_BOOT_EN_SET (1 << 1)
148#define CR0_BOOT_MAN_NS (1 << 2)
149#define CR0_NUM_CHANS_SHIFT 4
150#define CR0_NUM_CHANS_MASK 0x7
151#define CR0_NUM_PERIPH_SHIFT 12
152#define CR0_NUM_PERIPH_MASK 0x1f
153#define CR0_NUM_EVENTS_SHIFT 17
154#define CR0_NUM_EVENTS_MASK 0x1f
155
156#define CR1_ICACHE_LEN_SHIFT 0
157#define CR1_ICACHE_LEN_MASK 0x7
158#define CR1_NUM_ICACHELINES_SHIFT 4
159#define CR1_NUM_ICACHELINES_MASK 0xf
160
161#define CRD_DATA_WIDTH_SHIFT 0
162#define CRD_DATA_WIDTH_MASK 0x7
163#define CRD_WR_CAP_SHIFT 4
164#define CRD_WR_CAP_MASK 0x7
165#define CRD_WR_Q_DEP_SHIFT 8
166#define CRD_WR_Q_DEP_MASK 0xf
167#define CRD_RD_CAP_SHIFT 12
168#define CRD_RD_CAP_MASK 0x7
169#define CRD_RD_Q_DEP_SHIFT 16
170#define CRD_RD_Q_DEP_MASK 0xf
171#define CRD_DATA_BUFF_SHIFT 20
172#define CRD_DATA_BUFF_MASK 0x3ff
173
174#define PART 0x330
175#define DESIGNER 0x41
176#define REVISION 0x0
177#define INTEG_CFG 0x0
178#define PERIPH_ID_VAL ((PART << 0) | (DESIGNER << 12))
179
180#define PL330_STATE_STOPPED (1 << 0)
181#define PL330_STATE_EXECUTING (1 << 1)
182#define PL330_STATE_WFE (1 << 2)
183#define PL330_STATE_FAULTING (1 << 3)
184#define PL330_STATE_COMPLETING (1 << 4)
185#define PL330_STATE_WFP (1 << 5)
186#define PL330_STATE_KILLING (1 << 6)
187#define PL330_STATE_FAULT_COMPLETING (1 << 7)
188#define PL330_STATE_CACHEMISS (1 << 8)
189#define PL330_STATE_UPDTPC (1 << 9)
190#define PL330_STATE_ATBARRIER (1 << 10)
191#define PL330_STATE_QUEUEBUSY (1 << 11)
192#define PL330_STATE_INVALID (1 << 15)
193
194#define PL330_STABLE_STATES (PL330_STATE_STOPPED | PL330_STATE_EXECUTING \
195 | PL330_STATE_WFE | PL330_STATE_FAULTING)
196
197#define CMD_DMAADDH 0x54
198#define CMD_DMAEND 0x00
199#define CMD_DMAFLUSHP 0x35
200#define CMD_DMAGO 0xa0
201#define CMD_DMALD 0x04
202#define CMD_DMALDP 0x25
203#define CMD_DMALP 0x20
204#define CMD_DMALPEND 0x28
205#define CMD_DMAKILL 0x01
206#define CMD_DMAMOV 0xbc
207#define CMD_DMANOP 0x18
208#define CMD_DMARMB 0x12
209#define CMD_DMASEV 0x34
210#define CMD_DMAST 0x08
211#define CMD_DMASTP 0x29
212#define CMD_DMASTZ 0x0c
213#define CMD_DMAWFE 0x36
214#define CMD_DMAWFP 0x30
215#define CMD_DMAWMB 0x13
216
217#define SZ_DMAADDH 3
218#define SZ_DMAEND 1
219#define SZ_DMAFLUSHP 2
220#define SZ_DMALD 1
221#define SZ_DMALDP 2
222#define SZ_DMALP 2
223#define SZ_DMALPEND 2
224#define SZ_DMAKILL 1
225#define SZ_DMAMOV 6
226#define SZ_DMANOP 1
227#define SZ_DMARMB 1
228#define SZ_DMASEV 2
229#define SZ_DMAST 1
230#define SZ_DMASTP 2
231#define SZ_DMASTZ 1
232#define SZ_DMAWFE 2
233#define SZ_DMAWFP 2
234#define SZ_DMAWMB 1
235#define SZ_DMAGO 6
236
237#define BRST_LEN(ccr) ((((ccr) >> CC_SRCBRSTLEN_SHFT) & 0xf) + 1)
238#define BRST_SIZE(ccr) (1 << (((ccr) >> CC_SRCBRSTSIZE_SHFT) & 0x7))
239
240#define BYTE_TO_BURST(b, ccr) ((b) / BRST_SIZE(ccr) / BRST_LEN(ccr))
241#define BURST_TO_BYTE(c, ccr) ((c) * BRST_SIZE(ccr) * BRST_LEN(ccr))
242
243/*
244 * With 256 bytes, we can do more than 2.5MB and 5MB xfers per req
245 * at 1byte/burst for P<->M and M<->M respectively.
246 * For typical scenario, at 1word/burst, 10MB and 20MB xfers per req
247 * should be enough for P<->M and M<->M respectively.
248 */
249#define MCODE_BUFF_PER_REQ 256
250
251/* Use this _only_ to wait on transient states */
252#define UNTIL(t, s) while (!(_state(t) & (s))) cpu_relax();
253
254#ifdef PL330_DEBUG_MCGEN
255static unsigned cmd_line;
256#define PL330_DBGCMD_DUMP(off, x...) do { \
257 printk("%x:", cmd_line); \
258 printk(KERN_CONT x); \
259 cmd_line += off; \
260 } while (0)
261#define PL330_DBGMC_START(addr) (cmd_line = addr)
262#else
263#define PL330_DBGCMD_DUMP(off, x...) do {} while (0)
264#define PL330_DBGMC_START(addr) do {} while (0)
265#endif
266
267/* The number of default descriptors */
268
269#define NR_DEFAULT_DESC 16
270
271/* Delay for runtime PM autosuspend, ms */
272#define PL330_AUTOSUSPEND_DELAY 20
273
274/* Populated by the PL330 core driver for DMA API driver's info */
275struct pl330_config {
276 u32 periph_id;
277#define DMAC_MODE_NS (1 << 0)
278 unsigned int mode;
279 unsigned int data_bus_width:10; /* In number of bits */
280 unsigned int data_buf_dep:11;
281 unsigned int num_chan:4;
282 unsigned int num_peri:6;
283 u32 peri_ns;
284 unsigned int num_events:6;
285 u32 irq_ns;
286};
287
288/*
289 * Request Configuration.
290 * The PL330 core does not modify this and uses the last
291 * working configuration if the request doesn't provide any.
292 *
293 * The Client may want to provide this info only for the
294 * first request and a request with new settings.
295 */
296struct pl330_reqcfg {
297 /* Address Incrementing */
298 unsigned dst_inc:1;
299 unsigned src_inc:1;
300
301 /*
302 * For now, the SRC & DST protection levels
303 * and burst size/length are assumed same.
304 */
305 bool nonsecure;
306 bool privileged;
307 bool insnaccess;
308 unsigned brst_len:5;
309 unsigned brst_size:3; /* in power of 2 */
310
311 enum pl330_cachectrl dcctl;
312 enum pl330_cachectrl scctl;
313 enum pl330_byteswap swap;
314 struct pl330_config *pcfg;
315};
316
317/*
318 * One cycle of DMAC operation.
319 * There may be more than one xfer in a request.
320 */
321struct pl330_xfer {
322 u32 src_addr;
323 u32 dst_addr;
324 /* Size to xfer */
325 u32 bytes;
326};
327
328/* The xfer callbacks are made with one of these arguments. */
329enum pl330_op_err {
330 /* The all xfers in the request were success. */
331 PL330_ERR_NONE,
332 /* If req aborted due to global error. */
333 PL330_ERR_ABORT,
334 /* If req failed due to problem with Channel. */
335 PL330_ERR_FAIL,
336};
337
338enum dmamov_dst {
339 SAR = 0,
340 CCR,
341 DAR,
342};
343
344enum pl330_dst {
345 SRC = 0,
346 DST,
347};
348
349enum pl330_cond {
350 SINGLE,
351 BURST,
352 ALWAYS,
353};
354
355struct dma_pl330_desc;
356
357struct _pl330_req {
358 u32 mc_bus;
359 void *mc_cpu;
360 struct dma_pl330_desc *desc;
361};
362
363/* ToBeDone for tasklet */
364struct _pl330_tbd {
365 bool reset_dmac;
366 bool reset_mngr;
367 u8 reset_chan;
368};
369
370/* A DMAC Thread */
371struct pl330_thread {
372 u8 id;
373 int ev;
374 /* If the channel is not yet acquired by any client */
375 bool free;
376 /* Parent DMAC */
377 struct pl330_dmac *dmac;
378 /* Only two at a time */
379 struct _pl330_req req[2];
380 /* Index of the last enqueued request */
381 unsigned lstenq;
382 /* Index of the last submitted request or -1 if the DMA is stopped */
383 int req_running;
384};
385
386enum pl330_dmac_state {
387 UNINIT,
388 INIT,
389 DYING,
390};
391
392enum desc_status {
393 /* In the DMAC pool */
394 FREE,
395 /*
396 * Allocated to some channel during prep_xxx
397 * Also may be sitting on the work_list.
398 */
399 PREP,
400 /*
401 * Sitting on the work_list and already submitted
402 * to the PL330 core. Not more than two descriptors
403 * of a channel can be BUSY at any time.
404 */
405 BUSY,
406 /*
407 * Sitting on the channel work_list but xfer done
408 * by PL330 core
409 */
410 DONE,
411};
412
413struct dma_pl330_chan {
414 /* Schedule desc completion */
415 struct tasklet_struct task;
416
417 /* DMA-Engine Channel */
418 struct dma_chan chan;
419
420 /* List of submitted descriptors */
421 struct list_head submitted_list;
422 /* List of issued descriptors */
423 struct list_head work_list;
424 /* List of completed descriptors */
425 struct list_head completed_list;
426
427 /* Pointer to the DMAC that manages this channel,
428 * NULL if the channel is available to be acquired.
429 * As the parent, this DMAC also provides descriptors
430 * to the channel.
431 */
432 struct pl330_dmac *dmac;
433
434 /* To protect channel manipulation */
435 spinlock_t lock;
436
437 /*
438 * Hardware channel thread of PL330 DMAC. NULL if the channel is
439 * available.
440 */
441 struct pl330_thread *thread;
442
443 /* For D-to-M and M-to-D channels */
444 int burst_sz; /* the peripheral fifo width */
445 int burst_len; /* the number of burst */
446 phys_addr_t fifo_addr;
447 /* DMA-mapped view of the FIFO; may differ if an IOMMU is present */
448 dma_addr_t fifo_dma;
449 enum dma_data_direction dir;
450 struct dma_slave_config slave_config;
451
452 /* for cyclic capability */
453 bool cyclic;
454
455 /* for runtime pm tracking */
456 bool active;
457};
458
459struct pl330_dmac {
460 /* DMA-Engine Device */
461 struct dma_device ddma;
462
463 /* Pool of descriptors available for the DMAC's channels */
464 struct list_head desc_pool;
465 /* To protect desc_pool manipulation */
466 spinlock_t pool_lock;
467
468 /* Size of MicroCode buffers for each channel. */
469 unsigned mcbufsz;
470 /* ioremap'ed address of PL330 registers. */
471 void __iomem *base;
472 /* Populated by the PL330 core driver during pl330_add */
473 struct pl330_config pcfg;
474
475 spinlock_t lock;
476 /* Maximum possible events/irqs */
477 int events[32];
478 /* BUS address of MicroCode buffer */
479 dma_addr_t mcode_bus;
480 /* CPU address of MicroCode buffer */
481 void *mcode_cpu;
482 /* List of all Channel threads */
483 struct pl330_thread *channels;
484 /* Pointer to the MANAGER thread */
485 struct pl330_thread *manager;
486 /* To handle bad news in interrupt */
487 struct tasklet_struct tasks;
488 struct _pl330_tbd dmac_tbd;
489 /* State of DMAC operation */
490 enum pl330_dmac_state state;
491 /* Holds list of reqs with due callbacks */
492 struct list_head req_done;
493
494 /* Peripheral channels connected to this DMAC */
495 unsigned int num_peripherals;
496 struct dma_pl330_chan *peripherals; /* keep at end */
497 int quirks;
498
499 struct reset_control *rstc;
500 struct reset_control *rstc_ocp;
501};
502
503static struct pl330_of_quirks {
504 char *quirk;
505 int id;
506} of_quirks[] = {
507 {
508 .quirk = "arm,pl330-broken-no-flushp",
509 .id = PL330_QUIRK_BROKEN_NO_FLUSHP,
510 },
511 {
512 .quirk = "arm,pl330-periph-burst",
513 .id = PL330_QUIRK_PERIPH_BURST,
514 }
515};
516
517struct dma_pl330_desc {
518 /* To attach to a queue as child */
519 struct list_head node;
520
521 /* Descriptor for the DMA Engine API */
522 struct dma_async_tx_descriptor txd;
523
524 /* Xfer for PL330 core */
525 struct pl330_xfer px;
526
527 struct pl330_reqcfg rqcfg;
528
529 enum desc_status status;
530
531 int bytes_requested;
532 bool last;
533
534 /* The channel which currently holds this desc */
535 struct dma_pl330_chan *pchan;
536
537 enum dma_transfer_direction rqtype;
538 /* Index of peripheral for the xfer. */
539 unsigned peri:5;
540 /* Hook to attach to DMAC's list of reqs with due callback */
541 struct list_head rqd;
542};
543
544struct _xfer_spec {
545 u32 ccr;
546 struct dma_pl330_desc *desc;
547};
548
549static int pl330_config_write(struct dma_chan *chan,
550 struct dma_slave_config *slave_config,
551 enum dma_transfer_direction direction);
552
553static inline bool _queue_full(struct pl330_thread *thrd)
554{
555 return thrd->req[0].desc != NULL && thrd->req[1].desc != NULL;
556}
557
558static inline bool is_manager(struct pl330_thread *thrd)
559{
560 return thrd->dmac->manager == thrd;
561}
562
563/* If manager of the thread is in Non-Secure mode */
564static inline bool _manager_ns(struct pl330_thread *thrd)
565{
566 return (thrd->dmac->pcfg.mode & DMAC_MODE_NS) ? true : false;
567}
568
569static inline u32 get_revision(u32 periph_id)
570{
571 return (periph_id >> PERIPH_REV_SHIFT) & PERIPH_REV_MASK;
572}
573
574static inline u32 _emit_END(unsigned dry_run, u8 buf[])
575{
576 if (dry_run)
577 return SZ_DMAEND;
578
579 buf[0] = CMD_DMAEND;
580
581 PL330_DBGCMD_DUMP(SZ_DMAEND, "\tDMAEND\n");
582
583 return SZ_DMAEND;
584}
585
586static inline u32 _emit_FLUSHP(unsigned dry_run, u8 buf[], u8 peri)
587{
588 if (dry_run)
589 return SZ_DMAFLUSHP;
590
591 buf[0] = CMD_DMAFLUSHP;
592
593 peri &= 0x1f;
594 peri <<= 3;
595 buf[1] = peri;
596
597 PL330_DBGCMD_DUMP(SZ_DMAFLUSHP, "\tDMAFLUSHP %u\n", peri >> 3);
598
599 return SZ_DMAFLUSHP;
600}
601
602static inline u32 _emit_LD(unsigned dry_run, u8 buf[], enum pl330_cond cond)
603{
604 if (dry_run)
605 return SZ_DMALD;
606
607 buf[0] = CMD_DMALD;
608
609 if (cond == SINGLE)
610 buf[0] |= (0 << 1) | (1 << 0);
611 else if (cond == BURST)
612 buf[0] |= (1 << 1) | (1 << 0);
613
614 PL330_DBGCMD_DUMP(SZ_DMALD, "\tDMALD%c\n",
615 cond == SINGLE ? 'S' : (cond == BURST ? 'B' : 'A'));
616
617 return SZ_DMALD;
618}
619
620static inline u32 _emit_LDP(unsigned dry_run, u8 buf[],
621 enum pl330_cond cond, u8 peri)
622{
623 if (dry_run)
624 return SZ_DMALDP;
625
626 buf[0] = CMD_DMALDP;
627
628 if (cond == BURST)
629 buf[0] |= (1 << 1);
630
631 peri &= 0x1f;
632 peri <<= 3;
633 buf[1] = peri;
634
635 PL330_DBGCMD_DUMP(SZ_DMALDP, "\tDMALDP%c %u\n",
636 cond == SINGLE ? 'S' : 'B', peri >> 3);
637
638 return SZ_DMALDP;
639}
640
641static inline u32 _emit_LP(unsigned dry_run, u8 buf[],
642 unsigned loop, u8 cnt)
643{
644 if (dry_run)
645 return SZ_DMALP;
646
647 buf[0] = CMD_DMALP;
648
649 if (loop)
650 buf[0] |= (1 << 1);
651
652 cnt--; /* DMAC increments by 1 internally */
653 buf[1] = cnt;
654
655 PL330_DBGCMD_DUMP(SZ_DMALP, "\tDMALP_%c %u\n", loop ? '1' : '0', cnt);
656
657 return SZ_DMALP;
658}
659
660struct _arg_LPEND {
661 enum pl330_cond cond;
662 bool forever;
663 unsigned loop;
664 u8 bjump;
665};
666
667static inline u32 _emit_LPEND(unsigned dry_run, u8 buf[],
668 const struct _arg_LPEND *arg)
669{
670 enum pl330_cond cond = arg->cond;
671 bool forever = arg->forever;
672 unsigned loop = arg->loop;
673 u8 bjump = arg->bjump;
674
675 if (dry_run)
676 return SZ_DMALPEND;
677
678 buf[0] = CMD_DMALPEND;
679
680 if (loop)
681 buf[0] |= (1 << 2);
682
683 if (!forever)
684 buf[0] |= (1 << 4);
685
686 if (cond == SINGLE)
687 buf[0] |= (0 << 1) | (1 << 0);
688 else if (cond == BURST)
689 buf[0] |= (1 << 1) | (1 << 0);
690
691 buf[1] = bjump;
692
693 PL330_DBGCMD_DUMP(SZ_DMALPEND, "\tDMALP%s%c_%c bjmpto_%x\n",
694 forever ? "FE" : "END",
695 cond == SINGLE ? 'S' : (cond == BURST ? 'B' : 'A'),
696 loop ? '1' : '0',
697 bjump);
698
699 return SZ_DMALPEND;
700}
701
702static inline u32 _emit_KILL(unsigned dry_run, u8 buf[])
703{
704 if (dry_run)
705 return SZ_DMAKILL;
706
707 buf[0] = CMD_DMAKILL;
708
709 return SZ_DMAKILL;
710}
711
712static inline u32 _emit_MOV(unsigned dry_run, u8 buf[],
713 enum dmamov_dst dst, u32 val)
714{
715 if (dry_run)
716 return SZ_DMAMOV;
717
718 buf[0] = CMD_DMAMOV;
719 buf[1] = dst;
720 buf[2] = val;
721 buf[3] = val >> 8;
722 buf[4] = val >> 16;
723 buf[5] = val >> 24;
724
725 PL330_DBGCMD_DUMP(SZ_DMAMOV, "\tDMAMOV %s 0x%x\n",
726 dst == SAR ? "SAR" : (dst == DAR ? "DAR" : "CCR"), val);
727
728 return SZ_DMAMOV;
729}
730
731static inline u32 _emit_RMB(unsigned dry_run, u8 buf[])
732{
733 if (dry_run)
734 return SZ_DMARMB;
735
736 buf[0] = CMD_DMARMB;
737
738 PL330_DBGCMD_DUMP(SZ_DMARMB, "\tDMARMB\n");
739
740 return SZ_DMARMB;
741}
742
743static inline u32 _emit_SEV(unsigned dry_run, u8 buf[], u8 ev)
744{
745 if (dry_run)
746 return SZ_DMASEV;
747
748 buf[0] = CMD_DMASEV;
749
750 ev &= 0x1f;
751 ev <<= 3;
752 buf[1] = ev;
753
754 PL330_DBGCMD_DUMP(SZ_DMASEV, "\tDMASEV %u\n", ev >> 3);
755
756 return SZ_DMASEV;
757}
758
759static inline u32 _emit_ST(unsigned dry_run, u8 buf[], enum pl330_cond cond)
760{
761 if (dry_run)
762 return SZ_DMAST;
763
764 buf[0] = CMD_DMAST;
765
766 if (cond == SINGLE)
767 buf[0] |= (0 << 1) | (1 << 0);
768 else if (cond == BURST)
769 buf[0] |= (1 << 1) | (1 << 0);
770
771 PL330_DBGCMD_DUMP(SZ_DMAST, "\tDMAST%c\n",
772 cond == SINGLE ? 'S' : (cond == BURST ? 'B' : 'A'));
773
774 return SZ_DMAST;
775}
776
777static inline u32 _emit_STP(unsigned dry_run, u8 buf[],
778 enum pl330_cond cond, u8 peri)
779{
780 if (dry_run)
781 return SZ_DMASTP;
782
783 buf[0] = CMD_DMASTP;
784
785 if (cond == BURST)
786 buf[0] |= (1 << 1);
787
788 peri &= 0x1f;
789 peri <<= 3;
790 buf[1] = peri;
791
792 PL330_DBGCMD_DUMP(SZ_DMASTP, "\tDMASTP%c %u\n",
793 cond == SINGLE ? 'S' : 'B', peri >> 3);
794
795 return SZ_DMASTP;
796}
797
798static inline u32 _emit_WFP(unsigned dry_run, u8 buf[],
799 enum pl330_cond cond, u8 peri)
800{
801 if (dry_run)
802 return SZ_DMAWFP;
803
804 buf[0] = CMD_DMAWFP;
805
806 if (cond == SINGLE)
807 buf[0] |= (0 << 1) | (0 << 0);
808 else if (cond == BURST)
809 buf[0] |= (1 << 1) | (0 << 0);
810 else
811 buf[0] |= (0 << 1) | (1 << 0);
812
813 peri &= 0x1f;
814 peri <<= 3;
815 buf[1] = peri;
816
817 PL330_DBGCMD_DUMP(SZ_DMAWFP, "\tDMAWFP%c %u\n",
818 cond == SINGLE ? 'S' : (cond == BURST ? 'B' : 'P'), peri >> 3);
819
820 return SZ_DMAWFP;
821}
822
823static inline u32 _emit_WMB(unsigned dry_run, u8 buf[])
824{
825 if (dry_run)
826 return SZ_DMAWMB;
827
828 buf[0] = CMD_DMAWMB;
829
830 PL330_DBGCMD_DUMP(SZ_DMAWMB, "\tDMAWMB\n");
831
832 return SZ_DMAWMB;
833}
834
835struct _arg_GO {
836 u8 chan;
837 u32 addr;
838 unsigned ns;
839};
840
841static inline u32 _emit_GO(unsigned dry_run, u8 buf[],
842 const struct _arg_GO *arg)
843{
844 u8 chan = arg->chan;
845 u32 addr = arg->addr;
846 unsigned ns = arg->ns;
847
848 if (dry_run)
849 return SZ_DMAGO;
850
851 buf[0] = CMD_DMAGO;
852 buf[0] |= (ns << 1);
853 buf[1] = chan & 0x7;
854 buf[2] = addr;
855 buf[3] = addr >> 8;
856 buf[4] = addr >> 16;
857 buf[5] = addr >> 24;
858
859 return SZ_DMAGO;
860}
861
862#define msecs_to_loops(t) (loops_per_jiffy / 1000 * HZ * t)
863
864/* Returns Time-Out */
865static bool _until_dmac_idle(struct pl330_thread *thrd)
866{
867 void __iomem *regs = thrd->dmac->base;
868 unsigned long loops = msecs_to_loops(5);
869
870 do {
871 /* Until Manager is Idle */
872 if (!(readl(regs + DBGSTATUS) & DBG_BUSY))
873 break;
874
875 cpu_relax();
876 } while (--loops);
877
878 if (!loops)
879 return true;
880
881 return false;
882}
883
884static inline void _execute_DBGINSN(struct pl330_thread *thrd,
885 u8 insn[], bool as_manager)
886{
887 void __iomem *regs = thrd->dmac->base;
888 u32 val;
889
890 /* If timed out due to halted state-machine */
891 if (_until_dmac_idle(thrd)) {
892 dev_err(thrd->dmac->ddma.dev, "DMAC halted!\n");
893 return;
894 }
895
896 val = (insn[0] << 16) | (insn[1] << 24);
897 if (!as_manager) {
898 val |= (1 << 0);
899 val |= (thrd->id << 8); /* Channel Number */
900 }
901 writel(val, regs + DBGINST0);
902
903 val = le32_to_cpu(*((__le32 *)&insn[2]));
904 writel(val, regs + DBGINST1);
905
906 /* Get going */
907 writel(0, regs + DBGCMD);
908}
909
910static inline u32 _state(struct pl330_thread *thrd)
911{
912 void __iomem *regs = thrd->dmac->base;
913 u32 val;
914
915 if (is_manager(thrd))
916 val = readl(regs + DS) & 0xf;
917 else
918 val = readl(regs + CS(thrd->id)) & 0xf;
919
920 switch (val) {
921 case DS_ST_STOP:
922 return PL330_STATE_STOPPED;
923 case DS_ST_EXEC:
924 return PL330_STATE_EXECUTING;
925 case DS_ST_CMISS:
926 return PL330_STATE_CACHEMISS;
927 case DS_ST_UPDTPC:
928 return PL330_STATE_UPDTPC;
929 case DS_ST_WFE:
930 return PL330_STATE_WFE;
931 case DS_ST_FAULT:
932 return PL330_STATE_FAULTING;
933 case DS_ST_ATBRR:
934 if (is_manager(thrd))
935 return PL330_STATE_INVALID;
936 else
937 return PL330_STATE_ATBARRIER;
938 case DS_ST_QBUSY:
939 if (is_manager(thrd))
940 return PL330_STATE_INVALID;
941 else
942 return PL330_STATE_QUEUEBUSY;
943 case DS_ST_WFP:
944 if (is_manager(thrd))
945 return PL330_STATE_INVALID;
946 else
947 return PL330_STATE_WFP;
948 case DS_ST_KILL:
949 if (is_manager(thrd))
950 return PL330_STATE_INVALID;
951 else
952 return PL330_STATE_KILLING;
953 case DS_ST_CMPLT:
954 if (is_manager(thrd))
955 return PL330_STATE_INVALID;
956 else
957 return PL330_STATE_COMPLETING;
958 case DS_ST_FLTCMP:
959 if (is_manager(thrd))
960 return PL330_STATE_INVALID;
961 else
962 return PL330_STATE_FAULT_COMPLETING;
963 default:
964 return PL330_STATE_INVALID;
965 }
966}
967
968static void _stop(struct pl330_thread *thrd)
969{
970 void __iomem *regs = thrd->dmac->base;
971 u8 insn[6] = {0, 0, 0, 0, 0, 0};
972 u32 inten = readl(regs + INTEN);
973
974 if (_state(thrd) == PL330_STATE_FAULT_COMPLETING)
975 UNTIL(thrd, PL330_STATE_FAULTING | PL330_STATE_KILLING);
976
977 /* Return if nothing needs to be done */
978 if (_state(thrd) == PL330_STATE_COMPLETING
979 || _state(thrd) == PL330_STATE_KILLING
980 || _state(thrd) == PL330_STATE_STOPPED)
981 return;
982
983 _emit_KILL(0, insn);
984
985 _execute_DBGINSN(thrd, insn, is_manager(thrd));
986
987 /* clear the event */
988 if (inten & (1 << thrd->ev))
989 writel(1 << thrd->ev, regs + INTCLR);
990 /* Stop generating interrupts for SEV */
991 writel(inten & ~(1 << thrd->ev), regs + INTEN);
992}
993
994/* Start doing req 'idx' of thread 'thrd' */
995static bool _trigger(struct pl330_thread *thrd)
996{
997 void __iomem *regs = thrd->dmac->base;
998 struct _pl330_req *req;
999 struct dma_pl330_desc *desc;
1000 struct _arg_GO go;
1001 unsigned ns;
1002 u8 insn[6] = {0, 0, 0, 0, 0, 0};
1003 int idx;
1004
1005 /* Return if already ACTIVE */
1006 if (_state(thrd) != PL330_STATE_STOPPED)
1007 return true;
1008
1009 idx = 1 - thrd->lstenq;
1010 if (thrd->req[idx].desc != NULL) {
1011 req = &thrd->req[idx];
1012 } else {
1013 idx = thrd->lstenq;
1014 if (thrd->req[idx].desc != NULL)
1015 req = &thrd->req[idx];
1016 else
1017 req = NULL;
1018 }
1019
1020 /* Return if no request */
1021 if (!req)
1022 return true;
1023
1024 /* Return if req is running */
1025 if (idx == thrd->req_running)
1026 return true;
1027
1028 desc = req->desc;
1029
1030 ns = desc->rqcfg.nonsecure ? 1 : 0;
1031
1032 /* See 'Abort Sources' point-4 at Page 2-25 */
1033 if (_manager_ns(thrd) && !ns)
1034 dev_info(thrd->dmac->ddma.dev, "%s:%d Recipe for ABORT!\n",
1035 __func__, __LINE__);
1036
1037 go.chan = thrd->id;
1038 go.addr = req->mc_bus;
1039 go.ns = ns;
1040 _emit_GO(0, insn, &go);
1041
1042 /* Set to generate interrupts for SEV */
1043 writel(readl(regs + INTEN) | (1 << thrd->ev), regs + INTEN);
1044
1045 /* Only manager can execute GO */
1046 _execute_DBGINSN(thrd, insn, true);
1047
1048 thrd->req_running = idx;
1049
1050 return true;
1051}
1052
1053static bool _start(struct pl330_thread *thrd)
1054{
1055 switch (_state(thrd)) {
1056 case PL330_STATE_FAULT_COMPLETING:
1057 UNTIL(thrd, PL330_STATE_FAULTING | PL330_STATE_KILLING);
1058
1059 if (_state(thrd) == PL330_STATE_KILLING)
1060 UNTIL(thrd, PL330_STATE_STOPPED)
1061 fallthrough;
1062
1063 case PL330_STATE_FAULTING:
1064 _stop(thrd);
1065 fallthrough;
1066
1067 case PL330_STATE_KILLING:
1068 case PL330_STATE_COMPLETING:
1069 UNTIL(thrd, PL330_STATE_STOPPED)
1070 fallthrough;
1071
1072 case PL330_STATE_STOPPED:
1073 return _trigger(thrd);
1074
1075 case PL330_STATE_WFP:
1076 case PL330_STATE_QUEUEBUSY:
1077 case PL330_STATE_ATBARRIER:
1078 case PL330_STATE_UPDTPC:
1079 case PL330_STATE_CACHEMISS:
1080 case PL330_STATE_EXECUTING:
1081 return true;
1082
1083 case PL330_STATE_WFE: /* For RESUME, nothing yet */
1084 default:
1085 return false;
1086 }
1087}
1088
1089static inline int _ldst_memtomem(unsigned dry_run, u8 buf[],
1090 const struct _xfer_spec *pxs, int cyc)
1091{
1092 int off = 0;
1093 struct pl330_config *pcfg = pxs->desc->rqcfg.pcfg;
1094
1095 /* check lock-up free version */
1096 if (get_revision(pcfg->periph_id) >= PERIPH_REV_R1P0) {
1097 while (cyc--) {
1098 off += _emit_LD(dry_run, &buf[off], ALWAYS);
1099 off += _emit_ST(dry_run, &buf[off], ALWAYS);
1100 }
1101 } else {
1102 while (cyc--) {
1103 off += _emit_LD(dry_run, &buf[off], ALWAYS);
1104 off += _emit_RMB(dry_run, &buf[off]);
1105 off += _emit_ST(dry_run, &buf[off], ALWAYS);
1106 off += _emit_WMB(dry_run, &buf[off]);
1107 }
1108 }
1109
1110 return off;
1111}
1112
1113static u32 _emit_load(unsigned int dry_run, u8 buf[],
1114 enum pl330_cond cond, enum dma_transfer_direction direction,
1115 u8 peri)
1116{
1117 int off = 0;
1118
1119 switch (direction) {
1120 case DMA_MEM_TO_MEM:
1121 case DMA_MEM_TO_DEV:
1122 off += _emit_LD(dry_run, &buf[off], cond);
1123 break;
1124
1125 case DMA_DEV_TO_MEM:
1126 if (cond == ALWAYS) {
1127 off += _emit_LDP(dry_run, &buf[off], SINGLE,
1128 peri);
1129 off += _emit_LDP(dry_run, &buf[off], BURST,
1130 peri);
1131 } else {
1132 off += _emit_LDP(dry_run, &buf[off], cond,
1133 peri);
1134 }
1135 break;
1136
1137 default:
1138 /* this code should be unreachable */
1139 WARN_ON(1);
1140 break;
1141 }
1142
1143 return off;
1144}
1145
1146static inline u32 _emit_store(unsigned int dry_run, u8 buf[],
1147 enum pl330_cond cond, enum dma_transfer_direction direction,
1148 u8 peri)
1149{
1150 int off = 0;
1151
1152 switch (direction) {
1153 case DMA_MEM_TO_MEM:
1154 case DMA_DEV_TO_MEM:
1155 off += _emit_ST(dry_run, &buf[off], cond);
1156 break;
1157
1158 case DMA_MEM_TO_DEV:
1159 if (cond == ALWAYS) {
1160 off += _emit_STP(dry_run, &buf[off], SINGLE,
1161 peri);
1162 off += _emit_STP(dry_run, &buf[off], BURST,
1163 peri);
1164 } else {
1165 off += _emit_STP(dry_run, &buf[off], cond,
1166 peri);
1167 }
1168 break;
1169
1170 default:
1171 /* this code should be unreachable */
1172 WARN_ON(1);
1173 break;
1174 }
1175
1176 return off;
1177}
1178
1179static inline int _ldst_peripheral(struct pl330_dmac *pl330,
1180 unsigned dry_run, u8 buf[],
1181 const struct _xfer_spec *pxs, int cyc,
1182 enum pl330_cond cond)
1183{
1184 int off = 0;
1185
1186 /*
1187 * do FLUSHP at beginning to clear any stale dma requests before the
1188 * first WFP.
1189 */
1190 if (!(pl330->quirks & PL330_QUIRK_BROKEN_NO_FLUSHP))
1191 off += _emit_FLUSHP(dry_run, &buf[off], pxs->desc->peri);
1192 while (cyc--) {
1193 off += _emit_WFP(dry_run, &buf[off], cond, pxs->desc->peri);
1194 off += _emit_load(dry_run, &buf[off], cond, pxs->desc->rqtype,
1195 pxs->desc->peri);
1196 off += _emit_store(dry_run, &buf[off], cond, pxs->desc->rqtype,
1197 pxs->desc->peri);
1198 }
1199
1200 return off;
1201}
1202
1203static int _bursts(struct pl330_dmac *pl330, unsigned dry_run, u8 buf[],
1204 const struct _xfer_spec *pxs, int cyc)
1205{
1206 int off = 0;
1207 enum pl330_cond cond = BRST_LEN(pxs->ccr) > 1 ? BURST : SINGLE;
1208
1209 if (pl330->quirks & PL330_QUIRK_PERIPH_BURST)
1210 cond = BURST;
1211
1212 switch (pxs->desc->rqtype) {
1213 case DMA_MEM_TO_DEV:
1214 case DMA_DEV_TO_MEM:
1215 off += _ldst_peripheral(pl330, dry_run, &buf[off], pxs, cyc,
1216 cond);
1217 break;
1218
1219 case DMA_MEM_TO_MEM:
1220 off += _ldst_memtomem(dry_run, &buf[off], pxs, cyc);
1221 break;
1222
1223 default:
1224 /* this code should be unreachable */
1225 WARN_ON(1);
1226 break;
1227 }
1228
1229 return off;
1230}
1231
1232/*
1233 * only the unaligned burst transfers have the dregs.
1234 * so, still transfer dregs with a reduced size burst
1235 * for mem-to-mem, mem-to-dev or dev-to-mem.
1236 */
1237static int _dregs(struct pl330_dmac *pl330, unsigned int dry_run, u8 buf[],
1238 const struct _xfer_spec *pxs, int transfer_length)
1239{
1240 int off = 0;
1241 int dregs_ccr;
1242
1243 if (transfer_length == 0)
1244 return off;
1245
1246 /*
1247 * dregs_len = (total bytes - BURST_TO_BYTE(bursts, ccr)) /
1248 * BRST_SIZE(ccr)
1249 * the dregs len must be smaller than burst len,
1250 * so, for higher efficiency, we can modify CCR
1251 * to use a reduced size burst len for the dregs.
1252 */
1253 dregs_ccr = pxs->ccr;
1254 dregs_ccr &= ~((0xf << CC_SRCBRSTLEN_SHFT) |
1255 (0xf << CC_DSTBRSTLEN_SHFT));
1256 dregs_ccr |= (((transfer_length - 1) & 0xf) <<
1257 CC_SRCBRSTLEN_SHFT);
1258 dregs_ccr |= (((transfer_length - 1) & 0xf) <<
1259 CC_DSTBRSTLEN_SHFT);
1260
1261 switch (pxs->desc->rqtype) {
1262 case DMA_MEM_TO_DEV:
1263 case DMA_DEV_TO_MEM:
1264 off += _emit_MOV(dry_run, &buf[off], CCR, dregs_ccr);
1265 off += _ldst_peripheral(pl330, dry_run, &buf[off], pxs, 1,
1266 BURST);
1267 break;
1268
1269 case DMA_MEM_TO_MEM:
1270 off += _emit_MOV(dry_run, &buf[off], CCR, dregs_ccr);
1271 off += _ldst_memtomem(dry_run, &buf[off], pxs, 1);
1272 break;
1273
1274 default:
1275 /* this code should be unreachable */
1276 WARN_ON(1);
1277 break;
1278 }
1279
1280 return off;
1281}
1282
1283/* Returns bytes consumed and updates bursts */
1284static inline int _loop(struct pl330_dmac *pl330, unsigned dry_run, u8 buf[],
1285 unsigned long *bursts, const struct _xfer_spec *pxs)
1286{
1287 int cyc, cycmax, szlp, szlpend, szbrst, off;
1288 unsigned lcnt0, lcnt1, ljmp0, ljmp1;
1289 struct _arg_LPEND lpend;
1290
1291 if (*bursts == 1)
1292 return _bursts(pl330, dry_run, buf, pxs, 1);
1293
1294 /* Max iterations possible in DMALP is 256 */
1295 if (*bursts >= 256*256) {
1296 lcnt1 = 256;
1297 lcnt0 = 256;
1298 cyc = *bursts / lcnt1 / lcnt0;
1299 } else if (*bursts > 256) {
1300 lcnt1 = 256;
1301 lcnt0 = *bursts / lcnt1;
1302 cyc = 1;
1303 } else {
1304 lcnt1 = *bursts;
1305 lcnt0 = 0;
1306 cyc = 1;
1307 }
1308
1309 szlp = _emit_LP(1, buf, 0, 0);
1310 szbrst = _bursts(pl330, 1, buf, pxs, 1);
1311
1312 lpend.cond = ALWAYS;
1313 lpend.forever = false;
1314 lpend.loop = 0;
1315 lpend.bjump = 0;
1316 szlpend = _emit_LPEND(1, buf, &lpend);
1317
1318 if (lcnt0) {
1319 szlp *= 2;
1320 szlpend *= 2;
1321 }
1322
1323 /*
1324 * Max bursts that we can unroll due to limit on the
1325 * size of backward jump that can be encoded in DMALPEND
1326 * which is 8-bits and hence 255
1327 */
1328 cycmax = (255 - (szlp + szlpend)) / szbrst;
1329
1330 cyc = (cycmax < cyc) ? cycmax : cyc;
1331
1332 off = 0;
1333
1334 if (lcnt0) {
1335 off += _emit_LP(dry_run, &buf[off], 0, lcnt0);
1336 ljmp0 = off;
1337 }
1338
1339 off += _emit_LP(dry_run, &buf[off], 1, lcnt1);
1340 ljmp1 = off;
1341
1342 off += _bursts(pl330, dry_run, &buf[off], pxs, cyc);
1343
1344 lpend.cond = ALWAYS;
1345 lpend.forever = false;
1346 lpend.loop = 1;
1347 lpend.bjump = off - ljmp1;
1348 off += _emit_LPEND(dry_run, &buf[off], &lpend);
1349
1350 if (lcnt0) {
1351 lpend.cond = ALWAYS;
1352 lpend.forever = false;
1353 lpend.loop = 0;
1354 lpend.bjump = off - ljmp0;
1355 off += _emit_LPEND(dry_run, &buf[off], &lpend);
1356 }
1357
1358 *bursts = lcnt1 * cyc;
1359 if (lcnt0)
1360 *bursts *= lcnt0;
1361
1362 return off;
1363}
1364
1365static inline int _setup_loops(struct pl330_dmac *pl330,
1366 unsigned dry_run, u8 buf[],
1367 const struct _xfer_spec *pxs)
1368{
1369 struct pl330_xfer *x = &pxs->desc->px;
1370 u32 ccr = pxs->ccr;
1371 unsigned long c, bursts = BYTE_TO_BURST(x->bytes, ccr);
1372 int num_dregs = (x->bytes - BURST_TO_BYTE(bursts, ccr)) /
1373 BRST_SIZE(ccr);
1374 int off = 0;
1375
1376 while (bursts) {
1377 c = bursts;
1378 off += _loop(pl330, dry_run, &buf[off], &c, pxs);
1379 bursts -= c;
1380 }
1381 off += _dregs(pl330, dry_run, &buf[off], pxs, num_dregs);
1382
1383 return off;
1384}
1385
1386static inline int _setup_xfer(struct pl330_dmac *pl330,
1387 unsigned dry_run, u8 buf[],
1388 const struct _xfer_spec *pxs)
1389{
1390 struct pl330_xfer *x = &pxs->desc->px;
1391 int off = 0;
1392
1393 /* DMAMOV SAR, x->src_addr */
1394 off += _emit_MOV(dry_run, &buf[off], SAR, x->src_addr);
1395 /* DMAMOV DAR, x->dst_addr */
1396 off += _emit_MOV(dry_run, &buf[off], DAR, x->dst_addr);
1397
1398 /* Setup Loop(s) */
1399 off += _setup_loops(pl330, dry_run, &buf[off], pxs);
1400
1401 return off;
1402}
1403
1404/*
1405 * A req is a sequence of one or more xfer units.
1406 * Returns the number of bytes taken to setup the MC for the req.
1407 */
1408static int _setup_req(struct pl330_dmac *pl330, unsigned dry_run,
1409 struct pl330_thread *thrd, unsigned index,
1410 struct _xfer_spec *pxs)
1411{
1412 struct _pl330_req *req = &thrd->req[index];
1413 u8 *buf = req->mc_cpu;
1414 int off = 0;
1415
1416 PL330_DBGMC_START(req->mc_bus);
1417
1418 /* DMAMOV CCR, ccr */
1419 off += _emit_MOV(dry_run, &buf[off], CCR, pxs->ccr);
1420
1421 off += _setup_xfer(pl330, dry_run, &buf[off], pxs);
1422
1423 /* DMASEV peripheral/event */
1424 off += _emit_SEV(dry_run, &buf[off], thrd->ev);
1425 /* DMAEND */
1426 off += _emit_END(dry_run, &buf[off]);
1427
1428 return off;
1429}
1430
1431static inline u32 _prepare_ccr(const struct pl330_reqcfg *rqc)
1432{
1433 u32 ccr = 0;
1434
1435 if (rqc->src_inc)
1436 ccr |= CC_SRCINC;
1437
1438 if (rqc->dst_inc)
1439 ccr |= CC_DSTINC;
1440
1441 /* We set same protection levels for Src and DST for now */
1442 if (rqc->privileged)
1443 ccr |= CC_SRCPRI | CC_DSTPRI;
1444 if (rqc->nonsecure)
1445 ccr |= CC_SRCNS | CC_DSTNS;
1446 if (rqc->insnaccess)
1447 ccr |= CC_SRCIA | CC_DSTIA;
1448
1449 ccr |= (((rqc->brst_len - 1) & 0xf) << CC_SRCBRSTLEN_SHFT);
1450 ccr |= (((rqc->brst_len - 1) & 0xf) << CC_DSTBRSTLEN_SHFT);
1451
1452 ccr |= (rqc->brst_size << CC_SRCBRSTSIZE_SHFT);
1453 ccr |= (rqc->brst_size << CC_DSTBRSTSIZE_SHFT);
1454
1455 ccr |= (rqc->scctl << CC_SRCCCTRL_SHFT);
1456 ccr |= (rqc->dcctl << CC_DSTCCTRL_SHFT);
1457
1458 ccr |= (rqc->swap << CC_SWAP_SHFT);
1459
1460 return ccr;
1461}
1462
1463/*
1464 * Submit a list of xfers after which the client wants notification.
1465 * Client is not notified after each xfer unit, just once after all
1466 * xfer units are done or some error occurs.
1467 */
1468static int pl330_submit_req(struct pl330_thread *thrd,
1469 struct dma_pl330_desc *desc)
1470{
1471 struct pl330_dmac *pl330 = thrd->dmac;
1472 struct _xfer_spec xs;
1473 unsigned long flags;
1474 unsigned idx;
1475 u32 ccr;
1476 int ret = 0;
1477
1478 switch (desc->rqtype) {
1479 case DMA_MEM_TO_DEV:
1480 break;
1481
1482 case DMA_DEV_TO_MEM:
1483 break;
1484
1485 case DMA_MEM_TO_MEM:
1486 break;
1487
1488 default:
1489 return -ENOTSUPP;
1490 }
1491
1492 if (pl330->state == DYING
1493 || pl330->dmac_tbd.reset_chan & (1 << thrd->id)) {
1494 dev_info(thrd->dmac->ddma.dev, "%s:%d\n",
1495 __func__, __LINE__);
1496 return -EAGAIN;
1497 }
1498
1499 /* If request for non-existing peripheral */
1500 if (desc->rqtype != DMA_MEM_TO_MEM &&
1501 desc->peri >= pl330->pcfg.num_peri) {
1502 dev_info(thrd->dmac->ddma.dev,
1503 "%s:%d Invalid peripheral(%u)!\n",
1504 __func__, __LINE__, desc->peri);
1505 return -EINVAL;
1506 }
1507
1508 spin_lock_irqsave(&pl330->lock, flags);
1509
1510 if (_queue_full(thrd)) {
1511 ret = -EAGAIN;
1512 goto xfer_exit;
1513 }
1514
1515 /* Prefer Secure Channel */
1516 if (!_manager_ns(thrd))
1517 desc->rqcfg.nonsecure = 0;
1518 else
1519 desc->rqcfg.nonsecure = 1;
1520
1521 ccr = _prepare_ccr(&desc->rqcfg);
1522
1523 idx = thrd->req[0].desc == NULL ? 0 : 1;
1524
1525 xs.ccr = ccr;
1526 xs.desc = desc;
1527
1528 /* First dry run to check if req is acceptable */
1529 ret = _setup_req(pl330, 1, thrd, idx, &xs);
1530
1531 if (ret > pl330->mcbufsz / 2) {
1532 dev_info(pl330->ddma.dev, "%s:%d Try increasing mcbufsz (%i/%i)\n",
1533 __func__, __LINE__, ret, pl330->mcbufsz / 2);
1534 ret = -ENOMEM;
1535 goto xfer_exit;
1536 }
1537
1538 /* Hook the request */
1539 thrd->lstenq = idx;
1540 thrd->req[idx].desc = desc;
1541 _setup_req(pl330, 0, thrd, idx, &xs);
1542
1543 ret = 0;
1544
1545xfer_exit:
1546 spin_unlock_irqrestore(&pl330->lock, flags);
1547
1548 return ret;
1549}
1550
1551static void dma_pl330_rqcb(struct dma_pl330_desc *desc, enum pl330_op_err err)
1552{
1553 struct dma_pl330_chan *pch;
1554 unsigned long flags;
1555
1556 if (!desc)
1557 return;
1558
1559 pch = desc->pchan;
1560
1561 /* If desc aborted */
1562 if (!pch)
1563 return;
1564
1565 spin_lock_irqsave(&pch->lock, flags);
1566
1567 desc->status = DONE;
1568
1569 spin_unlock_irqrestore(&pch->lock, flags);
1570
1571 tasklet_schedule(&pch->task);
1572}
1573
1574static void pl330_dotask(struct tasklet_struct *t)
1575{
1576 struct pl330_dmac *pl330 = from_tasklet(pl330, t, tasks);
1577 unsigned long flags;
1578 int i;
1579
1580 spin_lock_irqsave(&pl330->lock, flags);
1581
1582 /* The DMAC itself gone nuts */
1583 if (pl330->dmac_tbd.reset_dmac) {
1584 pl330->state = DYING;
1585 /* Reset the manager too */
1586 pl330->dmac_tbd.reset_mngr = true;
1587 /* Clear the reset flag */
1588 pl330->dmac_tbd.reset_dmac = false;
1589 }
1590
1591 if (pl330->dmac_tbd.reset_mngr) {
1592 _stop(pl330->manager);
1593 /* Reset all channels */
1594 pl330->dmac_tbd.reset_chan = (1 << pl330->pcfg.num_chan) - 1;
1595 /* Clear the reset flag */
1596 pl330->dmac_tbd.reset_mngr = false;
1597 }
1598
1599 for (i = 0; i < pl330->pcfg.num_chan; i++) {
1600
1601 if (pl330->dmac_tbd.reset_chan & (1 << i)) {
1602 struct pl330_thread *thrd = &pl330->channels[i];
1603 void __iomem *regs = pl330->base;
1604 enum pl330_op_err err;
1605
1606 _stop(thrd);
1607
1608 if (readl(regs + FSC) & (1 << thrd->id))
1609 err = PL330_ERR_FAIL;
1610 else
1611 err = PL330_ERR_ABORT;
1612
1613 spin_unlock_irqrestore(&pl330->lock, flags);
1614 dma_pl330_rqcb(thrd->req[1 - thrd->lstenq].desc, err);
1615 dma_pl330_rqcb(thrd->req[thrd->lstenq].desc, err);
1616 spin_lock_irqsave(&pl330->lock, flags);
1617
1618 thrd->req[0].desc = NULL;
1619 thrd->req[1].desc = NULL;
1620 thrd->req_running = -1;
1621
1622 /* Clear the reset flag */
1623 pl330->dmac_tbd.reset_chan &= ~(1 << i);
1624 }
1625 }
1626
1627 spin_unlock_irqrestore(&pl330->lock, flags);
1628
1629 return;
1630}
1631
1632/* Returns 1 if state was updated, 0 otherwise */
1633static int pl330_update(struct pl330_dmac *pl330)
1634{
1635 struct dma_pl330_desc *descdone;
1636 unsigned long flags;
1637 void __iomem *regs;
1638 u32 val;
1639 int id, ev, ret = 0;
1640
1641 regs = pl330->base;
1642
1643 spin_lock_irqsave(&pl330->lock, flags);
1644
1645 val = readl(regs + FSM) & 0x1;
1646 if (val)
1647 pl330->dmac_tbd.reset_mngr = true;
1648 else
1649 pl330->dmac_tbd.reset_mngr = false;
1650
1651 val = readl(regs + FSC) & ((1 << pl330->pcfg.num_chan) - 1);
1652 pl330->dmac_tbd.reset_chan |= val;
1653 if (val) {
1654 int i = 0;
1655 while (i < pl330->pcfg.num_chan) {
1656 if (val & (1 << i)) {
1657 dev_info(pl330->ddma.dev,
1658 "Reset Channel-%d\t CS-%x FTC-%x\n",
1659 i, readl(regs + CS(i)),
1660 readl(regs + FTC(i)));
1661 _stop(&pl330->channels[i]);
1662 }
1663 i++;
1664 }
1665 }
1666
1667 /* Check which event happened i.e, thread notified */
1668 val = readl(regs + ES);
1669 if (pl330->pcfg.num_events < 32
1670 && val & ~((1 << pl330->pcfg.num_events) - 1)) {
1671 pl330->dmac_tbd.reset_dmac = true;
1672 dev_err(pl330->ddma.dev, "%s:%d Unexpected!\n", __func__,
1673 __LINE__);
1674 ret = 1;
1675 goto updt_exit;
1676 }
1677
1678 for (ev = 0; ev < pl330->pcfg.num_events; ev++) {
1679 if (val & (1 << ev)) { /* Event occurred */
1680 struct pl330_thread *thrd;
1681 u32 inten = readl(regs + INTEN);
1682 int active;
1683
1684 /* Clear the event */
1685 if (inten & (1 << ev))
1686 writel(1 << ev, regs + INTCLR);
1687
1688 ret = 1;
1689
1690 id = pl330->events[ev];
1691
1692 thrd = &pl330->channels[id];
1693
1694 active = thrd->req_running;
1695 if (active == -1) /* Aborted */
1696 continue;
1697
1698 /* Detach the req */
1699 descdone = thrd->req[active].desc;
1700 thrd->req[active].desc = NULL;
1701
1702 thrd->req_running = -1;
1703
1704 /* Get going again ASAP */
1705 _start(thrd);
1706
1707 /* For now, just make a list of callbacks to be done */
1708 list_add_tail(&descdone->rqd, &pl330->req_done);
1709 }
1710 }
1711
1712 /* Now that we are in no hurry, do the callbacks */
1713 while (!list_empty(&pl330->req_done)) {
1714 descdone = list_first_entry(&pl330->req_done,
1715 struct dma_pl330_desc, rqd);
1716 list_del(&descdone->rqd);
1717 spin_unlock_irqrestore(&pl330->lock, flags);
1718 dma_pl330_rqcb(descdone, PL330_ERR_NONE);
1719 spin_lock_irqsave(&pl330->lock, flags);
1720 }
1721
1722updt_exit:
1723 spin_unlock_irqrestore(&pl330->lock, flags);
1724
1725 if (pl330->dmac_tbd.reset_dmac
1726 || pl330->dmac_tbd.reset_mngr
1727 || pl330->dmac_tbd.reset_chan) {
1728 ret = 1;
1729 tasklet_schedule(&pl330->tasks);
1730 }
1731
1732 return ret;
1733}
1734
1735/* Reserve an event */
1736static inline int _alloc_event(struct pl330_thread *thrd)
1737{
1738 struct pl330_dmac *pl330 = thrd->dmac;
1739 int ev;
1740
1741 for (ev = 0; ev < pl330->pcfg.num_events; ev++)
1742 if (pl330->events[ev] == -1) {
1743 pl330->events[ev] = thrd->id;
1744 return ev;
1745 }
1746
1747 return -1;
1748}
1749
1750static bool _chan_ns(const struct pl330_dmac *pl330, int i)
1751{
1752 return pl330->pcfg.irq_ns & (1 << i);
1753}
1754
1755/* Upon success, returns IdentityToken for the
1756 * allocated channel, NULL otherwise.
1757 */
1758static struct pl330_thread *pl330_request_channel(struct pl330_dmac *pl330)
1759{
1760 struct pl330_thread *thrd = NULL;
1761 int chans, i;
1762
1763 if (pl330->state == DYING)
1764 return NULL;
1765
1766 chans = pl330->pcfg.num_chan;
1767
1768 for (i = 0; i < chans; i++) {
1769 thrd = &pl330->channels[i];
1770 if ((thrd->free) && (!_manager_ns(thrd) ||
1771 _chan_ns(pl330, i))) {
1772 thrd->ev = _alloc_event(thrd);
1773 if (thrd->ev >= 0) {
1774 thrd->free = false;
1775 thrd->lstenq = 1;
1776 thrd->req[0].desc = NULL;
1777 thrd->req[1].desc = NULL;
1778 thrd->req_running = -1;
1779 break;
1780 }
1781 }
1782 thrd = NULL;
1783 }
1784
1785 return thrd;
1786}
1787
1788/* Release an event */
1789static inline void _free_event(struct pl330_thread *thrd, int ev)
1790{
1791 struct pl330_dmac *pl330 = thrd->dmac;
1792
1793 /* If the event is valid and was held by the thread */
1794 if (ev >= 0 && ev < pl330->pcfg.num_events
1795 && pl330->events[ev] == thrd->id)
1796 pl330->events[ev] = -1;
1797}
1798
1799static void pl330_release_channel(struct pl330_thread *thrd)
1800{
1801 if (!thrd || thrd->free)
1802 return;
1803
1804 _stop(thrd);
1805
1806 dma_pl330_rqcb(thrd->req[1 - thrd->lstenq].desc, PL330_ERR_ABORT);
1807 dma_pl330_rqcb(thrd->req[thrd->lstenq].desc, PL330_ERR_ABORT);
1808
1809 _free_event(thrd, thrd->ev);
1810 thrd->free = true;
1811}
1812
1813/* Initialize the structure for PL330 configuration, that can be used
1814 * by the client driver the make best use of the DMAC
1815 */
1816static void read_dmac_config(struct pl330_dmac *pl330)
1817{
1818 void __iomem *regs = pl330->base;
1819 u32 val;
1820
1821 val = readl(regs + CRD) >> CRD_DATA_WIDTH_SHIFT;
1822 val &= CRD_DATA_WIDTH_MASK;
1823 pl330->pcfg.data_bus_width = 8 * (1 << val);
1824
1825 val = readl(regs + CRD) >> CRD_DATA_BUFF_SHIFT;
1826 val &= CRD_DATA_BUFF_MASK;
1827 pl330->pcfg.data_buf_dep = val + 1;
1828
1829 val = readl(regs + CR0) >> CR0_NUM_CHANS_SHIFT;
1830 val &= CR0_NUM_CHANS_MASK;
1831 val += 1;
1832 pl330->pcfg.num_chan = val;
1833
1834 val = readl(regs + CR0);
1835 if (val & CR0_PERIPH_REQ_SET) {
1836 val = (val >> CR0_NUM_PERIPH_SHIFT) & CR0_NUM_PERIPH_MASK;
1837 val += 1;
1838 pl330->pcfg.num_peri = val;
1839 pl330->pcfg.peri_ns = readl(regs + CR4);
1840 } else {
1841 pl330->pcfg.num_peri = 0;
1842 }
1843
1844 val = readl(regs + CR0);
1845 if (val & CR0_BOOT_MAN_NS)
1846 pl330->pcfg.mode |= DMAC_MODE_NS;
1847 else
1848 pl330->pcfg.mode &= ~DMAC_MODE_NS;
1849
1850 val = readl(regs + CR0) >> CR0_NUM_EVENTS_SHIFT;
1851 val &= CR0_NUM_EVENTS_MASK;
1852 val += 1;
1853 pl330->pcfg.num_events = val;
1854
1855 pl330->pcfg.irq_ns = readl(regs + CR3);
1856}
1857
1858static inline void _reset_thread(struct pl330_thread *thrd)
1859{
1860 struct pl330_dmac *pl330 = thrd->dmac;
1861
1862 thrd->req[0].mc_cpu = pl330->mcode_cpu
1863 + (thrd->id * pl330->mcbufsz);
1864 thrd->req[0].mc_bus = pl330->mcode_bus
1865 + (thrd->id * pl330->mcbufsz);
1866 thrd->req[0].desc = NULL;
1867
1868 thrd->req[1].mc_cpu = thrd->req[0].mc_cpu
1869 + pl330->mcbufsz / 2;
1870 thrd->req[1].mc_bus = thrd->req[0].mc_bus
1871 + pl330->mcbufsz / 2;
1872 thrd->req[1].desc = NULL;
1873
1874 thrd->req_running = -1;
1875}
1876
1877static int dmac_alloc_threads(struct pl330_dmac *pl330)
1878{
1879 int chans = pl330->pcfg.num_chan;
1880 struct pl330_thread *thrd;
1881 int i;
1882
1883 /* Allocate 1 Manager and 'chans' Channel threads */
1884 pl330->channels = kcalloc(1 + chans, sizeof(*thrd),
1885 GFP_KERNEL);
1886 if (!pl330->channels)
1887 return -ENOMEM;
1888
1889 /* Init Channel threads */
1890 for (i = 0; i < chans; i++) {
1891 thrd = &pl330->channels[i];
1892 thrd->id = i;
1893 thrd->dmac = pl330;
1894 _reset_thread(thrd);
1895 thrd->free = true;
1896 }
1897
1898 /* MANAGER is indexed at the end */
1899 thrd = &pl330->channels[chans];
1900 thrd->id = chans;
1901 thrd->dmac = pl330;
1902 thrd->free = false;
1903 pl330->manager = thrd;
1904
1905 return 0;
1906}
1907
1908static int dmac_alloc_resources(struct pl330_dmac *pl330)
1909{
1910 int chans = pl330->pcfg.num_chan;
1911 int ret;
1912
1913 /*
1914 * Alloc MicroCode buffer for 'chans' Channel threads.
1915 * A channel's buffer offset is (Channel_Id * MCODE_BUFF_PERCHAN)
1916 */
1917 pl330->mcode_cpu = dma_alloc_attrs(pl330->ddma.dev,
1918 chans * pl330->mcbufsz,
1919 &pl330->mcode_bus, GFP_KERNEL,
1920 DMA_ATTR_PRIVILEGED);
1921 if (!pl330->mcode_cpu) {
1922 dev_err(pl330->ddma.dev, "%s:%d Can't allocate memory!\n",
1923 __func__, __LINE__);
1924 return -ENOMEM;
1925 }
1926
1927 ret = dmac_alloc_threads(pl330);
1928 if (ret) {
1929 dev_err(pl330->ddma.dev, "%s:%d Can't to create channels for DMAC!\n",
1930 __func__, __LINE__);
1931 dma_free_attrs(pl330->ddma.dev,
1932 chans * pl330->mcbufsz,
1933 pl330->mcode_cpu, pl330->mcode_bus,
1934 DMA_ATTR_PRIVILEGED);
1935 return ret;
1936 }
1937
1938 return 0;
1939}
1940
1941static int pl330_add(struct pl330_dmac *pl330)
1942{
1943 int i, ret;
1944
1945 /* Check if we can handle this DMAC */
1946 if ((pl330->pcfg.periph_id & 0xfffff) != PERIPH_ID_VAL) {
1947 dev_err(pl330->ddma.dev, "PERIPH_ID 0x%x !\n",
1948 pl330->pcfg.periph_id);
1949 return -EINVAL;
1950 }
1951
1952 /* Read the configuration of the DMAC */
1953 read_dmac_config(pl330);
1954
1955 if (pl330->pcfg.num_events == 0) {
1956 dev_err(pl330->ddma.dev, "%s:%d Can't work without events!\n",
1957 __func__, __LINE__);
1958 return -EINVAL;
1959 }
1960
1961 spin_lock_init(&pl330->lock);
1962
1963 INIT_LIST_HEAD(&pl330->req_done);
1964
1965 /* Use default MC buffer size if not provided */
1966 if (!pl330->mcbufsz)
1967 pl330->mcbufsz = MCODE_BUFF_PER_REQ * 2;
1968
1969 /* Mark all events as free */
1970 for (i = 0; i < pl330->pcfg.num_events; i++)
1971 pl330->events[i] = -1;
1972
1973 /* Allocate resources needed by the DMAC */
1974 ret = dmac_alloc_resources(pl330);
1975 if (ret) {
1976 dev_err(pl330->ddma.dev, "Unable to create channels for DMAC\n");
1977 return ret;
1978 }
1979
1980 tasklet_setup(&pl330->tasks, pl330_dotask);
1981
1982 pl330->state = INIT;
1983
1984 return 0;
1985}
1986
1987static int dmac_free_threads(struct pl330_dmac *pl330)
1988{
1989 struct pl330_thread *thrd;
1990 int i;
1991
1992 /* Release Channel threads */
1993 for (i = 0; i < pl330->pcfg.num_chan; i++) {
1994 thrd = &pl330->channels[i];
1995 pl330_release_channel(thrd);
1996 }
1997
1998 /* Free memory */
1999 kfree(pl330->channels);
2000
2001 return 0;
2002}
2003
2004static void pl330_del(struct pl330_dmac *pl330)
2005{
2006 pl330->state = UNINIT;
2007
2008 tasklet_kill(&pl330->tasks);
2009
2010 /* Free DMAC resources */
2011 dmac_free_threads(pl330);
2012
2013 dma_free_attrs(pl330->ddma.dev,
2014 pl330->pcfg.num_chan * pl330->mcbufsz, pl330->mcode_cpu,
2015 pl330->mcode_bus, DMA_ATTR_PRIVILEGED);
2016}
2017
2018/* forward declaration */
2019static struct amba_driver pl330_driver;
2020
2021static inline struct dma_pl330_chan *
2022to_pchan(struct dma_chan *ch)
2023{
2024 if (!ch)
2025 return NULL;
2026
2027 return container_of(ch, struct dma_pl330_chan, chan);
2028}
2029
2030static inline struct dma_pl330_desc *
2031to_desc(struct dma_async_tx_descriptor *tx)
2032{
2033 return container_of(tx, struct dma_pl330_desc, txd);
2034}
2035
2036static inline void fill_queue(struct dma_pl330_chan *pch)
2037{
2038 struct dma_pl330_desc *desc;
2039 int ret;
2040
2041 list_for_each_entry(desc, &pch->work_list, node) {
2042
2043 /* If already submitted */
2044 if (desc->status == BUSY)
2045 continue;
2046
2047 ret = pl330_submit_req(pch->thread, desc);
2048 if (!ret) {
2049 desc->status = BUSY;
2050 } else if (ret == -EAGAIN) {
2051 /* QFull or DMAC Dying */
2052 break;
2053 } else {
2054 /* Unacceptable request */
2055 desc->status = DONE;
2056 dev_err(pch->dmac->ddma.dev, "%s:%d Bad Desc(%d)\n",
2057 __func__, __LINE__, desc->txd.cookie);
2058 tasklet_schedule(&pch->task);
2059 }
2060 }
2061}
2062
2063static void pl330_tasklet(struct tasklet_struct *t)
2064{
2065 struct dma_pl330_chan *pch = from_tasklet(pch, t, task);
2066 struct dma_pl330_desc *desc, *_dt;
2067 unsigned long flags;
2068 bool power_down = false;
2069
2070 spin_lock_irqsave(&pch->lock, flags);
2071
2072 /* Pick up ripe tomatoes */
2073 list_for_each_entry_safe(desc, _dt, &pch->work_list, node)
2074 if (desc->status == DONE) {
2075 if (!pch->cyclic)
2076 dma_cookie_complete(&desc->txd);
2077 list_move_tail(&desc->node, &pch->completed_list);
2078 }
2079
2080 /* Try to submit a req imm. next to the last completed cookie */
2081 fill_queue(pch);
2082
2083 if (list_empty(&pch->work_list)) {
2084 spin_lock(&pch->thread->dmac->lock);
2085 _stop(pch->thread);
2086 spin_unlock(&pch->thread->dmac->lock);
2087 power_down = true;
2088 pch->active = false;
2089 } else {
2090 /* Make sure the PL330 Channel thread is active */
2091 spin_lock(&pch->thread->dmac->lock);
2092 _start(pch->thread);
2093 spin_unlock(&pch->thread->dmac->lock);
2094 }
2095
2096 while (!list_empty(&pch->completed_list)) {
2097 struct dmaengine_desc_callback cb;
2098
2099 desc = list_first_entry(&pch->completed_list,
2100 struct dma_pl330_desc, node);
2101
2102 dmaengine_desc_get_callback(&desc->txd, &cb);
2103
2104 if (pch->cyclic) {
2105 desc->status = PREP;
2106 list_move_tail(&desc->node, &pch->work_list);
2107 if (power_down) {
2108 pch->active = true;
2109 spin_lock(&pch->thread->dmac->lock);
2110 _start(pch->thread);
2111 spin_unlock(&pch->thread->dmac->lock);
2112 power_down = false;
2113 }
2114 } else {
2115 desc->status = FREE;
2116 list_move_tail(&desc->node, &pch->dmac->desc_pool);
2117 }
2118
2119 dma_descriptor_unmap(&desc->txd);
2120
2121 if (dmaengine_desc_callback_valid(&cb)) {
2122 spin_unlock_irqrestore(&pch->lock, flags);
2123 dmaengine_desc_callback_invoke(&cb, NULL);
2124 spin_lock_irqsave(&pch->lock, flags);
2125 }
2126 }
2127 spin_unlock_irqrestore(&pch->lock, flags);
2128
2129 /* If work list empty, power down */
2130 if (power_down) {
2131 pm_runtime_mark_last_busy(pch->dmac->ddma.dev);
2132 pm_runtime_put_autosuspend(pch->dmac->ddma.dev);
2133 }
2134}
2135
2136static struct dma_chan *of_dma_pl330_xlate(struct of_phandle_args *dma_spec,
2137 struct of_dma *ofdma)
2138{
2139 int count = dma_spec->args_count;
2140 struct pl330_dmac *pl330 = ofdma->of_dma_data;
2141 unsigned int chan_id;
2142
2143 if (!pl330)
2144 return NULL;
2145
2146 if (count != 1)
2147 return NULL;
2148
2149 chan_id = dma_spec->args[0];
2150 if (chan_id >= pl330->num_peripherals)
2151 return NULL;
2152
2153 return dma_get_slave_channel(&pl330->peripherals[chan_id].chan);
2154}
2155
2156static int pl330_alloc_chan_resources(struct dma_chan *chan)
2157{
2158 struct dma_pl330_chan *pch = to_pchan(chan);
2159 struct pl330_dmac *pl330 = pch->dmac;
2160 unsigned long flags;
2161
2162 spin_lock_irqsave(&pl330->lock, flags);
2163
2164 dma_cookie_init(chan);
2165 pch->cyclic = false;
2166
2167 pch->thread = pl330_request_channel(pl330);
2168 if (!pch->thread) {
2169 spin_unlock_irqrestore(&pl330->lock, flags);
2170 return -ENOMEM;
2171 }
2172
2173 tasklet_setup(&pch->task, pl330_tasklet);
2174
2175 spin_unlock_irqrestore(&pl330->lock, flags);
2176
2177 return 1;
2178}
2179
2180/*
2181 * We need the data direction between the DMAC (the dma-mapping "device") and
2182 * the FIFO (the dmaengine "dev"), from the FIFO's point of view. Confusing!
2183 */
2184static enum dma_data_direction
2185pl330_dma_slave_map_dir(enum dma_transfer_direction dir)
2186{
2187 switch (dir) {
2188 case DMA_MEM_TO_DEV:
2189 return DMA_FROM_DEVICE;
2190 case DMA_DEV_TO_MEM:
2191 return DMA_TO_DEVICE;
2192 case DMA_DEV_TO_DEV:
2193 return DMA_BIDIRECTIONAL;
2194 default:
2195 return DMA_NONE;
2196 }
2197}
2198
2199static void pl330_unprep_slave_fifo(struct dma_pl330_chan *pch)
2200{
2201 if (pch->dir != DMA_NONE)
2202 dma_unmap_resource(pch->chan.device->dev, pch->fifo_dma,
2203 1 << pch->burst_sz, pch->dir, 0);
2204 pch->dir = DMA_NONE;
2205}
2206
2207
2208static bool pl330_prep_slave_fifo(struct dma_pl330_chan *pch,
2209 enum dma_transfer_direction dir)
2210{
2211 struct device *dev = pch->chan.device->dev;
2212 enum dma_data_direction dma_dir = pl330_dma_slave_map_dir(dir);
2213
2214 /* Already mapped for this config? */
2215 if (pch->dir == dma_dir)
2216 return true;
2217
2218 pl330_unprep_slave_fifo(pch);
2219 pch->fifo_dma = dma_map_resource(dev, pch->fifo_addr,
2220 1 << pch->burst_sz, dma_dir, 0);
2221 if (dma_mapping_error(dev, pch->fifo_dma))
2222 return false;
2223
2224 pch->dir = dma_dir;
2225 return true;
2226}
2227
2228static int fixup_burst_len(int max_burst_len, int quirks)
2229{
2230 if (max_burst_len > PL330_MAX_BURST)
2231 return PL330_MAX_BURST;
2232 else if (max_burst_len < 1)
2233 return 1;
2234 else
2235 return max_burst_len;
2236}
2237
2238static int pl330_config_write(struct dma_chan *chan,
2239 struct dma_slave_config *slave_config,
2240 enum dma_transfer_direction direction)
2241{
2242 struct dma_pl330_chan *pch = to_pchan(chan);
2243
2244 pl330_unprep_slave_fifo(pch);
2245 if (direction == DMA_MEM_TO_DEV) {
2246 if (slave_config->dst_addr)
2247 pch->fifo_addr = slave_config->dst_addr;
2248 if (slave_config->dst_addr_width)
2249 pch->burst_sz = __ffs(slave_config->dst_addr_width);
2250 pch->burst_len = fixup_burst_len(slave_config->dst_maxburst,
2251 pch->dmac->quirks);
2252 } else if (direction == DMA_DEV_TO_MEM) {
2253 if (slave_config->src_addr)
2254 pch->fifo_addr = slave_config->src_addr;
2255 if (slave_config->src_addr_width)
2256 pch->burst_sz = __ffs(slave_config->src_addr_width);
2257 pch->burst_len = fixup_burst_len(slave_config->src_maxburst,
2258 pch->dmac->quirks);
2259 }
2260
2261 return 0;
2262}
2263
2264static int pl330_config(struct dma_chan *chan,
2265 struct dma_slave_config *slave_config)
2266{
2267 struct dma_pl330_chan *pch = to_pchan(chan);
2268
2269 memcpy(&pch->slave_config, slave_config, sizeof(*slave_config));
2270
2271 return 0;
2272}
2273
2274static int pl330_terminate_all(struct dma_chan *chan)
2275{
2276 struct dma_pl330_chan *pch = to_pchan(chan);
2277 struct dma_pl330_desc *desc;
2278 unsigned long flags;
2279 struct pl330_dmac *pl330 = pch->dmac;
2280 bool power_down = false;
2281
2282 pm_runtime_get_sync(pl330->ddma.dev);
2283 spin_lock_irqsave(&pch->lock, flags);
2284
2285 spin_lock(&pl330->lock);
2286 _stop(pch->thread);
2287 pch->thread->req[0].desc = NULL;
2288 pch->thread->req[1].desc = NULL;
2289 pch->thread->req_running = -1;
2290 spin_unlock(&pl330->lock);
2291
2292 power_down = pch->active;
2293 pch->active = false;
2294
2295 /* Mark all desc done */
2296 list_for_each_entry(desc, &pch->submitted_list, node) {
2297 desc->status = FREE;
2298 dma_cookie_complete(&desc->txd);
2299 }
2300
2301 list_for_each_entry(desc, &pch->work_list , node) {
2302 desc->status = FREE;
2303 dma_cookie_complete(&desc->txd);
2304 }
2305
2306 list_splice_tail_init(&pch->submitted_list, &pl330->desc_pool);
2307 list_splice_tail_init(&pch->work_list, &pl330->desc_pool);
2308 list_splice_tail_init(&pch->completed_list, &pl330->desc_pool);
2309 spin_unlock_irqrestore(&pch->lock, flags);
2310 pm_runtime_mark_last_busy(pl330->ddma.dev);
2311 if (power_down)
2312 pm_runtime_put_autosuspend(pl330->ddma.dev);
2313 pm_runtime_put_autosuspend(pl330->ddma.dev);
2314
2315 return 0;
2316}
2317
2318/*
2319 * We don't support DMA_RESUME command because of hardware
2320 * limitations, so after pausing the channel we cannot restore
2321 * it to active state. We have to terminate channel and setup
2322 * DMA transfer again. This pause feature was implemented to
2323 * allow safely read residue before channel termination.
2324 */
2325static int pl330_pause(struct dma_chan *chan)
2326{
2327 struct dma_pl330_chan *pch = to_pchan(chan);
2328 struct pl330_dmac *pl330 = pch->dmac;
2329 unsigned long flags;
2330
2331 pm_runtime_get_sync(pl330->ddma.dev);
2332 spin_lock_irqsave(&pch->lock, flags);
2333
2334 spin_lock(&pl330->lock);
2335 _stop(pch->thread);
2336 spin_unlock(&pl330->lock);
2337
2338 spin_unlock_irqrestore(&pch->lock, flags);
2339 pm_runtime_mark_last_busy(pl330->ddma.dev);
2340 pm_runtime_put_autosuspend(pl330->ddma.dev);
2341
2342 return 0;
2343}
2344
2345static void pl330_free_chan_resources(struct dma_chan *chan)
2346{
2347 struct dma_pl330_chan *pch = to_pchan(chan);
2348 struct pl330_dmac *pl330 = pch->dmac;
2349 unsigned long flags;
2350
2351 tasklet_kill(&pch->task);
2352
2353 pm_runtime_get_sync(pch->dmac->ddma.dev);
2354 spin_lock_irqsave(&pl330->lock, flags);
2355
2356 pl330_release_channel(pch->thread);
2357 pch->thread = NULL;
2358
2359 if (pch->cyclic)
2360 list_splice_tail_init(&pch->work_list, &pch->dmac->desc_pool);
2361
2362 spin_unlock_irqrestore(&pl330->lock, flags);
2363 pm_runtime_mark_last_busy(pch->dmac->ddma.dev);
2364 pm_runtime_put_autosuspend(pch->dmac->ddma.dev);
2365 pl330_unprep_slave_fifo(pch);
2366}
2367
2368static int pl330_get_current_xferred_count(struct dma_pl330_chan *pch,
2369 struct dma_pl330_desc *desc)
2370{
2371 struct pl330_thread *thrd = pch->thread;
2372 struct pl330_dmac *pl330 = pch->dmac;
2373 void __iomem *regs = thrd->dmac->base;
2374 u32 val, addr;
2375
2376 pm_runtime_get_sync(pl330->ddma.dev);
2377 val = addr = 0;
2378 if (desc->rqcfg.src_inc) {
2379 val = readl(regs + SA(thrd->id));
2380 addr = desc->px.src_addr;
2381 } else {
2382 val = readl(regs + DA(thrd->id));
2383 addr = desc->px.dst_addr;
2384 }
2385 pm_runtime_mark_last_busy(pch->dmac->ddma.dev);
2386 pm_runtime_put_autosuspend(pl330->ddma.dev);
2387
2388 /* If DMAMOV hasn't finished yet, SAR/DAR can be zero */
2389 if (!val)
2390 return 0;
2391
2392 return val - addr;
2393}
2394
2395static enum dma_status
2396pl330_tx_status(struct dma_chan *chan, dma_cookie_t cookie,
2397 struct dma_tx_state *txstate)
2398{
2399 enum dma_status ret;
2400 unsigned long flags;
2401 struct dma_pl330_desc *desc, *running = NULL, *last_enq = NULL;
2402 struct dma_pl330_chan *pch = to_pchan(chan);
2403 unsigned int transferred, residual = 0;
2404
2405 ret = dma_cookie_status(chan, cookie, txstate);
2406
2407 if (!txstate)
2408 return ret;
2409
2410 if (ret == DMA_COMPLETE)
2411 goto out;
2412
2413 spin_lock_irqsave(&pch->lock, flags);
2414 spin_lock(&pch->thread->dmac->lock);
2415
2416 if (pch->thread->req_running != -1)
2417 running = pch->thread->req[pch->thread->req_running].desc;
2418
2419 last_enq = pch->thread->req[pch->thread->lstenq].desc;
2420
2421 /* Check in pending list */
2422 list_for_each_entry(desc, &pch->work_list, node) {
2423 if (desc->status == DONE)
2424 transferred = desc->bytes_requested;
2425 else if (running && desc == running)
2426 transferred =
2427 pl330_get_current_xferred_count(pch, desc);
2428 else if (desc->status == BUSY)
2429 /*
2430 * Busy but not running means either just enqueued,
2431 * or finished and not yet marked done
2432 */
2433 if (desc == last_enq)
2434 transferred = 0;
2435 else
2436 transferred = desc->bytes_requested;
2437 else
2438 transferred = 0;
2439 residual += desc->bytes_requested - transferred;
2440 if (desc->txd.cookie == cookie) {
2441 switch (desc->status) {
2442 case DONE:
2443 ret = DMA_COMPLETE;
2444 break;
2445 case PREP:
2446 case BUSY:
2447 ret = DMA_IN_PROGRESS;
2448 break;
2449 default:
2450 WARN_ON(1);
2451 }
2452 break;
2453 }
2454 if (desc->last)
2455 residual = 0;
2456 }
2457 spin_unlock(&pch->thread->dmac->lock);
2458 spin_unlock_irqrestore(&pch->lock, flags);
2459
2460out:
2461 dma_set_residue(txstate, residual);
2462
2463 return ret;
2464}
2465
2466static void pl330_issue_pending(struct dma_chan *chan)
2467{
2468 struct dma_pl330_chan *pch = to_pchan(chan);
2469 unsigned long flags;
2470
2471 spin_lock_irqsave(&pch->lock, flags);
2472 if (list_empty(&pch->work_list)) {
2473 /*
2474 * Warn on nothing pending. Empty submitted_list may
2475 * break our pm_runtime usage counter as it is
2476 * updated on work_list emptiness status.
2477 */
2478 WARN_ON(list_empty(&pch->submitted_list));
2479 pch->active = true;
2480 pm_runtime_get_sync(pch->dmac->ddma.dev);
2481 }
2482 list_splice_tail_init(&pch->submitted_list, &pch->work_list);
2483 spin_unlock_irqrestore(&pch->lock, flags);
2484
2485 pl330_tasklet(&pch->task);
2486}
2487
2488/*
2489 * We returned the last one of the circular list of descriptor(s)
2490 * from prep_xxx, so the argument to submit corresponds to the last
2491 * descriptor of the list.
2492 */
2493static dma_cookie_t pl330_tx_submit(struct dma_async_tx_descriptor *tx)
2494{
2495 struct dma_pl330_desc *desc, *last = to_desc(tx);
2496 struct dma_pl330_chan *pch = to_pchan(tx->chan);
2497 dma_cookie_t cookie;
2498 unsigned long flags;
2499
2500 spin_lock_irqsave(&pch->lock, flags);
2501
2502 /* Assign cookies to all nodes */
2503 while (!list_empty(&last->node)) {
2504 desc = list_entry(last->node.next, struct dma_pl330_desc, node);
2505 if (pch->cyclic) {
2506 desc->txd.callback = last->txd.callback;
2507 desc->txd.callback_param = last->txd.callback_param;
2508 }
2509 desc->last = false;
2510
2511 dma_cookie_assign(&desc->txd);
2512
2513 list_move_tail(&desc->node, &pch->submitted_list);
2514 }
2515
2516 last->last = true;
2517 cookie = dma_cookie_assign(&last->txd);
2518 list_add_tail(&last->node, &pch->submitted_list);
2519 spin_unlock_irqrestore(&pch->lock, flags);
2520
2521 return cookie;
2522}
2523
2524static inline void _init_desc(struct dma_pl330_desc *desc)
2525{
2526 desc->rqcfg.swap = SWAP_NO;
2527 desc->rqcfg.scctl = CCTRL0;
2528 desc->rqcfg.dcctl = CCTRL0;
2529 desc->txd.tx_submit = pl330_tx_submit;
2530
2531 INIT_LIST_HEAD(&desc->node);
2532}
2533
2534/* Returns the number of descriptors added to the DMAC pool */
2535static int add_desc(struct list_head *pool, spinlock_t *lock,
2536 gfp_t flg, int count)
2537{
2538 struct dma_pl330_desc *desc;
2539 unsigned long flags;
2540 int i;
2541
2542 desc = kcalloc(count, sizeof(*desc), flg);
2543 if (!desc)
2544 return 0;
2545
2546 spin_lock_irqsave(lock, flags);
2547
2548 for (i = 0; i < count; i++) {
2549 _init_desc(&desc[i]);
2550 list_add_tail(&desc[i].node, pool);
2551 }
2552
2553 spin_unlock_irqrestore(lock, flags);
2554
2555 return count;
2556}
2557
2558static struct dma_pl330_desc *pluck_desc(struct list_head *pool,
2559 spinlock_t *lock)
2560{
2561 struct dma_pl330_desc *desc = NULL;
2562 unsigned long flags;
2563
2564 spin_lock_irqsave(lock, flags);
2565
2566 if (!list_empty(pool)) {
2567 desc = list_entry(pool->next,
2568 struct dma_pl330_desc, node);
2569
2570 list_del_init(&desc->node);
2571
2572 desc->status = PREP;
2573 desc->txd.callback = NULL;
2574 }
2575
2576 spin_unlock_irqrestore(lock, flags);
2577
2578 return desc;
2579}
2580
2581static struct dma_pl330_desc *pl330_get_desc(struct dma_pl330_chan *pch)
2582{
2583 struct pl330_dmac *pl330 = pch->dmac;
2584 u8 *peri_id = pch->chan.private;
2585 struct dma_pl330_desc *desc;
2586
2587 /* Pluck one desc from the pool of DMAC */
2588 desc = pluck_desc(&pl330->desc_pool, &pl330->pool_lock);
2589
2590 /* If the DMAC pool is empty, alloc new */
2591 if (!desc) {
2592 DEFINE_SPINLOCK(lock);
2593 LIST_HEAD(pool);
2594
2595 if (!add_desc(&pool, &lock, GFP_ATOMIC, 1))
2596 return NULL;
2597
2598 desc = pluck_desc(&pool, &lock);
2599 WARN_ON(!desc || !list_empty(&pool));
2600 }
2601
2602 /* Initialize the descriptor */
2603 desc->pchan = pch;
2604 desc->txd.cookie = 0;
2605 async_tx_ack(&desc->txd);
2606
2607 desc->peri = peri_id ? pch->chan.chan_id : 0;
2608 desc->rqcfg.pcfg = &pch->dmac->pcfg;
2609
2610 dma_async_tx_descriptor_init(&desc->txd, &pch->chan);
2611
2612 return desc;
2613}
2614
2615static inline void fill_px(struct pl330_xfer *px,
2616 dma_addr_t dst, dma_addr_t src, size_t len)
2617{
2618 px->bytes = len;
2619 px->dst_addr = dst;
2620 px->src_addr = src;
2621}
2622
2623static struct dma_pl330_desc *
2624__pl330_prep_dma_memcpy(struct dma_pl330_chan *pch, dma_addr_t dst,
2625 dma_addr_t src, size_t len)
2626{
2627 struct dma_pl330_desc *desc = pl330_get_desc(pch);
2628
2629 if (!desc) {
2630 dev_err(pch->dmac->ddma.dev, "%s:%d Unable to fetch desc\n",
2631 __func__, __LINE__);
2632 return NULL;
2633 }
2634
2635 /*
2636 * Ideally we should lookout for reqs bigger than
2637 * those that can be programmed with 256 bytes of
2638 * MC buffer, but considering a req size is seldom
2639 * going to be word-unaligned and more than 200MB,
2640 * we take it easy.
2641 * Also, should the limit is reached we'd rather
2642 * have the platform increase MC buffer size than
2643 * complicating this API driver.
2644 */
2645 fill_px(&desc->px, dst, src, len);
2646
2647 return desc;
2648}
2649
2650/* Call after fixing burst size */
2651static inline int get_burst_len(struct dma_pl330_desc *desc, size_t len)
2652{
2653 struct dma_pl330_chan *pch = desc->pchan;
2654 struct pl330_dmac *pl330 = pch->dmac;
2655 int burst_len;
2656
2657 burst_len = pl330->pcfg.data_bus_width / 8;
2658 burst_len *= pl330->pcfg.data_buf_dep / pl330->pcfg.num_chan;
2659 burst_len >>= desc->rqcfg.brst_size;
2660
2661 /* src/dst_burst_len can't be more than 16 */
2662 if (burst_len > PL330_MAX_BURST)
2663 burst_len = PL330_MAX_BURST;
2664
2665 return burst_len;
2666}
2667
2668static struct dma_async_tx_descriptor *pl330_prep_dma_cyclic(
2669 struct dma_chan *chan, dma_addr_t dma_addr, size_t len,
2670 size_t period_len, enum dma_transfer_direction direction,
2671 unsigned long flags)
2672{
2673 struct dma_pl330_desc *desc = NULL, *first = NULL;
2674 struct dma_pl330_chan *pch = to_pchan(chan);
2675 struct pl330_dmac *pl330 = pch->dmac;
2676 unsigned int i;
2677 dma_addr_t dst;
2678 dma_addr_t src;
2679
2680 if (len % period_len != 0)
2681 return NULL;
2682
2683 if (!is_slave_direction(direction)) {
2684 dev_err(pch->dmac->ddma.dev, "%s:%d Invalid dma direction\n",
2685 __func__, __LINE__);
2686 return NULL;
2687 }
2688
2689 pl330_config_write(chan, &pch->slave_config, direction);
2690
2691 if (!pl330_prep_slave_fifo(pch, direction))
2692 return NULL;
2693
2694 for (i = 0; i < len / period_len; i++) {
2695 desc = pl330_get_desc(pch);
2696 if (!desc) {
2697 unsigned long iflags;
2698
2699 dev_err(pch->dmac->ddma.dev, "%s:%d Unable to fetch desc\n",
2700 __func__, __LINE__);
2701
2702 if (!first)
2703 return NULL;
2704
2705 spin_lock_irqsave(&pl330->pool_lock, iflags);
2706
2707 while (!list_empty(&first->node)) {
2708 desc = list_entry(first->node.next,
2709 struct dma_pl330_desc, node);
2710 list_move_tail(&desc->node, &pl330->desc_pool);
2711 }
2712
2713 list_move_tail(&first->node, &pl330->desc_pool);
2714
2715 spin_unlock_irqrestore(&pl330->pool_lock, iflags);
2716
2717 return NULL;
2718 }
2719
2720 switch (direction) {
2721 case DMA_MEM_TO_DEV:
2722 desc->rqcfg.src_inc = 1;
2723 desc->rqcfg.dst_inc = 0;
2724 src = dma_addr;
2725 dst = pch->fifo_dma;
2726 break;
2727 case DMA_DEV_TO_MEM:
2728 desc->rqcfg.src_inc = 0;
2729 desc->rqcfg.dst_inc = 1;
2730 src = pch->fifo_dma;
2731 dst = dma_addr;
2732 break;
2733 default:
2734 break;
2735 }
2736
2737 desc->rqtype = direction;
2738 desc->rqcfg.brst_size = pch->burst_sz;
2739 desc->rqcfg.brst_len = pch->burst_len;
2740 desc->bytes_requested = period_len;
2741 fill_px(&desc->px, dst, src, period_len);
2742
2743 if (!first)
2744 first = desc;
2745 else
2746 list_add_tail(&desc->node, &first->node);
2747
2748 dma_addr += period_len;
2749 }
2750
2751 if (!desc)
2752 return NULL;
2753
2754 pch->cyclic = true;
2755 desc->txd.flags = flags;
2756
2757 return &desc->txd;
2758}
2759
2760static struct dma_async_tx_descriptor *
2761pl330_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dst,
2762 dma_addr_t src, size_t len, unsigned long flags)
2763{
2764 struct dma_pl330_desc *desc;
2765 struct dma_pl330_chan *pch = to_pchan(chan);
2766 struct pl330_dmac *pl330;
2767 int burst;
2768
2769 if (unlikely(!pch || !len))
2770 return NULL;
2771
2772 pl330 = pch->dmac;
2773
2774 desc = __pl330_prep_dma_memcpy(pch, dst, src, len);
2775 if (!desc)
2776 return NULL;
2777
2778 desc->rqcfg.src_inc = 1;
2779 desc->rqcfg.dst_inc = 1;
2780 desc->rqtype = DMA_MEM_TO_MEM;
2781
2782 /* Select max possible burst size */
2783 burst = pl330->pcfg.data_bus_width / 8;
2784
2785 /*
2786 * Make sure we use a burst size that aligns with all the memcpy
2787 * parameters because our DMA programming algorithm doesn't cope with
2788 * transfers which straddle an entry in the DMA device's MFIFO.
2789 */
2790 while ((src | dst | len) & (burst - 1))
2791 burst /= 2;
2792
2793 desc->rqcfg.brst_size = 0;
2794 while (burst != (1 << desc->rqcfg.brst_size))
2795 desc->rqcfg.brst_size++;
2796
2797 desc->rqcfg.brst_len = get_burst_len(desc, len);
2798 /*
2799 * If burst size is smaller than bus width then make sure we only
2800 * transfer one at a time to avoid a burst stradling an MFIFO entry.
2801 */
2802 if (burst * 8 < pl330->pcfg.data_bus_width)
2803 desc->rqcfg.brst_len = 1;
2804
2805 desc->bytes_requested = len;
2806
2807 desc->txd.flags = flags;
2808
2809 return &desc->txd;
2810}
2811
2812static void __pl330_giveback_desc(struct pl330_dmac *pl330,
2813 struct dma_pl330_desc *first)
2814{
2815 unsigned long flags;
2816 struct dma_pl330_desc *desc;
2817
2818 if (!first)
2819 return;
2820
2821 spin_lock_irqsave(&pl330->pool_lock, flags);
2822
2823 while (!list_empty(&first->node)) {
2824 desc = list_entry(first->node.next,
2825 struct dma_pl330_desc, node);
2826 list_move_tail(&desc->node, &pl330->desc_pool);
2827 }
2828
2829 list_move_tail(&first->node, &pl330->desc_pool);
2830
2831 spin_unlock_irqrestore(&pl330->pool_lock, flags);
2832}
2833
2834static struct dma_async_tx_descriptor *
2835pl330_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
2836 unsigned int sg_len, enum dma_transfer_direction direction,
2837 unsigned long flg, void *context)
2838{
2839 struct dma_pl330_desc *first, *desc = NULL;
2840 struct dma_pl330_chan *pch = to_pchan(chan);
2841 struct scatterlist *sg;
2842 int i;
2843
2844 if (unlikely(!pch || !sgl || !sg_len))
2845 return NULL;
2846
2847 pl330_config_write(chan, &pch->slave_config, direction);
2848
2849 if (!pl330_prep_slave_fifo(pch, direction))
2850 return NULL;
2851
2852 first = NULL;
2853
2854 for_each_sg(sgl, sg, sg_len, i) {
2855
2856 desc = pl330_get_desc(pch);
2857 if (!desc) {
2858 struct pl330_dmac *pl330 = pch->dmac;
2859
2860 dev_err(pch->dmac->ddma.dev,
2861 "%s:%d Unable to fetch desc\n",
2862 __func__, __LINE__);
2863 __pl330_giveback_desc(pl330, first);
2864
2865 return NULL;
2866 }
2867
2868 if (!first)
2869 first = desc;
2870 else
2871 list_add_tail(&desc->node, &first->node);
2872
2873 if (direction == DMA_MEM_TO_DEV) {
2874 desc->rqcfg.src_inc = 1;
2875 desc->rqcfg.dst_inc = 0;
2876 fill_px(&desc->px, pch->fifo_dma, sg_dma_address(sg),
2877 sg_dma_len(sg));
2878 } else {
2879 desc->rqcfg.src_inc = 0;
2880 desc->rqcfg.dst_inc = 1;
2881 fill_px(&desc->px, sg_dma_address(sg), pch->fifo_dma,
2882 sg_dma_len(sg));
2883 }
2884
2885 desc->rqcfg.brst_size = pch->burst_sz;
2886 desc->rqcfg.brst_len = pch->burst_len;
2887 desc->rqtype = direction;
2888 desc->bytes_requested = sg_dma_len(sg);
2889 }
2890
2891 /* Return the last desc in the chain */
2892 desc->txd.flags = flg;
2893 return &desc->txd;
2894}
2895
2896static irqreturn_t pl330_irq_handler(int irq, void *data)
2897{
2898 if (pl330_update(data))
2899 return IRQ_HANDLED;
2900 else
2901 return IRQ_NONE;
2902}
2903
2904#define PL330_DMA_BUSWIDTHS \
2905 BIT(DMA_SLAVE_BUSWIDTH_UNDEFINED) | \
2906 BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | \
2907 BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | \
2908 BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) | \
2909 BIT(DMA_SLAVE_BUSWIDTH_8_BYTES)
2910
2911#ifdef CONFIG_DEBUG_FS
2912static int pl330_debugfs_show(struct seq_file *s, void *data)
2913{
2914 struct pl330_dmac *pl330 = s->private;
2915 int chans, pchs, ch, pr;
2916
2917 chans = pl330->pcfg.num_chan;
2918 pchs = pl330->num_peripherals;
2919
2920 seq_puts(s, "PL330 physical channels:\n");
2921 seq_puts(s, "THREAD:\t\tCHANNEL:\n");
2922 seq_puts(s, "--------\t-----\n");
2923 for (ch = 0; ch < chans; ch++) {
2924 struct pl330_thread *thrd = &pl330->channels[ch];
2925 int found = -1;
2926
2927 for (pr = 0; pr < pchs; pr++) {
2928 struct dma_pl330_chan *pch = &pl330->peripherals[pr];
2929
2930 if (!pch->thread || thrd->id != pch->thread->id)
2931 continue;
2932
2933 found = pr;
2934 }
2935
2936 seq_printf(s, "%d\t\t", thrd->id);
2937 if (found == -1)
2938 seq_puts(s, "--\n");
2939 else
2940 seq_printf(s, "%d\n", found);
2941 }
2942
2943 return 0;
2944}
2945
2946DEFINE_SHOW_ATTRIBUTE(pl330_debugfs);
2947
2948static inline void init_pl330_debugfs(struct pl330_dmac *pl330)
2949{
2950 debugfs_create_file(dev_name(pl330->ddma.dev),
2951 S_IFREG | 0444, NULL, pl330,
2952 &pl330_debugfs_fops);
2953}
2954#else
2955static inline void init_pl330_debugfs(struct pl330_dmac *pl330)
2956{
2957}
2958#endif
2959
2960/*
2961 * Runtime PM callbacks are provided by amba/bus.c driver.
2962 *
2963 * It is assumed here that IRQ safe runtime PM is chosen in probe and amba
2964 * bus driver will only disable/enable the clock in runtime PM callbacks.
2965 */
2966static int __maybe_unused pl330_suspend(struct device *dev)
2967{
2968 struct amba_device *pcdev = to_amba_device(dev);
2969
2970 pm_runtime_force_suspend(dev);
2971 amba_pclk_unprepare(pcdev);
2972
2973 return 0;
2974}
2975
2976static int __maybe_unused pl330_resume(struct device *dev)
2977{
2978 struct amba_device *pcdev = to_amba_device(dev);
2979 int ret;
2980
2981 ret = amba_pclk_prepare(pcdev);
2982 if (ret)
2983 return ret;
2984
2985 pm_runtime_force_resume(dev);
2986
2987 return ret;
2988}
2989
2990static const struct dev_pm_ops pl330_pm = {
2991 SET_LATE_SYSTEM_SLEEP_PM_OPS(pl330_suspend, pl330_resume)
2992};
2993
2994static int
2995pl330_probe(struct amba_device *adev, const struct amba_id *id)
2996{
2997 struct pl330_config *pcfg;
2998 struct pl330_dmac *pl330;
2999 struct dma_pl330_chan *pch, *_p;
3000 struct dma_device *pd;
3001 struct resource *res;
3002 int i, ret, irq;
3003 int num_chan;
3004 struct device_node *np = adev->dev.of_node;
3005
3006 ret = dma_set_mask_and_coherent(&adev->dev, DMA_BIT_MASK(32));
3007 if (ret)
3008 return ret;
3009
3010 /* Allocate a new DMAC and its Channels */
3011 pl330 = devm_kzalloc(&adev->dev, sizeof(*pl330), GFP_KERNEL);
3012 if (!pl330)
3013 return -ENOMEM;
3014
3015 pd = &pl330->ddma;
3016 pd->dev = &adev->dev;
3017
3018 pl330->mcbufsz = 0;
3019
3020 /* get quirk */
3021 for (i = 0; i < ARRAY_SIZE(of_quirks); i++)
3022 if (of_property_read_bool(np, of_quirks[i].quirk))
3023 pl330->quirks |= of_quirks[i].id;
3024
3025 res = &adev->res;
3026 pl330->base = devm_ioremap_resource(&adev->dev, res);
3027 if (IS_ERR(pl330->base))
3028 return PTR_ERR(pl330->base);
3029
3030 amba_set_drvdata(adev, pl330);
3031
3032 pl330->rstc = devm_reset_control_get_optional(&adev->dev, "dma");
3033 if (IS_ERR(pl330->rstc)) {
3034 return dev_err_probe(&adev->dev, PTR_ERR(pl330->rstc), "Failed to get reset!\n");
3035 } else {
3036 ret = reset_control_deassert(pl330->rstc);
3037 if (ret) {
3038 dev_err(&adev->dev, "Couldn't deassert the device from reset!\n");
3039 return ret;
3040 }
3041 }
3042
3043 pl330->rstc_ocp = devm_reset_control_get_optional(&adev->dev, "dma-ocp");
3044 if (IS_ERR(pl330->rstc_ocp)) {
3045 return dev_err_probe(&adev->dev, PTR_ERR(pl330->rstc_ocp),
3046 "Failed to get OCP reset!\n");
3047 } else {
3048 ret = reset_control_deassert(pl330->rstc_ocp);
3049 if (ret) {
3050 dev_err(&adev->dev, "Couldn't deassert the device from OCP reset!\n");
3051 return ret;
3052 }
3053 }
3054
3055 for (i = 0; i < AMBA_NR_IRQS; i++) {
3056 irq = adev->irq[i];
3057 if (irq) {
3058 ret = devm_request_irq(&adev->dev, irq,
3059 pl330_irq_handler, 0,
3060 dev_name(&adev->dev), pl330);
3061 if (ret)
3062 return ret;
3063 } else {
3064 break;
3065 }
3066 }
3067
3068 pcfg = &pl330->pcfg;
3069
3070 pcfg->periph_id = adev->periphid;
3071 ret = pl330_add(pl330);
3072 if (ret)
3073 return ret;
3074
3075 INIT_LIST_HEAD(&pl330->desc_pool);
3076 spin_lock_init(&pl330->pool_lock);
3077
3078 /* Create a descriptor pool of default size */
3079 if (!add_desc(&pl330->desc_pool, &pl330->pool_lock,
3080 GFP_KERNEL, NR_DEFAULT_DESC))
3081 dev_warn(&adev->dev, "unable to allocate desc\n");
3082
3083 INIT_LIST_HEAD(&pd->channels);
3084
3085 /* Initialize channel parameters */
3086 num_chan = max_t(int, pcfg->num_peri, pcfg->num_chan);
3087
3088 pl330->num_peripherals = num_chan;
3089
3090 pl330->peripherals = kcalloc(num_chan, sizeof(*pch), GFP_KERNEL);
3091 if (!pl330->peripherals) {
3092 ret = -ENOMEM;
3093 goto probe_err2;
3094 }
3095
3096 for (i = 0; i < num_chan; i++) {
3097 pch = &pl330->peripherals[i];
3098
3099 pch->chan.private = adev->dev.of_node;
3100 INIT_LIST_HEAD(&pch->submitted_list);
3101 INIT_LIST_HEAD(&pch->work_list);
3102 INIT_LIST_HEAD(&pch->completed_list);
3103 spin_lock_init(&pch->lock);
3104 pch->thread = NULL;
3105 pch->chan.device = pd;
3106 pch->dmac = pl330;
3107 pch->dir = DMA_NONE;
3108
3109 /* Add the channel to the DMAC list */
3110 list_add_tail(&pch->chan.device_node, &pd->channels);
3111 }
3112
3113 dma_cap_set(DMA_MEMCPY, pd->cap_mask);
3114 if (pcfg->num_peri) {
3115 dma_cap_set(DMA_SLAVE, pd->cap_mask);
3116 dma_cap_set(DMA_CYCLIC, pd->cap_mask);
3117 dma_cap_set(DMA_PRIVATE, pd->cap_mask);
3118 }
3119
3120 pd->device_alloc_chan_resources = pl330_alloc_chan_resources;
3121 pd->device_free_chan_resources = pl330_free_chan_resources;
3122 pd->device_prep_dma_memcpy = pl330_prep_dma_memcpy;
3123 pd->device_prep_dma_cyclic = pl330_prep_dma_cyclic;
3124 pd->device_tx_status = pl330_tx_status;
3125 pd->device_prep_slave_sg = pl330_prep_slave_sg;
3126 pd->device_config = pl330_config;
3127 pd->device_pause = pl330_pause;
3128 pd->device_terminate_all = pl330_terminate_all;
3129 pd->device_issue_pending = pl330_issue_pending;
3130 pd->src_addr_widths = PL330_DMA_BUSWIDTHS;
3131 pd->dst_addr_widths = PL330_DMA_BUSWIDTHS;
3132 pd->directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV);
3133 pd->residue_granularity = DMA_RESIDUE_GRANULARITY_BURST;
3134 pd->max_burst = PL330_MAX_BURST;
3135
3136 ret = dma_async_device_register(pd);
3137 if (ret) {
3138 dev_err(&adev->dev, "unable to register DMAC\n");
3139 goto probe_err3;
3140 }
3141
3142 if (adev->dev.of_node) {
3143 ret = of_dma_controller_register(adev->dev.of_node,
3144 of_dma_pl330_xlate, pl330);
3145 if (ret) {
3146 dev_err(&adev->dev,
3147 "unable to register DMA to the generic DT DMA helpers\n");
3148 }
3149 }
3150
3151 /*
3152 * This is the limit for transfers with a buswidth of 1, larger
3153 * buswidths will have larger limits.
3154 */
3155 ret = dma_set_max_seg_size(&adev->dev, 1900800);
3156 if (ret)
3157 dev_err(&adev->dev, "unable to set the seg size\n");
3158
3159
3160 init_pl330_debugfs(pl330);
3161 dev_info(&adev->dev,
3162 "Loaded driver for PL330 DMAC-%x\n", adev->periphid);
3163 dev_info(&adev->dev,
3164 "\tDBUFF-%ux%ubytes Num_Chans-%u Num_Peri-%u Num_Events-%u\n",
3165 pcfg->data_buf_dep, pcfg->data_bus_width / 8, pcfg->num_chan,
3166 pcfg->num_peri, pcfg->num_events);
3167
3168 pm_runtime_irq_safe(&adev->dev);
3169 pm_runtime_use_autosuspend(&adev->dev);
3170 pm_runtime_set_autosuspend_delay(&adev->dev, PL330_AUTOSUSPEND_DELAY);
3171 pm_runtime_mark_last_busy(&adev->dev);
3172 pm_runtime_put_autosuspend(&adev->dev);
3173
3174 return 0;
3175probe_err3:
3176 /* Idle the DMAC */
3177 list_for_each_entry_safe(pch, _p, &pl330->ddma.channels,
3178 chan.device_node) {
3179
3180 /* Remove the channel */
3181 list_del(&pch->chan.device_node);
3182
3183 /* Flush the channel */
3184 if (pch->thread) {
3185 pl330_terminate_all(&pch->chan);
3186 pl330_free_chan_resources(&pch->chan);
3187 }
3188 }
3189probe_err2:
3190 pl330_del(pl330);
3191
3192 if (pl330->rstc_ocp)
3193 reset_control_assert(pl330->rstc_ocp);
3194
3195 if (pl330->rstc)
3196 reset_control_assert(pl330->rstc);
3197 return ret;
3198}
3199
3200static void pl330_remove(struct amba_device *adev)
3201{
3202 struct pl330_dmac *pl330 = amba_get_drvdata(adev);
3203 struct dma_pl330_chan *pch, *_p;
3204 int i, irq;
3205
3206 pm_runtime_get_noresume(pl330->ddma.dev);
3207
3208 if (adev->dev.of_node)
3209 of_dma_controller_free(adev->dev.of_node);
3210
3211 for (i = 0; i < AMBA_NR_IRQS; i++) {
3212 irq = adev->irq[i];
3213 if (irq)
3214 devm_free_irq(&adev->dev, irq, pl330);
3215 }
3216
3217 dma_async_device_unregister(&pl330->ddma);
3218
3219 /* Idle the DMAC */
3220 list_for_each_entry_safe(pch, _p, &pl330->ddma.channels,
3221 chan.device_node) {
3222
3223 /* Remove the channel */
3224 list_del(&pch->chan.device_node);
3225
3226 /* Flush the channel */
3227 if (pch->thread) {
3228 pl330_terminate_all(&pch->chan);
3229 pl330_free_chan_resources(&pch->chan);
3230 }
3231 }
3232
3233 pl330_del(pl330);
3234
3235 if (pl330->rstc_ocp)
3236 reset_control_assert(pl330->rstc_ocp);
3237
3238 if (pl330->rstc)
3239 reset_control_assert(pl330->rstc);
3240}
3241
3242static const struct amba_id pl330_ids[] = {
3243 {
3244 .id = 0x00041330,
3245 .mask = 0x000fffff,
3246 },
3247 { 0, 0 },
3248};
3249
3250MODULE_DEVICE_TABLE(amba, pl330_ids);
3251
3252static struct amba_driver pl330_driver = {
3253 .drv = {
3254 .owner = THIS_MODULE,
3255 .name = "dma-pl330",
3256 .pm = &pl330_pm,
3257 },
3258 .id_table = pl330_ids,
3259 .probe = pl330_probe,
3260 .remove = pl330_remove,
3261};
3262
3263module_amba_driver(pl330_driver);
3264
3265MODULE_AUTHOR("Jaswinder Singh <jassisinghbrar@gmail.com>");
3266MODULE_DESCRIPTION("API Driver for PL330 DMAC");
3267MODULE_LICENSE("GPL");