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1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * Copyright (c) 2012 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * Copyright (C) 2010 Samsung Electronics Co. Ltd.
7 * Jaswinder Singh <jassi.brar@samsung.com>
8 */
9
10#include <linux/debugfs.h>
11#include <linux/kernel.h>
12#include <linux/io.h>
13#include <linux/init.h>
14#include <linux/slab.h>
15#include <linux/module.h>
16#include <linux/string.h>
17#include <linux/delay.h>
18#include <linux/interrupt.h>
19#include <linux/dma-mapping.h>
20#include <linux/dmaengine.h>
21#include <linux/amba/bus.h>
22#include <linux/scatterlist.h>
23#include <linux/of.h>
24#include <linux/of_dma.h>
25#include <linux/err.h>
26#include <linux/pm_runtime.h>
27#include <linux/bug.h>
28#include <linux/reset.h>
29
30#include "dmaengine.h"
31#define PL330_MAX_CHAN 8
32#define PL330_MAX_IRQS 32
33#define PL330_MAX_PERI 32
34#define PL330_MAX_BURST 16
35
36#define PL330_QUIRK_BROKEN_NO_FLUSHP BIT(0)
37#define PL330_QUIRK_PERIPH_BURST BIT(1)
38
39enum pl330_cachectrl {
40 CCTRL0, /* Noncacheable and nonbufferable */
41 CCTRL1, /* Bufferable only */
42 CCTRL2, /* Cacheable, but do not allocate */
43 CCTRL3, /* Cacheable and bufferable, but do not allocate */
44 INVALID1, /* AWCACHE = 0x1000 */
45 INVALID2,
46 CCTRL6, /* Cacheable write-through, allocate on writes only */
47 CCTRL7, /* Cacheable write-back, allocate on writes only */
48};
49
50enum pl330_byteswap {
51 SWAP_NO,
52 SWAP_2,
53 SWAP_4,
54 SWAP_8,
55 SWAP_16,
56};
57
58/* Register and Bit field Definitions */
59#define DS 0x0
60#define DS_ST_STOP 0x0
61#define DS_ST_EXEC 0x1
62#define DS_ST_CMISS 0x2
63#define DS_ST_UPDTPC 0x3
64#define DS_ST_WFE 0x4
65#define DS_ST_ATBRR 0x5
66#define DS_ST_QBUSY 0x6
67#define DS_ST_WFP 0x7
68#define DS_ST_KILL 0x8
69#define DS_ST_CMPLT 0x9
70#define DS_ST_FLTCMP 0xe
71#define DS_ST_FAULT 0xf
72
73#define DPC 0x4
74#define INTEN 0x20
75#define ES 0x24
76#define INTSTATUS 0x28
77#define INTCLR 0x2c
78#define FSM 0x30
79#define FSC 0x34
80#define FTM 0x38
81
82#define _FTC 0x40
83#define FTC(n) (_FTC + (n)*0x4)
84
85#define _CS 0x100
86#define CS(n) (_CS + (n)*0x8)
87#define CS_CNS (1 << 21)
88
89#define _CPC 0x104
90#define CPC(n) (_CPC + (n)*0x8)
91
92#define _SA 0x400
93#define SA(n) (_SA + (n)*0x20)
94
95#define _DA 0x404
96#define DA(n) (_DA + (n)*0x20)
97
98#define _CC 0x408
99#define CC(n) (_CC + (n)*0x20)
100
101#define CC_SRCINC (1 << 0)
102#define CC_DSTINC (1 << 14)
103#define CC_SRCPRI (1 << 8)
104#define CC_DSTPRI (1 << 22)
105#define CC_SRCNS (1 << 9)
106#define CC_DSTNS (1 << 23)
107#define CC_SRCIA (1 << 10)
108#define CC_DSTIA (1 << 24)
109#define CC_SRCBRSTLEN_SHFT 4
110#define CC_DSTBRSTLEN_SHFT 18
111#define CC_SRCBRSTSIZE_SHFT 1
112#define CC_DSTBRSTSIZE_SHFT 15
113#define CC_SRCCCTRL_SHFT 11
114#define CC_SRCCCTRL_MASK 0x7
115#define CC_DSTCCTRL_SHFT 25
116#define CC_DRCCCTRL_MASK 0x7
117#define CC_SWAP_SHFT 28
118
119#define _LC0 0x40c
120#define LC0(n) (_LC0 + (n)*0x20)
121
122#define _LC1 0x410
123#define LC1(n) (_LC1 + (n)*0x20)
124
125#define DBGSTATUS 0xd00
126#define DBG_BUSY (1 << 0)
127
128#define DBGCMD 0xd04
129#define DBGINST0 0xd08
130#define DBGINST1 0xd0c
131
132#define CR0 0xe00
133#define CR1 0xe04
134#define CR2 0xe08
135#define CR3 0xe0c
136#define CR4 0xe10
137#define CRD 0xe14
138
139#define PERIPH_ID 0xfe0
140#define PERIPH_REV_SHIFT 20
141#define PERIPH_REV_MASK 0xf
142#define PERIPH_REV_R0P0 0
143#define PERIPH_REV_R1P0 1
144#define PERIPH_REV_R1P1 2
145
146#define CR0_PERIPH_REQ_SET (1 << 0)
147#define CR0_BOOT_EN_SET (1 << 1)
148#define CR0_BOOT_MAN_NS (1 << 2)
149#define CR0_NUM_CHANS_SHIFT 4
150#define CR0_NUM_CHANS_MASK 0x7
151#define CR0_NUM_PERIPH_SHIFT 12
152#define CR0_NUM_PERIPH_MASK 0x1f
153#define CR0_NUM_EVENTS_SHIFT 17
154#define CR0_NUM_EVENTS_MASK 0x1f
155
156#define CR1_ICACHE_LEN_SHIFT 0
157#define CR1_ICACHE_LEN_MASK 0x7
158#define CR1_NUM_ICACHELINES_SHIFT 4
159#define CR1_NUM_ICACHELINES_MASK 0xf
160
161#define CRD_DATA_WIDTH_SHIFT 0
162#define CRD_DATA_WIDTH_MASK 0x7
163#define CRD_WR_CAP_SHIFT 4
164#define CRD_WR_CAP_MASK 0x7
165#define CRD_WR_Q_DEP_SHIFT 8
166#define CRD_WR_Q_DEP_MASK 0xf
167#define CRD_RD_CAP_SHIFT 12
168#define CRD_RD_CAP_MASK 0x7
169#define CRD_RD_Q_DEP_SHIFT 16
170#define CRD_RD_Q_DEP_MASK 0xf
171#define CRD_DATA_BUFF_SHIFT 20
172#define CRD_DATA_BUFF_MASK 0x3ff
173
174#define PART 0x330
175#define DESIGNER 0x41
176#define REVISION 0x0
177#define INTEG_CFG 0x0
178#define PERIPH_ID_VAL ((PART << 0) | (DESIGNER << 12))
179
180#define PL330_STATE_STOPPED (1 << 0)
181#define PL330_STATE_EXECUTING (1 << 1)
182#define PL330_STATE_WFE (1 << 2)
183#define PL330_STATE_FAULTING (1 << 3)
184#define PL330_STATE_COMPLETING (1 << 4)
185#define PL330_STATE_WFP (1 << 5)
186#define PL330_STATE_KILLING (1 << 6)
187#define PL330_STATE_FAULT_COMPLETING (1 << 7)
188#define PL330_STATE_CACHEMISS (1 << 8)
189#define PL330_STATE_UPDTPC (1 << 9)
190#define PL330_STATE_ATBARRIER (1 << 10)
191#define PL330_STATE_QUEUEBUSY (1 << 11)
192#define PL330_STATE_INVALID (1 << 15)
193
194#define PL330_STABLE_STATES (PL330_STATE_STOPPED | PL330_STATE_EXECUTING \
195 | PL330_STATE_WFE | PL330_STATE_FAULTING)
196
197#define CMD_DMAADDH 0x54
198#define CMD_DMAEND 0x00
199#define CMD_DMAFLUSHP 0x35
200#define CMD_DMAGO 0xa0
201#define CMD_DMALD 0x04
202#define CMD_DMALDP 0x25
203#define CMD_DMALP 0x20
204#define CMD_DMALPEND 0x28
205#define CMD_DMAKILL 0x01
206#define CMD_DMAMOV 0xbc
207#define CMD_DMANOP 0x18
208#define CMD_DMARMB 0x12
209#define CMD_DMASEV 0x34
210#define CMD_DMAST 0x08
211#define CMD_DMASTP 0x29
212#define CMD_DMASTZ 0x0c
213#define CMD_DMAWFE 0x36
214#define CMD_DMAWFP 0x30
215#define CMD_DMAWMB 0x13
216
217#define SZ_DMAADDH 3
218#define SZ_DMAEND 1
219#define SZ_DMAFLUSHP 2
220#define SZ_DMALD 1
221#define SZ_DMALDP 2
222#define SZ_DMALP 2
223#define SZ_DMALPEND 2
224#define SZ_DMAKILL 1
225#define SZ_DMAMOV 6
226#define SZ_DMANOP 1
227#define SZ_DMARMB 1
228#define SZ_DMASEV 2
229#define SZ_DMAST 1
230#define SZ_DMASTP 2
231#define SZ_DMASTZ 1
232#define SZ_DMAWFE 2
233#define SZ_DMAWFP 2
234#define SZ_DMAWMB 1
235#define SZ_DMAGO 6
236
237#define BRST_LEN(ccr) ((((ccr) >> CC_SRCBRSTLEN_SHFT) & 0xf) + 1)
238#define BRST_SIZE(ccr) (1 << (((ccr) >> CC_SRCBRSTSIZE_SHFT) & 0x7))
239
240#define BYTE_TO_BURST(b, ccr) ((b) / BRST_SIZE(ccr) / BRST_LEN(ccr))
241#define BURST_TO_BYTE(c, ccr) ((c) * BRST_SIZE(ccr) * BRST_LEN(ccr))
242
243/*
244 * With 256 bytes, we can do more than 2.5MB and 5MB xfers per req
245 * at 1byte/burst for P<->M and M<->M respectively.
246 * For typical scenario, at 1word/burst, 10MB and 20MB xfers per req
247 * should be enough for P<->M and M<->M respectively.
248 */
249#define MCODE_BUFF_PER_REQ 256
250
251/* Use this _only_ to wait on transient states */
252#define UNTIL(t, s) while (!(_state(t) & (s))) cpu_relax();
253
254#ifdef PL330_DEBUG_MCGEN
255static unsigned cmd_line;
256#define PL330_DBGCMD_DUMP(off, x...) do { \
257 printk("%x:", cmd_line); \
258 printk(x); \
259 cmd_line += off; \
260 } while (0)
261#define PL330_DBGMC_START(addr) (cmd_line = addr)
262#else
263#define PL330_DBGCMD_DUMP(off, x...) do {} while (0)
264#define PL330_DBGMC_START(addr) do {} while (0)
265#endif
266
267/* The number of default descriptors */
268
269#define NR_DEFAULT_DESC 16
270
271/* Delay for runtime PM autosuspend, ms */
272#define PL330_AUTOSUSPEND_DELAY 20
273
274/* Populated by the PL330 core driver for DMA API driver's info */
275struct pl330_config {
276 u32 periph_id;
277#define DMAC_MODE_NS (1 << 0)
278 unsigned int mode;
279 unsigned int data_bus_width:10; /* In number of bits */
280 unsigned int data_buf_dep:11;
281 unsigned int num_chan:4;
282 unsigned int num_peri:6;
283 u32 peri_ns;
284 unsigned int num_events:6;
285 u32 irq_ns;
286};
287
288/*
289 * Request Configuration.
290 * The PL330 core does not modify this and uses the last
291 * working configuration if the request doesn't provide any.
292 *
293 * The Client may want to provide this info only for the
294 * first request and a request with new settings.
295 */
296struct pl330_reqcfg {
297 /* Address Incrementing */
298 unsigned dst_inc:1;
299 unsigned src_inc:1;
300
301 /*
302 * For now, the SRC & DST protection levels
303 * and burst size/length are assumed same.
304 */
305 bool nonsecure;
306 bool privileged;
307 bool insnaccess;
308 unsigned brst_len:5;
309 unsigned brst_size:3; /* in power of 2 */
310
311 enum pl330_cachectrl dcctl;
312 enum pl330_cachectrl scctl;
313 enum pl330_byteswap swap;
314 struct pl330_config *pcfg;
315};
316
317/*
318 * One cycle of DMAC operation.
319 * There may be more than one xfer in a request.
320 */
321struct pl330_xfer {
322 u32 src_addr;
323 u32 dst_addr;
324 /* Size to xfer */
325 u32 bytes;
326};
327
328/* The xfer callbacks are made with one of these arguments. */
329enum pl330_op_err {
330 /* The all xfers in the request were success. */
331 PL330_ERR_NONE,
332 /* If req aborted due to global error. */
333 PL330_ERR_ABORT,
334 /* If req failed due to problem with Channel. */
335 PL330_ERR_FAIL,
336};
337
338enum dmamov_dst {
339 SAR = 0,
340 CCR,
341 DAR,
342};
343
344enum pl330_dst {
345 SRC = 0,
346 DST,
347};
348
349enum pl330_cond {
350 SINGLE,
351 BURST,
352 ALWAYS,
353};
354
355struct dma_pl330_desc;
356
357struct _pl330_req {
358 u32 mc_bus;
359 void *mc_cpu;
360 struct dma_pl330_desc *desc;
361};
362
363/* ToBeDone for tasklet */
364struct _pl330_tbd {
365 bool reset_dmac;
366 bool reset_mngr;
367 u8 reset_chan;
368};
369
370/* A DMAC Thread */
371struct pl330_thread {
372 u8 id;
373 int ev;
374 /* If the channel is not yet acquired by any client */
375 bool free;
376 /* Parent DMAC */
377 struct pl330_dmac *dmac;
378 /* Only two at a time */
379 struct _pl330_req req[2];
380 /* Index of the last enqueued request */
381 unsigned lstenq;
382 /* Index of the last submitted request or -1 if the DMA is stopped */
383 int req_running;
384};
385
386enum pl330_dmac_state {
387 UNINIT,
388 INIT,
389 DYING,
390};
391
392enum desc_status {
393 /* In the DMAC pool */
394 FREE,
395 /*
396 * Allocated to some channel during prep_xxx
397 * Also may be sitting on the work_list.
398 */
399 PREP,
400 /*
401 * Sitting on the work_list and already submitted
402 * to the PL330 core. Not more than two descriptors
403 * of a channel can be BUSY at any time.
404 */
405 BUSY,
406 /*
407 * Sitting on the channel work_list but xfer done
408 * by PL330 core
409 */
410 DONE,
411};
412
413struct dma_pl330_chan {
414 /* Schedule desc completion */
415 struct tasklet_struct task;
416
417 /* DMA-Engine Channel */
418 struct dma_chan chan;
419
420 /* List of submitted descriptors */
421 struct list_head submitted_list;
422 /* List of issued descriptors */
423 struct list_head work_list;
424 /* List of completed descriptors */
425 struct list_head completed_list;
426
427 /* Pointer to the DMAC that manages this channel,
428 * NULL if the channel is available to be acquired.
429 * As the parent, this DMAC also provides descriptors
430 * to the channel.
431 */
432 struct pl330_dmac *dmac;
433
434 /* To protect channel manipulation */
435 spinlock_t lock;
436
437 /*
438 * Hardware channel thread of PL330 DMAC. NULL if the channel is
439 * available.
440 */
441 struct pl330_thread *thread;
442
443 /* For D-to-M and M-to-D channels */
444 int burst_sz; /* the peripheral fifo width */
445 int burst_len; /* the number of burst */
446 phys_addr_t fifo_addr;
447 /* DMA-mapped view of the FIFO; may differ if an IOMMU is present */
448 dma_addr_t fifo_dma;
449 enum dma_data_direction dir;
450 struct dma_slave_config slave_config;
451
452 /* for cyclic capability */
453 bool cyclic;
454
455 /* for runtime pm tracking */
456 bool active;
457};
458
459struct pl330_dmac {
460 /* DMA-Engine Device */
461 struct dma_device ddma;
462
463 /* Holds info about sg limitations */
464 struct device_dma_parameters dma_parms;
465
466 /* Pool of descriptors available for the DMAC's channels */
467 struct list_head desc_pool;
468 /* To protect desc_pool manipulation */
469 spinlock_t pool_lock;
470
471 /* Size of MicroCode buffers for each channel. */
472 unsigned mcbufsz;
473 /* ioremap'ed address of PL330 registers. */
474 void __iomem *base;
475 /* Populated by the PL330 core driver during pl330_add */
476 struct pl330_config pcfg;
477
478 spinlock_t lock;
479 /* Maximum possible events/irqs */
480 int events[32];
481 /* BUS address of MicroCode buffer */
482 dma_addr_t mcode_bus;
483 /* CPU address of MicroCode buffer */
484 void *mcode_cpu;
485 /* List of all Channel threads */
486 struct pl330_thread *channels;
487 /* Pointer to the MANAGER thread */
488 struct pl330_thread *manager;
489 /* To handle bad news in interrupt */
490 struct tasklet_struct tasks;
491 struct _pl330_tbd dmac_tbd;
492 /* State of DMAC operation */
493 enum pl330_dmac_state state;
494 /* Holds list of reqs with due callbacks */
495 struct list_head req_done;
496
497 /* Peripheral channels connected to this DMAC */
498 unsigned int num_peripherals;
499 struct dma_pl330_chan *peripherals; /* keep at end */
500 int quirks;
501
502 struct reset_control *rstc;
503 struct reset_control *rstc_ocp;
504};
505
506static struct pl330_of_quirks {
507 char *quirk;
508 int id;
509} of_quirks[] = {
510 {
511 .quirk = "arm,pl330-broken-no-flushp",
512 .id = PL330_QUIRK_BROKEN_NO_FLUSHP,
513 },
514 {
515 .quirk = "arm,pl330-periph-burst",
516 .id = PL330_QUIRK_PERIPH_BURST,
517 }
518};
519
520struct dma_pl330_desc {
521 /* To attach to a queue as child */
522 struct list_head node;
523
524 /* Descriptor for the DMA Engine API */
525 struct dma_async_tx_descriptor txd;
526
527 /* Xfer for PL330 core */
528 struct pl330_xfer px;
529
530 struct pl330_reqcfg rqcfg;
531
532 enum desc_status status;
533
534 int bytes_requested;
535 bool last;
536
537 /* The channel which currently holds this desc */
538 struct dma_pl330_chan *pchan;
539
540 enum dma_transfer_direction rqtype;
541 /* Index of peripheral for the xfer. */
542 unsigned peri:5;
543 /* Hook to attach to DMAC's list of reqs with due callback */
544 struct list_head rqd;
545};
546
547struct _xfer_spec {
548 u32 ccr;
549 struct dma_pl330_desc *desc;
550};
551
552static int pl330_config_write(struct dma_chan *chan,
553 struct dma_slave_config *slave_config,
554 enum dma_transfer_direction direction);
555
556static inline bool _queue_full(struct pl330_thread *thrd)
557{
558 return thrd->req[0].desc != NULL && thrd->req[1].desc != NULL;
559}
560
561static inline bool is_manager(struct pl330_thread *thrd)
562{
563 return thrd->dmac->manager == thrd;
564}
565
566/* If manager of the thread is in Non-Secure mode */
567static inline bool _manager_ns(struct pl330_thread *thrd)
568{
569 return (thrd->dmac->pcfg.mode & DMAC_MODE_NS) ? true : false;
570}
571
572static inline u32 get_revision(u32 periph_id)
573{
574 return (periph_id >> PERIPH_REV_SHIFT) & PERIPH_REV_MASK;
575}
576
577static inline u32 _emit_END(unsigned dry_run, u8 buf[])
578{
579 if (dry_run)
580 return SZ_DMAEND;
581
582 buf[0] = CMD_DMAEND;
583
584 PL330_DBGCMD_DUMP(SZ_DMAEND, "\tDMAEND\n");
585
586 return SZ_DMAEND;
587}
588
589static inline u32 _emit_FLUSHP(unsigned dry_run, u8 buf[], u8 peri)
590{
591 if (dry_run)
592 return SZ_DMAFLUSHP;
593
594 buf[0] = CMD_DMAFLUSHP;
595
596 peri &= 0x1f;
597 peri <<= 3;
598 buf[1] = peri;
599
600 PL330_DBGCMD_DUMP(SZ_DMAFLUSHP, "\tDMAFLUSHP %u\n", peri >> 3);
601
602 return SZ_DMAFLUSHP;
603}
604
605static inline u32 _emit_LD(unsigned dry_run, u8 buf[], enum pl330_cond cond)
606{
607 if (dry_run)
608 return SZ_DMALD;
609
610 buf[0] = CMD_DMALD;
611
612 if (cond == SINGLE)
613 buf[0] |= (0 << 1) | (1 << 0);
614 else if (cond == BURST)
615 buf[0] |= (1 << 1) | (1 << 0);
616
617 PL330_DBGCMD_DUMP(SZ_DMALD, "\tDMALD%c\n",
618 cond == SINGLE ? 'S' : (cond == BURST ? 'B' : 'A'));
619
620 return SZ_DMALD;
621}
622
623static inline u32 _emit_LDP(unsigned dry_run, u8 buf[],
624 enum pl330_cond cond, u8 peri)
625{
626 if (dry_run)
627 return SZ_DMALDP;
628
629 buf[0] = CMD_DMALDP;
630
631 if (cond == BURST)
632 buf[0] |= (1 << 1);
633
634 peri &= 0x1f;
635 peri <<= 3;
636 buf[1] = peri;
637
638 PL330_DBGCMD_DUMP(SZ_DMALDP, "\tDMALDP%c %u\n",
639 cond == SINGLE ? 'S' : 'B', peri >> 3);
640
641 return SZ_DMALDP;
642}
643
644static inline u32 _emit_LP(unsigned dry_run, u8 buf[],
645 unsigned loop, u8 cnt)
646{
647 if (dry_run)
648 return SZ_DMALP;
649
650 buf[0] = CMD_DMALP;
651
652 if (loop)
653 buf[0] |= (1 << 1);
654
655 cnt--; /* DMAC increments by 1 internally */
656 buf[1] = cnt;
657
658 PL330_DBGCMD_DUMP(SZ_DMALP, "\tDMALP_%c %u\n", loop ? '1' : '0', cnt);
659
660 return SZ_DMALP;
661}
662
663struct _arg_LPEND {
664 enum pl330_cond cond;
665 bool forever;
666 unsigned loop;
667 u8 bjump;
668};
669
670static inline u32 _emit_LPEND(unsigned dry_run, u8 buf[],
671 const struct _arg_LPEND *arg)
672{
673 enum pl330_cond cond = arg->cond;
674 bool forever = arg->forever;
675 unsigned loop = arg->loop;
676 u8 bjump = arg->bjump;
677
678 if (dry_run)
679 return SZ_DMALPEND;
680
681 buf[0] = CMD_DMALPEND;
682
683 if (loop)
684 buf[0] |= (1 << 2);
685
686 if (!forever)
687 buf[0] |= (1 << 4);
688
689 if (cond == SINGLE)
690 buf[0] |= (0 << 1) | (1 << 0);
691 else if (cond == BURST)
692 buf[0] |= (1 << 1) | (1 << 0);
693
694 buf[1] = bjump;
695
696 PL330_DBGCMD_DUMP(SZ_DMALPEND, "\tDMALP%s%c_%c bjmpto_%x\n",
697 forever ? "FE" : "END",
698 cond == SINGLE ? 'S' : (cond == BURST ? 'B' : 'A'),
699 loop ? '1' : '0',
700 bjump);
701
702 return SZ_DMALPEND;
703}
704
705static inline u32 _emit_KILL(unsigned dry_run, u8 buf[])
706{
707 if (dry_run)
708 return SZ_DMAKILL;
709
710 buf[0] = CMD_DMAKILL;
711
712 return SZ_DMAKILL;
713}
714
715static inline u32 _emit_MOV(unsigned dry_run, u8 buf[],
716 enum dmamov_dst dst, u32 val)
717{
718 if (dry_run)
719 return SZ_DMAMOV;
720
721 buf[0] = CMD_DMAMOV;
722 buf[1] = dst;
723 buf[2] = val;
724 buf[3] = val >> 8;
725 buf[4] = val >> 16;
726 buf[5] = val >> 24;
727
728 PL330_DBGCMD_DUMP(SZ_DMAMOV, "\tDMAMOV %s 0x%x\n",
729 dst == SAR ? "SAR" : (dst == DAR ? "DAR" : "CCR"), val);
730
731 return SZ_DMAMOV;
732}
733
734static inline u32 _emit_RMB(unsigned dry_run, u8 buf[])
735{
736 if (dry_run)
737 return SZ_DMARMB;
738
739 buf[0] = CMD_DMARMB;
740
741 PL330_DBGCMD_DUMP(SZ_DMARMB, "\tDMARMB\n");
742
743 return SZ_DMARMB;
744}
745
746static inline u32 _emit_SEV(unsigned dry_run, u8 buf[], u8 ev)
747{
748 if (dry_run)
749 return SZ_DMASEV;
750
751 buf[0] = CMD_DMASEV;
752
753 ev &= 0x1f;
754 ev <<= 3;
755 buf[1] = ev;
756
757 PL330_DBGCMD_DUMP(SZ_DMASEV, "\tDMASEV %u\n", ev >> 3);
758
759 return SZ_DMASEV;
760}
761
762static inline u32 _emit_ST(unsigned dry_run, u8 buf[], enum pl330_cond cond)
763{
764 if (dry_run)
765 return SZ_DMAST;
766
767 buf[0] = CMD_DMAST;
768
769 if (cond == SINGLE)
770 buf[0] |= (0 << 1) | (1 << 0);
771 else if (cond == BURST)
772 buf[0] |= (1 << 1) | (1 << 0);
773
774 PL330_DBGCMD_DUMP(SZ_DMAST, "\tDMAST%c\n",
775 cond == SINGLE ? 'S' : (cond == BURST ? 'B' : 'A'));
776
777 return SZ_DMAST;
778}
779
780static inline u32 _emit_STP(unsigned dry_run, u8 buf[],
781 enum pl330_cond cond, u8 peri)
782{
783 if (dry_run)
784 return SZ_DMASTP;
785
786 buf[0] = CMD_DMASTP;
787
788 if (cond == BURST)
789 buf[0] |= (1 << 1);
790
791 peri &= 0x1f;
792 peri <<= 3;
793 buf[1] = peri;
794
795 PL330_DBGCMD_DUMP(SZ_DMASTP, "\tDMASTP%c %u\n",
796 cond == SINGLE ? 'S' : 'B', peri >> 3);
797
798 return SZ_DMASTP;
799}
800
801static inline u32 _emit_WFP(unsigned dry_run, u8 buf[],
802 enum pl330_cond cond, u8 peri)
803{
804 if (dry_run)
805 return SZ_DMAWFP;
806
807 buf[0] = CMD_DMAWFP;
808
809 if (cond == SINGLE)
810 buf[0] |= (0 << 1) | (0 << 0);
811 else if (cond == BURST)
812 buf[0] |= (1 << 1) | (0 << 0);
813 else
814 buf[0] |= (0 << 1) | (1 << 0);
815
816 peri &= 0x1f;
817 peri <<= 3;
818 buf[1] = peri;
819
820 PL330_DBGCMD_DUMP(SZ_DMAWFP, "\tDMAWFP%c %u\n",
821 cond == SINGLE ? 'S' : (cond == BURST ? 'B' : 'P'), peri >> 3);
822
823 return SZ_DMAWFP;
824}
825
826static inline u32 _emit_WMB(unsigned dry_run, u8 buf[])
827{
828 if (dry_run)
829 return SZ_DMAWMB;
830
831 buf[0] = CMD_DMAWMB;
832
833 PL330_DBGCMD_DUMP(SZ_DMAWMB, "\tDMAWMB\n");
834
835 return SZ_DMAWMB;
836}
837
838struct _arg_GO {
839 u8 chan;
840 u32 addr;
841 unsigned ns;
842};
843
844static inline u32 _emit_GO(unsigned dry_run, u8 buf[],
845 const struct _arg_GO *arg)
846{
847 u8 chan = arg->chan;
848 u32 addr = arg->addr;
849 unsigned ns = arg->ns;
850
851 if (dry_run)
852 return SZ_DMAGO;
853
854 buf[0] = CMD_DMAGO;
855 buf[0] |= (ns << 1);
856 buf[1] = chan & 0x7;
857 buf[2] = addr;
858 buf[3] = addr >> 8;
859 buf[4] = addr >> 16;
860 buf[5] = addr >> 24;
861
862 return SZ_DMAGO;
863}
864
865#define msecs_to_loops(t) (loops_per_jiffy / 1000 * HZ * t)
866
867/* Returns Time-Out */
868static bool _until_dmac_idle(struct pl330_thread *thrd)
869{
870 void __iomem *regs = thrd->dmac->base;
871 unsigned long loops = msecs_to_loops(5);
872
873 do {
874 /* Until Manager is Idle */
875 if (!(readl(regs + DBGSTATUS) & DBG_BUSY))
876 break;
877
878 cpu_relax();
879 } while (--loops);
880
881 if (!loops)
882 return true;
883
884 return false;
885}
886
887static inline void _execute_DBGINSN(struct pl330_thread *thrd,
888 u8 insn[], bool as_manager)
889{
890 void __iomem *regs = thrd->dmac->base;
891 u32 val;
892
893 /* If timed out due to halted state-machine */
894 if (_until_dmac_idle(thrd)) {
895 dev_err(thrd->dmac->ddma.dev, "DMAC halted!\n");
896 return;
897 }
898
899 val = (insn[0] << 16) | (insn[1] << 24);
900 if (!as_manager) {
901 val |= (1 << 0);
902 val |= (thrd->id << 8); /* Channel Number */
903 }
904 writel(val, regs + DBGINST0);
905
906 val = le32_to_cpu(*((__le32 *)&insn[2]));
907 writel(val, regs + DBGINST1);
908
909 /* Get going */
910 writel(0, regs + DBGCMD);
911}
912
913static inline u32 _state(struct pl330_thread *thrd)
914{
915 void __iomem *regs = thrd->dmac->base;
916 u32 val;
917
918 if (is_manager(thrd))
919 val = readl(regs + DS) & 0xf;
920 else
921 val = readl(regs + CS(thrd->id)) & 0xf;
922
923 switch (val) {
924 case DS_ST_STOP:
925 return PL330_STATE_STOPPED;
926 case DS_ST_EXEC:
927 return PL330_STATE_EXECUTING;
928 case DS_ST_CMISS:
929 return PL330_STATE_CACHEMISS;
930 case DS_ST_UPDTPC:
931 return PL330_STATE_UPDTPC;
932 case DS_ST_WFE:
933 return PL330_STATE_WFE;
934 case DS_ST_FAULT:
935 return PL330_STATE_FAULTING;
936 case DS_ST_ATBRR:
937 if (is_manager(thrd))
938 return PL330_STATE_INVALID;
939 else
940 return PL330_STATE_ATBARRIER;
941 case DS_ST_QBUSY:
942 if (is_manager(thrd))
943 return PL330_STATE_INVALID;
944 else
945 return PL330_STATE_QUEUEBUSY;
946 case DS_ST_WFP:
947 if (is_manager(thrd))
948 return PL330_STATE_INVALID;
949 else
950 return PL330_STATE_WFP;
951 case DS_ST_KILL:
952 if (is_manager(thrd))
953 return PL330_STATE_INVALID;
954 else
955 return PL330_STATE_KILLING;
956 case DS_ST_CMPLT:
957 if (is_manager(thrd))
958 return PL330_STATE_INVALID;
959 else
960 return PL330_STATE_COMPLETING;
961 case DS_ST_FLTCMP:
962 if (is_manager(thrd))
963 return PL330_STATE_INVALID;
964 else
965 return PL330_STATE_FAULT_COMPLETING;
966 default:
967 return PL330_STATE_INVALID;
968 }
969}
970
971static void _stop(struct pl330_thread *thrd)
972{
973 void __iomem *regs = thrd->dmac->base;
974 u8 insn[6] = {0, 0, 0, 0, 0, 0};
975 u32 inten = readl(regs + INTEN);
976
977 if (_state(thrd) == PL330_STATE_FAULT_COMPLETING)
978 UNTIL(thrd, PL330_STATE_FAULTING | PL330_STATE_KILLING);
979
980 /* Return if nothing needs to be done */
981 if (_state(thrd) == PL330_STATE_COMPLETING
982 || _state(thrd) == PL330_STATE_KILLING
983 || _state(thrd) == PL330_STATE_STOPPED)
984 return;
985
986 _emit_KILL(0, insn);
987
988 _execute_DBGINSN(thrd, insn, is_manager(thrd));
989
990 /* clear the event */
991 if (inten & (1 << thrd->ev))
992 writel(1 << thrd->ev, regs + INTCLR);
993 /* Stop generating interrupts for SEV */
994 writel(inten & ~(1 << thrd->ev), regs + INTEN);
995}
996
997/* Start doing req 'idx' of thread 'thrd' */
998static bool _trigger(struct pl330_thread *thrd)
999{
1000 void __iomem *regs = thrd->dmac->base;
1001 struct _pl330_req *req;
1002 struct dma_pl330_desc *desc;
1003 struct _arg_GO go;
1004 unsigned ns;
1005 u8 insn[6] = {0, 0, 0, 0, 0, 0};
1006 int idx;
1007
1008 /* Return if already ACTIVE */
1009 if (_state(thrd) != PL330_STATE_STOPPED)
1010 return true;
1011
1012 idx = 1 - thrd->lstenq;
1013 if (thrd->req[idx].desc != NULL) {
1014 req = &thrd->req[idx];
1015 } else {
1016 idx = thrd->lstenq;
1017 if (thrd->req[idx].desc != NULL)
1018 req = &thrd->req[idx];
1019 else
1020 req = NULL;
1021 }
1022
1023 /* Return if no request */
1024 if (!req)
1025 return true;
1026
1027 /* Return if req is running */
1028 if (idx == thrd->req_running)
1029 return true;
1030
1031 desc = req->desc;
1032
1033 ns = desc->rqcfg.nonsecure ? 1 : 0;
1034
1035 /* See 'Abort Sources' point-4 at Page 2-25 */
1036 if (_manager_ns(thrd) && !ns)
1037 dev_info(thrd->dmac->ddma.dev, "%s:%d Recipe for ABORT!\n",
1038 __func__, __LINE__);
1039
1040 go.chan = thrd->id;
1041 go.addr = req->mc_bus;
1042 go.ns = ns;
1043 _emit_GO(0, insn, &go);
1044
1045 /* Set to generate interrupts for SEV */
1046 writel(readl(regs + INTEN) | (1 << thrd->ev), regs + INTEN);
1047
1048 /* Only manager can execute GO */
1049 _execute_DBGINSN(thrd, insn, true);
1050
1051 thrd->req_running = idx;
1052
1053 return true;
1054}
1055
1056static bool _start(struct pl330_thread *thrd)
1057{
1058 switch (_state(thrd)) {
1059 case PL330_STATE_FAULT_COMPLETING:
1060 UNTIL(thrd, PL330_STATE_FAULTING | PL330_STATE_KILLING);
1061
1062 if (_state(thrd) == PL330_STATE_KILLING)
1063 UNTIL(thrd, PL330_STATE_STOPPED)
1064 fallthrough;
1065
1066 case PL330_STATE_FAULTING:
1067 _stop(thrd);
1068 fallthrough;
1069
1070 case PL330_STATE_KILLING:
1071 case PL330_STATE_COMPLETING:
1072 UNTIL(thrd, PL330_STATE_STOPPED)
1073 fallthrough;
1074
1075 case PL330_STATE_STOPPED:
1076 return _trigger(thrd);
1077
1078 case PL330_STATE_WFP:
1079 case PL330_STATE_QUEUEBUSY:
1080 case PL330_STATE_ATBARRIER:
1081 case PL330_STATE_UPDTPC:
1082 case PL330_STATE_CACHEMISS:
1083 case PL330_STATE_EXECUTING:
1084 return true;
1085
1086 case PL330_STATE_WFE: /* For RESUME, nothing yet */
1087 default:
1088 return false;
1089 }
1090}
1091
1092static inline int _ldst_memtomem(unsigned dry_run, u8 buf[],
1093 const struct _xfer_spec *pxs, int cyc)
1094{
1095 int off = 0;
1096 struct pl330_config *pcfg = pxs->desc->rqcfg.pcfg;
1097
1098 /* check lock-up free version */
1099 if (get_revision(pcfg->periph_id) >= PERIPH_REV_R1P0) {
1100 while (cyc--) {
1101 off += _emit_LD(dry_run, &buf[off], ALWAYS);
1102 off += _emit_ST(dry_run, &buf[off], ALWAYS);
1103 }
1104 } else {
1105 while (cyc--) {
1106 off += _emit_LD(dry_run, &buf[off], ALWAYS);
1107 off += _emit_RMB(dry_run, &buf[off]);
1108 off += _emit_ST(dry_run, &buf[off], ALWAYS);
1109 off += _emit_WMB(dry_run, &buf[off]);
1110 }
1111 }
1112
1113 return off;
1114}
1115
1116static u32 _emit_load(unsigned int dry_run, u8 buf[],
1117 enum pl330_cond cond, enum dma_transfer_direction direction,
1118 u8 peri)
1119{
1120 int off = 0;
1121
1122 switch (direction) {
1123 case DMA_MEM_TO_MEM:
1124 case DMA_MEM_TO_DEV:
1125 off += _emit_LD(dry_run, &buf[off], cond);
1126 break;
1127
1128 case DMA_DEV_TO_MEM:
1129 if (cond == ALWAYS) {
1130 off += _emit_LDP(dry_run, &buf[off], SINGLE,
1131 peri);
1132 off += _emit_LDP(dry_run, &buf[off], BURST,
1133 peri);
1134 } else {
1135 off += _emit_LDP(dry_run, &buf[off], cond,
1136 peri);
1137 }
1138 break;
1139
1140 default:
1141 /* this code should be unreachable */
1142 WARN_ON(1);
1143 break;
1144 }
1145
1146 return off;
1147}
1148
1149static inline u32 _emit_store(unsigned int dry_run, u8 buf[],
1150 enum pl330_cond cond, enum dma_transfer_direction direction,
1151 u8 peri)
1152{
1153 int off = 0;
1154
1155 switch (direction) {
1156 case DMA_MEM_TO_MEM:
1157 case DMA_DEV_TO_MEM:
1158 off += _emit_ST(dry_run, &buf[off], cond);
1159 break;
1160
1161 case DMA_MEM_TO_DEV:
1162 if (cond == ALWAYS) {
1163 off += _emit_STP(dry_run, &buf[off], SINGLE,
1164 peri);
1165 off += _emit_STP(dry_run, &buf[off], BURST,
1166 peri);
1167 } else {
1168 off += _emit_STP(dry_run, &buf[off], cond,
1169 peri);
1170 }
1171 break;
1172
1173 default:
1174 /* this code should be unreachable */
1175 WARN_ON(1);
1176 break;
1177 }
1178
1179 return off;
1180}
1181
1182static inline int _ldst_peripheral(struct pl330_dmac *pl330,
1183 unsigned dry_run, u8 buf[],
1184 const struct _xfer_spec *pxs, int cyc,
1185 enum pl330_cond cond)
1186{
1187 int off = 0;
1188
1189 /*
1190 * do FLUSHP at beginning to clear any stale dma requests before the
1191 * first WFP.
1192 */
1193 if (!(pl330->quirks & PL330_QUIRK_BROKEN_NO_FLUSHP))
1194 off += _emit_FLUSHP(dry_run, &buf[off], pxs->desc->peri);
1195 while (cyc--) {
1196 off += _emit_WFP(dry_run, &buf[off], cond, pxs->desc->peri);
1197 off += _emit_load(dry_run, &buf[off], cond, pxs->desc->rqtype,
1198 pxs->desc->peri);
1199 off += _emit_store(dry_run, &buf[off], cond, pxs->desc->rqtype,
1200 pxs->desc->peri);
1201 }
1202
1203 return off;
1204}
1205
1206static int _bursts(struct pl330_dmac *pl330, unsigned dry_run, u8 buf[],
1207 const struct _xfer_spec *pxs, int cyc)
1208{
1209 int off = 0;
1210 enum pl330_cond cond = BRST_LEN(pxs->ccr) > 1 ? BURST : SINGLE;
1211
1212 if (pl330->quirks & PL330_QUIRK_PERIPH_BURST)
1213 cond = BURST;
1214
1215 switch (pxs->desc->rqtype) {
1216 case DMA_MEM_TO_DEV:
1217 case DMA_DEV_TO_MEM:
1218 off += _ldst_peripheral(pl330, dry_run, &buf[off], pxs, cyc,
1219 cond);
1220 break;
1221
1222 case DMA_MEM_TO_MEM:
1223 off += _ldst_memtomem(dry_run, &buf[off], pxs, cyc);
1224 break;
1225
1226 default:
1227 /* this code should be unreachable */
1228 WARN_ON(1);
1229 break;
1230 }
1231
1232 return off;
1233}
1234
1235/*
1236 * only the unaligned burst transfers have the dregs.
1237 * so, still transfer dregs with a reduced size burst
1238 * for mem-to-mem, mem-to-dev or dev-to-mem.
1239 */
1240static int _dregs(struct pl330_dmac *pl330, unsigned int dry_run, u8 buf[],
1241 const struct _xfer_spec *pxs, int transfer_length)
1242{
1243 int off = 0;
1244 int dregs_ccr;
1245
1246 if (transfer_length == 0)
1247 return off;
1248
1249 /*
1250 * dregs_len = (total bytes - BURST_TO_BYTE(bursts, ccr)) /
1251 * BRST_SIZE(ccr)
1252 * the dregs len must be smaller than burst len,
1253 * so, for higher efficiency, we can modify CCR
1254 * to use a reduced size burst len for the dregs.
1255 */
1256 dregs_ccr = pxs->ccr;
1257 dregs_ccr &= ~((0xf << CC_SRCBRSTLEN_SHFT) |
1258 (0xf << CC_DSTBRSTLEN_SHFT));
1259 dregs_ccr |= (((transfer_length - 1) & 0xf) <<
1260 CC_SRCBRSTLEN_SHFT);
1261 dregs_ccr |= (((transfer_length - 1) & 0xf) <<
1262 CC_DSTBRSTLEN_SHFT);
1263
1264 switch (pxs->desc->rqtype) {
1265 case DMA_MEM_TO_DEV:
1266 case DMA_DEV_TO_MEM:
1267 off += _emit_MOV(dry_run, &buf[off], CCR, dregs_ccr);
1268 off += _ldst_peripheral(pl330, dry_run, &buf[off], pxs, 1,
1269 BURST);
1270 break;
1271
1272 case DMA_MEM_TO_MEM:
1273 off += _emit_MOV(dry_run, &buf[off], CCR, dregs_ccr);
1274 off += _ldst_memtomem(dry_run, &buf[off], pxs, 1);
1275 break;
1276
1277 default:
1278 /* this code should be unreachable */
1279 WARN_ON(1);
1280 break;
1281 }
1282
1283 return off;
1284}
1285
1286/* Returns bytes consumed and updates bursts */
1287static inline int _loop(struct pl330_dmac *pl330, unsigned dry_run, u8 buf[],
1288 unsigned long *bursts, const struct _xfer_spec *pxs)
1289{
1290 int cyc, cycmax, szlp, szlpend, szbrst, off;
1291 unsigned lcnt0, lcnt1, ljmp0, ljmp1;
1292 struct _arg_LPEND lpend;
1293
1294 if (*bursts == 1)
1295 return _bursts(pl330, dry_run, buf, pxs, 1);
1296
1297 /* Max iterations possible in DMALP is 256 */
1298 if (*bursts >= 256*256) {
1299 lcnt1 = 256;
1300 lcnt0 = 256;
1301 cyc = *bursts / lcnt1 / lcnt0;
1302 } else if (*bursts > 256) {
1303 lcnt1 = 256;
1304 lcnt0 = *bursts / lcnt1;
1305 cyc = 1;
1306 } else {
1307 lcnt1 = *bursts;
1308 lcnt0 = 0;
1309 cyc = 1;
1310 }
1311
1312 szlp = _emit_LP(1, buf, 0, 0);
1313 szbrst = _bursts(pl330, 1, buf, pxs, 1);
1314
1315 lpend.cond = ALWAYS;
1316 lpend.forever = false;
1317 lpend.loop = 0;
1318 lpend.bjump = 0;
1319 szlpend = _emit_LPEND(1, buf, &lpend);
1320
1321 if (lcnt0) {
1322 szlp *= 2;
1323 szlpend *= 2;
1324 }
1325
1326 /*
1327 * Max bursts that we can unroll due to limit on the
1328 * size of backward jump that can be encoded in DMALPEND
1329 * which is 8-bits and hence 255
1330 */
1331 cycmax = (255 - (szlp + szlpend)) / szbrst;
1332
1333 cyc = (cycmax < cyc) ? cycmax : cyc;
1334
1335 off = 0;
1336
1337 if (lcnt0) {
1338 off += _emit_LP(dry_run, &buf[off], 0, lcnt0);
1339 ljmp0 = off;
1340 }
1341
1342 off += _emit_LP(dry_run, &buf[off], 1, lcnt1);
1343 ljmp1 = off;
1344
1345 off += _bursts(pl330, dry_run, &buf[off], pxs, cyc);
1346
1347 lpend.cond = ALWAYS;
1348 lpend.forever = false;
1349 lpend.loop = 1;
1350 lpend.bjump = off - ljmp1;
1351 off += _emit_LPEND(dry_run, &buf[off], &lpend);
1352
1353 if (lcnt0) {
1354 lpend.cond = ALWAYS;
1355 lpend.forever = false;
1356 lpend.loop = 0;
1357 lpend.bjump = off - ljmp0;
1358 off += _emit_LPEND(dry_run, &buf[off], &lpend);
1359 }
1360
1361 *bursts = lcnt1 * cyc;
1362 if (lcnt0)
1363 *bursts *= lcnt0;
1364
1365 return off;
1366}
1367
1368static inline int _setup_loops(struct pl330_dmac *pl330,
1369 unsigned dry_run, u8 buf[],
1370 const struct _xfer_spec *pxs)
1371{
1372 struct pl330_xfer *x = &pxs->desc->px;
1373 u32 ccr = pxs->ccr;
1374 unsigned long c, bursts = BYTE_TO_BURST(x->bytes, ccr);
1375 int num_dregs = (x->bytes - BURST_TO_BYTE(bursts, ccr)) /
1376 BRST_SIZE(ccr);
1377 int off = 0;
1378
1379 while (bursts) {
1380 c = bursts;
1381 off += _loop(pl330, dry_run, &buf[off], &c, pxs);
1382 bursts -= c;
1383 }
1384 off += _dregs(pl330, dry_run, &buf[off], pxs, num_dregs);
1385
1386 return off;
1387}
1388
1389static inline int _setup_xfer(struct pl330_dmac *pl330,
1390 unsigned dry_run, u8 buf[],
1391 const struct _xfer_spec *pxs)
1392{
1393 struct pl330_xfer *x = &pxs->desc->px;
1394 int off = 0;
1395
1396 /* DMAMOV SAR, x->src_addr */
1397 off += _emit_MOV(dry_run, &buf[off], SAR, x->src_addr);
1398 /* DMAMOV DAR, x->dst_addr */
1399 off += _emit_MOV(dry_run, &buf[off], DAR, x->dst_addr);
1400
1401 /* Setup Loop(s) */
1402 off += _setup_loops(pl330, dry_run, &buf[off], pxs);
1403
1404 return off;
1405}
1406
1407/*
1408 * A req is a sequence of one or more xfer units.
1409 * Returns the number of bytes taken to setup the MC for the req.
1410 */
1411static int _setup_req(struct pl330_dmac *pl330, unsigned dry_run,
1412 struct pl330_thread *thrd, unsigned index,
1413 struct _xfer_spec *pxs)
1414{
1415 struct _pl330_req *req = &thrd->req[index];
1416 u8 *buf = req->mc_cpu;
1417 int off = 0;
1418
1419 PL330_DBGMC_START(req->mc_bus);
1420
1421 /* DMAMOV CCR, ccr */
1422 off += _emit_MOV(dry_run, &buf[off], CCR, pxs->ccr);
1423
1424 off += _setup_xfer(pl330, dry_run, &buf[off], pxs);
1425
1426 /* DMASEV peripheral/event */
1427 off += _emit_SEV(dry_run, &buf[off], thrd->ev);
1428 /* DMAEND */
1429 off += _emit_END(dry_run, &buf[off]);
1430
1431 return off;
1432}
1433
1434static inline u32 _prepare_ccr(const struct pl330_reqcfg *rqc)
1435{
1436 u32 ccr = 0;
1437
1438 if (rqc->src_inc)
1439 ccr |= CC_SRCINC;
1440
1441 if (rqc->dst_inc)
1442 ccr |= CC_DSTINC;
1443
1444 /* We set same protection levels for Src and DST for now */
1445 if (rqc->privileged)
1446 ccr |= CC_SRCPRI | CC_DSTPRI;
1447 if (rqc->nonsecure)
1448 ccr |= CC_SRCNS | CC_DSTNS;
1449 if (rqc->insnaccess)
1450 ccr |= CC_SRCIA | CC_DSTIA;
1451
1452 ccr |= (((rqc->brst_len - 1) & 0xf) << CC_SRCBRSTLEN_SHFT);
1453 ccr |= (((rqc->brst_len - 1) & 0xf) << CC_DSTBRSTLEN_SHFT);
1454
1455 ccr |= (rqc->brst_size << CC_SRCBRSTSIZE_SHFT);
1456 ccr |= (rqc->brst_size << CC_DSTBRSTSIZE_SHFT);
1457
1458 ccr |= (rqc->scctl << CC_SRCCCTRL_SHFT);
1459 ccr |= (rqc->dcctl << CC_DSTCCTRL_SHFT);
1460
1461 ccr |= (rqc->swap << CC_SWAP_SHFT);
1462
1463 return ccr;
1464}
1465
1466/*
1467 * Submit a list of xfers after which the client wants notification.
1468 * Client is not notified after each xfer unit, just once after all
1469 * xfer units are done or some error occurs.
1470 */
1471static int pl330_submit_req(struct pl330_thread *thrd,
1472 struct dma_pl330_desc *desc)
1473{
1474 struct pl330_dmac *pl330 = thrd->dmac;
1475 struct _xfer_spec xs;
1476 unsigned long flags;
1477 unsigned idx;
1478 u32 ccr;
1479 int ret = 0;
1480
1481 switch (desc->rqtype) {
1482 case DMA_MEM_TO_DEV:
1483 break;
1484
1485 case DMA_DEV_TO_MEM:
1486 break;
1487
1488 case DMA_MEM_TO_MEM:
1489 break;
1490
1491 default:
1492 return -ENOTSUPP;
1493 }
1494
1495 if (pl330->state == DYING
1496 || pl330->dmac_tbd.reset_chan & (1 << thrd->id)) {
1497 dev_info(thrd->dmac->ddma.dev, "%s:%d\n",
1498 __func__, __LINE__);
1499 return -EAGAIN;
1500 }
1501
1502 /* If request for non-existing peripheral */
1503 if (desc->rqtype != DMA_MEM_TO_MEM &&
1504 desc->peri >= pl330->pcfg.num_peri) {
1505 dev_info(thrd->dmac->ddma.dev,
1506 "%s:%d Invalid peripheral(%u)!\n",
1507 __func__, __LINE__, desc->peri);
1508 return -EINVAL;
1509 }
1510
1511 spin_lock_irqsave(&pl330->lock, flags);
1512
1513 if (_queue_full(thrd)) {
1514 ret = -EAGAIN;
1515 goto xfer_exit;
1516 }
1517
1518 /* Prefer Secure Channel */
1519 if (!_manager_ns(thrd))
1520 desc->rqcfg.nonsecure = 0;
1521 else
1522 desc->rqcfg.nonsecure = 1;
1523
1524 ccr = _prepare_ccr(&desc->rqcfg);
1525
1526 idx = thrd->req[0].desc == NULL ? 0 : 1;
1527
1528 xs.ccr = ccr;
1529 xs.desc = desc;
1530
1531 /* First dry run to check if req is acceptable */
1532 ret = _setup_req(pl330, 1, thrd, idx, &xs);
1533 if (ret < 0)
1534 goto xfer_exit;
1535
1536 if (ret > pl330->mcbufsz / 2) {
1537 dev_info(pl330->ddma.dev, "%s:%d Try increasing mcbufsz (%i/%i)\n",
1538 __func__, __LINE__, ret, pl330->mcbufsz / 2);
1539 ret = -ENOMEM;
1540 goto xfer_exit;
1541 }
1542
1543 /* Hook the request */
1544 thrd->lstenq = idx;
1545 thrd->req[idx].desc = desc;
1546 _setup_req(pl330, 0, thrd, idx, &xs);
1547
1548 ret = 0;
1549
1550xfer_exit:
1551 spin_unlock_irqrestore(&pl330->lock, flags);
1552
1553 return ret;
1554}
1555
1556static void dma_pl330_rqcb(struct dma_pl330_desc *desc, enum pl330_op_err err)
1557{
1558 struct dma_pl330_chan *pch;
1559 unsigned long flags;
1560
1561 if (!desc)
1562 return;
1563
1564 pch = desc->pchan;
1565
1566 /* If desc aborted */
1567 if (!pch)
1568 return;
1569
1570 spin_lock_irqsave(&pch->lock, flags);
1571
1572 desc->status = DONE;
1573
1574 spin_unlock_irqrestore(&pch->lock, flags);
1575
1576 tasklet_schedule(&pch->task);
1577}
1578
1579static void pl330_dotask(unsigned long data)
1580{
1581 struct pl330_dmac *pl330 = (struct pl330_dmac *) data;
1582 unsigned long flags;
1583 int i;
1584
1585 spin_lock_irqsave(&pl330->lock, flags);
1586
1587 /* The DMAC itself gone nuts */
1588 if (pl330->dmac_tbd.reset_dmac) {
1589 pl330->state = DYING;
1590 /* Reset the manager too */
1591 pl330->dmac_tbd.reset_mngr = true;
1592 /* Clear the reset flag */
1593 pl330->dmac_tbd.reset_dmac = false;
1594 }
1595
1596 if (pl330->dmac_tbd.reset_mngr) {
1597 _stop(pl330->manager);
1598 /* Reset all channels */
1599 pl330->dmac_tbd.reset_chan = (1 << pl330->pcfg.num_chan) - 1;
1600 /* Clear the reset flag */
1601 pl330->dmac_tbd.reset_mngr = false;
1602 }
1603
1604 for (i = 0; i < pl330->pcfg.num_chan; i++) {
1605
1606 if (pl330->dmac_tbd.reset_chan & (1 << i)) {
1607 struct pl330_thread *thrd = &pl330->channels[i];
1608 void __iomem *regs = pl330->base;
1609 enum pl330_op_err err;
1610
1611 _stop(thrd);
1612
1613 if (readl(regs + FSC) & (1 << thrd->id))
1614 err = PL330_ERR_FAIL;
1615 else
1616 err = PL330_ERR_ABORT;
1617
1618 spin_unlock_irqrestore(&pl330->lock, flags);
1619 dma_pl330_rqcb(thrd->req[1 - thrd->lstenq].desc, err);
1620 dma_pl330_rqcb(thrd->req[thrd->lstenq].desc, err);
1621 spin_lock_irqsave(&pl330->lock, flags);
1622
1623 thrd->req[0].desc = NULL;
1624 thrd->req[1].desc = NULL;
1625 thrd->req_running = -1;
1626
1627 /* Clear the reset flag */
1628 pl330->dmac_tbd.reset_chan &= ~(1 << i);
1629 }
1630 }
1631
1632 spin_unlock_irqrestore(&pl330->lock, flags);
1633
1634 return;
1635}
1636
1637/* Returns 1 if state was updated, 0 otherwise */
1638static int pl330_update(struct pl330_dmac *pl330)
1639{
1640 struct dma_pl330_desc *descdone;
1641 unsigned long flags;
1642 void __iomem *regs;
1643 u32 val;
1644 int id, ev, ret = 0;
1645
1646 regs = pl330->base;
1647
1648 spin_lock_irqsave(&pl330->lock, flags);
1649
1650 val = readl(regs + FSM) & 0x1;
1651 if (val)
1652 pl330->dmac_tbd.reset_mngr = true;
1653 else
1654 pl330->dmac_tbd.reset_mngr = false;
1655
1656 val = readl(regs + FSC) & ((1 << pl330->pcfg.num_chan) - 1);
1657 pl330->dmac_tbd.reset_chan |= val;
1658 if (val) {
1659 int i = 0;
1660 while (i < pl330->pcfg.num_chan) {
1661 if (val & (1 << i)) {
1662 dev_info(pl330->ddma.dev,
1663 "Reset Channel-%d\t CS-%x FTC-%x\n",
1664 i, readl(regs + CS(i)),
1665 readl(regs + FTC(i)));
1666 _stop(&pl330->channels[i]);
1667 }
1668 i++;
1669 }
1670 }
1671
1672 /* Check which event happened i.e, thread notified */
1673 val = readl(regs + ES);
1674 if (pl330->pcfg.num_events < 32
1675 && val & ~((1 << pl330->pcfg.num_events) - 1)) {
1676 pl330->dmac_tbd.reset_dmac = true;
1677 dev_err(pl330->ddma.dev, "%s:%d Unexpected!\n", __func__,
1678 __LINE__);
1679 ret = 1;
1680 goto updt_exit;
1681 }
1682
1683 for (ev = 0; ev < pl330->pcfg.num_events; ev++) {
1684 if (val & (1 << ev)) { /* Event occurred */
1685 struct pl330_thread *thrd;
1686 u32 inten = readl(regs + INTEN);
1687 int active;
1688
1689 /* Clear the event */
1690 if (inten & (1 << ev))
1691 writel(1 << ev, regs + INTCLR);
1692
1693 ret = 1;
1694
1695 id = pl330->events[ev];
1696
1697 thrd = &pl330->channels[id];
1698
1699 active = thrd->req_running;
1700 if (active == -1) /* Aborted */
1701 continue;
1702
1703 /* Detach the req */
1704 descdone = thrd->req[active].desc;
1705 thrd->req[active].desc = NULL;
1706
1707 thrd->req_running = -1;
1708
1709 /* Get going again ASAP */
1710 _start(thrd);
1711
1712 /* For now, just make a list of callbacks to be done */
1713 list_add_tail(&descdone->rqd, &pl330->req_done);
1714 }
1715 }
1716
1717 /* Now that we are in no hurry, do the callbacks */
1718 while (!list_empty(&pl330->req_done)) {
1719 descdone = list_first_entry(&pl330->req_done,
1720 struct dma_pl330_desc, rqd);
1721 list_del(&descdone->rqd);
1722 spin_unlock_irqrestore(&pl330->lock, flags);
1723 dma_pl330_rqcb(descdone, PL330_ERR_NONE);
1724 spin_lock_irqsave(&pl330->lock, flags);
1725 }
1726
1727updt_exit:
1728 spin_unlock_irqrestore(&pl330->lock, flags);
1729
1730 if (pl330->dmac_tbd.reset_dmac
1731 || pl330->dmac_tbd.reset_mngr
1732 || pl330->dmac_tbd.reset_chan) {
1733 ret = 1;
1734 tasklet_schedule(&pl330->tasks);
1735 }
1736
1737 return ret;
1738}
1739
1740/* Reserve an event */
1741static inline int _alloc_event(struct pl330_thread *thrd)
1742{
1743 struct pl330_dmac *pl330 = thrd->dmac;
1744 int ev;
1745
1746 for (ev = 0; ev < pl330->pcfg.num_events; ev++)
1747 if (pl330->events[ev] == -1) {
1748 pl330->events[ev] = thrd->id;
1749 return ev;
1750 }
1751
1752 return -1;
1753}
1754
1755static bool _chan_ns(const struct pl330_dmac *pl330, int i)
1756{
1757 return pl330->pcfg.irq_ns & (1 << i);
1758}
1759
1760/* Upon success, returns IdentityToken for the
1761 * allocated channel, NULL otherwise.
1762 */
1763static struct pl330_thread *pl330_request_channel(struct pl330_dmac *pl330)
1764{
1765 struct pl330_thread *thrd = NULL;
1766 int chans, i;
1767
1768 if (pl330->state == DYING)
1769 return NULL;
1770
1771 chans = pl330->pcfg.num_chan;
1772
1773 for (i = 0; i < chans; i++) {
1774 thrd = &pl330->channels[i];
1775 if ((thrd->free) && (!_manager_ns(thrd) ||
1776 _chan_ns(pl330, i))) {
1777 thrd->ev = _alloc_event(thrd);
1778 if (thrd->ev >= 0) {
1779 thrd->free = false;
1780 thrd->lstenq = 1;
1781 thrd->req[0].desc = NULL;
1782 thrd->req[1].desc = NULL;
1783 thrd->req_running = -1;
1784 break;
1785 }
1786 }
1787 thrd = NULL;
1788 }
1789
1790 return thrd;
1791}
1792
1793/* Release an event */
1794static inline void _free_event(struct pl330_thread *thrd, int ev)
1795{
1796 struct pl330_dmac *pl330 = thrd->dmac;
1797
1798 /* If the event is valid and was held by the thread */
1799 if (ev >= 0 && ev < pl330->pcfg.num_events
1800 && pl330->events[ev] == thrd->id)
1801 pl330->events[ev] = -1;
1802}
1803
1804static void pl330_release_channel(struct pl330_thread *thrd)
1805{
1806 if (!thrd || thrd->free)
1807 return;
1808
1809 _stop(thrd);
1810
1811 dma_pl330_rqcb(thrd->req[1 - thrd->lstenq].desc, PL330_ERR_ABORT);
1812 dma_pl330_rqcb(thrd->req[thrd->lstenq].desc, PL330_ERR_ABORT);
1813
1814 _free_event(thrd, thrd->ev);
1815 thrd->free = true;
1816}
1817
1818/* Initialize the structure for PL330 configuration, that can be used
1819 * by the client driver the make best use of the DMAC
1820 */
1821static void read_dmac_config(struct pl330_dmac *pl330)
1822{
1823 void __iomem *regs = pl330->base;
1824 u32 val;
1825
1826 val = readl(regs + CRD) >> CRD_DATA_WIDTH_SHIFT;
1827 val &= CRD_DATA_WIDTH_MASK;
1828 pl330->pcfg.data_bus_width = 8 * (1 << val);
1829
1830 val = readl(regs + CRD) >> CRD_DATA_BUFF_SHIFT;
1831 val &= CRD_DATA_BUFF_MASK;
1832 pl330->pcfg.data_buf_dep = val + 1;
1833
1834 val = readl(regs + CR0) >> CR0_NUM_CHANS_SHIFT;
1835 val &= CR0_NUM_CHANS_MASK;
1836 val += 1;
1837 pl330->pcfg.num_chan = val;
1838
1839 val = readl(regs + CR0);
1840 if (val & CR0_PERIPH_REQ_SET) {
1841 val = (val >> CR0_NUM_PERIPH_SHIFT) & CR0_NUM_PERIPH_MASK;
1842 val += 1;
1843 pl330->pcfg.num_peri = val;
1844 pl330->pcfg.peri_ns = readl(regs + CR4);
1845 } else {
1846 pl330->pcfg.num_peri = 0;
1847 }
1848
1849 val = readl(regs + CR0);
1850 if (val & CR0_BOOT_MAN_NS)
1851 pl330->pcfg.mode |= DMAC_MODE_NS;
1852 else
1853 pl330->pcfg.mode &= ~DMAC_MODE_NS;
1854
1855 val = readl(regs + CR0) >> CR0_NUM_EVENTS_SHIFT;
1856 val &= CR0_NUM_EVENTS_MASK;
1857 val += 1;
1858 pl330->pcfg.num_events = val;
1859
1860 pl330->pcfg.irq_ns = readl(regs + CR3);
1861}
1862
1863static inline void _reset_thread(struct pl330_thread *thrd)
1864{
1865 struct pl330_dmac *pl330 = thrd->dmac;
1866
1867 thrd->req[0].mc_cpu = pl330->mcode_cpu
1868 + (thrd->id * pl330->mcbufsz);
1869 thrd->req[0].mc_bus = pl330->mcode_bus
1870 + (thrd->id * pl330->mcbufsz);
1871 thrd->req[0].desc = NULL;
1872
1873 thrd->req[1].mc_cpu = thrd->req[0].mc_cpu
1874 + pl330->mcbufsz / 2;
1875 thrd->req[1].mc_bus = thrd->req[0].mc_bus
1876 + pl330->mcbufsz / 2;
1877 thrd->req[1].desc = NULL;
1878
1879 thrd->req_running = -1;
1880}
1881
1882static int dmac_alloc_threads(struct pl330_dmac *pl330)
1883{
1884 int chans = pl330->pcfg.num_chan;
1885 struct pl330_thread *thrd;
1886 int i;
1887
1888 /* Allocate 1 Manager and 'chans' Channel threads */
1889 pl330->channels = kcalloc(1 + chans, sizeof(*thrd),
1890 GFP_KERNEL);
1891 if (!pl330->channels)
1892 return -ENOMEM;
1893
1894 /* Init Channel threads */
1895 for (i = 0; i < chans; i++) {
1896 thrd = &pl330->channels[i];
1897 thrd->id = i;
1898 thrd->dmac = pl330;
1899 _reset_thread(thrd);
1900 thrd->free = true;
1901 }
1902
1903 /* MANAGER is indexed at the end */
1904 thrd = &pl330->channels[chans];
1905 thrd->id = chans;
1906 thrd->dmac = pl330;
1907 thrd->free = false;
1908 pl330->manager = thrd;
1909
1910 return 0;
1911}
1912
1913static int dmac_alloc_resources(struct pl330_dmac *pl330)
1914{
1915 int chans = pl330->pcfg.num_chan;
1916 int ret;
1917
1918 /*
1919 * Alloc MicroCode buffer for 'chans' Channel threads.
1920 * A channel's buffer offset is (Channel_Id * MCODE_BUFF_PERCHAN)
1921 */
1922 pl330->mcode_cpu = dma_alloc_attrs(pl330->ddma.dev,
1923 chans * pl330->mcbufsz,
1924 &pl330->mcode_bus, GFP_KERNEL,
1925 DMA_ATTR_PRIVILEGED);
1926 if (!pl330->mcode_cpu) {
1927 dev_err(pl330->ddma.dev, "%s:%d Can't allocate memory!\n",
1928 __func__, __LINE__);
1929 return -ENOMEM;
1930 }
1931
1932 ret = dmac_alloc_threads(pl330);
1933 if (ret) {
1934 dev_err(pl330->ddma.dev, "%s:%d Can't to create channels for DMAC!\n",
1935 __func__, __LINE__);
1936 dma_free_attrs(pl330->ddma.dev,
1937 chans * pl330->mcbufsz,
1938 pl330->mcode_cpu, pl330->mcode_bus,
1939 DMA_ATTR_PRIVILEGED);
1940 return ret;
1941 }
1942
1943 return 0;
1944}
1945
1946static int pl330_add(struct pl330_dmac *pl330)
1947{
1948 int i, ret;
1949
1950 /* Check if we can handle this DMAC */
1951 if ((pl330->pcfg.periph_id & 0xfffff) != PERIPH_ID_VAL) {
1952 dev_err(pl330->ddma.dev, "PERIPH_ID 0x%x !\n",
1953 pl330->pcfg.periph_id);
1954 return -EINVAL;
1955 }
1956
1957 /* Read the configuration of the DMAC */
1958 read_dmac_config(pl330);
1959
1960 if (pl330->pcfg.num_events == 0) {
1961 dev_err(pl330->ddma.dev, "%s:%d Can't work without events!\n",
1962 __func__, __LINE__);
1963 return -EINVAL;
1964 }
1965
1966 spin_lock_init(&pl330->lock);
1967
1968 INIT_LIST_HEAD(&pl330->req_done);
1969
1970 /* Use default MC buffer size if not provided */
1971 if (!pl330->mcbufsz)
1972 pl330->mcbufsz = MCODE_BUFF_PER_REQ * 2;
1973
1974 /* Mark all events as free */
1975 for (i = 0; i < pl330->pcfg.num_events; i++)
1976 pl330->events[i] = -1;
1977
1978 /* Allocate resources needed by the DMAC */
1979 ret = dmac_alloc_resources(pl330);
1980 if (ret) {
1981 dev_err(pl330->ddma.dev, "Unable to create channels for DMAC\n");
1982 return ret;
1983 }
1984
1985 tasklet_init(&pl330->tasks, pl330_dotask, (unsigned long) pl330);
1986
1987 pl330->state = INIT;
1988
1989 return 0;
1990}
1991
1992static int dmac_free_threads(struct pl330_dmac *pl330)
1993{
1994 struct pl330_thread *thrd;
1995 int i;
1996
1997 /* Release Channel threads */
1998 for (i = 0; i < pl330->pcfg.num_chan; i++) {
1999 thrd = &pl330->channels[i];
2000 pl330_release_channel(thrd);
2001 }
2002
2003 /* Free memory */
2004 kfree(pl330->channels);
2005
2006 return 0;
2007}
2008
2009static void pl330_del(struct pl330_dmac *pl330)
2010{
2011 pl330->state = UNINIT;
2012
2013 tasklet_kill(&pl330->tasks);
2014
2015 /* Free DMAC resources */
2016 dmac_free_threads(pl330);
2017
2018 dma_free_attrs(pl330->ddma.dev,
2019 pl330->pcfg.num_chan * pl330->mcbufsz, pl330->mcode_cpu,
2020 pl330->mcode_bus, DMA_ATTR_PRIVILEGED);
2021}
2022
2023/* forward declaration */
2024static struct amba_driver pl330_driver;
2025
2026static inline struct dma_pl330_chan *
2027to_pchan(struct dma_chan *ch)
2028{
2029 if (!ch)
2030 return NULL;
2031
2032 return container_of(ch, struct dma_pl330_chan, chan);
2033}
2034
2035static inline struct dma_pl330_desc *
2036to_desc(struct dma_async_tx_descriptor *tx)
2037{
2038 return container_of(tx, struct dma_pl330_desc, txd);
2039}
2040
2041static inline void fill_queue(struct dma_pl330_chan *pch)
2042{
2043 struct dma_pl330_desc *desc;
2044 int ret;
2045
2046 list_for_each_entry(desc, &pch->work_list, node) {
2047
2048 /* If already submitted */
2049 if (desc->status == BUSY)
2050 continue;
2051
2052 ret = pl330_submit_req(pch->thread, desc);
2053 if (!ret) {
2054 desc->status = BUSY;
2055 } else if (ret == -EAGAIN) {
2056 /* QFull or DMAC Dying */
2057 break;
2058 } else {
2059 /* Unacceptable request */
2060 desc->status = DONE;
2061 dev_err(pch->dmac->ddma.dev, "%s:%d Bad Desc(%d)\n",
2062 __func__, __LINE__, desc->txd.cookie);
2063 tasklet_schedule(&pch->task);
2064 }
2065 }
2066}
2067
2068static void pl330_tasklet(unsigned long data)
2069{
2070 struct dma_pl330_chan *pch = (struct dma_pl330_chan *)data;
2071 struct dma_pl330_desc *desc, *_dt;
2072 unsigned long flags;
2073 bool power_down = false;
2074
2075 spin_lock_irqsave(&pch->lock, flags);
2076
2077 /* Pick up ripe tomatoes */
2078 list_for_each_entry_safe(desc, _dt, &pch->work_list, node)
2079 if (desc->status == DONE) {
2080 if (!pch->cyclic)
2081 dma_cookie_complete(&desc->txd);
2082 list_move_tail(&desc->node, &pch->completed_list);
2083 }
2084
2085 /* Try to submit a req imm. next to the last completed cookie */
2086 fill_queue(pch);
2087
2088 if (list_empty(&pch->work_list)) {
2089 spin_lock(&pch->thread->dmac->lock);
2090 _stop(pch->thread);
2091 spin_unlock(&pch->thread->dmac->lock);
2092 power_down = true;
2093 pch->active = false;
2094 } else {
2095 /* Make sure the PL330 Channel thread is active */
2096 spin_lock(&pch->thread->dmac->lock);
2097 _start(pch->thread);
2098 spin_unlock(&pch->thread->dmac->lock);
2099 }
2100
2101 while (!list_empty(&pch->completed_list)) {
2102 struct dmaengine_desc_callback cb;
2103
2104 desc = list_first_entry(&pch->completed_list,
2105 struct dma_pl330_desc, node);
2106
2107 dmaengine_desc_get_callback(&desc->txd, &cb);
2108
2109 if (pch->cyclic) {
2110 desc->status = PREP;
2111 list_move_tail(&desc->node, &pch->work_list);
2112 if (power_down) {
2113 pch->active = true;
2114 spin_lock(&pch->thread->dmac->lock);
2115 _start(pch->thread);
2116 spin_unlock(&pch->thread->dmac->lock);
2117 power_down = false;
2118 }
2119 } else {
2120 desc->status = FREE;
2121 list_move_tail(&desc->node, &pch->dmac->desc_pool);
2122 }
2123
2124 dma_descriptor_unmap(&desc->txd);
2125
2126 if (dmaengine_desc_callback_valid(&cb)) {
2127 spin_unlock_irqrestore(&pch->lock, flags);
2128 dmaengine_desc_callback_invoke(&cb, NULL);
2129 spin_lock_irqsave(&pch->lock, flags);
2130 }
2131 }
2132 spin_unlock_irqrestore(&pch->lock, flags);
2133
2134 /* If work list empty, power down */
2135 if (power_down) {
2136 pm_runtime_mark_last_busy(pch->dmac->ddma.dev);
2137 pm_runtime_put_autosuspend(pch->dmac->ddma.dev);
2138 }
2139}
2140
2141static struct dma_chan *of_dma_pl330_xlate(struct of_phandle_args *dma_spec,
2142 struct of_dma *ofdma)
2143{
2144 int count = dma_spec->args_count;
2145 struct pl330_dmac *pl330 = ofdma->of_dma_data;
2146 unsigned int chan_id;
2147
2148 if (!pl330)
2149 return NULL;
2150
2151 if (count != 1)
2152 return NULL;
2153
2154 chan_id = dma_spec->args[0];
2155 if (chan_id >= pl330->num_peripherals)
2156 return NULL;
2157
2158 return dma_get_slave_channel(&pl330->peripherals[chan_id].chan);
2159}
2160
2161static int pl330_alloc_chan_resources(struct dma_chan *chan)
2162{
2163 struct dma_pl330_chan *pch = to_pchan(chan);
2164 struct pl330_dmac *pl330 = pch->dmac;
2165 unsigned long flags;
2166
2167 spin_lock_irqsave(&pl330->lock, flags);
2168
2169 dma_cookie_init(chan);
2170 pch->cyclic = false;
2171
2172 pch->thread = pl330_request_channel(pl330);
2173 if (!pch->thread) {
2174 spin_unlock_irqrestore(&pl330->lock, flags);
2175 return -ENOMEM;
2176 }
2177
2178 tasklet_init(&pch->task, pl330_tasklet, (unsigned long) pch);
2179
2180 spin_unlock_irqrestore(&pl330->lock, flags);
2181
2182 return 1;
2183}
2184
2185/*
2186 * We need the data direction between the DMAC (the dma-mapping "device") and
2187 * the FIFO (the dmaengine "dev"), from the FIFO's point of view. Confusing!
2188 */
2189static enum dma_data_direction
2190pl330_dma_slave_map_dir(enum dma_transfer_direction dir)
2191{
2192 switch (dir) {
2193 case DMA_MEM_TO_DEV:
2194 return DMA_FROM_DEVICE;
2195 case DMA_DEV_TO_MEM:
2196 return DMA_TO_DEVICE;
2197 case DMA_DEV_TO_DEV:
2198 return DMA_BIDIRECTIONAL;
2199 default:
2200 return DMA_NONE;
2201 }
2202}
2203
2204static void pl330_unprep_slave_fifo(struct dma_pl330_chan *pch)
2205{
2206 if (pch->dir != DMA_NONE)
2207 dma_unmap_resource(pch->chan.device->dev, pch->fifo_dma,
2208 1 << pch->burst_sz, pch->dir, 0);
2209 pch->dir = DMA_NONE;
2210}
2211
2212
2213static bool pl330_prep_slave_fifo(struct dma_pl330_chan *pch,
2214 enum dma_transfer_direction dir)
2215{
2216 struct device *dev = pch->chan.device->dev;
2217 enum dma_data_direction dma_dir = pl330_dma_slave_map_dir(dir);
2218
2219 /* Already mapped for this config? */
2220 if (pch->dir == dma_dir)
2221 return true;
2222
2223 pl330_unprep_slave_fifo(pch);
2224 pch->fifo_dma = dma_map_resource(dev, pch->fifo_addr,
2225 1 << pch->burst_sz, dma_dir, 0);
2226 if (dma_mapping_error(dev, pch->fifo_dma))
2227 return false;
2228
2229 pch->dir = dma_dir;
2230 return true;
2231}
2232
2233static int fixup_burst_len(int max_burst_len, int quirks)
2234{
2235 if (max_burst_len > PL330_MAX_BURST)
2236 return PL330_MAX_BURST;
2237 else if (max_burst_len < 1)
2238 return 1;
2239 else
2240 return max_burst_len;
2241}
2242
2243static int pl330_config_write(struct dma_chan *chan,
2244 struct dma_slave_config *slave_config,
2245 enum dma_transfer_direction direction)
2246{
2247 struct dma_pl330_chan *pch = to_pchan(chan);
2248
2249 pl330_unprep_slave_fifo(pch);
2250 if (direction == DMA_MEM_TO_DEV) {
2251 if (slave_config->dst_addr)
2252 pch->fifo_addr = slave_config->dst_addr;
2253 if (slave_config->dst_addr_width)
2254 pch->burst_sz = __ffs(slave_config->dst_addr_width);
2255 pch->burst_len = fixup_burst_len(slave_config->dst_maxburst,
2256 pch->dmac->quirks);
2257 } else if (direction == DMA_DEV_TO_MEM) {
2258 if (slave_config->src_addr)
2259 pch->fifo_addr = slave_config->src_addr;
2260 if (slave_config->src_addr_width)
2261 pch->burst_sz = __ffs(slave_config->src_addr_width);
2262 pch->burst_len = fixup_burst_len(slave_config->src_maxburst,
2263 pch->dmac->quirks);
2264 }
2265
2266 return 0;
2267}
2268
2269static int pl330_config(struct dma_chan *chan,
2270 struct dma_slave_config *slave_config)
2271{
2272 struct dma_pl330_chan *pch = to_pchan(chan);
2273
2274 memcpy(&pch->slave_config, slave_config, sizeof(*slave_config));
2275
2276 return 0;
2277}
2278
2279static int pl330_terminate_all(struct dma_chan *chan)
2280{
2281 struct dma_pl330_chan *pch = to_pchan(chan);
2282 struct dma_pl330_desc *desc;
2283 unsigned long flags;
2284 struct pl330_dmac *pl330 = pch->dmac;
2285 bool power_down = false;
2286
2287 pm_runtime_get_sync(pl330->ddma.dev);
2288 spin_lock_irqsave(&pch->lock, flags);
2289
2290 spin_lock(&pl330->lock);
2291 _stop(pch->thread);
2292 pch->thread->req[0].desc = NULL;
2293 pch->thread->req[1].desc = NULL;
2294 pch->thread->req_running = -1;
2295 spin_unlock(&pl330->lock);
2296
2297 power_down = pch->active;
2298 pch->active = false;
2299
2300 /* Mark all desc done */
2301 list_for_each_entry(desc, &pch->submitted_list, node) {
2302 desc->status = FREE;
2303 dma_cookie_complete(&desc->txd);
2304 }
2305
2306 list_for_each_entry(desc, &pch->work_list , node) {
2307 desc->status = FREE;
2308 dma_cookie_complete(&desc->txd);
2309 }
2310
2311 list_splice_tail_init(&pch->submitted_list, &pl330->desc_pool);
2312 list_splice_tail_init(&pch->work_list, &pl330->desc_pool);
2313 list_splice_tail_init(&pch->completed_list, &pl330->desc_pool);
2314 spin_unlock_irqrestore(&pch->lock, flags);
2315 pm_runtime_mark_last_busy(pl330->ddma.dev);
2316 if (power_down)
2317 pm_runtime_put_autosuspend(pl330->ddma.dev);
2318 pm_runtime_put_autosuspend(pl330->ddma.dev);
2319
2320 return 0;
2321}
2322
2323/*
2324 * We don't support DMA_RESUME command because of hardware
2325 * limitations, so after pausing the channel we cannot restore
2326 * it to active state. We have to terminate channel and setup
2327 * DMA transfer again. This pause feature was implemented to
2328 * allow safely read residue before channel termination.
2329 */
2330static int pl330_pause(struct dma_chan *chan)
2331{
2332 struct dma_pl330_chan *pch = to_pchan(chan);
2333 struct pl330_dmac *pl330 = pch->dmac;
2334 unsigned long flags;
2335
2336 pm_runtime_get_sync(pl330->ddma.dev);
2337 spin_lock_irqsave(&pch->lock, flags);
2338
2339 spin_lock(&pl330->lock);
2340 _stop(pch->thread);
2341 spin_unlock(&pl330->lock);
2342
2343 spin_unlock_irqrestore(&pch->lock, flags);
2344 pm_runtime_mark_last_busy(pl330->ddma.dev);
2345 pm_runtime_put_autosuspend(pl330->ddma.dev);
2346
2347 return 0;
2348}
2349
2350static void pl330_free_chan_resources(struct dma_chan *chan)
2351{
2352 struct dma_pl330_chan *pch = to_pchan(chan);
2353 struct pl330_dmac *pl330 = pch->dmac;
2354 unsigned long flags;
2355
2356 tasklet_kill(&pch->task);
2357
2358 pm_runtime_get_sync(pch->dmac->ddma.dev);
2359 spin_lock_irqsave(&pl330->lock, flags);
2360
2361 pl330_release_channel(pch->thread);
2362 pch->thread = NULL;
2363
2364 if (pch->cyclic)
2365 list_splice_tail_init(&pch->work_list, &pch->dmac->desc_pool);
2366
2367 spin_unlock_irqrestore(&pl330->lock, flags);
2368 pm_runtime_mark_last_busy(pch->dmac->ddma.dev);
2369 pm_runtime_put_autosuspend(pch->dmac->ddma.dev);
2370 pl330_unprep_slave_fifo(pch);
2371}
2372
2373static int pl330_get_current_xferred_count(struct dma_pl330_chan *pch,
2374 struct dma_pl330_desc *desc)
2375{
2376 struct pl330_thread *thrd = pch->thread;
2377 struct pl330_dmac *pl330 = pch->dmac;
2378 void __iomem *regs = thrd->dmac->base;
2379 u32 val, addr;
2380
2381 pm_runtime_get_sync(pl330->ddma.dev);
2382 val = addr = 0;
2383 if (desc->rqcfg.src_inc) {
2384 val = readl(regs + SA(thrd->id));
2385 addr = desc->px.src_addr;
2386 } else {
2387 val = readl(regs + DA(thrd->id));
2388 addr = desc->px.dst_addr;
2389 }
2390 pm_runtime_mark_last_busy(pch->dmac->ddma.dev);
2391 pm_runtime_put_autosuspend(pl330->ddma.dev);
2392
2393 /* If DMAMOV hasn't finished yet, SAR/DAR can be zero */
2394 if (!val)
2395 return 0;
2396
2397 return val - addr;
2398}
2399
2400static enum dma_status
2401pl330_tx_status(struct dma_chan *chan, dma_cookie_t cookie,
2402 struct dma_tx_state *txstate)
2403{
2404 enum dma_status ret;
2405 unsigned long flags;
2406 struct dma_pl330_desc *desc, *running = NULL, *last_enq = NULL;
2407 struct dma_pl330_chan *pch = to_pchan(chan);
2408 unsigned int transferred, residual = 0;
2409
2410 ret = dma_cookie_status(chan, cookie, txstate);
2411
2412 if (!txstate)
2413 return ret;
2414
2415 if (ret == DMA_COMPLETE)
2416 goto out;
2417
2418 spin_lock_irqsave(&pch->lock, flags);
2419 spin_lock(&pch->thread->dmac->lock);
2420
2421 if (pch->thread->req_running != -1)
2422 running = pch->thread->req[pch->thread->req_running].desc;
2423
2424 last_enq = pch->thread->req[pch->thread->lstenq].desc;
2425
2426 /* Check in pending list */
2427 list_for_each_entry(desc, &pch->work_list, node) {
2428 if (desc->status == DONE)
2429 transferred = desc->bytes_requested;
2430 else if (running && desc == running)
2431 transferred =
2432 pl330_get_current_xferred_count(pch, desc);
2433 else if (desc->status == BUSY)
2434 /*
2435 * Busy but not running means either just enqueued,
2436 * or finished and not yet marked done
2437 */
2438 if (desc == last_enq)
2439 transferred = 0;
2440 else
2441 transferred = desc->bytes_requested;
2442 else
2443 transferred = 0;
2444 residual += desc->bytes_requested - transferred;
2445 if (desc->txd.cookie == cookie) {
2446 switch (desc->status) {
2447 case DONE:
2448 ret = DMA_COMPLETE;
2449 break;
2450 case PREP:
2451 case BUSY:
2452 ret = DMA_IN_PROGRESS;
2453 break;
2454 default:
2455 WARN_ON(1);
2456 }
2457 break;
2458 }
2459 if (desc->last)
2460 residual = 0;
2461 }
2462 spin_unlock(&pch->thread->dmac->lock);
2463 spin_unlock_irqrestore(&pch->lock, flags);
2464
2465out:
2466 dma_set_residue(txstate, residual);
2467
2468 return ret;
2469}
2470
2471static void pl330_issue_pending(struct dma_chan *chan)
2472{
2473 struct dma_pl330_chan *pch = to_pchan(chan);
2474 unsigned long flags;
2475
2476 spin_lock_irqsave(&pch->lock, flags);
2477 if (list_empty(&pch->work_list)) {
2478 /*
2479 * Warn on nothing pending. Empty submitted_list may
2480 * break our pm_runtime usage counter as it is
2481 * updated on work_list emptiness status.
2482 */
2483 WARN_ON(list_empty(&pch->submitted_list));
2484 pch->active = true;
2485 pm_runtime_get_sync(pch->dmac->ddma.dev);
2486 }
2487 list_splice_tail_init(&pch->submitted_list, &pch->work_list);
2488 spin_unlock_irqrestore(&pch->lock, flags);
2489
2490 pl330_tasklet((unsigned long)pch);
2491}
2492
2493/*
2494 * We returned the last one of the circular list of descriptor(s)
2495 * from prep_xxx, so the argument to submit corresponds to the last
2496 * descriptor of the list.
2497 */
2498static dma_cookie_t pl330_tx_submit(struct dma_async_tx_descriptor *tx)
2499{
2500 struct dma_pl330_desc *desc, *last = to_desc(tx);
2501 struct dma_pl330_chan *pch = to_pchan(tx->chan);
2502 dma_cookie_t cookie;
2503 unsigned long flags;
2504
2505 spin_lock_irqsave(&pch->lock, flags);
2506
2507 /* Assign cookies to all nodes */
2508 while (!list_empty(&last->node)) {
2509 desc = list_entry(last->node.next, struct dma_pl330_desc, node);
2510 if (pch->cyclic) {
2511 desc->txd.callback = last->txd.callback;
2512 desc->txd.callback_param = last->txd.callback_param;
2513 }
2514 desc->last = false;
2515
2516 dma_cookie_assign(&desc->txd);
2517
2518 list_move_tail(&desc->node, &pch->submitted_list);
2519 }
2520
2521 last->last = true;
2522 cookie = dma_cookie_assign(&last->txd);
2523 list_add_tail(&last->node, &pch->submitted_list);
2524 spin_unlock_irqrestore(&pch->lock, flags);
2525
2526 return cookie;
2527}
2528
2529static inline void _init_desc(struct dma_pl330_desc *desc)
2530{
2531 desc->rqcfg.swap = SWAP_NO;
2532 desc->rqcfg.scctl = CCTRL0;
2533 desc->rqcfg.dcctl = CCTRL0;
2534 desc->txd.tx_submit = pl330_tx_submit;
2535
2536 INIT_LIST_HEAD(&desc->node);
2537}
2538
2539/* Returns the number of descriptors added to the DMAC pool */
2540static int add_desc(struct list_head *pool, spinlock_t *lock,
2541 gfp_t flg, int count)
2542{
2543 struct dma_pl330_desc *desc;
2544 unsigned long flags;
2545 int i;
2546
2547 desc = kcalloc(count, sizeof(*desc), flg);
2548 if (!desc)
2549 return 0;
2550
2551 spin_lock_irqsave(lock, flags);
2552
2553 for (i = 0; i < count; i++) {
2554 _init_desc(&desc[i]);
2555 list_add_tail(&desc[i].node, pool);
2556 }
2557
2558 spin_unlock_irqrestore(lock, flags);
2559
2560 return count;
2561}
2562
2563static struct dma_pl330_desc *pluck_desc(struct list_head *pool,
2564 spinlock_t *lock)
2565{
2566 struct dma_pl330_desc *desc = NULL;
2567 unsigned long flags;
2568
2569 spin_lock_irqsave(lock, flags);
2570
2571 if (!list_empty(pool)) {
2572 desc = list_entry(pool->next,
2573 struct dma_pl330_desc, node);
2574
2575 list_del_init(&desc->node);
2576
2577 desc->status = PREP;
2578 desc->txd.callback = NULL;
2579 }
2580
2581 spin_unlock_irqrestore(lock, flags);
2582
2583 return desc;
2584}
2585
2586static struct dma_pl330_desc *pl330_get_desc(struct dma_pl330_chan *pch)
2587{
2588 struct pl330_dmac *pl330 = pch->dmac;
2589 u8 *peri_id = pch->chan.private;
2590 struct dma_pl330_desc *desc;
2591
2592 /* Pluck one desc from the pool of DMAC */
2593 desc = pluck_desc(&pl330->desc_pool, &pl330->pool_lock);
2594
2595 /* If the DMAC pool is empty, alloc new */
2596 if (!desc) {
2597 DEFINE_SPINLOCK(lock);
2598 LIST_HEAD(pool);
2599
2600 if (!add_desc(&pool, &lock, GFP_ATOMIC, 1))
2601 return NULL;
2602
2603 desc = pluck_desc(&pool, &lock);
2604 WARN_ON(!desc || !list_empty(&pool));
2605 }
2606
2607 /* Initialize the descriptor */
2608 desc->pchan = pch;
2609 desc->txd.cookie = 0;
2610 async_tx_ack(&desc->txd);
2611
2612 desc->peri = peri_id ? pch->chan.chan_id : 0;
2613 desc->rqcfg.pcfg = &pch->dmac->pcfg;
2614
2615 dma_async_tx_descriptor_init(&desc->txd, &pch->chan);
2616
2617 return desc;
2618}
2619
2620static inline void fill_px(struct pl330_xfer *px,
2621 dma_addr_t dst, dma_addr_t src, size_t len)
2622{
2623 px->bytes = len;
2624 px->dst_addr = dst;
2625 px->src_addr = src;
2626}
2627
2628static struct dma_pl330_desc *
2629__pl330_prep_dma_memcpy(struct dma_pl330_chan *pch, dma_addr_t dst,
2630 dma_addr_t src, size_t len)
2631{
2632 struct dma_pl330_desc *desc = pl330_get_desc(pch);
2633
2634 if (!desc) {
2635 dev_err(pch->dmac->ddma.dev, "%s:%d Unable to fetch desc\n",
2636 __func__, __LINE__);
2637 return NULL;
2638 }
2639
2640 /*
2641 * Ideally we should lookout for reqs bigger than
2642 * those that can be programmed with 256 bytes of
2643 * MC buffer, but considering a req size is seldom
2644 * going to be word-unaligned and more than 200MB,
2645 * we take it easy.
2646 * Also, should the limit is reached we'd rather
2647 * have the platform increase MC buffer size than
2648 * complicating this API driver.
2649 */
2650 fill_px(&desc->px, dst, src, len);
2651
2652 return desc;
2653}
2654
2655/* Call after fixing burst size */
2656static inline int get_burst_len(struct dma_pl330_desc *desc, size_t len)
2657{
2658 struct dma_pl330_chan *pch = desc->pchan;
2659 struct pl330_dmac *pl330 = pch->dmac;
2660 int burst_len;
2661
2662 burst_len = pl330->pcfg.data_bus_width / 8;
2663 burst_len *= pl330->pcfg.data_buf_dep / pl330->pcfg.num_chan;
2664 burst_len >>= desc->rqcfg.brst_size;
2665
2666 /* src/dst_burst_len can't be more than 16 */
2667 if (burst_len > PL330_MAX_BURST)
2668 burst_len = PL330_MAX_BURST;
2669
2670 return burst_len;
2671}
2672
2673static struct dma_async_tx_descriptor *pl330_prep_dma_cyclic(
2674 struct dma_chan *chan, dma_addr_t dma_addr, size_t len,
2675 size_t period_len, enum dma_transfer_direction direction,
2676 unsigned long flags)
2677{
2678 struct dma_pl330_desc *desc = NULL, *first = NULL;
2679 struct dma_pl330_chan *pch = to_pchan(chan);
2680 struct pl330_dmac *pl330 = pch->dmac;
2681 unsigned int i;
2682 dma_addr_t dst;
2683 dma_addr_t src;
2684
2685 if (len % period_len != 0)
2686 return NULL;
2687
2688 if (!is_slave_direction(direction)) {
2689 dev_err(pch->dmac->ddma.dev, "%s:%d Invalid dma direction\n",
2690 __func__, __LINE__);
2691 return NULL;
2692 }
2693
2694 pl330_config_write(chan, &pch->slave_config, direction);
2695
2696 if (!pl330_prep_slave_fifo(pch, direction))
2697 return NULL;
2698
2699 for (i = 0; i < len / period_len; i++) {
2700 desc = pl330_get_desc(pch);
2701 if (!desc) {
2702 dev_err(pch->dmac->ddma.dev, "%s:%d Unable to fetch desc\n",
2703 __func__, __LINE__);
2704
2705 if (!first)
2706 return NULL;
2707
2708 spin_lock_irqsave(&pl330->pool_lock, flags);
2709
2710 while (!list_empty(&first->node)) {
2711 desc = list_entry(first->node.next,
2712 struct dma_pl330_desc, node);
2713 list_move_tail(&desc->node, &pl330->desc_pool);
2714 }
2715
2716 list_move_tail(&first->node, &pl330->desc_pool);
2717
2718 spin_unlock_irqrestore(&pl330->pool_lock, flags);
2719
2720 return NULL;
2721 }
2722
2723 switch (direction) {
2724 case DMA_MEM_TO_DEV:
2725 desc->rqcfg.src_inc = 1;
2726 desc->rqcfg.dst_inc = 0;
2727 src = dma_addr;
2728 dst = pch->fifo_dma;
2729 break;
2730 case DMA_DEV_TO_MEM:
2731 desc->rqcfg.src_inc = 0;
2732 desc->rqcfg.dst_inc = 1;
2733 src = pch->fifo_dma;
2734 dst = dma_addr;
2735 break;
2736 default:
2737 break;
2738 }
2739
2740 desc->rqtype = direction;
2741 desc->rqcfg.brst_size = pch->burst_sz;
2742 desc->rqcfg.brst_len = pch->burst_len;
2743 desc->bytes_requested = period_len;
2744 fill_px(&desc->px, dst, src, period_len);
2745
2746 if (!first)
2747 first = desc;
2748 else
2749 list_add_tail(&desc->node, &first->node);
2750
2751 dma_addr += period_len;
2752 }
2753
2754 if (!desc)
2755 return NULL;
2756
2757 pch->cyclic = true;
2758 desc->txd.flags = flags;
2759
2760 return &desc->txd;
2761}
2762
2763static struct dma_async_tx_descriptor *
2764pl330_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dst,
2765 dma_addr_t src, size_t len, unsigned long flags)
2766{
2767 struct dma_pl330_desc *desc;
2768 struct dma_pl330_chan *pch = to_pchan(chan);
2769 struct pl330_dmac *pl330;
2770 int burst;
2771
2772 if (unlikely(!pch || !len))
2773 return NULL;
2774
2775 pl330 = pch->dmac;
2776
2777 desc = __pl330_prep_dma_memcpy(pch, dst, src, len);
2778 if (!desc)
2779 return NULL;
2780
2781 desc->rqcfg.src_inc = 1;
2782 desc->rqcfg.dst_inc = 1;
2783 desc->rqtype = DMA_MEM_TO_MEM;
2784
2785 /* Select max possible burst size */
2786 burst = pl330->pcfg.data_bus_width / 8;
2787
2788 /*
2789 * Make sure we use a burst size that aligns with all the memcpy
2790 * parameters because our DMA programming algorithm doesn't cope with
2791 * transfers which straddle an entry in the DMA device's MFIFO.
2792 */
2793 while ((src | dst | len) & (burst - 1))
2794 burst /= 2;
2795
2796 desc->rqcfg.brst_size = 0;
2797 while (burst != (1 << desc->rqcfg.brst_size))
2798 desc->rqcfg.brst_size++;
2799
2800 desc->rqcfg.brst_len = get_burst_len(desc, len);
2801 /*
2802 * If burst size is smaller than bus width then make sure we only
2803 * transfer one at a time to avoid a burst stradling an MFIFO entry.
2804 */
2805 if (desc->rqcfg.brst_size * 8 < pl330->pcfg.data_bus_width)
2806 desc->rqcfg.brst_len = 1;
2807
2808 desc->bytes_requested = len;
2809
2810 desc->txd.flags = flags;
2811
2812 return &desc->txd;
2813}
2814
2815static void __pl330_giveback_desc(struct pl330_dmac *pl330,
2816 struct dma_pl330_desc *first)
2817{
2818 unsigned long flags;
2819 struct dma_pl330_desc *desc;
2820
2821 if (!first)
2822 return;
2823
2824 spin_lock_irqsave(&pl330->pool_lock, flags);
2825
2826 while (!list_empty(&first->node)) {
2827 desc = list_entry(first->node.next,
2828 struct dma_pl330_desc, node);
2829 list_move_tail(&desc->node, &pl330->desc_pool);
2830 }
2831
2832 list_move_tail(&first->node, &pl330->desc_pool);
2833
2834 spin_unlock_irqrestore(&pl330->pool_lock, flags);
2835}
2836
2837static struct dma_async_tx_descriptor *
2838pl330_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
2839 unsigned int sg_len, enum dma_transfer_direction direction,
2840 unsigned long flg, void *context)
2841{
2842 struct dma_pl330_desc *first, *desc = NULL;
2843 struct dma_pl330_chan *pch = to_pchan(chan);
2844 struct scatterlist *sg;
2845 int i;
2846
2847 if (unlikely(!pch || !sgl || !sg_len))
2848 return NULL;
2849
2850 pl330_config_write(chan, &pch->slave_config, direction);
2851
2852 if (!pl330_prep_slave_fifo(pch, direction))
2853 return NULL;
2854
2855 first = NULL;
2856
2857 for_each_sg(sgl, sg, sg_len, i) {
2858
2859 desc = pl330_get_desc(pch);
2860 if (!desc) {
2861 struct pl330_dmac *pl330 = pch->dmac;
2862
2863 dev_err(pch->dmac->ddma.dev,
2864 "%s:%d Unable to fetch desc\n",
2865 __func__, __LINE__);
2866 __pl330_giveback_desc(pl330, first);
2867
2868 return NULL;
2869 }
2870
2871 if (!first)
2872 first = desc;
2873 else
2874 list_add_tail(&desc->node, &first->node);
2875
2876 if (direction == DMA_MEM_TO_DEV) {
2877 desc->rqcfg.src_inc = 1;
2878 desc->rqcfg.dst_inc = 0;
2879 fill_px(&desc->px, pch->fifo_dma, sg_dma_address(sg),
2880 sg_dma_len(sg));
2881 } else {
2882 desc->rqcfg.src_inc = 0;
2883 desc->rqcfg.dst_inc = 1;
2884 fill_px(&desc->px, sg_dma_address(sg), pch->fifo_dma,
2885 sg_dma_len(sg));
2886 }
2887
2888 desc->rqcfg.brst_size = pch->burst_sz;
2889 desc->rqcfg.brst_len = pch->burst_len;
2890 desc->rqtype = direction;
2891 desc->bytes_requested = sg_dma_len(sg);
2892 }
2893
2894 /* Return the last desc in the chain */
2895 desc->txd.flags = flg;
2896 return &desc->txd;
2897}
2898
2899static irqreturn_t pl330_irq_handler(int irq, void *data)
2900{
2901 if (pl330_update(data))
2902 return IRQ_HANDLED;
2903 else
2904 return IRQ_NONE;
2905}
2906
2907#define PL330_DMA_BUSWIDTHS \
2908 BIT(DMA_SLAVE_BUSWIDTH_UNDEFINED) | \
2909 BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | \
2910 BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | \
2911 BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) | \
2912 BIT(DMA_SLAVE_BUSWIDTH_8_BYTES)
2913
2914#ifdef CONFIG_DEBUG_FS
2915static int pl330_debugfs_show(struct seq_file *s, void *data)
2916{
2917 struct pl330_dmac *pl330 = s->private;
2918 int chans, pchs, ch, pr;
2919
2920 chans = pl330->pcfg.num_chan;
2921 pchs = pl330->num_peripherals;
2922
2923 seq_puts(s, "PL330 physical channels:\n");
2924 seq_puts(s, "THREAD:\t\tCHANNEL:\n");
2925 seq_puts(s, "--------\t-----\n");
2926 for (ch = 0; ch < chans; ch++) {
2927 struct pl330_thread *thrd = &pl330->channels[ch];
2928 int found = -1;
2929
2930 for (pr = 0; pr < pchs; pr++) {
2931 struct dma_pl330_chan *pch = &pl330->peripherals[pr];
2932
2933 if (!pch->thread || thrd->id != pch->thread->id)
2934 continue;
2935
2936 found = pr;
2937 }
2938
2939 seq_printf(s, "%d\t\t", thrd->id);
2940 if (found == -1)
2941 seq_puts(s, "--\n");
2942 else
2943 seq_printf(s, "%d\n", found);
2944 }
2945
2946 return 0;
2947}
2948
2949DEFINE_SHOW_ATTRIBUTE(pl330_debugfs);
2950
2951static inline void init_pl330_debugfs(struct pl330_dmac *pl330)
2952{
2953 debugfs_create_file(dev_name(pl330->ddma.dev),
2954 S_IFREG | 0444, NULL, pl330,
2955 &pl330_debugfs_fops);
2956}
2957#else
2958static inline void init_pl330_debugfs(struct pl330_dmac *pl330)
2959{
2960}
2961#endif
2962
2963/*
2964 * Runtime PM callbacks are provided by amba/bus.c driver.
2965 *
2966 * It is assumed here that IRQ safe runtime PM is chosen in probe and amba
2967 * bus driver will only disable/enable the clock in runtime PM callbacks.
2968 */
2969static int __maybe_unused pl330_suspend(struct device *dev)
2970{
2971 struct amba_device *pcdev = to_amba_device(dev);
2972
2973 pm_runtime_force_suspend(dev);
2974 amba_pclk_unprepare(pcdev);
2975
2976 return 0;
2977}
2978
2979static int __maybe_unused pl330_resume(struct device *dev)
2980{
2981 struct amba_device *pcdev = to_amba_device(dev);
2982 int ret;
2983
2984 ret = amba_pclk_prepare(pcdev);
2985 if (ret)
2986 return ret;
2987
2988 pm_runtime_force_resume(dev);
2989
2990 return ret;
2991}
2992
2993static const struct dev_pm_ops pl330_pm = {
2994 SET_LATE_SYSTEM_SLEEP_PM_OPS(pl330_suspend, pl330_resume)
2995};
2996
2997static int
2998pl330_probe(struct amba_device *adev, const struct amba_id *id)
2999{
3000 struct pl330_config *pcfg;
3001 struct pl330_dmac *pl330;
3002 struct dma_pl330_chan *pch, *_p;
3003 struct dma_device *pd;
3004 struct resource *res;
3005 int i, ret, irq;
3006 int num_chan;
3007 struct device_node *np = adev->dev.of_node;
3008
3009 ret = dma_set_mask_and_coherent(&adev->dev, DMA_BIT_MASK(32));
3010 if (ret)
3011 return ret;
3012
3013 /* Allocate a new DMAC and its Channels */
3014 pl330 = devm_kzalloc(&adev->dev, sizeof(*pl330), GFP_KERNEL);
3015 if (!pl330)
3016 return -ENOMEM;
3017
3018 pd = &pl330->ddma;
3019 pd->dev = &adev->dev;
3020
3021 pl330->mcbufsz = 0;
3022
3023 /* get quirk */
3024 for (i = 0; i < ARRAY_SIZE(of_quirks); i++)
3025 if (of_property_read_bool(np, of_quirks[i].quirk))
3026 pl330->quirks |= of_quirks[i].id;
3027
3028 res = &adev->res;
3029 pl330->base = devm_ioremap_resource(&adev->dev, res);
3030 if (IS_ERR(pl330->base))
3031 return PTR_ERR(pl330->base);
3032
3033 amba_set_drvdata(adev, pl330);
3034
3035 pl330->rstc = devm_reset_control_get_optional(&adev->dev, "dma");
3036 if (IS_ERR(pl330->rstc)) {
3037 if (PTR_ERR(pl330->rstc) != -EPROBE_DEFER)
3038 dev_err(&adev->dev, "Failed to get reset!\n");
3039 return PTR_ERR(pl330->rstc);
3040 } else {
3041 ret = reset_control_deassert(pl330->rstc);
3042 if (ret) {
3043 dev_err(&adev->dev, "Couldn't deassert the device from reset!\n");
3044 return ret;
3045 }
3046 }
3047
3048 pl330->rstc_ocp = devm_reset_control_get_optional(&adev->dev, "dma-ocp");
3049 if (IS_ERR(pl330->rstc_ocp)) {
3050 if (PTR_ERR(pl330->rstc_ocp) != -EPROBE_DEFER)
3051 dev_err(&adev->dev, "Failed to get OCP reset!\n");
3052 return PTR_ERR(pl330->rstc_ocp);
3053 } else {
3054 ret = reset_control_deassert(pl330->rstc_ocp);
3055 if (ret) {
3056 dev_err(&adev->dev, "Couldn't deassert the device from OCP reset!\n");
3057 return ret;
3058 }
3059 }
3060
3061 for (i = 0; i < AMBA_NR_IRQS; i++) {
3062 irq = adev->irq[i];
3063 if (irq) {
3064 ret = devm_request_irq(&adev->dev, irq,
3065 pl330_irq_handler, 0,
3066 dev_name(&adev->dev), pl330);
3067 if (ret)
3068 return ret;
3069 } else {
3070 break;
3071 }
3072 }
3073
3074 pcfg = &pl330->pcfg;
3075
3076 pcfg->periph_id = adev->periphid;
3077 ret = pl330_add(pl330);
3078 if (ret)
3079 return ret;
3080
3081 INIT_LIST_HEAD(&pl330->desc_pool);
3082 spin_lock_init(&pl330->pool_lock);
3083
3084 /* Create a descriptor pool of default size */
3085 if (!add_desc(&pl330->desc_pool, &pl330->pool_lock,
3086 GFP_KERNEL, NR_DEFAULT_DESC))
3087 dev_warn(&adev->dev, "unable to allocate desc\n");
3088
3089 INIT_LIST_HEAD(&pd->channels);
3090
3091 /* Initialize channel parameters */
3092 num_chan = max_t(int, pcfg->num_peri, pcfg->num_chan);
3093
3094 pl330->num_peripherals = num_chan;
3095
3096 pl330->peripherals = kcalloc(num_chan, sizeof(*pch), GFP_KERNEL);
3097 if (!pl330->peripherals) {
3098 ret = -ENOMEM;
3099 goto probe_err2;
3100 }
3101
3102 for (i = 0; i < num_chan; i++) {
3103 pch = &pl330->peripherals[i];
3104
3105 pch->chan.private = adev->dev.of_node;
3106 INIT_LIST_HEAD(&pch->submitted_list);
3107 INIT_LIST_HEAD(&pch->work_list);
3108 INIT_LIST_HEAD(&pch->completed_list);
3109 spin_lock_init(&pch->lock);
3110 pch->thread = NULL;
3111 pch->chan.device = pd;
3112 pch->dmac = pl330;
3113 pch->dir = DMA_NONE;
3114
3115 /* Add the channel to the DMAC list */
3116 list_add_tail(&pch->chan.device_node, &pd->channels);
3117 }
3118
3119 dma_cap_set(DMA_MEMCPY, pd->cap_mask);
3120 if (pcfg->num_peri) {
3121 dma_cap_set(DMA_SLAVE, pd->cap_mask);
3122 dma_cap_set(DMA_CYCLIC, pd->cap_mask);
3123 dma_cap_set(DMA_PRIVATE, pd->cap_mask);
3124 }
3125
3126 pd->device_alloc_chan_resources = pl330_alloc_chan_resources;
3127 pd->device_free_chan_resources = pl330_free_chan_resources;
3128 pd->device_prep_dma_memcpy = pl330_prep_dma_memcpy;
3129 pd->device_prep_dma_cyclic = pl330_prep_dma_cyclic;
3130 pd->device_tx_status = pl330_tx_status;
3131 pd->device_prep_slave_sg = pl330_prep_slave_sg;
3132 pd->device_config = pl330_config;
3133 pd->device_pause = pl330_pause;
3134 pd->device_terminate_all = pl330_terminate_all;
3135 pd->device_issue_pending = pl330_issue_pending;
3136 pd->src_addr_widths = PL330_DMA_BUSWIDTHS;
3137 pd->dst_addr_widths = PL330_DMA_BUSWIDTHS;
3138 pd->directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV);
3139 pd->residue_granularity = DMA_RESIDUE_GRANULARITY_BURST;
3140 pd->max_burst = PL330_MAX_BURST;
3141
3142 ret = dma_async_device_register(pd);
3143 if (ret) {
3144 dev_err(&adev->dev, "unable to register DMAC\n");
3145 goto probe_err3;
3146 }
3147
3148 if (adev->dev.of_node) {
3149 ret = of_dma_controller_register(adev->dev.of_node,
3150 of_dma_pl330_xlate, pl330);
3151 if (ret) {
3152 dev_err(&adev->dev,
3153 "unable to register DMA to the generic DT DMA helpers\n");
3154 }
3155 }
3156
3157 adev->dev.dma_parms = &pl330->dma_parms;
3158
3159 /*
3160 * This is the limit for transfers with a buswidth of 1, larger
3161 * buswidths will have larger limits.
3162 */
3163 ret = dma_set_max_seg_size(&adev->dev, 1900800);
3164 if (ret)
3165 dev_err(&adev->dev, "unable to set the seg size\n");
3166
3167
3168 init_pl330_debugfs(pl330);
3169 dev_info(&adev->dev,
3170 "Loaded driver for PL330 DMAC-%x\n", adev->periphid);
3171 dev_info(&adev->dev,
3172 "\tDBUFF-%ux%ubytes Num_Chans-%u Num_Peri-%u Num_Events-%u\n",
3173 pcfg->data_buf_dep, pcfg->data_bus_width / 8, pcfg->num_chan,
3174 pcfg->num_peri, pcfg->num_events);
3175
3176 pm_runtime_irq_safe(&adev->dev);
3177 pm_runtime_use_autosuspend(&adev->dev);
3178 pm_runtime_set_autosuspend_delay(&adev->dev, PL330_AUTOSUSPEND_DELAY);
3179 pm_runtime_mark_last_busy(&adev->dev);
3180 pm_runtime_put_autosuspend(&adev->dev);
3181
3182 return 0;
3183probe_err3:
3184 /* Idle the DMAC */
3185 list_for_each_entry_safe(pch, _p, &pl330->ddma.channels,
3186 chan.device_node) {
3187
3188 /* Remove the channel */
3189 list_del(&pch->chan.device_node);
3190
3191 /* Flush the channel */
3192 if (pch->thread) {
3193 pl330_terminate_all(&pch->chan);
3194 pl330_free_chan_resources(&pch->chan);
3195 }
3196 }
3197probe_err2:
3198 pl330_del(pl330);
3199
3200 if (pl330->rstc_ocp)
3201 reset_control_assert(pl330->rstc_ocp);
3202
3203 if (pl330->rstc)
3204 reset_control_assert(pl330->rstc);
3205 return ret;
3206}
3207
3208static int pl330_remove(struct amba_device *adev)
3209{
3210 struct pl330_dmac *pl330 = amba_get_drvdata(adev);
3211 struct dma_pl330_chan *pch, *_p;
3212 int i, irq;
3213
3214 pm_runtime_get_noresume(pl330->ddma.dev);
3215
3216 if (adev->dev.of_node)
3217 of_dma_controller_free(adev->dev.of_node);
3218
3219 for (i = 0; i < AMBA_NR_IRQS; i++) {
3220 irq = adev->irq[i];
3221 if (irq)
3222 devm_free_irq(&adev->dev, irq, pl330);
3223 }
3224
3225 dma_async_device_unregister(&pl330->ddma);
3226
3227 /* Idle the DMAC */
3228 list_for_each_entry_safe(pch, _p, &pl330->ddma.channels,
3229 chan.device_node) {
3230
3231 /* Remove the channel */
3232 list_del(&pch->chan.device_node);
3233
3234 /* Flush the channel */
3235 if (pch->thread) {
3236 pl330_terminate_all(&pch->chan);
3237 pl330_free_chan_resources(&pch->chan);
3238 }
3239 }
3240
3241 pl330_del(pl330);
3242
3243 if (pl330->rstc_ocp)
3244 reset_control_assert(pl330->rstc_ocp);
3245
3246 if (pl330->rstc)
3247 reset_control_assert(pl330->rstc);
3248 return 0;
3249}
3250
3251static const struct amba_id pl330_ids[] = {
3252 {
3253 .id = 0x00041330,
3254 .mask = 0x000fffff,
3255 },
3256 { 0, 0 },
3257};
3258
3259MODULE_DEVICE_TABLE(amba, pl330_ids);
3260
3261static struct amba_driver pl330_driver = {
3262 .drv = {
3263 .owner = THIS_MODULE,
3264 .name = "dma-pl330",
3265 .pm = &pl330_pm,
3266 },
3267 .id_table = pl330_ids,
3268 .probe = pl330_probe,
3269 .remove = pl330_remove,
3270};
3271
3272module_amba_driver(pl330_driver);
3273
3274MODULE_AUTHOR("Jaswinder Singh <jassisinghbrar@gmail.com>");
3275MODULE_DESCRIPTION("API Driver for PL330 DMAC");
3276MODULE_LICENSE("GPL");
1/*
2 * Copyright (c) 2012 Samsung Electronics Co., Ltd.
3 * http://www.samsung.com
4 *
5 * Copyright (C) 2010 Samsung Electronics Co. Ltd.
6 * Jaswinder Singh <jassi.brar@samsung.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 */
13
14#include <linux/kernel.h>
15#include <linux/io.h>
16#include <linux/init.h>
17#include <linux/slab.h>
18#include <linux/module.h>
19#include <linux/string.h>
20#include <linux/delay.h>
21#include <linux/interrupt.h>
22#include <linux/dma-mapping.h>
23#include <linux/dmaengine.h>
24#include <linux/amba/bus.h>
25#include <linux/amba/pl330.h>
26#include <linux/scatterlist.h>
27#include <linux/of.h>
28#include <linux/of_dma.h>
29#include <linux/err.h>
30#include <linux/pm_runtime.h>
31
32#include "dmaengine.h"
33#define PL330_MAX_CHAN 8
34#define PL330_MAX_IRQS 32
35#define PL330_MAX_PERI 32
36#define PL330_MAX_BURST 16
37
38#define PL330_QUIRK_BROKEN_NO_FLUSHP BIT(0)
39
40enum pl330_cachectrl {
41 CCTRL0, /* Noncacheable and nonbufferable */
42 CCTRL1, /* Bufferable only */
43 CCTRL2, /* Cacheable, but do not allocate */
44 CCTRL3, /* Cacheable and bufferable, but do not allocate */
45 INVALID1, /* AWCACHE = 0x1000 */
46 INVALID2,
47 CCTRL6, /* Cacheable write-through, allocate on writes only */
48 CCTRL7, /* Cacheable write-back, allocate on writes only */
49};
50
51enum pl330_byteswap {
52 SWAP_NO,
53 SWAP_2,
54 SWAP_4,
55 SWAP_8,
56 SWAP_16,
57};
58
59/* Register and Bit field Definitions */
60#define DS 0x0
61#define DS_ST_STOP 0x0
62#define DS_ST_EXEC 0x1
63#define DS_ST_CMISS 0x2
64#define DS_ST_UPDTPC 0x3
65#define DS_ST_WFE 0x4
66#define DS_ST_ATBRR 0x5
67#define DS_ST_QBUSY 0x6
68#define DS_ST_WFP 0x7
69#define DS_ST_KILL 0x8
70#define DS_ST_CMPLT 0x9
71#define DS_ST_FLTCMP 0xe
72#define DS_ST_FAULT 0xf
73
74#define DPC 0x4
75#define INTEN 0x20
76#define ES 0x24
77#define INTSTATUS 0x28
78#define INTCLR 0x2c
79#define FSM 0x30
80#define FSC 0x34
81#define FTM 0x38
82
83#define _FTC 0x40
84#define FTC(n) (_FTC + (n)*0x4)
85
86#define _CS 0x100
87#define CS(n) (_CS + (n)*0x8)
88#define CS_CNS (1 << 21)
89
90#define _CPC 0x104
91#define CPC(n) (_CPC + (n)*0x8)
92
93#define _SA 0x400
94#define SA(n) (_SA + (n)*0x20)
95
96#define _DA 0x404
97#define DA(n) (_DA + (n)*0x20)
98
99#define _CC 0x408
100#define CC(n) (_CC + (n)*0x20)
101
102#define CC_SRCINC (1 << 0)
103#define CC_DSTINC (1 << 14)
104#define CC_SRCPRI (1 << 8)
105#define CC_DSTPRI (1 << 22)
106#define CC_SRCNS (1 << 9)
107#define CC_DSTNS (1 << 23)
108#define CC_SRCIA (1 << 10)
109#define CC_DSTIA (1 << 24)
110#define CC_SRCBRSTLEN_SHFT 4
111#define CC_DSTBRSTLEN_SHFT 18
112#define CC_SRCBRSTSIZE_SHFT 1
113#define CC_DSTBRSTSIZE_SHFT 15
114#define CC_SRCCCTRL_SHFT 11
115#define CC_SRCCCTRL_MASK 0x7
116#define CC_DSTCCTRL_SHFT 25
117#define CC_DRCCCTRL_MASK 0x7
118#define CC_SWAP_SHFT 28
119
120#define _LC0 0x40c
121#define LC0(n) (_LC0 + (n)*0x20)
122
123#define _LC1 0x410
124#define LC1(n) (_LC1 + (n)*0x20)
125
126#define DBGSTATUS 0xd00
127#define DBG_BUSY (1 << 0)
128
129#define DBGCMD 0xd04
130#define DBGINST0 0xd08
131#define DBGINST1 0xd0c
132
133#define CR0 0xe00
134#define CR1 0xe04
135#define CR2 0xe08
136#define CR3 0xe0c
137#define CR4 0xe10
138#define CRD 0xe14
139
140#define PERIPH_ID 0xfe0
141#define PERIPH_REV_SHIFT 20
142#define PERIPH_REV_MASK 0xf
143#define PERIPH_REV_R0P0 0
144#define PERIPH_REV_R1P0 1
145#define PERIPH_REV_R1P1 2
146
147#define CR0_PERIPH_REQ_SET (1 << 0)
148#define CR0_BOOT_EN_SET (1 << 1)
149#define CR0_BOOT_MAN_NS (1 << 2)
150#define CR0_NUM_CHANS_SHIFT 4
151#define CR0_NUM_CHANS_MASK 0x7
152#define CR0_NUM_PERIPH_SHIFT 12
153#define CR0_NUM_PERIPH_MASK 0x1f
154#define CR0_NUM_EVENTS_SHIFT 17
155#define CR0_NUM_EVENTS_MASK 0x1f
156
157#define CR1_ICACHE_LEN_SHIFT 0
158#define CR1_ICACHE_LEN_MASK 0x7
159#define CR1_NUM_ICACHELINES_SHIFT 4
160#define CR1_NUM_ICACHELINES_MASK 0xf
161
162#define CRD_DATA_WIDTH_SHIFT 0
163#define CRD_DATA_WIDTH_MASK 0x7
164#define CRD_WR_CAP_SHIFT 4
165#define CRD_WR_CAP_MASK 0x7
166#define CRD_WR_Q_DEP_SHIFT 8
167#define CRD_WR_Q_DEP_MASK 0xf
168#define CRD_RD_CAP_SHIFT 12
169#define CRD_RD_CAP_MASK 0x7
170#define CRD_RD_Q_DEP_SHIFT 16
171#define CRD_RD_Q_DEP_MASK 0xf
172#define CRD_DATA_BUFF_SHIFT 20
173#define CRD_DATA_BUFF_MASK 0x3ff
174
175#define PART 0x330
176#define DESIGNER 0x41
177#define REVISION 0x0
178#define INTEG_CFG 0x0
179#define PERIPH_ID_VAL ((PART << 0) | (DESIGNER << 12))
180
181#define PL330_STATE_STOPPED (1 << 0)
182#define PL330_STATE_EXECUTING (1 << 1)
183#define PL330_STATE_WFE (1 << 2)
184#define PL330_STATE_FAULTING (1 << 3)
185#define PL330_STATE_COMPLETING (1 << 4)
186#define PL330_STATE_WFP (1 << 5)
187#define PL330_STATE_KILLING (1 << 6)
188#define PL330_STATE_FAULT_COMPLETING (1 << 7)
189#define PL330_STATE_CACHEMISS (1 << 8)
190#define PL330_STATE_UPDTPC (1 << 9)
191#define PL330_STATE_ATBARRIER (1 << 10)
192#define PL330_STATE_QUEUEBUSY (1 << 11)
193#define PL330_STATE_INVALID (1 << 15)
194
195#define PL330_STABLE_STATES (PL330_STATE_STOPPED | PL330_STATE_EXECUTING \
196 | PL330_STATE_WFE | PL330_STATE_FAULTING)
197
198#define CMD_DMAADDH 0x54
199#define CMD_DMAEND 0x00
200#define CMD_DMAFLUSHP 0x35
201#define CMD_DMAGO 0xa0
202#define CMD_DMALD 0x04
203#define CMD_DMALDP 0x25
204#define CMD_DMALP 0x20
205#define CMD_DMALPEND 0x28
206#define CMD_DMAKILL 0x01
207#define CMD_DMAMOV 0xbc
208#define CMD_DMANOP 0x18
209#define CMD_DMARMB 0x12
210#define CMD_DMASEV 0x34
211#define CMD_DMAST 0x08
212#define CMD_DMASTP 0x29
213#define CMD_DMASTZ 0x0c
214#define CMD_DMAWFE 0x36
215#define CMD_DMAWFP 0x30
216#define CMD_DMAWMB 0x13
217
218#define SZ_DMAADDH 3
219#define SZ_DMAEND 1
220#define SZ_DMAFLUSHP 2
221#define SZ_DMALD 1
222#define SZ_DMALDP 2
223#define SZ_DMALP 2
224#define SZ_DMALPEND 2
225#define SZ_DMAKILL 1
226#define SZ_DMAMOV 6
227#define SZ_DMANOP 1
228#define SZ_DMARMB 1
229#define SZ_DMASEV 2
230#define SZ_DMAST 1
231#define SZ_DMASTP 2
232#define SZ_DMASTZ 1
233#define SZ_DMAWFE 2
234#define SZ_DMAWFP 2
235#define SZ_DMAWMB 1
236#define SZ_DMAGO 6
237
238#define BRST_LEN(ccr) ((((ccr) >> CC_SRCBRSTLEN_SHFT) & 0xf) + 1)
239#define BRST_SIZE(ccr) (1 << (((ccr) >> CC_SRCBRSTSIZE_SHFT) & 0x7))
240
241#define BYTE_TO_BURST(b, ccr) ((b) / BRST_SIZE(ccr) / BRST_LEN(ccr))
242#define BURST_TO_BYTE(c, ccr) ((c) * BRST_SIZE(ccr) * BRST_LEN(ccr))
243
244/*
245 * With 256 bytes, we can do more than 2.5MB and 5MB xfers per req
246 * at 1byte/burst for P<->M and M<->M respectively.
247 * For typical scenario, at 1word/burst, 10MB and 20MB xfers per req
248 * should be enough for P<->M and M<->M respectively.
249 */
250#define MCODE_BUFF_PER_REQ 256
251
252/* Use this _only_ to wait on transient states */
253#define UNTIL(t, s) while (!(_state(t) & (s))) cpu_relax();
254
255#ifdef PL330_DEBUG_MCGEN
256static unsigned cmd_line;
257#define PL330_DBGCMD_DUMP(off, x...) do { \
258 printk("%x:", cmd_line); \
259 printk(x); \
260 cmd_line += off; \
261 } while (0)
262#define PL330_DBGMC_START(addr) (cmd_line = addr)
263#else
264#define PL330_DBGCMD_DUMP(off, x...) do {} while (0)
265#define PL330_DBGMC_START(addr) do {} while (0)
266#endif
267
268/* The number of default descriptors */
269
270#define NR_DEFAULT_DESC 16
271
272/* Delay for runtime PM autosuspend, ms */
273#define PL330_AUTOSUSPEND_DELAY 20
274
275/* Populated by the PL330 core driver for DMA API driver's info */
276struct pl330_config {
277 u32 periph_id;
278#define DMAC_MODE_NS (1 << 0)
279 unsigned int mode;
280 unsigned int data_bus_width:10; /* In number of bits */
281 unsigned int data_buf_dep:11;
282 unsigned int num_chan:4;
283 unsigned int num_peri:6;
284 u32 peri_ns;
285 unsigned int num_events:6;
286 u32 irq_ns;
287};
288
289/**
290 * Request Configuration.
291 * The PL330 core does not modify this and uses the last
292 * working configuration if the request doesn't provide any.
293 *
294 * The Client may want to provide this info only for the
295 * first request and a request with new settings.
296 */
297struct pl330_reqcfg {
298 /* Address Incrementing */
299 unsigned dst_inc:1;
300 unsigned src_inc:1;
301
302 /*
303 * For now, the SRC & DST protection levels
304 * and burst size/length are assumed same.
305 */
306 bool nonsecure;
307 bool privileged;
308 bool insnaccess;
309 unsigned brst_len:5;
310 unsigned brst_size:3; /* in power of 2 */
311
312 enum pl330_cachectrl dcctl;
313 enum pl330_cachectrl scctl;
314 enum pl330_byteswap swap;
315 struct pl330_config *pcfg;
316};
317
318/*
319 * One cycle of DMAC operation.
320 * There may be more than one xfer in a request.
321 */
322struct pl330_xfer {
323 u32 src_addr;
324 u32 dst_addr;
325 /* Size to xfer */
326 u32 bytes;
327};
328
329/* The xfer callbacks are made with one of these arguments. */
330enum pl330_op_err {
331 /* The all xfers in the request were success. */
332 PL330_ERR_NONE,
333 /* If req aborted due to global error. */
334 PL330_ERR_ABORT,
335 /* If req failed due to problem with Channel. */
336 PL330_ERR_FAIL,
337};
338
339enum dmamov_dst {
340 SAR = 0,
341 CCR,
342 DAR,
343};
344
345enum pl330_dst {
346 SRC = 0,
347 DST,
348};
349
350enum pl330_cond {
351 SINGLE,
352 BURST,
353 ALWAYS,
354};
355
356struct dma_pl330_desc;
357
358struct _pl330_req {
359 u32 mc_bus;
360 void *mc_cpu;
361 struct dma_pl330_desc *desc;
362};
363
364/* ToBeDone for tasklet */
365struct _pl330_tbd {
366 bool reset_dmac;
367 bool reset_mngr;
368 u8 reset_chan;
369};
370
371/* A DMAC Thread */
372struct pl330_thread {
373 u8 id;
374 int ev;
375 /* If the channel is not yet acquired by any client */
376 bool free;
377 /* Parent DMAC */
378 struct pl330_dmac *dmac;
379 /* Only two at a time */
380 struct _pl330_req req[2];
381 /* Index of the last enqueued request */
382 unsigned lstenq;
383 /* Index of the last submitted request or -1 if the DMA is stopped */
384 int req_running;
385};
386
387enum pl330_dmac_state {
388 UNINIT,
389 INIT,
390 DYING,
391};
392
393enum desc_status {
394 /* In the DMAC pool */
395 FREE,
396 /*
397 * Allocated to some channel during prep_xxx
398 * Also may be sitting on the work_list.
399 */
400 PREP,
401 /*
402 * Sitting on the work_list and already submitted
403 * to the PL330 core. Not more than two descriptors
404 * of a channel can be BUSY at any time.
405 */
406 BUSY,
407 /*
408 * Sitting on the channel work_list but xfer done
409 * by PL330 core
410 */
411 DONE,
412};
413
414struct dma_pl330_chan {
415 /* Schedule desc completion */
416 struct tasklet_struct task;
417
418 /* DMA-Engine Channel */
419 struct dma_chan chan;
420
421 /* List of submitted descriptors */
422 struct list_head submitted_list;
423 /* List of issued descriptors */
424 struct list_head work_list;
425 /* List of completed descriptors */
426 struct list_head completed_list;
427
428 /* Pointer to the DMAC that manages this channel,
429 * NULL if the channel is available to be acquired.
430 * As the parent, this DMAC also provides descriptors
431 * to the channel.
432 */
433 struct pl330_dmac *dmac;
434
435 /* To protect channel manipulation */
436 spinlock_t lock;
437
438 /*
439 * Hardware channel thread of PL330 DMAC. NULL if the channel is
440 * available.
441 */
442 struct pl330_thread *thread;
443
444 /* For D-to-M and M-to-D channels */
445 int burst_sz; /* the peripheral fifo width */
446 int burst_len; /* the number of burst */
447 dma_addr_t fifo_addr;
448
449 /* for cyclic capability */
450 bool cyclic;
451
452 /* for runtime pm tracking */
453 bool active;
454};
455
456struct pl330_dmac {
457 /* DMA-Engine Device */
458 struct dma_device ddma;
459
460 /* Holds info about sg limitations */
461 struct device_dma_parameters dma_parms;
462
463 /* Pool of descriptors available for the DMAC's channels */
464 struct list_head desc_pool;
465 /* To protect desc_pool manipulation */
466 spinlock_t pool_lock;
467
468 /* Size of MicroCode buffers for each channel. */
469 unsigned mcbufsz;
470 /* ioremap'ed address of PL330 registers. */
471 void __iomem *base;
472 /* Populated by the PL330 core driver during pl330_add */
473 struct pl330_config pcfg;
474
475 spinlock_t lock;
476 /* Maximum possible events/irqs */
477 int events[32];
478 /* BUS address of MicroCode buffer */
479 dma_addr_t mcode_bus;
480 /* CPU address of MicroCode buffer */
481 void *mcode_cpu;
482 /* List of all Channel threads */
483 struct pl330_thread *channels;
484 /* Pointer to the MANAGER thread */
485 struct pl330_thread *manager;
486 /* To handle bad news in interrupt */
487 struct tasklet_struct tasks;
488 struct _pl330_tbd dmac_tbd;
489 /* State of DMAC operation */
490 enum pl330_dmac_state state;
491 /* Holds list of reqs with due callbacks */
492 struct list_head req_done;
493
494 /* Peripheral channels connected to this DMAC */
495 unsigned int num_peripherals;
496 struct dma_pl330_chan *peripherals; /* keep at end */
497 int quirks;
498};
499
500static struct pl330_of_quirks {
501 char *quirk;
502 int id;
503} of_quirks[] = {
504 {
505 .quirk = "arm,pl330-broken-no-flushp",
506 .id = PL330_QUIRK_BROKEN_NO_FLUSHP,
507 }
508};
509
510struct dma_pl330_desc {
511 /* To attach to a queue as child */
512 struct list_head node;
513
514 /* Descriptor for the DMA Engine API */
515 struct dma_async_tx_descriptor txd;
516
517 /* Xfer for PL330 core */
518 struct pl330_xfer px;
519
520 struct pl330_reqcfg rqcfg;
521
522 enum desc_status status;
523
524 int bytes_requested;
525 bool last;
526
527 /* The channel which currently holds this desc */
528 struct dma_pl330_chan *pchan;
529
530 enum dma_transfer_direction rqtype;
531 /* Index of peripheral for the xfer. */
532 unsigned peri:5;
533 /* Hook to attach to DMAC's list of reqs with due callback */
534 struct list_head rqd;
535};
536
537struct _xfer_spec {
538 u32 ccr;
539 struct dma_pl330_desc *desc;
540};
541
542static inline bool _queue_empty(struct pl330_thread *thrd)
543{
544 return thrd->req[0].desc == NULL && thrd->req[1].desc == NULL;
545}
546
547static inline bool _queue_full(struct pl330_thread *thrd)
548{
549 return thrd->req[0].desc != NULL && thrd->req[1].desc != NULL;
550}
551
552static inline bool is_manager(struct pl330_thread *thrd)
553{
554 return thrd->dmac->manager == thrd;
555}
556
557/* If manager of the thread is in Non-Secure mode */
558static inline bool _manager_ns(struct pl330_thread *thrd)
559{
560 return (thrd->dmac->pcfg.mode & DMAC_MODE_NS) ? true : false;
561}
562
563static inline u32 get_revision(u32 periph_id)
564{
565 return (periph_id >> PERIPH_REV_SHIFT) & PERIPH_REV_MASK;
566}
567
568static inline u32 _emit_ADDH(unsigned dry_run, u8 buf[],
569 enum pl330_dst da, u16 val)
570{
571 if (dry_run)
572 return SZ_DMAADDH;
573
574 buf[0] = CMD_DMAADDH;
575 buf[0] |= (da << 1);
576 buf[1] = val;
577 buf[2] = val >> 8;
578
579 PL330_DBGCMD_DUMP(SZ_DMAADDH, "\tDMAADDH %s %u\n",
580 da == 1 ? "DA" : "SA", val);
581
582 return SZ_DMAADDH;
583}
584
585static inline u32 _emit_END(unsigned dry_run, u8 buf[])
586{
587 if (dry_run)
588 return SZ_DMAEND;
589
590 buf[0] = CMD_DMAEND;
591
592 PL330_DBGCMD_DUMP(SZ_DMAEND, "\tDMAEND\n");
593
594 return SZ_DMAEND;
595}
596
597static inline u32 _emit_FLUSHP(unsigned dry_run, u8 buf[], u8 peri)
598{
599 if (dry_run)
600 return SZ_DMAFLUSHP;
601
602 buf[0] = CMD_DMAFLUSHP;
603
604 peri &= 0x1f;
605 peri <<= 3;
606 buf[1] = peri;
607
608 PL330_DBGCMD_DUMP(SZ_DMAFLUSHP, "\tDMAFLUSHP %u\n", peri >> 3);
609
610 return SZ_DMAFLUSHP;
611}
612
613static inline u32 _emit_LD(unsigned dry_run, u8 buf[], enum pl330_cond cond)
614{
615 if (dry_run)
616 return SZ_DMALD;
617
618 buf[0] = CMD_DMALD;
619
620 if (cond == SINGLE)
621 buf[0] |= (0 << 1) | (1 << 0);
622 else if (cond == BURST)
623 buf[0] |= (1 << 1) | (1 << 0);
624
625 PL330_DBGCMD_DUMP(SZ_DMALD, "\tDMALD%c\n",
626 cond == SINGLE ? 'S' : (cond == BURST ? 'B' : 'A'));
627
628 return SZ_DMALD;
629}
630
631static inline u32 _emit_LDP(unsigned dry_run, u8 buf[],
632 enum pl330_cond cond, u8 peri)
633{
634 if (dry_run)
635 return SZ_DMALDP;
636
637 buf[0] = CMD_DMALDP;
638
639 if (cond == BURST)
640 buf[0] |= (1 << 1);
641
642 peri &= 0x1f;
643 peri <<= 3;
644 buf[1] = peri;
645
646 PL330_DBGCMD_DUMP(SZ_DMALDP, "\tDMALDP%c %u\n",
647 cond == SINGLE ? 'S' : 'B', peri >> 3);
648
649 return SZ_DMALDP;
650}
651
652static inline u32 _emit_LP(unsigned dry_run, u8 buf[],
653 unsigned loop, u8 cnt)
654{
655 if (dry_run)
656 return SZ_DMALP;
657
658 buf[0] = CMD_DMALP;
659
660 if (loop)
661 buf[0] |= (1 << 1);
662
663 cnt--; /* DMAC increments by 1 internally */
664 buf[1] = cnt;
665
666 PL330_DBGCMD_DUMP(SZ_DMALP, "\tDMALP_%c %u\n", loop ? '1' : '0', cnt);
667
668 return SZ_DMALP;
669}
670
671struct _arg_LPEND {
672 enum pl330_cond cond;
673 bool forever;
674 unsigned loop;
675 u8 bjump;
676};
677
678static inline u32 _emit_LPEND(unsigned dry_run, u8 buf[],
679 const struct _arg_LPEND *arg)
680{
681 enum pl330_cond cond = arg->cond;
682 bool forever = arg->forever;
683 unsigned loop = arg->loop;
684 u8 bjump = arg->bjump;
685
686 if (dry_run)
687 return SZ_DMALPEND;
688
689 buf[0] = CMD_DMALPEND;
690
691 if (loop)
692 buf[0] |= (1 << 2);
693
694 if (!forever)
695 buf[0] |= (1 << 4);
696
697 if (cond == SINGLE)
698 buf[0] |= (0 << 1) | (1 << 0);
699 else if (cond == BURST)
700 buf[0] |= (1 << 1) | (1 << 0);
701
702 buf[1] = bjump;
703
704 PL330_DBGCMD_DUMP(SZ_DMALPEND, "\tDMALP%s%c_%c bjmpto_%x\n",
705 forever ? "FE" : "END",
706 cond == SINGLE ? 'S' : (cond == BURST ? 'B' : 'A'),
707 loop ? '1' : '0',
708 bjump);
709
710 return SZ_DMALPEND;
711}
712
713static inline u32 _emit_KILL(unsigned dry_run, u8 buf[])
714{
715 if (dry_run)
716 return SZ_DMAKILL;
717
718 buf[0] = CMD_DMAKILL;
719
720 return SZ_DMAKILL;
721}
722
723static inline u32 _emit_MOV(unsigned dry_run, u8 buf[],
724 enum dmamov_dst dst, u32 val)
725{
726 if (dry_run)
727 return SZ_DMAMOV;
728
729 buf[0] = CMD_DMAMOV;
730 buf[1] = dst;
731 buf[2] = val;
732 buf[3] = val >> 8;
733 buf[4] = val >> 16;
734 buf[5] = val >> 24;
735
736 PL330_DBGCMD_DUMP(SZ_DMAMOV, "\tDMAMOV %s 0x%x\n",
737 dst == SAR ? "SAR" : (dst == DAR ? "DAR" : "CCR"), val);
738
739 return SZ_DMAMOV;
740}
741
742static inline u32 _emit_NOP(unsigned dry_run, u8 buf[])
743{
744 if (dry_run)
745 return SZ_DMANOP;
746
747 buf[0] = CMD_DMANOP;
748
749 PL330_DBGCMD_DUMP(SZ_DMANOP, "\tDMANOP\n");
750
751 return SZ_DMANOP;
752}
753
754static inline u32 _emit_RMB(unsigned dry_run, u8 buf[])
755{
756 if (dry_run)
757 return SZ_DMARMB;
758
759 buf[0] = CMD_DMARMB;
760
761 PL330_DBGCMD_DUMP(SZ_DMARMB, "\tDMARMB\n");
762
763 return SZ_DMARMB;
764}
765
766static inline u32 _emit_SEV(unsigned dry_run, u8 buf[], u8 ev)
767{
768 if (dry_run)
769 return SZ_DMASEV;
770
771 buf[0] = CMD_DMASEV;
772
773 ev &= 0x1f;
774 ev <<= 3;
775 buf[1] = ev;
776
777 PL330_DBGCMD_DUMP(SZ_DMASEV, "\tDMASEV %u\n", ev >> 3);
778
779 return SZ_DMASEV;
780}
781
782static inline u32 _emit_ST(unsigned dry_run, u8 buf[], enum pl330_cond cond)
783{
784 if (dry_run)
785 return SZ_DMAST;
786
787 buf[0] = CMD_DMAST;
788
789 if (cond == SINGLE)
790 buf[0] |= (0 << 1) | (1 << 0);
791 else if (cond == BURST)
792 buf[0] |= (1 << 1) | (1 << 0);
793
794 PL330_DBGCMD_DUMP(SZ_DMAST, "\tDMAST%c\n",
795 cond == SINGLE ? 'S' : (cond == BURST ? 'B' : 'A'));
796
797 return SZ_DMAST;
798}
799
800static inline u32 _emit_STP(unsigned dry_run, u8 buf[],
801 enum pl330_cond cond, u8 peri)
802{
803 if (dry_run)
804 return SZ_DMASTP;
805
806 buf[0] = CMD_DMASTP;
807
808 if (cond == BURST)
809 buf[0] |= (1 << 1);
810
811 peri &= 0x1f;
812 peri <<= 3;
813 buf[1] = peri;
814
815 PL330_DBGCMD_DUMP(SZ_DMASTP, "\tDMASTP%c %u\n",
816 cond == SINGLE ? 'S' : 'B', peri >> 3);
817
818 return SZ_DMASTP;
819}
820
821static inline u32 _emit_STZ(unsigned dry_run, u8 buf[])
822{
823 if (dry_run)
824 return SZ_DMASTZ;
825
826 buf[0] = CMD_DMASTZ;
827
828 PL330_DBGCMD_DUMP(SZ_DMASTZ, "\tDMASTZ\n");
829
830 return SZ_DMASTZ;
831}
832
833static inline u32 _emit_WFE(unsigned dry_run, u8 buf[], u8 ev,
834 unsigned invalidate)
835{
836 if (dry_run)
837 return SZ_DMAWFE;
838
839 buf[0] = CMD_DMAWFE;
840
841 ev &= 0x1f;
842 ev <<= 3;
843 buf[1] = ev;
844
845 if (invalidate)
846 buf[1] |= (1 << 1);
847
848 PL330_DBGCMD_DUMP(SZ_DMAWFE, "\tDMAWFE %u%s\n",
849 ev >> 3, invalidate ? ", I" : "");
850
851 return SZ_DMAWFE;
852}
853
854static inline u32 _emit_WFP(unsigned dry_run, u8 buf[],
855 enum pl330_cond cond, u8 peri)
856{
857 if (dry_run)
858 return SZ_DMAWFP;
859
860 buf[0] = CMD_DMAWFP;
861
862 if (cond == SINGLE)
863 buf[0] |= (0 << 1) | (0 << 0);
864 else if (cond == BURST)
865 buf[0] |= (1 << 1) | (0 << 0);
866 else
867 buf[0] |= (0 << 1) | (1 << 0);
868
869 peri &= 0x1f;
870 peri <<= 3;
871 buf[1] = peri;
872
873 PL330_DBGCMD_DUMP(SZ_DMAWFP, "\tDMAWFP%c %u\n",
874 cond == SINGLE ? 'S' : (cond == BURST ? 'B' : 'P'), peri >> 3);
875
876 return SZ_DMAWFP;
877}
878
879static inline u32 _emit_WMB(unsigned dry_run, u8 buf[])
880{
881 if (dry_run)
882 return SZ_DMAWMB;
883
884 buf[0] = CMD_DMAWMB;
885
886 PL330_DBGCMD_DUMP(SZ_DMAWMB, "\tDMAWMB\n");
887
888 return SZ_DMAWMB;
889}
890
891struct _arg_GO {
892 u8 chan;
893 u32 addr;
894 unsigned ns;
895};
896
897static inline u32 _emit_GO(unsigned dry_run, u8 buf[],
898 const struct _arg_GO *arg)
899{
900 u8 chan = arg->chan;
901 u32 addr = arg->addr;
902 unsigned ns = arg->ns;
903
904 if (dry_run)
905 return SZ_DMAGO;
906
907 buf[0] = CMD_DMAGO;
908 buf[0] |= (ns << 1);
909 buf[1] = chan & 0x7;
910 buf[2] = addr;
911 buf[3] = addr >> 8;
912 buf[4] = addr >> 16;
913 buf[5] = addr >> 24;
914
915 return SZ_DMAGO;
916}
917
918#define msecs_to_loops(t) (loops_per_jiffy / 1000 * HZ * t)
919
920/* Returns Time-Out */
921static bool _until_dmac_idle(struct pl330_thread *thrd)
922{
923 void __iomem *regs = thrd->dmac->base;
924 unsigned long loops = msecs_to_loops(5);
925
926 do {
927 /* Until Manager is Idle */
928 if (!(readl(regs + DBGSTATUS) & DBG_BUSY))
929 break;
930
931 cpu_relax();
932 } while (--loops);
933
934 if (!loops)
935 return true;
936
937 return false;
938}
939
940static inline void _execute_DBGINSN(struct pl330_thread *thrd,
941 u8 insn[], bool as_manager)
942{
943 void __iomem *regs = thrd->dmac->base;
944 u32 val;
945
946 val = (insn[0] << 16) | (insn[1] << 24);
947 if (!as_manager) {
948 val |= (1 << 0);
949 val |= (thrd->id << 8); /* Channel Number */
950 }
951 writel(val, regs + DBGINST0);
952
953 val = le32_to_cpu(*((__le32 *)&insn[2]));
954 writel(val, regs + DBGINST1);
955
956 /* If timed out due to halted state-machine */
957 if (_until_dmac_idle(thrd)) {
958 dev_err(thrd->dmac->ddma.dev, "DMAC halted!\n");
959 return;
960 }
961
962 /* Get going */
963 writel(0, regs + DBGCMD);
964}
965
966static inline u32 _state(struct pl330_thread *thrd)
967{
968 void __iomem *regs = thrd->dmac->base;
969 u32 val;
970
971 if (is_manager(thrd))
972 val = readl(regs + DS) & 0xf;
973 else
974 val = readl(regs + CS(thrd->id)) & 0xf;
975
976 switch (val) {
977 case DS_ST_STOP:
978 return PL330_STATE_STOPPED;
979 case DS_ST_EXEC:
980 return PL330_STATE_EXECUTING;
981 case DS_ST_CMISS:
982 return PL330_STATE_CACHEMISS;
983 case DS_ST_UPDTPC:
984 return PL330_STATE_UPDTPC;
985 case DS_ST_WFE:
986 return PL330_STATE_WFE;
987 case DS_ST_FAULT:
988 return PL330_STATE_FAULTING;
989 case DS_ST_ATBRR:
990 if (is_manager(thrd))
991 return PL330_STATE_INVALID;
992 else
993 return PL330_STATE_ATBARRIER;
994 case DS_ST_QBUSY:
995 if (is_manager(thrd))
996 return PL330_STATE_INVALID;
997 else
998 return PL330_STATE_QUEUEBUSY;
999 case DS_ST_WFP:
1000 if (is_manager(thrd))
1001 return PL330_STATE_INVALID;
1002 else
1003 return PL330_STATE_WFP;
1004 case DS_ST_KILL:
1005 if (is_manager(thrd))
1006 return PL330_STATE_INVALID;
1007 else
1008 return PL330_STATE_KILLING;
1009 case DS_ST_CMPLT:
1010 if (is_manager(thrd))
1011 return PL330_STATE_INVALID;
1012 else
1013 return PL330_STATE_COMPLETING;
1014 case DS_ST_FLTCMP:
1015 if (is_manager(thrd))
1016 return PL330_STATE_INVALID;
1017 else
1018 return PL330_STATE_FAULT_COMPLETING;
1019 default:
1020 return PL330_STATE_INVALID;
1021 }
1022}
1023
1024static void _stop(struct pl330_thread *thrd)
1025{
1026 void __iomem *regs = thrd->dmac->base;
1027 u8 insn[6] = {0, 0, 0, 0, 0, 0};
1028
1029 if (_state(thrd) == PL330_STATE_FAULT_COMPLETING)
1030 UNTIL(thrd, PL330_STATE_FAULTING | PL330_STATE_KILLING);
1031
1032 /* Return if nothing needs to be done */
1033 if (_state(thrd) == PL330_STATE_COMPLETING
1034 || _state(thrd) == PL330_STATE_KILLING
1035 || _state(thrd) == PL330_STATE_STOPPED)
1036 return;
1037
1038 _emit_KILL(0, insn);
1039
1040 /* Stop generating interrupts for SEV */
1041 writel(readl(regs + INTEN) & ~(1 << thrd->ev), regs + INTEN);
1042
1043 _execute_DBGINSN(thrd, insn, is_manager(thrd));
1044}
1045
1046/* Start doing req 'idx' of thread 'thrd' */
1047static bool _trigger(struct pl330_thread *thrd)
1048{
1049 void __iomem *regs = thrd->dmac->base;
1050 struct _pl330_req *req;
1051 struct dma_pl330_desc *desc;
1052 struct _arg_GO go;
1053 unsigned ns;
1054 u8 insn[6] = {0, 0, 0, 0, 0, 0};
1055 int idx;
1056
1057 /* Return if already ACTIVE */
1058 if (_state(thrd) != PL330_STATE_STOPPED)
1059 return true;
1060
1061 idx = 1 - thrd->lstenq;
1062 if (thrd->req[idx].desc != NULL) {
1063 req = &thrd->req[idx];
1064 } else {
1065 idx = thrd->lstenq;
1066 if (thrd->req[idx].desc != NULL)
1067 req = &thrd->req[idx];
1068 else
1069 req = NULL;
1070 }
1071
1072 /* Return if no request */
1073 if (!req)
1074 return true;
1075
1076 /* Return if req is running */
1077 if (idx == thrd->req_running)
1078 return true;
1079
1080 desc = req->desc;
1081
1082 ns = desc->rqcfg.nonsecure ? 1 : 0;
1083
1084 /* See 'Abort Sources' point-4 at Page 2-25 */
1085 if (_manager_ns(thrd) && !ns)
1086 dev_info(thrd->dmac->ddma.dev, "%s:%d Recipe for ABORT!\n",
1087 __func__, __LINE__);
1088
1089 go.chan = thrd->id;
1090 go.addr = req->mc_bus;
1091 go.ns = ns;
1092 _emit_GO(0, insn, &go);
1093
1094 /* Set to generate interrupts for SEV */
1095 writel(readl(regs + INTEN) | (1 << thrd->ev), regs + INTEN);
1096
1097 /* Only manager can execute GO */
1098 _execute_DBGINSN(thrd, insn, true);
1099
1100 thrd->req_running = idx;
1101
1102 return true;
1103}
1104
1105static bool _start(struct pl330_thread *thrd)
1106{
1107 switch (_state(thrd)) {
1108 case PL330_STATE_FAULT_COMPLETING:
1109 UNTIL(thrd, PL330_STATE_FAULTING | PL330_STATE_KILLING);
1110
1111 if (_state(thrd) == PL330_STATE_KILLING)
1112 UNTIL(thrd, PL330_STATE_STOPPED)
1113
1114 case PL330_STATE_FAULTING:
1115 _stop(thrd);
1116
1117 case PL330_STATE_KILLING:
1118 case PL330_STATE_COMPLETING:
1119 UNTIL(thrd, PL330_STATE_STOPPED)
1120
1121 case PL330_STATE_STOPPED:
1122 return _trigger(thrd);
1123
1124 case PL330_STATE_WFP:
1125 case PL330_STATE_QUEUEBUSY:
1126 case PL330_STATE_ATBARRIER:
1127 case PL330_STATE_UPDTPC:
1128 case PL330_STATE_CACHEMISS:
1129 case PL330_STATE_EXECUTING:
1130 return true;
1131
1132 case PL330_STATE_WFE: /* For RESUME, nothing yet */
1133 default:
1134 return false;
1135 }
1136}
1137
1138static inline int _ldst_memtomem(unsigned dry_run, u8 buf[],
1139 const struct _xfer_spec *pxs, int cyc)
1140{
1141 int off = 0;
1142 struct pl330_config *pcfg = pxs->desc->rqcfg.pcfg;
1143
1144 /* check lock-up free version */
1145 if (get_revision(pcfg->periph_id) >= PERIPH_REV_R1P0) {
1146 while (cyc--) {
1147 off += _emit_LD(dry_run, &buf[off], ALWAYS);
1148 off += _emit_ST(dry_run, &buf[off], ALWAYS);
1149 }
1150 } else {
1151 while (cyc--) {
1152 off += _emit_LD(dry_run, &buf[off], ALWAYS);
1153 off += _emit_RMB(dry_run, &buf[off]);
1154 off += _emit_ST(dry_run, &buf[off], ALWAYS);
1155 off += _emit_WMB(dry_run, &buf[off]);
1156 }
1157 }
1158
1159 return off;
1160}
1161
1162static inline int _ldst_devtomem(struct pl330_dmac *pl330, unsigned dry_run,
1163 u8 buf[], const struct _xfer_spec *pxs,
1164 int cyc)
1165{
1166 int off = 0;
1167 enum pl330_cond cond;
1168
1169 if (pl330->quirks & PL330_QUIRK_BROKEN_NO_FLUSHP)
1170 cond = BURST;
1171 else
1172 cond = SINGLE;
1173
1174 while (cyc--) {
1175 off += _emit_WFP(dry_run, &buf[off], cond, pxs->desc->peri);
1176 off += _emit_LDP(dry_run, &buf[off], cond, pxs->desc->peri);
1177 off += _emit_ST(dry_run, &buf[off], ALWAYS);
1178
1179 if (!(pl330->quirks & PL330_QUIRK_BROKEN_NO_FLUSHP))
1180 off += _emit_FLUSHP(dry_run, &buf[off],
1181 pxs->desc->peri);
1182 }
1183
1184 return off;
1185}
1186
1187static inline int _ldst_memtodev(struct pl330_dmac *pl330,
1188 unsigned dry_run, u8 buf[],
1189 const struct _xfer_spec *pxs, int cyc)
1190{
1191 int off = 0;
1192 enum pl330_cond cond;
1193
1194 if (pl330->quirks & PL330_QUIRK_BROKEN_NO_FLUSHP)
1195 cond = BURST;
1196 else
1197 cond = SINGLE;
1198
1199 while (cyc--) {
1200 off += _emit_WFP(dry_run, &buf[off], cond, pxs->desc->peri);
1201 off += _emit_LD(dry_run, &buf[off], ALWAYS);
1202 off += _emit_STP(dry_run, &buf[off], cond, pxs->desc->peri);
1203
1204 if (!(pl330->quirks & PL330_QUIRK_BROKEN_NO_FLUSHP))
1205 off += _emit_FLUSHP(dry_run, &buf[off],
1206 pxs->desc->peri);
1207 }
1208
1209 return off;
1210}
1211
1212static int _bursts(struct pl330_dmac *pl330, unsigned dry_run, u8 buf[],
1213 const struct _xfer_spec *pxs, int cyc)
1214{
1215 int off = 0;
1216
1217 switch (pxs->desc->rqtype) {
1218 case DMA_MEM_TO_DEV:
1219 off += _ldst_memtodev(pl330, dry_run, &buf[off], pxs, cyc);
1220 break;
1221 case DMA_DEV_TO_MEM:
1222 off += _ldst_devtomem(pl330, dry_run, &buf[off], pxs, cyc);
1223 break;
1224 case DMA_MEM_TO_MEM:
1225 off += _ldst_memtomem(dry_run, &buf[off], pxs, cyc);
1226 break;
1227 default:
1228 off += 0x40000000; /* Scare off the Client */
1229 break;
1230 }
1231
1232 return off;
1233}
1234
1235/* Returns bytes consumed and updates bursts */
1236static inline int _loop(struct pl330_dmac *pl330, unsigned dry_run, u8 buf[],
1237 unsigned long *bursts, const struct _xfer_spec *pxs)
1238{
1239 int cyc, cycmax, szlp, szlpend, szbrst, off;
1240 unsigned lcnt0, lcnt1, ljmp0, ljmp1;
1241 struct _arg_LPEND lpend;
1242
1243 if (*bursts == 1)
1244 return _bursts(pl330, dry_run, buf, pxs, 1);
1245
1246 /* Max iterations possible in DMALP is 256 */
1247 if (*bursts >= 256*256) {
1248 lcnt1 = 256;
1249 lcnt0 = 256;
1250 cyc = *bursts / lcnt1 / lcnt0;
1251 } else if (*bursts > 256) {
1252 lcnt1 = 256;
1253 lcnt0 = *bursts / lcnt1;
1254 cyc = 1;
1255 } else {
1256 lcnt1 = *bursts;
1257 lcnt0 = 0;
1258 cyc = 1;
1259 }
1260
1261 szlp = _emit_LP(1, buf, 0, 0);
1262 szbrst = _bursts(pl330, 1, buf, pxs, 1);
1263
1264 lpend.cond = ALWAYS;
1265 lpend.forever = false;
1266 lpend.loop = 0;
1267 lpend.bjump = 0;
1268 szlpend = _emit_LPEND(1, buf, &lpend);
1269
1270 if (lcnt0) {
1271 szlp *= 2;
1272 szlpend *= 2;
1273 }
1274
1275 /*
1276 * Max bursts that we can unroll due to limit on the
1277 * size of backward jump that can be encoded in DMALPEND
1278 * which is 8-bits and hence 255
1279 */
1280 cycmax = (255 - (szlp + szlpend)) / szbrst;
1281
1282 cyc = (cycmax < cyc) ? cycmax : cyc;
1283
1284 off = 0;
1285
1286 if (lcnt0) {
1287 off += _emit_LP(dry_run, &buf[off], 0, lcnt0);
1288 ljmp0 = off;
1289 }
1290
1291 off += _emit_LP(dry_run, &buf[off], 1, lcnt1);
1292 ljmp1 = off;
1293
1294 off += _bursts(pl330, dry_run, &buf[off], pxs, cyc);
1295
1296 lpend.cond = ALWAYS;
1297 lpend.forever = false;
1298 lpend.loop = 1;
1299 lpend.bjump = off - ljmp1;
1300 off += _emit_LPEND(dry_run, &buf[off], &lpend);
1301
1302 if (lcnt0) {
1303 lpend.cond = ALWAYS;
1304 lpend.forever = false;
1305 lpend.loop = 0;
1306 lpend.bjump = off - ljmp0;
1307 off += _emit_LPEND(dry_run, &buf[off], &lpend);
1308 }
1309
1310 *bursts = lcnt1 * cyc;
1311 if (lcnt0)
1312 *bursts *= lcnt0;
1313
1314 return off;
1315}
1316
1317static inline int _setup_loops(struct pl330_dmac *pl330,
1318 unsigned dry_run, u8 buf[],
1319 const struct _xfer_spec *pxs)
1320{
1321 struct pl330_xfer *x = &pxs->desc->px;
1322 u32 ccr = pxs->ccr;
1323 unsigned long c, bursts = BYTE_TO_BURST(x->bytes, ccr);
1324 int off = 0;
1325
1326 while (bursts) {
1327 c = bursts;
1328 off += _loop(pl330, dry_run, &buf[off], &c, pxs);
1329 bursts -= c;
1330 }
1331
1332 return off;
1333}
1334
1335static inline int _setup_xfer(struct pl330_dmac *pl330,
1336 unsigned dry_run, u8 buf[],
1337 const struct _xfer_spec *pxs)
1338{
1339 struct pl330_xfer *x = &pxs->desc->px;
1340 int off = 0;
1341
1342 /* DMAMOV SAR, x->src_addr */
1343 off += _emit_MOV(dry_run, &buf[off], SAR, x->src_addr);
1344 /* DMAMOV DAR, x->dst_addr */
1345 off += _emit_MOV(dry_run, &buf[off], DAR, x->dst_addr);
1346
1347 /* Setup Loop(s) */
1348 off += _setup_loops(pl330, dry_run, &buf[off], pxs);
1349
1350 return off;
1351}
1352
1353/*
1354 * A req is a sequence of one or more xfer units.
1355 * Returns the number of bytes taken to setup the MC for the req.
1356 */
1357static int _setup_req(struct pl330_dmac *pl330, unsigned dry_run,
1358 struct pl330_thread *thrd, unsigned index,
1359 struct _xfer_spec *pxs)
1360{
1361 struct _pl330_req *req = &thrd->req[index];
1362 struct pl330_xfer *x;
1363 u8 *buf = req->mc_cpu;
1364 int off = 0;
1365
1366 PL330_DBGMC_START(req->mc_bus);
1367
1368 /* DMAMOV CCR, ccr */
1369 off += _emit_MOV(dry_run, &buf[off], CCR, pxs->ccr);
1370
1371 x = &pxs->desc->px;
1372 /* Error if xfer length is not aligned at burst size */
1373 if (x->bytes % (BRST_SIZE(pxs->ccr) * BRST_LEN(pxs->ccr)))
1374 return -EINVAL;
1375
1376 off += _setup_xfer(pl330, dry_run, &buf[off], pxs);
1377
1378 /* DMASEV peripheral/event */
1379 off += _emit_SEV(dry_run, &buf[off], thrd->ev);
1380 /* DMAEND */
1381 off += _emit_END(dry_run, &buf[off]);
1382
1383 return off;
1384}
1385
1386static inline u32 _prepare_ccr(const struct pl330_reqcfg *rqc)
1387{
1388 u32 ccr = 0;
1389
1390 if (rqc->src_inc)
1391 ccr |= CC_SRCINC;
1392
1393 if (rqc->dst_inc)
1394 ccr |= CC_DSTINC;
1395
1396 /* We set same protection levels for Src and DST for now */
1397 if (rqc->privileged)
1398 ccr |= CC_SRCPRI | CC_DSTPRI;
1399 if (rqc->nonsecure)
1400 ccr |= CC_SRCNS | CC_DSTNS;
1401 if (rqc->insnaccess)
1402 ccr |= CC_SRCIA | CC_DSTIA;
1403
1404 ccr |= (((rqc->brst_len - 1) & 0xf) << CC_SRCBRSTLEN_SHFT);
1405 ccr |= (((rqc->brst_len - 1) & 0xf) << CC_DSTBRSTLEN_SHFT);
1406
1407 ccr |= (rqc->brst_size << CC_SRCBRSTSIZE_SHFT);
1408 ccr |= (rqc->brst_size << CC_DSTBRSTSIZE_SHFT);
1409
1410 ccr |= (rqc->scctl << CC_SRCCCTRL_SHFT);
1411 ccr |= (rqc->dcctl << CC_DSTCCTRL_SHFT);
1412
1413 ccr |= (rqc->swap << CC_SWAP_SHFT);
1414
1415 return ccr;
1416}
1417
1418/*
1419 * Submit a list of xfers after which the client wants notification.
1420 * Client is not notified after each xfer unit, just once after all
1421 * xfer units are done or some error occurs.
1422 */
1423static int pl330_submit_req(struct pl330_thread *thrd,
1424 struct dma_pl330_desc *desc)
1425{
1426 struct pl330_dmac *pl330 = thrd->dmac;
1427 struct _xfer_spec xs;
1428 unsigned long flags;
1429 unsigned idx;
1430 u32 ccr;
1431 int ret = 0;
1432
1433 if (pl330->state == DYING
1434 || pl330->dmac_tbd.reset_chan & (1 << thrd->id)) {
1435 dev_info(thrd->dmac->ddma.dev, "%s:%d\n",
1436 __func__, __LINE__);
1437 return -EAGAIN;
1438 }
1439
1440 /* If request for non-existing peripheral */
1441 if (desc->rqtype != DMA_MEM_TO_MEM &&
1442 desc->peri >= pl330->pcfg.num_peri) {
1443 dev_info(thrd->dmac->ddma.dev,
1444 "%s:%d Invalid peripheral(%u)!\n",
1445 __func__, __LINE__, desc->peri);
1446 return -EINVAL;
1447 }
1448
1449 spin_lock_irqsave(&pl330->lock, flags);
1450
1451 if (_queue_full(thrd)) {
1452 ret = -EAGAIN;
1453 goto xfer_exit;
1454 }
1455
1456 /* Prefer Secure Channel */
1457 if (!_manager_ns(thrd))
1458 desc->rqcfg.nonsecure = 0;
1459 else
1460 desc->rqcfg.nonsecure = 1;
1461
1462 ccr = _prepare_ccr(&desc->rqcfg);
1463
1464 idx = thrd->req[0].desc == NULL ? 0 : 1;
1465
1466 xs.ccr = ccr;
1467 xs.desc = desc;
1468
1469 /* First dry run to check if req is acceptable */
1470 ret = _setup_req(pl330, 1, thrd, idx, &xs);
1471 if (ret < 0)
1472 goto xfer_exit;
1473
1474 if (ret > pl330->mcbufsz / 2) {
1475 dev_info(pl330->ddma.dev, "%s:%d Try increasing mcbufsz (%i/%i)\n",
1476 __func__, __LINE__, ret, pl330->mcbufsz / 2);
1477 ret = -ENOMEM;
1478 goto xfer_exit;
1479 }
1480
1481 /* Hook the request */
1482 thrd->lstenq = idx;
1483 thrd->req[idx].desc = desc;
1484 _setup_req(pl330, 0, thrd, idx, &xs);
1485
1486 ret = 0;
1487
1488xfer_exit:
1489 spin_unlock_irqrestore(&pl330->lock, flags);
1490
1491 return ret;
1492}
1493
1494static void dma_pl330_rqcb(struct dma_pl330_desc *desc, enum pl330_op_err err)
1495{
1496 struct dma_pl330_chan *pch;
1497 unsigned long flags;
1498
1499 if (!desc)
1500 return;
1501
1502 pch = desc->pchan;
1503
1504 /* If desc aborted */
1505 if (!pch)
1506 return;
1507
1508 spin_lock_irqsave(&pch->lock, flags);
1509
1510 desc->status = DONE;
1511
1512 spin_unlock_irqrestore(&pch->lock, flags);
1513
1514 tasklet_schedule(&pch->task);
1515}
1516
1517static void pl330_dotask(unsigned long data)
1518{
1519 struct pl330_dmac *pl330 = (struct pl330_dmac *) data;
1520 unsigned long flags;
1521 int i;
1522
1523 spin_lock_irqsave(&pl330->lock, flags);
1524
1525 /* The DMAC itself gone nuts */
1526 if (pl330->dmac_tbd.reset_dmac) {
1527 pl330->state = DYING;
1528 /* Reset the manager too */
1529 pl330->dmac_tbd.reset_mngr = true;
1530 /* Clear the reset flag */
1531 pl330->dmac_tbd.reset_dmac = false;
1532 }
1533
1534 if (pl330->dmac_tbd.reset_mngr) {
1535 _stop(pl330->manager);
1536 /* Reset all channels */
1537 pl330->dmac_tbd.reset_chan = (1 << pl330->pcfg.num_chan) - 1;
1538 /* Clear the reset flag */
1539 pl330->dmac_tbd.reset_mngr = false;
1540 }
1541
1542 for (i = 0; i < pl330->pcfg.num_chan; i++) {
1543
1544 if (pl330->dmac_tbd.reset_chan & (1 << i)) {
1545 struct pl330_thread *thrd = &pl330->channels[i];
1546 void __iomem *regs = pl330->base;
1547 enum pl330_op_err err;
1548
1549 _stop(thrd);
1550
1551 if (readl(regs + FSC) & (1 << thrd->id))
1552 err = PL330_ERR_FAIL;
1553 else
1554 err = PL330_ERR_ABORT;
1555
1556 spin_unlock_irqrestore(&pl330->lock, flags);
1557 dma_pl330_rqcb(thrd->req[1 - thrd->lstenq].desc, err);
1558 dma_pl330_rqcb(thrd->req[thrd->lstenq].desc, err);
1559 spin_lock_irqsave(&pl330->lock, flags);
1560
1561 thrd->req[0].desc = NULL;
1562 thrd->req[1].desc = NULL;
1563 thrd->req_running = -1;
1564
1565 /* Clear the reset flag */
1566 pl330->dmac_tbd.reset_chan &= ~(1 << i);
1567 }
1568 }
1569
1570 spin_unlock_irqrestore(&pl330->lock, flags);
1571
1572 return;
1573}
1574
1575/* Returns 1 if state was updated, 0 otherwise */
1576static int pl330_update(struct pl330_dmac *pl330)
1577{
1578 struct dma_pl330_desc *descdone, *tmp;
1579 unsigned long flags;
1580 void __iomem *regs;
1581 u32 val;
1582 int id, ev, ret = 0;
1583
1584 regs = pl330->base;
1585
1586 spin_lock_irqsave(&pl330->lock, flags);
1587
1588 val = readl(regs + FSM) & 0x1;
1589 if (val)
1590 pl330->dmac_tbd.reset_mngr = true;
1591 else
1592 pl330->dmac_tbd.reset_mngr = false;
1593
1594 val = readl(regs + FSC) & ((1 << pl330->pcfg.num_chan) - 1);
1595 pl330->dmac_tbd.reset_chan |= val;
1596 if (val) {
1597 int i = 0;
1598 while (i < pl330->pcfg.num_chan) {
1599 if (val & (1 << i)) {
1600 dev_info(pl330->ddma.dev,
1601 "Reset Channel-%d\t CS-%x FTC-%x\n",
1602 i, readl(regs + CS(i)),
1603 readl(regs + FTC(i)));
1604 _stop(&pl330->channels[i]);
1605 }
1606 i++;
1607 }
1608 }
1609
1610 /* Check which event happened i.e, thread notified */
1611 val = readl(regs + ES);
1612 if (pl330->pcfg.num_events < 32
1613 && val & ~((1 << pl330->pcfg.num_events) - 1)) {
1614 pl330->dmac_tbd.reset_dmac = true;
1615 dev_err(pl330->ddma.dev, "%s:%d Unexpected!\n", __func__,
1616 __LINE__);
1617 ret = 1;
1618 goto updt_exit;
1619 }
1620
1621 for (ev = 0; ev < pl330->pcfg.num_events; ev++) {
1622 if (val & (1 << ev)) { /* Event occurred */
1623 struct pl330_thread *thrd;
1624 u32 inten = readl(regs + INTEN);
1625 int active;
1626
1627 /* Clear the event */
1628 if (inten & (1 << ev))
1629 writel(1 << ev, regs + INTCLR);
1630
1631 ret = 1;
1632
1633 id = pl330->events[ev];
1634
1635 thrd = &pl330->channels[id];
1636
1637 active = thrd->req_running;
1638 if (active == -1) /* Aborted */
1639 continue;
1640
1641 /* Detach the req */
1642 descdone = thrd->req[active].desc;
1643 thrd->req[active].desc = NULL;
1644
1645 thrd->req_running = -1;
1646
1647 /* Get going again ASAP */
1648 _start(thrd);
1649
1650 /* For now, just make a list of callbacks to be done */
1651 list_add_tail(&descdone->rqd, &pl330->req_done);
1652 }
1653 }
1654
1655 /* Now that we are in no hurry, do the callbacks */
1656 list_for_each_entry_safe(descdone, tmp, &pl330->req_done, rqd) {
1657 list_del(&descdone->rqd);
1658 spin_unlock_irqrestore(&pl330->lock, flags);
1659 dma_pl330_rqcb(descdone, PL330_ERR_NONE);
1660 spin_lock_irqsave(&pl330->lock, flags);
1661 }
1662
1663updt_exit:
1664 spin_unlock_irqrestore(&pl330->lock, flags);
1665
1666 if (pl330->dmac_tbd.reset_dmac
1667 || pl330->dmac_tbd.reset_mngr
1668 || pl330->dmac_tbd.reset_chan) {
1669 ret = 1;
1670 tasklet_schedule(&pl330->tasks);
1671 }
1672
1673 return ret;
1674}
1675
1676/* Reserve an event */
1677static inline int _alloc_event(struct pl330_thread *thrd)
1678{
1679 struct pl330_dmac *pl330 = thrd->dmac;
1680 int ev;
1681
1682 for (ev = 0; ev < pl330->pcfg.num_events; ev++)
1683 if (pl330->events[ev] == -1) {
1684 pl330->events[ev] = thrd->id;
1685 return ev;
1686 }
1687
1688 return -1;
1689}
1690
1691static bool _chan_ns(const struct pl330_dmac *pl330, int i)
1692{
1693 return pl330->pcfg.irq_ns & (1 << i);
1694}
1695
1696/* Upon success, returns IdentityToken for the
1697 * allocated channel, NULL otherwise.
1698 */
1699static struct pl330_thread *pl330_request_channel(struct pl330_dmac *pl330)
1700{
1701 struct pl330_thread *thrd = NULL;
1702 int chans, i;
1703
1704 if (pl330->state == DYING)
1705 return NULL;
1706
1707 chans = pl330->pcfg.num_chan;
1708
1709 for (i = 0; i < chans; i++) {
1710 thrd = &pl330->channels[i];
1711 if ((thrd->free) && (!_manager_ns(thrd) ||
1712 _chan_ns(pl330, i))) {
1713 thrd->ev = _alloc_event(thrd);
1714 if (thrd->ev >= 0) {
1715 thrd->free = false;
1716 thrd->lstenq = 1;
1717 thrd->req[0].desc = NULL;
1718 thrd->req[1].desc = NULL;
1719 thrd->req_running = -1;
1720 break;
1721 }
1722 }
1723 thrd = NULL;
1724 }
1725
1726 return thrd;
1727}
1728
1729/* Release an event */
1730static inline void _free_event(struct pl330_thread *thrd, int ev)
1731{
1732 struct pl330_dmac *pl330 = thrd->dmac;
1733
1734 /* If the event is valid and was held by the thread */
1735 if (ev >= 0 && ev < pl330->pcfg.num_events
1736 && pl330->events[ev] == thrd->id)
1737 pl330->events[ev] = -1;
1738}
1739
1740static void pl330_release_channel(struct pl330_thread *thrd)
1741{
1742 struct pl330_dmac *pl330;
1743
1744 if (!thrd || thrd->free)
1745 return;
1746
1747 _stop(thrd);
1748
1749 dma_pl330_rqcb(thrd->req[1 - thrd->lstenq].desc, PL330_ERR_ABORT);
1750 dma_pl330_rqcb(thrd->req[thrd->lstenq].desc, PL330_ERR_ABORT);
1751
1752 pl330 = thrd->dmac;
1753
1754 _free_event(thrd, thrd->ev);
1755 thrd->free = true;
1756}
1757
1758/* Initialize the structure for PL330 configuration, that can be used
1759 * by the client driver the make best use of the DMAC
1760 */
1761static void read_dmac_config(struct pl330_dmac *pl330)
1762{
1763 void __iomem *regs = pl330->base;
1764 u32 val;
1765
1766 val = readl(regs + CRD) >> CRD_DATA_WIDTH_SHIFT;
1767 val &= CRD_DATA_WIDTH_MASK;
1768 pl330->pcfg.data_bus_width = 8 * (1 << val);
1769
1770 val = readl(regs + CRD) >> CRD_DATA_BUFF_SHIFT;
1771 val &= CRD_DATA_BUFF_MASK;
1772 pl330->pcfg.data_buf_dep = val + 1;
1773
1774 val = readl(regs + CR0) >> CR0_NUM_CHANS_SHIFT;
1775 val &= CR0_NUM_CHANS_MASK;
1776 val += 1;
1777 pl330->pcfg.num_chan = val;
1778
1779 val = readl(regs + CR0);
1780 if (val & CR0_PERIPH_REQ_SET) {
1781 val = (val >> CR0_NUM_PERIPH_SHIFT) & CR0_NUM_PERIPH_MASK;
1782 val += 1;
1783 pl330->pcfg.num_peri = val;
1784 pl330->pcfg.peri_ns = readl(regs + CR4);
1785 } else {
1786 pl330->pcfg.num_peri = 0;
1787 }
1788
1789 val = readl(regs + CR0);
1790 if (val & CR0_BOOT_MAN_NS)
1791 pl330->pcfg.mode |= DMAC_MODE_NS;
1792 else
1793 pl330->pcfg.mode &= ~DMAC_MODE_NS;
1794
1795 val = readl(regs + CR0) >> CR0_NUM_EVENTS_SHIFT;
1796 val &= CR0_NUM_EVENTS_MASK;
1797 val += 1;
1798 pl330->pcfg.num_events = val;
1799
1800 pl330->pcfg.irq_ns = readl(regs + CR3);
1801}
1802
1803static inline void _reset_thread(struct pl330_thread *thrd)
1804{
1805 struct pl330_dmac *pl330 = thrd->dmac;
1806
1807 thrd->req[0].mc_cpu = pl330->mcode_cpu
1808 + (thrd->id * pl330->mcbufsz);
1809 thrd->req[0].mc_bus = pl330->mcode_bus
1810 + (thrd->id * pl330->mcbufsz);
1811 thrd->req[0].desc = NULL;
1812
1813 thrd->req[1].mc_cpu = thrd->req[0].mc_cpu
1814 + pl330->mcbufsz / 2;
1815 thrd->req[1].mc_bus = thrd->req[0].mc_bus
1816 + pl330->mcbufsz / 2;
1817 thrd->req[1].desc = NULL;
1818
1819 thrd->req_running = -1;
1820}
1821
1822static int dmac_alloc_threads(struct pl330_dmac *pl330)
1823{
1824 int chans = pl330->pcfg.num_chan;
1825 struct pl330_thread *thrd;
1826 int i;
1827
1828 /* Allocate 1 Manager and 'chans' Channel threads */
1829 pl330->channels = kzalloc((1 + chans) * sizeof(*thrd),
1830 GFP_KERNEL);
1831 if (!pl330->channels)
1832 return -ENOMEM;
1833
1834 /* Init Channel threads */
1835 for (i = 0; i < chans; i++) {
1836 thrd = &pl330->channels[i];
1837 thrd->id = i;
1838 thrd->dmac = pl330;
1839 _reset_thread(thrd);
1840 thrd->free = true;
1841 }
1842
1843 /* MANAGER is indexed at the end */
1844 thrd = &pl330->channels[chans];
1845 thrd->id = chans;
1846 thrd->dmac = pl330;
1847 thrd->free = false;
1848 pl330->manager = thrd;
1849
1850 return 0;
1851}
1852
1853static int dmac_alloc_resources(struct pl330_dmac *pl330)
1854{
1855 int chans = pl330->pcfg.num_chan;
1856 int ret;
1857
1858 /*
1859 * Alloc MicroCode buffer for 'chans' Channel threads.
1860 * A channel's buffer offset is (Channel_Id * MCODE_BUFF_PERCHAN)
1861 */
1862 pl330->mcode_cpu = dma_alloc_coherent(pl330->ddma.dev,
1863 chans * pl330->mcbufsz,
1864 &pl330->mcode_bus, GFP_KERNEL);
1865 if (!pl330->mcode_cpu) {
1866 dev_err(pl330->ddma.dev, "%s:%d Can't allocate memory!\n",
1867 __func__, __LINE__);
1868 return -ENOMEM;
1869 }
1870
1871 ret = dmac_alloc_threads(pl330);
1872 if (ret) {
1873 dev_err(pl330->ddma.dev, "%s:%d Can't to create channels for DMAC!\n",
1874 __func__, __LINE__);
1875 dma_free_coherent(pl330->ddma.dev,
1876 chans * pl330->mcbufsz,
1877 pl330->mcode_cpu, pl330->mcode_bus);
1878 return ret;
1879 }
1880
1881 return 0;
1882}
1883
1884static int pl330_add(struct pl330_dmac *pl330)
1885{
1886 int i, ret;
1887
1888 /* Check if we can handle this DMAC */
1889 if ((pl330->pcfg.periph_id & 0xfffff) != PERIPH_ID_VAL) {
1890 dev_err(pl330->ddma.dev, "PERIPH_ID 0x%x !\n",
1891 pl330->pcfg.periph_id);
1892 return -EINVAL;
1893 }
1894
1895 /* Read the configuration of the DMAC */
1896 read_dmac_config(pl330);
1897
1898 if (pl330->pcfg.num_events == 0) {
1899 dev_err(pl330->ddma.dev, "%s:%d Can't work without events!\n",
1900 __func__, __LINE__);
1901 return -EINVAL;
1902 }
1903
1904 spin_lock_init(&pl330->lock);
1905
1906 INIT_LIST_HEAD(&pl330->req_done);
1907
1908 /* Use default MC buffer size if not provided */
1909 if (!pl330->mcbufsz)
1910 pl330->mcbufsz = MCODE_BUFF_PER_REQ * 2;
1911
1912 /* Mark all events as free */
1913 for (i = 0; i < pl330->pcfg.num_events; i++)
1914 pl330->events[i] = -1;
1915
1916 /* Allocate resources needed by the DMAC */
1917 ret = dmac_alloc_resources(pl330);
1918 if (ret) {
1919 dev_err(pl330->ddma.dev, "Unable to create channels for DMAC\n");
1920 return ret;
1921 }
1922
1923 tasklet_init(&pl330->tasks, pl330_dotask, (unsigned long) pl330);
1924
1925 pl330->state = INIT;
1926
1927 return 0;
1928}
1929
1930static int dmac_free_threads(struct pl330_dmac *pl330)
1931{
1932 struct pl330_thread *thrd;
1933 int i;
1934
1935 /* Release Channel threads */
1936 for (i = 0; i < pl330->pcfg.num_chan; i++) {
1937 thrd = &pl330->channels[i];
1938 pl330_release_channel(thrd);
1939 }
1940
1941 /* Free memory */
1942 kfree(pl330->channels);
1943
1944 return 0;
1945}
1946
1947static void pl330_del(struct pl330_dmac *pl330)
1948{
1949 pl330->state = UNINIT;
1950
1951 tasklet_kill(&pl330->tasks);
1952
1953 /* Free DMAC resources */
1954 dmac_free_threads(pl330);
1955
1956 dma_free_coherent(pl330->ddma.dev,
1957 pl330->pcfg.num_chan * pl330->mcbufsz, pl330->mcode_cpu,
1958 pl330->mcode_bus);
1959}
1960
1961/* forward declaration */
1962static struct amba_driver pl330_driver;
1963
1964static inline struct dma_pl330_chan *
1965to_pchan(struct dma_chan *ch)
1966{
1967 if (!ch)
1968 return NULL;
1969
1970 return container_of(ch, struct dma_pl330_chan, chan);
1971}
1972
1973static inline struct dma_pl330_desc *
1974to_desc(struct dma_async_tx_descriptor *tx)
1975{
1976 return container_of(tx, struct dma_pl330_desc, txd);
1977}
1978
1979static inline void fill_queue(struct dma_pl330_chan *pch)
1980{
1981 struct dma_pl330_desc *desc;
1982 int ret;
1983
1984 list_for_each_entry(desc, &pch->work_list, node) {
1985
1986 /* If already submitted */
1987 if (desc->status == BUSY)
1988 continue;
1989
1990 ret = pl330_submit_req(pch->thread, desc);
1991 if (!ret) {
1992 desc->status = BUSY;
1993 } else if (ret == -EAGAIN) {
1994 /* QFull or DMAC Dying */
1995 break;
1996 } else {
1997 /* Unacceptable request */
1998 desc->status = DONE;
1999 dev_err(pch->dmac->ddma.dev, "%s:%d Bad Desc(%d)\n",
2000 __func__, __LINE__, desc->txd.cookie);
2001 tasklet_schedule(&pch->task);
2002 }
2003 }
2004}
2005
2006static void pl330_tasklet(unsigned long data)
2007{
2008 struct dma_pl330_chan *pch = (struct dma_pl330_chan *)data;
2009 struct dma_pl330_desc *desc, *_dt;
2010 unsigned long flags;
2011 bool power_down = false;
2012
2013 spin_lock_irqsave(&pch->lock, flags);
2014
2015 /* Pick up ripe tomatoes */
2016 list_for_each_entry_safe(desc, _dt, &pch->work_list, node)
2017 if (desc->status == DONE) {
2018 if (!pch->cyclic)
2019 dma_cookie_complete(&desc->txd);
2020 list_move_tail(&desc->node, &pch->completed_list);
2021 }
2022
2023 /* Try to submit a req imm. next to the last completed cookie */
2024 fill_queue(pch);
2025
2026 if (list_empty(&pch->work_list)) {
2027 spin_lock(&pch->thread->dmac->lock);
2028 _stop(pch->thread);
2029 spin_unlock(&pch->thread->dmac->lock);
2030 power_down = true;
2031 pch->active = false;
2032 } else {
2033 /* Make sure the PL330 Channel thread is active */
2034 spin_lock(&pch->thread->dmac->lock);
2035 _start(pch->thread);
2036 spin_unlock(&pch->thread->dmac->lock);
2037 }
2038
2039 while (!list_empty(&pch->completed_list)) {
2040 struct dmaengine_desc_callback cb;
2041
2042 desc = list_first_entry(&pch->completed_list,
2043 struct dma_pl330_desc, node);
2044
2045 dmaengine_desc_get_callback(&desc->txd, &cb);
2046
2047 if (pch->cyclic) {
2048 desc->status = PREP;
2049 list_move_tail(&desc->node, &pch->work_list);
2050 if (power_down) {
2051 pch->active = true;
2052 spin_lock(&pch->thread->dmac->lock);
2053 _start(pch->thread);
2054 spin_unlock(&pch->thread->dmac->lock);
2055 power_down = false;
2056 }
2057 } else {
2058 desc->status = FREE;
2059 list_move_tail(&desc->node, &pch->dmac->desc_pool);
2060 }
2061
2062 dma_descriptor_unmap(&desc->txd);
2063
2064 if (dmaengine_desc_callback_valid(&cb)) {
2065 spin_unlock_irqrestore(&pch->lock, flags);
2066 dmaengine_desc_callback_invoke(&cb, NULL);
2067 spin_lock_irqsave(&pch->lock, flags);
2068 }
2069 }
2070 spin_unlock_irqrestore(&pch->lock, flags);
2071
2072 /* If work list empty, power down */
2073 if (power_down) {
2074 pm_runtime_mark_last_busy(pch->dmac->ddma.dev);
2075 pm_runtime_put_autosuspend(pch->dmac->ddma.dev);
2076 }
2077}
2078
2079bool pl330_filter(struct dma_chan *chan, void *param)
2080{
2081 u8 *peri_id;
2082
2083 if (chan->device->dev->driver != &pl330_driver.drv)
2084 return false;
2085
2086 peri_id = chan->private;
2087 return *peri_id == (unsigned long)param;
2088}
2089EXPORT_SYMBOL(pl330_filter);
2090
2091static struct dma_chan *of_dma_pl330_xlate(struct of_phandle_args *dma_spec,
2092 struct of_dma *ofdma)
2093{
2094 int count = dma_spec->args_count;
2095 struct pl330_dmac *pl330 = ofdma->of_dma_data;
2096 unsigned int chan_id;
2097
2098 if (!pl330)
2099 return NULL;
2100
2101 if (count != 1)
2102 return NULL;
2103
2104 chan_id = dma_spec->args[0];
2105 if (chan_id >= pl330->num_peripherals)
2106 return NULL;
2107
2108 return dma_get_slave_channel(&pl330->peripherals[chan_id].chan);
2109}
2110
2111static int pl330_alloc_chan_resources(struct dma_chan *chan)
2112{
2113 struct dma_pl330_chan *pch = to_pchan(chan);
2114 struct pl330_dmac *pl330 = pch->dmac;
2115 unsigned long flags;
2116
2117 spin_lock_irqsave(&pl330->lock, flags);
2118
2119 dma_cookie_init(chan);
2120 pch->cyclic = false;
2121
2122 pch->thread = pl330_request_channel(pl330);
2123 if (!pch->thread) {
2124 spin_unlock_irqrestore(&pl330->lock, flags);
2125 return -ENOMEM;
2126 }
2127
2128 tasklet_init(&pch->task, pl330_tasklet, (unsigned long) pch);
2129
2130 spin_unlock_irqrestore(&pl330->lock, flags);
2131
2132 return 1;
2133}
2134
2135static int pl330_config(struct dma_chan *chan,
2136 struct dma_slave_config *slave_config)
2137{
2138 struct dma_pl330_chan *pch = to_pchan(chan);
2139
2140 if (slave_config->direction == DMA_MEM_TO_DEV) {
2141 if (slave_config->dst_addr)
2142 pch->fifo_addr = slave_config->dst_addr;
2143 if (slave_config->dst_addr_width)
2144 pch->burst_sz = __ffs(slave_config->dst_addr_width);
2145 if (slave_config->dst_maxburst)
2146 pch->burst_len = slave_config->dst_maxburst;
2147 } else if (slave_config->direction == DMA_DEV_TO_MEM) {
2148 if (slave_config->src_addr)
2149 pch->fifo_addr = slave_config->src_addr;
2150 if (slave_config->src_addr_width)
2151 pch->burst_sz = __ffs(slave_config->src_addr_width);
2152 if (slave_config->src_maxburst)
2153 pch->burst_len = slave_config->src_maxburst;
2154 }
2155
2156 return 0;
2157}
2158
2159static int pl330_terminate_all(struct dma_chan *chan)
2160{
2161 struct dma_pl330_chan *pch = to_pchan(chan);
2162 struct dma_pl330_desc *desc;
2163 unsigned long flags;
2164 struct pl330_dmac *pl330 = pch->dmac;
2165 LIST_HEAD(list);
2166 bool power_down = false;
2167
2168 pm_runtime_get_sync(pl330->ddma.dev);
2169 spin_lock_irqsave(&pch->lock, flags);
2170 spin_lock(&pl330->lock);
2171 _stop(pch->thread);
2172 spin_unlock(&pl330->lock);
2173
2174 pch->thread->req[0].desc = NULL;
2175 pch->thread->req[1].desc = NULL;
2176 pch->thread->req_running = -1;
2177 power_down = pch->active;
2178 pch->active = false;
2179
2180 /* Mark all desc done */
2181 list_for_each_entry(desc, &pch->submitted_list, node) {
2182 desc->status = FREE;
2183 dma_cookie_complete(&desc->txd);
2184 }
2185
2186 list_for_each_entry(desc, &pch->work_list , node) {
2187 desc->status = FREE;
2188 dma_cookie_complete(&desc->txd);
2189 }
2190
2191 list_splice_tail_init(&pch->submitted_list, &pl330->desc_pool);
2192 list_splice_tail_init(&pch->work_list, &pl330->desc_pool);
2193 list_splice_tail_init(&pch->completed_list, &pl330->desc_pool);
2194 spin_unlock_irqrestore(&pch->lock, flags);
2195 pm_runtime_mark_last_busy(pl330->ddma.dev);
2196 if (power_down)
2197 pm_runtime_put_autosuspend(pl330->ddma.dev);
2198 pm_runtime_put_autosuspend(pl330->ddma.dev);
2199
2200 return 0;
2201}
2202
2203/*
2204 * We don't support DMA_RESUME command because of hardware
2205 * limitations, so after pausing the channel we cannot restore
2206 * it to active state. We have to terminate channel and setup
2207 * DMA transfer again. This pause feature was implemented to
2208 * allow safely read residue before channel termination.
2209 */
2210static int pl330_pause(struct dma_chan *chan)
2211{
2212 struct dma_pl330_chan *pch = to_pchan(chan);
2213 struct pl330_dmac *pl330 = pch->dmac;
2214 unsigned long flags;
2215
2216 pm_runtime_get_sync(pl330->ddma.dev);
2217 spin_lock_irqsave(&pch->lock, flags);
2218
2219 spin_lock(&pl330->lock);
2220 _stop(pch->thread);
2221 spin_unlock(&pl330->lock);
2222
2223 spin_unlock_irqrestore(&pch->lock, flags);
2224 pm_runtime_mark_last_busy(pl330->ddma.dev);
2225 pm_runtime_put_autosuspend(pl330->ddma.dev);
2226
2227 return 0;
2228}
2229
2230static void pl330_free_chan_resources(struct dma_chan *chan)
2231{
2232 struct dma_pl330_chan *pch = to_pchan(chan);
2233 struct pl330_dmac *pl330 = pch->dmac;
2234 unsigned long flags;
2235
2236 tasklet_kill(&pch->task);
2237
2238 pm_runtime_get_sync(pch->dmac->ddma.dev);
2239 spin_lock_irqsave(&pl330->lock, flags);
2240
2241 pl330_release_channel(pch->thread);
2242 pch->thread = NULL;
2243
2244 if (pch->cyclic)
2245 list_splice_tail_init(&pch->work_list, &pch->dmac->desc_pool);
2246
2247 spin_unlock_irqrestore(&pl330->lock, flags);
2248 pm_runtime_mark_last_busy(pch->dmac->ddma.dev);
2249 pm_runtime_put_autosuspend(pch->dmac->ddma.dev);
2250}
2251
2252static int pl330_get_current_xferred_count(struct dma_pl330_chan *pch,
2253 struct dma_pl330_desc *desc)
2254{
2255 struct pl330_thread *thrd = pch->thread;
2256 struct pl330_dmac *pl330 = pch->dmac;
2257 void __iomem *regs = thrd->dmac->base;
2258 u32 val, addr;
2259
2260 pm_runtime_get_sync(pl330->ddma.dev);
2261 val = addr = 0;
2262 if (desc->rqcfg.src_inc) {
2263 val = readl(regs + SA(thrd->id));
2264 addr = desc->px.src_addr;
2265 } else {
2266 val = readl(regs + DA(thrd->id));
2267 addr = desc->px.dst_addr;
2268 }
2269 pm_runtime_mark_last_busy(pch->dmac->ddma.dev);
2270 pm_runtime_put_autosuspend(pl330->ddma.dev);
2271
2272 /* If DMAMOV hasn't finished yet, SAR/DAR can be zero */
2273 if (!val)
2274 return 0;
2275
2276 return val - addr;
2277}
2278
2279static enum dma_status
2280pl330_tx_status(struct dma_chan *chan, dma_cookie_t cookie,
2281 struct dma_tx_state *txstate)
2282{
2283 enum dma_status ret;
2284 unsigned long flags;
2285 struct dma_pl330_desc *desc, *running = NULL, *last_enq = NULL;
2286 struct dma_pl330_chan *pch = to_pchan(chan);
2287 unsigned int transferred, residual = 0;
2288
2289 ret = dma_cookie_status(chan, cookie, txstate);
2290
2291 if (!txstate)
2292 return ret;
2293
2294 if (ret == DMA_COMPLETE)
2295 goto out;
2296
2297 spin_lock_irqsave(&pch->lock, flags);
2298 spin_lock(&pch->thread->dmac->lock);
2299
2300 if (pch->thread->req_running != -1)
2301 running = pch->thread->req[pch->thread->req_running].desc;
2302
2303 last_enq = pch->thread->req[pch->thread->lstenq].desc;
2304
2305 /* Check in pending list */
2306 list_for_each_entry(desc, &pch->work_list, node) {
2307 if (desc->status == DONE)
2308 transferred = desc->bytes_requested;
2309 else if (running && desc == running)
2310 transferred =
2311 pl330_get_current_xferred_count(pch, desc);
2312 else if (desc->status == BUSY)
2313 /*
2314 * Busy but not running means either just enqueued,
2315 * or finished and not yet marked done
2316 */
2317 if (desc == last_enq)
2318 transferred = 0;
2319 else
2320 transferred = desc->bytes_requested;
2321 else
2322 transferred = 0;
2323 residual += desc->bytes_requested - transferred;
2324 if (desc->txd.cookie == cookie) {
2325 switch (desc->status) {
2326 case DONE:
2327 ret = DMA_COMPLETE;
2328 break;
2329 case PREP:
2330 case BUSY:
2331 ret = DMA_IN_PROGRESS;
2332 break;
2333 default:
2334 WARN_ON(1);
2335 }
2336 break;
2337 }
2338 if (desc->last)
2339 residual = 0;
2340 }
2341 spin_unlock(&pch->thread->dmac->lock);
2342 spin_unlock_irqrestore(&pch->lock, flags);
2343
2344out:
2345 dma_set_residue(txstate, residual);
2346
2347 return ret;
2348}
2349
2350static void pl330_issue_pending(struct dma_chan *chan)
2351{
2352 struct dma_pl330_chan *pch = to_pchan(chan);
2353 unsigned long flags;
2354
2355 spin_lock_irqsave(&pch->lock, flags);
2356 if (list_empty(&pch->work_list)) {
2357 /*
2358 * Warn on nothing pending. Empty submitted_list may
2359 * break our pm_runtime usage counter as it is
2360 * updated on work_list emptiness status.
2361 */
2362 WARN_ON(list_empty(&pch->submitted_list));
2363 pch->active = true;
2364 pm_runtime_get_sync(pch->dmac->ddma.dev);
2365 }
2366 list_splice_tail_init(&pch->submitted_list, &pch->work_list);
2367 spin_unlock_irqrestore(&pch->lock, flags);
2368
2369 pl330_tasklet((unsigned long)pch);
2370}
2371
2372/*
2373 * We returned the last one of the circular list of descriptor(s)
2374 * from prep_xxx, so the argument to submit corresponds to the last
2375 * descriptor of the list.
2376 */
2377static dma_cookie_t pl330_tx_submit(struct dma_async_tx_descriptor *tx)
2378{
2379 struct dma_pl330_desc *desc, *last = to_desc(tx);
2380 struct dma_pl330_chan *pch = to_pchan(tx->chan);
2381 dma_cookie_t cookie;
2382 unsigned long flags;
2383
2384 spin_lock_irqsave(&pch->lock, flags);
2385
2386 /* Assign cookies to all nodes */
2387 while (!list_empty(&last->node)) {
2388 desc = list_entry(last->node.next, struct dma_pl330_desc, node);
2389 if (pch->cyclic) {
2390 desc->txd.callback = last->txd.callback;
2391 desc->txd.callback_param = last->txd.callback_param;
2392 }
2393 desc->last = false;
2394
2395 dma_cookie_assign(&desc->txd);
2396
2397 list_move_tail(&desc->node, &pch->submitted_list);
2398 }
2399
2400 last->last = true;
2401 cookie = dma_cookie_assign(&last->txd);
2402 list_add_tail(&last->node, &pch->submitted_list);
2403 spin_unlock_irqrestore(&pch->lock, flags);
2404
2405 return cookie;
2406}
2407
2408static inline void _init_desc(struct dma_pl330_desc *desc)
2409{
2410 desc->rqcfg.swap = SWAP_NO;
2411 desc->rqcfg.scctl = CCTRL0;
2412 desc->rqcfg.dcctl = CCTRL0;
2413 desc->txd.tx_submit = pl330_tx_submit;
2414
2415 INIT_LIST_HEAD(&desc->node);
2416}
2417
2418/* Returns the number of descriptors added to the DMAC pool */
2419static int add_desc(struct pl330_dmac *pl330, gfp_t flg, int count)
2420{
2421 struct dma_pl330_desc *desc;
2422 unsigned long flags;
2423 int i;
2424
2425 desc = kcalloc(count, sizeof(*desc), flg);
2426 if (!desc)
2427 return 0;
2428
2429 spin_lock_irqsave(&pl330->pool_lock, flags);
2430
2431 for (i = 0; i < count; i++) {
2432 _init_desc(&desc[i]);
2433 list_add_tail(&desc[i].node, &pl330->desc_pool);
2434 }
2435
2436 spin_unlock_irqrestore(&pl330->pool_lock, flags);
2437
2438 return count;
2439}
2440
2441static struct dma_pl330_desc *pluck_desc(struct pl330_dmac *pl330)
2442{
2443 struct dma_pl330_desc *desc = NULL;
2444 unsigned long flags;
2445
2446 spin_lock_irqsave(&pl330->pool_lock, flags);
2447
2448 if (!list_empty(&pl330->desc_pool)) {
2449 desc = list_entry(pl330->desc_pool.next,
2450 struct dma_pl330_desc, node);
2451
2452 list_del_init(&desc->node);
2453
2454 desc->status = PREP;
2455 desc->txd.callback = NULL;
2456 }
2457
2458 spin_unlock_irqrestore(&pl330->pool_lock, flags);
2459
2460 return desc;
2461}
2462
2463static struct dma_pl330_desc *pl330_get_desc(struct dma_pl330_chan *pch)
2464{
2465 struct pl330_dmac *pl330 = pch->dmac;
2466 u8 *peri_id = pch->chan.private;
2467 struct dma_pl330_desc *desc;
2468
2469 /* Pluck one desc from the pool of DMAC */
2470 desc = pluck_desc(pl330);
2471
2472 /* If the DMAC pool is empty, alloc new */
2473 if (!desc) {
2474 if (!add_desc(pl330, GFP_ATOMIC, 1))
2475 return NULL;
2476
2477 /* Try again */
2478 desc = pluck_desc(pl330);
2479 if (!desc) {
2480 dev_err(pch->dmac->ddma.dev,
2481 "%s:%d ALERT!\n", __func__, __LINE__);
2482 return NULL;
2483 }
2484 }
2485
2486 /* Initialize the descriptor */
2487 desc->pchan = pch;
2488 desc->txd.cookie = 0;
2489 async_tx_ack(&desc->txd);
2490
2491 desc->peri = peri_id ? pch->chan.chan_id : 0;
2492 desc->rqcfg.pcfg = &pch->dmac->pcfg;
2493
2494 dma_async_tx_descriptor_init(&desc->txd, &pch->chan);
2495
2496 return desc;
2497}
2498
2499static inline void fill_px(struct pl330_xfer *px,
2500 dma_addr_t dst, dma_addr_t src, size_t len)
2501{
2502 px->bytes = len;
2503 px->dst_addr = dst;
2504 px->src_addr = src;
2505}
2506
2507static struct dma_pl330_desc *
2508__pl330_prep_dma_memcpy(struct dma_pl330_chan *pch, dma_addr_t dst,
2509 dma_addr_t src, size_t len)
2510{
2511 struct dma_pl330_desc *desc = pl330_get_desc(pch);
2512
2513 if (!desc) {
2514 dev_err(pch->dmac->ddma.dev, "%s:%d Unable to fetch desc\n",
2515 __func__, __LINE__);
2516 return NULL;
2517 }
2518
2519 /*
2520 * Ideally we should lookout for reqs bigger than
2521 * those that can be programmed with 256 bytes of
2522 * MC buffer, but considering a req size is seldom
2523 * going to be word-unaligned and more than 200MB,
2524 * we take it easy.
2525 * Also, should the limit is reached we'd rather
2526 * have the platform increase MC buffer size than
2527 * complicating this API driver.
2528 */
2529 fill_px(&desc->px, dst, src, len);
2530
2531 return desc;
2532}
2533
2534/* Call after fixing burst size */
2535static inline int get_burst_len(struct dma_pl330_desc *desc, size_t len)
2536{
2537 struct dma_pl330_chan *pch = desc->pchan;
2538 struct pl330_dmac *pl330 = pch->dmac;
2539 int burst_len;
2540
2541 burst_len = pl330->pcfg.data_bus_width / 8;
2542 burst_len *= pl330->pcfg.data_buf_dep / pl330->pcfg.num_chan;
2543 burst_len >>= desc->rqcfg.brst_size;
2544
2545 /* src/dst_burst_len can't be more than 16 */
2546 if (burst_len > 16)
2547 burst_len = 16;
2548
2549 while (burst_len > 1) {
2550 if (!(len % (burst_len << desc->rqcfg.brst_size)))
2551 break;
2552 burst_len--;
2553 }
2554
2555 return burst_len;
2556}
2557
2558static struct dma_async_tx_descriptor *pl330_prep_dma_cyclic(
2559 struct dma_chan *chan, dma_addr_t dma_addr, size_t len,
2560 size_t period_len, enum dma_transfer_direction direction,
2561 unsigned long flags)
2562{
2563 struct dma_pl330_desc *desc = NULL, *first = NULL;
2564 struct dma_pl330_chan *pch = to_pchan(chan);
2565 struct pl330_dmac *pl330 = pch->dmac;
2566 unsigned int i;
2567 dma_addr_t dst;
2568 dma_addr_t src;
2569
2570 if (len % period_len != 0)
2571 return NULL;
2572
2573 if (!is_slave_direction(direction)) {
2574 dev_err(pch->dmac->ddma.dev, "%s:%d Invalid dma direction\n",
2575 __func__, __LINE__);
2576 return NULL;
2577 }
2578
2579 for (i = 0; i < len / period_len; i++) {
2580 desc = pl330_get_desc(pch);
2581 if (!desc) {
2582 dev_err(pch->dmac->ddma.dev, "%s:%d Unable to fetch desc\n",
2583 __func__, __LINE__);
2584
2585 if (!first)
2586 return NULL;
2587
2588 spin_lock_irqsave(&pl330->pool_lock, flags);
2589
2590 while (!list_empty(&first->node)) {
2591 desc = list_entry(first->node.next,
2592 struct dma_pl330_desc, node);
2593 list_move_tail(&desc->node, &pl330->desc_pool);
2594 }
2595
2596 list_move_tail(&first->node, &pl330->desc_pool);
2597
2598 spin_unlock_irqrestore(&pl330->pool_lock, flags);
2599
2600 return NULL;
2601 }
2602
2603 switch (direction) {
2604 case DMA_MEM_TO_DEV:
2605 desc->rqcfg.src_inc = 1;
2606 desc->rqcfg.dst_inc = 0;
2607 src = dma_addr;
2608 dst = pch->fifo_addr;
2609 break;
2610 case DMA_DEV_TO_MEM:
2611 desc->rqcfg.src_inc = 0;
2612 desc->rqcfg.dst_inc = 1;
2613 src = pch->fifo_addr;
2614 dst = dma_addr;
2615 break;
2616 default:
2617 break;
2618 }
2619
2620 desc->rqtype = direction;
2621 desc->rqcfg.brst_size = pch->burst_sz;
2622 desc->rqcfg.brst_len = 1;
2623 desc->bytes_requested = period_len;
2624 fill_px(&desc->px, dst, src, period_len);
2625
2626 if (!first)
2627 first = desc;
2628 else
2629 list_add_tail(&desc->node, &first->node);
2630
2631 dma_addr += period_len;
2632 }
2633
2634 if (!desc)
2635 return NULL;
2636
2637 pch->cyclic = true;
2638 desc->txd.flags = flags;
2639
2640 return &desc->txd;
2641}
2642
2643static struct dma_async_tx_descriptor *
2644pl330_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dst,
2645 dma_addr_t src, size_t len, unsigned long flags)
2646{
2647 struct dma_pl330_desc *desc;
2648 struct dma_pl330_chan *pch = to_pchan(chan);
2649 struct pl330_dmac *pl330;
2650 int burst;
2651
2652 if (unlikely(!pch || !len))
2653 return NULL;
2654
2655 pl330 = pch->dmac;
2656
2657 desc = __pl330_prep_dma_memcpy(pch, dst, src, len);
2658 if (!desc)
2659 return NULL;
2660
2661 desc->rqcfg.src_inc = 1;
2662 desc->rqcfg.dst_inc = 1;
2663 desc->rqtype = DMA_MEM_TO_MEM;
2664
2665 /* Select max possible burst size */
2666 burst = pl330->pcfg.data_bus_width / 8;
2667
2668 /*
2669 * Make sure we use a burst size that aligns with all the memcpy
2670 * parameters because our DMA programming algorithm doesn't cope with
2671 * transfers which straddle an entry in the DMA device's MFIFO.
2672 */
2673 while ((src | dst | len) & (burst - 1))
2674 burst /= 2;
2675
2676 desc->rqcfg.brst_size = 0;
2677 while (burst != (1 << desc->rqcfg.brst_size))
2678 desc->rqcfg.brst_size++;
2679
2680 /*
2681 * If burst size is smaller than bus width then make sure we only
2682 * transfer one at a time to avoid a burst stradling an MFIFO entry.
2683 */
2684 if (desc->rqcfg.brst_size * 8 < pl330->pcfg.data_bus_width)
2685 desc->rqcfg.brst_len = 1;
2686
2687 desc->rqcfg.brst_len = get_burst_len(desc, len);
2688 desc->bytes_requested = len;
2689
2690 desc->txd.flags = flags;
2691
2692 return &desc->txd;
2693}
2694
2695static void __pl330_giveback_desc(struct pl330_dmac *pl330,
2696 struct dma_pl330_desc *first)
2697{
2698 unsigned long flags;
2699 struct dma_pl330_desc *desc;
2700
2701 if (!first)
2702 return;
2703
2704 spin_lock_irqsave(&pl330->pool_lock, flags);
2705
2706 while (!list_empty(&first->node)) {
2707 desc = list_entry(first->node.next,
2708 struct dma_pl330_desc, node);
2709 list_move_tail(&desc->node, &pl330->desc_pool);
2710 }
2711
2712 list_move_tail(&first->node, &pl330->desc_pool);
2713
2714 spin_unlock_irqrestore(&pl330->pool_lock, flags);
2715}
2716
2717static struct dma_async_tx_descriptor *
2718pl330_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
2719 unsigned int sg_len, enum dma_transfer_direction direction,
2720 unsigned long flg, void *context)
2721{
2722 struct dma_pl330_desc *first, *desc = NULL;
2723 struct dma_pl330_chan *pch = to_pchan(chan);
2724 struct scatterlist *sg;
2725 int i;
2726 dma_addr_t addr;
2727
2728 if (unlikely(!pch || !sgl || !sg_len))
2729 return NULL;
2730
2731 addr = pch->fifo_addr;
2732
2733 first = NULL;
2734
2735 for_each_sg(sgl, sg, sg_len, i) {
2736
2737 desc = pl330_get_desc(pch);
2738 if (!desc) {
2739 struct pl330_dmac *pl330 = pch->dmac;
2740
2741 dev_err(pch->dmac->ddma.dev,
2742 "%s:%d Unable to fetch desc\n",
2743 __func__, __LINE__);
2744 __pl330_giveback_desc(pl330, first);
2745
2746 return NULL;
2747 }
2748
2749 if (!first)
2750 first = desc;
2751 else
2752 list_add_tail(&desc->node, &first->node);
2753
2754 if (direction == DMA_MEM_TO_DEV) {
2755 desc->rqcfg.src_inc = 1;
2756 desc->rqcfg.dst_inc = 0;
2757 fill_px(&desc->px,
2758 addr, sg_dma_address(sg), sg_dma_len(sg));
2759 } else {
2760 desc->rqcfg.src_inc = 0;
2761 desc->rqcfg.dst_inc = 1;
2762 fill_px(&desc->px,
2763 sg_dma_address(sg), addr, sg_dma_len(sg));
2764 }
2765
2766 desc->rqcfg.brst_size = pch->burst_sz;
2767 desc->rqcfg.brst_len = 1;
2768 desc->rqtype = direction;
2769 desc->bytes_requested = sg_dma_len(sg);
2770 }
2771
2772 /* Return the last desc in the chain */
2773 desc->txd.flags = flg;
2774 return &desc->txd;
2775}
2776
2777static irqreturn_t pl330_irq_handler(int irq, void *data)
2778{
2779 if (pl330_update(data))
2780 return IRQ_HANDLED;
2781 else
2782 return IRQ_NONE;
2783}
2784
2785#define PL330_DMA_BUSWIDTHS \
2786 BIT(DMA_SLAVE_BUSWIDTH_UNDEFINED) | \
2787 BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | \
2788 BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | \
2789 BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) | \
2790 BIT(DMA_SLAVE_BUSWIDTH_8_BYTES)
2791
2792/*
2793 * Runtime PM callbacks are provided by amba/bus.c driver.
2794 *
2795 * It is assumed here that IRQ safe runtime PM is chosen in probe and amba
2796 * bus driver will only disable/enable the clock in runtime PM callbacks.
2797 */
2798static int __maybe_unused pl330_suspend(struct device *dev)
2799{
2800 struct amba_device *pcdev = to_amba_device(dev);
2801
2802 pm_runtime_disable(dev);
2803
2804 if (!pm_runtime_status_suspended(dev)) {
2805 /* amba did not disable the clock */
2806 amba_pclk_disable(pcdev);
2807 }
2808 amba_pclk_unprepare(pcdev);
2809
2810 return 0;
2811}
2812
2813static int __maybe_unused pl330_resume(struct device *dev)
2814{
2815 struct amba_device *pcdev = to_amba_device(dev);
2816 int ret;
2817
2818 ret = amba_pclk_prepare(pcdev);
2819 if (ret)
2820 return ret;
2821
2822 if (!pm_runtime_status_suspended(dev))
2823 ret = amba_pclk_enable(pcdev);
2824
2825 pm_runtime_enable(dev);
2826
2827 return ret;
2828}
2829
2830static SIMPLE_DEV_PM_OPS(pl330_pm, pl330_suspend, pl330_resume);
2831
2832static int
2833pl330_probe(struct amba_device *adev, const struct amba_id *id)
2834{
2835 struct dma_pl330_platdata *pdat;
2836 struct pl330_config *pcfg;
2837 struct pl330_dmac *pl330;
2838 struct dma_pl330_chan *pch, *_p;
2839 struct dma_device *pd;
2840 struct resource *res;
2841 int i, ret, irq;
2842 int num_chan;
2843 struct device_node *np = adev->dev.of_node;
2844
2845 pdat = dev_get_platdata(&adev->dev);
2846
2847 ret = dma_set_mask_and_coherent(&adev->dev, DMA_BIT_MASK(32));
2848 if (ret)
2849 return ret;
2850
2851 /* Allocate a new DMAC and its Channels */
2852 pl330 = devm_kzalloc(&adev->dev, sizeof(*pl330), GFP_KERNEL);
2853 if (!pl330)
2854 return -ENOMEM;
2855
2856 pd = &pl330->ddma;
2857 pd->dev = &adev->dev;
2858
2859 pl330->mcbufsz = pdat ? pdat->mcbuf_sz : 0;
2860
2861 /* get quirk */
2862 for (i = 0; i < ARRAY_SIZE(of_quirks); i++)
2863 if (of_property_read_bool(np, of_quirks[i].quirk))
2864 pl330->quirks |= of_quirks[i].id;
2865
2866 res = &adev->res;
2867 pl330->base = devm_ioremap_resource(&adev->dev, res);
2868 if (IS_ERR(pl330->base))
2869 return PTR_ERR(pl330->base);
2870
2871 amba_set_drvdata(adev, pl330);
2872
2873 for (i = 0; i < AMBA_NR_IRQS; i++) {
2874 irq = adev->irq[i];
2875 if (irq) {
2876 ret = devm_request_irq(&adev->dev, irq,
2877 pl330_irq_handler, 0,
2878 dev_name(&adev->dev), pl330);
2879 if (ret)
2880 return ret;
2881 } else {
2882 break;
2883 }
2884 }
2885
2886 pcfg = &pl330->pcfg;
2887
2888 pcfg->periph_id = adev->periphid;
2889 ret = pl330_add(pl330);
2890 if (ret)
2891 return ret;
2892
2893 INIT_LIST_HEAD(&pl330->desc_pool);
2894 spin_lock_init(&pl330->pool_lock);
2895
2896 /* Create a descriptor pool of default size */
2897 if (!add_desc(pl330, GFP_KERNEL, NR_DEFAULT_DESC))
2898 dev_warn(&adev->dev, "unable to allocate desc\n");
2899
2900 INIT_LIST_HEAD(&pd->channels);
2901
2902 /* Initialize channel parameters */
2903 if (pdat)
2904 num_chan = max_t(int, pdat->nr_valid_peri, pcfg->num_chan);
2905 else
2906 num_chan = max_t(int, pcfg->num_peri, pcfg->num_chan);
2907
2908 pl330->num_peripherals = num_chan;
2909
2910 pl330->peripherals = kzalloc(num_chan * sizeof(*pch), GFP_KERNEL);
2911 if (!pl330->peripherals) {
2912 ret = -ENOMEM;
2913 goto probe_err2;
2914 }
2915
2916 for (i = 0; i < num_chan; i++) {
2917 pch = &pl330->peripherals[i];
2918 if (!adev->dev.of_node)
2919 pch->chan.private = pdat ? &pdat->peri_id[i] : NULL;
2920 else
2921 pch->chan.private = adev->dev.of_node;
2922
2923 INIT_LIST_HEAD(&pch->submitted_list);
2924 INIT_LIST_HEAD(&pch->work_list);
2925 INIT_LIST_HEAD(&pch->completed_list);
2926 spin_lock_init(&pch->lock);
2927 pch->thread = NULL;
2928 pch->chan.device = pd;
2929 pch->dmac = pl330;
2930
2931 /* Add the channel to the DMAC list */
2932 list_add_tail(&pch->chan.device_node, &pd->channels);
2933 }
2934
2935 if (pdat) {
2936 pd->cap_mask = pdat->cap_mask;
2937 } else {
2938 dma_cap_set(DMA_MEMCPY, pd->cap_mask);
2939 if (pcfg->num_peri) {
2940 dma_cap_set(DMA_SLAVE, pd->cap_mask);
2941 dma_cap_set(DMA_CYCLIC, pd->cap_mask);
2942 dma_cap_set(DMA_PRIVATE, pd->cap_mask);
2943 }
2944 }
2945
2946 pd->device_alloc_chan_resources = pl330_alloc_chan_resources;
2947 pd->device_free_chan_resources = pl330_free_chan_resources;
2948 pd->device_prep_dma_memcpy = pl330_prep_dma_memcpy;
2949 pd->device_prep_dma_cyclic = pl330_prep_dma_cyclic;
2950 pd->device_tx_status = pl330_tx_status;
2951 pd->device_prep_slave_sg = pl330_prep_slave_sg;
2952 pd->device_config = pl330_config;
2953 pd->device_pause = pl330_pause;
2954 pd->device_terminate_all = pl330_terminate_all;
2955 pd->device_issue_pending = pl330_issue_pending;
2956 pd->src_addr_widths = PL330_DMA_BUSWIDTHS;
2957 pd->dst_addr_widths = PL330_DMA_BUSWIDTHS;
2958 pd->directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV);
2959 pd->residue_granularity = DMA_RESIDUE_GRANULARITY_SEGMENT;
2960 pd->max_burst = ((pl330->quirks & PL330_QUIRK_BROKEN_NO_FLUSHP) ?
2961 1 : PL330_MAX_BURST);
2962
2963 ret = dma_async_device_register(pd);
2964 if (ret) {
2965 dev_err(&adev->dev, "unable to register DMAC\n");
2966 goto probe_err3;
2967 }
2968
2969 if (adev->dev.of_node) {
2970 ret = of_dma_controller_register(adev->dev.of_node,
2971 of_dma_pl330_xlate, pl330);
2972 if (ret) {
2973 dev_err(&adev->dev,
2974 "unable to register DMA to the generic DT DMA helpers\n");
2975 }
2976 }
2977
2978 adev->dev.dma_parms = &pl330->dma_parms;
2979
2980 /*
2981 * This is the limit for transfers with a buswidth of 1, larger
2982 * buswidths will have larger limits.
2983 */
2984 ret = dma_set_max_seg_size(&adev->dev, 1900800);
2985 if (ret)
2986 dev_err(&adev->dev, "unable to set the seg size\n");
2987
2988
2989 dev_info(&adev->dev,
2990 "Loaded driver for PL330 DMAC-%x\n", adev->periphid);
2991 dev_info(&adev->dev,
2992 "\tDBUFF-%ux%ubytes Num_Chans-%u Num_Peri-%u Num_Events-%u\n",
2993 pcfg->data_buf_dep, pcfg->data_bus_width / 8, pcfg->num_chan,
2994 pcfg->num_peri, pcfg->num_events);
2995
2996 pm_runtime_irq_safe(&adev->dev);
2997 pm_runtime_use_autosuspend(&adev->dev);
2998 pm_runtime_set_autosuspend_delay(&adev->dev, PL330_AUTOSUSPEND_DELAY);
2999 pm_runtime_mark_last_busy(&adev->dev);
3000 pm_runtime_put_autosuspend(&adev->dev);
3001
3002 return 0;
3003probe_err3:
3004 /* Idle the DMAC */
3005 list_for_each_entry_safe(pch, _p, &pl330->ddma.channels,
3006 chan.device_node) {
3007
3008 /* Remove the channel */
3009 list_del(&pch->chan.device_node);
3010
3011 /* Flush the channel */
3012 if (pch->thread) {
3013 pl330_terminate_all(&pch->chan);
3014 pl330_free_chan_resources(&pch->chan);
3015 }
3016 }
3017probe_err2:
3018 pl330_del(pl330);
3019
3020 return ret;
3021}
3022
3023static int pl330_remove(struct amba_device *adev)
3024{
3025 struct pl330_dmac *pl330 = amba_get_drvdata(adev);
3026 struct dma_pl330_chan *pch, *_p;
3027 int i, irq;
3028
3029 pm_runtime_get_noresume(pl330->ddma.dev);
3030
3031 if (adev->dev.of_node)
3032 of_dma_controller_free(adev->dev.of_node);
3033
3034 for (i = 0; i < AMBA_NR_IRQS; i++) {
3035 irq = adev->irq[i];
3036 devm_free_irq(&adev->dev, irq, pl330);
3037 }
3038
3039 dma_async_device_unregister(&pl330->ddma);
3040
3041 /* Idle the DMAC */
3042 list_for_each_entry_safe(pch, _p, &pl330->ddma.channels,
3043 chan.device_node) {
3044
3045 /* Remove the channel */
3046 list_del(&pch->chan.device_node);
3047
3048 /* Flush the channel */
3049 if (pch->thread) {
3050 pl330_terminate_all(&pch->chan);
3051 pl330_free_chan_resources(&pch->chan);
3052 }
3053 }
3054
3055 pl330_del(pl330);
3056
3057 return 0;
3058}
3059
3060static struct amba_id pl330_ids[] = {
3061 {
3062 .id = 0x00041330,
3063 .mask = 0x000fffff,
3064 },
3065 { 0, 0 },
3066};
3067
3068MODULE_DEVICE_TABLE(amba, pl330_ids);
3069
3070static struct amba_driver pl330_driver = {
3071 .drv = {
3072 .owner = THIS_MODULE,
3073 .name = "dma-pl330",
3074 .pm = &pl330_pm,
3075 },
3076 .id_table = pl330_ids,
3077 .probe = pl330_probe,
3078 .remove = pl330_remove,
3079};
3080
3081module_amba_driver(pl330_driver);
3082
3083MODULE_AUTHOR("Jaswinder Singh <jassisinghbrar@gmail.com>");
3084MODULE_DESCRIPTION("API Driver for PL330 DMAC");
3085MODULE_LICENSE("GPL");