Loading...
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (c) 2015 MediaTek Inc.
4 * Author: Hanyi Wu <hanyi.wu@mediatek.com>
5 * Sascha Hauer <s.hauer@pengutronix.de>
6 * Dawei Chien <dawei.chien@mediatek.com>
7 * Louis Yu <louis.yu@mediatek.com>
8 */
9
10#include <linux/clk.h>
11#include <linux/delay.h>
12#include <linux/interrupt.h>
13#include <linux/kernel.h>
14#include <linux/module.h>
15#include <linux/nvmem-consumer.h>
16#include <linux/of.h>
17#include <linux/of_address.h>
18#include <linux/of_device.h>
19#include <linux/platform_device.h>
20#include <linux/slab.h>
21#include <linux/io.h>
22#include <linux/thermal.h>
23#include <linux/reset.h>
24#include <linux/types.h>
25
26/* AUXADC Registers */
27#define AUXADC_CON1_SET_V 0x008
28#define AUXADC_CON1_CLR_V 0x00c
29#define AUXADC_CON2_V 0x010
30#define AUXADC_DATA(channel) (0x14 + (channel) * 4)
31
32#define APMIXED_SYS_TS_CON1 0x604
33
34/* Thermal Controller Registers */
35#define TEMP_MONCTL0 0x000
36#define TEMP_MONCTL1 0x004
37#define TEMP_MONCTL2 0x008
38#define TEMP_MONIDET0 0x014
39#define TEMP_MONIDET1 0x018
40#define TEMP_MSRCTL0 0x038
41#define TEMP_MSRCTL1 0x03c
42#define TEMP_AHBPOLL 0x040
43#define TEMP_AHBTO 0x044
44#define TEMP_ADCPNP0 0x048
45#define TEMP_ADCPNP1 0x04c
46#define TEMP_ADCPNP2 0x050
47#define TEMP_ADCPNP3 0x0b4
48
49#define TEMP_ADCMUX 0x054
50#define TEMP_ADCEN 0x060
51#define TEMP_PNPMUXADDR 0x064
52#define TEMP_ADCMUXADDR 0x068
53#define TEMP_ADCENADDR 0x074
54#define TEMP_ADCVALIDADDR 0x078
55#define TEMP_ADCVOLTADDR 0x07c
56#define TEMP_RDCTRL 0x080
57#define TEMP_ADCVALIDMASK 0x084
58#define TEMP_ADCVOLTAGESHIFT 0x088
59#define TEMP_ADCWRITECTRL 0x08c
60#define TEMP_MSR0 0x090
61#define TEMP_MSR1 0x094
62#define TEMP_MSR2 0x098
63#define TEMP_MSR3 0x0B8
64
65#define TEMP_SPARE0 0x0f0
66
67#define TEMP_ADCPNP0_1 0x148
68#define TEMP_ADCPNP1_1 0x14c
69#define TEMP_ADCPNP2_1 0x150
70#define TEMP_MSR0_1 0x190
71#define TEMP_MSR1_1 0x194
72#define TEMP_MSR2_1 0x198
73#define TEMP_ADCPNP3_1 0x1b4
74#define TEMP_MSR3_1 0x1B8
75
76#define PTPCORESEL 0x400
77
78#define TEMP_MONCTL1_PERIOD_UNIT(x) ((x) & 0x3ff)
79
80#define TEMP_MONCTL2_FILTER_INTERVAL(x) (((x) & 0x3ff) << 16)
81#define TEMP_MONCTL2_SENSOR_INTERVAL(x) ((x) & 0x3ff)
82
83#define TEMP_AHBPOLL_ADC_POLL_INTERVAL(x) (x)
84
85#define TEMP_ADCWRITECTRL_ADC_PNP_WRITE BIT(0)
86#define TEMP_ADCWRITECTRL_ADC_MUX_WRITE BIT(1)
87
88#define TEMP_ADCVALIDMASK_VALID_HIGH BIT(5)
89#define TEMP_ADCVALIDMASK_VALID_POS(bit) (bit)
90
91/* MT8173 thermal sensors */
92#define MT8173_TS1 0
93#define MT8173_TS2 1
94#define MT8173_TS3 2
95#define MT8173_TS4 3
96#define MT8173_TSABB 4
97
98/* AUXADC channel 11 is used for the temperature sensors */
99#define MT8173_TEMP_AUXADC_CHANNEL 11
100
101/* The total number of temperature sensors in the MT8173 */
102#define MT8173_NUM_SENSORS 5
103
104/* The number of banks in the MT8173 */
105#define MT8173_NUM_ZONES 4
106
107/* The number of sensing points per bank */
108#define MT8173_NUM_SENSORS_PER_ZONE 4
109
110/* The number of controller in the MT8173 */
111#define MT8173_NUM_CONTROLLER 1
112
113/* The calibration coefficient of sensor */
114#define MT8173_CALIBRATION 165
115
116/*
117 * Layout of the fuses providing the calibration data
118 * These macros could be used for MT8183, MT8173, MT2701, and MT2712.
119 * MT8183 has 6 sensors and needs 6 VTS calibration data.
120 * MT8173 has 5 sensors and needs 5 VTS calibration data.
121 * MT2701 has 3 sensors and needs 3 VTS calibration data.
122 * MT2712 has 4 sensors and needs 4 VTS calibration data.
123 */
124#define CALIB_BUF0_VALID_V1 BIT(0)
125#define CALIB_BUF1_ADC_GE_V1(x) (((x) >> 22) & 0x3ff)
126#define CALIB_BUF0_VTS_TS1_V1(x) (((x) >> 17) & 0x1ff)
127#define CALIB_BUF0_VTS_TS2_V1(x) (((x) >> 8) & 0x1ff)
128#define CALIB_BUF1_VTS_TS3_V1(x) (((x) >> 0) & 0x1ff)
129#define CALIB_BUF2_VTS_TS4_V1(x) (((x) >> 23) & 0x1ff)
130#define CALIB_BUF2_VTS_TS5_V1(x) (((x) >> 5) & 0x1ff)
131#define CALIB_BUF2_VTS_TSABB_V1(x) (((x) >> 14) & 0x1ff)
132#define CALIB_BUF0_DEGC_CALI_V1(x) (((x) >> 1) & 0x3f)
133#define CALIB_BUF0_O_SLOPE_V1(x) (((x) >> 26) & 0x3f)
134#define CALIB_BUF0_O_SLOPE_SIGN_V1(x) (((x) >> 7) & 0x1)
135#define CALIB_BUF1_ID_V1(x) (((x) >> 9) & 0x1)
136
137/*
138 * Layout of the fuses providing the calibration data
139 * These macros could be used for MT7622.
140 */
141#define CALIB_BUF0_ADC_OE_V2(x) (((x) >> 22) & 0x3ff)
142#define CALIB_BUF0_ADC_GE_V2(x) (((x) >> 12) & 0x3ff)
143#define CALIB_BUF0_DEGC_CALI_V2(x) (((x) >> 6) & 0x3f)
144#define CALIB_BUF0_O_SLOPE_V2(x) (((x) >> 0) & 0x3f)
145#define CALIB_BUF1_VTS_TS1_V2(x) (((x) >> 23) & 0x1ff)
146#define CALIB_BUF1_VTS_TS2_V2(x) (((x) >> 14) & 0x1ff)
147#define CALIB_BUF1_VTS_TSABB_V2(x) (((x) >> 5) & 0x1ff)
148#define CALIB_BUF1_VALID_V2(x) (((x) >> 4) & 0x1)
149#define CALIB_BUF1_O_SLOPE_SIGN_V2(x) (((x) >> 3) & 0x1)
150
151enum {
152 VTS1,
153 VTS2,
154 VTS3,
155 VTS4,
156 VTS5,
157 VTSABB,
158 MAX_NUM_VTS,
159};
160
161enum mtk_thermal_version {
162 MTK_THERMAL_V1 = 1,
163 MTK_THERMAL_V2,
164};
165
166/* MT2701 thermal sensors */
167#define MT2701_TS1 0
168#define MT2701_TS2 1
169#define MT2701_TSABB 2
170
171/* AUXADC channel 11 is used for the temperature sensors */
172#define MT2701_TEMP_AUXADC_CHANNEL 11
173
174/* The total number of temperature sensors in the MT2701 */
175#define MT2701_NUM_SENSORS 3
176
177/* The number of sensing points per bank */
178#define MT2701_NUM_SENSORS_PER_ZONE 3
179
180/* The number of controller in the MT2701 */
181#define MT2701_NUM_CONTROLLER 1
182
183/* The calibration coefficient of sensor */
184#define MT2701_CALIBRATION 165
185
186/* MT2712 thermal sensors */
187#define MT2712_TS1 0
188#define MT2712_TS2 1
189#define MT2712_TS3 2
190#define MT2712_TS4 3
191
192/* AUXADC channel 11 is used for the temperature sensors */
193#define MT2712_TEMP_AUXADC_CHANNEL 11
194
195/* The total number of temperature sensors in the MT2712 */
196#define MT2712_NUM_SENSORS 4
197
198/* The number of sensing points per bank */
199#define MT2712_NUM_SENSORS_PER_ZONE 4
200
201/* The number of controller in the MT2712 */
202#define MT2712_NUM_CONTROLLER 1
203
204/* The calibration coefficient of sensor */
205#define MT2712_CALIBRATION 165
206
207#define MT7622_TEMP_AUXADC_CHANNEL 11
208#define MT7622_NUM_SENSORS 1
209#define MT7622_NUM_ZONES 1
210#define MT7622_NUM_SENSORS_PER_ZONE 1
211#define MT7622_TS1 0
212#define MT7622_NUM_CONTROLLER 1
213
214/* The maximum number of banks */
215#define MAX_NUM_ZONES 8
216
217/* The calibration coefficient of sensor */
218#define MT7622_CALIBRATION 165
219
220/* MT8183 thermal sensors */
221#define MT8183_TS1 0
222#define MT8183_TS2 1
223#define MT8183_TS3 2
224#define MT8183_TS4 3
225#define MT8183_TS5 4
226#define MT8183_TSABB 5
227
228/* AUXADC channel is used for the temperature sensors */
229#define MT8183_TEMP_AUXADC_CHANNEL 11
230
231/* The total number of temperature sensors in the MT8183 */
232#define MT8183_NUM_SENSORS 6
233
234/* The number of banks in the MT8183 */
235#define MT8183_NUM_ZONES 1
236
237/* The number of sensing points per bank */
238#define MT8183_NUM_SENSORS_PER_ZONE 6
239
240/* The number of controller in the MT8183 */
241#define MT8183_NUM_CONTROLLER 2
242
243/* The calibration coefficient of sensor */
244#define MT8183_CALIBRATION 153
245
246struct mtk_thermal;
247
248struct thermal_bank_cfg {
249 unsigned int num_sensors;
250 const int *sensors;
251};
252
253struct mtk_thermal_bank {
254 struct mtk_thermal *mt;
255 int id;
256};
257
258struct mtk_thermal_data {
259 s32 num_banks;
260 s32 num_sensors;
261 s32 auxadc_channel;
262 const int *vts_index;
263 const int *sensor_mux_values;
264 const int *msr;
265 const int *adcpnp;
266 const int cali_val;
267 const int num_controller;
268 const int *controller_offset;
269 bool need_switch_bank;
270 struct thermal_bank_cfg bank_data[MAX_NUM_ZONES];
271 enum mtk_thermal_version version;
272};
273
274struct mtk_thermal {
275 struct device *dev;
276 void __iomem *thermal_base;
277
278 struct clk *clk_peri_therm;
279 struct clk *clk_auxadc;
280 /* lock: for getting and putting banks */
281 struct mutex lock;
282
283 /* Calibration values */
284 s32 adc_ge;
285 s32 adc_oe;
286 s32 degc_cali;
287 s32 o_slope;
288 s32 o_slope_sign;
289 s32 vts[MAX_NUM_VTS];
290
291 const struct mtk_thermal_data *conf;
292 struct mtk_thermal_bank banks[MAX_NUM_ZONES];
293};
294
295/* MT8183 thermal sensor data */
296static const int mt8183_bank_data[MT8183_NUM_SENSORS] = {
297 MT8183_TS1, MT8183_TS2, MT8183_TS3, MT8183_TS4, MT8183_TS5, MT8183_TSABB
298};
299
300static const int mt8183_msr[MT8183_NUM_SENSORS_PER_ZONE] = {
301 TEMP_MSR0_1, TEMP_MSR1_1, TEMP_MSR2_1, TEMP_MSR1, TEMP_MSR0, TEMP_MSR3_1
302};
303
304static const int mt8183_adcpnp[MT8183_NUM_SENSORS_PER_ZONE] = {
305 TEMP_ADCPNP0_1, TEMP_ADCPNP1_1, TEMP_ADCPNP2_1,
306 TEMP_ADCPNP1, TEMP_ADCPNP0, TEMP_ADCPNP3_1
307};
308
309static const int mt8183_mux_values[MT8183_NUM_SENSORS] = { 0, 1, 2, 3, 4, 0 };
310static const int mt8183_tc_offset[MT8183_NUM_CONTROLLER] = {0x0, 0x100};
311
312static const int mt8183_vts_index[MT8183_NUM_SENSORS] = {
313 VTS1, VTS2, VTS3, VTS4, VTS5, VTSABB
314};
315
316/* MT8173 thermal sensor data */
317static const int mt8173_bank_data[MT8173_NUM_ZONES][3] = {
318 { MT8173_TS2, MT8173_TS3 },
319 { MT8173_TS2, MT8173_TS4 },
320 { MT8173_TS1, MT8173_TS2, MT8173_TSABB },
321 { MT8173_TS2 },
322};
323
324static const int mt8173_msr[MT8173_NUM_SENSORS_PER_ZONE] = {
325 TEMP_MSR0, TEMP_MSR1, TEMP_MSR2, TEMP_MSR3
326};
327
328static const int mt8173_adcpnp[MT8173_NUM_SENSORS_PER_ZONE] = {
329 TEMP_ADCPNP0, TEMP_ADCPNP1, TEMP_ADCPNP2, TEMP_ADCPNP3
330};
331
332static const int mt8173_mux_values[MT8173_NUM_SENSORS] = { 0, 1, 2, 3, 16 };
333static const int mt8173_tc_offset[MT8173_NUM_CONTROLLER] = { 0x0, };
334
335static const int mt8173_vts_index[MT8173_NUM_SENSORS] = {
336 VTS1, VTS2, VTS3, VTS4, VTSABB
337};
338
339/* MT2701 thermal sensor data */
340static const int mt2701_bank_data[MT2701_NUM_SENSORS] = {
341 MT2701_TS1, MT2701_TS2, MT2701_TSABB
342};
343
344static const int mt2701_msr[MT2701_NUM_SENSORS_PER_ZONE] = {
345 TEMP_MSR0, TEMP_MSR1, TEMP_MSR2
346};
347
348static const int mt2701_adcpnp[MT2701_NUM_SENSORS_PER_ZONE] = {
349 TEMP_ADCPNP0, TEMP_ADCPNP1, TEMP_ADCPNP2
350};
351
352static const int mt2701_mux_values[MT2701_NUM_SENSORS] = { 0, 1, 16 };
353static const int mt2701_tc_offset[MT2701_NUM_CONTROLLER] = { 0x0, };
354
355static const int mt2701_vts_index[MT2701_NUM_SENSORS] = {
356 VTS1, VTS2, VTS3
357};
358
359/* MT2712 thermal sensor data */
360static const int mt2712_bank_data[MT2712_NUM_SENSORS] = {
361 MT2712_TS1, MT2712_TS2, MT2712_TS3, MT2712_TS4
362};
363
364static const int mt2712_msr[MT2712_NUM_SENSORS_PER_ZONE] = {
365 TEMP_MSR0, TEMP_MSR1, TEMP_MSR2, TEMP_MSR3
366};
367
368static const int mt2712_adcpnp[MT2712_NUM_SENSORS_PER_ZONE] = {
369 TEMP_ADCPNP0, TEMP_ADCPNP1, TEMP_ADCPNP2, TEMP_ADCPNP3
370};
371
372static const int mt2712_mux_values[MT2712_NUM_SENSORS] = { 0, 1, 2, 3 };
373static const int mt2712_tc_offset[MT2712_NUM_CONTROLLER] = { 0x0, };
374
375static const int mt2712_vts_index[MT2712_NUM_SENSORS] = {
376 VTS1, VTS2, VTS3, VTS4
377};
378
379/* MT7622 thermal sensor data */
380static const int mt7622_bank_data[MT7622_NUM_SENSORS] = { MT7622_TS1, };
381static const int mt7622_msr[MT7622_NUM_SENSORS_PER_ZONE] = { TEMP_MSR0, };
382static const int mt7622_adcpnp[MT7622_NUM_SENSORS_PER_ZONE] = { TEMP_ADCPNP0, };
383static const int mt7622_mux_values[MT7622_NUM_SENSORS] = { 0, };
384static const int mt7622_vts_index[MT7622_NUM_SENSORS] = { VTS1 };
385static const int mt7622_tc_offset[MT7622_NUM_CONTROLLER] = { 0x0, };
386
387/*
388 * The MT8173 thermal controller has four banks. Each bank can read up to
389 * four temperature sensors simultaneously. The MT8173 has a total of 5
390 * temperature sensors. We use each bank to measure a certain area of the
391 * SoC. Since TS2 is located centrally in the SoC it is influenced by multiple
392 * areas, hence is used in different banks.
393 *
394 * The thermal core only gets the maximum temperature of all banks, so
395 * the bank concept wouldn't be necessary here. However, the SVS (Smart
396 * Voltage Scaling) unit makes its decisions based on the same bank
397 * data, and this indeed needs the temperatures of the individual banks
398 * for making better decisions.
399 */
400static const struct mtk_thermal_data mt8173_thermal_data = {
401 .auxadc_channel = MT8173_TEMP_AUXADC_CHANNEL,
402 .num_banks = MT8173_NUM_ZONES,
403 .num_sensors = MT8173_NUM_SENSORS,
404 .vts_index = mt8173_vts_index,
405 .cali_val = MT8173_CALIBRATION,
406 .num_controller = MT8173_NUM_CONTROLLER,
407 .controller_offset = mt8173_tc_offset,
408 .need_switch_bank = true,
409 .bank_data = {
410 {
411 .num_sensors = 2,
412 .sensors = mt8173_bank_data[0],
413 }, {
414 .num_sensors = 2,
415 .sensors = mt8173_bank_data[1],
416 }, {
417 .num_sensors = 3,
418 .sensors = mt8173_bank_data[2],
419 }, {
420 .num_sensors = 1,
421 .sensors = mt8173_bank_data[3],
422 },
423 },
424 .msr = mt8173_msr,
425 .adcpnp = mt8173_adcpnp,
426 .sensor_mux_values = mt8173_mux_values,
427 .version = MTK_THERMAL_V1,
428};
429
430/*
431 * The MT2701 thermal controller has one bank, which can read up to
432 * three temperature sensors simultaneously. The MT2701 has a total of 3
433 * temperature sensors.
434 *
435 * The thermal core only gets the maximum temperature of this one bank,
436 * so the bank concept wouldn't be necessary here. However, the SVS (Smart
437 * Voltage Scaling) unit makes its decisions based on the same bank
438 * data.
439 */
440static const struct mtk_thermal_data mt2701_thermal_data = {
441 .auxadc_channel = MT2701_TEMP_AUXADC_CHANNEL,
442 .num_banks = 1,
443 .num_sensors = MT2701_NUM_SENSORS,
444 .vts_index = mt2701_vts_index,
445 .cali_val = MT2701_CALIBRATION,
446 .num_controller = MT2701_NUM_CONTROLLER,
447 .controller_offset = mt2701_tc_offset,
448 .need_switch_bank = true,
449 .bank_data = {
450 {
451 .num_sensors = 3,
452 .sensors = mt2701_bank_data,
453 },
454 },
455 .msr = mt2701_msr,
456 .adcpnp = mt2701_adcpnp,
457 .sensor_mux_values = mt2701_mux_values,
458 .version = MTK_THERMAL_V1,
459};
460
461/*
462 * The MT2712 thermal controller has one bank, which can read up to
463 * four temperature sensors simultaneously. The MT2712 has a total of 4
464 * temperature sensors.
465 *
466 * The thermal core only gets the maximum temperature of this one bank,
467 * so the bank concept wouldn't be necessary here. However, the SVS (Smart
468 * Voltage Scaling) unit makes its decisions based on the same bank
469 * data.
470 */
471static const struct mtk_thermal_data mt2712_thermal_data = {
472 .auxadc_channel = MT2712_TEMP_AUXADC_CHANNEL,
473 .num_banks = 1,
474 .num_sensors = MT2712_NUM_SENSORS,
475 .vts_index = mt2712_vts_index,
476 .cali_val = MT2712_CALIBRATION,
477 .num_controller = MT2712_NUM_CONTROLLER,
478 .controller_offset = mt2712_tc_offset,
479 .need_switch_bank = true,
480 .bank_data = {
481 {
482 .num_sensors = 4,
483 .sensors = mt2712_bank_data,
484 },
485 },
486 .msr = mt2712_msr,
487 .adcpnp = mt2712_adcpnp,
488 .sensor_mux_values = mt2712_mux_values,
489 .version = MTK_THERMAL_V1,
490};
491
492/*
493 * MT7622 have only one sensing point which uses AUXADC Channel 11 for raw data
494 * access.
495 */
496static const struct mtk_thermal_data mt7622_thermal_data = {
497 .auxadc_channel = MT7622_TEMP_AUXADC_CHANNEL,
498 .num_banks = MT7622_NUM_ZONES,
499 .num_sensors = MT7622_NUM_SENSORS,
500 .vts_index = mt7622_vts_index,
501 .cali_val = MT7622_CALIBRATION,
502 .num_controller = MT7622_NUM_CONTROLLER,
503 .controller_offset = mt7622_tc_offset,
504 .need_switch_bank = true,
505 .bank_data = {
506 {
507 .num_sensors = 1,
508 .sensors = mt7622_bank_data,
509 },
510 },
511 .msr = mt7622_msr,
512 .adcpnp = mt7622_adcpnp,
513 .sensor_mux_values = mt7622_mux_values,
514 .version = MTK_THERMAL_V2,
515};
516
517/*
518 * The MT8183 thermal controller has one bank for the current SW framework.
519 * The MT8183 has a total of 6 temperature sensors.
520 * There are two thermal controller to control the six sensor.
521 * The first one bind 2 sensor, and the other bind 4 sensors.
522 * The thermal core only gets the maximum temperature of all sensor, so
523 * the bank concept wouldn't be necessary here. However, the SVS (Smart
524 * Voltage Scaling) unit makes its decisions based on the same bank
525 * data, and this indeed needs the temperatures of the individual banks
526 * for making better decisions.
527 */
528static const struct mtk_thermal_data mt8183_thermal_data = {
529 .auxadc_channel = MT8183_TEMP_AUXADC_CHANNEL,
530 .num_banks = MT8183_NUM_ZONES,
531 .num_sensors = MT8183_NUM_SENSORS,
532 .vts_index = mt8183_vts_index,
533 .cali_val = MT8183_CALIBRATION,
534 .num_controller = MT8183_NUM_CONTROLLER,
535 .controller_offset = mt8183_tc_offset,
536 .need_switch_bank = false,
537 .bank_data = {
538 {
539 .num_sensors = 6,
540 .sensors = mt8183_bank_data,
541 },
542 },
543
544 .msr = mt8183_msr,
545 .adcpnp = mt8183_adcpnp,
546 .sensor_mux_values = mt8183_mux_values,
547 .version = MTK_THERMAL_V1,
548};
549
550/**
551 * raw_to_mcelsius - convert a raw ADC value to mcelsius
552 * @mt: The thermal controller
553 * @sensno: sensor number
554 * @raw: raw ADC value
555 *
556 * This converts the raw ADC value to mcelsius using the SoC specific
557 * calibration constants
558 */
559static int raw_to_mcelsius_v1(struct mtk_thermal *mt, int sensno, s32 raw)
560{
561 s32 tmp;
562
563 raw &= 0xfff;
564
565 tmp = 203450520 << 3;
566 tmp /= mt->conf->cali_val + mt->o_slope;
567 tmp /= 10000 + mt->adc_ge;
568 tmp *= raw - mt->vts[sensno] - 3350;
569 tmp >>= 3;
570
571 return mt->degc_cali * 500 - tmp;
572}
573
574static int raw_to_mcelsius_v2(struct mtk_thermal *mt, int sensno, s32 raw)
575{
576 s32 format_1 = 0;
577 s32 format_2 = 0;
578 s32 g_oe = 1;
579 s32 g_gain = 1;
580 s32 g_x_roomt = 0;
581 s32 tmp = 0;
582
583 if (raw == 0)
584 return 0;
585
586 raw &= 0xfff;
587 g_gain = 10000 + (((mt->adc_ge - 512) * 10000) >> 12);
588 g_oe = mt->adc_oe - 512;
589 format_1 = mt->vts[VTS2] + 3105 - g_oe;
590 format_2 = (mt->degc_cali * 10) >> 1;
591 g_x_roomt = (((format_1 * 10000) >> 12) * 10000) / g_gain;
592
593 tmp = (((((raw - g_oe) * 10000) >> 12) * 10000) / g_gain) - g_x_roomt;
594 tmp = tmp * 10 * 100 / 11;
595
596 if (mt->o_slope_sign == 0)
597 tmp = tmp / (165 - mt->o_slope);
598 else
599 tmp = tmp / (165 + mt->o_slope);
600
601 return (format_2 - tmp) * 100;
602}
603
604/**
605 * mtk_thermal_get_bank - get bank
606 * @bank: The bank
607 *
608 * The bank registers are banked, we have to select a bank in the
609 * PTPCORESEL register to access it.
610 */
611static void mtk_thermal_get_bank(struct mtk_thermal_bank *bank)
612{
613 struct mtk_thermal *mt = bank->mt;
614 u32 val;
615
616 if (mt->conf->need_switch_bank) {
617 mutex_lock(&mt->lock);
618
619 val = readl(mt->thermal_base + PTPCORESEL);
620 val &= ~0xf;
621 val |= bank->id;
622 writel(val, mt->thermal_base + PTPCORESEL);
623 }
624}
625
626/**
627 * mtk_thermal_put_bank - release bank
628 * @bank: The bank
629 *
630 * release a bank previously taken with mtk_thermal_get_bank,
631 */
632static void mtk_thermal_put_bank(struct mtk_thermal_bank *bank)
633{
634 struct mtk_thermal *mt = bank->mt;
635
636 if (mt->conf->need_switch_bank)
637 mutex_unlock(&mt->lock);
638}
639
640/**
641 * mtk_thermal_bank_temperature - get the temperature of a bank
642 * @bank: The bank
643 *
644 * The temperature of a bank is considered the maximum temperature of
645 * the sensors associated to the bank.
646 */
647static int mtk_thermal_bank_temperature(struct mtk_thermal_bank *bank)
648{
649 struct mtk_thermal *mt = bank->mt;
650 const struct mtk_thermal_data *conf = mt->conf;
651 int i, temp = INT_MIN, max = INT_MIN;
652 u32 raw;
653
654 for (i = 0; i < conf->bank_data[bank->id].num_sensors; i++) {
655 raw = readl(mt->thermal_base + conf->msr[i]);
656
657 if (mt->conf->version == MTK_THERMAL_V1) {
658 temp = raw_to_mcelsius_v1(
659 mt, conf->bank_data[bank->id].sensors[i], raw);
660 } else {
661 temp = raw_to_mcelsius_v2(
662 mt, conf->bank_data[bank->id].sensors[i], raw);
663 }
664
665 /*
666 * The first read of a sensor often contains very high bogus
667 * temperature value. Filter these out so that the system does
668 * not immediately shut down.
669 */
670 if (temp > 200000)
671 temp = 0;
672
673 if (temp > max)
674 max = temp;
675 }
676
677 return max;
678}
679
680static int mtk_read_temp(void *data, int *temperature)
681{
682 struct mtk_thermal *mt = data;
683 int i;
684 int tempmax = INT_MIN;
685
686 for (i = 0; i < mt->conf->num_banks; i++) {
687 struct mtk_thermal_bank *bank = &mt->banks[i];
688
689 mtk_thermal_get_bank(bank);
690
691 tempmax = max(tempmax, mtk_thermal_bank_temperature(bank));
692
693 mtk_thermal_put_bank(bank);
694 }
695
696 *temperature = tempmax;
697
698 return 0;
699}
700
701static const struct thermal_zone_of_device_ops mtk_thermal_ops = {
702 .get_temp = mtk_read_temp,
703};
704
705static void mtk_thermal_init_bank(struct mtk_thermal *mt, int num,
706 u32 apmixed_phys_base, u32 auxadc_phys_base,
707 int ctrl_id)
708{
709 struct mtk_thermal_bank *bank = &mt->banks[num];
710 const struct mtk_thermal_data *conf = mt->conf;
711 int i;
712
713 int offset = mt->conf->controller_offset[ctrl_id];
714 void __iomem *controller_base = mt->thermal_base + offset;
715
716 bank->id = num;
717 bank->mt = mt;
718
719 mtk_thermal_get_bank(bank);
720
721 /* bus clock 66M counting unit is 12 * 15.15ns * 256 = 46.540us */
722 writel(TEMP_MONCTL1_PERIOD_UNIT(12), controller_base + TEMP_MONCTL1);
723
724 /*
725 * filt interval is 1 * 46.540us = 46.54us,
726 * sen interval is 429 * 46.540us = 19.96ms
727 */
728 writel(TEMP_MONCTL2_FILTER_INTERVAL(1) |
729 TEMP_MONCTL2_SENSOR_INTERVAL(429),
730 controller_base + TEMP_MONCTL2);
731
732 /* poll is set to 10u */
733 writel(TEMP_AHBPOLL_ADC_POLL_INTERVAL(768),
734 controller_base + TEMP_AHBPOLL);
735
736 /* temperature sampling control, 1 sample */
737 writel(0x0, controller_base + TEMP_MSRCTL0);
738
739 /* exceed this polling time, IRQ would be inserted */
740 writel(0xffffffff, controller_base + TEMP_AHBTO);
741
742 /* number of interrupts per event, 1 is enough */
743 writel(0x0, controller_base + TEMP_MONIDET0);
744 writel(0x0, controller_base + TEMP_MONIDET1);
745
746 /*
747 * The MT8173 thermal controller does not have its own ADC. Instead it
748 * uses AHB bus accesses to control the AUXADC. To do this the thermal
749 * controller has to be programmed with the physical addresses of the
750 * AUXADC registers and with the various bit positions in the AUXADC.
751 * Also the thermal controller controls a mux in the APMIXEDSYS register
752 * space.
753 */
754
755 /*
756 * this value will be stored to TEMP_PNPMUXADDR (TEMP_SPARE0)
757 * automatically by hw
758 */
759 writel(BIT(conf->auxadc_channel), controller_base + TEMP_ADCMUX);
760
761 /* AHB address for auxadc mux selection */
762 writel(auxadc_phys_base + AUXADC_CON1_CLR_V,
763 controller_base + TEMP_ADCMUXADDR);
764
765 if (mt->conf->version == MTK_THERMAL_V1) {
766 /* AHB address for pnp sensor mux selection */
767 writel(apmixed_phys_base + APMIXED_SYS_TS_CON1,
768 controller_base + TEMP_PNPMUXADDR);
769 }
770
771 /* AHB value for auxadc enable */
772 writel(BIT(conf->auxadc_channel), controller_base + TEMP_ADCEN);
773
774 /* AHB address for auxadc enable (channel 0 immediate mode selected) */
775 writel(auxadc_phys_base + AUXADC_CON1_SET_V,
776 controller_base + TEMP_ADCENADDR);
777
778 /* AHB address for auxadc valid bit */
779 writel(auxadc_phys_base + AUXADC_DATA(conf->auxadc_channel),
780 controller_base + TEMP_ADCVALIDADDR);
781
782 /* AHB address for auxadc voltage output */
783 writel(auxadc_phys_base + AUXADC_DATA(conf->auxadc_channel),
784 controller_base + TEMP_ADCVOLTADDR);
785
786 /* read valid & voltage are at the same register */
787 writel(0x0, controller_base + TEMP_RDCTRL);
788
789 /* indicate where the valid bit is */
790 writel(TEMP_ADCVALIDMASK_VALID_HIGH | TEMP_ADCVALIDMASK_VALID_POS(12),
791 controller_base + TEMP_ADCVALIDMASK);
792
793 /* no shift */
794 writel(0x0, controller_base + TEMP_ADCVOLTAGESHIFT);
795
796 /* enable auxadc mux write transaction */
797 writel(TEMP_ADCWRITECTRL_ADC_MUX_WRITE,
798 controller_base + TEMP_ADCWRITECTRL);
799
800 for (i = 0; i < conf->bank_data[num].num_sensors; i++)
801 writel(conf->sensor_mux_values[conf->bank_data[num].sensors[i]],
802 mt->thermal_base + conf->adcpnp[i]);
803
804 writel((1 << conf->bank_data[num].num_sensors) - 1,
805 controller_base + TEMP_MONCTL0);
806
807 writel(TEMP_ADCWRITECTRL_ADC_PNP_WRITE |
808 TEMP_ADCWRITECTRL_ADC_MUX_WRITE,
809 controller_base + TEMP_ADCWRITECTRL);
810
811 mtk_thermal_put_bank(bank);
812}
813
814static u64 of_get_phys_base(struct device_node *np)
815{
816 u64 size64;
817 const __be32 *regaddr_p;
818
819 regaddr_p = of_get_address(np, 0, &size64, NULL);
820 if (!regaddr_p)
821 return OF_BAD_ADDR;
822
823 return of_translate_address(np, regaddr_p);
824}
825
826static int mtk_thermal_extract_efuse_v1(struct mtk_thermal *mt, u32 *buf)
827{
828 int i;
829
830 if (!(buf[0] & CALIB_BUF0_VALID_V1))
831 return -EINVAL;
832
833 mt->adc_ge = CALIB_BUF1_ADC_GE_V1(buf[1]);
834
835 for (i = 0; i < mt->conf->num_sensors; i++) {
836 switch (mt->conf->vts_index[i]) {
837 case VTS1:
838 mt->vts[VTS1] = CALIB_BUF0_VTS_TS1_V1(buf[0]);
839 break;
840 case VTS2:
841 mt->vts[VTS2] = CALIB_BUF0_VTS_TS2_V1(buf[0]);
842 break;
843 case VTS3:
844 mt->vts[VTS3] = CALIB_BUF1_VTS_TS3_V1(buf[1]);
845 break;
846 case VTS4:
847 mt->vts[VTS4] = CALIB_BUF2_VTS_TS4_V1(buf[2]);
848 break;
849 case VTS5:
850 mt->vts[VTS5] = CALIB_BUF2_VTS_TS5_V1(buf[2]);
851 break;
852 case VTSABB:
853 mt->vts[VTSABB] =
854 CALIB_BUF2_VTS_TSABB_V1(buf[2]);
855 break;
856 default:
857 break;
858 }
859 }
860
861 mt->degc_cali = CALIB_BUF0_DEGC_CALI_V1(buf[0]);
862 if (CALIB_BUF1_ID_V1(buf[1]) &
863 CALIB_BUF0_O_SLOPE_SIGN_V1(buf[0]))
864 mt->o_slope = -CALIB_BUF0_O_SLOPE_V1(buf[0]);
865 else
866 mt->o_slope = CALIB_BUF0_O_SLOPE_V1(buf[0]);
867
868 return 0;
869}
870
871static int mtk_thermal_extract_efuse_v2(struct mtk_thermal *mt, u32 *buf)
872{
873 if (!CALIB_BUF1_VALID_V2(buf[1]))
874 return -EINVAL;
875
876 mt->adc_oe = CALIB_BUF0_ADC_OE_V2(buf[0]);
877 mt->adc_ge = CALIB_BUF0_ADC_GE_V2(buf[0]);
878 mt->degc_cali = CALIB_BUF0_DEGC_CALI_V2(buf[0]);
879 mt->o_slope = CALIB_BUF0_O_SLOPE_V2(buf[0]);
880 mt->vts[VTS1] = CALIB_BUF1_VTS_TS1_V2(buf[1]);
881 mt->vts[VTS2] = CALIB_BUF1_VTS_TS2_V2(buf[1]);
882 mt->vts[VTSABB] = CALIB_BUF1_VTS_TSABB_V2(buf[1]);
883 mt->o_slope_sign = CALIB_BUF1_O_SLOPE_SIGN_V2(buf[1]);
884
885 return 0;
886}
887
888static int mtk_thermal_get_calibration_data(struct device *dev,
889 struct mtk_thermal *mt)
890{
891 struct nvmem_cell *cell;
892 u32 *buf;
893 size_t len;
894 int i, ret = 0;
895
896 /* Start with default values */
897 mt->adc_ge = 512;
898 for (i = 0; i < mt->conf->num_sensors; i++)
899 mt->vts[i] = 260;
900 mt->degc_cali = 40;
901 mt->o_slope = 0;
902
903 cell = nvmem_cell_get(dev, "calibration-data");
904 if (IS_ERR(cell)) {
905 if (PTR_ERR(cell) == -EPROBE_DEFER)
906 return PTR_ERR(cell);
907 return 0;
908 }
909
910 buf = (u32 *)nvmem_cell_read(cell, &len);
911
912 nvmem_cell_put(cell);
913
914 if (IS_ERR(buf))
915 return PTR_ERR(buf);
916
917 if (len < 3 * sizeof(u32)) {
918 dev_warn(dev, "invalid calibration data\n");
919 ret = -EINVAL;
920 goto out;
921 }
922
923 if (mt->conf->version == MTK_THERMAL_V1)
924 ret = mtk_thermal_extract_efuse_v1(mt, buf);
925 else
926 ret = mtk_thermal_extract_efuse_v2(mt, buf);
927
928 if (ret) {
929 dev_info(dev, "Device not calibrated, using default calibration values\n");
930 ret = 0;
931 }
932
933out:
934 kfree(buf);
935
936 return ret;
937}
938
939static const struct of_device_id mtk_thermal_of_match[] = {
940 {
941 .compatible = "mediatek,mt8173-thermal",
942 .data = (void *)&mt8173_thermal_data,
943 },
944 {
945 .compatible = "mediatek,mt2701-thermal",
946 .data = (void *)&mt2701_thermal_data,
947 },
948 {
949 .compatible = "mediatek,mt2712-thermal",
950 .data = (void *)&mt2712_thermal_data,
951 },
952 {
953 .compatible = "mediatek,mt7622-thermal",
954 .data = (void *)&mt7622_thermal_data,
955 },
956 {
957 .compatible = "mediatek,mt8183-thermal",
958 .data = (void *)&mt8183_thermal_data,
959 }, {
960 },
961};
962MODULE_DEVICE_TABLE(of, mtk_thermal_of_match);
963
964static void mtk_thermal_turn_on_buffer(void __iomem *apmixed_base)
965{
966 int tmp;
967
968 tmp = readl(apmixed_base + APMIXED_SYS_TS_CON1);
969 tmp &= ~(0x37);
970 tmp |= 0x1;
971 writel(tmp, apmixed_base + APMIXED_SYS_TS_CON1);
972 udelay(200);
973}
974
975static void mtk_thermal_release_periodic_ts(struct mtk_thermal *mt,
976 void __iomem *auxadc_base)
977{
978 int tmp;
979
980 writel(0x800, auxadc_base + AUXADC_CON1_SET_V);
981 writel(0x1, mt->thermal_base + TEMP_MONCTL0);
982 tmp = readl(mt->thermal_base + TEMP_MSRCTL1);
983 writel((tmp & (~0x10e)), mt->thermal_base + TEMP_MSRCTL1);
984}
985
986static int mtk_thermal_probe(struct platform_device *pdev)
987{
988 int ret, i, ctrl_id;
989 struct device_node *auxadc, *apmixedsys, *np = pdev->dev.of_node;
990 struct mtk_thermal *mt;
991 struct resource *res;
992 u64 auxadc_phys_base, apmixed_phys_base;
993 struct thermal_zone_device *tzdev;
994 void __iomem *apmixed_base, *auxadc_base;
995
996 mt = devm_kzalloc(&pdev->dev, sizeof(*mt), GFP_KERNEL);
997 if (!mt)
998 return -ENOMEM;
999
1000 mt->conf = of_device_get_match_data(&pdev->dev);
1001
1002 mt->clk_peri_therm = devm_clk_get(&pdev->dev, "therm");
1003 if (IS_ERR(mt->clk_peri_therm))
1004 return PTR_ERR(mt->clk_peri_therm);
1005
1006 mt->clk_auxadc = devm_clk_get(&pdev->dev, "auxadc");
1007 if (IS_ERR(mt->clk_auxadc))
1008 return PTR_ERR(mt->clk_auxadc);
1009
1010 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1011 mt->thermal_base = devm_ioremap_resource(&pdev->dev, res);
1012 if (IS_ERR(mt->thermal_base))
1013 return PTR_ERR(mt->thermal_base);
1014
1015 ret = mtk_thermal_get_calibration_data(&pdev->dev, mt);
1016 if (ret)
1017 return ret;
1018
1019 mutex_init(&mt->lock);
1020
1021 mt->dev = &pdev->dev;
1022
1023 auxadc = of_parse_phandle(np, "mediatek,auxadc", 0);
1024 if (!auxadc) {
1025 dev_err(&pdev->dev, "missing auxadc node\n");
1026 return -ENODEV;
1027 }
1028
1029 auxadc_base = of_iomap(auxadc, 0);
1030 auxadc_phys_base = of_get_phys_base(auxadc);
1031
1032 of_node_put(auxadc);
1033
1034 if (auxadc_phys_base == OF_BAD_ADDR) {
1035 dev_err(&pdev->dev, "Can't get auxadc phys address\n");
1036 return -EINVAL;
1037 }
1038
1039 apmixedsys = of_parse_phandle(np, "mediatek,apmixedsys", 0);
1040 if (!apmixedsys) {
1041 dev_err(&pdev->dev, "missing apmixedsys node\n");
1042 return -ENODEV;
1043 }
1044
1045 apmixed_base = of_iomap(apmixedsys, 0);
1046 apmixed_phys_base = of_get_phys_base(apmixedsys);
1047
1048 of_node_put(apmixedsys);
1049
1050 if (apmixed_phys_base == OF_BAD_ADDR) {
1051 dev_err(&pdev->dev, "Can't get auxadc phys address\n");
1052 return -EINVAL;
1053 }
1054
1055 ret = device_reset(&pdev->dev);
1056 if (ret)
1057 return ret;
1058
1059 ret = clk_prepare_enable(mt->clk_auxadc);
1060 if (ret) {
1061 dev_err(&pdev->dev, "Can't enable auxadc clk: %d\n", ret);
1062 return ret;
1063 }
1064
1065 ret = clk_prepare_enable(mt->clk_peri_therm);
1066 if (ret) {
1067 dev_err(&pdev->dev, "Can't enable peri clk: %d\n", ret);
1068 goto err_disable_clk_auxadc;
1069 }
1070
1071 if (mt->conf->version == MTK_THERMAL_V2) {
1072 mtk_thermal_turn_on_buffer(apmixed_base);
1073 mtk_thermal_release_periodic_ts(mt, auxadc_base);
1074 }
1075
1076 for (ctrl_id = 0; ctrl_id < mt->conf->num_controller ; ctrl_id++)
1077 for (i = 0; i < mt->conf->num_banks; i++)
1078 mtk_thermal_init_bank(mt, i, apmixed_phys_base,
1079 auxadc_phys_base, ctrl_id);
1080
1081 platform_set_drvdata(pdev, mt);
1082
1083 tzdev = devm_thermal_zone_of_sensor_register(&pdev->dev, 0, mt,
1084 &mtk_thermal_ops);
1085 if (IS_ERR(tzdev)) {
1086 ret = PTR_ERR(tzdev);
1087 goto err_disable_clk_peri_therm;
1088 }
1089
1090 return 0;
1091
1092err_disable_clk_peri_therm:
1093 clk_disable_unprepare(mt->clk_peri_therm);
1094err_disable_clk_auxadc:
1095 clk_disable_unprepare(mt->clk_auxadc);
1096
1097 return ret;
1098}
1099
1100static int mtk_thermal_remove(struct platform_device *pdev)
1101{
1102 struct mtk_thermal *mt = platform_get_drvdata(pdev);
1103
1104 clk_disable_unprepare(mt->clk_peri_therm);
1105 clk_disable_unprepare(mt->clk_auxadc);
1106
1107 return 0;
1108}
1109
1110static struct platform_driver mtk_thermal_driver = {
1111 .probe = mtk_thermal_probe,
1112 .remove = mtk_thermal_remove,
1113 .driver = {
1114 .name = "mtk-thermal",
1115 .of_match_table = mtk_thermal_of_match,
1116 },
1117};
1118
1119module_platform_driver(mtk_thermal_driver);
1120
1121MODULE_AUTHOR("Michael Kao <michael.kao@mediatek.com>");
1122MODULE_AUTHOR("Louis Yu <louis.yu@mediatek.com>");
1123MODULE_AUTHOR("Dawei Chien <dawei.chien@mediatek.com>");
1124MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de>");
1125MODULE_AUTHOR("Hanyi Wu <hanyi.wu@mediatek.com>");
1126MODULE_DESCRIPTION("Mediatek thermal driver");
1127MODULE_LICENSE("GPL v2");
1/*
2 * Copyright (c) 2015 MediaTek Inc.
3 * Author: Hanyi Wu <hanyi.wu@mediatek.com>
4 * Sascha Hauer <s.hauer@pengutronix.de>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15
16#include <linux/clk.h>
17#include <linux/delay.h>
18#include <linux/interrupt.h>
19#include <linux/kernel.h>
20#include <linux/module.h>
21#include <linux/nvmem-consumer.h>
22#include <linux/of.h>
23#include <linux/of_address.h>
24#include <linux/platform_device.h>
25#include <linux/slab.h>
26#include <linux/io.h>
27#include <linux/thermal.h>
28#include <linux/reset.h>
29#include <linux/types.h>
30
31/* AUXADC Registers */
32#define AUXADC_CON0_V 0x000
33#define AUXADC_CON1_V 0x004
34#define AUXADC_CON1_SET_V 0x008
35#define AUXADC_CON1_CLR_V 0x00c
36#define AUXADC_CON2_V 0x010
37#define AUXADC_DATA(channel) (0x14 + (channel) * 4)
38#define AUXADC_MISC_V 0x094
39
40#define AUXADC_CON1_CHANNEL(x) BIT(x)
41
42#define APMIXED_SYS_TS_CON1 0x604
43
44/* Thermal Controller Registers */
45#define TEMP_MONCTL0 0x000
46#define TEMP_MONCTL1 0x004
47#define TEMP_MONCTL2 0x008
48#define TEMP_MONIDET0 0x014
49#define TEMP_MONIDET1 0x018
50#define TEMP_MSRCTL0 0x038
51#define TEMP_AHBPOLL 0x040
52#define TEMP_AHBTO 0x044
53#define TEMP_ADCPNP0 0x048
54#define TEMP_ADCPNP1 0x04c
55#define TEMP_ADCPNP2 0x050
56#define TEMP_ADCPNP3 0x0b4
57
58#define TEMP_ADCMUX 0x054
59#define TEMP_ADCEN 0x060
60#define TEMP_PNPMUXADDR 0x064
61#define TEMP_ADCMUXADDR 0x068
62#define TEMP_ADCENADDR 0x074
63#define TEMP_ADCVALIDADDR 0x078
64#define TEMP_ADCVOLTADDR 0x07c
65#define TEMP_RDCTRL 0x080
66#define TEMP_ADCVALIDMASK 0x084
67#define TEMP_ADCVOLTAGESHIFT 0x088
68#define TEMP_ADCWRITECTRL 0x08c
69#define TEMP_MSR0 0x090
70#define TEMP_MSR1 0x094
71#define TEMP_MSR2 0x098
72#define TEMP_MSR3 0x0B8
73
74#define TEMP_SPARE0 0x0f0
75
76#define PTPCORESEL 0x400
77
78#define TEMP_MONCTL1_PERIOD_UNIT(x) ((x) & 0x3ff)
79
80#define TEMP_MONCTL2_FILTER_INTERVAL(x) (((x) & 0x3ff) << 16)
81#define TEMP_MONCTL2_SENSOR_INTERVAL(x) ((x) & 0x3ff)
82
83#define TEMP_AHBPOLL_ADC_POLL_INTERVAL(x) (x)
84
85#define TEMP_ADCWRITECTRL_ADC_PNP_WRITE BIT(0)
86#define TEMP_ADCWRITECTRL_ADC_MUX_WRITE BIT(1)
87
88#define TEMP_ADCVALIDMASK_VALID_HIGH BIT(5)
89#define TEMP_ADCVALIDMASK_VALID_POS(bit) (bit)
90
91#define MT8173_TS1 0
92#define MT8173_TS2 1
93#define MT8173_TS3 2
94#define MT8173_TS4 3
95#define MT8173_TSABB 4
96
97/* AUXADC channel 11 is used for the temperature sensors */
98#define MT8173_TEMP_AUXADC_CHANNEL 11
99
100/* The total number of temperature sensors in the MT8173 */
101#define MT8173_NUM_SENSORS 5
102
103/* The number of banks in the MT8173 */
104#define MT8173_NUM_ZONES 4
105
106/* The number of sensing points per bank */
107#define MT8173_NUM_SENSORS_PER_ZONE 4
108
109/* Layout of the fuses providing the calibration data */
110#define MT8173_CALIB_BUF0_VALID BIT(0)
111#define MT8173_CALIB_BUF1_ADC_GE(x) (((x) >> 22) & 0x3ff)
112#define MT8173_CALIB_BUF0_VTS_TS1(x) (((x) >> 17) & 0x1ff)
113#define MT8173_CALIB_BUF0_VTS_TS2(x) (((x) >> 8) & 0x1ff)
114#define MT8173_CALIB_BUF1_VTS_TS3(x) (((x) >> 0) & 0x1ff)
115#define MT8173_CALIB_BUF2_VTS_TS4(x) (((x) >> 23) & 0x1ff)
116#define MT8173_CALIB_BUF2_VTS_TSABB(x) (((x) >> 14) & 0x1ff)
117#define MT8173_CALIB_BUF0_DEGC_CALI(x) (((x) >> 1) & 0x3f)
118#define MT8173_CALIB_BUF0_O_SLOPE(x) (((x) >> 26) & 0x3f)
119
120#define THERMAL_NAME "mtk-thermal"
121
122struct mtk_thermal;
123
124struct mtk_thermal_bank {
125 struct mtk_thermal *mt;
126 int id;
127};
128
129struct mtk_thermal {
130 struct device *dev;
131 void __iomem *thermal_base;
132
133 struct clk *clk_peri_therm;
134 struct clk *clk_auxadc;
135
136 struct mtk_thermal_bank banks[MT8173_NUM_ZONES];
137
138 /* lock: for getting and putting banks */
139 struct mutex lock;
140
141 /* Calibration values */
142 s32 adc_ge;
143 s32 degc_cali;
144 s32 o_slope;
145 s32 vts[MT8173_NUM_SENSORS];
146
147 struct thermal_zone_device *tzd;
148};
149
150struct mtk_thermal_bank_cfg {
151 unsigned int num_sensors;
152 unsigned int sensors[MT8173_NUM_SENSORS_PER_ZONE];
153};
154
155static const int sensor_mux_values[MT8173_NUM_SENSORS] = { 0, 1, 2, 3, 16 };
156
157/*
158 * The MT8173 thermal controller has four banks. Each bank can read up to
159 * four temperature sensors simultaneously. The MT8173 has a total of 5
160 * temperature sensors. We use each bank to measure a certain area of the
161 * SoC. Since TS2 is located centrally in the SoC it is influenced by multiple
162 * areas, hence is used in different banks.
163 *
164 * The thermal core only gets the maximum temperature of all banks, so
165 * the bank concept wouldn't be necessary here. However, the SVS (Smart
166 * Voltage Scaling) unit makes its decisions based on the same bank
167 * data, and this indeed needs the temperatures of the individual banks
168 * for making better decisions.
169 */
170static const struct mtk_thermal_bank_cfg bank_data[] = {
171 {
172 .num_sensors = 2,
173 .sensors = { MT8173_TS2, MT8173_TS3 },
174 }, {
175 .num_sensors = 2,
176 .sensors = { MT8173_TS2, MT8173_TS4 },
177 }, {
178 .num_sensors = 3,
179 .sensors = { MT8173_TS1, MT8173_TS2, MT8173_TSABB },
180 }, {
181 .num_sensors = 1,
182 .sensors = { MT8173_TS2 },
183 },
184};
185
186struct mtk_thermal_sense_point {
187 int msr;
188 int adcpnp;
189};
190
191static const struct mtk_thermal_sense_point
192 sensing_points[MT8173_NUM_SENSORS_PER_ZONE] = {
193 {
194 .msr = TEMP_MSR0,
195 .adcpnp = TEMP_ADCPNP0,
196 }, {
197 .msr = TEMP_MSR1,
198 .adcpnp = TEMP_ADCPNP1,
199 }, {
200 .msr = TEMP_MSR2,
201 .adcpnp = TEMP_ADCPNP2,
202 }, {
203 .msr = TEMP_MSR3,
204 .adcpnp = TEMP_ADCPNP3,
205 },
206};
207
208/**
209 * raw_to_mcelsius - convert a raw ADC value to mcelsius
210 * @mt: The thermal controller
211 * @raw: raw ADC value
212 *
213 * This converts the raw ADC value to mcelsius using the SoC specific
214 * calibration constants
215 */
216static int raw_to_mcelsius(struct mtk_thermal *mt, int sensno, s32 raw)
217{
218 s32 tmp;
219
220 raw &= 0xfff;
221
222 tmp = 203450520 << 3;
223 tmp /= 165 + mt->o_slope;
224 tmp /= 10000 + mt->adc_ge;
225 tmp *= raw - mt->vts[sensno] - 3350;
226 tmp >>= 3;
227
228 return mt->degc_cali * 500 - tmp;
229}
230
231/**
232 * mtk_thermal_get_bank - get bank
233 * @bank: The bank
234 *
235 * The bank registers are banked, we have to select a bank in the
236 * PTPCORESEL register to access it.
237 */
238static void mtk_thermal_get_bank(struct mtk_thermal_bank *bank)
239{
240 struct mtk_thermal *mt = bank->mt;
241 u32 val;
242
243 mutex_lock(&mt->lock);
244
245 val = readl(mt->thermal_base + PTPCORESEL);
246 val &= ~0xf;
247 val |= bank->id;
248 writel(val, mt->thermal_base + PTPCORESEL);
249}
250
251/**
252 * mtk_thermal_put_bank - release bank
253 * @bank: The bank
254 *
255 * release a bank previously taken with mtk_thermal_get_bank,
256 */
257static void mtk_thermal_put_bank(struct mtk_thermal_bank *bank)
258{
259 struct mtk_thermal *mt = bank->mt;
260
261 mutex_unlock(&mt->lock);
262}
263
264/**
265 * mtk_thermal_bank_temperature - get the temperature of a bank
266 * @bank: The bank
267 *
268 * The temperature of a bank is considered the maximum temperature of
269 * the sensors associated to the bank.
270 */
271static int mtk_thermal_bank_temperature(struct mtk_thermal_bank *bank)
272{
273 struct mtk_thermal *mt = bank->mt;
274 int i, temp = INT_MIN, max = INT_MIN;
275 u32 raw;
276
277 for (i = 0; i < bank_data[bank->id].num_sensors; i++) {
278 raw = readl(mt->thermal_base + sensing_points[i].msr);
279
280 temp = raw_to_mcelsius(mt, bank_data[bank->id].sensors[i], raw);
281
282 /*
283 * The first read of a sensor often contains very high bogus
284 * temperature value. Filter these out so that the system does
285 * not immediately shut down.
286 */
287 if (temp > 200000)
288 temp = 0;
289
290 if (temp > max)
291 max = temp;
292 }
293
294 return max;
295}
296
297static int mtk_read_temp(void *data, int *temperature)
298{
299 struct mtk_thermal *mt = data;
300 int i;
301 int tempmax = INT_MIN;
302
303 for (i = 0; i < MT8173_NUM_ZONES; i++) {
304 struct mtk_thermal_bank *bank = &mt->banks[i];
305
306 mtk_thermal_get_bank(bank);
307
308 tempmax = max(tempmax, mtk_thermal_bank_temperature(bank));
309
310 mtk_thermal_put_bank(bank);
311 }
312
313 *temperature = tempmax;
314
315 return 0;
316}
317
318static const struct thermal_zone_of_device_ops mtk_thermal_ops = {
319 .get_temp = mtk_read_temp,
320};
321
322static void mtk_thermal_init_bank(struct mtk_thermal *mt, int num,
323 u32 apmixed_phys_base, u32 auxadc_phys_base)
324{
325 struct mtk_thermal_bank *bank = &mt->banks[num];
326 const struct mtk_thermal_bank_cfg *cfg = &bank_data[num];
327 int i;
328
329 bank->id = num;
330 bank->mt = mt;
331
332 mtk_thermal_get_bank(bank);
333
334 /* bus clock 66M counting unit is 12 * 15.15ns * 256 = 46.540us */
335 writel(TEMP_MONCTL1_PERIOD_UNIT(12), mt->thermal_base + TEMP_MONCTL1);
336
337 /*
338 * filt interval is 1 * 46.540us = 46.54us,
339 * sen interval is 429 * 46.540us = 19.96ms
340 */
341 writel(TEMP_MONCTL2_FILTER_INTERVAL(1) |
342 TEMP_MONCTL2_SENSOR_INTERVAL(429),
343 mt->thermal_base + TEMP_MONCTL2);
344
345 /* poll is set to 10u */
346 writel(TEMP_AHBPOLL_ADC_POLL_INTERVAL(768),
347 mt->thermal_base + TEMP_AHBPOLL);
348
349 /* temperature sampling control, 1 sample */
350 writel(0x0, mt->thermal_base + TEMP_MSRCTL0);
351
352 /* exceed this polling time, IRQ would be inserted */
353 writel(0xffffffff, mt->thermal_base + TEMP_AHBTO);
354
355 /* number of interrupts per event, 1 is enough */
356 writel(0x0, mt->thermal_base + TEMP_MONIDET0);
357 writel(0x0, mt->thermal_base + TEMP_MONIDET1);
358
359 /*
360 * The MT8173 thermal controller does not have its own ADC. Instead it
361 * uses AHB bus accesses to control the AUXADC. To do this the thermal
362 * controller has to be programmed with the physical addresses of the
363 * AUXADC registers and with the various bit positions in the AUXADC.
364 * Also the thermal controller controls a mux in the APMIXEDSYS register
365 * space.
366 */
367
368 /*
369 * this value will be stored to TEMP_PNPMUXADDR (TEMP_SPARE0)
370 * automatically by hw
371 */
372 writel(BIT(MT8173_TEMP_AUXADC_CHANNEL), mt->thermal_base + TEMP_ADCMUX);
373
374 /* AHB address for auxadc mux selection */
375 writel(auxadc_phys_base + AUXADC_CON1_CLR_V,
376 mt->thermal_base + TEMP_ADCMUXADDR);
377
378 /* AHB address for pnp sensor mux selection */
379 writel(apmixed_phys_base + APMIXED_SYS_TS_CON1,
380 mt->thermal_base + TEMP_PNPMUXADDR);
381
382 /* AHB value for auxadc enable */
383 writel(BIT(MT8173_TEMP_AUXADC_CHANNEL), mt->thermal_base + TEMP_ADCEN);
384
385 /* AHB address for auxadc enable (channel 0 immediate mode selected) */
386 writel(auxadc_phys_base + AUXADC_CON1_SET_V,
387 mt->thermal_base + TEMP_ADCENADDR);
388
389 /* AHB address for auxadc valid bit */
390 writel(auxadc_phys_base + AUXADC_DATA(MT8173_TEMP_AUXADC_CHANNEL),
391 mt->thermal_base + TEMP_ADCVALIDADDR);
392
393 /* AHB address for auxadc voltage output */
394 writel(auxadc_phys_base + AUXADC_DATA(MT8173_TEMP_AUXADC_CHANNEL),
395 mt->thermal_base + TEMP_ADCVOLTADDR);
396
397 /* read valid & voltage are at the same register */
398 writel(0x0, mt->thermal_base + TEMP_RDCTRL);
399
400 /* indicate where the valid bit is */
401 writel(TEMP_ADCVALIDMASK_VALID_HIGH | TEMP_ADCVALIDMASK_VALID_POS(12),
402 mt->thermal_base + TEMP_ADCVALIDMASK);
403
404 /* no shift */
405 writel(0x0, mt->thermal_base + TEMP_ADCVOLTAGESHIFT);
406
407 /* enable auxadc mux write transaction */
408 writel(TEMP_ADCWRITECTRL_ADC_MUX_WRITE,
409 mt->thermal_base + TEMP_ADCWRITECTRL);
410
411 for (i = 0; i < cfg->num_sensors; i++)
412 writel(sensor_mux_values[cfg->sensors[i]],
413 mt->thermal_base + sensing_points[i].adcpnp);
414
415 writel((1 << cfg->num_sensors) - 1, mt->thermal_base + TEMP_MONCTL0);
416
417 writel(TEMP_ADCWRITECTRL_ADC_PNP_WRITE |
418 TEMP_ADCWRITECTRL_ADC_MUX_WRITE,
419 mt->thermal_base + TEMP_ADCWRITECTRL);
420
421 mtk_thermal_put_bank(bank);
422}
423
424static u64 of_get_phys_base(struct device_node *np)
425{
426 u64 size64;
427 const __be32 *regaddr_p;
428
429 regaddr_p = of_get_address(np, 0, &size64, NULL);
430 if (!regaddr_p)
431 return OF_BAD_ADDR;
432
433 return of_translate_address(np, regaddr_p);
434}
435
436static int mtk_thermal_get_calibration_data(struct device *dev,
437 struct mtk_thermal *mt)
438{
439 struct nvmem_cell *cell;
440 u32 *buf;
441 size_t len;
442 int i, ret = 0;
443
444 /* Start with default values */
445 mt->adc_ge = 512;
446 for (i = 0; i < MT8173_NUM_SENSORS; i++)
447 mt->vts[i] = 260;
448 mt->degc_cali = 40;
449 mt->o_slope = 0;
450
451 cell = nvmem_cell_get(dev, "calibration-data");
452 if (IS_ERR(cell)) {
453 if (PTR_ERR(cell) == -EPROBE_DEFER)
454 return PTR_ERR(cell);
455 return 0;
456 }
457
458 buf = (u32 *)nvmem_cell_read(cell, &len);
459
460 nvmem_cell_put(cell);
461
462 if (IS_ERR(buf))
463 return PTR_ERR(buf);
464
465 if (len < 3 * sizeof(u32)) {
466 dev_warn(dev, "invalid calibration data\n");
467 ret = -EINVAL;
468 goto out;
469 }
470
471 if (buf[0] & MT8173_CALIB_BUF0_VALID) {
472 mt->adc_ge = MT8173_CALIB_BUF1_ADC_GE(buf[1]);
473 mt->vts[MT8173_TS1] = MT8173_CALIB_BUF0_VTS_TS1(buf[0]);
474 mt->vts[MT8173_TS2] = MT8173_CALIB_BUF0_VTS_TS2(buf[0]);
475 mt->vts[MT8173_TS3] = MT8173_CALIB_BUF1_VTS_TS3(buf[1]);
476 mt->vts[MT8173_TS4] = MT8173_CALIB_BUF2_VTS_TS4(buf[2]);
477 mt->vts[MT8173_TSABB] = MT8173_CALIB_BUF2_VTS_TSABB(buf[2]);
478 mt->degc_cali = MT8173_CALIB_BUF0_DEGC_CALI(buf[0]);
479 mt->o_slope = MT8173_CALIB_BUF0_O_SLOPE(buf[0]);
480 } else {
481 dev_info(dev, "Device not calibrated, using default calibration values\n");
482 }
483
484out:
485 kfree(buf);
486
487 return ret;
488}
489
490static int mtk_thermal_probe(struct platform_device *pdev)
491{
492 int ret, i;
493 struct device_node *auxadc, *apmixedsys, *np = pdev->dev.of_node;
494 struct mtk_thermal *mt;
495 struct resource *res;
496 u64 auxadc_phys_base, apmixed_phys_base;
497
498 mt = devm_kzalloc(&pdev->dev, sizeof(*mt), GFP_KERNEL);
499 if (!mt)
500 return -ENOMEM;
501
502 mt->clk_peri_therm = devm_clk_get(&pdev->dev, "therm");
503 if (IS_ERR(mt->clk_peri_therm))
504 return PTR_ERR(mt->clk_peri_therm);
505
506 mt->clk_auxadc = devm_clk_get(&pdev->dev, "auxadc");
507 if (IS_ERR(mt->clk_auxadc))
508 return PTR_ERR(mt->clk_auxadc);
509
510 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
511 mt->thermal_base = devm_ioremap_resource(&pdev->dev, res);
512 if (IS_ERR(mt->thermal_base))
513 return PTR_ERR(mt->thermal_base);
514
515 ret = mtk_thermal_get_calibration_data(&pdev->dev, mt);
516 if (ret)
517 return ret;
518
519 mutex_init(&mt->lock);
520
521 mt->dev = &pdev->dev;
522
523 auxadc = of_parse_phandle(np, "mediatek,auxadc", 0);
524 if (!auxadc) {
525 dev_err(&pdev->dev, "missing auxadc node\n");
526 return -ENODEV;
527 }
528
529 auxadc_phys_base = of_get_phys_base(auxadc);
530
531 of_node_put(auxadc);
532
533 if (auxadc_phys_base == OF_BAD_ADDR) {
534 dev_err(&pdev->dev, "Can't get auxadc phys address\n");
535 return -EINVAL;
536 }
537
538 apmixedsys = of_parse_phandle(np, "mediatek,apmixedsys", 0);
539 if (!apmixedsys) {
540 dev_err(&pdev->dev, "missing apmixedsys node\n");
541 return -ENODEV;
542 }
543
544 apmixed_phys_base = of_get_phys_base(apmixedsys);
545
546 of_node_put(apmixedsys);
547
548 if (apmixed_phys_base == OF_BAD_ADDR) {
549 dev_err(&pdev->dev, "Can't get auxadc phys address\n");
550 return -EINVAL;
551 }
552
553 ret = clk_prepare_enable(mt->clk_auxadc);
554 if (ret) {
555 dev_err(&pdev->dev, "Can't enable auxadc clk: %d\n", ret);
556 return ret;
557 }
558
559 ret = device_reset(&pdev->dev);
560 if (ret)
561 goto err_disable_clk_auxadc;
562
563 ret = clk_prepare_enable(mt->clk_peri_therm);
564 if (ret) {
565 dev_err(&pdev->dev, "Can't enable peri clk: %d\n", ret);
566 goto err_disable_clk_auxadc;
567 }
568
569 for (i = 0; i < MT8173_NUM_ZONES; i++)
570 mtk_thermal_init_bank(mt, i, apmixed_phys_base,
571 auxadc_phys_base);
572
573 platform_set_drvdata(pdev, mt);
574
575 mt->tzd = thermal_zone_of_sensor_register(&pdev->dev, 0, mt,
576 &mtk_thermal_ops);
577 if (IS_ERR(mt->tzd))
578 goto err_register;
579
580 return 0;
581
582err_register:
583 clk_disable_unprepare(mt->clk_peri_therm);
584
585err_disable_clk_auxadc:
586 clk_disable_unprepare(mt->clk_auxadc);
587
588 return ret;
589}
590
591static int mtk_thermal_remove(struct platform_device *pdev)
592{
593 struct mtk_thermal *mt = platform_get_drvdata(pdev);
594
595 thermal_zone_of_sensor_unregister(&pdev->dev, mt->tzd);
596
597 clk_disable_unprepare(mt->clk_peri_therm);
598 clk_disable_unprepare(mt->clk_auxadc);
599
600 return 0;
601}
602
603static const struct of_device_id mtk_thermal_of_match[] = {
604 {
605 .compatible = "mediatek,mt8173-thermal",
606 }, {
607 },
608};
609
610static struct platform_driver mtk_thermal_driver = {
611 .probe = mtk_thermal_probe,
612 .remove = mtk_thermal_remove,
613 .driver = {
614 .name = THERMAL_NAME,
615 .of_match_table = mtk_thermal_of_match,
616 },
617};
618
619module_platform_driver(mtk_thermal_driver);
620
621MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de>");
622MODULE_AUTHOR("Hanyi Wu <hanyi.wu@mediatek.com>");
623MODULE_DESCRIPTION("Mediatek thermal driver");
624MODULE_LICENSE("GPL v2");