Loading...
1// SPDX-License-Identifier: GPL-2.0-only
2/* CAN bus driver for Microchip 251x/25625 CAN Controller with SPI Interface
3 *
4 * MCP2510 support and bug fixes by Christian Pellegrin
5 * <chripell@evolware.org>
6 *
7 * Copyright 2009 Christian Pellegrin EVOL S.r.l.
8 *
9 * Copyright 2007 Raymarine UK, Ltd. All Rights Reserved.
10 * Written under contract by:
11 * Chris Elston, Katalix Systems, Ltd.
12 *
13 * Based on Microchip MCP251x CAN controller driver written by
14 * David Vrabel, Copyright 2006 Arcom Control Systems Ltd.
15 *
16 * Based on CAN bus driver for the CCAN controller written by
17 * - Sascha Hauer, Marc Kleine-Budde, Pengutronix
18 * - Simon Kallweit, intefo AG
19 * Copyright 2007
20 */
21
22#include <linux/can/core.h>
23#include <linux/can/dev.h>
24#include <linux/can/led.h>
25#include <linux/clk.h>
26#include <linux/completion.h>
27#include <linux/delay.h>
28#include <linux/device.h>
29#include <linux/freezer.h>
30#include <linux/interrupt.h>
31#include <linux/io.h>
32#include <linux/kernel.h>
33#include <linux/module.h>
34#include <linux/netdevice.h>
35#include <linux/property.h>
36#include <linux/platform_device.h>
37#include <linux/slab.h>
38#include <linux/spi/spi.h>
39#include <linux/uaccess.h>
40#include <linux/regulator/consumer.h>
41
42/* SPI interface instruction set */
43#define INSTRUCTION_WRITE 0x02
44#define INSTRUCTION_READ 0x03
45#define INSTRUCTION_BIT_MODIFY 0x05
46#define INSTRUCTION_LOAD_TXB(n) (0x40 + 2 * (n))
47#define INSTRUCTION_READ_RXB(n) (((n) == 0) ? 0x90 : 0x94)
48#define INSTRUCTION_RESET 0xC0
49#define RTS_TXB0 0x01
50#define RTS_TXB1 0x02
51#define RTS_TXB2 0x04
52#define INSTRUCTION_RTS(n) (0x80 | ((n) & 0x07))
53
54/* MPC251x registers */
55#define CANSTAT 0x0e
56#define CANCTRL 0x0f
57# define CANCTRL_REQOP_MASK 0xe0
58# define CANCTRL_REQOP_CONF 0x80
59# define CANCTRL_REQOP_LISTEN_ONLY 0x60
60# define CANCTRL_REQOP_LOOPBACK 0x40
61# define CANCTRL_REQOP_SLEEP 0x20
62# define CANCTRL_REQOP_NORMAL 0x00
63# define CANCTRL_OSM 0x08
64# define CANCTRL_ABAT 0x10
65#define TEC 0x1c
66#define REC 0x1d
67#define CNF1 0x2a
68# define CNF1_SJW_SHIFT 6
69#define CNF2 0x29
70# define CNF2_BTLMODE 0x80
71# define CNF2_SAM 0x40
72# define CNF2_PS1_SHIFT 3
73#define CNF3 0x28
74# define CNF3_SOF 0x08
75# define CNF3_WAKFIL 0x04
76# define CNF3_PHSEG2_MASK 0x07
77#define CANINTE 0x2b
78# define CANINTE_MERRE 0x80
79# define CANINTE_WAKIE 0x40
80# define CANINTE_ERRIE 0x20
81# define CANINTE_TX2IE 0x10
82# define CANINTE_TX1IE 0x08
83# define CANINTE_TX0IE 0x04
84# define CANINTE_RX1IE 0x02
85# define CANINTE_RX0IE 0x01
86#define CANINTF 0x2c
87# define CANINTF_MERRF 0x80
88# define CANINTF_WAKIF 0x40
89# define CANINTF_ERRIF 0x20
90# define CANINTF_TX2IF 0x10
91# define CANINTF_TX1IF 0x08
92# define CANINTF_TX0IF 0x04
93# define CANINTF_RX1IF 0x02
94# define CANINTF_RX0IF 0x01
95# define CANINTF_RX (CANINTF_RX0IF | CANINTF_RX1IF)
96# define CANINTF_TX (CANINTF_TX2IF | CANINTF_TX1IF | CANINTF_TX0IF)
97# define CANINTF_ERR (CANINTF_ERRIF)
98#define EFLG 0x2d
99# define EFLG_EWARN 0x01
100# define EFLG_RXWAR 0x02
101# define EFLG_TXWAR 0x04
102# define EFLG_RXEP 0x08
103# define EFLG_TXEP 0x10
104# define EFLG_TXBO 0x20
105# define EFLG_RX0OVR 0x40
106# define EFLG_RX1OVR 0x80
107#define TXBCTRL(n) (((n) * 0x10) + 0x30 + TXBCTRL_OFF)
108# define TXBCTRL_ABTF 0x40
109# define TXBCTRL_MLOA 0x20
110# define TXBCTRL_TXERR 0x10
111# define TXBCTRL_TXREQ 0x08
112#define TXBSIDH(n) (((n) * 0x10) + 0x30 + TXBSIDH_OFF)
113# define SIDH_SHIFT 3
114#define TXBSIDL(n) (((n) * 0x10) + 0x30 + TXBSIDL_OFF)
115# define SIDL_SID_MASK 7
116# define SIDL_SID_SHIFT 5
117# define SIDL_EXIDE_SHIFT 3
118# define SIDL_EID_SHIFT 16
119# define SIDL_EID_MASK 3
120#define TXBEID8(n) (((n) * 0x10) + 0x30 + TXBEID8_OFF)
121#define TXBEID0(n) (((n) * 0x10) + 0x30 + TXBEID0_OFF)
122#define TXBDLC(n) (((n) * 0x10) + 0x30 + TXBDLC_OFF)
123# define DLC_RTR_SHIFT 6
124#define TXBCTRL_OFF 0
125#define TXBSIDH_OFF 1
126#define TXBSIDL_OFF 2
127#define TXBEID8_OFF 3
128#define TXBEID0_OFF 4
129#define TXBDLC_OFF 5
130#define TXBDAT_OFF 6
131#define RXBCTRL(n) (((n) * 0x10) + 0x60 + RXBCTRL_OFF)
132# define RXBCTRL_BUKT 0x04
133# define RXBCTRL_RXM0 0x20
134# define RXBCTRL_RXM1 0x40
135#define RXBSIDH(n) (((n) * 0x10) + 0x60 + RXBSIDH_OFF)
136# define RXBSIDH_SHIFT 3
137#define RXBSIDL(n) (((n) * 0x10) + 0x60 + RXBSIDL_OFF)
138# define RXBSIDL_IDE 0x08
139# define RXBSIDL_SRR 0x10
140# define RXBSIDL_EID 3
141# define RXBSIDL_SHIFT 5
142#define RXBEID8(n) (((n) * 0x10) + 0x60 + RXBEID8_OFF)
143#define RXBEID0(n) (((n) * 0x10) + 0x60 + RXBEID0_OFF)
144#define RXBDLC(n) (((n) * 0x10) + 0x60 + RXBDLC_OFF)
145# define RXBDLC_LEN_MASK 0x0f
146# define RXBDLC_RTR 0x40
147#define RXBCTRL_OFF 0
148#define RXBSIDH_OFF 1
149#define RXBSIDL_OFF 2
150#define RXBEID8_OFF 3
151#define RXBEID0_OFF 4
152#define RXBDLC_OFF 5
153#define RXBDAT_OFF 6
154#define RXFSID(n) ((n < 3) ? 0 : 4)
155#define RXFSIDH(n) ((n) * 4 + RXFSID(n))
156#define RXFSIDL(n) ((n) * 4 + 1 + RXFSID(n))
157#define RXFEID8(n) ((n) * 4 + 2 + RXFSID(n))
158#define RXFEID0(n) ((n) * 4 + 3 + RXFSID(n))
159#define RXMSIDH(n) ((n) * 4 + 0x20)
160#define RXMSIDL(n) ((n) * 4 + 0x21)
161#define RXMEID8(n) ((n) * 4 + 0x22)
162#define RXMEID0(n) ((n) * 4 + 0x23)
163
164#define GET_BYTE(val, byte) \
165 (((val) >> ((byte) * 8)) & 0xff)
166#define SET_BYTE(val, byte) \
167 (((val) & 0xff) << ((byte) * 8))
168
169/* Buffer size required for the largest SPI transfer (i.e., reading a
170 * frame)
171 */
172#define CAN_FRAME_MAX_DATA_LEN 8
173#define SPI_TRANSFER_BUF_LEN (6 + CAN_FRAME_MAX_DATA_LEN)
174#define CAN_FRAME_MAX_BITS 128
175
176#define TX_ECHO_SKB_MAX 1
177
178#define MCP251X_OST_DELAY_MS (5)
179
180#define DEVICE_NAME "mcp251x"
181
182static const struct can_bittiming_const mcp251x_bittiming_const = {
183 .name = DEVICE_NAME,
184 .tseg1_min = 3,
185 .tseg1_max = 16,
186 .tseg2_min = 2,
187 .tseg2_max = 8,
188 .sjw_max = 4,
189 .brp_min = 1,
190 .brp_max = 64,
191 .brp_inc = 1,
192};
193
194enum mcp251x_model {
195 CAN_MCP251X_MCP2510 = 0x2510,
196 CAN_MCP251X_MCP2515 = 0x2515,
197 CAN_MCP251X_MCP25625 = 0x25625,
198};
199
200struct mcp251x_priv {
201 struct can_priv can;
202 struct net_device *net;
203 struct spi_device *spi;
204 enum mcp251x_model model;
205
206 struct mutex mcp_lock; /* SPI device lock */
207
208 u8 *spi_tx_buf;
209 u8 *spi_rx_buf;
210
211 struct sk_buff *tx_skb;
212 int tx_len;
213
214 struct workqueue_struct *wq;
215 struct work_struct tx_work;
216 struct work_struct restart_work;
217
218 int force_quit;
219 int after_suspend;
220#define AFTER_SUSPEND_UP 1
221#define AFTER_SUSPEND_DOWN 2
222#define AFTER_SUSPEND_POWER 4
223#define AFTER_SUSPEND_RESTART 8
224 int restart_tx;
225 struct regulator *power;
226 struct regulator *transceiver;
227 struct clk *clk;
228};
229
230#define MCP251X_IS(_model) \
231static inline int mcp251x_is_##_model(struct spi_device *spi) \
232{ \
233 struct mcp251x_priv *priv = spi_get_drvdata(spi); \
234 return priv->model == CAN_MCP251X_MCP##_model; \
235}
236
237MCP251X_IS(2510);
238
239static void mcp251x_clean(struct net_device *net)
240{
241 struct mcp251x_priv *priv = netdev_priv(net);
242
243 if (priv->tx_skb || priv->tx_len)
244 net->stats.tx_errors++;
245 dev_kfree_skb(priv->tx_skb);
246 if (priv->tx_len)
247 can_free_echo_skb(priv->net, 0);
248 priv->tx_skb = NULL;
249 priv->tx_len = 0;
250}
251
252/* Note about handling of error return of mcp251x_spi_trans: accessing
253 * registers via SPI is not really different conceptually than using
254 * normal I/O assembler instructions, although it's much more
255 * complicated from a practical POV. So it's not advisable to always
256 * check the return value of this function. Imagine that every
257 * read{b,l}, write{b,l} and friends would be bracketed in "if ( < 0)
258 * error();", it would be a great mess (well there are some situation
259 * when exception handling C++ like could be useful after all). So we
260 * just check that transfers are OK at the beginning of our
261 * conversation with the chip and to avoid doing really nasty things
262 * (like injecting bogus packets in the network stack).
263 */
264static int mcp251x_spi_trans(struct spi_device *spi, int len)
265{
266 struct mcp251x_priv *priv = spi_get_drvdata(spi);
267 struct spi_transfer t = {
268 .tx_buf = priv->spi_tx_buf,
269 .rx_buf = priv->spi_rx_buf,
270 .len = len,
271 .cs_change = 0,
272 };
273 struct spi_message m;
274 int ret;
275
276 spi_message_init(&m);
277 spi_message_add_tail(&t, &m);
278
279 ret = spi_sync(spi, &m);
280 if (ret)
281 dev_err(&spi->dev, "spi transfer failed: ret = %d\n", ret);
282 return ret;
283}
284
285static u8 mcp251x_read_reg(struct spi_device *spi, u8 reg)
286{
287 struct mcp251x_priv *priv = spi_get_drvdata(spi);
288 u8 val = 0;
289
290 priv->spi_tx_buf[0] = INSTRUCTION_READ;
291 priv->spi_tx_buf[1] = reg;
292
293 mcp251x_spi_trans(spi, 3);
294 val = priv->spi_rx_buf[2];
295
296 return val;
297}
298
299static void mcp251x_read_2regs(struct spi_device *spi, u8 reg, u8 *v1, u8 *v2)
300{
301 struct mcp251x_priv *priv = spi_get_drvdata(spi);
302
303 priv->spi_tx_buf[0] = INSTRUCTION_READ;
304 priv->spi_tx_buf[1] = reg;
305
306 mcp251x_spi_trans(spi, 4);
307
308 *v1 = priv->spi_rx_buf[2];
309 *v2 = priv->spi_rx_buf[3];
310}
311
312static void mcp251x_write_reg(struct spi_device *spi, u8 reg, u8 val)
313{
314 struct mcp251x_priv *priv = spi_get_drvdata(spi);
315
316 priv->spi_tx_buf[0] = INSTRUCTION_WRITE;
317 priv->spi_tx_buf[1] = reg;
318 priv->spi_tx_buf[2] = val;
319
320 mcp251x_spi_trans(spi, 3);
321}
322
323static void mcp251x_write_2regs(struct spi_device *spi, u8 reg, u8 v1, u8 v2)
324{
325 struct mcp251x_priv *priv = spi_get_drvdata(spi);
326
327 priv->spi_tx_buf[0] = INSTRUCTION_WRITE;
328 priv->spi_tx_buf[1] = reg;
329 priv->spi_tx_buf[2] = v1;
330 priv->spi_tx_buf[3] = v2;
331
332 mcp251x_spi_trans(spi, 4);
333}
334
335static void mcp251x_write_bits(struct spi_device *spi, u8 reg,
336 u8 mask, u8 val)
337{
338 struct mcp251x_priv *priv = spi_get_drvdata(spi);
339
340 priv->spi_tx_buf[0] = INSTRUCTION_BIT_MODIFY;
341 priv->spi_tx_buf[1] = reg;
342 priv->spi_tx_buf[2] = mask;
343 priv->spi_tx_buf[3] = val;
344
345 mcp251x_spi_trans(spi, 4);
346}
347
348static void mcp251x_hw_tx_frame(struct spi_device *spi, u8 *buf,
349 int len, int tx_buf_idx)
350{
351 struct mcp251x_priv *priv = spi_get_drvdata(spi);
352
353 if (mcp251x_is_2510(spi)) {
354 int i;
355
356 for (i = 1; i < TXBDAT_OFF + len; i++)
357 mcp251x_write_reg(spi, TXBCTRL(tx_buf_idx) + i,
358 buf[i]);
359 } else {
360 memcpy(priv->spi_tx_buf, buf, TXBDAT_OFF + len);
361 mcp251x_spi_trans(spi, TXBDAT_OFF + len);
362 }
363}
364
365static void mcp251x_hw_tx(struct spi_device *spi, struct can_frame *frame,
366 int tx_buf_idx)
367{
368 struct mcp251x_priv *priv = spi_get_drvdata(spi);
369 u32 sid, eid, exide, rtr;
370 u8 buf[SPI_TRANSFER_BUF_LEN];
371
372 exide = (frame->can_id & CAN_EFF_FLAG) ? 1 : 0; /* Extended ID Enable */
373 if (exide)
374 sid = (frame->can_id & CAN_EFF_MASK) >> 18;
375 else
376 sid = frame->can_id & CAN_SFF_MASK; /* Standard ID */
377 eid = frame->can_id & CAN_EFF_MASK; /* Extended ID */
378 rtr = (frame->can_id & CAN_RTR_FLAG) ? 1 : 0; /* Remote transmission */
379
380 buf[TXBCTRL_OFF] = INSTRUCTION_LOAD_TXB(tx_buf_idx);
381 buf[TXBSIDH_OFF] = sid >> SIDH_SHIFT;
382 buf[TXBSIDL_OFF] = ((sid & SIDL_SID_MASK) << SIDL_SID_SHIFT) |
383 (exide << SIDL_EXIDE_SHIFT) |
384 ((eid >> SIDL_EID_SHIFT) & SIDL_EID_MASK);
385 buf[TXBEID8_OFF] = GET_BYTE(eid, 1);
386 buf[TXBEID0_OFF] = GET_BYTE(eid, 0);
387 buf[TXBDLC_OFF] = (rtr << DLC_RTR_SHIFT) | frame->can_dlc;
388 memcpy(buf + TXBDAT_OFF, frame->data, frame->can_dlc);
389 mcp251x_hw_tx_frame(spi, buf, frame->can_dlc, tx_buf_idx);
390
391 /* use INSTRUCTION_RTS, to avoid "repeated frame problem" */
392 priv->spi_tx_buf[0] = INSTRUCTION_RTS(1 << tx_buf_idx);
393 mcp251x_spi_trans(priv->spi, 1);
394}
395
396static void mcp251x_hw_rx_frame(struct spi_device *spi, u8 *buf,
397 int buf_idx)
398{
399 struct mcp251x_priv *priv = spi_get_drvdata(spi);
400
401 if (mcp251x_is_2510(spi)) {
402 int i, len;
403
404 for (i = 1; i < RXBDAT_OFF; i++)
405 buf[i] = mcp251x_read_reg(spi, RXBCTRL(buf_idx) + i);
406
407 len = get_can_dlc(buf[RXBDLC_OFF] & RXBDLC_LEN_MASK);
408 for (; i < (RXBDAT_OFF + len); i++)
409 buf[i] = mcp251x_read_reg(spi, RXBCTRL(buf_idx) + i);
410 } else {
411 priv->spi_tx_buf[RXBCTRL_OFF] = INSTRUCTION_READ_RXB(buf_idx);
412 mcp251x_spi_trans(spi, SPI_TRANSFER_BUF_LEN);
413 memcpy(buf, priv->spi_rx_buf, SPI_TRANSFER_BUF_LEN);
414 }
415}
416
417static void mcp251x_hw_rx(struct spi_device *spi, int buf_idx)
418{
419 struct mcp251x_priv *priv = spi_get_drvdata(spi);
420 struct sk_buff *skb;
421 struct can_frame *frame;
422 u8 buf[SPI_TRANSFER_BUF_LEN];
423
424 skb = alloc_can_skb(priv->net, &frame);
425 if (!skb) {
426 dev_err(&spi->dev, "cannot allocate RX skb\n");
427 priv->net->stats.rx_dropped++;
428 return;
429 }
430
431 mcp251x_hw_rx_frame(spi, buf, buf_idx);
432 if (buf[RXBSIDL_OFF] & RXBSIDL_IDE) {
433 /* Extended ID format */
434 frame->can_id = CAN_EFF_FLAG;
435 frame->can_id |=
436 /* Extended ID part */
437 SET_BYTE(buf[RXBSIDL_OFF] & RXBSIDL_EID, 2) |
438 SET_BYTE(buf[RXBEID8_OFF], 1) |
439 SET_BYTE(buf[RXBEID0_OFF], 0) |
440 /* Standard ID part */
441 (((buf[RXBSIDH_OFF] << RXBSIDH_SHIFT) |
442 (buf[RXBSIDL_OFF] >> RXBSIDL_SHIFT)) << 18);
443 /* Remote transmission request */
444 if (buf[RXBDLC_OFF] & RXBDLC_RTR)
445 frame->can_id |= CAN_RTR_FLAG;
446 } else {
447 /* Standard ID format */
448 frame->can_id =
449 (buf[RXBSIDH_OFF] << RXBSIDH_SHIFT) |
450 (buf[RXBSIDL_OFF] >> RXBSIDL_SHIFT);
451 if (buf[RXBSIDL_OFF] & RXBSIDL_SRR)
452 frame->can_id |= CAN_RTR_FLAG;
453 }
454 /* Data length */
455 frame->can_dlc = get_can_dlc(buf[RXBDLC_OFF] & RXBDLC_LEN_MASK);
456 memcpy(frame->data, buf + RXBDAT_OFF, frame->can_dlc);
457
458 priv->net->stats.rx_packets++;
459 priv->net->stats.rx_bytes += frame->can_dlc;
460
461 can_led_event(priv->net, CAN_LED_EVENT_RX);
462
463 netif_rx_ni(skb);
464}
465
466static void mcp251x_hw_sleep(struct spi_device *spi)
467{
468 mcp251x_write_reg(spi, CANCTRL, CANCTRL_REQOP_SLEEP);
469}
470
471/* May only be called when device is sleeping! */
472static int mcp251x_hw_wake(struct spi_device *spi)
473{
474 unsigned long timeout;
475
476 /* Force wakeup interrupt to wake device, but don't execute IST */
477 disable_irq(spi->irq);
478 mcp251x_write_2regs(spi, CANINTE, CANINTE_WAKIE, CANINTF_WAKIF);
479
480 /* Wait for oscillator startup timer after wake up */
481 mdelay(MCP251X_OST_DELAY_MS);
482
483 /* Put device into config mode */
484 mcp251x_write_reg(spi, CANCTRL, CANCTRL_REQOP_CONF);
485
486 /* Wait for the device to enter config mode */
487 timeout = jiffies + HZ;
488 while ((mcp251x_read_reg(spi, CANSTAT) & CANCTRL_REQOP_MASK) !=
489 CANCTRL_REQOP_CONF) {
490 schedule();
491 if (time_after(jiffies, timeout)) {
492 dev_err(&spi->dev, "MCP251x didn't enter in config mode\n");
493 return -EBUSY;
494 }
495 }
496
497 /* Disable and clear pending interrupts */
498 mcp251x_write_2regs(spi, CANINTE, 0x00, 0x00);
499 enable_irq(spi->irq);
500
501 return 0;
502}
503
504static netdev_tx_t mcp251x_hard_start_xmit(struct sk_buff *skb,
505 struct net_device *net)
506{
507 struct mcp251x_priv *priv = netdev_priv(net);
508 struct spi_device *spi = priv->spi;
509
510 if (priv->tx_skb || priv->tx_len) {
511 dev_warn(&spi->dev, "hard_xmit called while tx busy\n");
512 return NETDEV_TX_BUSY;
513 }
514
515 if (can_dropped_invalid_skb(net, skb))
516 return NETDEV_TX_OK;
517
518 netif_stop_queue(net);
519 priv->tx_skb = skb;
520 queue_work(priv->wq, &priv->tx_work);
521
522 return NETDEV_TX_OK;
523}
524
525static int mcp251x_do_set_mode(struct net_device *net, enum can_mode mode)
526{
527 struct mcp251x_priv *priv = netdev_priv(net);
528
529 switch (mode) {
530 case CAN_MODE_START:
531 mcp251x_clean(net);
532 /* We have to delay work since SPI I/O may sleep */
533 priv->can.state = CAN_STATE_ERROR_ACTIVE;
534 priv->restart_tx = 1;
535 if (priv->can.restart_ms == 0)
536 priv->after_suspend = AFTER_SUSPEND_RESTART;
537 queue_work(priv->wq, &priv->restart_work);
538 break;
539 default:
540 return -EOPNOTSUPP;
541 }
542
543 return 0;
544}
545
546static int mcp251x_set_normal_mode(struct spi_device *spi)
547{
548 struct mcp251x_priv *priv = spi_get_drvdata(spi);
549 unsigned long timeout;
550
551 /* Enable interrupts */
552 mcp251x_write_reg(spi, CANINTE,
553 CANINTE_ERRIE | CANINTE_TX2IE | CANINTE_TX1IE |
554 CANINTE_TX0IE | CANINTE_RX1IE | CANINTE_RX0IE);
555
556 if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK) {
557 /* Put device into loopback mode */
558 mcp251x_write_reg(spi, CANCTRL, CANCTRL_REQOP_LOOPBACK);
559 } else if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY) {
560 /* Put device into listen-only mode */
561 mcp251x_write_reg(spi, CANCTRL, CANCTRL_REQOP_LISTEN_ONLY);
562 } else {
563 /* Put device into normal mode */
564 mcp251x_write_reg(spi, CANCTRL, CANCTRL_REQOP_NORMAL);
565
566 /* Wait for the device to enter normal mode */
567 timeout = jiffies + HZ;
568 while (mcp251x_read_reg(spi, CANSTAT) & CANCTRL_REQOP_MASK) {
569 schedule();
570 if (time_after(jiffies, timeout)) {
571 dev_err(&spi->dev, "MCP251x didn't enter in normal mode\n");
572 return -EBUSY;
573 }
574 }
575 }
576 priv->can.state = CAN_STATE_ERROR_ACTIVE;
577 return 0;
578}
579
580static int mcp251x_do_set_bittiming(struct net_device *net)
581{
582 struct mcp251x_priv *priv = netdev_priv(net);
583 struct can_bittiming *bt = &priv->can.bittiming;
584 struct spi_device *spi = priv->spi;
585
586 mcp251x_write_reg(spi, CNF1, ((bt->sjw - 1) << CNF1_SJW_SHIFT) |
587 (bt->brp - 1));
588 mcp251x_write_reg(spi, CNF2, CNF2_BTLMODE |
589 (priv->can.ctrlmode & CAN_CTRLMODE_3_SAMPLES ?
590 CNF2_SAM : 0) |
591 ((bt->phase_seg1 - 1) << CNF2_PS1_SHIFT) |
592 (bt->prop_seg - 1));
593 mcp251x_write_bits(spi, CNF3, CNF3_PHSEG2_MASK,
594 (bt->phase_seg2 - 1));
595 dev_dbg(&spi->dev, "CNF: 0x%02x 0x%02x 0x%02x\n",
596 mcp251x_read_reg(spi, CNF1),
597 mcp251x_read_reg(spi, CNF2),
598 mcp251x_read_reg(spi, CNF3));
599
600 return 0;
601}
602
603static int mcp251x_setup(struct net_device *net, struct spi_device *spi)
604{
605 mcp251x_do_set_bittiming(net);
606
607 mcp251x_write_reg(spi, RXBCTRL(0),
608 RXBCTRL_BUKT | RXBCTRL_RXM0 | RXBCTRL_RXM1);
609 mcp251x_write_reg(spi, RXBCTRL(1),
610 RXBCTRL_RXM0 | RXBCTRL_RXM1);
611 return 0;
612}
613
614static int mcp251x_hw_reset(struct spi_device *spi)
615{
616 struct mcp251x_priv *priv = spi_get_drvdata(spi);
617 unsigned long timeout;
618 int ret;
619
620 /* Wait for oscillator startup timer after power up */
621 mdelay(MCP251X_OST_DELAY_MS);
622
623 priv->spi_tx_buf[0] = INSTRUCTION_RESET;
624 ret = mcp251x_spi_trans(spi, 1);
625 if (ret)
626 return ret;
627
628 /* Wait for oscillator startup timer after reset */
629 mdelay(MCP251X_OST_DELAY_MS);
630
631 /* Wait for reset to finish */
632 timeout = jiffies + HZ;
633 while ((mcp251x_read_reg(spi, CANSTAT) & CANCTRL_REQOP_MASK) !=
634 CANCTRL_REQOP_CONF) {
635 usleep_range(MCP251X_OST_DELAY_MS * 1000,
636 MCP251X_OST_DELAY_MS * 1000 * 2);
637
638 if (time_after(jiffies, timeout)) {
639 dev_err(&spi->dev,
640 "MCP251x didn't enter in conf mode after reset\n");
641 return -EBUSY;
642 }
643 }
644 return 0;
645}
646
647static int mcp251x_hw_probe(struct spi_device *spi)
648{
649 u8 ctrl;
650 int ret;
651
652 ret = mcp251x_hw_reset(spi);
653 if (ret)
654 return ret;
655
656 ctrl = mcp251x_read_reg(spi, CANCTRL);
657
658 dev_dbg(&spi->dev, "CANCTRL 0x%02x\n", ctrl);
659
660 /* Check for power up default value */
661 if ((ctrl & 0x17) != 0x07)
662 return -ENODEV;
663
664 return 0;
665}
666
667static int mcp251x_power_enable(struct regulator *reg, int enable)
668{
669 if (IS_ERR_OR_NULL(reg))
670 return 0;
671
672 if (enable)
673 return regulator_enable(reg);
674 else
675 return regulator_disable(reg);
676}
677
678static int mcp251x_stop(struct net_device *net)
679{
680 struct mcp251x_priv *priv = netdev_priv(net);
681 struct spi_device *spi = priv->spi;
682
683 close_candev(net);
684
685 priv->force_quit = 1;
686 free_irq(spi->irq, priv);
687 destroy_workqueue(priv->wq);
688 priv->wq = NULL;
689
690 mutex_lock(&priv->mcp_lock);
691
692 /* Disable and clear pending interrupts */
693 mcp251x_write_2regs(spi, CANINTE, 0x00, 0x00);
694
695 mcp251x_write_reg(spi, TXBCTRL(0), 0);
696 mcp251x_clean(net);
697
698 mcp251x_hw_sleep(spi);
699
700 mcp251x_power_enable(priv->transceiver, 0);
701
702 priv->can.state = CAN_STATE_STOPPED;
703
704 mutex_unlock(&priv->mcp_lock);
705
706 can_led_event(net, CAN_LED_EVENT_STOP);
707
708 return 0;
709}
710
711static void mcp251x_error_skb(struct net_device *net, int can_id, int data1)
712{
713 struct sk_buff *skb;
714 struct can_frame *frame;
715
716 skb = alloc_can_err_skb(net, &frame);
717 if (skb) {
718 frame->can_id |= can_id;
719 frame->data[1] = data1;
720 netif_rx_ni(skb);
721 } else {
722 netdev_err(net, "cannot allocate error skb\n");
723 }
724}
725
726static void mcp251x_tx_work_handler(struct work_struct *ws)
727{
728 struct mcp251x_priv *priv = container_of(ws, struct mcp251x_priv,
729 tx_work);
730 struct spi_device *spi = priv->spi;
731 struct net_device *net = priv->net;
732 struct can_frame *frame;
733
734 mutex_lock(&priv->mcp_lock);
735 if (priv->tx_skb) {
736 if (priv->can.state == CAN_STATE_BUS_OFF) {
737 mcp251x_clean(net);
738 } else {
739 frame = (struct can_frame *)priv->tx_skb->data;
740
741 if (frame->can_dlc > CAN_FRAME_MAX_DATA_LEN)
742 frame->can_dlc = CAN_FRAME_MAX_DATA_LEN;
743 mcp251x_hw_tx(spi, frame, 0);
744 priv->tx_len = 1 + frame->can_dlc;
745 can_put_echo_skb(priv->tx_skb, net, 0);
746 priv->tx_skb = NULL;
747 }
748 }
749 mutex_unlock(&priv->mcp_lock);
750}
751
752static void mcp251x_restart_work_handler(struct work_struct *ws)
753{
754 struct mcp251x_priv *priv = container_of(ws, struct mcp251x_priv,
755 restart_work);
756 struct spi_device *spi = priv->spi;
757 struct net_device *net = priv->net;
758
759 mutex_lock(&priv->mcp_lock);
760 if (priv->after_suspend) {
761 if (priv->after_suspend & AFTER_SUSPEND_POWER) {
762 mcp251x_hw_reset(spi);
763 mcp251x_setup(net, spi);
764 } else {
765 mcp251x_hw_wake(spi);
766 }
767 priv->force_quit = 0;
768 if (priv->after_suspend & AFTER_SUSPEND_RESTART) {
769 mcp251x_set_normal_mode(spi);
770 } else if (priv->after_suspend & AFTER_SUSPEND_UP) {
771 netif_device_attach(net);
772 mcp251x_clean(net);
773 mcp251x_set_normal_mode(spi);
774 netif_wake_queue(net);
775 } else {
776 mcp251x_hw_sleep(spi);
777 }
778 priv->after_suspend = 0;
779 }
780
781 if (priv->restart_tx) {
782 priv->restart_tx = 0;
783 mcp251x_write_reg(spi, TXBCTRL(0), 0);
784 mcp251x_clean(net);
785 netif_wake_queue(net);
786 mcp251x_error_skb(net, CAN_ERR_RESTARTED, 0);
787 }
788 mutex_unlock(&priv->mcp_lock);
789}
790
791static irqreturn_t mcp251x_can_ist(int irq, void *dev_id)
792{
793 struct mcp251x_priv *priv = dev_id;
794 struct spi_device *spi = priv->spi;
795 struct net_device *net = priv->net;
796
797 mutex_lock(&priv->mcp_lock);
798 while (!priv->force_quit) {
799 enum can_state new_state;
800 u8 intf, eflag;
801 u8 clear_intf = 0;
802 int can_id = 0, data1 = 0;
803
804 mcp251x_read_2regs(spi, CANINTF, &intf, &eflag);
805
806 /* mask out flags we don't care about */
807 intf &= CANINTF_RX | CANINTF_TX | CANINTF_ERR;
808
809 /* receive buffer 0 */
810 if (intf & CANINTF_RX0IF) {
811 mcp251x_hw_rx(spi, 0);
812 /* Free one buffer ASAP
813 * (The MCP2515/25625 does this automatically.)
814 */
815 if (mcp251x_is_2510(spi))
816 mcp251x_write_bits(spi, CANINTF,
817 CANINTF_RX0IF, 0x00);
818 }
819
820 /* receive buffer 1 */
821 if (intf & CANINTF_RX1IF) {
822 mcp251x_hw_rx(spi, 1);
823 /* The MCP2515/25625 does this automatically. */
824 if (mcp251x_is_2510(spi))
825 clear_intf |= CANINTF_RX1IF;
826 }
827
828 /* any error or tx interrupt we need to clear? */
829 if (intf & (CANINTF_ERR | CANINTF_TX))
830 clear_intf |= intf & (CANINTF_ERR | CANINTF_TX);
831 if (clear_intf)
832 mcp251x_write_bits(spi, CANINTF, clear_intf, 0x00);
833
834 if (eflag & (EFLG_RX0OVR | EFLG_RX1OVR))
835 mcp251x_write_bits(spi, EFLG, eflag, 0x00);
836
837 /* Update can state */
838 if (eflag & EFLG_TXBO) {
839 new_state = CAN_STATE_BUS_OFF;
840 can_id |= CAN_ERR_BUSOFF;
841 } else if (eflag & EFLG_TXEP) {
842 new_state = CAN_STATE_ERROR_PASSIVE;
843 can_id |= CAN_ERR_CRTL;
844 data1 |= CAN_ERR_CRTL_TX_PASSIVE;
845 } else if (eflag & EFLG_RXEP) {
846 new_state = CAN_STATE_ERROR_PASSIVE;
847 can_id |= CAN_ERR_CRTL;
848 data1 |= CAN_ERR_CRTL_RX_PASSIVE;
849 } else if (eflag & EFLG_TXWAR) {
850 new_state = CAN_STATE_ERROR_WARNING;
851 can_id |= CAN_ERR_CRTL;
852 data1 |= CAN_ERR_CRTL_TX_WARNING;
853 } else if (eflag & EFLG_RXWAR) {
854 new_state = CAN_STATE_ERROR_WARNING;
855 can_id |= CAN_ERR_CRTL;
856 data1 |= CAN_ERR_CRTL_RX_WARNING;
857 } else {
858 new_state = CAN_STATE_ERROR_ACTIVE;
859 }
860
861 /* Update can state statistics */
862 switch (priv->can.state) {
863 case CAN_STATE_ERROR_ACTIVE:
864 if (new_state >= CAN_STATE_ERROR_WARNING &&
865 new_state <= CAN_STATE_BUS_OFF)
866 priv->can.can_stats.error_warning++;
867 fallthrough;
868 case CAN_STATE_ERROR_WARNING:
869 if (new_state >= CAN_STATE_ERROR_PASSIVE &&
870 new_state <= CAN_STATE_BUS_OFF)
871 priv->can.can_stats.error_passive++;
872 break;
873 default:
874 break;
875 }
876 priv->can.state = new_state;
877
878 if (intf & CANINTF_ERRIF) {
879 /* Handle overflow counters */
880 if (eflag & (EFLG_RX0OVR | EFLG_RX1OVR)) {
881 if (eflag & EFLG_RX0OVR) {
882 net->stats.rx_over_errors++;
883 net->stats.rx_errors++;
884 }
885 if (eflag & EFLG_RX1OVR) {
886 net->stats.rx_over_errors++;
887 net->stats.rx_errors++;
888 }
889 can_id |= CAN_ERR_CRTL;
890 data1 |= CAN_ERR_CRTL_RX_OVERFLOW;
891 }
892 mcp251x_error_skb(net, can_id, data1);
893 }
894
895 if (priv->can.state == CAN_STATE_BUS_OFF) {
896 if (priv->can.restart_ms == 0) {
897 priv->force_quit = 1;
898 priv->can.can_stats.bus_off++;
899 can_bus_off(net);
900 mcp251x_hw_sleep(spi);
901 break;
902 }
903 }
904
905 if (intf == 0)
906 break;
907
908 if (intf & CANINTF_TX) {
909 net->stats.tx_packets++;
910 net->stats.tx_bytes += priv->tx_len - 1;
911 can_led_event(net, CAN_LED_EVENT_TX);
912 if (priv->tx_len) {
913 can_get_echo_skb(net, 0);
914 priv->tx_len = 0;
915 }
916 netif_wake_queue(net);
917 }
918 }
919 mutex_unlock(&priv->mcp_lock);
920 return IRQ_HANDLED;
921}
922
923static int mcp251x_open(struct net_device *net)
924{
925 struct mcp251x_priv *priv = netdev_priv(net);
926 struct spi_device *spi = priv->spi;
927 unsigned long flags = 0;
928 int ret;
929
930 ret = open_candev(net);
931 if (ret) {
932 dev_err(&spi->dev, "unable to set initial baudrate!\n");
933 return ret;
934 }
935
936 mutex_lock(&priv->mcp_lock);
937 mcp251x_power_enable(priv->transceiver, 1);
938
939 priv->force_quit = 0;
940 priv->tx_skb = NULL;
941 priv->tx_len = 0;
942
943 if (!dev_fwnode(&spi->dev))
944 flags = IRQF_TRIGGER_FALLING;
945
946 ret = request_threaded_irq(spi->irq, NULL, mcp251x_can_ist,
947 flags | IRQF_ONESHOT, dev_name(&spi->dev),
948 priv);
949 if (ret) {
950 dev_err(&spi->dev, "failed to acquire irq %d\n", spi->irq);
951 goto out_close;
952 }
953
954 priv->wq = alloc_workqueue("mcp251x_wq", WQ_FREEZABLE | WQ_MEM_RECLAIM,
955 0);
956 if (!priv->wq) {
957 ret = -ENOMEM;
958 goto out_clean;
959 }
960 INIT_WORK(&priv->tx_work, mcp251x_tx_work_handler);
961 INIT_WORK(&priv->restart_work, mcp251x_restart_work_handler);
962
963 ret = mcp251x_hw_wake(spi);
964 if (ret)
965 goto out_free_wq;
966 ret = mcp251x_setup(net, spi);
967 if (ret)
968 goto out_free_wq;
969 ret = mcp251x_set_normal_mode(spi);
970 if (ret)
971 goto out_free_wq;
972
973 can_led_event(net, CAN_LED_EVENT_OPEN);
974
975 netif_wake_queue(net);
976 mutex_unlock(&priv->mcp_lock);
977
978 return 0;
979
980out_free_wq:
981 destroy_workqueue(priv->wq);
982out_clean:
983 free_irq(spi->irq, priv);
984 mcp251x_hw_sleep(spi);
985out_close:
986 mcp251x_power_enable(priv->transceiver, 0);
987 close_candev(net);
988 mutex_unlock(&priv->mcp_lock);
989 return ret;
990}
991
992static const struct net_device_ops mcp251x_netdev_ops = {
993 .ndo_open = mcp251x_open,
994 .ndo_stop = mcp251x_stop,
995 .ndo_start_xmit = mcp251x_hard_start_xmit,
996 .ndo_change_mtu = can_change_mtu,
997};
998
999static const struct of_device_id mcp251x_of_match[] = {
1000 {
1001 .compatible = "microchip,mcp2510",
1002 .data = (void *)CAN_MCP251X_MCP2510,
1003 },
1004 {
1005 .compatible = "microchip,mcp2515",
1006 .data = (void *)CAN_MCP251X_MCP2515,
1007 },
1008 {
1009 .compatible = "microchip,mcp25625",
1010 .data = (void *)CAN_MCP251X_MCP25625,
1011 },
1012 { }
1013};
1014MODULE_DEVICE_TABLE(of, mcp251x_of_match);
1015
1016static const struct spi_device_id mcp251x_id_table[] = {
1017 {
1018 .name = "mcp2510",
1019 .driver_data = (kernel_ulong_t)CAN_MCP251X_MCP2510,
1020 },
1021 {
1022 .name = "mcp2515",
1023 .driver_data = (kernel_ulong_t)CAN_MCP251X_MCP2515,
1024 },
1025 {
1026 .name = "mcp25625",
1027 .driver_data = (kernel_ulong_t)CAN_MCP251X_MCP25625,
1028 },
1029 { }
1030};
1031MODULE_DEVICE_TABLE(spi, mcp251x_id_table);
1032
1033static int mcp251x_can_probe(struct spi_device *spi)
1034{
1035 const void *match = device_get_match_data(&spi->dev);
1036 struct net_device *net;
1037 struct mcp251x_priv *priv;
1038 struct clk *clk;
1039 u32 freq;
1040 int ret;
1041
1042 clk = devm_clk_get_optional(&spi->dev, NULL);
1043 if (IS_ERR(clk))
1044 return PTR_ERR(clk);
1045
1046 freq = clk_get_rate(clk);
1047 if (freq == 0)
1048 device_property_read_u32(&spi->dev, "clock-frequency", &freq);
1049
1050 /* Sanity check */
1051 if (freq < 1000000 || freq > 25000000)
1052 return -ERANGE;
1053
1054 /* Allocate can/net device */
1055 net = alloc_candev(sizeof(struct mcp251x_priv), TX_ECHO_SKB_MAX);
1056 if (!net)
1057 return -ENOMEM;
1058
1059 ret = clk_prepare_enable(clk);
1060 if (ret)
1061 goto out_free;
1062
1063 net->netdev_ops = &mcp251x_netdev_ops;
1064 net->flags |= IFF_ECHO;
1065
1066 priv = netdev_priv(net);
1067 priv->can.bittiming_const = &mcp251x_bittiming_const;
1068 priv->can.do_set_mode = mcp251x_do_set_mode;
1069 priv->can.clock.freq = freq / 2;
1070 priv->can.ctrlmode_supported = CAN_CTRLMODE_3_SAMPLES |
1071 CAN_CTRLMODE_LOOPBACK | CAN_CTRLMODE_LISTENONLY;
1072 if (match)
1073 priv->model = (enum mcp251x_model)match;
1074 else
1075 priv->model = spi_get_device_id(spi)->driver_data;
1076 priv->net = net;
1077 priv->clk = clk;
1078
1079 spi_set_drvdata(spi, priv);
1080
1081 /* Configure the SPI bus */
1082 spi->bits_per_word = 8;
1083 if (mcp251x_is_2510(spi))
1084 spi->max_speed_hz = spi->max_speed_hz ? : 5 * 1000 * 1000;
1085 else
1086 spi->max_speed_hz = spi->max_speed_hz ? : 10 * 1000 * 1000;
1087 ret = spi_setup(spi);
1088 if (ret)
1089 goto out_clk;
1090
1091 priv->power = devm_regulator_get_optional(&spi->dev, "vdd");
1092 priv->transceiver = devm_regulator_get_optional(&spi->dev, "xceiver");
1093 if ((PTR_ERR(priv->power) == -EPROBE_DEFER) ||
1094 (PTR_ERR(priv->transceiver) == -EPROBE_DEFER)) {
1095 ret = -EPROBE_DEFER;
1096 goto out_clk;
1097 }
1098
1099 ret = mcp251x_power_enable(priv->power, 1);
1100 if (ret)
1101 goto out_clk;
1102
1103 priv->spi = spi;
1104 mutex_init(&priv->mcp_lock);
1105
1106 priv->spi_tx_buf = devm_kzalloc(&spi->dev, SPI_TRANSFER_BUF_LEN,
1107 GFP_KERNEL);
1108 if (!priv->spi_tx_buf) {
1109 ret = -ENOMEM;
1110 goto error_probe;
1111 }
1112
1113 priv->spi_rx_buf = devm_kzalloc(&spi->dev, SPI_TRANSFER_BUF_LEN,
1114 GFP_KERNEL);
1115 if (!priv->spi_rx_buf) {
1116 ret = -ENOMEM;
1117 goto error_probe;
1118 }
1119
1120 SET_NETDEV_DEV(net, &spi->dev);
1121
1122 /* Here is OK to not lock the MCP, no one knows about it yet */
1123 ret = mcp251x_hw_probe(spi);
1124 if (ret) {
1125 if (ret == -ENODEV)
1126 dev_err(&spi->dev, "Cannot initialize MCP%x. Wrong wiring?\n",
1127 priv->model);
1128 goto error_probe;
1129 }
1130
1131 mcp251x_hw_sleep(spi);
1132
1133 ret = register_candev(net);
1134 if (ret)
1135 goto error_probe;
1136
1137 devm_can_led_init(net);
1138
1139 netdev_info(net, "MCP%x successfully initialized.\n", priv->model);
1140 return 0;
1141
1142error_probe:
1143 mcp251x_power_enable(priv->power, 0);
1144
1145out_clk:
1146 clk_disable_unprepare(clk);
1147
1148out_free:
1149 free_candev(net);
1150
1151 dev_err(&spi->dev, "Probe failed, err=%d\n", -ret);
1152 return ret;
1153}
1154
1155static int mcp251x_can_remove(struct spi_device *spi)
1156{
1157 struct mcp251x_priv *priv = spi_get_drvdata(spi);
1158 struct net_device *net = priv->net;
1159
1160 unregister_candev(net);
1161
1162 mcp251x_power_enable(priv->power, 0);
1163
1164 clk_disable_unprepare(priv->clk);
1165
1166 free_candev(net);
1167
1168 return 0;
1169}
1170
1171static int __maybe_unused mcp251x_can_suspend(struct device *dev)
1172{
1173 struct spi_device *spi = to_spi_device(dev);
1174 struct mcp251x_priv *priv = spi_get_drvdata(spi);
1175 struct net_device *net = priv->net;
1176
1177 priv->force_quit = 1;
1178 disable_irq(spi->irq);
1179 /* Note: at this point neither IST nor workqueues are running.
1180 * open/stop cannot be called anyway so locking is not needed
1181 */
1182 if (netif_running(net)) {
1183 netif_device_detach(net);
1184
1185 mcp251x_hw_sleep(spi);
1186 mcp251x_power_enable(priv->transceiver, 0);
1187 priv->after_suspend = AFTER_SUSPEND_UP;
1188 } else {
1189 priv->after_suspend = AFTER_SUSPEND_DOWN;
1190 }
1191
1192 mcp251x_power_enable(priv->power, 0);
1193 priv->after_suspend |= AFTER_SUSPEND_POWER;
1194
1195 return 0;
1196}
1197
1198static int __maybe_unused mcp251x_can_resume(struct device *dev)
1199{
1200 struct spi_device *spi = to_spi_device(dev);
1201 struct mcp251x_priv *priv = spi_get_drvdata(spi);
1202
1203 if (priv->after_suspend & AFTER_SUSPEND_POWER)
1204 mcp251x_power_enable(priv->power, 1);
1205 if (priv->after_suspend & AFTER_SUSPEND_UP)
1206 mcp251x_power_enable(priv->transceiver, 1);
1207
1208 if (priv->after_suspend & (AFTER_SUSPEND_POWER | AFTER_SUSPEND_UP))
1209 queue_work(priv->wq, &priv->restart_work);
1210 else
1211 priv->after_suspend = 0;
1212
1213 priv->force_quit = 0;
1214 enable_irq(spi->irq);
1215 return 0;
1216}
1217
1218static SIMPLE_DEV_PM_OPS(mcp251x_can_pm_ops, mcp251x_can_suspend,
1219 mcp251x_can_resume);
1220
1221static struct spi_driver mcp251x_can_driver = {
1222 .driver = {
1223 .name = DEVICE_NAME,
1224 .of_match_table = mcp251x_of_match,
1225 .pm = &mcp251x_can_pm_ops,
1226 },
1227 .id_table = mcp251x_id_table,
1228 .probe = mcp251x_can_probe,
1229 .remove = mcp251x_can_remove,
1230};
1231module_spi_driver(mcp251x_can_driver);
1232
1233MODULE_AUTHOR("Chris Elston <celston@katalix.com>, "
1234 "Christian Pellegrin <chripell@evolware.org>");
1235MODULE_DESCRIPTION("Microchip 251x/25625 CAN driver");
1236MODULE_LICENSE("GPL v2");
1/*
2 * CAN bus driver for Microchip 251x CAN Controller with SPI Interface
3 *
4 * MCP2510 support and bug fixes by Christian Pellegrin
5 * <chripell@evolware.org>
6 *
7 * Copyright 2009 Christian Pellegrin EVOL S.r.l.
8 *
9 * Copyright 2007 Raymarine UK, Ltd. All Rights Reserved.
10 * Written under contract by:
11 * Chris Elston, Katalix Systems, Ltd.
12 *
13 * Based on Microchip MCP251x CAN controller driver written by
14 * David Vrabel, Copyright 2006 Arcom Control Systems Ltd.
15 *
16 * Based on CAN bus driver for the CCAN controller written by
17 * - Sascha Hauer, Marc Kleine-Budde, Pengutronix
18 * - Simon Kallweit, intefo AG
19 * Copyright 2007
20 *
21 * This program is free software; you can redistribute it and/or modify
22 * it under the terms of the version 2 of the GNU General Public License
23 * as published by the Free Software Foundation
24 *
25 * This program is distributed in the hope that it will be useful,
26 * but WITHOUT ANY WARRANTY; without even the implied warranty of
27 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
28 * GNU General Public License for more details.
29 *
30 * You should have received a copy of the GNU General Public License
31 * along with this program; if not, see <http://www.gnu.org/licenses/>.
32 *
33 *
34 *
35 * Your platform definition file should specify something like:
36 *
37 * static struct mcp251x_platform_data mcp251x_info = {
38 * .oscillator_frequency = 8000000,
39 * };
40 *
41 * static struct spi_board_info spi_board_info[] = {
42 * {
43 * .modalias = "mcp2510",
44 * // or "mcp2515" depending on your controller
45 * .platform_data = &mcp251x_info,
46 * .irq = IRQ_EINT13,
47 * .max_speed_hz = 2*1000*1000,
48 * .chip_select = 2,
49 * },
50 * };
51 *
52 * Please see mcp251x.h for a description of the fields in
53 * struct mcp251x_platform_data.
54 *
55 */
56
57#include <linux/can/core.h>
58#include <linux/can/dev.h>
59#include <linux/can/led.h>
60#include <linux/can/platform/mcp251x.h>
61#include <linux/clk.h>
62#include <linux/completion.h>
63#include <linux/delay.h>
64#include <linux/device.h>
65#include <linux/dma-mapping.h>
66#include <linux/freezer.h>
67#include <linux/interrupt.h>
68#include <linux/io.h>
69#include <linux/kernel.h>
70#include <linux/module.h>
71#include <linux/netdevice.h>
72#include <linux/of.h>
73#include <linux/of_device.h>
74#include <linux/platform_device.h>
75#include <linux/slab.h>
76#include <linux/spi/spi.h>
77#include <linux/uaccess.h>
78#include <linux/regulator/consumer.h>
79
80/* SPI interface instruction set */
81#define INSTRUCTION_WRITE 0x02
82#define INSTRUCTION_READ 0x03
83#define INSTRUCTION_BIT_MODIFY 0x05
84#define INSTRUCTION_LOAD_TXB(n) (0x40 + 2 * (n))
85#define INSTRUCTION_READ_RXB(n) (((n) == 0) ? 0x90 : 0x94)
86#define INSTRUCTION_RESET 0xC0
87#define RTS_TXB0 0x01
88#define RTS_TXB1 0x02
89#define RTS_TXB2 0x04
90#define INSTRUCTION_RTS(n) (0x80 | ((n) & 0x07))
91
92
93/* MPC251x registers */
94#define CANSTAT 0x0e
95#define CANCTRL 0x0f
96# define CANCTRL_REQOP_MASK 0xe0
97# define CANCTRL_REQOP_CONF 0x80
98# define CANCTRL_REQOP_LISTEN_ONLY 0x60
99# define CANCTRL_REQOP_LOOPBACK 0x40
100# define CANCTRL_REQOP_SLEEP 0x20
101# define CANCTRL_REQOP_NORMAL 0x00
102# define CANCTRL_OSM 0x08
103# define CANCTRL_ABAT 0x10
104#define TEC 0x1c
105#define REC 0x1d
106#define CNF1 0x2a
107# define CNF1_SJW_SHIFT 6
108#define CNF2 0x29
109# define CNF2_BTLMODE 0x80
110# define CNF2_SAM 0x40
111# define CNF2_PS1_SHIFT 3
112#define CNF3 0x28
113# define CNF3_SOF 0x08
114# define CNF3_WAKFIL 0x04
115# define CNF3_PHSEG2_MASK 0x07
116#define CANINTE 0x2b
117# define CANINTE_MERRE 0x80
118# define CANINTE_WAKIE 0x40
119# define CANINTE_ERRIE 0x20
120# define CANINTE_TX2IE 0x10
121# define CANINTE_TX1IE 0x08
122# define CANINTE_TX0IE 0x04
123# define CANINTE_RX1IE 0x02
124# define CANINTE_RX0IE 0x01
125#define CANINTF 0x2c
126# define CANINTF_MERRF 0x80
127# define CANINTF_WAKIF 0x40
128# define CANINTF_ERRIF 0x20
129# define CANINTF_TX2IF 0x10
130# define CANINTF_TX1IF 0x08
131# define CANINTF_TX0IF 0x04
132# define CANINTF_RX1IF 0x02
133# define CANINTF_RX0IF 0x01
134# define CANINTF_RX (CANINTF_RX0IF | CANINTF_RX1IF)
135# define CANINTF_TX (CANINTF_TX2IF | CANINTF_TX1IF | CANINTF_TX0IF)
136# define CANINTF_ERR (CANINTF_ERRIF)
137#define EFLG 0x2d
138# define EFLG_EWARN 0x01
139# define EFLG_RXWAR 0x02
140# define EFLG_TXWAR 0x04
141# define EFLG_RXEP 0x08
142# define EFLG_TXEP 0x10
143# define EFLG_TXBO 0x20
144# define EFLG_RX0OVR 0x40
145# define EFLG_RX1OVR 0x80
146#define TXBCTRL(n) (((n) * 0x10) + 0x30 + TXBCTRL_OFF)
147# define TXBCTRL_ABTF 0x40
148# define TXBCTRL_MLOA 0x20
149# define TXBCTRL_TXERR 0x10
150# define TXBCTRL_TXREQ 0x08
151#define TXBSIDH(n) (((n) * 0x10) + 0x30 + TXBSIDH_OFF)
152# define SIDH_SHIFT 3
153#define TXBSIDL(n) (((n) * 0x10) + 0x30 + TXBSIDL_OFF)
154# define SIDL_SID_MASK 7
155# define SIDL_SID_SHIFT 5
156# define SIDL_EXIDE_SHIFT 3
157# define SIDL_EID_SHIFT 16
158# define SIDL_EID_MASK 3
159#define TXBEID8(n) (((n) * 0x10) + 0x30 + TXBEID8_OFF)
160#define TXBEID0(n) (((n) * 0x10) + 0x30 + TXBEID0_OFF)
161#define TXBDLC(n) (((n) * 0x10) + 0x30 + TXBDLC_OFF)
162# define DLC_RTR_SHIFT 6
163#define TXBCTRL_OFF 0
164#define TXBSIDH_OFF 1
165#define TXBSIDL_OFF 2
166#define TXBEID8_OFF 3
167#define TXBEID0_OFF 4
168#define TXBDLC_OFF 5
169#define TXBDAT_OFF 6
170#define RXBCTRL(n) (((n) * 0x10) + 0x60 + RXBCTRL_OFF)
171# define RXBCTRL_BUKT 0x04
172# define RXBCTRL_RXM0 0x20
173# define RXBCTRL_RXM1 0x40
174#define RXBSIDH(n) (((n) * 0x10) + 0x60 + RXBSIDH_OFF)
175# define RXBSIDH_SHIFT 3
176#define RXBSIDL(n) (((n) * 0x10) + 0x60 + RXBSIDL_OFF)
177# define RXBSIDL_IDE 0x08
178# define RXBSIDL_SRR 0x10
179# define RXBSIDL_EID 3
180# define RXBSIDL_SHIFT 5
181#define RXBEID8(n) (((n) * 0x10) + 0x60 + RXBEID8_OFF)
182#define RXBEID0(n) (((n) * 0x10) + 0x60 + RXBEID0_OFF)
183#define RXBDLC(n) (((n) * 0x10) + 0x60 + RXBDLC_OFF)
184# define RXBDLC_LEN_MASK 0x0f
185# define RXBDLC_RTR 0x40
186#define RXBCTRL_OFF 0
187#define RXBSIDH_OFF 1
188#define RXBSIDL_OFF 2
189#define RXBEID8_OFF 3
190#define RXBEID0_OFF 4
191#define RXBDLC_OFF 5
192#define RXBDAT_OFF 6
193#define RXFSID(n) ((n < 3) ? 0 : 4)
194#define RXFSIDH(n) ((n) * 4 + RXFSID(n))
195#define RXFSIDL(n) ((n) * 4 + 1 + RXFSID(n))
196#define RXFEID8(n) ((n) * 4 + 2 + RXFSID(n))
197#define RXFEID0(n) ((n) * 4 + 3 + RXFSID(n))
198#define RXMSIDH(n) ((n) * 4 + 0x20)
199#define RXMSIDL(n) ((n) * 4 + 0x21)
200#define RXMEID8(n) ((n) * 4 + 0x22)
201#define RXMEID0(n) ((n) * 4 + 0x23)
202
203#define GET_BYTE(val, byte) \
204 (((val) >> ((byte) * 8)) & 0xff)
205#define SET_BYTE(val, byte) \
206 (((val) & 0xff) << ((byte) * 8))
207
208/*
209 * Buffer size required for the largest SPI transfer (i.e., reading a
210 * frame)
211 */
212#define CAN_FRAME_MAX_DATA_LEN 8
213#define SPI_TRANSFER_BUF_LEN (6 + CAN_FRAME_MAX_DATA_LEN)
214#define CAN_FRAME_MAX_BITS 128
215
216#define TX_ECHO_SKB_MAX 1
217
218#define MCP251X_OST_DELAY_MS (5)
219
220#define DEVICE_NAME "mcp251x"
221
222static int mcp251x_enable_dma; /* Enable SPI DMA. Default: 0 (Off) */
223module_param(mcp251x_enable_dma, int, S_IRUGO);
224MODULE_PARM_DESC(mcp251x_enable_dma, "Enable SPI DMA. Default: 0 (Off)");
225
226static const struct can_bittiming_const mcp251x_bittiming_const = {
227 .name = DEVICE_NAME,
228 .tseg1_min = 3,
229 .tseg1_max = 16,
230 .tseg2_min = 2,
231 .tseg2_max = 8,
232 .sjw_max = 4,
233 .brp_min = 1,
234 .brp_max = 64,
235 .brp_inc = 1,
236};
237
238enum mcp251x_model {
239 CAN_MCP251X_MCP2510 = 0x2510,
240 CAN_MCP251X_MCP2515 = 0x2515,
241};
242
243struct mcp251x_priv {
244 struct can_priv can;
245 struct net_device *net;
246 struct spi_device *spi;
247 enum mcp251x_model model;
248
249 struct mutex mcp_lock; /* SPI device lock */
250
251 u8 *spi_tx_buf;
252 u8 *spi_rx_buf;
253 dma_addr_t spi_tx_dma;
254 dma_addr_t spi_rx_dma;
255
256 struct sk_buff *tx_skb;
257 int tx_len;
258
259 struct workqueue_struct *wq;
260 struct work_struct tx_work;
261 struct work_struct restart_work;
262
263 int force_quit;
264 int after_suspend;
265#define AFTER_SUSPEND_UP 1
266#define AFTER_SUSPEND_DOWN 2
267#define AFTER_SUSPEND_POWER 4
268#define AFTER_SUSPEND_RESTART 8
269 int restart_tx;
270 struct regulator *power;
271 struct regulator *transceiver;
272 struct clk *clk;
273};
274
275#define MCP251X_IS(_model) \
276static inline int mcp251x_is_##_model(struct spi_device *spi) \
277{ \
278 struct mcp251x_priv *priv = spi_get_drvdata(spi); \
279 return priv->model == CAN_MCP251X_MCP##_model; \
280}
281
282MCP251X_IS(2510);
283MCP251X_IS(2515);
284
285static void mcp251x_clean(struct net_device *net)
286{
287 struct mcp251x_priv *priv = netdev_priv(net);
288
289 if (priv->tx_skb || priv->tx_len)
290 net->stats.tx_errors++;
291 if (priv->tx_skb)
292 dev_kfree_skb(priv->tx_skb);
293 if (priv->tx_len)
294 can_free_echo_skb(priv->net, 0);
295 priv->tx_skb = NULL;
296 priv->tx_len = 0;
297}
298
299/*
300 * Note about handling of error return of mcp251x_spi_trans: accessing
301 * registers via SPI is not really different conceptually than using
302 * normal I/O assembler instructions, although it's much more
303 * complicated from a practical POV. So it's not advisable to always
304 * check the return value of this function. Imagine that every
305 * read{b,l}, write{b,l} and friends would be bracketed in "if ( < 0)
306 * error();", it would be a great mess (well there are some situation
307 * when exception handling C++ like could be useful after all). So we
308 * just check that transfers are OK at the beginning of our
309 * conversation with the chip and to avoid doing really nasty things
310 * (like injecting bogus packets in the network stack).
311 */
312static int mcp251x_spi_trans(struct spi_device *spi, int len)
313{
314 struct mcp251x_priv *priv = spi_get_drvdata(spi);
315 struct spi_transfer t = {
316 .tx_buf = priv->spi_tx_buf,
317 .rx_buf = priv->spi_rx_buf,
318 .len = len,
319 .cs_change = 0,
320 };
321 struct spi_message m;
322 int ret;
323
324 spi_message_init(&m);
325
326 if (mcp251x_enable_dma) {
327 t.tx_dma = priv->spi_tx_dma;
328 t.rx_dma = priv->spi_rx_dma;
329 m.is_dma_mapped = 1;
330 }
331
332 spi_message_add_tail(&t, &m);
333
334 ret = spi_sync(spi, &m);
335 if (ret)
336 dev_err(&spi->dev, "spi transfer failed: ret = %d\n", ret);
337 return ret;
338}
339
340static u8 mcp251x_read_reg(struct spi_device *spi, uint8_t reg)
341{
342 struct mcp251x_priv *priv = spi_get_drvdata(spi);
343 u8 val = 0;
344
345 priv->spi_tx_buf[0] = INSTRUCTION_READ;
346 priv->spi_tx_buf[1] = reg;
347
348 mcp251x_spi_trans(spi, 3);
349 val = priv->spi_rx_buf[2];
350
351 return val;
352}
353
354static void mcp251x_read_2regs(struct spi_device *spi, uint8_t reg,
355 uint8_t *v1, uint8_t *v2)
356{
357 struct mcp251x_priv *priv = spi_get_drvdata(spi);
358
359 priv->spi_tx_buf[0] = INSTRUCTION_READ;
360 priv->spi_tx_buf[1] = reg;
361
362 mcp251x_spi_trans(spi, 4);
363
364 *v1 = priv->spi_rx_buf[2];
365 *v2 = priv->spi_rx_buf[3];
366}
367
368static void mcp251x_write_reg(struct spi_device *spi, u8 reg, uint8_t val)
369{
370 struct mcp251x_priv *priv = spi_get_drvdata(spi);
371
372 priv->spi_tx_buf[0] = INSTRUCTION_WRITE;
373 priv->spi_tx_buf[1] = reg;
374 priv->spi_tx_buf[2] = val;
375
376 mcp251x_spi_trans(spi, 3);
377}
378
379static void mcp251x_write_bits(struct spi_device *spi, u8 reg,
380 u8 mask, uint8_t val)
381{
382 struct mcp251x_priv *priv = spi_get_drvdata(spi);
383
384 priv->spi_tx_buf[0] = INSTRUCTION_BIT_MODIFY;
385 priv->spi_tx_buf[1] = reg;
386 priv->spi_tx_buf[2] = mask;
387 priv->spi_tx_buf[3] = val;
388
389 mcp251x_spi_trans(spi, 4);
390}
391
392static void mcp251x_hw_tx_frame(struct spi_device *spi, u8 *buf,
393 int len, int tx_buf_idx)
394{
395 struct mcp251x_priv *priv = spi_get_drvdata(spi);
396
397 if (mcp251x_is_2510(spi)) {
398 int i;
399
400 for (i = 1; i < TXBDAT_OFF + len; i++)
401 mcp251x_write_reg(spi, TXBCTRL(tx_buf_idx) + i,
402 buf[i]);
403 } else {
404 memcpy(priv->spi_tx_buf, buf, TXBDAT_OFF + len);
405 mcp251x_spi_trans(spi, TXBDAT_OFF + len);
406 }
407}
408
409static void mcp251x_hw_tx(struct spi_device *spi, struct can_frame *frame,
410 int tx_buf_idx)
411{
412 struct mcp251x_priv *priv = spi_get_drvdata(spi);
413 u32 sid, eid, exide, rtr;
414 u8 buf[SPI_TRANSFER_BUF_LEN];
415
416 exide = (frame->can_id & CAN_EFF_FLAG) ? 1 : 0; /* Extended ID Enable */
417 if (exide)
418 sid = (frame->can_id & CAN_EFF_MASK) >> 18;
419 else
420 sid = frame->can_id & CAN_SFF_MASK; /* Standard ID */
421 eid = frame->can_id & CAN_EFF_MASK; /* Extended ID */
422 rtr = (frame->can_id & CAN_RTR_FLAG) ? 1 : 0; /* Remote transmission */
423
424 buf[TXBCTRL_OFF] = INSTRUCTION_LOAD_TXB(tx_buf_idx);
425 buf[TXBSIDH_OFF] = sid >> SIDH_SHIFT;
426 buf[TXBSIDL_OFF] = ((sid & SIDL_SID_MASK) << SIDL_SID_SHIFT) |
427 (exide << SIDL_EXIDE_SHIFT) |
428 ((eid >> SIDL_EID_SHIFT) & SIDL_EID_MASK);
429 buf[TXBEID8_OFF] = GET_BYTE(eid, 1);
430 buf[TXBEID0_OFF] = GET_BYTE(eid, 0);
431 buf[TXBDLC_OFF] = (rtr << DLC_RTR_SHIFT) | frame->can_dlc;
432 memcpy(buf + TXBDAT_OFF, frame->data, frame->can_dlc);
433 mcp251x_hw_tx_frame(spi, buf, frame->can_dlc, tx_buf_idx);
434
435 /* use INSTRUCTION_RTS, to avoid "repeated frame problem" */
436 priv->spi_tx_buf[0] = INSTRUCTION_RTS(1 << tx_buf_idx);
437 mcp251x_spi_trans(priv->spi, 1);
438}
439
440static void mcp251x_hw_rx_frame(struct spi_device *spi, u8 *buf,
441 int buf_idx)
442{
443 struct mcp251x_priv *priv = spi_get_drvdata(spi);
444
445 if (mcp251x_is_2510(spi)) {
446 int i, len;
447
448 for (i = 1; i < RXBDAT_OFF; i++)
449 buf[i] = mcp251x_read_reg(spi, RXBCTRL(buf_idx) + i);
450
451 len = get_can_dlc(buf[RXBDLC_OFF] & RXBDLC_LEN_MASK);
452 for (; i < (RXBDAT_OFF + len); i++)
453 buf[i] = mcp251x_read_reg(spi, RXBCTRL(buf_idx) + i);
454 } else {
455 priv->spi_tx_buf[RXBCTRL_OFF] = INSTRUCTION_READ_RXB(buf_idx);
456 mcp251x_spi_trans(spi, SPI_TRANSFER_BUF_LEN);
457 memcpy(buf, priv->spi_rx_buf, SPI_TRANSFER_BUF_LEN);
458 }
459}
460
461static void mcp251x_hw_rx(struct spi_device *spi, int buf_idx)
462{
463 struct mcp251x_priv *priv = spi_get_drvdata(spi);
464 struct sk_buff *skb;
465 struct can_frame *frame;
466 u8 buf[SPI_TRANSFER_BUF_LEN];
467
468 skb = alloc_can_skb(priv->net, &frame);
469 if (!skb) {
470 dev_err(&spi->dev, "cannot allocate RX skb\n");
471 priv->net->stats.rx_dropped++;
472 return;
473 }
474
475 mcp251x_hw_rx_frame(spi, buf, buf_idx);
476 if (buf[RXBSIDL_OFF] & RXBSIDL_IDE) {
477 /* Extended ID format */
478 frame->can_id = CAN_EFF_FLAG;
479 frame->can_id |=
480 /* Extended ID part */
481 SET_BYTE(buf[RXBSIDL_OFF] & RXBSIDL_EID, 2) |
482 SET_BYTE(buf[RXBEID8_OFF], 1) |
483 SET_BYTE(buf[RXBEID0_OFF], 0) |
484 /* Standard ID part */
485 (((buf[RXBSIDH_OFF] << RXBSIDH_SHIFT) |
486 (buf[RXBSIDL_OFF] >> RXBSIDL_SHIFT)) << 18);
487 /* Remote transmission request */
488 if (buf[RXBDLC_OFF] & RXBDLC_RTR)
489 frame->can_id |= CAN_RTR_FLAG;
490 } else {
491 /* Standard ID format */
492 frame->can_id =
493 (buf[RXBSIDH_OFF] << RXBSIDH_SHIFT) |
494 (buf[RXBSIDL_OFF] >> RXBSIDL_SHIFT);
495 if (buf[RXBSIDL_OFF] & RXBSIDL_SRR)
496 frame->can_id |= CAN_RTR_FLAG;
497 }
498 /* Data length */
499 frame->can_dlc = get_can_dlc(buf[RXBDLC_OFF] & RXBDLC_LEN_MASK);
500 memcpy(frame->data, buf + RXBDAT_OFF, frame->can_dlc);
501
502 priv->net->stats.rx_packets++;
503 priv->net->stats.rx_bytes += frame->can_dlc;
504
505 can_led_event(priv->net, CAN_LED_EVENT_RX);
506
507 netif_rx_ni(skb);
508}
509
510static void mcp251x_hw_sleep(struct spi_device *spi)
511{
512 mcp251x_write_reg(spi, CANCTRL, CANCTRL_REQOP_SLEEP);
513}
514
515static netdev_tx_t mcp251x_hard_start_xmit(struct sk_buff *skb,
516 struct net_device *net)
517{
518 struct mcp251x_priv *priv = netdev_priv(net);
519 struct spi_device *spi = priv->spi;
520
521 if (priv->tx_skb || priv->tx_len) {
522 dev_warn(&spi->dev, "hard_xmit called while tx busy\n");
523 return NETDEV_TX_BUSY;
524 }
525
526 if (can_dropped_invalid_skb(net, skb))
527 return NETDEV_TX_OK;
528
529 netif_stop_queue(net);
530 priv->tx_skb = skb;
531 queue_work(priv->wq, &priv->tx_work);
532
533 return NETDEV_TX_OK;
534}
535
536static int mcp251x_do_set_mode(struct net_device *net, enum can_mode mode)
537{
538 struct mcp251x_priv *priv = netdev_priv(net);
539
540 switch (mode) {
541 case CAN_MODE_START:
542 mcp251x_clean(net);
543 /* We have to delay work since SPI I/O may sleep */
544 priv->can.state = CAN_STATE_ERROR_ACTIVE;
545 priv->restart_tx = 1;
546 if (priv->can.restart_ms == 0)
547 priv->after_suspend = AFTER_SUSPEND_RESTART;
548 queue_work(priv->wq, &priv->restart_work);
549 break;
550 default:
551 return -EOPNOTSUPP;
552 }
553
554 return 0;
555}
556
557static int mcp251x_set_normal_mode(struct spi_device *spi)
558{
559 struct mcp251x_priv *priv = spi_get_drvdata(spi);
560 unsigned long timeout;
561
562 /* Enable interrupts */
563 mcp251x_write_reg(spi, CANINTE,
564 CANINTE_ERRIE | CANINTE_TX2IE | CANINTE_TX1IE |
565 CANINTE_TX0IE | CANINTE_RX1IE | CANINTE_RX0IE);
566
567 if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK) {
568 /* Put device into loopback mode */
569 mcp251x_write_reg(spi, CANCTRL, CANCTRL_REQOP_LOOPBACK);
570 } else if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY) {
571 /* Put device into listen-only mode */
572 mcp251x_write_reg(spi, CANCTRL, CANCTRL_REQOP_LISTEN_ONLY);
573 } else {
574 /* Put device into normal mode */
575 mcp251x_write_reg(spi, CANCTRL, CANCTRL_REQOP_NORMAL);
576
577 /* Wait for the device to enter normal mode */
578 timeout = jiffies + HZ;
579 while (mcp251x_read_reg(spi, CANSTAT) & CANCTRL_REQOP_MASK) {
580 schedule();
581 if (time_after(jiffies, timeout)) {
582 dev_err(&spi->dev, "MCP251x didn't"
583 " enter in normal mode\n");
584 return -EBUSY;
585 }
586 }
587 }
588 priv->can.state = CAN_STATE_ERROR_ACTIVE;
589 return 0;
590}
591
592static int mcp251x_do_set_bittiming(struct net_device *net)
593{
594 struct mcp251x_priv *priv = netdev_priv(net);
595 struct can_bittiming *bt = &priv->can.bittiming;
596 struct spi_device *spi = priv->spi;
597
598 mcp251x_write_reg(spi, CNF1, ((bt->sjw - 1) << CNF1_SJW_SHIFT) |
599 (bt->brp - 1));
600 mcp251x_write_reg(spi, CNF2, CNF2_BTLMODE |
601 (priv->can.ctrlmode & CAN_CTRLMODE_3_SAMPLES ?
602 CNF2_SAM : 0) |
603 ((bt->phase_seg1 - 1) << CNF2_PS1_SHIFT) |
604 (bt->prop_seg - 1));
605 mcp251x_write_bits(spi, CNF3, CNF3_PHSEG2_MASK,
606 (bt->phase_seg2 - 1));
607 dev_dbg(&spi->dev, "CNF: 0x%02x 0x%02x 0x%02x\n",
608 mcp251x_read_reg(spi, CNF1),
609 mcp251x_read_reg(spi, CNF2),
610 mcp251x_read_reg(spi, CNF3));
611
612 return 0;
613}
614
615static int mcp251x_setup(struct net_device *net, struct mcp251x_priv *priv,
616 struct spi_device *spi)
617{
618 mcp251x_do_set_bittiming(net);
619
620 mcp251x_write_reg(spi, RXBCTRL(0),
621 RXBCTRL_BUKT | RXBCTRL_RXM0 | RXBCTRL_RXM1);
622 mcp251x_write_reg(spi, RXBCTRL(1),
623 RXBCTRL_RXM0 | RXBCTRL_RXM1);
624 return 0;
625}
626
627static int mcp251x_hw_reset(struct spi_device *spi)
628{
629 struct mcp251x_priv *priv = spi_get_drvdata(spi);
630 u8 reg;
631 int ret;
632
633 /* Wait for oscillator startup timer after power up */
634 mdelay(MCP251X_OST_DELAY_MS);
635
636 priv->spi_tx_buf[0] = INSTRUCTION_RESET;
637 ret = mcp251x_spi_trans(spi, 1);
638 if (ret)
639 return ret;
640
641 /* Wait for oscillator startup timer after reset */
642 mdelay(MCP251X_OST_DELAY_MS);
643
644 reg = mcp251x_read_reg(spi, CANSTAT);
645 if ((reg & CANCTRL_REQOP_MASK) != CANCTRL_REQOP_CONF)
646 return -ENODEV;
647
648 return 0;
649}
650
651static int mcp251x_hw_probe(struct spi_device *spi)
652{
653 u8 ctrl;
654 int ret;
655
656 ret = mcp251x_hw_reset(spi);
657 if (ret)
658 return ret;
659
660 ctrl = mcp251x_read_reg(spi, CANCTRL);
661
662 dev_dbg(&spi->dev, "CANCTRL 0x%02x\n", ctrl);
663
664 /* Check for power up default value */
665 if ((ctrl & 0x17) != 0x07)
666 return -ENODEV;
667
668 return 0;
669}
670
671static int mcp251x_power_enable(struct regulator *reg, int enable)
672{
673 if (IS_ERR_OR_NULL(reg))
674 return 0;
675
676 if (enable)
677 return regulator_enable(reg);
678 else
679 return regulator_disable(reg);
680}
681
682static void mcp251x_open_clean(struct net_device *net)
683{
684 struct mcp251x_priv *priv = netdev_priv(net);
685 struct spi_device *spi = priv->spi;
686
687 free_irq(spi->irq, priv);
688 mcp251x_hw_sleep(spi);
689 mcp251x_power_enable(priv->transceiver, 0);
690 close_candev(net);
691}
692
693static int mcp251x_stop(struct net_device *net)
694{
695 struct mcp251x_priv *priv = netdev_priv(net);
696 struct spi_device *spi = priv->spi;
697
698 close_candev(net);
699
700 priv->force_quit = 1;
701 free_irq(spi->irq, priv);
702 destroy_workqueue(priv->wq);
703 priv->wq = NULL;
704
705 mutex_lock(&priv->mcp_lock);
706
707 /* Disable and clear pending interrupts */
708 mcp251x_write_reg(spi, CANINTE, 0x00);
709 mcp251x_write_reg(spi, CANINTF, 0x00);
710
711 mcp251x_write_reg(spi, TXBCTRL(0), 0);
712 mcp251x_clean(net);
713
714 mcp251x_hw_sleep(spi);
715
716 mcp251x_power_enable(priv->transceiver, 0);
717
718 priv->can.state = CAN_STATE_STOPPED;
719
720 mutex_unlock(&priv->mcp_lock);
721
722 can_led_event(net, CAN_LED_EVENT_STOP);
723
724 return 0;
725}
726
727static void mcp251x_error_skb(struct net_device *net, int can_id, int data1)
728{
729 struct sk_buff *skb;
730 struct can_frame *frame;
731
732 skb = alloc_can_err_skb(net, &frame);
733 if (skb) {
734 frame->can_id |= can_id;
735 frame->data[1] = data1;
736 netif_rx_ni(skb);
737 } else {
738 netdev_err(net, "cannot allocate error skb\n");
739 }
740}
741
742static void mcp251x_tx_work_handler(struct work_struct *ws)
743{
744 struct mcp251x_priv *priv = container_of(ws, struct mcp251x_priv,
745 tx_work);
746 struct spi_device *spi = priv->spi;
747 struct net_device *net = priv->net;
748 struct can_frame *frame;
749
750 mutex_lock(&priv->mcp_lock);
751 if (priv->tx_skb) {
752 if (priv->can.state == CAN_STATE_BUS_OFF) {
753 mcp251x_clean(net);
754 } else {
755 frame = (struct can_frame *)priv->tx_skb->data;
756
757 if (frame->can_dlc > CAN_FRAME_MAX_DATA_LEN)
758 frame->can_dlc = CAN_FRAME_MAX_DATA_LEN;
759 mcp251x_hw_tx(spi, frame, 0);
760 priv->tx_len = 1 + frame->can_dlc;
761 can_put_echo_skb(priv->tx_skb, net, 0);
762 priv->tx_skb = NULL;
763 }
764 }
765 mutex_unlock(&priv->mcp_lock);
766}
767
768static void mcp251x_restart_work_handler(struct work_struct *ws)
769{
770 struct mcp251x_priv *priv = container_of(ws, struct mcp251x_priv,
771 restart_work);
772 struct spi_device *spi = priv->spi;
773 struct net_device *net = priv->net;
774
775 mutex_lock(&priv->mcp_lock);
776 if (priv->after_suspend) {
777 mcp251x_hw_reset(spi);
778 mcp251x_setup(net, priv, spi);
779 if (priv->after_suspend & AFTER_SUSPEND_RESTART) {
780 mcp251x_set_normal_mode(spi);
781 } else if (priv->after_suspend & AFTER_SUSPEND_UP) {
782 netif_device_attach(net);
783 mcp251x_clean(net);
784 mcp251x_set_normal_mode(spi);
785 netif_wake_queue(net);
786 } else {
787 mcp251x_hw_sleep(spi);
788 }
789 priv->after_suspend = 0;
790 priv->force_quit = 0;
791 }
792
793 if (priv->restart_tx) {
794 priv->restart_tx = 0;
795 mcp251x_write_reg(spi, TXBCTRL(0), 0);
796 mcp251x_clean(net);
797 netif_wake_queue(net);
798 mcp251x_error_skb(net, CAN_ERR_RESTARTED, 0);
799 }
800 mutex_unlock(&priv->mcp_lock);
801}
802
803static irqreturn_t mcp251x_can_ist(int irq, void *dev_id)
804{
805 struct mcp251x_priv *priv = dev_id;
806 struct spi_device *spi = priv->spi;
807 struct net_device *net = priv->net;
808
809 mutex_lock(&priv->mcp_lock);
810 while (!priv->force_quit) {
811 enum can_state new_state;
812 u8 intf, eflag;
813 u8 clear_intf = 0;
814 int can_id = 0, data1 = 0;
815
816 mcp251x_read_2regs(spi, CANINTF, &intf, &eflag);
817
818 /* mask out flags we don't care about */
819 intf &= CANINTF_RX | CANINTF_TX | CANINTF_ERR;
820
821 /* receive buffer 0 */
822 if (intf & CANINTF_RX0IF) {
823 mcp251x_hw_rx(spi, 0);
824 /*
825 * Free one buffer ASAP
826 * (The MCP2515 does this automatically.)
827 */
828 if (mcp251x_is_2510(spi))
829 mcp251x_write_bits(spi, CANINTF, CANINTF_RX0IF, 0x00);
830 }
831
832 /* receive buffer 1 */
833 if (intf & CANINTF_RX1IF) {
834 mcp251x_hw_rx(spi, 1);
835 /* the MCP2515 does this automatically */
836 if (mcp251x_is_2510(spi))
837 clear_intf |= CANINTF_RX1IF;
838 }
839
840 /* any error or tx interrupt we need to clear? */
841 if (intf & (CANINTF_ERR | CANINTF_TX))
842 clear_intf |= intf & (CANINTF_ERR | CANINTF_TX);
843 if (clear_intf)
844 mcp251x_write_bits(spi, CANINTF, clear_intf, 0x00);
845
846 if (eflag & (EFLG_RX0OVR | EFLG_RX1OVR))
847 mcp251x_write_bits(spi, EFLG, eflag, 0x00);
848
849 /* Update can state */
850 if (eflag & EFLG_TXBO) {
851 new_state = CAN_STATE_BUS_OFF;
852 can_id |= CAN_ERR_BUSOFF;
853 } else if (eflag & EFLG_TXEP) {
854 new_state = CAN_STATE_ERROR_PASSIVE;
855 can_id |= CAN_ERR_CRTL;
856 data1 |= CAN_ERR_CRTL_TX_PASSIVE;
857 } else if (eflag & EFLG_RXEP) {
858 new_state = CAN_STATE_ERROR_PASSIVE;
859 can_id |= CAN_ERR_CRTL;
860 data1 |= CAN_ERR_CRTL_RX_PASSIVE;
861 } else if (eflag & EFLG_TXWAR) {
862 new_state = CAN_STATE_ERROR_WARNING;
863 can_id |= CAN_ERR_CRTL;
864 data1 |= CAN_ERR_CRTL_TX_WARNING;
865 } else if (eflag & EFLG_RXWAR) {
866 new_state = CAN_STATE_ERROR_WARNING;
867 can_id |= CAN_ERR_CRTL;
868 data1 |= CAN_ERR_CRTL_RX_WARNING;
869 } else {
870 new_state = CAN_STATE_ERROR_ACTIVE;
871 }
872
873 /* Update can state statistics */
874 switch (priv->can.state) {
875 case CAN_STATE_ERROR_ACTIVE:
876 if (new_state >= CAN_STATE_ERROR_WARNING &&
877 new_state <= CAN_STATE_BUS_OFF)
878 priv->can.can_stats.error_warning++;
879 case CAN_STATE_ERROR_WARNING: /* fallthrough */
880 if (new_state >= CAN_STATE_ERROR_PASSIVE &&
881 new_state <= CAN_STATE_BUS_OFF)
882 priv->can.can_stats.error_passive++;
883 break;
884 default:
885 break;
886 }
887 priv->can.state = new_state;
888
889 if (intf & CANINTF_ERRIF) {
890 /* Handle overflow counters */
891 if (eflag & (EFLG_RX0OVR | EFLG_RX1OVR)) {
892 if (eflag & EFLG_RX0OVR) {
893 net->stats.rx_over_errors++;
894 net->stats.rx_errors++;
895 }
896 if (eflag & EFLG_RX1OVR) {
897 net->stats.rx_over_errors++;
898 net->stats.rx_errors++;
899 }
900 can_id |= CAN_ERR_CRTL;
901 data1 |= CAN_ERR_CRTL_RX_OVERFLOW;
902 }
903 mcp251x_error_skb(net, can_id, data1);
904 }
905
906 if (priv->can.state == CAN_STATE_BUS_OFF) {
907 if (priv->can.restart_ms == 0) {
908 priv->force_quit = 1;
909 priv->can.can_stats.bus_off++;
910 can_bus_off(net);
911 mcp251x_hw_sleep(spi);
912 break;
913 }
914 }
915
916 if (intf == 0)
917 break;
918
919 if (intf & CANINTF_TX) {
920 net->stats.tx_packets++;
921 net->stats.tx_bytes += priv->tx_len - 1;
922 can_led_event(net, CAN_LED_EVENT_TX);
923 if (priv->tx_len) {
924 can_get_echo_skb(net, 0);
925 priv->tx_len = 0;
926 }
927 netif_wake_queue(net);
928 }
929
930 }
931 mutex_unlock(&priv->mcp_lock);
932 return IRQ_HANDLED;
933}
934
935static int mcp251x_open(struct net_device *net)
936{
937 struct mcp251x_priv *priv = netdev_priv(net);
938 struct spi_device *spi = priv->spi;
939 unsigned long flags = IRQF_ONESHOT | IRQF_TRIGGER_FALLING;
940 int ret;
941
942 ret = open_candev(net);
943 if (ret) {
944 dev_err(&spi->dev, "unable to set initial baudrate!\n");
945 return ret;
946 }
947
948 mutex_lock(&priv->mcp_lock);
949 mcp251x_power_enable(priv->transceiver, 1);
950
951 priv->force_quit = 0;
952 priv->tx_skb = NULL;
953 priv->tx_len = 0;
954
955 ret = request_threaded_irq(spi->irq, NULL, mcp251x_can_ist,
956 flags | IRQF_ONESHOT, DEVICE_NAME, priv);
957 if (ret) {
958 dev_err(&spi->dev, "failed to acquire irq %d\n", spi->irq);
959 mcp251x_power_enable(priv->transceiver, 0);
960 close_candev(net);
961 goto open_unlock;
962 }
963
964 priv->wq = create_freezable_workqueue("mcp251x_wq");
965 INIT_WORK(&priv->tx_work, mcp251x_tx_work_handler);
966 INIT_WORK(&priv->restart_work, mcp251x_restart_work_handler);
967
968 ret = mcp251x_hw_reset(spi);
969 if (ret) {
970 mcp251x_open_clean(net);
971 goto open_unlock;
972 }
973 ret = mcp251x_setup(net, priv, spi);
974 if (ret) {
975 mcp251x_open_clean(net);
976 goto open_unlock;
977 }
978 ret = mcp251x_set_normal_mode(spi);
979 if (ret) {
980 mcp251x_open_clean(net);
981 goto open_unlock;
982 }
983
984 can_led_event(net, CAN_LED_EVENT_OPEN);
985
986 netif_wake_queue(net);
987
988open_unlock:
989 mutex_unlock(&priv->mcp_lock);
990 return ret;
991}
992
993static const struct net_device_ops mcp251x_netdev_ops = {
994 .ndo_open = mcp251x_open,
995 .ndo_stop = mcp251x_stop,
996 .ndo_start_xmit = mcp251x_hard_start_xmit,
997 .ndo_change_mtu = can_change_mtu,
998};
999
1000static const struct of_device_id mcp251x_of_match[] = {
1001 {
1002 .compatible = "microchip,mcp2510",
1003 .data = (void *)CAN_MCP251X_MCP2510,
1004 },
1005 {
1006 .compatible = "microchip,mcp2515",
1007 .data = (void *)CAN_MCP251X_MCP2515,
1008 },
1009 { }
1010};
1011MODULE_DEVICE_TABLE(of, mcp251x_of_match);
1012
1013static const struct spi_device_id mcp251x_id_table[] = {
1014 {
1015 .name = "mcp2510",
1016 .driver_data = (kernel_ulong_t)CAN_MCP251X_MCP2510,
1017 },
1018 {
1019 .name = "mcp2515",
1020 .driver_data = (kernel_ulong_t)CAN_MCP251X_MCP2515,
1021 },
1022 { }
1023};
1024MODULE_DEVICE_TABLE(spi, mcp251x_id_table);
1025
1026static int mcp251x_can_probe(struct spi_device *spi)
1027{
1028 const struct of_device_id *of_id = of_match_device(mcp251x_of_match,
1029 &spi->dev);
1030 struct mcp251x_platform_data *pdata = dev_get_platdata(&spi->dev);
1031 struct net_device *net;
1032 struct mcp251x_priv *priv;
1033 struct clk *clk;
1034 int freq, ret;
1035
1036 clk = devm_clk_get(&spi->dev, NULL);
1037 if (IS_ERR(clk)) {
1038 if (pdata)
1039 freq = pdata->oscillator_frequency;
1040 else
1041 return PTR_ERR(clk);
1042 } else {
1043 freq = clk_get_rate(clk);
1044 }
1045
1046 /* Sanity check */
1047 if (freq < 1000000 || freq > 25000000)
1048 return -ERANGE;
1049
1050 /* Allocate can/net device */
1051 net = alloc_candev(sizeof(struct mcp251x_priv), TX_ECHO_SKB_MAX);
1052 if (!net)
1053 return -ENOMEM;
1054
1055 if (!IS_ERR(clk)) {
1056 ret = clk_prepare_enable(clk);
1057 if (ret)
1058 goto out_free;
1059 }
1060
1061 net->netdev_ops = &mcp251x_netdev_ops;
1062 net->flags |= IFF_ECHO;
1063
1064 priv = netdev_priv(net);
1065 priv->can.bittiming_const = &mcp251x_bittiming_const;
1066 priv->can.do_set_mode = mcp251x_do_set_mode;
1067 priv->can.clock.freq = freq / 2;
1068 priv->can.ctrlmode_supported = CAN_CTRLMODE_3_SAMPLES |
1069 CAN_CTRLMODE_LOOPBACK | CAN_CTRLMODE_LISTENONLY;
1070 if (of_id)
1071 priv->model = (enum mcp251x_model)of_id->data;
1072 else
1073 priv->model = spi_get_device_id(spi)->driver_data;
1074 priv->net = net;
1075 priv->clk = clk;
1076
1077 spi_set_drvdata(spi, priv);
1078
1079 /* Configure the SPI bus */
1080 spi->bits_per_word = 8;
1081 if (mcp251x_is_2510(spi))
1082 spi->max_speed_hz = spi->max_speed_hz ? : 5 * 1000 * 1000;
1083 else
1084 spi->max_speed_hz = spi->max_speed_hz ? : 10 * 1000 * 1000;
1085 ret = spi_setup(spi);
1086 if (ret)
1087 goto out_clk;
1088
1089 priv->power = devm_regulator_get_optional(&spi->dev, "vdd");
1090 priv->transceiver = devm_regulator_get_optional(&spi->dev, "xceiver");
1091 if ((PTR_ERR(priv->power) == -EPROBE_DEFER) ||
1092 (PTR_ERR(priv->transceiver) == -EPROBE_DEFER)) {
1093 ret = -EPROBE_DEFER;
1094 goto out_clk;
1095 }
1096
1097 ret = mcp251x_power_enable(priv->power, 1);
1098 if (ret)
1099 goto out_clk;
1100
1101 priv->spi = spi;
1102 mutex_init(&priv->mcp_lock);
1103
1104 /* If requested, allocate DMA buffers */
1105 if (mcp251x_enable_dma) {
1106 spi->dev.coherent_dma_mask = ~0;
1107
1108 /*
1109 * Minimum coherent DMA allocation is PAGE_SIZE, so allocate
1110 * that much and share it between Tx and Rx DMA buffers.
1111 */
1112 priv->spi_tx_buf = dmam_alloc_coherent(&spi->dev,
1113 PAGE_SIZE,
1114 &priv->spi_tx_dma,
1115 GFP_DMA);
1116
1117 if (priv->spi_tx_buf) {
1118 priv->spi_rx_buf = (priv->spi_tx_buf + (PAGE_SIZE / 2));
1119 priv->spi_rx_dma = (dma_addr_t)(priv->spi_tx_dma +
1120 (PAGE_SIZE / 2));
1121 } else {
1122 /* Fall back to non-DMA */
1123 mcp251x_enable_dma = 0;
1124 }
1125 }
1126
1127 /* Allocate non-DMA buffers */
1128 if (!mcp251x_enable_dma) {
1129 priv->spi_tx_buf = devm_kzalloc(&spi->dev, SPI_TRANSFER_BUF_LEN,
1130 GFP_KERNEL);
1131 if (!priv->spi_tx_buf) {
1132 ret = -ENOMEM;
1133 goto error_probe;
1134 }
1135 priv->spi_rx_buf = devm_kzalloc(&spi->dev, SPI_TRANSFER_BUF_LEN,
1136 GFP_KERNEL);
1137 if (!priv->spi_rx_buf) {
1138 ret = -ENOMEM;
1139 goto error_probe;
1140 }
1141 }
1142
1143 SET_NETDEV_DEV(net, &spi->dev);
1144
1145 /* Here is OK to not lock the MCP, no one knows about it yet */
1146 ret = mcp251x_hw_probe(spi);
1147 if (ret)
1148 goto error_probe;
1149
1150 mcp251x_hw_sleep(spi);
1151
1152 ret = register_candev(net);
1153 if (ret)
1154 goto error_probe;
1155
1156 devm_can_led_init(net);
1157
1158 return 0;
1159
1160error_probe:
1161 mcp251x_power_enable(priv->power, 0);
1162
1163out_clk:
1164 if (!IS_ERR(clk))
1165 clk_disable_unprepare(clk);
1166
1167out_free:
1168 free_candev(net);
1169
1170 return ret;
1171}
1172
1173static int mcp251x_can_remove(struct spi_device *spi)
1174{
1175 struct mcp251x_priv *priv = spi_get_drvdata(spi);
1176 struct net_device *net = priv->net;
1177
1178 unregister_candev(net);
1179
1180 mcp251x_power_enable(priv->power, 0);
1181
1182 if (!IS_ERR(priv->clk))
1183 clk_disable_unprepare(priv->clk);
1184
1185 free_candev(net);
1186
1187 return 0;
1188}
1189
1190static int __maybe_unused mcp251x_can_suspend(struct device *dev)
1191{
1192 struct spi_device *spi = to_spi_device(dev);
1193 struct mcp251x_priv *priv = spi_get_drvdata(spi);
1194 struct net_device *net = priv->net;
1195
1196 priv->force_quit = 1;
1197 disable_irq(spi->irq);
1198 /*
1199 * Note: at this point neither IST nor workqueues are running.
1200 * open/stop cannot be called anyway so locking is not needed
1201 */
1202 if (netif_running(net)) {
1203 netif_device_detach(net);
1204
1205 mcp251x_hw_sleep(spi);
1206 mcp251x_power_enable(priv->transceiver, 0);
1207 priv->after_suspend = AFTER_SUSPEND_UP;
1208 } else {
1209 priv->after_suspend = AFTER_SUSPEND_DOWN;
1210 }
1211
1212 if (!IS_ERR_OR_NULL(priv->power)) {
1213 regulator_disable(priv->power);
1214 priv->after_suspend |= AFTER_SUSPEND_POWER;
1215 }
1216
1217 return 0;
1218}
1219
1220static int __maybe_unused mcp251x_can_resume(struct device *dev)
1221{
1222 struct spi_device *spi = to_spi_device(dev);
1223 struct mcp251x_priv *priv = spi_get_drvdata(spi);
1224
1225 if (priv->after_suspend & AFTER_SUSPEND_POWER)
1226 mcp251x_power_enable(priv->power, 1);
1227
1228 if (priv->after_suspend & AFTER_SUSPEND_UP) {
1229 mcp251x_power_enable(priv->transceiver, 1);
1230 queue_work(priv->wq, &priv->restart_work);
1231 } else {
1232 priv->after_suspend = 0;
1233 }
1234
1235 priv->force_quit = 0;
1236 enable_irq(spi->irq);
1237 return 0;
1238}
1239
1240static SIMPLE_DEV_PM_OPS(mcp251x_can_pm_ops, mcp251x_can_suspend,
1241 mcp251x_can_resume);
1242
1243static struct spi_driver mcp251x_can_driver = {
1244 .driver = {
1245 .name = DEVICE_NAME,
1246 .of_match_table = mcp251x_of_match,
1247 .pm = &mcp251x_can_pm_ops,
1248 },
1249 .id_table = mcp251x_id_table,
1250 .probe = mcp251x_can_probe,
1251 .remove = mcp251x_can_remove,
1252};
1253module_spi_driver(mcp251x_can_driver);
1254
1255MODULE_AUTHOR("Chris Elston <celston@katalix.com>, "
1256 "Christian Pellegrin <chripell@evolware.org>");
1257MODULE_DESCRIPTION("Microchip 251x CAN driver");
1258MODULE_LICENSE("GPL v2");